Commit | Line | Data |
---|---|---|
6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
b7d491e7 | 27 | #include <linux/stringify.h> |
6aa8b732 | 28 | |
3eeb3288 | 29 | #include "x86.h" |
38ba30ba | 30 | #include "tss.h" |
e99f0507 | 31 | |
a9945549 AK |
32 | /* |
33 | * Operand types | |
34 | */ | |
b1ea50b2 AK |
35 | #define OpNone 0ull |
36 | #define OpImplicit 1ull /* No generic decode */ | |
37 | #define OpReg 2ull /* Register */ | |
38 | #define OpMem 3ull /* Memory */ | |
39 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
40 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
41 | #define OpMem64 6ull /* Memory, 64-bit */ | |
42 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
43 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
44 | #define OpCL 9ull /* CL register (for shifts) */ |
45 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
46 | #define OpOne 11ull /* Implied 1 */ | |
5e2c6883 | 47 | #define OpImm 12ull /* Sign extended up to 32-bit immediate */ |
0fe59128 AK |
48 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
49 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
50 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
51 | #define OpSI 16ull /* SI/ESI/RSI */ | |
52 | #define OpImmFAddr 17ull /* Immediate far address */ | |
53 | #define OpMemFAddr 18ull /* Far address in memory */ | |
54 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
c191a7a0 AK |
55 | #define OpES 20ull /* ES */ |
56 | #define OpCS 21ull /* CS */ | |
57 | #define OpSS 22ull /* SS */ | |
58 | #define OpDS 23ull /* DS */ | |
59 | #define OpFS 24ull /* FS */ | |
60 | #define OpGS 25ull /* GS */ | |
28867cee | 61 | #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
5e2c6883 | 62 | #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ |
0fe59128 AK |
63 | |
64 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 65 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 66 | |
6aa8b732 AK |
67 | /* |
68 | * Opcode effective-address decode tables. | |
69 | * Note that we only emulate instructions that have at least one memory | |
70 | * operand (excluding implicit stack references). We assume that stack | |
71 | * references and instruction fetches will never occur in special memory | |
72 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
73 | * not be handled. | |
74 | */ | |
75 | ||
76 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 77 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 78 | /* Destination operand type. */ |
a9945549 AK |
79 | #define DstShift 1 |
80 | #define ImplicitOps (OpImplicit << DstShift) | |
81 | #define DstReg (OpReg << DstShift) | |
82 | #define DstMem (OpMem << DstShift) | |
83 | #define DstAcc (OpAcc << DstShift) | |
84 | #define DstDI (OpDI << DstShift) | |
85 | #define DstMem64 (OpMem64 << DstShift) | |
86 | #define DstImmUByte (OpImmUByte << DstShift) | |
87 | #define DstDX (OpDX << DstShift) | |
88 | #define DstMask (OpMask << DstShift) | |
6aa8b732 | 89 | /* Source operand type. */ |
0fe59128 AK |
90 | #define SrcShift 6 |
91 | #define SrcNone (OpNone << SrcShift) | |
92 | #define SrcReg (OpReg << SrcShift) | |
93 | #define SrcMem (OpMem << SrcShift) | |
94 | #define SrcMem16 (OpMem16 << SrcShift) | |
95 | #define SrcMem32 (OpMem32 << SrcShift) | |
96 | #define SrcImm (OpImm << SrcShift) | |
97 | #define SrcImmByte (OpImmByte << SrcShift) | |
98 | #define SrcOne (OpOne << SrcShift) | |
99 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
100 | #define SrcImmU (OpImmU << SrcShift) | |
101 | #define SrcSI (OpSI << SrcShift) | |
102 | #define SrcImmFAddr (OpImmFAddr << SrcShift) | |
103 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
104 | #define SrcAcc (OpAcc << SrcShift) | |
105 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
5e2c6883 | 106 | #define SrcImm64 (OpImm64 << SrcShift) |
0fe59128 | 107 | #define SrcDX (OpDX << SrcShift) |
28867cee | 108 | #define SrcMem8 (OpMem8 << SrcShift) |
0fe59128 | 109 | #define SrcMask (OpMask << SrcShift) |
221192bd MT |
110 | #define BitOp (1<<11) |
111 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
112 | #define String (1<<13) /* String instruction (rep capable) */ | |
113 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
114 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
115 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
116 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
117 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
118 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
045a282c | 119 | #define Escape (5<<15) /* Escape to coprocessor instruction */ |
221192bd | 120 | #define Sse (1<<18) /* SSE Vector instruction */ |
20c29ff2 AK |
121 | /* Generic ModRM decode. */ |
122 | #define ModRM (1<<19) | |
123 | /* Destination is only written; never read. */ | |
124 | #define Mov (1<<20) | |
d8769fed | 125 | /* Misc flags */ |
8ea7d6ae | 126 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 127 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 128 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 129 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 130 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 131 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 132 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 133 | #define No64 (1<<28) |
d5ae7ce8 | 134 | #define PageTable (1 << 29) /* instruction used to write page table */ |
0dc8d10f | 135 | /* Source 2 operand type */ |
d5ae7ce8 | 136 | #define Src2Shift (30) |
4dd6a57d AK |
137 | #define Src2None (OpNone << Src2Shift) |
138 | #define Src2CL (OpCL << Src2Shift) | |
139 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
140 | #define Src2One (OpOne << Src2Shift) | |
141 | #define Src2Imm (OpImm << Src2Shift) | |
c191a7a0 AK |
142 | #define Src2ES (OpES << Src2Shift) |
143 | #define Src2CS (OpCS << Src2Shift) | |
144 | #define Src2SS (OpSS << Src2Shift) | |
145 | #define Src2DS (OpDS << Src2Shift) | |
146 | #define Src2FS (OpFS << Src2Shift) | |
147 | #define Src2GS (OpGS << Src2Shift) | |
4dd6a57d | 148 | #define Src2Mask (OpMask << Src2Shift) |
cbe2c9d3 | 149 | #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ |
1c11b376 AK |
150 | #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
151 | #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ | |
152 | #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ | |
e28bbd44 | 153 | #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ |
b6744dc3 | 154 | #define NoWrite ((u64)1 << 45) /* No writeback */ |
6aa8b732 | 155 | |
d0e53325 AK |
156 | #define X2(x...) x, x |
157 | #define X3(x...) X2(x), x | |
158 | #define X4(x...) X2(x), X2(x) | |
159 | #define X5(x...) X4(x), x | |
160 | #define X6(x...) X4(x), X2(x) | |
161 | #define X7(x...) X4(x), X3(x) | |
162 | #define X8(x...) X4(x), X4(x) | |
163 | #define X16(x...) X8(x), X8(x) | |
83babbca | 164 | |
e28bbd44 AK |
165 | #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) |
166 | #define FASTOP_SIZE 8 | |
167 | ||
168 | /* | |
169 | * fastop functions have a special calling convention: | |
170 | * | |
171 | * dst: [rdx]:rax (in/out) | |
172 | * src: rbx (in/out) | |
173 | * src2: rcx (in) | |
174 | * flags: rflags (in/out) | |
175 | * | |
176 | * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for | |
177 | * different operand sizes can be reached by calculation, rather than a jump | |
178 | * table (which would be bigger than the code). | |
179 | * | |
180 | * fastop functions are declared as taking a never-defined fastop parameter, | |
181 | * so they can't be called from C directly. | |
182 | */ | |
183 | ||
184 | struct fastop; | |
185 | ||
d65b1dee | 186 | struct opcode { |
b1ea50b2 AK |
187 | u64 flags : 56; |
188 | u64 intercept : 8; | |
120df890 | 189 | union { |
ef65c889 | 190 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
fd0a0d82 MK |
191 | const struct opcode *group; |
192 | const struct group_dual *gdual; | |
193 | const struct gprefix *gprefix; | |
045a282c | 194 | const struct escape *esc; |
e28bbd44 | 195 | void (*fastop)(struct fastop *fake); |
120df890 | 196 | } u; |
d09beabd | 197 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
198 | }; |
199 | ||
200 | struct group_dual { | |
201 | struct opcode mod012[8]; | |
202 | struct opcode mod3[8]; | |
d65b1dee AK |
203 | }; |
204 | ||
0d7cdee8 AK |
205 | struct gprefix { |
206 | struct opcode pfx_no; | |
207 | struct opcode pfx_66; | |
208 | struct opcode pfx_f2; | |
209 | struct opcode pfx_f3; | |
210 | }; | |
211 | ||
045a282c GN |
212 | struct escape { |
213 | struct opcode op[8]; | |
214 | struct opcode high[64]; | |
215 | }; | |
216 | ||
6aa8b732 | 217 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
218 | #define EFLG_ID (1<<21) |
219 | #define EFLG_VIP (1<<20) | |
220 | #define EFLG_VIF (1<<19) | |
221 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
222 | #define EFLG_VM (1<<17) |
223 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
224 | #define EFLG_IOPL (3<<12) |
225 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
226 | #define EFLG_OF (1<<11) |
227 | #define EFLG_DF (1<<10) | |
b1d86143 | 228 | #define EFLG_IF (1<<9) |
d4c6a154 | 229 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
230 | #define EFLG_SF (1<<7) |
231 | #define EFLG_ZF (1<<6) | |
232 | #define EFLG_AF (1<<4) | |
233 | #define EFLG_PF (1<<2) | |
234 | #define EFLG_CF (1<<0) | |
235 | ||
62bd430e MG |
236 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
237 | #define EFLG_RESERVED_ONE_MASK 2 | |
238 | ||
dd856efa AK |
239 | static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) |
240 | { | |
241 | if (!(ctxt->regs_valid & (1 << nr))) { | |
242 | ctxt->regs_valid |= 1 << nr; | |
243 | ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); | |
244 | } | |
245 | return ctxt->_regs[nr]; | |
246 | } | |
247 | ||
248 | static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
249 | { | |
250 | ctxt->regs_valid |= 1 << nr; | |
251 | ctxt->regs_dirty |= 1 << nr; | |
252 | return &ctxt->_regs[nr]; | |
253 | } | |
254 | ||
255 | static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
256 | { | |
257 | reg_read(ctxt, nr); | |
258 | return reg_write(ctxt, nr); | |
259 | } | |
260 | ||
261 | static void writeback_registers(struct x86_emulate_ctxt *ctxt) | |
262 | { | |
263 | unsigned reg; | |
264 | ||
265 | for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) | |
266 | ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); | |
267 | } | |
268 | ||
269 | static void invalidate_registers(struct x86_emulate_ctxt *ctxt) | |
270 | { | |
271 | ctxt->regs_dirty = 0; | |
272 | ctxt->regs_valid = 0; | |
273 | } | |
274 | ||
6aa8b732 AK |
275 | /* |
276 | * Instruction emulation: | |
277 | * Most instructions are emulated directly via a fragment of inline assembly | |
278 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
279 | * any modified flags. | |
280 | */ | |
281 | ||
05b3e0c2 | 282 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
283 | #define _LO32 "k" /* force 32-bit operand */ |
284 | #define _STK "%%rsp" /* stack pointer */ | |
285 | #elif defined(__i386__) | |
286 | #define _LO32 "" /* force 32-bit operand */ | |
287 | #define _STK "%%esp" /* stack pointer */ | |
288 | #endif | |
289 | ||
290 | /* | |
291 | * These EFLAGS bits are restored from saved value during emulation, and | |
292 | * any changes are written back to the saved value after emulation. | |
293 | */ | |
294 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
295 | ||
296 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
297 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
298 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
299 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
300 | "push %"_tmp"; " \ | |
301 | "push %"_tmp"; " \ | |
302 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
303 | "andl %"_LO32 _tmp",("_STK"); " \ | |
304 | "pushf; " \ | |
305 | "notl %"_LO32 _tmp"; " \ | |
306 | "andl %"_LO32 _tmp",("_STK"); " \ | |
307 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
308 | "pop %"_tmp"; " \ | |
309 | "orl %"_LO32 _tmp",("_STK"); " \ | |
310 | "popf; " \ | |
311 | "pop %"_sav"; " | |
6aa8b732 AK |
312 | |
313 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
314 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
315 | /* _sav |= EFLAGS & _msk; */ \ | |
316 | "pushf; " \ | |
317 | "pop %"_tmp"; " \ | |
318 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
319 | "orl %"_LO32 _tmp",%"_sav"; " | |
320 | ||
dda96d8f AK |
321 | #ifdef CONFIG_X86_64 |
322 | #define ON64(x) x | |
323 | #else | |
324 | #define ON64(x) | |
325 | #endif | |
326 | ||
a31b9cea | 327 | #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
328 | do { \ |
329 | __asm__ __volatile__ ( \ | |
330 | _PRE_EFLAGS("0", "4", "2") \ | |
331 | _op _suffix " %"_x"3,%1; " \ | |
332 | _POST_EFLAGS("0", "4", "2") \ | |
a31b9cea AK |
333 | : "=m" ((ctxt)->eflags), \ |
334 | "+q" (*(_dsttype*)&(ctxt)->dst.val), \ | |
6b7ad61f | 335 | "=&r" (_tmp) \ |
a31b9cea | 336 | : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ |
f3fd92fb | 337 | } while (0) |
6b7ad61f AK |
338 | |
339 | ||
6aa8b732 | 340 | /* Raw emulation: instruction has two explicit operands. */ |
a31b9cea | 341 | #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6b7ad61f AK |
342 | do { \ |
343 | unsigned long _tmp; \ | |
344 | \ | |
a31b9cea | 345 | switch ((ctxt)->dst.bytes) { \ |
6b7ad61f | 346 | case 2: \ |
a31b9cea | 347 | ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ |
6b7ad61f AK |
348 | break; \ |
349 | case 4: \ | |
a31b9cea | 350 | ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ |
6b7ad61f AK |
351 | break; \ |
352 | case 8: \ | |
a31b9cea | 353 | ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
354 | break; \ |
355 | } \ | |
6aa8b732 AK |
356 | } while (0) |
357 | ||
a31b9cea | 358 | #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6aa8b732 | 359 | do { \ |
6b7ad61f | 360 | unsigned long _tmp; \ |
a31b9cea | 361 | switch ((ctxt)->dst.bytes) { \ |
6aa8b732 | 362 | case 1: \ |
a31b9cea | 363 | ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ |
6aa8b732 AK |
364 | break; \ |
365 | default: \ | |
a31b9cea | 366 | __emulate_2op_nobyte(ctxt, _op, \ |
6aa8b732 AK |
367 | _wx, _wy, _lx, _ly, _qx, _qy); \ |
368 | break; \ | |
369 | } \ | |
370 | } while (0) | |
371 | ||
372 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
a31b9cea AK |
373 | #define emulate_2op_SrcB(ctxt, _op) \ |
374 | __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") | |
6aa8b732 AK |
375 | |
376 | /* Source operand is byte, word, long or quad sized. */ | |
a31b9cea AK |
377 | #define emulate_2op_SrcV(ctxt, _op) \ |
378 | __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") | |
6aa8b732 AK |
379 | |
380 | /* Source operand is word, long or quad sized. */ | |
a31b9cea AK |
381 | #define emulate_2op_SrcV_nobyte(ctxt, _op) \ |
382 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") | |
6aa8b732 | 383 | |
d175226a | 384 | /* Instruction has three operands and one operand is stored in ECX register */ |
29053a60 | 385 | #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ |
7295261c AK |
386 | do { \ |
387 | unsigned long _tmp; \ | |
761441b9 AK |
388 | _type _clv = (ctxt)->src2.val; \ |
389 | _type _srcv = (ctxt)->src.val; \ | |
390 | _type _dstv = (ctxt)->dst.val; \ | |
7295261c AK |
391 | \ |
392 | __asm__ __volatile__ ( \ | |
393 | _PRE_EFLAGS("0", "5", "2") \ | |
394 | _op _suffix " %4,%1 \n" \ | |
395 | _POST_EFLAGS("0", "5", "2") \ | |
761441b9 | 396 | : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ |
7295261c AK |
397 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ |
398 | ); \ | |
399 | \ | |
761441b9 AK |
400 | (ctxt)->src2.val = (unsigned long) _clv; \ |
401 | (ctxt)->src2.val = (unsigned long) _srcv; \ | |
402 | (ctxt)->dst.val = (unsigned long) _dstv; \ | |
d175226a GT |
403 | } while (0) |
404 | ||
761441b9 | 405 | #define emulate_2op_cl(ctxt, _op) \ |
7295261c | 406 | do { \ |
761441b9 | 407 | switch ((ctxt)->dst.bytes) { \ |
7295261c | 408 | case 2: \ |
29053a60 | 409 | __emulate_2op_cl(ctxt, _op, "w", u16); \ |
7295261c AK |
410 | break; \ |
411 | case 4: \ | |
29053a60 | 412 | __emulate_2op_cl(ctxt, _op, "l", u32); \ |
7295261c AK |
413 | break; \ |
414 | case 8: \ | |
29053a60 | 415 | ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ |
7295261c AK |
416 | break; \ |
417 | } \ | |
d175226a GT |
418 | } while (0) |
419 | ||
d1eef45d | 420 | #define __emulate_1op(ctxt, _op, _suffix) \ |
6aa8b732 AK |
421 | do { \ |
422 | unsigned long _tmp; \ | |
423 | \ | |
dda96d8f AK |
424 | __asm__ __volatile__ ( \ |
425 | _PRE_EFLAGS("0", "3", "2") \ | |
426 | _op _suffix " %1; " \ | |
427 | _POST_EFLAGS("0", "3", "2") \ | |
d1eef45d | 428 | : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ |
dda96d8f AK |
429 | "=&r" (_tmp) \ |
430 | : "i" (EFLAGS_MASK)); \ | |
431 | } while (0) | |
432 | ||
433 | /* Instruction has only one explicit operand (no source operand). */ | |
d1eef45d | 434 | #define emulate_1op(ctxt, _op) \ |
dda96d8f | 435 | do { \ |
d1eef45d AK |
436 | switch ((ctxt)->dst.bytes) { \ |
437 | case 1: __emulate_1op(ctxt, _op, "b"); break; \ | |
438 | case 2: __emulate_1op(ctxt, _op, "w"); break; \ | |
439 | case 4: __emulate_1op(ctxt, _op, "l"); break; \ | |
440 | case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ | |
6aa8b732 AK |
441 | } \ |
442 | } while (0) | |
443 | ||
4d758349 AK |
444 | static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); |
445 | ||
b7d491e7 AK |
446 | #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" |
447 | #define FOP_RET "ret \n\t" | |
448 | ||
449 | #define FOP_START(op) \ | |
450 | extern void em_##op(struct fastop *fake); \ | |
451 | asm(".pushsection .text, \"ax\" \n\t" \ | |
452 | ".global em_" #op " \n\t" \ | |
453 | FOP_ALIGN \ | |
454 | "em_" #op ": \n\t" | |
455 | ||
456 | #define FOP_END \ | |
457 | ".popsection") | |
458 | ||
0bdea068 AK |
459 | #define FOPNOP() FOP_ALIGN FOP_RET |
460 | ||
b7d491e7 AK |
461 | #define FOP1E(op, dst) \ |
462 | FOP_ALIGN #op " %" #dst " \n\t" FOP_RET | |
463 | ||
464 | #define FASTOP1(op) \ | |
465 | FOP_START(op) \ | |
466 | FOP1E(op##b, al) \ | |
467 | FOP1E(op##w, ax) \ | |
468 | FOP1E(op##l, eax) \ | |
469 | ON64(FOP1E(op##q, rax)) \ | |
470 | FOP_END | |
471 | ||
f7857f35 AK |
472 | #define FOP2E(op, dst, src) \ |
473 | FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET | |
474 | ||
475 | #define FASTOP2(op) \ | |
476 | FOP_START(op) \ | |
477 | FOP2E(op##b, al, bl) \ | |
478 | FOP2E(op##w, ax, bx) \ | |
479 | FOP2E(op##l, eax, ebx) \ | |
480 | ON64(FOP2E(op##q, rax, rbx)) \ | |
481 | FOP_END | |
482 | ||
11c363ba AK |
483 | /* 2 operand, word only */ |
484 | #define FASTOP2W(op) \ | |
485 | FOP_START(op) \ | |
486 | FOPNOP() \ | |
487 | FOP2E(op##w, ax, bx) \ | |
488 | FOP2E(op##l, eax, ebx) \ | |
489 | ON64(FOP2E(op##q, rax, rbx)) \ | |
490 | FOP_END | |
491 | ||
007a3b54 AK |
492 | /* 2 operand, src is CL */ |
493 | #define FASTOP2CL(op) \ | |
494 | FOP_START(op) \ | |
495 | FOP2E(op##b, al, cl) \ | |
496 | FOP2E(op##w, ax, cl) \ | |
497 | FOP2E(op##l, eax, cl) \ | |
498 | ON64(FOP2E(op##q, rax, cl)) \ | |
499 | FOP_END | |
500 | ||
0bdea068 AK |
501 | #define FOP3E(op, dst, src, src2) \ |
502 | FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET | |
503 | ||
504 | /* 3-operand, word-only, src2=cl */ | |
505 | #define FASTOP3WCL(op) \ | |
506 | FOP_START(op) \ | |
507 | FOPNOP() \ | |
508 | FOP3E(op##w, ax, bx, cl) \ | |
509 | FOP3E(op##l, eax, ebx, cl) \ | |
510 | ON64(FOP3E(op##q, rax, rbx, cl)) \ | |
511 | FOP_END | |
512 | ||
9ae9feba AK |
513 | /* Special case for SETcc - 1 instruction per cc */ |
514 | #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" | |
515 | ||
516 | FOP_START(setcc) | |
517 | FOP_SETCC(seto) | |
518 | FOP_SETCC(setno) | |
519 | FOP_SETCC(setc) | |
520 | FOP_SETCC(setnc) | |
521 | FOP_SETCC(setz) | |
522 | FOP_SETCC(setnz) | |
523 | FOP_SETCC(setbe) | |
524 | FOP_SETCC(setnbe) | |
525 | FOP_SETCC(sets) | |
526 | FOP_SETCC(setns) | |
527 | FOP_SETCC(setp) | |
528 | FOP_SETCC(setnp) | |
529 | FOP_SETCC(setl) | |
530 | FOP_SETCC(setnl) | |
531 | FOP_SETCC(setle) | |
532 | FOP_SETCC(setnle) | |
533 | FOP_END; | |
534 | ||
e8f2b1d6 | 535 | #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ |
f6b3597b AK |
536 | do { \ |
537 | unsigned long _tmp; \ | |
dd856efa AK |
538 | ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \ |
539 | ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \ | |
f6b3597b AK |
540 | \ |
541 | __asm__ __volatile__ ( \ | |
542 | _PRE_EFLAGS("0", "5", "1") \ | |
543 | "1: \n\t" \ | |
544 | _op _suffix " %6; " \ | |
545 | "2: \n\t" \ | |
546 | _POST_EFLAGS("0", "5", "1") \ | |
547 | ".pushsection .fixup,\"ax\" \n\t" \ | |
548 | "3: movb $1, %4 \n\t" \ | |
549 | "jmp 2b \n\t" \ | |
550 | ".popsection \n\t" \ | |
551 | _ASM_EXTABLE(1b, 3b) \ | |
e8f2b1d6 AK |
552 | : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ |
553 | "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ | |
cb7cb286 | 554 | : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \ |
f6b3597b AK |
555 | } while (0) |
556 | ||
3f9f53b0 | 557 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
e8f2b1d6 | 558 | #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ |
7295261c | 559 | do { \ |
e8f2b1d6 | 560 | switch((ctxt)->src.bytes) { \ |
7295261c | 561 | case 1: \ |
e8f2b1d6 | 562 | __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ |
7295261c AK |
563 | break; \ |
564 | case 2: \ | |
e8f2b1d6 | 565 | __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ |
7295261c AK |
566 | break; \ |
567 | case 4: \ | |
e8f2b1d6 | 568 | __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ |
f6b3597b AK |
569 | break; \ |
570 | case 8: ON64( \ | |
e8f2b1d6 | 571 | __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ |
f6b3597b AK |
572 | break; \ |
573 | } \ | |
574 | } while (0) | |
575 | ||
8a76d7f2 JR |
576 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
577 | enum x86_intercept intercept, | |
578 | enum x86_intercept_stage stage) | |
579 | { | |
580 | struct x86_instruction_info info = { | |
581 | .intercept = intercept, | |
9dac77fa AK |
582 | .rep_prefix = ctxt->rep_prefix, |
583 | .modrm_mod = ctxt->modrm_mod, | |
584 | .modrm_reg = ctxt->modrm_reg, | |
585 | .modrm_rm = ctxt->modrm_rm, | |
586 | .src_val = ctxt->src.val64, | |
587 | .src_bytes = ctxt->src.bytes, | |
588 | .dst_bytes = ctxt->dst.bytes, | |
589 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
590 | .next_rip = ctxt->eip, |
591 | }; | |
592 | ||
2953538e | 593 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
594 | } |
595 | ||
f47cfa31 AK |
596 | static void assign_masked(ulong *dest, ulong src, ulong mask) |
597 | { | |
598 | *dest = (*dest & ~mask) | (src & mask); | |
599 | } | |
600 | ||
9dac77fa | 601 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 602 | { |
9dac77fa | 603 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
604 | } |
605 | ||
f47cfa31 AK |
606 | static ulong stack_mask(struct x86_emulate_ctxt *ctxt) |
607 | { | |
608 | u16 sel; | |
609 | struct desc_struct ss; | |
610 | ||
611 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
612 | return ~0UL; | |
613 | ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); | |
614 | return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ | |
615 | } | |
616 | ||
612e89f0 AK |
617 | static int stack_size(struct x86_emulate_ctxt *ctxt) |
618 | { | |
619 | return (__fls(stack_mask(ctxt)) + 1) >> 3; | |
620 | } | |
621 | ||
6aa8b732 | 622 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 623 | static inline unsigned long |
9dac77fa | 624 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 625 | { |
9dac77fa | 626 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
627 | return reg; |
628 | else | |
9dac77fa | 629 | return reg & ad_mask(ctxt); |
e4706772 HH |
630 | } |
631 | ||
632 | static inline unsigned long | |
9dac77fa | 633 | register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 634 | { |
9dac77fa | 635 | return address_mask(ctxt, reg); |
e4706772 HH |
636 | } |
637 | ||
5ad105e5 AK |
638 | static void masked_increment(ulong *reg, ulong mask, int inc) |
639 | { | |
640 | assign_masked(reg, *reg + inc, mask); | |
641 | } | |
642 | ||
7a957275 | 643 | static inline void |
9dac77fa | 644 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
7a957275 | 645 | { |
5ad105e5 AK |
646 | ulong mask; |
647 | ||
9dac77fa | 648 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
5ad105e5 | 649 | mask = ~0UL; |
7a957275 | 650 | else |
5ad105e5 AK |
651 | mask = ad_mask(ctxt); |
652 | masked_increment(reg, mask, inc); | |
653 | } | |
654 | ||
655 | static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) | |
656 | { | |
dd856efa | 657 | masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); |
7a957275 | 658 | } |
6aa8b732 | 659 | |
9dac77fa | 660 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
7a957275 | 661 | { |
9dac77fa | 662 | register_address_increment(ctxt, &ctxt->_eip, rel); |
7a957275 | 663 | } |
098c937b | 664 | |
56697687 AK |
665 | static u32 desc_limit_scaled(struct desc_struct *desc) |
666 | { | |
667 | u32 limit = get_desc_limit(desc); | |
668 | ||
669 | return desc->g ? (limit << 12) | 0xfff : limit; | |
670 | } | |
671 | ||
9dac77fa | 672 | static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df | 673 | { |
9dac77fa AK |
674 | ctxt->has_seg_override = true; |
675 | ctxt->seg_override = seg; | |
7a5b56df AK |
676 | } |
677 | ||
7b105ca2 | 678 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
679 | { |
680 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
681 | return 0; | |
682 | ||
7b105ca2 | 683 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
684 | } |
685 | ||
9dac77fa | 686 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt) |
7a5b56df | 687 | { |
9dac77fa | 688 | if (!ctxt->has_seg_override) |
7a5b56df AK |
689 | return 0; |
690 | ||
9dac77fa | 691 | return ctxt->seg_override; |
7a5b56df AK |
692 | } |
693 | ||
35d3d4a1 AK |
694 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
695 | u32 error, bool valid) | |
54b8486f | 696 | { |
da9cb575 AK |
697 | ctxt->exception.vector = vec; |
698 | ctxt->exception.error_code = error; | |
699 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 700 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
701 | } |
702 | ||
3b88e41a JR |
703 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
704 | { | |
705 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
706 | } | |
707 | ||
35d3d4a1 | 708 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 709 | { |
35d3d4a1 | 710 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
711 | } |
712 | ||
618ff15d AK |
713 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
714 | { | |
715 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
716 | } | |
717 | ||
35d3d4a1 | 718 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 719 | { |
35d3d4a1 | 720 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
721 | } |
722 | ||
35d3d4a1 | 723 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 724 | { |
35d3d4a1 | 725 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
726 | } |
727 | ||
34d1f490 AK |
728 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
729 | { | |
35d3d4a1 | 730 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
731 | } |
732 | ||
1253791d AK |
733 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
734 | { | |
735 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
736 | } | |
737 | ||
1aa36616 AK |
738 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
739 | { | |
740 | u16 selector; | |
741 | struct desc_struct desc; | |
742 | ||
743 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
744 | return selector; | |
745 | } | |
746 | ||
747 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
748 | unsigned seg) | |
749 | { | |
750 | u16 dummy; | |
751 | u32 base3; | |
752 | struct desc_struct desc; | |
753 | ||
754 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
755 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
756 | } | |
757 | ||
1c11b376 AK |
758 | /* |
759 | * x86 defines three classes of vector instructions: explicitly | |
760 | * aligned, explicitly unaligned, and the rest, which change behaviour | |
761 | * depending on whether they're AVX encoded or not. | |
762 | * | |
763 | * Also included is CMPXCHG16B which is not a vector instruction, yet it is | |
764 | * subject to the same check. | |
765 | */ | |
766 | static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) | |
767 | { | |
768 | if (likely(size < 16)) | |
769 | return false; | |
770 | ||
771 | if (ctxt->d & Aligned) | |
772 | return true; | |
773 | else if (ctxt->d & Unaligned) | |
774 | return false; | |
775 | else if (ctxt->d & Avx) | |
776 | return false; | |
777 | else | |
778 | return true; | |
779 | } | |
780 | ||
3d9b938e | 781 | static int __linearize(struct x86_emulate_ctxt *ctxt, |
52fd8b44 | 782 | struct segmented_address addr, |
3d9b938e | 783 | unsigned size, bool write, bool fetch, |
52fd8b44 AK |
784 | ulong *linear) |
785 | { | |
618ff15d AK |
786 | struct desc_struct desc; |
787 | bool usable; | |
52fd8b44 | 788 | ulong la; |
618ff15d | 789 | u32 lim; |
1aa36616 | 790 | u16 sel; |
3a78a4f4 | 791 | unsigned cpl; |
52fd8b44 | 792 | |
7b105ca2 | 793 | la = seg_base(ctxt, addr.seg) + addr.ea; |
618ff15d | 794 | switch (ctxt->mode) { |
618ff15d AK |
795 | case X86EMUL_MODE_PROT64: |
796 | if (((signed long)la << 16) >> 16 != la) | |
797 | return emulate_gp(ctxt, 0); | |
798 | break; | |
799 | default: | |
1aa36616 AK |
800 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
801 | addr.seg); | |
618ff15d AK |
802 | if (!usable) |
803 | goto bad; | |
58b7825b GN |
804 | /* code segment in protected mode or read-only data segment */ |
805 | if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) | |
806 | || !(desc.type & 2)) && write) | |
618ff15d AK |
807 | goto bad; |
808 | /* unreadable code segment */ | |
3d9b938e | 809 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
810 | goto bad; |
811 | lim = desc_limit_scaled(&desc); | |
812 | if ((desc.type & 8) || !(desc.type & 4)) { | |
813 | /* expand-up segment */ | |
814 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
815 | goto bad; | |
816 | } else { | |
fc058680 | 817 | /* expand-down segment */ |
618ff15d AK |
818 | if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) |
819 | goto bad; | |
820 | lim = desc.d ? 0xffffffff : 0xffff; | |
821 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
822 | goto bad; | |
823 | } | |
717746e3 | 824 | cpl = ctxt->ops->cpl(ctxt); |
618ff15d AK |
825 | if (!(desc.type & 8)) { |
826 | /* data segment */ | |
827 | if (cpl > desc.dpl) | |
828 | goto bad; | |
829 | } else if ((desc.type & 8) && !(desc.type & 4)) { | |
830 | /* nonconforming code segment */ | |
831 | if (cpl != desc.dpl) | |
832 | goto bad; | |
833 | } else if ((desc.type & 8) && (desc.type & 4)) { | |
834 | /* conforming code segment */ | |
835 | if (cpl < desc.dpl) | |
836 | goto bad; | |
837 | } | |
838 | break; | |
839 | } | |
9dac77fa | 840 | if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) |
52fd8b44 | 841 | la &= (u32)-1; |
1c11b376 AK |
842 | if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) |
843 | return emulate_gp(ctxt, 0); | |
52fd8b44 AK |
844 | *linear = la; |
845 | return X86EMUL_CONTINUE; | |
618ff15d AK |
846 | bad: |
847 | if (addr.seg == VCPU_SREG_SS) | |
0afbe2f8 | 848 | return emulate_ss(ctxt, sel); |
618ff15d | 849 | else |
0afbe2f8 | 850 | return emulate_gp(ctxt, sel); |
52fd8b44 AK |
851 | } |
852 | ||
3d9b938e NE |
853 | static int linearize(struct x86_emulate_ctxt *ctxt, |
854 | struct segmented_address addr, | |
855 | unsigned size, bool write, | |
856 | ulong *linear) | |
857 | { | |
858 | return __linearize(ctxt, addr, size, write, false, linear); | |
859 | } | |
860 | ||
861 | ||
3ca3ac4d AK |
862 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
863 | struct segmented_address addr, | |
864 | void *data, | |
865 | unsigned size) | |
866 | { | |
9fa088f4 AK |
867 | int rc; |
868 | ulong linear; | |
869 | ||
83b8795a | 870 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
871 | if (rc != X86EMUL_CONTINUE) |
872 | return rc; | |
0f65dd70 | 873 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
874 | } |
875 | ||
807941b1 TY |
876 | /* |
877 | * Fetch the next byte of the instruction being emulated which is pointed to | |
878 | * by ctxt->_eip, then increment ctxt->_eip. | |
879 | * | |
880 | * Also prefetch the remaining bytes of the instruction without crossing page | |
881 | * boundary if they are not in fetch_cache yet. | |
882 | */ | |
883 | static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) | |
62266869 | 884 | { |
9dac77fa | 885 | struct fetch_cache *fc = &ctxt->fetch; |
62266869 | 886 | int rc; |
2fb53ad8 | 887 | int size, cur_size; |
62266869 | 888 | |
807941b1 | 889 | if (ctxt->_eip == fc->end) { |
3d9b938e | 890 | unsigned long linear; |
807941b1 TY |
891 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
892 | .ea = ctxt->_eip }; | |
2fb53ad8 | 893 | cur_size = fc->end - fc->start; |
807941b1 TY |
894 | size = min(15UL - cur_size, |
895 | PAGE_SIZE - offset_in_page(ctxt->_eip)); | |
3d9b938e | 896 | rc = __linearize(ctxt, addr, size, false, true, &linear); |
7d88bb48 | 897 | if (unlikely(rc != X86EMUL_CONTINUE)) |
3d9b938e | 898 | return rc; |
ef5d75cc TY |
899 | rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, |
900 | size, &ctxt->exception); | |
7d88bb48 | 901 | if (unlikely(rc != X86EMUL_CONTINUE)) |
62266869 | 902 | return rc; |
2fb53ad8 | 903 | fc->end += size; |
62266869 | 904 | } |
807941b1 TY |
905 | *dest = fc->data[ctxt->_eip - fc->start]; |
906 | ctxt->_eip++; | |
3e2815e9 | 907 | return X86EMUL_CONTINUE; |
62266869 AK |
908 | } |
909 | ||
910 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
807941b1 | 911 | void *dest, unsigned size) |
62266869 | 912 | { |
3e2815e9 | 913 | int rc; |
62266869 | 914 | |
eb3c79e6 | 915 | /* x86 instructions are limited to 15 bytes. */ |
7d88bb48 | 916 | if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) |
eb3c79e6 | 917 | return X86EMUL_UNHANDLEABLE; |
62266869 | 918 | while (size--) { |
807941b1 | 919 | rc = do_insn_fetch_byte(ctxt, dest++); |
3e2815e9 | 920 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
921 | return rc; |
922 | } | |
3e2815e9 | 923 | return X86EMUL_CONTINUE; |
62266869 AK |
924 | } |
925 | ||
67cbc90d | 926 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 927 | #define insn_fetch(_type, _ctxt) \ |
67cbc90d | 928 | ({ unsigned long _x; \ |
e85a1085 | 929 | rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ |
67cbc90d TY |
930 | if (rc != X86EMUL_CONTINUE) \ |
931 | goto done; \ | |
67cbc90d TY |
932 | (_type)_x; \ |
933 | }) | |
934 | ||
807941b1 TY |
935 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
936 | ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ | |
67cbc90d TY |
937 | if (rc != X86EMUL_CONTINUE) \ |
938 | goto done; \ | |
67cbc90d TY |
939 | }) |
940 | ||
1e3c5cb0 RR |
941 | /* |
942 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
943 | * pointer into the block that addresses the relevant register. | |
944 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
945 | */ | |
dd856efa | 946 | static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, |
1e3c5cb0 | 947 | int highbyte_regs) |
6aa8b732 AK |
948 | { |
949 | void *p; | |
950 | ||
6aa8b732 | 951 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) |
dd856efa AK |
952 | p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; |
953 | else | |
954 | p = reg_rmw(ctxt, modrm_reg); | |
6aa8b732 AK |
955 | return p; |
956 | } | |
957 | ||
958 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 959 | struct segmented_address addr, |
6aa8b732 AK |
960 | u16 *size, unsigned long *address, int op_bytes) |
961 | { | |
962 | int rc; | |
963 | ||
964 | if (op_bytes == 2) | |
965 | op_bytes = 3; | |
966 | *address = 0; | |
3ca3ac4d | 967 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 968 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 969 | return rc; |
30b31ab6 | 970 | addr.ea += 2; |
3ca3ac4d | 971 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
972 | return rc; |
973 | } | |
974 | ||
34b77652 AK |
975 | FASTOP2(add); |
976 | FASTOP2(or); | |
977 | FASTOP2(adc); | |
978 | FASTOP2(sbb); | |
979 | FASTOP2(and); | |
980 | FASTOP2(sub); | |
981 | FASTOP2(xor); | |
982 | FASTOP2(cmp); | |
983 | FASTOP2(test); | |
984 | ||
985 | FASTOP3WCL(shld); | |
986 | FASTOP3WCL(shrd); | |
987 | ||
988 | FASTOP2W(imul); | |
989 | ||
990 | FASTOP1(not); | |
991 | FASTOP1(neg); | |
992 | FASTOP1(inc); | |
993 | FASTOP1(dec); | |
994 | ||
995 | FASTOP2CL(rol); | |
996 | FASTOP2CL(ror); | |
997 | FASTOP2CL(rcl); | |
998 | FASTOP2CL(rcr); | |
999 | FASTOP2CL(shl); | |
1000 | FASTOP2CL(shr); | |
1001 | FASTOP2CL(sar); | |
1002 | ||
1003 | FASTOP2W(bsf); | |
1004 | FASTOP2W(bsr); | |
1005 | FASTOP2W(bt); | |
1006 | FASTOP2W(bts); | |
1007 | FASTOP2W(btr); | |
1008 | FASTOP2W(btc); | |
1009 | ||
9ae9feba | 1010 | static u8 test_cc(unsigned int condition, unsigned long flags) |
bbe9abbd | 1011 | { |
9ae9feba AK |
1012 | u8 rc; |
1013 | void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); | |
bbe9abbd | 1014 | |
9ae9feba | 1015 | flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; |
3f0c3d0b | 1016 | asm("push %[flags]; popf; call *%[fastop]" |
9ae9feba AK |
1017 | : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); |
1018 | return rc; | |
bbe9abbd NK |
1019 | } |
1020 | ||
91ff3cb4 AK |
1021 | static void fetch_register_operand(struct operand *op) |
1022 | { | |
1023 | switch (op->bytes) { | |
1024 | case 1: | |
1025 | op->val = *(u8 *)op->addr.reg; | |
1026 | break; | |
1027 | case 2: | |
1028 | op->val = *(u16 *)op->addr.reg; | |
1029 | break; | |
1030 | case 4: | |
1031 | op->val = *(u32 *)op->addr.reg; | |
1032 | break; | |
1033 | case 8: | |
1034 | op->val = *(u64 *)op->addr.reg; | |
1035 | break; | |
1036 | } | |
1037 | } | |
1038 | ||
1253791d AK |
1039 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
1040 | { | |
1041 | ctxt->ops->get_fpu(ctxt); | |
1042 | switch (reg) { | |
89a87c67 MK |
1043 | case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; |
1044 | case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; | |
1045 | case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; | |
1046 | case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; | |
1047 | case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; | |
1048 | case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; | |
1049 | case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; | |
1050 | case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; | |
1253791d | 1051 | #ifdef CONFIG_X86_64 |
89a87c67 MK |
1052 | case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; |
1053 | case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; | |
1054 | case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; | |
1055 | case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; | |
1056 | case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; | |
1057 | case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; | |
1058 | case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; | |
1059 | case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; | |
1253791d AK |
1060 | #endif |
1061 | default: BUG(); | |
1062 | } | |
1063 | ctxt->ops->put_fpu(ctxt); | |
1064 | } | |
1065 | ||
1066 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
1067 | int reg) | |
1068 | { | |
1069 | ctxt->ops->get_fpu(ctxt); | |
1070 | switch (reg) { | |
89a87c67 MK |
1071 | case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; |
1072 | case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; | |
1073 | case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; | |
1074 | case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; | |
1075 | case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; | |
1076 | case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; | |
1077 | case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; | |
1078 | case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; | |
1253791d | 1079 | #ifdef CONFIG_X86_64 |
89a87c67 MK |
1080 | case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; |
1081 | case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; | |
1082 | case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; | |
1083 | case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; | |
1084 | case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; | |
1085 | case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; | |
1086 | case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; | |
1087 | case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; | |
1253791d AK |
1088 | #endif |
1089 | default: BUG(); | |
1090 | } | |
1091 | ctxt->ops->put_fpu(ctxt); | |
1092 | } | |
1093 | ||
cbe2c9d3 AK |
1094 | static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) |
1095 | { | |
1096 | ctxt->ops->get_fpu(ctxt); | |
1097 | switch (reg) { | |
1098 | case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; | |
1099 | case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; | |
1100 | case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; | |
1101 | case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; | |
1102 | case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; | |
1103 | case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; | |
1104 | case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; | |
1105 | case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; | |
1106 | default: BUG(); | |
1107 | } | |
1108 | ctxt->ops->put_fpu(ctxt); | |
1109 | } | |
1110 | ||
1111 | static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) | |
1112 | { | |
1113 | ctxt->ops->get_fpu(ctxt); | |
1114 | switch (reg) { | |
1115 | case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; | |
1116 | case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; | |
1117 | case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; | |
1118 | case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; | |
1119 | case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; | |
1120 | case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; | |
1121 | case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; | |
1122 | case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; | |
1123 | default: BUG(); | |
1124 | } | |
1125 | ctxt->ops->put_fpu(ctxt); | |
1126 | } | |
1127 | ||
045a282c GN |
1128 | static int em_fninit(struct x86_emulate_ctxt *ctxt) |
1129 | { | |
1130 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1131 | return emulate_nm(ctxt); | |
1132 | ||
1133 | ctxt->ops->get_fpu(ctxt); | |
1134 | asm volatile("fninit"); | |
1135 | ctxt->ops->put_fpu(ctxt); | |
1136 | return X86EMUL_CONTINUE; | |
1137 | } | |
1138 | ||
1139 | static int em_fnstcw(struct x86_emulate_ctxt *ctxt) | |
1140 | { | |
1141 | u16 fcw; | |
1142 | ||
1143 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1144 | return emulate_nm(ctxt); | |
1145 | ||
1146 | ctxt->ops->get_fpu(ctxt); | |
1147 | asm volatile("fnstcw %0": "+m"(fcw)); | |
1148 | ctxt->ops->put_fpu(ctxt); | |
1149 | ||
1150 | /* force 2 byte destination */ | |
1151 | ctxt->dst.bytes = 2; | |
1152 | ctxt->dst.val = fcw; | |
1153 | ||
1154 | return X86EMUL_CONTINUE; | |
1155 | } | |
1156 | ||
1157 | static int em_fnstsw(struct x86_emulate_ctxt *ctxt) | |
1158 | { | |
1159 | u16 fsw; | |
1160 | ||
1161 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1162 | return emulate_nm(ctxt); | |
1163 | ||
1164 | ctxt->ops->get_fpu(ctxt); | |
1165 | asm volatile("fnstsw %0": "+m"(fsw)); | |
1166 | ctxt->ops->put_fpu(ctxt); | |
1167 | ||
1168 | /* force 2 byte destination */ | |
1169 | ctxt->dst.bytes = 2; | |
1170 | ctxt->dst.val = fsw; | |
1171 | ||
1172 | return X86EMUL_CONTINUE; | |
1173 | } | |
1174 | ||
1253791d | 1175 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, |
2adb5ad9 | 1176 | struct operand *op) |
3c118e24 | 1177 | { |
9dac77fa AK |
1178 | unsigned reg = ctxt->modrm_reg; |
1179 | int highbyte_regs = ctxt->rex_prefix == 0; | |
33615aa9 | 1180 | |
9dac77fa AK |
1181 | if (!(ctxt->d & ModRM)) |
1182 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 1183 | |
9dac77fa | 1184 | if (ctxt->d & Sse) { |
1253791d AK |
1185 | op->type = OP_XMM; |
1186 | op->bytes = 16; | |
1187 | op->addr.xmm = reg; | |
1188 | read_sse_reg(ctxt, &op->vec_val, reg); | |
1189 | return; | |
1190 | } | |
cbe2c9d3 AK |
1191 | if (ctxt->d & Mmx) { |
1192 | reg &= 7; | |
1193 | op->type = OP_MM; | |
1194 | op->bytes = 8; | |
1195 | op->addr.mm = reg; | |
1196 | return; | |
1197 | } | |
1253791d | 1198 | |
3c118e24 | 1199 | op->type = OP_REG; |
2adb5ad9 | 1200 | if (ctxt->d & ByteOp) { |
dd856efa | 1201 | op->addr.reg = decode_register(ctxt, reg, highbyte_regs); |
3c118e24 AK |
1202 | op->bytes = 1; |
1203 | } else { | |
dd856efa | 1204 | op->addr.reg = decode_register(ctxt, reg, 0); |
9dac77fa | 1205 | op->bytes = ctxt->op_bytes; |
3c118e24 | 1206 | } |
91ff3cb4 | 1207 | fetch_register_operand(op); |
3c118e24 AK |
1208 | op->orig_val = op->val; |
1209 | } | |
1210 | ||
a6e3407b AK |
1211 | static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) |
1212 | { | |
1213 | if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) | |
1214 | ctxt->modrm_seg = VCPU_SREG_SS; | |
1215 | } | |
1216 | ||
1c73ef66 | 1217 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 1218 | struct operand *op) |
1c73ef66 | 1219 | { |
1c73ef66 | 1220 | u8 sib; |
f5b4edcd | 1221 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 1222 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 1223 | ulong modrm_ea = 0; |
1c73ef66 | 1224 | |
9dac77fa AK |
1225 | if (ctxt->rex_prefix) { |
1226 | ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ | |
1227 | index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ | |
1228 | ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ | |
1c73ef66 AK |
1229 | } |
1230 | ||
9dac77fa AK |
1231 | ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; |
1232 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; | |
1233 | ctxt->modrm_rm |= (ctxt->modrm & 0x07); | |
1234 | ctxt->modrm_seg = VCPU_SREG_DS; | |
1c73ef66 | 1235 | |
9dac77fa | 1236 | if (ctxt->modrm_mod == 3) { |
2dbd0dd7 | 1237 | op->type = OP_REG; |
9dac77fa | 1238 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
dd856efa | 1239 | op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp); |
9dac77fa | 1240 | if (ctxt->d & Sse) { |
1253791d AK |
1241 | op->type = OP_XMM; |
1242 | op->bytes = 16; | |
9dac77fa AK |
1243 | op->addr.xmm = ctxt->modrm_rm; |
1244 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
1245 | return rc; |
1246 | } | |
cbe2c9d3 AK |
1247 | if (ctxt->d & Mmx) { |
1248 | op->type = OP_MM; | |
1249 | op->bytes = 8; | |
1250 | op->addr.xmm = ctxt->modrm_rm & 7; | |
1251 | return rc; | |
1252 | } | |
2dbd0dd7 | 1253 | fetch_register_operand(op); |
1c73ef66 AK |
1254 | return rc; |
1255 | } | |
1256 | ||
2dbd0dd7 AK |
1257 | op->type = OP_MEM; |
1258 | ||
9dac77fa | 1259 | if (ctxt->ad_bytes == 2) { |
dd856efa AK |
1260 | unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); |
1261 | unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); | |
1262 | unsigned si = reg_read(ctxt, VCPU_REGS_RSI); | |
1263 | unsigned di = reg_read(ctxt, VCPU_REGS_RDI); | |
1c73ef66 AK |
1264 | |
1265 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 1266 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1267 | case 0: |
9dac77fa | 1268 | if (ctxt->modrm_rm == 6) |
e85a1085 | 1269 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1270 | break; |
1271 | case 1: | |
e85a1085 | 1272 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1273 | break; |
1274 | case 2: | |
e85a1085 | 1275 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1276 | break; |
1277 | } | |
9dac77fa | 1278 | switch (ctxt->modrm_rm) { |
1c73ef66 | 1279 | case 0: |
2dbd0dd7 | 1280 | modrm_ea += bx + si; |
1c73ef66 AK |
1281 | break; |
1282 | case 1: | |
2dbd0dd7 | 1283 | modrm_ea += bx + di; |
1c73ef66 AK |
1284 | break; |
1285 | case 2: | |
2dbd0dd7 | 1286 | modrm_ea += bp + si; |
1c73ef66 AK |
1287 | break; |
1288 | case 3: | |
2dbd0dd7 | 1289 | modrm_ea += bp + di; |
1c73ef66 AK |
1290 | break; |
1291 | case 4: | |
2dbd0dd7 | 1292 | modrm_ea += si; |
1c73ef66 AK |
1293 | break; |
1294 | case 5: | |
2dbd0dd7 | 1295 | modrm_ea += di; |
1c73ef66 AK |
1296 | break; |
1297 | case 6: | |
9dac77fa | 1298 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 1299 | modrm_ea += bp; |
1c73ef66 AK |
1300 | break; |
1301 | case 7: | |
2dbd0dd7 | 1302 | modrm_ea += bx; |
1c73ef66 AK |
1303 | break; |
1304 | } | |
9dac77fa AK |
1305 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
1306 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
1307 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 1308 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
1309 | } else { |
1310 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 1311 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 1312 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
1313 | index_reg |= (sib >> 3) & 7; |
1314 | base_reg |= sib & 7; | |
1315 | scale = sib >> 6; | |
1316 | ||
9dac77fa | 1317 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 1318 | modrm_ea += insn_fetch(s32, ctxt); |
a6e3407b | 1319 | else { |
dd856efa | 1320 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1321 | adjust_modrm_seg(ctxt, base_reg); |
1322 | } | |
dc71d0f1 | 1323 | if (index_reg != 4) |
dd856efa | 1324 | modrm_ea += reg_read(ctxt, index_reg) << scale; |
9dac77fa | 1325 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { |
84411d85 | 1326 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 1327 | ctxt->rip_relative = 1; |
a6e3407b AK |
1328 | } else { |
1329 | base_reg = ctxt->modrm_rm; | |
dd856efa | 1330 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1331 | adjust_modrm_seg(ctxt, base_reg); |
1332 | } | |
9dac77fa | 1333 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1334 | case 0: |
9dac77fa | 1335 | if (ctxt->modrm_rm == 5) |
e85a1085 | 1336 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1337 | break; |
1338 | case 1: | |
e85a1085 | 1339 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1340 | break; |
1341 | case 2: | |
e85a1085 | 1342 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1343 | break; |
1344 | } | |
1345 | } | |
90de84f5 | 1346 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
1347 | done: |
1348 | return rc; | |
1349 | } | |
1350 | ||
1351 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1352 | struct operand *op) |
1c73ef66 | 1353 | { |
3e2815e9 | 1354 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1355 | |
2dbd0dd7 | 1356 | op->type = OP_MEM; |
9dac77fa | 1357 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1358 | case 2: |
e85a1085 | 1359 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1360 | break; |
1361 | case 4: | |
e85a1085 | 1362 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1363 | break; |
1364 | case 8: | |
e85a1085 | 1365 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1366 | break; |
1367 | } | |
1368 | done: | |
1369 | return rc; | |
1370 | } | |
1371 | ||
9dac77fa | 1372 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1373 | { |
7129eeca | 1374 | long sv = 0, mask; |
35c843c4 | 1375 | |
9dac77fa AK |
1376 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
1377 | mask = ~(ctxt->dst.bytes * 8 - 1); | |
35c843c4 | 1378 | |
9dac77fa AK |
1379 | if (ctxt->src.bytes == 2) |
1380 | sv = (s16)ctxt->src.val & (s16)mask; | |
1381 | else if (ctxt->src.bytes == 4) | |
1382 | sv = (s32)ctxt->src.val & (s32)mask; | |
35c843c4 | 1383 | |
9dac77fa | 1384 | ctxt->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 1385 | } |
ba7ff2b7 WY |
1386 | |
1387 | /* only subword offset */ | |
9dac77fa | 1388 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1389 | } |
1390 | ||
dde7e6d1 | 1391 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1392 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1393 | { |
dde7e6d1 | 1394 | int rc; |
9dac77fa | 1395 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1396 | |
f23b070e XG |
1397 | if (mc->pos < mc->end) |
1398 | goto read_cached; | |
6aa8b732 | 1399 | |
f23b070e XG |
1400 | WARN_ON((mc->end + size) >= sizeof(mc->data)); |
1401 | ||
1402 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, | |
1403 | &ctxt->exception); | |
1404 | if (rc != X86EMUL_CONTINUE) | |
1405 | return rc; | |
1406 | ||
1407 | mc->end += size; | |
1408 | ||
1409 | read_cached: | |
1410 | memcpy(dest, mc->data + mc->pos, size); | |
1411 | mc->pos += size; | |
dde7e6d1 AK |
1412 | return X86EMUL_CONTINUE; |
1413 | } | |
6aa8b732 | 1414 | |
3ca3ac4d AK |
1415 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1416 | struct segmented_address addr, | |
1417 | void *data, | |
1418 | unsigned size) | |
1419 | { | |
9fa088f4 AK |
1420 | int rc; |
1421 | ulong linear; | |
1422 | ||
83b8795a | 1423 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1424 | if (rc != X86EMUL_CONTINUE) |
1425 | return rc; | |
7b105ca2 | 1426 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1427 | } |
1428 | ||
1429 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1430 | struct segmented_address addr, | |
1431 | const void *data, | |
1432 | unsigned size) | |
1433 | { | |
9fa088f4 AK |
1434 | int rc; |
1435 | ulong linear; | |
1436 | ||
83b8795a | 1437 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1438 | if (rc != X86EMUL_CONTINUE) |
1439 | return rc; | |
0f65dd70 AK |
1440 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1441 | &ctxt->exception); | |
3ca3ac4d AK |
1442 | } |
1443 | ||
1444 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1445 | struct segmented_address addr, | |
1446 | const void *orig_data, const void *data, | |
1447 | unsigned size) | |
1448 | { | |
9fa088f4 AK |
1449 | int rc; |
1450 | ulong linear; | |
1451 | ||
83b8795a | 1452 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1453 | if (rc != X86EMUL_CONTINUE) |
1454 | return rc; | |
0f65dd70 AK |
1455 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1456 | size, &ctxt->exception); | |
3ca3ac4d AK |
1457 | } |
1458 | ||
dde7e6d1 | 1459 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1460 | unsigned int size, unsigned short port, |
1461 | void *dest) | |
1462 | { | |
9dac77fa | 1463 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1464 | |
dde7e6d1 | 1465 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1466 | unsigned int in_page, n; |
9dac77fa | 1467 | unsigned int count = ctxt->rep_prefix ? |
dd856efa | 1468 | address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; |
dde7e6d1 | 1469 | in_page = (ctxt->eflags & EFLG_DF) ? |
dd856efa AK |
1470 | offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : |
1471 | PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); | |
dde7e6d1 AK |
1472 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, |
1473 | count); | |
1474 | if (n == 0) | |
1475 | n = 1; | |
1476 | rc->pos = rc->end = 0; | |
7b105ca2 | 1477 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1478 | return 0; |
1479 | rc->end = n * size; | |
6aa8b732 AK |
1480 | } |
1481 | ||
b3356bf0 GN |
1482 | if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) { |
1483 | ctxt->dst.data = rc->data + rc->pos; | |
1484 | ctxt->dst.type = OP_MEM_STR; | |
1485 | ctxt->dst.count = (rc->end - rc->pos) / size; | |
1486 | rc->pos = rc->end; | |
1487 | } else { | |
1488 | memcpy(dest, rc->data + rc->pos, size); | |
1489 | rc->pos += size; | |
1490 | } | |
dde7e6d1 AK |
1491 | return 1; |
1492 | } | |
6aa8b732 | 1493 | |
7f3d35fd KW |
1494 | static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, |
1495 | u16 index, struct desc_struct *desc) | |
1496 | { | |
1497 | struct desc_ptr dt; | |
1498 | ulong addr; | |
1499 | ||
1500 | ctxt->ops->get_idt(ctxt, &dt); | |
1501 | ||
1502 | if (dt.size < index * 8 + 7) | |
1503 | return emulate_gp(ctxt, index << 3 | 0x2); | |
1504 | ||
1505 | addr = dt.address + index * 8; | |
1506 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1507 | &ctxt->exception); | |
1508 | } | |
1509 | ||
dde7e6d1 | 1510 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1511 | u16 selector, struct desc_ptr *dt) |
1512 | { | |
0225fb50 | 1513 | const struct x86_emulate_ops *ops = ctxt->ops; |
7b105ca2 | 1514 | |
dde7e6d1 AK |
1515 | if (selector & 1 << 2) { |
1516 | struct desc_struct desc; | |
1aa36616 AK |
1517 | u16 sel; |
1518 | ||
dde7e6d1 | 1519 | memset (dt, 0, sizeof *dt); |
1aa36616 | 1520 | if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) |
dde7e6d1 | 1521 | return; |
e09d082c | 1522 | |
dde7e6d1 AK |
1523 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1524 | dt->address = get_desc_base(&desc); | |
1525 | } else | |
4bff1e86 | 1526 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1527 | } |
120df890 | 1528 | |
dde7e6d1 AK |
1529 | /* allowed just for 8 bytes segments */ |
1530 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
e919464b AK |
1531 | u16 selector, struct desc_struct *desc, |
1532 | ulong *desc_addr_p) | |
dde7e6d1 AK |
1533 | { |
1534 | struct desc_ptr dt; | |
1535 | u16 index = selector >> 3; | |
dde7e6d1 | 1536 | ulong addr; |
120df890 | 1537 | |
7b105ca2 | 1538 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1539 | |
35d3d4a1 AK |
1540 | if (dt.size < index * 8 + 7) |
1541 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1542 | |
e919464b | 1543 | *desc_addr_p = addr = dt.address + index * 8; |
7b105ca2 TY |
1544 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, |
1545 | &ctxt->exception); | |
dde7e6d1 | 1546 | } |
ef65c889 | 1547 | |
dde7e6d1 AK |
1548 | /* allowed just for 8 bytes segments */ |
1549 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1550 | u16 selector, struct desc_struct *desc) |
1551 | { | |
1552 | struct desc_ptr dt; | |
1553 | u16 index = selector >> 3; | |
dde7e6d1 | 1554 | ulong addr; |
6aa8b732 | 1555 | |
7b105ca2 | 1556 | get_descriptor_table_ptr(ctxt, selector, &dt); |
6e3d5dfb | 1557 | |
35d3d4a1 AK |
1558 | if (dt.size < index * 8 + 7) |
1559 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1560 | |
dde7e6d1 | 1561 | addr = dt.address + index * 8; |
7b105ca2 TY |
1562 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1563 | &ctxt->exception); | |
dde7e6d1 | 1564 | } |
c7e75a3d | 1565 | |
5601d05b | 1566 | /* Does not support long mode */ |
dde7e6d1 | 1567 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1568 | u16 selector, int seg) |
1569 | { | |
869be99c | 1570 | struct desc_struct seg_desc, old_desc; |
dde7e6d1 AK |
1571 | u8 dpl, rpl, cpl; |
1572 | unsigned err_vec = GP_VECTOR; | |
1573 | u32 err_code = 0; | |
1574 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
e919464b | 1575 | ulong desc_addr; |
dde7e6d1 | 1576 | int ret; |
03ebebeb | 1577 | u16 dummy; |
69f55cb1 | 1578 | |
dde7e6d1 | 1579 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1580 | |
f8da94e9 KW |
1581 | if (ctxt->mode == X86EMUL_MODE_REAL) { |
1582 | /* set real mode segment descriptor (keep limit etc. for | |
1583 | * unreal mode) */ | |
03ebebeb | 1584 | ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); |
dde7e6d1 | 1585 | set_desc_base(&seg_desc, selector << 4); |
dde7e6d1 | 1586 | goto load; |
f8da94e9 KW |
1587 | } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { |
1588 | /* VM86 needs a clean new segment descriptor */ | |
1589 | set_desc_base(&seg_desc, selector << 4); | |
1590 | set_desc_limit(&seg_desc, 0xffff); | |
1591 | seg_desc.type = 3; | |
1592 | seg_desc.p = 1; | |
1593 | seg_desc.s = 1; | |
1594 | seg_desc.dpl = 3; | |
1595 | goto load; | |
dde7e6d1 AK |
1596 | } |
1597 | ||
79d5b4c3 AK |
1598 | rpl = selector & 3; |
1599 | cpl = ctxt->ops->cpl(ctxt); | |
1600 | ||
1601 | /* NULL selector is not valid for TR, CS and SS (except for long mode) */ | |
1602 | if ((seg == VCPU_SREG_CS | |
1603 | || (seg == VCPU_SREG_SS | |
1604 | && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) | |
1605 | || seg == VCPU_SREG_TR) | |
dde7e6d1 AK |
1606 | && null_selector) |
1607 | goto exception; | |
1608 | ||
1609 | /* TR should be in GDT only */ | |
1610 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1611 | goto exception; | |
1612 | ||
1613 | if (null_selector) /* for NULL selector skip all following checks */ | |
1614 | goto load; | |
1615 | ||
e919464b | 1616 | ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); |
dde7e6d1 AK |
1617 | if (ret != X86EMUL_CONTINUE) |
1618 | return ret; | |
1619 | ||
1620 | err_code = selector & 0xfffc; | |
1621 | err_vec = GP_VECTOR; | |
1622 | ||
fc058680 | 1623 | /* can't load system descriptor into segment selector */ |
dde7e6d1 AK |
1624 | if (seg <= VCPU_SREG_GS && !seg_desc.s) |
1625 | goto exception; | |
1626 | ||
1627 | if (!seg_desc.p) { | |
1628 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1629 | goto exception; | |
1630 | } | |
1631 | ||
dde7e6d1 | 1632 | dpl = seg_desc.dpl; |
dde7e6d1 AK |
1633 | |
1634 | switch (seg) { | |
1635 | case VCPU_SREG_SS: | |
1636 | /* | |
1637 | * segment is not a writable data segment or segment | |
1638 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1639 | */ | |
1640 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1641 | goto exception; | |
6aa8b732 | 1642 | break; |
dde7e6d1 AK |
1643 | case VCPU_SREG_CS: |
1644 | if (!(seg_desc.type & 8)) | |
1645 | goto exception; | |
1646 | ||
1647 | if (seg_desc.type & 4) { | |
1648 | /* conforming */ | |
1649 | if (dpl > cpl) | |
1650 | goto exception; | |
1651 | } else { | |
1652 | /* nonconforming */ | |
1653 | if (rpl > cpl || dpl != cpl) | |
1654 | goto exception; | |
1655 | } | |
1656 | /* CS(RPL) <- CPL */ | |
1657 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1658 | break; |
dde7e6d1 AK |
1659 | case VCPU_SREG_TR: |
1660 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1661 | goto exception; | |
869be99c AK |
1662 | old_desc = seg_desc; |
1663 | seg_desc.type |= 2; /* busy */ | |
1664 | ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, | |
1665 | sizeof(seg_desc), &ctxt->exception); | |
1666 | if (ret != X86EMUL_CONTINUE) | |
1667 | return ret; | |
dde7e6d1 AK |
1668 | break; |
1669 | case VCPU_SREG_LDTR: | |
1670 | if (seg_desc.s || seg_desc.type != 2) | |
1671 | goto exception; | |
1672 | break; | |
1673 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1674 | /* |
dde7e6d1 AK |
1675 | * segment is not a data or readable code segment or |
1676 | * ((segment is a data or nonconforming code segment) | |
1677 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1678 | */ |
dde7e6d1 AK |
1679 | if ((seg_desc.type & 0xa) == 0x8 || |
1680 | (((seg_desc.type & 0xc) != 0xc) && | |
1681 | (rpl > dpl && cpl > dpl))) | |
1682 | goto exception; | |
6aa8b732 | 1683 | break; |
dde7e6d1 AK |
1684 | } |
1685 | ||
1686 | if (seg_desc.s) { | |
1687 | /* mark segment as accessed */ | |
1688 | seg_desc.type |= 1; | |
7b105ca2 | 1689 | ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1690 | if (ret != X86EMUL_CONTINUE) |
1691 | return ret; | |
1692 | } | |
1693 | load: | |
7b105ca2 | 1694 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); |
dde7e6d1 AK |
1695 | return X86EMUL_CONTINUE; |
1696 | exception: | |
1697 | emulate_exception(ctxt, err_vec, err_code, true); | |
1698 | return X86EMUL_PROPAGATE_FAULT; | |
1699 | } | |
1700 | ||
31be40b3 WY |
1701 | static void write_register_operand(struct operand *op) |
1702 | { | |
1703 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1704 | switch (op->bytes) { | |
1705 | case 1: | |
1706 | *(u8 *)op->addr.reg = (u8)op->val; | |
1707 | break; | |
1708 | case 2: | |
1709 | *(u16 *)op->addr.reg = (u16)op->val; | |
1710 | break; | |
1711 | case 4: | |
1712 | *op->addr.reg = (u32)op->val; | |
1713 | break; /* 64b: zero-extend */ | |
1714 | case 8: | |
1715 | *op->addr.reg = op->val; | |
1716 | break; | |
1717 | } | |
1718 | } | |
1719 | ||
adddcecf | 1720 | static int writeback(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 AK |
1721 | { |
1722 | int rc; | |
dde7e6d1 | 1723 | |
b6744dc3 AK |
1724 | if (ctxt->d & NoWrite) |
1725 | return X86EMUL_CONTINUE; | |
1726 | ||
9dac77fa | 1727 | switch (ctxt->dst.type) { |
dde7e6d1 | 1728 | case OP_REG: |
9dac77fa | 1729 | write_register_operand(&ctxt->dst); |
6aa8b732 | 1730 | break; |
dde7e6d1 | 1731 | case OP_MEM: |
9dac77fa | 1732 | if (ctxt->lock_prefix) |
3ca3ac4d | 1733 | rc = segmented_cmpxchg(ctxt, |
9dac77fa AK |
1734 | ctxt->dst.addr.mem, |
1735 | &ctxt->dst.orig_val, | |
1736 | &ctxt->dst.val, | |
1737 | ctxt->dst.bytes); | |
341de7e3 | 1738 | else |
3ca3ac4d | 1739 | rc = segmented_write(ctxt, |
9dac77fa AK |
1740 | ctxt->dst.addr.mem, |
1741 | &ctxt->dst.val, | |
1742 | ctxt->dst.bytes); | |
dde7e6d1 AK |
1743 | if (rc != X86EMUL_CONTINUE) |
1744 | return rc; | |
a682e354 | 1745 | break; |
b3356bf0 GN |
1746 | case OP_MEM_STR: |
1747 | rc = segmented_write(ctxt, | |
1748 | ctxt->dst.addr.mem, | |
1749 | ctxt->dst.data, | |
1750 | ctxt->dst.bytes * ctxt->dst.count); | |
1751 | if (rc != X86EMUL_CONTINUE) | |
1752 | return rc; | |
1753 | break; | |
1253791d | 1754 | case OP_XMM: |
9dac77fa | 1755 | write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); |
1253791d | 1756 | break; |
cbe2c9d3 AK |
1757 | case OP_MM: |
1758 | write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm); | |
1759 | break; | |
dde7e6d1 AK |
1760 | case OP_NONE: |
1761 | /* no writeback */ | |
414e6277 | 1762 | break; |
dde7e6d1 | 1763 | default: |
414e6277 | 1764 | break; |
6aa8b732 | 1765 | } |
dde7e6d1 AK |
1766 | return X86EMUL_CONTINUE; |
1767 | } | |
6aa8b732 | 1768 | |
51ddff50 | 1769 | static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) |
dde7e6d1 | 1770 | { |
4179bb02 | 1771 | struct segmented_address addr; |
0dc8d10f | 1772 | |
5ad105e5 | 1773 | rsp_increment(ctxt, -bytes); |
dd856efa | 1774 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
4179bb02 TY |
1775 | addr.seg = VCPU_SREG_SS; |
1776 | ||
51ddff50 AK |
1777 | return segmented_write(ctxt, addr, data, bytes); |
1778 | } | |
1779 | ||
1780 | static int em_push(struct x86_emulate_ctxt *ctxt) | |
1781 | { | |
4179bb02 | 1782 | /* Disable writeback. */ |
9dac77fa | 1783 | ctxt->dst.type = OP_NONE; |
51ddff50 | 1784 | return push(ctxt, &ctxt->src.val, ctxt->op_bytes); |
dde7e6d1 | 1785 | } |
69f55cb1 | 1786 | |
dde7e6d1 | 1787 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1788 | void *dest, int len) |
1789 | { | |
dde7e6d1 | 1790 | int rc; |
90de84f5 | 1791 | struct segmented_address addr; |
8b4caf66 | 1792 | |
dd856efa | 1793 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
90de84f5 | 1794 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1795 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1796 | if (rc != X86EMUL_CONTINUE) |
1797 | return rc; | |
1798 | ||
5ad105e5 | 1799 | rsp_increment(ctxt, len); |
dde7e6d1 | 1800 | return rc; |
8b4caf66 LV |
1801 | } |
1802 | ||
c54fe504 TY |
1803 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1804 | { | |
9dac77fa | 1805 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1806 | } |
1807 | ||
dde7e6d1 | 1808 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1809 | void *dest, int len) |
9de41573 GN |
1810 | { |
1811 | int rc; | |
dde7e6d1 AK |
1812 | unsigned long val, change_mask; |
1813 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1814 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1815 | |
3b9be3bf | 1816 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1817 | if (rc != X86EMUL_CONTINUE) |
1818 | return rc; | |
9de41573 | 1819 | |
dde7e6d1 AK |
1820 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1821 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1822 | |
dde7e6d1 AK |
1823 | switch(ctxt->mode) { |
1824 | case X86EMUL_MODE_PROT64: | |
1825 | case X86EMUL_MODE_PROT32: | |
1826 | case X86EMUL_MODE_PROT16: | |
1827 | if (cpl == 0) | |
1828 | change_mask |= EFLG_IOPL; | |
1829 | if (cpl <= iopl) | |
1830 | change_mask |= EFLG_IF; | |
1831 | break; | |
1832 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1833 | if (iopl < 3) |
1834 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1835 | change_mask |= EFLG_IF; |
1836 | break; | |
1837 | default: /* real mode */ | |
1838 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1839 | break; | |
9de41573 | 1840 | } |
dde7e6d1 AK |
1841 | |
1842 | *(unsigned long *)dest = | |
1843 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1844 | ||
1845 | return rc; | |
9de41573 GN |
1846 | } |
1847 | ||
62aaa2f0 TY |
1848 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1849 | { | |
9dac77fa AK |
1850 | ctxt->dst.type = OP_REG; |
1851 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1852 | ctxt->dst.bytes = ctxt->op_bytes; | |
1853 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1854 | } |
1855 | ||
612e89f0 AK |
1856 | static int em_enter(struct x86_emulate_ctxt *ctxt) |
1857 | { | |
1858 | int rc; | |
1859 | unsigned frame_size = ctxt->src.val; | |
1860 | unsigned nesting_level = ctxt->src2.val & 31; | |
dd856efa | 1861 | ulong rbp; |
612e89f0 AK |
1862 | |
1863 | if (nesting_level) | |
1864 | return X86EMUL_UNHANDLEABLE; | |
1865 | ||
dd856efa AK |
1866 | rbp = reg_read(ctxt, VCPU_REGS_RBP); |
1867 | rc = push(ctxt, &rbp, stack_size(ctxt)); | |
612e89f0 AK |
1868 | if (rc != X86EMUL_CONTINUE) |
1869 | return rc; | |
dd856efa | 1870 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), |
612e89f0 | 1871 | stack_mask(ctxt)); |
dd856efa AK |
1872 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), |
1873 | reg_read(ctxt, VCPU_REGS_RSP) - frame_size, | |
612e89f0 AK |
1874 | stack_mask(ctxt)); |
1875 | return X86EMUL_CONTINUE; | |
1876 | } | |
1877 | ||
f47cfa31 AK |
1878 | static int em_leave(struct x86_emulate_ctxt *ctxt) |
1879 | { | |
dd856efa | 1880 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), |
f47cfa31 | 1881 | stack_mask(ctxt)); |
dd856efa | 1882 | return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); |
f47cfa31 AK |
1883 | } |
1884 | ||
1cd196ea | 1885 | static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
7b262e90 | 1886 | { |
1cd196ea AK |
1887 | int seg = ctxt->src2.val; |
1888 | ||
9dac77fa | 1889 | ctxt->src.val = get_segment_selector(ctxt, seg); |
7b262e90 | 1890 | |
4487b3b4 | 1891 | return em_push(ctxt); |
7b262e90 GN |
1892 | } |
1893 | ||
1cd196ea | 1894 | static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1895 | { |
1cd196ea | 1896 | int seg = ctxt->src2.val; |
dde7e6d1 AK |
1897 | unsigned long selector; |
1898 | int rc; | |
38ba30ba | 1899 | |
9dac77fa | 1900 | rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
dde7e6d1 AK |
1901 | if (rc != X86EMUL_CONTINUE) |
1902 | return rc; | |
1903 | ||
7b105ca2 | 1904 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1905 | return rc; |
38ba30ba GN |
1906 | } |
1907 | ||
b96a7fad | 1908 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1909 | { |
dd856efa | 1910 | unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); |
dde7e6d1 AK |
1911 | int rc = X86EMUL_CONTINUE; |
1912 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1913 | |
dde7e6d1 AK |
1914 | while (reg <= VCPU_REGS_RDI) { |
1915 | (reg == VCPU_REGS_RSP) ? | |
dd856efa | 1916 | (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); |
38ba30ba | 1917 | |
4487b3b4 | 1918 | rc = em_push(ctxt); |
dde7e6d1 AK |
1919 | if (rc != X86EMUL_CONTINUE) |
1920 | return rc; | |
38ba30ba | 1921 | |
dde7e6d1 | 1922 | ++reg; |
38ba30ba | 1923 | } |
38ba30ba | 1924 | |
dde7e6d1 | 1925 | return rc; |
38ba30ba GN |
1926 | } |
1927 | ||
62aaa2f0 TY |
1928 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1929 | { | |
9dac77fa | 1930 | ctxt->src.val = (unsigned long)ctxt->eflags; |
62aaa2f0 TY |
1931 | return em_push(ctxt); |
1932 | } | |
1933 | ||
b96a7fad | 1934 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1935 | { |
dde7e6d1 AK |
1936 | int rc = X86EMUL_CONTINUE; |
1937 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1938 | |
dde7e6d1 AK |
1939 | while (reg >= VCPU_REGS_RAX) { |
1940 | if (reg == VCPU_REGS_RSP) { | |
5ad105e5 | 1941 | rsp_increment(ctxt, ctxt->op_bytes); |
dde7e6d1 AK |
1942 | --reg; |
1943 | } | |
38ba30ba | 1944 | |
dd856efa | 1945 | rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes); |
dde7e6d1 AK |
1946 | if (rc != X86EMUL_CONTINUE) |
1947 | break; | |
1948 | --reg; | |
38ba30ba | 1949 | } |
dde7e6d1 | 1950 | return rc; |
38ba30ba GN |
1951 | } |
1952 | ||
dd856efa | 1953 | static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1954 | { |
0225fb50 | 1955 | const struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1956 | int rc; |
6e154e56 MG |
1957 | struct desc_ptr dt; |
1958 | gva_t cs_addr; | |
1959 | gva_t eip_addr; | |
1960 | u16 cs, eip; | |
6e154e56 MG |
1961 | |
1962 | /* TODO: Add limit checks */ | |
9dac77fa | 1963 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1964 | rc = em_push(ctxt); |
5c56e1cf AK |
1965 | if (rc != X86EMUL_CONTINUE) |
1966 | return rc; | |
6e154e56 MG |
1967 | |
1968 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1969 | ||
9dac77fa | 1970 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1971 | rc = em_push(ctxt); |
5c56e1cf AK |
1972 | if (rc != X86EMUL_CONTINUE) |
1973 | return rc; | |
6e154e56 | 1974 | |
9dac77fa | 1975 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1976 | rc = em_push(ctxt); |
5c56e1cf AK |
1977 | if (rc != X86EMUL_CONTINUE) |
1978 | return rc; | |
1979 | ||
4bff1e86 | 1980 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1981 | |
1982 | eip_addr = dt.address + (irq << 2); | |
1983 | cs_addr = dt.address + (irq << 2) + 2; | |
1984 | ||
0f65dd70 | 1985 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
1986 | if (rc != X86EMUL_CONTINUE) |
1987 | return rc; | |
1988 | ||
0f65dd70 | 1989 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
1990 | if (rc != X86EMUL_CONTINUE) |
1991 | return rc; | |
1992 | ||
7b105ca2 | 1993 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
1994 | if (rc != X86EMUL_CONTINUE) |
1995 | return rc; | |
1996 | ||
9dac77fa | 1997 | ctxt->_eip = eip; |
6e154e56 MG |
1998 | |
1999 | return rc; | |
2000 | } | |
2001 | ||
dd856efa AK |
2002 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
2003 | { | |
2004 | int rc; | |
2005 | ||
2006 | invalidate_registers(ctxt); | |
2007 | rc = __emulate_int_real(ctxt, irq); | |
2008 | if (rc == X86EMUL_CONTINUE) | |
2009 | writeback_registers(ctxt); | |
2010 | return rc; | |
2011 | } | |
2012 | ||
7b105ca2 | 2013 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
2014 | { |
2015 | switch(ctxt->mode) { | |
2016 | case X86EMUL_MODE_REAL: | |
dd856efa | 2017 | return __emulate_int_real(ctxt, irq); |
6e154e56 MG |
2018 | case X86EMUL_MODE_VM86: |
2019 | case X86EMUL_MODE_PROT16: | |
2020 | case X86EMUL_MODE_PROT32: | |
2021 | case X86EMUL_MODE_PROT64: | |
2022 | default: | |
2023 | /* Protected mode interrupts unimplemented yet */ | |
2024 | return X86EMUL_UNHANDLEABLE; | |
2025 | } | |
2026 | } | |
2027 | ||
7b105ca2 | 2028 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 2029 | { |
dde7e6d1 AK |
2030 | int rc = X86EMUL_CONTINUE; |
2031 | unsigned long temp_eip = 0; | |
2032 | unsigned long temp_eflags = 0; | |
2033 | unsigned long cs = 0; | |
2034 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
2035 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
2036 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
2037 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 2038 | |
dde7e6d1 | 2039 | /* TODO: Add stack limit check */ |
38ba30ba | 2040 | |
9dac77fa | 2041 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 2042 | |
dde7e6d1 AK |
2043 | if (rc != X86EMUL_CONTINUE) |
2044 | return rc; | |
38ba30ba | 2045 | |
35d3d4a1 AK |
2046 | if (temp_eip & ~0xffff) |
2047 | return emulate_gp(ctxt, 0); | |
38ba30ba | 2048 | |
9dac77fa | 2049 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 2050 | |
dde7e6d1 AK |
2051 | if (rc != X86EMUL_CONTINUE) |
2052 | return rc; | |
38ba30ba | 2053 | |
9dac77fa | 2054 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 2055 | |
dde7e6d1 AK |
2056 | if (rc != X86EMUL_CONTINUE) |
2057 | return rc; | |
38ba30ba | 2058 | |
7b105ca2 | 2059 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 2060 | |
dde7e6d1 AK |
2061 | if (rc != X86EMUL_CONTINUE) |
2062 | return rc; | |
38ba30ba | 2063 | |
9dac77fa | 2064 | ctxt->_eip = temp_eip; |
38ba30ba | 2065 | |
38ba30ba | 2066 | |
9dac77fa | 2067 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 2068 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 2069 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
2070 | ctxt->eflags &= ~0xffff; |
2071 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 2072 | } |
dde7e6d1 AK |
2073 | |
2074 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
2075 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
2076 | ||
2077 | return rc; | |
38ba30ba GN |
2078 | } |
2079 | ||
e01991e7 | 2080 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 2081 | { |
dde7e6d1 AK |
2082 | switch(ctxt->mode) { |
2083 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 2084 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
2085 | case X86EMUL_MODE_VM86: |
2086 | case X86EMUL_MODE_PROT16: | |
2087 | case X86EMUL_MODE_PROT32: | |
2088 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 2089 | default: |
dde7e6d1 AK |
2090 | /* iret from protected mode unimplemented yet */ |
2091 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 2092 | } |
c37eda13 WY |
2093 | } |
2094 | ||
d2f62766 TY |
2095 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
2096 | { | |
d2f62766 TY |
2097 | int rc; |
2098 | unsigned short sel; | |
2099 | ||
9dac77fa | 2100 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 2101 | |
7b105ca2 | 2102 | rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); |
d2f62766 TY |
2103 | if (rc != X86EMUL_CONTINUE) |
2104 | return rc; | |
2105 | ||
9dac77fa AK |
2106 | ctxt->_eip = 0; |
2107 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
d2f62766 TY |
2108 | return X86EMUL_CONTINUE; |
2109 | } | |
2110 | ||
3329ece1 AK |
2111 | static int em_mul_ex(struct x86_emulate_ctxt *ctxt) |
2112 | { | |
2113 | u8 ex = 0; | |
2114 | ||
2115 | emulate_1op_rax_rdx(ctxt, "mul", ex); | |
2116 | return X86EMUL_CONTINUE; | |
2117 | } | |
2118 | ||
2119 | static int em_imul_ex(struct x86_emulate_ctxt *ctxt) | |
2120 | { | |
2121 | u8 ex = 0; | |
2122 | ||
2123 | emulate_1op_rax_rdx(ctxt, "imul", ex); | |
2124 | return X86EMUL_CONTINUE; | |
2125 | } | |
2126 | ||
2127 | static int em_div_ex(struct x86_emulate_ctxt *ctxt) | |
8cdbd2c9 | 2128 | { |
34d1f490 | 2129 | u8 de = 0; |
8cdbd2c9 | 2130 | |
3329ece1 AK |
2131 | emulate_1op_rax_rdx(ctxt, "div", de); |
2132 | if (de) | |
2133 | return emulate_de(ctxt); | |
2134 | return X86EMUL_CONTINUE; | |
2135 | } | |
2136 | ||
2137 | static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) | |
2138 | { | |
2139 | u8 de = 0; | |
2140 | ||
2141 | emulate_1op_rax_rdx(ctxt, "idiv", de); | |
34d1f490 AK |
2142 | if (de) |
2143 | return emulate_de(ctxt); | |
8c5eee30 | 2144 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
2145 | } |
2146 | ||
51187683 | 2147 | static int em_grp45(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 2148 | { |
4179bb02 | 2149 | int rc = X86EMUL_CONTINUE; |
8cdbd2c9 | 2150 | |
9dac77fa | 2151 | switch (ctxt->modrm_reg) { |
d19292e4 MG |
2152 | case 2: /* call near abs */ { |
2153 | long int old_eip; | |
9dac77fa AK |
2154 | old_eip = ctxt->_eip; |
2155 | ctxt->_eip = ctxt->src.val; | |
2156 | ctxt->src.val = old_eip; | |
4487b3b4 | 2157 | rc = em_push(ctxt); |
d19292e4 MG |
2158 | break; |
2159 | } | |
8cdbd2c9 | 2160 | case 4: /* jmp abs */ |
9dac77fa | 2161 | ctxt->_eip = ctxt->src.val; |
8cdbd2c9 | 2162 | break; |
d2f62766 TY |
2163 | case 5: /* jmp far */ |
2164 | rc = em_jmp_far(ctxt); | |
2165 | break; | |
8cdbd2c9 | 2166 | case 6: /* push */ |
4487b3b4 | 2167 | rc = em_push(ctxt); |
8cdbd2c9 | 2168 | break; |
8cdbd2c9 | 2169 | } |
4179bb02 | 2170 | return rc; |
8cdbd2c9 LV |
2171 | } |
2172 | ||
e0dac408 | 2173 | static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 2174 | { |
9dac77fa | 2175 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 2176 | |
dd856efa AK |
2177 | if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || |
2178 | ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { | |
2179 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); | |
2180 | *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); | |
05f086f8 | 2181 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 2182 | } else { |
dd856efa AK |
2183 | ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | |
2184 | (u32) reg_read(ctxt, VCPU_REGS_RBX); | |
8cdbd2c9 | 2185 | |
05f086f8 | 2186 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 2187 | } |
1b30eaa8 | 2188 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
2189 | } |
2190 | ||
ebda02c2 TY |
2191 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
2192 | { | |
9dac77fa AK |
2193 | ctxt->dst.type = OP_REG; |
2194 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2195 | ctxt->dst.bytes = ctxt->op_bytes; | |
ebda02c2 TY |
2196 | return em_pop(ctxt); |
2197 | } | |
2198 | ||
e01991e7 | 2199 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 2200 | { |
a77ab5ea AK |
2201 | int rc; |
2202 | unsigned long cs; | |
2203 | ||
9dac77fa | 2204 | rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); |
1b30eaa8 | 2205 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2206 | return rc; |
9dac77fa AK |
2207 | if (ctxt->op_bytes == 4) |
2208 | ctxt->_eip = (u32)ctxt->_eip; | |
2209 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); | |
1b30eaa8 | 2210 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2211 | return rc; |
7b105ca2 | 2212 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
2213 | return rc; |
2214 | } | |
2215 | ||
e940b5c2 TY |
2216 | static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
2217 | { | |
2218 | /* Save real source value, then compare EAX against destination. */ | |
2219 | ctxt->src.orig_val = ctxt->src.val; | |
dd856efa | 2220 | ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX); |
158de57f | 2221 | fastop(ctxt, em_cmp); |
e940b5c2 TY |
2222 | |
2223 | if (ctxt->eflags & EFLG_ZF) { | |
2224 | /* Success: write back to memory. */ | |
2225 | ctxt->dst.val = ctxt->src.orig_val; | |
2226 | } else { | |
2227 | /* Failure: write the value we saw to EAX. */ | |
2228 | ctxt->dst.type = OP_REG; | |
dd856efa | 2229 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
e940b5c2 TY |
2230 | } |
2231 | return X86EMUL_CONTINUE; | |
2232 | } | |
2233 | ||
d4b4325f | 2234 | static int em_lseg(struct x86_emulate_ctxt *ctxt) |
09b5f4d3 | 2235 | { |
d4b4325f | 2236 | int seg = ctxt->src2.val; |
09b5f4d3 WY |
2237 | unsigned short sel; |
2238 | int rc; | |
2239 | ||
9dac77fa | 2240 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 2241 | |
7b105ca2 | 2242 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
2243 | if (rc != X86EMUL_CONTINUE) |
2244 | return rc; | |
2245 | ||
9dac77fa | 2246 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
2247 | return rc; |
2248 | } | |
2249 | ||
7b105ca2 | 2250 | static void |
e66bb2cc | 2251 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 2252 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 2253 | { |
e66bb2cc | 2254 | cs->l = 0; /* will be adjusted later */ |
79168fd1 | 2255 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 2256 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 2257 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
2258 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
2259 | cs->s = 1; | |
2260 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
2261 | cs->p = 1; |
2262 | cs->d = 1; | |
99245b50 | 2263 | cs->avl = 0; |
e66bb2cc | 2264 | |
79168fd1 GN |
2265 | set_desc_base(ss, 0); /* flat segment */ |
2266 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
2267 | ss->g = 1; /* 4kb granularity */ |
2268 | ss->s = 1; | |
2269 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 2270 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 2271 | ss->dpl = 0; |
79168fd1 | 2272 | ss->p = 1; |
99245b50 GN |
2273 | ss->l = 0; |
2274 | ss->avl = 0; | |
e66bb2cc AP |
2275 | } |
2276 | ||
1a18a69b AK |
2277 | static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
2278 | { | |
2279 | u32 eax, ebx, ecx, edx; | |
2280 | ||
2281 | eax = ecx = 0; | |
0017f93a AK |
2282 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2283 | return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx | |
1a18a69b AK |
2284 | && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx |
2285 | && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; | |
2286 | } | |
2287 | ||
c2226fc9 SB |
2288 | static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
2289 | { | |
0225fb50 | 2290 | const struct x86_emulate_ops *ops = ctxt->ops; |
c2226fc9 SB |
2291 | u32 eax, ebx, ecx, edx; |
2292 | ||
2293 | /* | |
2294 | * syscall should always be enabled in longmode - so only become | |
2295 | * vendor specific (cpuid) if other modes are active... | |
2296 | */ | |
2297 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2298 | return true; | |
2299 | ||
2300 | eax = 0x00000000; | |
2301 | ecx = 0x00000000; | |
0017f93a AK |
2302 | ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2303 | /* | |
2304 | * Intel ("GenuineIntel") | |
2305 | * remark: Intel CPUs only support "syscall" in 64bit | |
2306 | * longmode. Also an 64bit guest with a | |
2307 | * 32bit compat-app running will #UD !! While this | |
2308 | * behaviour can be fixed (by emulating) into AMD | |
2309 | * response - CPUs of AMD can't behave like Intel. | |
2310 | */ | |
2311 | if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
2312 | ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
2313 | edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
2314 | return false; | |
2315 | ||
2316 | /* AMD ("AuthenticAMD") */ | |
2317 | if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
2318 | ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
2319 | edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
2320 | return true; | |
2321 | ||
2322 | /* AMD ("AMDisbetter!") */ | |
2323 | if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
2324 | ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
2325 | edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
2326 | return true; | |
c2226fc9 SB |
2327 | |
2328 | /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
2329 | return false; | |
2330 | } | |
2331 | ||
e01991e7 | 2332 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 2333 | { |
0225fb50 | 2334 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2335 | struct desc_struct cs, ss; |
e66bb2cc | 2336 | u64 msr_data; |
79168fd1 | 2337 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2338 | u64 efer = 0; |
e66bb2cc AP |
2339 | |
2340 | /* syscall is not available in real mode */ | |
2e901c4c | 2341 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
2342 | ctxt->mode == X86EMUL_MODE_VM86) |
2343 | return emulate_ud(ctxt); | |
e66bb2cc | 2344 | |
c2226fc9 SB |
2345 | if (!(em_syscall_is_enabled(ctxt))) |
2346 | return emulate_ud(ctxt); | |
2347 | ||
c2ad2bb3 | 2348 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 2349 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 2350 | |
c2226fc9 SB |
2351 | if (!(efer & EFER_SCE)) |
2352 | return emulate_ud(ctxt); | |
2353 | ||
717746e3 | 2354 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 2355 | msr_data >>= 32; |
79168fd1 GN |
2356 | cs_sel = (u16)(msr_data & 0xfffc); |
2357 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 2358 | |
c2ad2bb3 | 2359 | if (efer & EFER_LMA) { |
79168fd1 | 2360 | cs.d = 0; |
e66bb2cc AP |
2361 | cs.l = 1; |
2362 | } | |
1aa36616 AK |
2363 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2364 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 2365 | |
dd856efa | 2366 | *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; |
c2ad2bb3 | 2367 | if (efer & EFER_LMA) { |
e66bb2cc | 2368 | #ifdef CONFIG_X86_64 |
dd856efa | 2369 | *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF; |
e66bb2cc | 2370 | |
717746e3 | 2371 | ops->get_msr(ctxt, |
3fb1b5db GN |
2372 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
2373 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 2374 | ctxt->_eip = msr_data; |
e66bb2cc | 2375 | |
717746e3 | 2376 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
2377 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
2378 | #endif | |
2379 | } else { | |
2380 | /* legacy mode */ | |
717746e3 | 2381 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 2382 | ctxt->_eip = (u32)msr_data; |
e66bb2cc AP |
2383 | |
2384 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
2385 | } | |
2386 | ||
e54cfa97 | 2387 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2388 | } |
2389 | ||
e01991e7 | 2390 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 2391 | { |
0225fb50 | 2392 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2393 | struct desc_struct cs, ss; |
8c604352 | 2394 | u64 msr_data; |
79168fd1 | 2395 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2396 | u64 efer = 0; |
8c604352 | 2397 | |
7b105ca2 | 2398 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 2399 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
2400 | if (ctxt->mode == X86EMUL_MODE_REAL) |
2401 | return emulate_gp(ctxt, 0); | |
8c604352 | 2402 | |
1a18a69b AK |
2403 | /* |
2404 | * Not recognized on AMD in compat mode (but is recognized in legacy | |
2405 | * mode). | |
2406 | */ | |
2407 | if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) | |
2408 | && !vendor_intel(ctxt)) | |
2409 | return emulate_ud(ctxt); | |
2410 | ||
8c604352 AP |
2411 | /* XXX sysenter/sysexit have not been tested in 64bit mode. |
2412 | * Therefore, we inject an #UD. | |
2413 | */ | |
35d3d4a1 AK |
2414 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
2415 | return emulate_ud(ctxt); | |
8c604352 | 2416 | |
7b105ca2 | 2417 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 2418 | |
717746e3 | 2419 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
2420 | switch (ctxt->mode) { |
2421 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
2422 | if ((msr_data & 0xfffc) == 0x0) |
2423 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2424 | break; |
2425 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
2426 | if (msr_data == 0x0) |
2427 | return emulate_gp(ctxt, 0); | |
8c604352 | 2428 | break; |
9d1b39a9 GN |
2429 | default: |
2430 | break; | |
8c604352 AP |
2431 | } |
2432 | ||
2433 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
2434 | cs_sel = (u16)msr_data; |
2435 | cs_sel &= ~SELECTOR_RPL_MASK; | |
2436 | ss_sel = cs_sel + 8; | |
2437 | ss_sel &= ~SELECTOR_RPL_MASK; | |
c2ad2bb3 | 2438 | if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
79168fd1 | 2439 | cs.d = 0; |
8c604352 AP |
2440 | cs.l = 1; |
2441 | } | |
2442 | ||
1aa36616 AK |
2443 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2444 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 2445 | |
717746e3 | 2446 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
9dac77fa | 2447 | ctxt->_eip = msr_data; |
8c604352 | 2448 | |
717746e3 | 2449 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
dd856efa | 2450 | *reg_write(ctxt, VCPU_REGS_RSP) = msr_data; |
8c604352 | 2451 | |
e54cfa97 | 2452 | return X86EMUL_CONTINUE; |
8c604352 AP |
2453 | } |
2454 | ||
e01991e7 | 2455 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 2456 | { |
0225fb50 | 2457 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2458 | struct desc_struct cs, ss; |
4668f050 AP |
2459 | u64 msr_data; |
2460 | int usermode; | |
1249b96e | 2461 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 2462 | |
a0044755 GN |
2463 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2464 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
2465 | ctxt->mode == X86EMUL_MODE_VM86) |
2466 | return emulate_gp(ctxt, 0); | |
4668f050 | 2467 | |
7b105ca2 | 2468 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 2469 | |
9dac77fa | 2470 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
2471 | usermode = X86EMUL_MODE_PROT64; |
2472 | else | |
2473 | usermode = X86EMUL_MODE_PROT32; | |
2474 | ||
2475 | cs.dpl = 3; | |
2476 | ss.dpl = 3; | |
717746e3 | 2477 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2478 | switch (usermode) { |
2479 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2480 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
2481 | if ((msr_data & 0xfffc) == 0x0) |
2482 | return emulate_gp(ctxt, 0); | |
79168fd1 | 2483 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2484 | break; |
2485 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2486 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2487 | if (msr_data == 0x0) |
2488 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2489 | ss_sel = cs_sel + 8; |
2490 | cs.d = 0; | |
4668f050 AP |
2491 | cs.l = 1; |
2492 | break; | |
2493 | } | |
79168fd1 GN |
2494 | cs_sel |= SELECTOR_RPL_MASK; |
2495 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2496 | |
1aa36616 AK |
2497 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2498 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2499 | |
dd856efa AK |
2500 | ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX); |
2501 | *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX); | |
4668f050 | 2502 | |
e54cfa97 | 2503 | return X86EMUL_CONTINUE; |
4668f050 AP |
2504 | } |
2505 | ||
7b105ca2 | 2506 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2507 | { |
2508 | int iopl; | |
2509 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2510 | return false; | |
2511 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2512 | return true; | |
2513 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2514 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2515 | } |
2516 | ||
2517 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2518 | u16 port, u16 len) |
2519 | { | |
0225fb50 | 2520 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2521 | struct desc_struct tr_seg; |
5601d05b | 2522 | u32 base3; |
f850e2e6 | 2523 | int r; |
1aa36616 | 2524 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2525 | unsigned mask = (1 << len) - 1; |
5601d05b | 2526 | unsigned long base; |
f850e2e6 | 2527 | |
1aa36616 | 2528 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2529 | if (!tr_seg.p) |
f850e2e6 | 2530 | return false; |
79168fd1 | 2531 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2532 | return false; |
5601d05b GN |
2533 | base = get_desc_base(&tr_seg); |
2534 | #ifdef CONFIG_X86_64 | |
2535 | base |= ((u64)base3) << 32; | |
2536 | #endif | |
0f65dd70 | 2537 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2538 | if (r != X86EMUL_CONTINUE) |
2539 | return false; | |
79168fd1 | 2540 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2541 | return false; |
0f65dd70 | 2542 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2543 | if (r != X86EMUL_CONTINUE) |
2544 | return false; | |
2545 | if ((perm >> bit_idx) & mask) | |
2546 | return false; | |
2547 | return true; | |
2548 | } | |
2549 | ||
2550 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2551 | u16 port, u16 len) |
2552 | { | |
4fc40f07 GN |
2553 | if (ctxt->perm_ok) |
2554 | return true; | |
2555 | ||
7b105ca2 TY |
2556 | if (emulator_bad_iopl(ctxt)) |
2557 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2558 | return false; |
4fc40f07 GN |
2559 | |
2560 | ctxt->perm_ok = true; | |
2561 | ||
f850e2e6 GN |
2562 | return true; |
2563 | } | |
2564 | ||
38ba30ba | 2565 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2566 | struct tss_segment_16 *tss) |
2567 | { | |
9dac77fa | 2568 | tss->ip = ctxt->_eip; |
38ba30ba | 2569 | tss->flag = ctxt->eflags; |
dd856efa AK |
2570 | tss->ax = reg_read(ctxt, VCPU_REGS_RAX); |
2571 | tss->cx = reg_read(ctxt, VCPU_REGS_RCX); | |
2572 | tss->dx = reg_read(ctxt, VCPU_REGS_RDX); | |
2573 | tss->bx = reg_read(ctxt, VCPU_REGS_RBX); | |
2574 | tss->sp = reg_read(ctxt, VCPU_REGS_RSP); | |
2575 | tss->bp = reg_read(ctxt, VCPU_REGS_RBP); | |
2576 | tss->si = reg_read(ctxt, VCPU_REGS_RSI); | |
2577 | tss->di = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2578 | |
1aa36616 AK |
2579 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2580 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2581 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2582 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2583 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2584 | } |
2585 | ||
2586 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2587 | struct tss_segment_16 *tss) |
2588 | { | |
38ba30ba GN |
2589 | int ret; |
2590 | ||
9dac77fa | 2591 | ctxt->_eip = tss->ip; |
38ba30ba | 2592 | ctxt->eflags = tss->flag | 2; |
dd856efa AK |
2593 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; |
2594 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; | |
2595 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; | |
2596 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; | |
2597 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; | |
2598 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; | |
2599 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; | |
2600 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; | |
38ba30ba GN |
2601 | |
2602 | /* | |
2603 | * SDM says that segment selectors are loaded before segment | |
2604 | * descriptors | |
2605 | */ | |
1aa36616 AK |
2606 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2607 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2608 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2609 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2610 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba GN |
2611 | |
2612 | /* | |
fc058680 | 2613 | * Now load segment descriptors. If fault happens at this stage |
38ba30ba GN |
2614 | * it is handled in a context of new task |
2615 | */ | |
7b105ca2 | 2616 | ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); |
38ba30ba GN |
2617 | if (ret != X86EMUL_CONTINUE) |
2618 | return ret; | |
7b105ca2 | 2619 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2620 | if (ret != X86EMUL_CONTINUE) |
2621 | return ret; | |
7b105ca2 | 2622 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2623 | if (ret != X86EMUL_CONTINUE) |
2624 | return ret; | |
7b105ca2 | 2625 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2626 | if (ret != X86EMUL_CONTINUE) |
2627 | return ret; | |
7b105ca2 | 2628 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2629 | if (ret != X86EMUL_CONTINUE) |
2630 | return ret; | |
2631 | ||
2632 | return X86EMUL_CONTINUE; | |
2633 | } | |
2634 | ||
2635 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2636 | u16 tss_selector, u16 old_tss_sel, |
2637 | ulong old_tss_base, struct desc_struct *new_desc) | |
2638 | { | |
0225fb50 | 2639 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2640 | struct tss_segment_16 tss_seg; |
2641 | int ret; | |
bcc55cba | 2642 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2643 | |
0f65dd70 | 2644 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2645 | &ctxt->exception); |
db297e3d | 2646 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2647 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2648 | return ret; |
38ba30ba | 2649 | |
7b105ca2 | 2650 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2651 | |
0f65dd70 | 2652 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2653 | &ctxt->exception); |
db297e3d | 2654 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2655 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2656 | return ret; |
38ba30ba | 2657 | |
0f65dd70 | 2658 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2659 | &ctxt->exception); |
db297e3d | 2660 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2661 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2662 | return ret; |
38ba30ba GN |
2663 | |
2664 | if (old_tss_sel != 0xffff) { | |
2665 | tss_seg.prev_task_link = old_tss_sel; | |
2666 | ||
0f65dd70 | 2667 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2668 | &tss_seg.prev_task_link, |
2669 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2670 | &ctxt->exception); |
db297e3d | 2671 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2672 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2673 | return ret; |
38ba30ba GN |
2674 | } |
2675 | ||
7b105ca2 | 2676 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2677 | } |
2678 | ||
2679 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2680 | struct tss_segment_32 *tss) |
2681 | { | |
7b105ca2 | 2682 | tss->cr3 = ctxt->ops->get_cr(ctxt, 3); |
9dac77fa | 2683 | tss->eip = ctxt->_eip; |
38ba30ba | 2684 | tss->eflags = ctxt->eflags; |
dd856efa AK |
2685 | tss->eax = reg_read(ctxt, VCPU_REGS_RAX); |
2686 | tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
2687 | tss->edx = reg_read(ctxt, VCPU_REGS_RDX); | |
2688 | tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); | |
2689 | tss->esp = reg_read(ctxt, VCPU_REGS_RSP); | |
2690 | tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); | |
2691 | tss->esi = reg_read(ctxt, VCPU_REGS_RSI); | |
2692 | tss->edi = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2693 | |
1aa36616 AK |
2694 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2695 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2696 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2697 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2698 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2699 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
2700 | tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2701 | } |
2702 | ||
2703 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2704 | struct tss_segment_32 *tss) |
2705 | { | |
38ba30ba GN |
2706 | int ret; |
2707 | ||
7b105ca2 | 2708 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2709 | return emulate_gp(ctxt, 0); |
9dac77fa | 2710 | ctxt->_eip = tss->eip; |
38ba30ba | 2711 | ctxt->eflags = tss->eflags | 2; |
4cee4798 KW |
2712 | |
2713 | /* General purpose registers */ | |
dd856efa AK |
2714 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; |
2715 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; | |
2716 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; | |
2717 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; | |
2718 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; | |
2719 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; | |
2720 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; | |
2721 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; | |
38ba30ba GN |
2722 | |
2723 | /* | |
2724 | * SDM says that segment selectors are loaded before segment | |
2725 | * descriptors | |
2726 | */ | |
1aa36616 AK |
2727 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2728 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2729 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2730 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2731 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2732 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2733 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba | 2734 | |
4cee4798 KW |
2735 | /* |
2736 | * If we're switching between Protected Mode and VM86, we need to make | |
2737 | * sure to update the mode before loading the segment descriptors so | |
2738 | * that the selectors are interpreted correctly. | |
2739 | * | |
2740 | * Need to get rflags to the vcpu struct immediately because it | |
2741 | * influences the CPL which is checked at least when loading the segment | |
2742 | * descriptors and when pushing an error code to the new kernel stack. | |
2743 | * | |
2744 | * TODO Introduce a separate ctxt->ops->set_cpl callback | |
2745 | */ | |
2746 | if (ctxt->eflags & X86_EFLAGS_VM) | |
2747 | ctxt->mode = X86EMUL_MODE_VM86; | |
2748 | else | |
2749 | ctxt->mode = X86EMUL_MODE_PROT32; | |
2750 | ||
2751 | ctxt->ops->set_rflags(ctxt, ctxt->eflags); | |
2752 | ||
38ba30ba GN |
2753 | /* |
2754 | * Now load segment descriptors. If fault happenes at this stage | |
2755 | * it is handled in a context of new task | |
2756 | */ | |
7b105ca2 | 2757 | ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
38ba30ba GN |
2758 | if (ret != X86EMUL_CONTINUE) |
2759 | return ret; | |
7b105ca2 | 2760 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2761 | if (ret != X86EMUL_CONTINUE) |
2762 | return ret; | |
7b105ca2 | 2763 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2764 | if (ret != X86EMUL_CONTINUE) |
2765 | return ret; | |
7b105ca2 | 2766 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2767 | if (ret != X86EMUL_CONTINUE) |
2768 | return ret; | |
7b105ca2 | 2769 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2770 | if (ret != X86EMUL_CONTINUE) |
2771 | return ret; | |
7b105ca2 | 2772 | ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); |
38ba30ba GN |
2773 | if (ret != X86EMUL_CONTINUE) |
2774 | return ret; | |
7b105ca2 | 2775 | ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); |
38ba30ba GN |
2776 | if (ret != X86EMUL_CONTINUE) |
2777 | return ret; | |
2778 | ||
2779 | return X86EMUL_CONTINUE; | |
2780 | } | |
2781 | ||
2782 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2783 | u16 tss_selector, u16 old_tss_sel, |
2784 | ulong old_tss_base, struct desc_struct *new_desc) | |
2785 | { | |
0225fb50 | 2786 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2787 | struct tss_segment_32 tss_seg; |
2788 | int ret; | |
bcc55cba | 2789 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2790 | |
0f65dd70 | 2791 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2792 | &ctxt->exception); |
db297e3d | 2793 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2794 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2795 | return ret; |
38ba30ba | 2796 | |
7b105ca2 | 2797 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2798 | |
0f65dd70 | 2799 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2800 | &ctxt->exception); |
db297e3d | 2801 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2802 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2803 | return ret; |
38ba30ba | 2804 | |
0f65dd70 | 2805 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2806 | &ctxt->exception); |
db297e3d | 2807 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2808 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2809 | return ret; |
38ba30ba GN |
2810 | |
2811 | if (old_tss_sel != 0xffff) { | |
2812 | tss_seg.prev_task_link = old_tss_sel; | |
2813 | ||
0f65dd70 | 2814 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2815 | &tss_seg.prev_task_link, |
2816 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2817 | &ctxt->exception); |
db297e3d | 2818 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2819 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2820 | return ret; |
38ba30ba GN |
2821 | } |
2822 | ||
7b105ca2 | 2823 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2824 | } |
2825 | ||
2826 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2827 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2828 | bool has_error_code, u32 error_code) |
38ba30ba | 2829 | { |
0225fb50 | 2830 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2831 | struct desc_struct curr_tss_desc, next_tss_desc; |
2832 | int ret; | |
1aa36616 | 2833 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2834 | ulong old_tss_base = |
4bff1e86 | 2835 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2836 | u32 desc_limit; |
e919464b | 2837 | ulong desc_addr; |
38ba30ba GN |
2838 | |
2839 | /* FIXME: old_tss_base == ~0 ? */ | |
2840 | ||
e919464b | 2841 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); |
38ba30ba GN |
2842 | if (ret != X86EMUL_CONTINUE) |
2843 | return ret; | |
e919464b | 2844 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); |
38ba30ba GN |
2845 | if (ret != X86EMUL_CONTINUE) |
2846 | return ret; | |
2847 | ||
2848 | /* FIXME: check that next_tss_desc is tss */ | |
2849 | ||
7f3d35fd KW |
2850 | /* |
2851 | * Check privileges. The three cases are task switch caused by... | |
2852 | * | |
2853 | * 1. jmp/call/int to task gate: Check against DPL of the task gate | |
2854 | * 2. Exception/IRQ/iret: No check is performed | |
fc058680 | 2855 | * 3. jmp/call to TSS: Check against DPL of the TSS |
7f3d35fd KW |
2856 | */ |
2857 | if (reason == TASK_SWITCH_GATE) { | |
2858 | if (idt_index != -1) { | |
2859 | /* Software interrupts */ | |
2860 | struct desc_struct task_gate_desc; | |
2861 | int dpl; | |
2862 | ||
2863 | ret = read_interrupt_descriptor(ctxt, idt_index, | |
2864 | &task_gate_desc); | |
2865 | if (ret != X86EMUL_CONTINUE) | |
2866 | return ret; | |
2867 | ||
2868 | dpl = task_gate_desc.dpl; | |
2869 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2870 | return emulate_gp(ctxt, (idt_index << 3) | 0x2); | |
2871 | } | |
2872 | } else if (reason != TASK_SWITCH_IRET) { | |
2873 | int dpl = next_tss_desc.dpl; | |
2874 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2875 | return emulate_gp(ctxt, tss_selector); | |
38ba30ba GN |
2876 | } |
2877 | ||
7f3d35fd | 2878 | |
ceffb459 GN |
2879 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2880 | if (!next_tss_desc.p || | |
2881 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2882 | desc_limit < 0x2b)) { | |
54b8486f | 2883 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2884 | return X86EMUL_PROPAGATE_FAULT; |
2885 | } | |
2886 | ||
2887 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2888 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2889 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2890 | } |
2891 | ||
2892 | if (reason == TASK_SWITCH_IRET) | |
2893 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2894 | ||
2895 | /* set back link to prev task only if NT bit is set in eflags | |
fc058680 | 2896 | note that old_tss_sel is not used after this point */ |
38ba30ba GN |
2897 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) |
2898 | old_tss_sel = 0xffff; | |
2899 | ||
2900 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2901 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2902 | old_tss_base, &next_tss_desc); |
2903 | else | |
7b105ca2 | 2904 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2905 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2906 | if (ret != X86EMUL_CONTINUE) |
2907 | return ret; | |
38ba30ba GN |
2908 | |
2909 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2910 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2911 | ||
2912 | if (reason != TASK_SWITCH_IRET) { | |
2913 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2914 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2915 | } |
2916 | ||
717746e3 | 2917 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2918 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2919 | |
e269fb21 | 2920 | if (has_error_code) { |
9dac77fa AK |
2921 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2922 | ctxt->lock_prefix = 0; | |
2923 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2924 | ret = em_push(ctxt); |
e269fb21 JK |
2925 | } |
2926 | ||
38ba30ba GN |
2927 | return ret; |
2928 | } | |
2929 | ||
2930 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2931 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2932 | bool has_error_code, u32 error_code) |
38ba30ba | 2933 | { |
38ba30ba GN |
2934 | int rc; |
2935 | ||
dd856efa | 2936 | invalidate_registers(ctxt); |
9dac77fa AK |
2937 | ctxt->_eip = ctxt->eip; |
2938 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2939 | |
7f3d35fd | 2940 | rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, |
e269fb21 | 2941 | has_error_code, error_code); |
38ba30ba | 2942 | |
dd856efa | 2943 | if (rc == X86EMUL_CONTINUE) { |
9dac77fa | 2944 | ctxt->eip = ctxt->_eip; |
dd856efa AK |
2945 | writeback_registers(ctxt); |
2946 | } | |
38ba30ba | 2947 | |
a0c0ab2f | 2948 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2949 | } |
2950 | ||
f3bd64c6 GN |
2951 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, |
2952 | struct operand *op) | |
a682e354 | 2953 | { |
b3356bf0 | 2954 | int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count; |
a682e354 | 2955 | |
dd856efa AK |
2956 | register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes); |
2957 | op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg)); | |
a682e354 GN |
2958 | } |
2959 | ||
7af04fc0 AK |
2960 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2961 | { | |
7af04fc0 AK |
2962 | u8 al, old_al; |
2963 | bool af, cf, old_cf; | |
2964 | ||
2965 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2966 | al = ctxt->dst.val; |
7af04fc0 AK |
2967 | |
2968 | old_al = al; | |
2969 | old_cf = cf; | |
2970 | cf = false; | |
2971 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2972 | if ((al & 0x0f) > 9 || af) { | |
2973 | al -= 6; | |
2974 | cf = old_cf | (al >= 250); | |
2975 | af = true; | |
2976 | } else { | |
2977 | af = false; | |
2978 | } | |
2979 | if (old_al > 0x99 || old_cf) { | |
2980 | al -= 0x60; | |
2981 | cf = true; | |
2982 | } | |
2983 | ||
9dac77fa | 2984 | ctxt->dst.val = al; |
7af04fc0 | 2985 | /* Set PF, ZF, SF */ |
9dac77fa AK |
2986 | ctxt->src.type = OP_IMM; |
2987 | ctxt->src.val = 0; | |
2988 | ctxt->src.bytes = 1; | |
158de57f | 2989 | fastop(ctxt, em_or); |
7af04fc0 AK |
2990 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
2991 | if (cf) | |
2992 | ctxt->eflags |= X86_EFLAGS_CF; | |
2993 | if (af) | |
2994 | ctxt->eflags |= X86_EFLAGS_AF; | |
2995 | return X86EMUL_CONTINUE; | |
2996 | } | |
2997 | ||
7f662273 GN |
2998 | static int em_aad(struct x86_emulate_ctxt *ctxt) |
2999 | { | |
3000 | u8 al = ctxt->dst.val & 0xff; | |
3001 | u8 ah = (ctxt->dst.val >> 8) & 0xff; | |
3002 | ||
3003 | al = (al + (ah * ctxt->src.val)) & 0xff; | |
3004 | ||
3005 | ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; | |
3006 | ||
f583c29b GN |
3007 | /* Set PF, ZF, SF */ |
3008 | ctxt->src.type = OP_IMM; | |
3009 | ctxt->src.val = 0; | |
3010 | ctxt->src.bytes = 1; | |
3011 | fastop(ctxt, em_or); | |
7f662273 GN |
3012 | |
3013 | return X86EMUL_CONTINUE; | |
3014 | } | |
3015 | ||
d4ddafcd TY |
3016 | static int em_call(struct x86_emulate_ctxt *ctxt) |
3017 | { | |
3018 | long rel = ctxt->src.val; | |
3019 | ||
3020 | ctxt->src.val = (unsigned long)ctxt->_eip; | |
3021 | jmp_rel(ctxt, rel); | |
3022 | return em_push(ctxt); | |
3023 | } | |
3024 | ||
0ef753b8 AK |
3025 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
3026 | { | |
0ef753b8 AK |
3027 | u16 sel, old_cs; |
3028 | ulong old_eip; | |
3029 | int rc; | |
3030 | ||
1aa36616 | 3031 | old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
9dac77fa | 3032 | old_eip = ctxt->_eip; |
0ef753b8 | 3033 | |
9dac77fa | 3034 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
7b105ca2 | 3035 | if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) |
0ef753b8 AK |
3036 | return X86EMUL_CONTINUE; |
3037 | ||
9dac77fa AK |
3038 | ctxt->_eip = 0; |
3039 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
0ef753b8 | 3040 | |
9dac77fa | 3041 | ctxt->src.val = old_cs; |
4487b3b4 | 3042 | rc = em_push(ctxt); |
0ef753b8 AK |
3043 | if (rc != X86EMUL_CONTINUE) |
3044 | return rc; | |
3045 | ||
9dac77fa | 3046 | ctxt->src.val = old_eip; |
4487b3b4 | 3047 | return em_push(ctxt); |
0ef753b8 AK |
3048 | } |
3049 | ||
40ece7c7 AK |
3050 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
3051 | { | |
40ece7c7 AK |
3052 | int rc; |
3053 | ||
9dac77fa AK |
3054 | ctxt->dst.type = OP_REG; |
3055 | ctxt->dst.addr.reg = &ctxt->_eip; | |
3056 | ctxt->dst.bytes = ctxt->op_bytes; | |
3057 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
40ece7c7 AK |
3058 | if (rc != X86EMUL_CONTINUE) |
3059 | return rc; | |
5ad105e5 | 3060 | rsp_increment(ctxt, ctxt->src.val); |
40ece7c7 AK |
3061 | return X86EMUL_CONTINUE; |
3062 | } | |
3063 | ||
e4f973ae TY |
3064 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
3065 | { | |
e4f973ae | 3066 | /* Write back the register source. */ |
9dac77fa AK |
3067 | ctxt->src.val = ctxt->dst.val; |
3068 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
3069 | |
3070 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
3071 | ctxt->dst.val = ctxt->src.orig_val; |
3072 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
3073 | return X86EMUL_CONTINUE; |
3074 | } | |
3075 | ||
5c82aa29 AK |
3076 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
3077 | { | |
9dac77fa | 3078 | ctxt->dst.val = ctxt->src2.val; |
4d758349 | 3079 | return fastop(ctxt, em_imul); |
5c82aa29 AK |
3080 | } |
3081 | ||
61429142 AK |
3082 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
3083 | { | |
9dac77fa AK |
3084 | ctxt->dst.type = OP_REG; |
3085 | ctxt->dst.bytes = ctxt->src.bytes; | |
dd856efa | 3086 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
9dac77fa | 3087 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); |
61429142 AK |
3088 | |
3089 | return X86EMUL_CONTINUE; | |
3090 | } | |
3091 | ||
48bb5d3c AK |
3092 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
3093 | { | |
48bb5d3c AK |
3094 | u64 tsc = 0; |
3095 | ||
717746e3 | 3096 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
dd856efa AK |
3097 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; |
3098 | *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; | |
48bb5d3c AK |
3099 | return X86EMUL_CONTINUE; |
3100 | } | |
3101 | ||
222d21aa AK |
3102 | static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
3103 | { | |
3104 | u64 pmc; | |
3105 | ||
dd856efa | 3106 | if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) |
222d21aa | 3107 | return emulate_gp(ctxt, 0); |
dd856efa AK |
3108 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; |
3109 | *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; | |
222d21aa AK |
3110 | return X86EMUL_CONTINUE; |
3111 | } | |
3112 | ||
b9eac5f4 AK |
3113 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
3114 | { | |
49597d81 | 3115 | memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes); |
b9eac5f4 AK |
3116 | return X86EMUL_CONTINUE; |
3117 | } | |
3118 | ||
bc00f8d2 TY |
3119 | static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
3120 | { | |
3121 | if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) | |
3122 | return emulate_gp(ctxt, 0); | |
3123 | ||
3124 | /* Disable writeback. */ | |
3125 | ctxt->dst.type = OP_NONE; | |
3126 | return X86EMUL_CONTINUE; | |
3127 | } | |
3128 | ||
3129 | static int em_dr_write(struct x86_emulate_ctxt *ctxt) | |
3130 | { | |
3131 | unsigned long val; | |
3132 | ||
3133 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3134 | val = ctxt->src.val & ~0ULL; | |
3135 | else | |
3136 | val = ctxt->src.val & ~0U; | |
3137 | ||
3138 | /* #UD condition is already handled. */ | |
3139 | if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) | |
3140 | return emulate_gp(ctxt, 0); | |
3141 | ||
3142 | /* Disable writeback. */ | |
3143 | ctxt->dst.type = OP_NONE; | |
3144 | return X86EMUL_CONTINUE; | |
3145 | } | |
3146 | ||
e1e210b0 TY |
3147 | static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
3148 | { | |
3149 | u64 msr_data; | |
3150 | ||
dd856efa AK |
3151 | msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) |
3152 | | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); | |
3153 | if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) | |
e1e210b0 TY |
3154 | return emulate_gp(ctxt, 0); |
3155 | ||
3156 | return X86EMUL_CONTINUE; | |
3157 | } | |
3158 | ||
3159 | static int em_rdmsr(struct x86_emulate_ctxt *ctxt) | |
3160 | { | |
3161 | u64 msr_data; | |
3162 | ||
dd856efa | 3163 | if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) |
e1e210b0 TY |
3164 | return emulate_gp(ctxt, 0); |
3165 | ||
dd856efa AK |
3166 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; |
3167 | *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; | |
e1e210b0 TY |
3168 | return X86EMUL_CONTINUE; |
3169 | } | |
3170 | ||
1bd5f469 TY |
3171 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
3172 | { | |
9dac77fa | 3173 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3174 | return emulate_ud(ctxt); |
3175 | ||
9dac77fa | 3176 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
1bd5f469 TY |
3177 | return X86EMUL_CONTINUE; |
3178 | } | |
3179 | ||
3180 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
3181 | { | |
9dac77fa | 3182 | u16 sel = ctxt->src.val; |
1bd5f469 | 3183 | |
9dac77fa | 3184 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3185 | return emulate_ud(ctxt); |
3186 | ||
9dac77fa | 3187 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
3188 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
3189 | ||
3190 | /* Disable writeback. */ | |
9dac77fa AK |
3191 | ctxt->dst.type = OP_NONE; |
3192 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
3193 | } |
3194 | ||
a14e579f AK |
3195 | static int em_lldt(struct x86_emulate_ctxt *ctxt) |
3196 | { | |
3197 | u16 sel = ctxt->src.val; | |
3198 | ||
3199 | /* Disable writeback. */ | |
3200 | ctxt->dst.type = OP_NONE; | |
3201 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); | |
3202 | } | |
3203 | ||
80890006 AK |
3204 | static int em_ltr(struct x86_emulate_ctxt *ctxt) |
3205 | { | |
3206 | u16 sel = ctxt->src.val; | |
3207 | ||
3208 | /* Disable writeback. */ | |
3209 | ctxt->dst.type = OP_NONE; | |
3210 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); | |
3211 | } | |
3212 | ||
38503911 AK |
3213 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
3214 | { | |
9fa088f4 AK |
3215 | int rc; |
3216 | ulong linear; | |
3217 | ||
9dac77fa | 3218 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 3219 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 3220 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 3221 | /* Disable writeback. */ |
9dac77fa | 3222 | ctxt->dst.type = OP_NONE; |
38503911 AK |
3223 | return X86EMUL_CONTINUE; |
3224 | } | |
3225 | ||
2d04a05b AK |
3226 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
3227 | { | |
3228 | ulong cr0; | |
3229 | ||
3230 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
3231 | cr0 &= ~X86_CR0_TS; | |
3232 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
3233 | return X86EMUL_CONTINUE; | |
3234 | } | |
3235 | ||
26d05cc7 AK |
3236 | static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
3237 | { | |
26d05cc7 AK |
3238 | int rc; |
3239 | ||
9dac77fa | 3240 | if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) |
26d05cc7 AK |
3241 | return X86EMUL_UNHANDLEABLE; |
3242 | ||
3243 | rc = ctxt->ops->fix_hypercall(ctxt); | |
3244 | if (rc != X86EMUL_CONTINUE) | |
3245 | return rc; | |
3246 | ||
3247 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 3248 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 3249 | /* Disable writeback. */ |
9dac77fa | 3250 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3251 | return X86EMUL_CONTINUE; |
3252 | } | |
3253 | ||
96051572 AK |
3254 | static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, |
3255 | void (*get)(struct x86_emulate_ctxt *ctxt, | |
3256 | struct desc_ptr *ptr)) | |
3257 | { | |
3258 | struct desc_ptr desc_ptr; | |
3259 | ||
3260 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3261 | ctxt->op_bytes = 8; | |
3262 | get(ctxt, &desc_ptr); | |
3263 | if (ctxt->op_bytes == 2) { | |
3264 | ctxt->op_bytes = 4; | |
3265 | desc_ptr.address &= 0x00ffffff; | |
3266 | } | |
3267 | /* Disable writeback. */ | |
3268 | ctxt->dst.type = OP_NONE; | |
3269 | return segmented_write(ctxt, ctxt->dst.addr.mem, | |
3270 | &desc_ptr, 2 + ctxt->op_bytes); | |
3271 | } | |
3272 | ||
3273 | static int em_sgdt(struct x86_emulate_ctxt *ctxt) | |
3274 | { | |
3275 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); | |
3276 | } | |
3277 | ||
3278 | static int em_sidt(struct x86_emulate_ctxt *ctxt) | |
3279 | { | |
3280 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); | |
3281 | } | |
3282 | ||
26d05cc7 AK |
3283 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) |
3284 | { | |
26d05cc7 AK |
3285 | struct desc_ptr desc_ptr; |
3286 | int rc; | |
3287 | ||
510425ff AK |
3288 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3289 | ctxt->op_bytes = 8; | |
9dac77fa | 3290 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 3291 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3292 | ctxt->op_bytes); |
26d05cc7 AK |
3293 | if (rc != X86EMUL_CONTINUE) |
3294 | return rc; | |
3295 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
3296 | /* Disable writeback. */ | |
9dac77fa | 3297 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3298 | return X86EMUL_CONTINUE; |
3299 | } | |
3300 | ||
5ef39c71 | 3301 | static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 3302 | { |
26d05cc7 AK |
3303 | int rc; |
3304 | ||
5ef39c71 AK |
3305 | rc = ctxt->ops->fix_hypercall(ctxt); |
3306 | ||
26d05cc7 | 3307 | /* Disable writeback. */ |
9dac77fa | 3308 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3309 | return rc; |
3310 | } | |
3311 | ||
3312 | static int em_lidt(struct x86_emulate_ctxt *ctxt) | |
3313 | { | |
26d05cc7 AK |
3314 | struct desc_ptr desc_ptr; |
3315 | int rc; | |
3316 | ||
510425ff AK |
3317 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3318 | ctxt->op_bytes = 8; | |
9dac77fa | 3319 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
509cf9fe | 3320 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3321 | ctxt->op_bytes); |
26d05cc7 AK |
3322 | if (rc != X86EMUL_CONTINUE) |
3323 | return rc; | |
3324 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
3325 | /* Disable writeback. */ | |
9dac77fa | 3326 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3327 | return X86EMUL_CONTINUE; |
3328 | } | |
3329 | ||
3330 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
3331 | { | |
9dac77fa AK |
3332 | ctxt->dst.bytes = 2; |
3333 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); | |
26d05cc7 AK |
3334 | return X86EMUL_CONTINUE; |
3335 | } | |
3336 | ||
3337 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
3338 | { | |
26d05cc7 | 3339 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
3340 | | (ctxt->src.val & 0x0f)); |
3341 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
3342 | return X86EMUL_CONTINUE; |
3343 | } | |
3344 | ||
d06e03ad TY |
3345 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
3346 | { | |
dd856efa AK |
3347 | register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); |
3348 | if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && | |
9dac77fa AK |
3349 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) |
3350 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
3351 | |
3352 | return X86EMUL_CONTINUE; | |
3353 | } | |
3354 | ||
3355 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
3356 | { | |
dd856efa | 3357 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) |
9dac77fa | 3358 | jmp_rel(ctxt, ctxt->src.val); |
d06e03ad TY |
3359 | |
3360 | return X86EMUL_CONTINUE; | |
3361 | } | |
3362 | ||
d7841a4b TY |
3363 | static int em_in(struct x86_emulate_ctxt *ctxt) |
3364 | { | |
3365 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, | |
3366 | &ctxt->dst.val)) | |
3367 | return X86EMUL_IO_NEEDED; | |
3368 | ||
3369 | return X86EMUL_CONTINUE; | |
3370 | } | |
3371 | ||
3372 | static int em_out(struct x86_emulate_ctxt *ctxt) | |
3373 | { | |
3374 | ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, | |
3375 | &ctxt->src.val, 1); | |
3376 | /* Disable writeback. */ | |
3377 | ctxt->dst.type = OP_NONE; | |
3378 | return X86EMUL_CONTINUE; | |
3379 | } | |
3380 | ||
f411e6cd TY |
3381 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
3382 | { | |
3383 | if (emulator_bad_iopl(ctxt)) | |
3384 | return emulate_gp(ctxt, 0); | |
3385 | ||
3386 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
3387 | return X86EMUL_CONTINUE; | |
3388 | } | |
3389 | ||
3390 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
3391 | { | |
3392 | if (emulator_bad_iopl(ctxt)) | |
3393 | return emulate_gp(ctxt, 0); | |
3394 | ||
3395 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
3396 | ctxt->eflags |= X86_EFLAGS_IF; | |
3397 | return X86EMUL_CONTINUE; | |
3398 | } | |
3399 | ||
6d6eede4 AK |
3400 | static int em_cpuid(struct x86_emulate_ctxt *ctxt) |
3401 | { | |
3402 | u32 eax, ebx, ecx, edx; | |
3403 | ||
dd856efa AK |
3404 | eax = reg_read(ctxt, VCPU_REGS_RAX); |
3405 | ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
6d6eede4 | 3406 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
dd856efa AK |
3407 | *reg_write(ctxt, VCPU_REGS_RAX) = eax; |
3408 | *reg_write(ctxt, VCPU_REGS_RBX) = ebx; | |
3409 | *reg_write(ctxt, VCPU_REGS_RCX) = ecx; | |
3410 | *reg_write(ctxt, VCPU_REGS_RDX) = edx; | |
6d6eede4 AK |
3411 | return X86EMUL_CONTINUE; |
3412 | } | |
3413 | ||
2dd7caa0 AK |
3414 | static int em_lahf(struct x86_emulate_ctxt *ctxt) |
3415 | { | |
dd856efa AK |
3416 | *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; |
3417 | *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; | |
2dd7caa0 AK |
3418 | return X86EMUL_CONTINUE; |
3419 | } | |
3420 | ||
9299836e AK |
3421 | static int em_bswap(struct x86_emulate_ctxt *ctxt) |
3422 | { | |
3423 | switch (ctxt->op_bytes) { | |
3424 | #ifdef CONFIG_X86_64 | |
3425 | case 8: | |
3426 | asm("bswap %0" : "+r"(ctxt->dst.val)); | |
3427 | break; | |
3428 | #endif | |
3429 | default: | |
3430 | asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); | |
3431 | break; | |
3432 | } | |
3433 | return X86EMUL_CONTINUE; | |
3434 | } | |
3435 | ||
cfec82cb JR |
3436 | static bool valid_cr(int nr) |
3437 | { | |
3438 | switch (nr) { | |
3439 | case 0: | |
3440 | case 2 ... 4: | |
3441 | case 8: | |
3442 | return true; | |
3443 | default: | |
3444 | return false; | |
3445 | } | |
3446 | } | |
3447 | ||
3448 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
3449 | { | |
9dac77fa | 3450 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
3451 | return emulate_ud(ctxt); |
3452 | ||
3453 | return X86EMUL_CONTINUE; | |
3454 | } | |
3455 | ||
3456 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
3457 | { | |
9dac77fa AK |
3458 | u64 new_val = ctxt->src.val64; |
3459 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 3460 | u64 efer = 0; |
cfec82cb JR |
3461 | |
3462 | static u64 cr_reserved_bits[] = { | |
3463 | 0xffffffff00000000ULL, | |
3464 | 0, 0, 0, /* CR3 checked later */ | |
3465 | CR4_RESERVED_BITS, | |
3466 | 0, 0, 0, | |
3467 | CR8_RESERVED_BITS, | |
3468 | }; | |
3469 | ||
3470 | if (!valid_cr(cr)) | |
3471 | return emulate_ud(ctxt); | |
3472 | ||
3473 | if (new_val & cr_reserved_bits[cr]) | |
3474 | return emulate_gp(ctxt, 0); | |
3475 | ||
3476 | switch (cr) { | |
3477 | case 0: { | |
c2ad2bb3 | 3478 | u64 cr4; |
cfec82cb JR |
3479 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
3480 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
3481 | return emulate_gp(ctxt, 0); | |
3482 | ||
717746e3 AK |
3483 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3484 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
3485 | |
3486 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
3487 | !(cr4 & X86_CR4_PAE)) | |
3488 | return emulate_gp(ctxt, 0); | |
3489 | ||
3490 | break; | |
3491 | } | |
3492 | case 3: { | |
3493 | u64 rsvd = 0; | |
3494 | ||
c2ad2bb3 AK |
3495 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
3496 | if (efer & EFER_LMA) | |
cfec82cb | 3497 | rsvd = CR3_L_MODE_RESERVED_BITS; |
fd72c419 | 3498 | else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) |
cfec82cb | 3499 | rsvd = CR3_PAE_RESERVED_BITS; |
fd72c419 | 3500 | else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) |
cfec82cb JR |
3501 | rsvd = CR3_NONPAE_RESERVED_BITS; |
3502 | ||
3503 | if (new_val & rsvd) | |
3504 | return emulate_gp(ctxt, 0); | |
3505 | ||
3506 | break; | |
3507 | } | |
3508 | case 4: { | |
717746e3 | 3509 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
cfec82cb JR |
3510 | |
3511 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
3512 | return emulate_gp(ctxt, 0); | |
3513 | ||
3514 | break; | |
3515 | } | |
3516 | } | |
3517 | ||
3518 | return X86EMUL_CONTINUE; | |
3519 | } | |
3520 | ||
3b88e41a JR |
3521 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
3522 | { | |
3523 | unsigned long dr7; | |
3524 | ||
717746e3 | 3525 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
3526 | |
3527 | /* Check if DR7.Global_Enable is set */ | |
3528 | return dr7 & (1 << 13); | |
3529 | } | |
3530 | ||
3531 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
3532 | { | |
9dac77fa | 3533 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
3534 | u64 cr4; |
3535 | ||
3536 | if (dr > 7) | |
3537 | return emulate_ud(ctxt); | |
3538 | ||
717746e3 | 3539 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
3540 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
3541 | return emulate_ud(ctxt); | |
3542 | ||
3543 | if (check_dr7_gd(ctxt)) | |
3544 | return emulate_db(ctxt); | |
3545 | ||
3546 | return X86EMUL_CONTINUE; | |
3547 | } | |
3548 | ||
3549 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
3550 | { | |
9dac77fa AK |
3551 | u64 new_val = ctxt->src.val64; |
3552 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
3553 | |
3554 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
3555 | return emulate_gp(ctxt, 0); | |
3556 | ||
3557 | return check_dr_read(ctxt); | |
3558 | } | |
3559 | ||
01de8b09 JR |
3560 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
3561 | { | |
3562 | u64 efer; | |
3563 | ||
717746e3 | 3564 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
3565 | |
3566 | if (!(efer & EFER_SVME)) | |
3567 | return emulate_ud(ctxt); | |
3568 | ||
3569 | return X86EMUL_CONTINUE; | |
3570 | } | |
3571 | ||
3572 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
3573 | { | |
dd856efa | 3574 | u64 rax = reg_read(ctxt, VCPU_REGS_RAX); |
01de8b09 JR |
3575 | |
3576 | /* Valid physical address? */ | |
d4224449 | 3577 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
3578 | return emulate_gp(ctxt, 0); |
3579 | ||
3580 | return check_svme(ctxt); | |
3581 | } | |
3582 | ||
d7eb8203 JR |
3583 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
3584 | { | |
717746e3 | 3585 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 3586 | |
717746e3 | 3587 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
3588 | return emulate_ud(ctxt); |
3589 | ||
3590 | return X86EMUL_CONTINUE; | |
3591 | } | |
3592 | ||
8061252e JR |
3593 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
3594 | { | |
717746e3 | 3595 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
dd856efa | 3596 | u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); |
8061252e | 3597 | |
717746e3 | 3598 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
8061252e JR |
3599 | (rcx > 3)) |
3600 | return emulate_gp(ctxt, 0); | |
3601 | ||
3602 | return X86EMUL_CONTINUE; | |
3603 | } | |
3604 | ||
f6511935 JR |
3605 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
3606 | { | |
9dac77fa AK |
3607 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
3608 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
3609 | return emulate_gp(ctxt, 0); |
3610 | ||
3611 | return X86EMUL_CONTINUE; | |
3612 | } | |
3613 | ||
3614 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
3615 | { | |
9dac77fa AK |
3616 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
3617 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
3618 | return emulate_gp(ctxt, 0); |
3619 | ||
3620 | return X86EMUL_CONTINUE; | |
3621 | } | |
3622 | ||
73fba5f4 | 3623 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 3624 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
3625 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
3626 | .check_perm = (_p) } | |
73fba5f4 | 3627 | #define N D(0) |
01de8b09 | 3628 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
1c2545be TY |
3629 | #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } |
3630 | #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } | |
045a282c | 3631 | #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } |
73fba5f4 | 3632 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
e28bbd44 | 3633 | #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } |
c4f035c6 AK |
3634 | #define II(_f, _e, _i) \ |
3635 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
3636 | #define IIP(_f, _e, _i, _p) \ |
3637 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
3638 | .check_perm = (_p) } | |
aa97bb48 | 3639 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 3640 | |
8d8f4e9f | 3641 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 3642 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f | 3643 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
f7857f35 | 3644 | #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) |
d7841a4b TY |
3645 | #define I2bvIP(_f, _e, _i, _p) \ |
3646 | IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) | |
8d8f4e9f | 3647 | |
fb864fbc AK |
3648 | #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
3649 | F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
3650 | F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 3651 | |
fd0a0d82 | 3652 | static const struct opcode group7_rm1[] = { |
1c2545be TY |
3653 | DI(SrcNone | Priv, monitor), |
3654 | DI(SrcNone | Priv, mwait), | |
d7eb8203 JR |
3655 | N, N, N, N, N, N, |
3656 | }; | |
3657 | ||
fd0a0d82 | 3658 | static const struct opcode group7_rm3[] = { |
1c2545be TY |
3659 | DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), |
3660 | II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall), | |
3661 | DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), | |
3662 | DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), | |
3663 | DIP(SrcNone | Prot | Priv, stgi, check_svme), | |
3664 | DIP(SrcNone | Prot | Priv, clgi, check_svme), | |
3665 | DIP(SrcNone | Prot | Priv, skinit, check_svme), | |
3666 | DIP(SrcNone | Prot | Priv, invlpga, check_svme), | |
01de8b09 | 3667 | }; |
6230f7fc | 3668 | |
fd0a0d82 | 3669 | static const struct opcode group7_rm7[] = { |
d7eb8203 | 3670 | N, |
1c2545be | 3671 | DIP(SrcNone, rdtscp, check_rdtsc), |
d7eb8203 JR |
3672 | N, N, N, N, N, N, |
3673 | }; | |
d67fc27a | 3674 | |
fd0a0d82 | 3675 | static const struct opcode group1[] = { |
fb864fbc AK |
3676 | F(Lock, em_add), |
3677 | F(Lock | PageTable, em_or), | |
3678 | F(Lock, em_adc), | |
3679 | F(Lock, em_sbb), | |
3680 | F(Lock | PageTable, em_and), | |
3681 | F(Lock, em_sub), | |
3682 | F(Lock, em_xor), | |
3683 | F(NoWrite, em_cmp), | |
73fba5f4 AK |
3684 | }; |
3685 | ||
fd0a0d82 | 3686 | static const struct opcode group1A[] = { |
1c2545be | 3687 | I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, |
73fba5f4 AK |
3688 | }; |
3689 | ||
007a3b54 AK |
3690 | static const struct opcode group2[] = { |
3691 | F(DstMem | ModRM, em_rol), | |
3692 | F(DstMem | ModRM, em_ror), | |
3693 | F(DstMem | ModRM, em_rcl), | |
3694 | F(DstMem | ModRM, em_rcr), | |
3695 | F(DstMem | ModRM, em_shl), | |
3696 | F(DstMem | ModRM, em_shr), | |
3697 | F(DstMem | ModRM, em_shl), | |
3698 | F(DstMem | ModRM, em_sar), | |
3699 | }; | |
3700 | ||
fd0a0d82 | 3701 | static const struct opcode group3[] = { |
fb864fbc AK |
3702 | F(DstMem | SrcImm | NoWrite, em_test), |
3703 | F(DstMem | SrcImm | NoWrite, em_test), | |
45a1467d AK |
3704 | F(DstMem | SrcNone | Lock, em_not), |
3705 | F(DstMem | SrcNone | Lock, em_neg), | |
1c2545be TY |
3706 | I(SrcMem, em_mul_ex), |
3707 | I(SrcMem, em_imul_ex), | |
3708 | I(SrcMem, em_div_ex), | |
3709 | I(SrcMem, em_idiv_ex), | |
73fba5f4 AK |
3710 | }; |
3711 | ||
fd0a0d82 | 3712 | static const struct opcode group4[] = { |
95413dc4 AK |
3713 | F(ByteOp | DstMem | SrcNone | Lock, em_inc), |
3714 | F(ByteOp | DstMem | SrcNone | Lock, em_dec), | |
73fba5f4 AK |
3715 | N, N, N, N, N, N, |
3716 | }; | |
3717 | ||
fd0a0d82 | 3718 | static const struct opcode group5[] = { |
95413dc4 AK |
3719 | F(DstMem | SrcNone | Lock, em_inc), |
3720 | F(DstMem | SrcNone | Lock, em_dec), | |
1c2545be TY |
3721 | I(SrcMem | Stack, em_grp45), |
3722 | I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), | |
3723 | I(SrcMem | Stack, em_grp45), | |
3724 | I(SrcMemFAddr | ImplicitOps, em_grp45), | |
3725 | I(SrcMem | Stack, em_grp45), N, | |
73fba5f4 AK |
3726 | }; |
3727 | ||
fd0a0d82 | 3728 | static const struct opcode group6[] = { |
1c2545be TY |
3729 | DI(Prot, sldt), |
3730 | DI(Prot, str), | |
a14e579f | 3731 | II(Prot | Priv | SrcMem16, em_lldt, lldt), |
80890006 | 3732 | II(Prot | Priv | SrcMem16, em_ltr, ltr), |
dee6bb70 JR |
3733 | N, N, N, N, |
3734 | }; | |
3735 | ||
fd0a0d82 | 3736 | static const struct group_dual group7 = { { |
96051572 AK |
3737 | II(Mov | DstMem | Priv, em_sgdt, sgdt), |
3738 | II(Mov | DstMem | Priv, em_sidt, sidt), | |
1c2545be TY |
3739 | II(SrcMem | Priv, em_lgdt, lgdt), |
3740 | II(SrcMem | Priv, em_lidt, lidt), | |
3741 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, | |
3742 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3743 | II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3744 | }, { |
1c2545be | 3745 | I(SrcNone | Priv | VendorSpecific, em_vmcall), |
5ef39c71 | 3746 | EXT(0, group7_rm1), |
01de8b09 | 3747 | N, EXT(0, group7_rm3), |
1c2545be TY |
3748 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, |
3749 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3750 | EXT(0, group7_rm7), | |
73fba5f4 AK |
3751 | } }; |
3752 | ||
fd0a0d82 | 3753 | static const struct opcode group8[] = { |
73fba5f4 | 3754 | N, N, N, N, |
11c363ba AK |
3755 | F(DstMem | SrcImmByte | NoWrite, em_bt), |
3756 | F(DstMem | SrcImmByte | Lock | PageTable, em_bts), | |
3757 | F(DstMem | SrcImmByte | Lock, em_btr), | |
3758 | F(DstMem | SrcImmByte | Lock | PageTable, em_btc), | |
73fba5f4 AK |
3759 | }; |
3760 | ||
fd0a0d82 | 3761 | static const struct group_dual group9 = { { |
1c2545be | 3762 | N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
73fba5f4 AK |
3763 | }, { |
3764 | N, N, N, N, N, N, N, N, | |
3765 | } }; | |
3766 | ||
fd0a0d82 | 3767 | static const struct opcode group11[] = { |
1c2545be | 3768 | I(DstMem | SrcImm | Mov | PageTable, em_mov), |
d5ae7ce8 | 3769 | X7(D(Undefined)), |
a4d4a7c1 AK |
3770 | }; |
3771 | ||
fd0a0d82 | 3772 | static const struct gprefix pfx_0f_6f_0f_7f = { |
e5971755 | 3773 | I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), |
aa97bb48 AK |
3774 | }; |
3775 | ||
fd0a0d82 | 3776 | static const struct gprefix pfx_vmovntpx = { |
3e114eb4 AK |
3777 | I(0, em_mov), N, N, N, |
3778 | }; | |
3779 | ||
045a282c GN |
3780 | static const struct escape escape_d9 = { { |
3781 | N, N, N, N, N, N, N, I(DstMem, em_fnstcw), | |
3782 | }, { | |
3783 | /* 0xC0 - 0xC7 */ | |
3784 | N, N, N, N, N, N, N, N, | |
3785 | /* 0xC8 - 0xCF */ | |
3786 | N, N, N, N, N, N, N, N, | |
3787 | /* 0xD0 - 0xC7 */ | |
3788 | N, N, N, N, N, N, N, N, | |
3789 | /* 0xD8 - 0xDF */ | |
3790 | N, N, N, N, N, N, N, N, | |
3791 | /* 0xE0 - 0xE7 */ | |
3792 | N, N, N, N, N, N, N, N, | |
3793 | /* 0xE8 - 0xEF */ | |
3794 | N, N, N, N, N, N, N, N, | |
3795 | /* 0xF0 - 0xF7 */ | |
3796 | N, N, N, N, N, N, N, N, | |
3797 | /* 0xF8 - 0xFF */ | |
3798 | N, N, N, N, N, N, N, N, | |
3799 | } }; | |
3800 | ||
3801 | static const struct escape escape_db = { { | |
3802 | N, N, N, N, N, N, N, N, | |
3803 | }, { | |
3804 | /* 0xC0 - 0xC7 */ | |
3805 | N, N, N, N, N, N, N, N, | |
3806 | /* 0xC8 - 0xCF */ | |
3807 | N, N, N, N, N, N, N, N, | |
3808 | /* 0xD0 - 0xC7 */ | |
3809 | N, N, N, N, N, N, N, N, | |
3810 | /* 0xD8 - 0xDF */ | |
3811 | N, N, N, N, N, N, N, N, | |
3812 | /* 0xE0 - 0xE7 */ | |
3813 | N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, | |
3814 | /* 0xE8 - 0xEF */ | |
3815 | N, N, N, N, N, N, N, N, | |
3816 | /* 0xF0 - 0xF7 */ | |
3817 | N, N, N, N, N, N, N, N, | |
3818 | /* 0xF8 - 0xFF */ | |
3819 | N, N, N, N, N, N, N, N, | |
3820 | } }; | |
3821 | ||
3822 | static const struct escape escape_dd = { { | |
3823 | N, N, N, N, N, N, N, I(DstMem, em_fnstsw), | |
3824 | }, { | |
3825 | /* 0xC0 - 0xC7 */ | |
3826 | N, N, N, N, N, N, N, N, | |
3827 | /* 0xC8 - 0xCF */ | |
3828 | N, N, N, N, N, N, N, N, | |
3829 | /* 0xD0 - 0xC7 */ | |
3830 | N, N, N, N, N, N, N, N, | |
3831 | /* 0xD8 - 0xDF */ | |
3832 | N, N, N, N, N, N, N, N, | |
3833 | /* 0xE0 - 0xE7 */ | |
3834 | N, N, N, N, N, N, N, N, | |
3835 | /* 0xE8 - 0xEF */ | |
3836 | N, N, N, N, N, N, N, N, | |
3837 | /* 0xF0 - 0xF7 */ | |
3838 | N, N, N, N, N, N, N, N, | |
3839 | /* 0xF8 - 0xFF */ | |
3840 | N, N, N, N, N, N, N, N, | |
3841 | } }; | |
3842 | ||
fd0a0d82 | 3843 | static const struct opcode opcode_table[256] = { |
73fba5f4 | 3844 | /* 0x00 - 0x07 */ |
fb864fbc | 3845 | F6ALU(Lock, em_add), |
1cd196ea AK |
3846 | I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
3847 | I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), | |
73fba5f4 | 3848 | /* 0x08 - 0x0F */ |
fb864fbc | 3849 | F6ALU(Lock | PageTable, em_or), |
1cd196ea AK |
3850 | I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
3851 | N, | |
73fba5f4 | 3852 | /* 0x10 - 0x17 */ |
fb864fbc | 3853 | F6ALU(Lock, em_adc), |
1cd196ea AK |
3854 | I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
3855 | I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), | |
73fba5f4 | 3856 | /* 0x18 - 0x1F */ |
fb864fbc | 3857 | F6ALU(Lock, em_sbb), |
1cd196ea AK |
3858 | I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
3859 | I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), | |
73fba5f4 | 3860 | /* 0x20 - 0x27 */ |
fb864fbc | 3861 | F6ALU(Lock | PageTable, em_and), N, N, |
73fba5f4 | 3862 | /* 0x28 - 0x2F */ |
fb864fbc | 3863 | F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 3864 | /* 0x30 - 0x37 */ |
fb864fbc | 3865 | F6ALU(Lock, em_xor), N, N, |
73fba5f4 | 3866 | /* 0x38 - 0x3F */ |
fb864fbc | 3867 | F6ALU(NoWrite, em_cmp), N, N, |
73fba5f4 | 3868 | /* 0x40 - 0x4F */ |
95413dc4 | 3869 | X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), |
73fba5f4 | 3870 | /* 0x50 - 0x57 */ |
63540382 | 3871 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 3872 | /* 0x58 - 0x5F */ |
c54fe504 | 3873 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 3874 | /* 0x60 - 0x67 */ |
b96a7fad TY |
3875 | I(ImplicitOps | Stack | No64, em_pusha), |
3876 | I(ImplicitOps | Stack | No64, em_popa), | |
73fba5f4 AK |
3877 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
3878 | N, N, N, N, | |
3879 | /* 0x68 - 0x6F */ | |
d46164db AK |
3880 | I(SrcImm | Mov | Stack, em_push), |
3881 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
3882 | I(SrcImmByte | Mov | Stack, em_push), |
3883 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
b3356bf0 | 3884 | I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ |
2b5e97e1 | 3885 | I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ |
73fba5f4 AK |
3886 | /* 0x70 - 0x7F */ |
3887 | X16(D(SrcImmByte)), | |
3888 | /* 0x80 - 0x87 */ | |
1c2545be TY |
3889 | G(ByteOp | DstMem | SrcImm, group1), |
3890 | G(DstMem | SrcImm, group1), | |
3891 | G(ByteOp | DstMem | SrcImm | No64, group1), | |
3892 | G(DstMem | SrcImmByte, group1), | |
fb864fbc | 3893 | F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), |
d5ae7ce8 | 3894 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
73fba5f4 | 3895 | /* 0x88 - 0x8F */ |
d5ae7ce8 | 3896 | I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
b9eac5f4 | 3897 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
d5ae7ce8 | 3898 | I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
1bd5f469 TY |
3899 | D(ModRM | SrcMem | NoAccess | DstReg), |
3900 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
3901 | G(0, group1A), | |
73fba5f4 | 3902 | /* 0x90 - 0x97 */ |
bf608f88 | 3903 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 3904 | /* 0x98 - 0x9F */ |
61429142 | 3905 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 3906 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 | 3907 | II(ImplicitOps | Stack, em_pushf, pushf), |
2dd7caa0 | 3908 | II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf), |
73fba5f4 | 3909 | /* 0xA0 - 0xA7 */ |
b9eac5f4 | 3910 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
d5ae7ce8 | 3911 | I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
b9eac5f4 | 3912 | I2bv(SrcSI | DstDI | Mov | String, em_mov), |
fb864fbc | 3913 | F2bv(SrcSI | DstDI | String | NoWrite, em_cmp), |
73fba5f4 | 3914 | /* 0xA8 - 0xAF */ |
fb864fbc | 3915 | F2bv(DstAcc | SrcImm | NoWrite, em_test), |
b9eac5f4 AK |
3916 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
3917 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
fb864fbc | 3918 | F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp), |
73fba5f4 | 3919 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 3920 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3921 | /* 0xB8 - 0xBF */ |
5e2c6883 | 3922 | X8(I(DstReg | SrcImm64 | Mov, em_mov)), |
73fba5f4 | 3923 | /* 0xC0 - 0xC7 */ |
007a3b54 | 3924 | G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), |
40ece7c7 | 3925 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
ebda02c2 | 3926 | I(ImplicitOps | Stack, em_ret), |
d4b4325f AK |
3927 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
3928 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), | |
a4d4a7c1 | 3929 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 3930 | /* 0xC8 - 0xCF */ |
612e89f0 AK |
3931 | I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), |
3932 | N, I(ImplicitOps | Stack, em_ret_far), | |
3c6e276f | 3933 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 3934 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 3935 | /* 0xD0 - 0xD7 */ |
007a3b54 AK |
3936 | G(Src2One | ByteOp, group2), G(Src2One, group2), |
3937 | G(Src2CL | ByteOp, group2), G(Src2CL, group2), | |
7f662273 | 3938 | N, I(DstAcc | SrcImmByte | No64, em_aad), N, N, |
73fba5f4 | 3939 | /* 0xD8 - 0xDF */ |
045a282c | 3940 | N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, |
73fba5f4 | 3941 | /* 0xE0 - 0xE7 */ |
d06e03ad TY |
3942 | X3(I(SrcImmByte, em_loop)), |
3943 | I(SrcImmByte, em_jcxz), | |
d7841a4b TY |
3944 | I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
3945 | I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), | |
73fba5f4 | 3946 | /* 0xE8 - 0xEF */ |
d4ddafcd | 3947 | I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), |
db5b0762 | 3948 | I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), |
d7841a4b TY |
3949 | I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
3950 | I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), | |
73fba5f4 | 3951 | /* 0xF0 - 0xF7 */ |
bf608f88 | 3952 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
3953 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
3954 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 3955 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
3956 | D(ImplicitOps), D(ImplicitOps), |
3957 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
3958 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
3959 | }; | |
3960 | ||
fd0a0d82 | 3961 | static const struct opcode twobyte_table[256] = { |
73fba5f4 | 3962 | /* 0x00 - 0x0F */ |
dee6bb70 | 3963 | G(0, group6), GD(0, &group7), N, N, |
db5b0762 TY |
3964 | N, I(ImplicitOps | VendorSpecific, em_syscall), |
3965 | II(ImplicitOps | Priv, em_clts, clts), N, | |
3c6e276f | 3966 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
3967 | N, D(ImplicitOps | ModRM), N, N, |
3968 | /* 0x10 - 0x1F */ | |
3969 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
3970 | /* 0x20 - 0x2F */ | |
cfec82cb | 3971 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 3972 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
bc00f8d2 TY |
3973 | IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), |
3974 | IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), | |
73fba5f4 | 3975 | N, N, N, N, |
3e114eb4 AK |
3976 | N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx), |
3977 | N, N, N, N, | |
73fba5f4 | 3978 | /* 0x30 - 0x3F */ |
e1e210b0 | 3979 | II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
8061252e | 3980 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
e1e210b0 | 3981 | II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
222d21aa | 3982 | IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
db5b0762 TY |
3983 | I(ImplicitOps | VendorSpecific, em_sysenter), |
3984 | I(ImplicitOps | Priv | VendorSpecific, em_sysexit), | |
d867162c | 3985 | N, N, |
73fba5f4 AK |
3986 | N, N, N, N, N, N, N, N, |
3987 | /* 0x40 - 0x4F */ | |
3988 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
3989 | /* 0x50 - 0x5F */ | |
3990 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3991 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
3992 | N, N, N, N, |
3993 | N, N, N, N, | |
3994 | N, N, N, N, | |
3995 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 3996 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
3997 | N, N, N, N, |
3998 | N, N, N, N, | |
3999 | N, N, N, N, | |
4000 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
4001 | /* 0x80 - 0x8F */ |
4002 | X16(D(SrcImm)), | |
4003 | /* 0x90 - 0x9F */ | |
ee45b58e | 4004 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 | 4005 | /* 0xA0 - 0xA7 */ |
1cd196ea | 4006 | I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
11c363ba AK |
4007 | II(ImplicitOps, em_cpuid, cpuid), |
4008 | F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), | |
0bdea068 AK |
4009 | F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), |
4010 | F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, | |
73fba5f4 | 4011 | /* 0xA8 - 0xAF */ |
1cd196ea | 4012 | I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
d5ae7ce8 | 4013 | DI(ImplicitOps, rsm), |
11c363ba | 4014 | F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
0bdea068 AK |
4015 | F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), |
4016 | F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), | |
4d758349 | 4017 | D(ModRM), F(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 4018 | /* 0xB0 - 0xB7 */ |
e940b5c2 | 4019 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), |
d4b4325f | 4020 | I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
11c363ba | 4021 | F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
d4b4325f AK |
4022 | I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
4023 | I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), | |
2adb5ad9 | 4024 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 AK |
4025 | /* 0xB8 - 0xBF */ |
4026 | N, N, | |
ce7faab2 | 4027 | G(BitOp, group8), |
11c363ba AK |
4028 | F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), |
4029 | F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr), | |
2adb5ad9 | 4030 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
9299836e | 4031 | /* 0xC0 - 0xC7 */ |
739ae406 | 4032 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 4033 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 | 4034 | N, N, N, GD(0, &group9), |
9299836e AK |
4035 | /* 0xC8 - 0xCF */ |
4036 | X8(I(DstReg, em_bswap)), | |
73fba5f4 AK |
4037 | /* 0xD0 - 0xDF */ |
4038 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
4039 | /* 0xE0 - 0xEF */ | |
4040 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
4041 | /* 0xF0 - 0xFF */ | |
4042 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
4043 | }; | |
4044 | ||
4045 | #undef D | |
4046 | #undef N | |
4047 | #undef G | |
4048 | #undef GD | |
4049 | #undef I | |
aa97bb48 | 4050 | #undef GP |
01de8b09 | 4051 | #undef EXT |
73fba5f4 | 4052 | |
8d8f4e9f | 4053 | #undef D2bv |
f6511935 | 4054 | #undef D2bvIP |
8d8f4e9f | 4055 | #undef I2bv |
d7841a4b | 4056 | #undef I2bvIP |
d67fc27a | 4057 | #undef I6ALU |
8d8f4e9f | 4058 | |
9dac77fa | 4059 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
4060 | { |
4061 | unsigned size; | |
4062 | ||
9dac77fa | 4063 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
4064 | if (size == 8) |
4065 | size = 4; | |
4066 | return size; | |
4067 | } | |
4068 | ||
4069 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
4070 | unsigned size, bool sign_extension) | |
4071 | { | |
39f21ee5 AK |
4072 | int rc = X86EMUL_CONTINUE; |
4073 | ||
4074 | op->type = OP_IMM; | |
4075 | op->bytes = size; | |
9dac77fa | 4076 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
4077 | /* NB. Immediates are sign-extended as necessary. */ |
4078 | switch (op->bytes) { | |
4079 | case 1: | |
e85a1085 | 4080 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
4081 | break; |
4082 | case 2: | |
e85a1085 | 4083 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
4084 | break; |
4085 | case 4: | |
e85a1085 | 4086 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 | 4087 | break; |
5e2c6883 NA |
4088 | case 8: |
4089 | op->val = insn_fetch(s64, ctxt); | |
4090 | break; | |
39f21ee5 AK |
4091 | } |
4092 | if (!sign_extension) { | |
4093 | switch (op->bytes) { | |
4094 | case 1: | |
4095 | op->val &= 0xff; | |
4096 | break; | |
4097 | case 2: | |
4098 | op->val &= 0xffff; | |
4099 | break; | |
4100 | case 4: | |
4101 | op->val &= 0xffffffff; | |
4102 | break; | |
4103 | } | |
4104 | } | |
4105 | done: | |
4106 | return rc; | |
4107 | } | |
4108 | ||
a9945549 AK |
4109 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
4110 | unsigned d) | |
4111 | { | |
4112 | int rc = X86EMUL_CONTINUE; | |
4113 | ||
4114 | switch (d) { | |
4115 | case OpReg: | |
2adb5ad9 | 4116 | decode_register_operand(ctxt, op); |
a9945549 AK |
4117 | break; |
4118 | case OpImmUByte: | |
608aabe3 | 4119 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
4120 | break; |
4121 | case OpMem: | |
41ddf978 | 4122 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
4123 | mem_common: |
4124 | *op = ctxt->memop; | |
4125 | ctxt->memopp = op; | |
4126 | if ((ctxt->d & BitOp) && op == &ctxt->dst) | |
a9945549 AK |
4127 | fetch_bit_operand(ctxt); |
4128 | op->orig_val = op->val; | |
4129 | break; | |
41ddf978 AK |
4130 | case OpMem64: |
4131 | ctxt->memop.bytes = 8; | |
4132 | goto mem_common; | |
a9945549 AK |
4133 | case OpAcc: |
4134 | op->type = OP_REG; | |
4135 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
dd856efa | 4136 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
a9945549 AK |
4137 | fetch_register_operand(op); |
4138 | op->orig_val = op->val; | |
4139 | break; | |
4140 | case OpDI: | |
4141 | op->type = OP_MEM; | |
4142 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4143 | op->addr.mem.ea = | |
dd856efa | 4144 | register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI)); |
a9945549 AK |
4145 | op->addr.mem.seg = VCPU_SREG_ES; |
4146 | op->val = 0; | |
b3356bf0 | 4147 | op->count = 1; |
a9945549 AK |
4148 | break; |
4149 | case OpDX: | |
4150 | op->type = OP_REG; | |
4151 | op->bytes = 2; | |
dd856efa | 4152 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
a9945549 AK |
4153 | fetch_register_operand(op); |
4154 | break; | |
4dd6a57d AK |
4155 | case OpCL: |
4156 | op->bytes = 1; | |
dd856efa | 4157 | op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; |
4dd6a57d AK |
4158 | break; |
4159 | case OpImmByte: | |
4160 | rc = decode_imm(ctxt, op, 1, true); | |
4161 | break; | |
4162 | case OpOne: | |
4163 | op->bytes = 1; | |
4164 | op->val = 1; | |
4165 | break; | |
4166 | case OpImm: | |
4167 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
4168 | break; | |
5e2c6883 NA |
4169 | case OpImm64: |
4170 | rc = decode_imm(ctxt, op, ctxt->op_bytes, true); | |
4171 | break; | |
28867cee AK |
4172 | case OpMem8: |
4173 | ctxt->memop.bytes = 1; | |
4174 | goto mem_common; | |
0fe59128 AK |
4175 | case OpMem16: |
4176 | ctxt->memop.bytes = 2; | |
4177 | goto mem_common; | |
4178 | case OpMem32: | |
4179 | ctxt->memop.bytes = 4; | |
4180 | goto mem_common; | |
4181 | case OpImmU16: | |
4182 | rc = decode_imm(ctxt, op, 2, false); | |
4183 | break; | |
4184 | case OpImmU: | |
4185 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
4186 | break; | |
4187 | case OpSI: | |
4188 | op->type = OP_MEM; | |
4189 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4190 | op->addr.mem.ea = | |
dd856efa | 4191 | register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI)); |
0fe59128 AK |
4192 | op->addr.mem.seg = seg_override(ctxt); |
4193 | op->val = 0; | |
b3356bf0 | 4194 | op->count = 1; |
0fe59128 AK |
4195 | break; |
4196 | case OpImmFAddr: | |
4197 | op->type = OP_IMM; | |
4198 | op->addr.mem.ea = ctxt->_eip; | |
4199 | op->bytes = ctxt->op_bytes + 2; | |
4200 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
4201 | break; | |
4202 | case OpMemFAddr: | |
4203 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
4204 | goto mem_common; | |
c191a7a0 AK |
4205 | case OpES: |
4206 | op->val = VCPU_SREG_ES; | |
4207 | break; | |
4208 | case OpCS: | |
4209 | op->val = VCPU_SREG_CS; | |
4210 | break; | |
4211 | case OpSS: | |
4212 | op->val = VCPU_SREG_SS; | |
4213 | break; | |
4214 | case OpDS: | |
4215 | op->val = VCPU_SREG_DS; | |
4216 | break; | |
4217 | case OpFS: | |
4218 | op->val = VCPU_SREG_FS; | |
4219 | break; | |
4220 | case OpGS: | |
4221 | op->val = VCPU_SREG_GS; | |
4222 | break; | |
a9945549 AK |
4223 | case OpImplicit: |
4224 | /* Special instructions do their own operand decoding. */ | |
4225 | default: | |
4226 | op->type = OP_NONE; /* Disable writeback. */ | |
4227 | break; | |
4228 | } | |
4229 | ||
4230 | done: | |
4231 | return rc; | |
4232 | } | |
4233 | ||
ef5d75cc | 4234 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 4235 | { |
dde7e6d1 AK |
4236 | int rc = X86EMUL_CONTINUE; |
4237 | int mode = ctxt->mode; | |
46561646 | 4238 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 4239 | bool op_prefix = false; |
46561646 | 4240 | struct opcode opcode; |
dde7e6d1 | 4241 | |
f09ed83e AK |
4242 | ctxt->memop.type = OP_NONE; |
4243 | ctxt->memopp = NULL; | |
9dac77fa AK |
4244 | ctxt->_eip = ctxt->eip; |
4245 | ctxt->fetch.start = ctxt->_eip; | |
4246 | ctxt->fetch.end = ctxt->fetch.start + insn_len; | |
dc25e89e | 4247 | if (insn_len > 0) |
9dac77fa | 4248 | memcpy(ctxt->fetch.data, insn, insn_len); |
dde7e6d1 AK |
4249 | |
4250 | switch (mode) { | |
4251 | case X86EMUL_MODE_REAL: | |
4252 | case X86EMUL_MODE_VM86: | |
4253 | case X86EMUL_MODE_PROT16: | |
4254 | def_op_bytes = def_ad_bytes = 2; | |
4255 | break; | |
4256 | case X86EMUL_MODE_PROT32: | |
4257 | def_op_bytes = def_ad_bytes = 4; | |
4258 | break; | |
4259 | #ifdef CONFIG_X86_64 | |
4260 | case X86EMUL_MODE_PROT64: | |
4261 | def_op_bytes = 4; | |
4262 | def_ad_bytes = 8; | |
4263 | break; | |
4264 | #endif | |
4265 | default: | |
1d2887e2 | 4266 | return EMULATION_FAILED; |
dde7e6d1 AK |
4267 | } |
4268 | ||
9dac77fa AK |
4269 | ctxt->op_bytes = def_op_bytes; |
4270 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
4271 | |
4272 | /* Legacy prefixes. */ | |
4273 | for (;;) { | |
e85a1085 | 4274 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 4275 | case 0x66: /* operand-size override */ |
0d7cdee8 | 4276 | op_prefix = true; |
dde7e6d1 | 4277 | /* switch between 2/4 bytes */ |
9dac77fa | 4278 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
4279 | break; |
4280 | case 0x67: /* address-size override */ | |
4281 | if (mode == X86EMUL_MODE_PROT64) | |
4282 | /* switch between 4/8 bytes */ | |
9dac77fa | 4283 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
4284 | else |
4285 | /* switch between 2/4 bytes */ | |
9dac77fa | 4286 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
4287 | break; |
4288 | case 0x26: /* ES override */ | |
4289 | case 0x2e: /* CS override */ | |
4290 | case 0x36: /* SS override */ | |
4291 | case 0x3e: /* DS override */ | |
9dac77fa | 4292 | set_seg_override(ctxt, (ctxt->b >> 3) & 3); |
dde7e6d1 AK |
4293 | break; |
4294 | case 0x64: /* FS override */ | |
4295 | case 0x65: /* GS override */ | |
9dac77fa | 4296 | set_seg_override(ctxt, ctxt->b & 7); |
dde7e6d1 AK |
4297 | break; |
4298 | case 0x40 ... 0x4f: /* REX */ | |
4299 | if (mode != X86EMUL_MODE_PROT64) | |
4300 | goto done_prefixes; | |
9dac77fa | 4301 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
4302 | continue; |
4303 | case 0xf0: /* LOCK */ | |
9dac77fa | 4304 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
4305 | break; |
4306 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 4307 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 4308 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
4309 | break; |
4310 | default: | |
4311 | goto done_prefixes; | |
4312 | } | |
4313 | ||
4314 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
4315 | ||
9dac77fa | 4316 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
4317 | } |
4318 | ||
4319 | done_prefixes: | |
4320 | ||
4321 | /* REX prefix. */ | |
9dac77fa AK |
4322 | if (ctxt->rex_prefix & 8) |
4323 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
4324 | |
4325 | /* Opcode byte(s). */ | |
9dac77fa | 4326 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 4327 | /* Two-byte opcode? */ |
9dac77fa AK |
4328 | if (ctxt->b == 0x0f) { |
4329 | ctxt->twobyte = 1; | |
e85a1085 | 4330 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 4331 | opcode = twobyte_table[ctxt->b]; |
dde7e6d1 | 4332 | } |
9dac77fa | 4333 | ctxt->d = opcode.flags; |
dde7e6d1 | 4334 | |
9f4260e7 TY |
4335 | if (ctxt->d & ModRM) |
4336 | ctxt->modrm = insn_fetch(u8, ctxt); | |
4337 | ||
9dac77fa AK |
4338 | while (ctxt->d & GroupMask) { |
4339 | switch (ctxt->d & GroupMask) { | |
46561646 | 4340 | case Group: |
9dac77fa | 4341 | goffset = (ctxt->modrm >> 3) & 7; |
46561646 AK |
4342 | opcode = opcode.u.group[goffset]; |
4343 | break; | |
4344 | case GroupDual: | |
9dac77fa AK |
4345 | goffset = (ctxt->modrm >> 3) & 7; |
4346 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
4347 | opcode = opcode.u.gdual->mod3[goffset]; |
4348 | else | |
4349 | opcode = opcode.u.gdual->mod012[goffset]; | |
4350 | break; | |
4351 | case RMExt: | |
9dac77fa | 4352 | goffset = ctxt->modrm & 7; |
01de8b09 | 4353 | opcode = opcode.u.group[goffset]; |
46561646 AK |
4354 | break; |
4355 | case Prefix: | |
9dac77fa | 4356 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 4357 | return EMULATION_FAILED; |
9dac77fa | 4358 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
4359 | switch (simd_prefix) { |
4360 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
4361 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
4362 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
4363 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
4364 | } | |
4365 | break; | |
045a282c GN |
4366 | case Escape: |
4367 | if (ctxt->modrm > 0xbf) | |
4368 | opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; | |
4369 | else | |
4370 | opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; | |
4371 | break; | |
46561646 | 4372 | default: |
1d2887e2 | 4373 | return EMULATION_FAILED; |
0d7cdee8 | 4374 | } |
46561646 | 4375 | |
b1ea50b2 | 4376 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 4377 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
4378 | } |
4379 | ||
9dac77fa AK |
4380 | ctxt->execute = opcode.u.execute; |
4381 | ctxt->check_perm = opcode.check_perm; | |
4382 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 AK |
4383 | |
4384 | /* Unrecognised? */ | |
9dac77fa | 4385 | if (ctxt->d == 0 || (ctxt->d & Undefined)) |
1d2887e2 | 4386 | return EMULATION_FAILED; |
dde7e6d1 | 4387 | |
9dac77fa | 4388 | if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
1d2887e2 | 4389 | return EMULATION_FAILED; |
d867162c | 4390 | |
9dac77fa AK |
4391 | if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) |
4392 | ctxt->op_bytes = 8; | |
dde7e6d1 | 4393 | |
9dac77fa | 4394 | if (ctxt->d & Op3264) { |
7f9b4b75 | 4395 | if (mode == X86EMUL_MODE_PROT64) |
9dac77fa | 4396 | ctxt->op_bytes = 8; |
7f9b4b75 | 4397 | else |
9dac77fa | 4398 | ctxt->op_bytes = 4; |
7f9b4b75 AK |
4399 | } |
4400 | ||
9dac77fa AK |
4401 | if (ctxt->d & Sse) |
4402 | ctxt->op_bytes = 16; | |
cbe2c9d3 AK |
4403 | else if (ctxt->d & Mmx) |
4404 | ctxt->op_bytes = 8; | |
1253791d | 4405 | |
dde7e6d1 | 4406 | /* ModRM and SIB bytes. */ |
9dac77fa | 4407 | if (ctxt->d & ModRM) { |
f09ed83e | 4408 | rc = decode_modrm(ctxt, &ctxt->memop); |
9dac77fa AK |
4409 | if (!ctxt->has_seg_override) |
4410 | set_seg_override(ctxt, ctxt->modrm_seg); | |
4411 | } else if (ctxt->d & MemAbs) | |
f09ed83e | 4412 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
4413 | if (rc != X86EMUL_CONTINUE) |
4414 | goto done; | |
4415 | ||
9dac77fa AK |
4416 | if (!ctxt->has_seg_override) |
4417 | set_seg_override(ctxt, VCPU_SREG_DS); | |
dde7e6d1 | 4418 | |
f09ed83e | 4419 | ctxt->memop.addr.mem.seg = seg_override(ctxt); |
dde7e6d1 | 4420 | |
f09ed83e AK |
4421 | if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) |
4422 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
dde7e6d1 | 4423 | |
dde7e6d1 AK |
4424 | /* |
4425 | * Decode and fetch the source operand: register, memory | |
4426 | * or immediate. | |
4427 | */ | |
0fe59128 | 4428 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
4429 | if (rc != X86EMUL_CONTINUE) |
4430 | goto done; | |
4431 | ||
dde7e6d1 AK |
4432 | /* |
4433 | * Decode and fetch the second source operand: register, memory | |
4434 | * or immediate. | |
4435 | */ | |
4dd6a57d | 4436 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
4437 | if (rc != X86EMUL_CONTINUE) |
4438 | goto done; | |
4439 | ||
dde7e6d1 | 4440 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 4441 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 AK |
4442 | |
4443 | done: | |
f09ed83e AK |
4444 | if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) |
4445 | ctxt->memopp->addr.mem.ea += ctxt->_eip; | |
cb16c348 | 4446 | |
1d2887e2 | 4447 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
4448 | } |
4449 | ||
1cb3f3ae XG |
4450 | bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
4451 | { | |
4452 | return ctxt->d & PageTable; | |
4453 | } | |
4454 | ||
3e2f65d5 GN |
4455 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
4456 | { | |
3e2f65d5 GN |
4457 | /* The second termination condition only applies for REPE |
4458 | * and REPNE. Test if the repeat string operation prefix is | |
4459 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
4460 | * corresponding termination condition according to: | |
4461 | * - if REPE/REPZ and ZF = 0 then done | |
4462 | * - if REPNE/REPNZ and ZF = 1 then done | |
4463 | */ | |
9dac77fa AK |
4464 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
4465 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
4466 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 4467 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 4468 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
4469 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
4470 | return true; | |
4471 | ||
4472 | return false; | |
4473 | } | |
4474 | ||
cbe2c9d3 AK |
4475 | static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) |
4476 | { | |
4477 | bool fault = false; | |
4478 | ||
4479 | ctxt->ops->get_fpu(ctxt); | |
4480 | asm volatile("1: fwait \n\t" | |
4481 | "2: \n\t" | |
4482 | ".pushsection .fixup,\"ax\" \n\t" | |
4483 | "3: \n\t" | |
4484 | "movb $1, %[fault] \n\t" | |
4485 | "jmp 2b \n\t" | |
4486 | ".popsection \n\t" | |
4487 | _ASM_EXTABLE(1b, 3b) | |
38e8a2dd | 4488 | : [fault]"+qm"(fault)); |
cbe2c9d3 AK |
4489 | ctxt->ops->put_fpu(ctxt); |
4490 | ||
4491 | if (unlikely(fault)) | |
4492 | return emulate_exception(ctxt, MF_VECTOR, 0, false); | |
4493 | ||
4494 | return X86EMUL_CONTINUE; | |
4495 | } | |
4496 | ||
4497 | static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, | |
4498 | struct operand *op) | |
4499 | { | |
4500 | if (op->type == OP_MM) | |
4501 | read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); | |
4502 | } | |
4503 | ||
e28bbd44 AK |
4504 | static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) |
4505 | { | |
4506 | ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; | |
4507 | fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; | |
4508 | asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" | |
4509 | : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags) | |
4510 | : "c"(ctxt->src2.val), [fastop]"S"(fop)); | |
4511 | ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); | |
4512 | return X86EMUL_CONTINUE; | |
4513 | } | |
dd856efa | 4514 | |
7b105ca2 | 4515 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 4516 | { |
0225fb50 | 4517 | const struct x86_emulate_ops *ops = ctxt->ops; |
1b30eaa8 | 4518 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 4519 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 4520 | |
9dac77fa | 4521 | ctxt->mem_read.pos = 0; |
310b5d30 | 4522 | |
9dac77fa | 4523 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { |
35d3d4a1 | 4524 | rc = emulate_ud(ctxt); |
1161624f GN |
4525 | goto done; |
4526 | } | |
4527 | ||
d380a5e4 | 4528 | /* LOCK prefix is allowed only with some instructions */ |
9dac77fa | 4529 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
35d3d4a1 | 4530 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
4531 | goto done; |
4532 | } | |
4533 | ||
9dac77fa | 4534 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 4535 | rc = emulate_ud(ctxt); |
081bca0e AK |
4536 | goto done; |
4537 | } | |
4538 | ||
cbe2c9d3 AK |
4539 | if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) |
4540 | || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
1253791d AK |
4541 | rc = emulate_ud(ctxt); |
4542 | goto done; | |
4543 | } | |
4544 | ||
cbe2c9d3 | 4545 | if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
1253791d AK |
4546 | rc = emulate_nm(ctxt); |
4547 | goto done; | |
4548 | } | |
4549 | ||
cbe2c9d3 AK |
4550 | if (ctxt->d & Mmx) { |
4551 | rc = flush_pending_x87_faults(ctxt); | |
4552 | if (rc != X86EMUL_CONTINUE) | |
4553 | goto done; | |
4554 | /* | |
4555 | * Now that we know the fpu is exception safe, we can fetch | |
4556 | * operands from it. | |
4557 | */ | |
4558 | fetch_possible_mmx_operand(ctxt, &ctxt->src); | |
4559 | fetch_possible_mmx_operand(ctxt, &ctxt->src2); | |
4560 | if (!(ctxt->d & Mov)) | |
4561 | fetch_possible_mmx_operand(ctxt, &ctxt->dst); | |
4562 | } | |
4563 | ||
9dac77fa AK |
4564 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4565 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4566 | X86_ICPT_PRE_EXCEPT); |
c4f035c6 AK |
4567 | if (rc != X86EMUL_CONTINUE) |
4568 | goto done; | |
4569 | } | |
4570 | ||
e92805ac | 4571 | /* Privileged instruction can be executed only in CPL=0 */ |
9dac77fa | 4572 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
35d3d4a1 | 4573 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
4574 | goto done; |
4575 | } | |
4576 | ||
8ea7d6ae | 4577 | /* Instruction can only be executed in protected mode */ |
9d1b39a9 | 4578 | if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { |
8ea7d6ae JR |
4579 | rc = emulate_ud(ctxt); |
4580 | goto done; | |
4581 | } | |
4582 | ||
d09beabd | 4583 | /* Do instruction specific permission checks */ |
9dac77fa AK |
4584 | if (ctxt->check_perm) { |
4585 | rc = ctxt->check_perm(ctxt); | |
d09beabd JR |
4586 | if (rc != X86EMUL_CONTINUE) |
4587 | goto done; | |
4588 | } | |
4589 | ||
9dac77fa AK |
4590 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4591 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4592 | X86_ICPT_POST_EXCEPT); |
c4f035c6 AK |
4593 | if (rc != X86EMUL_CONTINUE) |
4594 | goto done; | |
4595 | } | |
4596 | ||
9dac77fa | 4597 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b9fa9d6b | 4598 | /* All REP prefixes have the same first termination condition */ |
dd856efa | 4599 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { |
9dac77fa | 4600 | ctxt->eip = ctxt->_eip; |
b9fa9d6b AK |
4601 | goto done; |
4602 | } | |
b9fa9d6b AK |
4603 | } |
4604 | ||
9dac77fa AK |
4605 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
4606 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
4607 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 4608 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 4609 | goto done; |
9dac77fa | 4610 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
4611 | } |
4612 | ||
9dac77fa AK |
4613 | if (ctxt->src2.type == OP_MEM) { |
4614 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
4615 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
4616 | if (rc != X86EMUL_CONTINUE) |
4617 | goto done; | |
4618 | } | |
4619 | ||
9dac77fa | 4620 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
4621 | goto special_insn; |
4622 | ||
4623 | ||
9dac77fa | 4624 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 4625 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
4626 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
4627 | &ctxt->dst.val, ctxt->dst.bytes); | |
69f55cb1 GN |
4628 | if (rc != X86EMUL_CONTINUE) |
4629 | goto done; | |
038e51de | 4630 | } |
9dac77fa | 4631 | ctxt->dst.orig_val = ctxt->dst.val; |
038e51de | 4632 | |
018a98db AK |
4633 | special_insn: |
4634 | ||
9dac77fa AK |
4635 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4636 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4637 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
4638 | if (rc != X86EMUL_CONTINUE) |
4639 | goto done; | |
4640 | } | |
4641 | ||
9dac77fa | 4642 | if (ctxt->execute) { |
e28bbd44 AK |
4643 | if (ctxt->d & Fastop) { |
4644 | void (*fop)(struct fastop *) = (void *)ctxt->execute; | |
4645 | rc = fastop(ctxt, fop); | |
4646 | if (rc != X86EMUL_CONTINUE) | |
4647 | goto done; | |
4648 | goto writeback; | |
4649 | } | |
9dac77fa | 4650 | rc = ctxt->execute(ctxt); |
ef65c889 AK |
4651 | if (rc != X86EMUL_CONTINUE) |
4652 | goto done; | |
4653 | goto writeback; | |
4654 | } | |
4655 | ||
9dac77fa | 4656 | if (ctxt->twobyte) |
6aa8b732 AK |
4657 | goto twobyte_insn; |
4658 | ||
9dac77fa | 4659 | switch (ctxt->b) { |
6aa8b732 | 4660 | case 0x63: /* movsxd */ |
8b4caf66 | 4661 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 4662 | goto cannot_emulate; |
9dac77fa | 4663 | ctxt->dst.val = (s32) ctxt->src.val; |
6aa8b732 | 4664 | break; |
b2833e3c | 4665 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa AK |
4666 | if (test_cc(ctxt->b, ctxt->eflags)) |
4667 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4668 | break; |
7e0b54b1 | 4669 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 4670 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 4671 | break; |
3d9e77df | 4672 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
dd856efa | 4673 | if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) |
34698d8c | 4674 | break; |
e4f973ae TY |
4675 | rc = em_xchg(ctxt); |
4676 | break; | |
e8b6fa70 | 4677 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
4678 | switch (ctxt->op_bytes) { |
4679 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
4680 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
4681 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
4682 | } |
4683 | break; | |
6e154e56 | 4684 | case 0xcc: /* int3 */ |
5c5df76b TY |
4685 | rc = emulate_int(ctxt, 3); |
4686 | break; | |
6e154e56 | 4687 | case 0xcd: /* int n */ |
9dac77fa | 4688 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
4689 | break; |
4690 | case 0xce: /* into */ | |
5c5df76b TY |
4691 | if (ctxt->eflags & EFLG_OF) |
4692 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 4693 | break; |
1a52e051 | 4694 | case 0xe9: /* jmp rel */ |
db5b0762 | 4695 | case 0xeb: /* jmp rel short */ |
9dac77fa AK |
4696 | jmp_rel(ctxt, ctxt->src.val); |
4697 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
1a52e051 | 4698 | break; |
111de5d6 | 4699 | case 0xf4: /* hlt */ |
6c3287f7 | 4700 | ctxt->ops->halt(ctxt); |
19fdfa0d | 4701 | break; |
111de5d6 AK |
4702 | case 0xf5: /* cmc */ |
4703 | /* complement carry flag from eflags reg */ | |
4704 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
4705 | break; |
4706 | case 0xf8: /* clc */ | |
4707 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 4708 | break; |
8744aa9a MG |
4709 | case 0xf9: /* stc */ |
4710 | ctxt->eflags |= EFLG_CF; | |
4711 | break; | |
fb4616f4 MG |
4712 | case 0xfc: /* cld */ |
4713 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
4714 | break; |
4715 | case 0xfd: /* std */ | |
4716 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 4717 | break; |
91269b8f AK |
4718 | default: |
4719 | goto cannot_emulate; | |
6aa8b732 | 4720 | } |
018a98db | 4721 | |
7d9ddaed AK |
4722 | if (rc != X86EMUL_CONTINUE) |
4723 | goto done; | |
4724 | ||
018a98db | 4725 | writeback: |
adddcecf | 4726 | rc = writeback(ctxt); |
1b30eaa8 | 4727 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
4728 | goto done; |
4729 | ||
5cd21917 GN |
4730 | /* |
4731 | * restore dst type in case the decoding will be reused | |
4732 | * (happens for string instruction ) | |
4733 | */ | |
9dac77fa | 4734 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 4735 | |
9dac77fa | 4736 | if ((ctxt->d & SrcMask) == SrcSI) |
f3bd64c6 | 4737 | string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); |
a682e354 | 4738 | |
9dac77fa | 4739 | if ((ctxt->d & DstMask) == DstDI) |
f3bd64c6 | 4740 | string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); |
d9271123 | 4741 | |
9dac77fa | 4742 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b3356bf0 | 4743 | unsigned int count; |
9dac77fa | 4744 | struct read_cache *r = &ctxt->io_read; |
b3356bf0 GN |
4745 | if ((ctxt->d & SrcMask) == SrcSI) |
4746 | count = ctxt->src.count; | |
4747 | else | |
4748 | count = ctxt->dst.count; | |
4749 | register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), | |
4750 | -count); | |
3e2f65d5 | 4751 | |
d2ddd1c4 GN |
4752 | if (!string_insn_completed(ctxt)) { |
4753 | /* | |
4754 | * Re-enter guest when pio read ahead buffer is empty | |
4755 | * or, if it is not used, after each 1024 iteration. | |
4756 | */ | |
dd856efa | 4757 | if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && |
d2ddd1c4 GN |
4758 | (r->end == 0 || r->end != r->pos)) { |
4759 | /* | |
4760 | * Reset read cache. Usually happens before | |
4761 | * decode, but since instruction is restarted | |
4762 | * we have to do it here. | |
4763 | */ | |
9dac77fa | 4764 | ctxt->mem_read.end = 0; |
dd856efa | 4765 | writeback_registers(ctxt); |
d2ddd1c4 GN |
4766 | return EMULATION_RESTART; |
4767 | } | |
4768 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 4769 | } |
5cd21917 | 4770 | } |
d2ddd1c4 | 4771 | |
9dac77fa | 4772 | ctxt->eip = ctxt->_eip; |
018a98db AK |
4773 | |
4774 | done: | |
da9cb575 AK |
4775 | if (rc == X86EMUL_PROPAGATE_FAULT) |
4776 | ctxt->have_exception = true; | |
775fde86 JR |
4777 | if (rc == X86EMUL_INTERCEPTED) |
4778 | return EMULATION_INTERCEPTED; | |
4779 | ||
dd856efa AK |
4780 | if (rc == X86EMUL_CONTINUE) |
4781 | writeback_registers(ctxt); | |
4782 | ||
d2ddd1c4 | 4783 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
4784 | |
4785 | twobyte_insn: | |
9dac77fa | 4786 | switch (ctxt->b) { |
018a98db | 4787 | case 0x09: /* wbinvd */ |
cfb22375 | 4788 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
4789 | break; |
4790 | case 0x08: /* invd */ | |
018a98db AK |
4791 | case 0x0d: /* GrpP (prefetch) */ |
4792 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
4793 | break; |
4794 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 4795 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 4796 | break; |
6aa8b732 | 4797 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 4798 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 4799 | break; |
6aa8b732 | 4800 | case 0x40 ... 0x4f: /* cmov */ |
9dac77fa AK |
4801 | ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; |
4802 | if (!test_cc(ctxt->b, ctxt->eflags)) | |
4803 | ctxt->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4804 | break; |
b2833e3c | 4805 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa AK |
4806 | if (test_cc(ctxt->b, ctxt->eflags)) |
4807 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4808 | break; |
ee45b58e | 4809 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 4810 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 4811 | break; |
2a7c5b8b GC |
4812 | case 0xae: /* clflush */ |
4813 | break; | |
6aa8b732 | 4814 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa | 4815 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 4816 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val |
9dac77fa | 4817 | : (u16) ctxt->src.val; |
6aa8b732 | 4818 | break; |
6aa8b732 | 4819 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa | 4820 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 4821 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : |
9dac77fa | 4822 | (s16) ctxt->src.val; |
6aa8b732 | 4823 | break; |
92f738a5 | 4824 | case 0xc0 ... 0xc1: /* xadd */ |
158de57f | 4825 | fastop(ctxt, em_add); |
92f738a5 | 4826 | /* Write back the register source. */ |
9dac77fa AK |
4827 | ctxt->src.val = ctxt->dst.orig_val; |
4828 | write_register_operand(&ctxt->src); | |
92f738a5 | 4829 | break; |
a012e65a | 4830 | case 0xc3: /* movnti */ |
9dac77fa AK |
4831 | ctxt->dst.bytes = ctxt->op_bytes; |
4832 | ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : | |
4833 | (u64) ctxt->src.val; | |
a012e65a | 4834 | break; |
91269b8f AK |
4835 | default: |
4836 | goto cannot_emulate; | |
6aa8b732 | 4837 | } |
7d9ddaed AK |
4838 | |
4839 | if (rc != X86EMUL_CONTINUE) | |
4840 | goto done; | |
4841 | ||
6aa8b732 AK |
4842 | goto writeback; |
4843 | ||
4844 | cannot_emulate: | |
a0c0ab2f | 4845 | return EMULATION_FAILED; |
6aa8b732 | 4846 | } |
dd856efa AK |
4847 | |
4848 | void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) | |
4849 | { | |
4850 | invalidate_registers(ctxt); | |
4851 | } | |
4852 | ||
4853 | void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) | |
4854 | { | |
4855 | writeback_registers(ctxt); | |
4856 | } |