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KVM: x86: mmu: replace assertions with MMU_WARN_ON, a conditional WARN_ON
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 126#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
221192bd 127#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 128/* Generic ModRM decode. */
129#define ModRM (1<<19)
130/* Destination is only written; never read. */
131#define Mov (1<<20)
d8769fed 132/* Misc flags */
8ea7d6ae 133#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 134#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 135#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 136#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 137#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 138#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 139#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 140#define No64 (1<<28)
d5ae7ce8 141#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 142#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 143/* Source 2 operand type */
0b789eee 144#define Src2Shift (31)
4dd6a57d 145#define Src2None (OpNone << Src2Shift)
ab2c5ce6 146#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 147#define Src2CL (OpCL << Src2Shift)
148#define Src2ImmByte (OpImmByte << Src2Shift)
149#define Src2One (OpOne << Src2Shift)
150#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 151#define Src2ES (OpES << Src2Shift)
152#define Src2CS (OpCS << Src2Shift)
153#define Src2SS (OpSS << Src2Shift)
154#define Src2DS (OpDS << Src2Shift)
155#define Src2FS (OpFS << Src2Shift)
156#define Src2GS (OpGS << Src2Shift)
4dd6a57d 157#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 158#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 159#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
160#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
161#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 162#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 163#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 164#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 165#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 166#define Intercept ((u64)1 << 48) /* Has valid intercept field */
167#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 168#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 169#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 170#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 171#define No16 ((u64)1 << 53) /* No 16 bit operand */
6aa8b732 172
820207c8 173#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 174
d0e53325
AK		 175#define X2(x...) x, x
176#define X3(x...) X2(x), x
177#define X4(x...) X2(x), X2(x)
178#define X5(x...) X4(x), x
179#define X6(x...) X4(x), X2(x)
180#define X7(x...) X4(x), X3(x)
181#define X8(x...) X4(x), X4(x)
182#define X16(x...) X8(x), X8(x)
83babbca 183
e28bbd44
AK		 184#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
185#define FASTOP_SIZE 8
186
187/*
188 * fastop functions have a special calling convention:
189 *
017da7b6
AK		 190 * dst: rax (in/out)
191 * src: rdx (in/out)
e28bbd44
AK		 192 * src2: rcx (in)
193 * flags: rflags (in/out)
b8c0b6ae 194 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 195 *
196 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
197 * different operand sizes can be reached by calculation, rather than a jump
198 * table (which would be bigger than the code).
199 *
200 * fastop functions are declared as taking a never-defined fastop parameter,
201 * so they can't be called from C directly.
202 */
203
204struct fastop;
205
d65b1dee 206struct opcode {
b1ea50b2
AK		 207 u64 flags : 56;
208 u64 intercept : 8;
120df890 209 union {
ef65c889 210 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 211 const struct opcode *group;
212 const struct group_dual *gdual;
213 const struct gprefix *gprefix;
045a282c 214 const struct escape *esc;
39f062ff 215 const struct instr_dual *idual;
e28bbd44 216 void (*fastop)(struct fastop *fake);
120df890 217 } u;
d09beabd 218 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 219};
220
221struct group_dual {
222 struct opcode mod012[8];
223 struct opcode mod3[8];
d65b1dee
AK		 224};
225
0d7cdee8
AK		 226struct gprefix {
227 struct opcode pfx_no;
228 struct opcode pfx_66;
229 struct opcode pfx_f2;
230 struct opcode pfx_f3;
231};
232
045a282c
GN		 233struct escape {
234 struct opcode op[8];
235 struct opcode high[64];
236};
237
39f062ff
NA		 238struct instr_dual {
239 struct opcode mod012;
240 struct opcode mod3;
241};
242
6aa8b732 243/* EFLAGS bit definitions. */
d4c6a154
GN		 244#define EFLG_ID (1<<21)
245#define EFLG_VIP (1<<20)
246#define EFLG_VIF (1<<19)
247#define EFLG_AC (1<<18)
b1d86143
AP		 248#define EFLG_VM (1<<17)
249#define EFLG_RF (1<<16)
d4c6a154
GN		 250#define EFLG_IOPL (3<<12)
251#define EFLG_NT (1<<14)
6aa8b732
AK		 252#define EFLG_OF (1<<11)
253#define EFLG_DF (1<<10)
b1d86143 254#define EFLG_IF (1<<9)
d4c6a154 255#define EFLG_TF (1<<8)
6aa8b732
AK		 256#define EFLG_SF (1<<7)
257#define EFLG_ZF (1<<6)
258#define EFLG_AF (1<<4)
259#define EFLG_PF (1<<2)
260#define EFLG_CF (1<<0)
261
62bd430e
MG		 262#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
263#define EFLG_RESERVED_ONE_MASK 2
264
dd856efa
AK		 265static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 if (!(ctxt->regs_valid & (1 << nr))) {
268 ctxt->regs_valid |= 1 << nr;
269 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
270 }
271 return ctxt->_regs[nr];
272}
273
274static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 ctxt->regs_valid |= 1 << nr;
277 ctxt->regs_dirty |= 1 << nr;
278 return &ctxt->_regs[nr];
279}
280
281static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
282{
283 reg_read(ctxt, nr);
284 return reg_write(ctxt, nr);
285}
286
287static void writeback_registers(struct x86_emulate_ctxt *ctxt)
288{
289 unsigned reg;
290
291 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
292 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
293}
294
295static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
296{
297 ctxt->regs_dirty = 0;
298 ctxt->regs_valid = 0;
299}
300
6aa8b732
AK		 301/*
302 * These EFLAGS bits are restored from saved value during emulation, and
303 * any changes are written back to the saved value after emulation.
304 */
305#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
306
dda96d8f
AK		 307#ifdef CONFIG_X86_64
308#define ON64(x) x
309#else
310#define ON64(x)
311#endif
312
4d758349
AK		 313static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
314
b7d491e7
AK		 315#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
316#define FOP_RET "ret \n\t"
317
318#define FOP_START(op) \
319 extern void em_##op(struct fastop *fake); \
320 asm(".pushsection .text, \"ax\" \n\t" \
321 ".global em_" #op " \n\t" \
322 FOP_ALIGN \
323 "em_" #op ": \n\t"
324
325#define FOP_END \
326 ".popsection")
327
0bdea068
AK		 328#define FOPNOP() FOP_ALIGN FOP_RET
329
b7d491e7 330#define FOP1E(op, dst) \
b8c0b6ae
AK		 331 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
332
333#define FOP1EEX(op, dst) \
334 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 335
336#define FASTOP1(op) \
337 FOP_START(op) \
338 FOP1E(op##b, al) \
339 FOP1E(op##w, ax) \
340 FOP1E(op##l, eax) \
341 ON64(FOP1E(op##q, rax)) \
342 FOP_END
343
b9fa409b
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m) */
345#define FASTOP1SRC2(op, name) \
346 FOP_START(name) \
347 FOP1E(op, cl) \
348 FOP1E(op, cx) \
349 FOP1E(op, ecx) \
350 ON64(FOP1E(op, rcx)) \
351 FOP_END
352
b8c0b6ae
AK		 353/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
354#define FASTOP1SRC2EX(op, name) \
355 FOP_START(name) \
356 FOP1EEX(op, cl) \
357 FOP1EEX(op, cx) \
358 FOP1EEX(op, ecx) \
359 ON64(FOP1EEX(op, rcx)) \
360 FOP_END
361
f7857f35
AK		 362#define FOP2E(op, dst, src) \
363 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
364
365#define FASTOP2(op) \
366 FOP_START(op) \
017da7b6
AK		 367 FOP2E(op##b, al, dl) \
368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 371 FOP_END
372
11c363ba
AK		 373/* 2 operand, word only */
374#define FASTOP2W(op) \
375 FOP_START(op) \
376 FOPNOP() \
017da7b6
AK		 377 FOP2E(op##w, ax, dx) \
378 FOP2E(op##l, eax, edx) \
379 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 380 FOP_END
381
007a3b54
AK		 382/* 2 operand, src is CL */
383#define FASTOP2CL(op) \
384 FOP_START(op) \
385 FOP2E(op##b, al, cl) \
386 FOP2E(op##w, ax, cl) \
387 FOP2E(op##l, eax, cl) \
388 ON64(FOP2E(op##q, rax, cl)) \
389 FOP_END
390
5aca3722
NA		 391/* 2 operand, src and dest are reversed */
392#define FASTOP2R(op, name) \
393 FOP_START(name) \
394 FOP2E(op##b, dl, al) \
395 FOP2E(op##w, dx, ax) \
396 FOP2E(op##l, edx, eax) \
397 ON64(FOP2E(op##q, rdx, rax)) \
398 FOP_END
399
0bdea068
AK		 400#define FOP3E(op, dst, src, src2) \
401 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
402
403/* 3-operand, word-only, src2=cl */
404#define FASTOP3WCL(op) \
405 FOP_START(op) \
406 FOPNOP() \
017da7b6
AK		 407 FOP3E(op##w, ax, dx, cl) \
408 FOP3E(op##l, eax, edx, cl) \
409 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 410 FOP_END
411
9ae9feba
AK		 412/* Special case for SETcc - 1 instruction per cc */
413#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
414
b8c0b6ae
AK		 415asm(".global kvm_fastop_exception \n"
416 "kvm_fastop_exception: xor %esi, %esi; ret");
417
9ae9feba
AK		 418FOP_START(setcc)
419FOP_SETCC(seto)
420FOP_SETCC(setno)
421FOP_SETCC(setc)
422FOP_SETCC(setnc)
423FOP_SETCC(setz)
424FOP_SETCC(setnz)
425FOP_SETCC(setbe)
426FOP_SETCC(setnbe)
427FOP_SETCC(sets)
428FOP_SETCC(setns)
429FOP_SETCC(setp)
430FOP_SETCC(setnp)
431FOP_SETCC(setl)
432FOP_SETCC(setnl)
433FOP_SETCC(setle)
434FOP_SETCC(setnle)
435FOP_END;
436
326f578f
PB		 437FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
438FOP_END;
439
8a76d7f2
JR		 440static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
441 enum x86_intercept intercept,
442 enum x86_intercept_stage stage)
443{
444 struct x86_instruction_info info = {
445 .intercept = intercept,
9dac77fa
AK		 446 .rep_prefix = ctxt->rep_prefix,
447 .modrm_mod = ctxt->modrm_mod,
448 .modrm_reg = ctxt->modrm_reg,
449 .modrm_rm = ctxt->modrm_rm,
450 .src_val = ctxt->src.val64,
6cbc5f5a 451 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 452 .src_bytes = ctxt->src.bytes,
453 .dst_bytes = ctxt->dst.bytes,
454 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 455 .next_rip = ctxt->eip,
456 };
457
2953538e 458 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 459}
460
f47cfa31
AK		 461static void assign_masked(ulong *dest, ulong src, ulong mask)
462{
463 *dest = (*dest & ~mask) | (src & mask);
464}
465
9dac77fa 466static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 467{
9dac77fa 468 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 469}
470
f47cfa31
AK		 471static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
472{
473 u16 sel;
474 struct desc_struct ss;
475
476 if (ctxt->mode == X86EMUL_MODE_PROT64)
477 return ~0UL;
478 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
479 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
480}
481
612e89f0
AK		 482static int stack_size(struct x86_emulate_ctxt *ctxt)
483{
484 return (__fls(stack_mask(ctxt)) + 1) >> 3;
485}
486
6aa8b732 487/* Access/update address held in a register, based on addressing mode. */
e4706772 488static inline unsigned long
9dac77fa 489address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 490{
9dac77fa 491 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 492 return reg;
493 else
9dac77fa 494 return reg & ad_mask(ctxt);
e4706772
HH		 495}
496
497static inline unsigned long
01485a22 498register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 499{
01485a22 500 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 501}
502
5ad105e5
AK		 503static void masked_increment(ulong *reg, ulong mask, int inc)
504{
505 assign_masked(reg, *reg + inc, mask);
506}
507
7a957275 508static inline void
01485a22 509register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 510{
5ad105e5
AK		 511 ulong mask;
512
9dac77fa 513 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 514 mask = ~0UL;
7a957275 515 else
5ad105e5 516 mask = ad_mask(ctxt);
01485a22 517 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 518}
519
520static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
521{
dd856efa 522 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 523}
6aa8b732 524
56697687
AK		 525static u32 desc_limit_scaled(struct desc_struct *desc)
526{
527 u32 limit = get_desc_limit(desc);
528
529 return desc->g ? (limit << 12) | 0xfff : limit;
530}
531
7b105ca2 532static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 533{
534 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
535 return 0;
536
7b105ca2 537 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 538}
539
35d3d4a1
AK		 540static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
541 u32 error, bool valid)
54b8486f 542{
e0ad0b47 543 WARN_ON(vec > 0x1f);
da9cb575
AK		 544 ctxt->exception.vector = vec;
545 ctxt->exception.error_code = error;
546 ctxt->exception.error_code_valid = valid;
35d3d4a1 547 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 548}
549
3b88e41a
JR		 550static int emulate_db(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, DB_VECTOR, 0, false);
553}
554
35d3d4a1 555static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 556{
35d3d4a1 557 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 558}
559
618ff15d
AK		 560static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
561{
562 return emulate_exception(ctxt, SS_VECTOR, err, true);
563}
564
35d3d4a1 565static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 566{
35d3d4a1 567 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 568}
569
35d3d4a1 570static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 571{
35d3d4a1 572 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 573}
574
34d1f490
AK		 575static int emulate_de(struct x86_emulate_ctxt *ctxt)
576{
35d3d4a1 577 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 578}
579
1253791d
AK		 580static int emulate_nm(struct x86_emulate_ctxt *ctxt)
581{
582 return emulate_exception(ctxt, NM_VECTOR, 0, false);
583}
584
1aa36616
AK		 585static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
586{
587 u16 selector;
588 struct desc_struct desc;
589
590 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
591 return selector;
592}
593
594static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
595 unsigned seg)
596{
597 u16 dummy;
598 u32 base3;
599 struct desc_struct desc;
600
601 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
602 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
603}
604
1c11b376
AK		 605/*
606 * x86 defines three classes of vector instructions: explicitly
607 * aligned, explicitly unaligned, and the rest, which change behaviour
608 * depending on whether they're AVX encoded or not.
609 *
610 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
611 * subject to the same check.
612 */
613static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
614{
615 if (likely(size < 16))
616 return false;
617
618 if (ctxt->d & Aligned)
619 return true;
620 else if (ctxt->d & Unaligned)
621 return false;
622 else if (ctxt->d & Avx)
623 return false;
624 else
625 return true;
626}
627
d09155d2
PB		 628static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned *max_size, unsigned size,
631 bool write, bool fetch,
d50eaa18 632 enum x86emul_mode mode, ulong *linear)
52fd8b44 633{
618ff15d
AK		 634 struct desc_struct desc;
635 bool usable;
52fd8b44 636 ulong la;
618ff15d 637 u32 lim;
1aa36616 638 u16 sel;
52fd8b44 639
7b105ca2 640 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 641 *max_size = 0;
d50eaa18 642 switch (mode) {
618ff15d 643 case X86EMUL_MODE_PROT64:
4be4de7e 644 if (is_noncanonical_address(la))
abc7d8a4 645 goto bad;
fd56e154
PB		 646
647 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
648 if (size > *max_size)
649 goto bad;
618ff15d
AK		 650 break;
651 default:
1aa36616
AK		 652 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
653 addr.seg);
618ff15d
AK		 654 if (!usable)
655 goto bad;
58b7825b
GN		 656 /* code segment in protected mode or read-only data segment */
657 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
658 || !(desc.type & 2)) && write)
618ff15d
AK		 659 goto bad;
660 /* unreadable code segment */
3d9b938e 661 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 662 goto bad;
663 lim = desc_limit_scaled(&desc);
997b0412 664 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 665 /* expand-down segment */
fd56e154 666 if (addr.ea <= lim)
618ff15d
AK		 667 goto bad;
668 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 669 }
997b0412
PB		 670 if (addr.ea > lim)
671 goto bad;
672 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 673 if (size > *max_size)
674 goto bad;
31ff6488 675 la &= (u32)-1;
618ff15d
AK		 676 break;
677 }
1c11b376
AK		 678 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
679 return emulate_gp(ctxt, 0);
52fd8b44
AK		 680 *linear = la;
681 return X86EMUL_CONTINUE;
618ff15d
AK		 682bad:
683 if (addr.seg == VCPU_SREG_SS)
3606189f 684 return emulate_ss(ctxt, 0);
618ff15d 685 else
3606189f 686 return emulate_gp(ctxt, 0);
52fd8b44
AK		 687}
688
3d9b938e
NE		 689static int linearize(struct x86_emulate_ctxt *ctxt,
690 struct segmented_address addr,
691 unsigned size, bool write,
692 ulong *linear)
693{
fd56e154 694 unsigned max_size;
d50eaa18
NA		 695 return __linearize(ctxt, addr, &max_size, size, write, false,
696 ctxt->mode, linear);
3d9b938e
NE		 697}
698
d50eaa18
NA		 699static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
700 enum x86emul_mode mode)
701{
702 ulong linear;
703 int rc;
704 unsigned max_size;
705 struct segmented_address addr = { .seg = VCPU_SREG_CS,
706 .ea = dst };
707
708 if (ctxt->op_bytes != sizeof(unsigned long))
709 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
710 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
711 if (rc == X86EMUL_CONTINUE)
712 ctxt->_eip = addr.ea;
713 return rc;
714}
715
716static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
717{
718 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 719}
720
d50eaa18
NA		 721static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
722 const struct desc_struct *cs_desc)
723{
724 enum x86emul_mode mode = ctxt->mode;
725
726#ifdef CONFIG_X86_64
727 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
728 u64 efer = 0;
729
730 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
731 if (efer & EFER_LMA)
732 mode = X86EMUL_MODE_PROT64;
733 }
734#endif
735 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
736 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
737 return assign_eip(ctxt, dst, mode);
738}
739
740static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
741{
742 return assign_eip_near(ctxt, ctxt->_eip + rel);
743}
3d9b938e 744
3ca3ac4d
AK		 745static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
746 struct segmented_address addr,
747 void *data,
748 unsigned size)
749{
9fa088f4
AK		 750 int rc;
751 ulong linear;
752
83b8795a 753 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 754 if (rc != X86EMUL_CONTINUE)
755 return rc;
0f65dd70 756 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 757}
758
807941b1 759/*
285ca9e9 760 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 761 * boundary if they are not in fetch_cache yet.
762 */
9506d57d 763static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 764{
62266869 765 int rc;
fd56e154 766 unsigned size, max_size;
285ca9e9 767 unsigned long linear;
17052f16 768 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 769 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 770 .ea = ctxt->eip + cur_size };
771
fd56e154
PB		 772 /*
773 * We do not know exactly how many bytes will be needed, and
774 * __linearize is expensive, so fetch as much as possible. We
775 * just have to avoid going beyond the 15 byte limit, the end
776 * of the segment, or the end of the page.
777 *
778 * __linearize is called with size 0 so that it does not do any
779 * boundary check itself. Instead, we use max_size to check
780 * against op_size.
781 */
d50eaa18
NA		 782 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
783 &linear);
719d5a9b
PB		 784 if (unlikely(rc != X86EMUL_CONTINUE))
785 return rc;
786
fd56e154 787 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 788 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 789
790 /*
791 * One instruction can only straddle two pages,
792 * and one has been loaded at the beginning of
793 * x86_decode_insn. So, if not enough bytes
794 * still, we must have hit the 15-byte boundary.
795 */
796 if (unlikely(size < op_size))
fd56e154
PB		 797 return emulate_gp(ctxt, 0);
798
17052f16 799 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 800 size, &ctxt->exception);
801 if (unlikely(rc != X86EMUL_CONTINUE))
802 return rc;
17052f16 803 ctxt->fetch.end += size;
3e2815e9 804 return X86EMUL_CONTINUE;
62266869
AK		 805}
806
9506d57d
PB		 807static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
808 unsigned size)
62266869 809{
08da44ae
NA		 810 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
811
812 if (unlikely(done_size < size))
813 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 814 else
815 return X86EMUL_CONTINUE;
62266869
AK		 816}
817
67cbc90d 818/* Fetch next part of the instruction being emulated. */
e85a1085 819#define insn_fetch(_type, _ctxt) \
9506d57d 820({ _type _x; \
9506d57d
PB		 821 \
822 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 823 if (rc != X86EMUL_CONTINUE) \
824 goto done; \
9506d57d 825 ctxt->_eip += sizeof(_type); \
17052f16
PB		 826 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
827 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 828 _x; \
67cbc90d
TY		 829})
830
807941b1 831#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 832({ \
9506d57d 833 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 834 if (rc != X86EMUL_CONTINUE) \
835 goto done; \
9506d57d 836 ctxt->_eip += (_size); \
17052f16
PB		 837 memcpy(_arr, ctxt->fetch.ptr, _size); \
838 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 839})
840
1e3c5cb0
RR		 841/*
842 * Given the 'reg' portion of a ModRM byte, and a register block, return a
843 * pointer into the block that addresses the relevant register.
844 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
845 */
dd856efa 846static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 847 int byteop)
6aa8b732
AK		 848{
849 void *p;
aa9ac1a6 850 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 851
6aa8b732 852 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 853 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
854 else
855 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 856 return p;
857}
858
859static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 860 struct segmented_address addr,
6aa8b732
AK		 861 u16 *size, unsigned long *address, int op_bytes)
862{
863 int rc;
864
865 if (op_bytes == 2)
866 op_bytes = 3;
867 *address = 0;
3ca3ac4d 868 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 869 if (rc != X86EMUL_CONTINUE)
6aa8b732 870 return rc;
30b31ab6 871 addr.ea += 2;
3ca3ac4d 872 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 873 return rc;
874}
875
34b77652
AK		 876FASTOP2(add);
877FASTOP2(or);
878FASTOP2(adc);
879FASTOP2(sbb);
880FASTOP2(and);
881FASTOP2(sub);
882FASTOP2(xor);
883FASTOP2(cmp);
884FASTOP2(test);
885
b9fa409b
AK		 886FASTOP1SRC2(mul, mul_ex);
887FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 888FASTOP1SRC2EX(div, div_ex);
889FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 890
34b77652
AK		 891FASTOP3WCL(shld);
892FASTOP3WCL(shrd);
893
894FASTOP2W(imul);
895
896FASTOP1(not);
897FASTOP1(neg);
898FASTOP1(inc);
899FASTOP1(dec);
900
901FASTOP2CL(rol);
902FASTOP2CL(ror);
903FASTOP2CL(rcl);
904FASTOP2CL(rcr);
905FASTOP2CL(shl);
906FASTOP2CL(shr);
907FASTOP2CL(sar);
908
909FASTOP2W(bsf);
910FASTOP2W(bsr);
911FASTOP2W(bt);
912FASTOP2W(bts);
913FASTOP2W(btr);
914FASTOP2W(btc);
915
e47a5f5f
AK		 916FASTOP2(xadd);
917
5aca3722
NA		 918FASTOP2R(cmp, cmp_r);
919
9ae9feba 920static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 921{
9ae9feba
AK		 922 u8 rc;
923 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 924
9ae9feba 925 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 926 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 927 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
928 return rc;
bbe9abbd
NK		 929}
930
91ff3cb4
AK		 931static void fetch_register_operand(struct operand *op)
932{
933 switch (op->bytes) {
934 case 1:
935 op->val = *(u8 *)op->addr.reg;
936 break;
937 case 2:
938 op->val = *(u16 *)op->addr.reg;
939 break;
940 case 4:
941 op->val = *(u32 *)op->addr.reg;
942 break;
943 case 8:
944 op->val = *(u64 *)op->addr.reg;
945 break;
946 }
947}
948
1253791d
AK		 949static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
950{
951 ctxt->ops->get_fpu(ctxt);
952 switch (reg) {
89a87c67
MK		 953 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
954 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
955 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
956 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
957 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
958 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
959 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
960 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 961#ifdef CONFIG_X86_64
89a87c67
MK		 962 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
963 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
964 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
965 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
966 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
967 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
968 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
969 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 970#endif
971 default: BUG();
972 }
973 ctxt->ops->put_fpu(ctxt);
974}
975
976static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
977 int reg)
978{
979 ctxt->ops->get_fpu(ctxt);
980 switch (reg) {
89a87c67
MK		 981 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
982 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
983 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
984 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
985 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
986 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
987 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
988 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 989#ifdef CONFIG_X86_64
89a87c67
MK		 990 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
991 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
992 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
993 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
994 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
995 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
996 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
997 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 998#endif
999 default: BUG();
1000 }
1001 ctxt->ops->put_fpu(ctxt);
1002}
1003
cbe2c9d3
AK		 1004static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1005{
1006 ctxt->ops->get_fpu(ctxt);
1007 switch (reg) {
1008 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1009 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1010 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1011 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1012 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1013 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1014 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1015 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1016 default: BUG();
1017 }
1018 ctxt->ops->put_fpu(ctxt);
1019}
1020
1021static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1022{
1023 ctxt->ops->get_fpu(ctxt);
1024 switch (reg) {
1025 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1026 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1027 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1028 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1029 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1030 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1031 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1032 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1033 default: BUG();
1034 }
1035 ctxt->ops->put_fpu(ctxt);
1036}
1037
045a282c
GN		 1038static int em_fninit(struct x86_emulate_ctxt *ctxt)
1039{
1040 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1041 return emulate_nm(ctxt);
1042
1043 ctxt->ops->get_fpu(ctxt);
1044 asm volatile("fninit");
1045 ctxt->ops->put_fpu(ctxt);
1046 return X86EMUL_CONTINUE;
1047}
1048
1049static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1050{
1051 u16 fcw;
1052
1053 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1054 return emulate_nm(ctxt);
1055
1056 ctxt->ops->get_fpu(ctxt);
1057 asm volatile("fnstcw %0": "+m"(fcw));
1058 ctxt->ops->put_fpu(ctxt);
1059
1060 /* force 2 byte destination */
1061 ctxt->dst.bytes = 2;
1062 ctxt->dst.val = fcw;
1063
1064 return X86EMUL_CONTINUE;
1065}
1066
1067static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1068{
1069 u16 fsw;
1070
1071 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1072 return emulate_nm(ctxt);
1073
1074 ctxt->ops->get_fpu(ctxt);
1075 asm volatile("fnstsw %0": "+m"(fsw));
1076 ctxt->ops->put_fpu(ctxt);
1077
1078 /* force 2 byte destination */
1079 ctxt->dst.bytes = 2;
1080 ctxt->dst.val = fsw;
1081
1082 return X86EMUL_CONTINUE;
1083}
1084
1253791d 1085static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1086 struct operand *op)
3c118e24 1087{
9dac77fa 1088 unsigned reg = ctxt->modrm_reg;
33615aa9 1089
9dac77fa
AK		 1090 if (!(ctxt->d & ModRM))
1091 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1092
9dac77fa 1093 if (ctxt->d & Sse) {
1253791d
AK		 1094 op->type = OP_XMM;
1095 op->bytes = 16;
1096 op->addr.xmm = reg;
1097 read_sse_reg(ctxt, &op->vec_val, reg);
1098 return;
1099 }
cbe2c9d3
AK		 1100 if (ctxt->d & Mmx) {
1101 reg &= 7;
1102 op->type = OP_MM;
1103 op->bytes = 8;
1104 op->addr.mm = reg;
1105 return;
1106 }
1253791d 1107
3c118e24 1108 op->type = OP_REG;
6d4d85ec
GN		 1109 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1110 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1111
91ff3cb4 1112 fetch_register_operand(op);
3c118e24
AK		 1113 op->orig_val = op->val;
1114}
1115
a6e3407b
AK		 1116static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1117{
1118 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1119 ctxt->modrm_seg = VCPU_SREG_SS;
1120}
1121
1c73ef66 1122static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1123 struct operand *op)
1c73ef66 1124{
1c73ef66 1125 u8 sib;
02357bdc 1126 int index_reg, base_reg, scale;
3e2815e9 1127 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1128 ulong modrm_ea = 0;
1c73ef66 1129
02357bdc
BD		 1130 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1131 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1132 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1133
02357bdc 1134 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1135 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1136 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1137 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1138
9b88ae99 1139 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1140 op->type = OP_REG;
9dac77fa 1141 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1142 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1143 ctxt->d & ByteOp);
9dac77fa 1144 if (ctxt->d & Sse) {
1253791d
AK		 1145 op->type = OP_XMM;
1146 op->bytes = 16;
9dac77fa
AK		 1147 op->addr.xmm = ctxt->modrm_rm;
1148 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1149 return rc;
1150 }
cbe2c9d3
AK		 1151 if (ctxt->d & Mmx) {
1152 op->type = OP_MM;
1153 op->bytes = 8;
bdc90722 1154 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1155 return rc;
1156 }
2dbd0dd7 1157 fetch_register_operand(op);
1c73ef66
AK		 1158 return rc;
1159 }
1160
2dbd0dd7
AK		 1161 op->type = OP_MEM;
1162
9dac77fa 1163 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1164 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1165 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1166 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1167 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1168
1169 /* 16-bit ModR/M decode. */
9dac77fa 1170 switch (ctxt->modrm_mod) {
1c73ef66 1171 case 0:
9dac77fa 1172 if (ctxt->modrm_rm == 6)
e85a1085 1173 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1174 break;
1175 case 1:
e85a1085 1176 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1177 break;
1178 case 2:
e85a1085 1179 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1180 break;
1181 }
9dac77fa 1182 switch (ctxt->modrm_rm) {
1c73ef66 1183 case 0:
2dbd0dd7 1184 modrm_ea += bx + si;
1c73ef66
AK		 1185 break;
1186 case 1:
2dbd0dd7 1187 modrm_ea += bx + di;
1c73ef66
AK		 1188 break;
1189 case 2:
2dbd0dd7 1190 modrm_ea += bp + si;
1c73ef66
AK		 1191 break;
1192 case 3:
2dbd0dd7 1193 modrm_ea += bp + di;
1c73ef66
AK		 1194 break;
1195 case 4:
2dbd0dd7 1196 modrm_ea += si;
1c73ef66
AK		 1197 break;
1198 case 5:
2dbd0dd7 1199 modrm_ea += di;
1c73ef66
AK		 1200 break;
1201 case 6:
9dac77fa 1202 if (ctxt->modrm_mod != 0)
2dbd0dd7 1203 modrm_ea += bp;
1c73ef66
AK		 1204 break;
1205 case 7:
2dbd0dd7 1206 modrm_ea += bx;
1c73ef66
AK		 1207 break;
1208 }
9dac77fa
AK		 1209 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1210 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1211 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1212 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1213 } else {
1214 /* 32/64-bit ModR/M decode. */
9dac77fa 1215 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1216 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1217 index_reg |= (sib >> 3) & 7;
1218 base_reg |= sib & 7;
1219 scale = sib >> 6;
1220
9dac77fa 1221 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1222 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1223 else {
dd856efa 1224 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1225 adjust_modrm_seg(ctxt, base_reg);
1226 }
dc71d0f1 1227 if (index_reg != 4)
dd856efa 1228 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1229 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1230 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1231 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1232 ctxt->rip_relative = 1;
a6e3407b
AK		 1233 } else {
1234 base_reg = ctxt->modrm_rm;
dd856efa 1235 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1236 adjust_modrm_seg(ctxt, base_reg);
1237 }
9dac77fa 1238 switch (ctxt->modrm_mod) {
1c73ef66 1239 case 1:
e85a1085 1240 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1241 break;
1242 case 2:
e85a1085 1243 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1244 break;
1245 }
1246 }
90de84f5 1247 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1248 if (ctxt->ad_bytes != 8)
1249 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1250
1c73ef66
AK		 1251done:
1252 return rc;
1253}
1254
1255static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1256 struct operand *op)
1c73ef66 1257{
3e2815e9 1258 int rc = X86EMUL_CONTINUE;
1c73ef66 1259
2dbd0dd7 1260 op->type = OP_MEM;
9dac77fa 1261 switch (ctxt->ad_bytes) {
1c73ef66 1262 case 2:
e85a1085 1263 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1264 break;
1265 case 4:
e85a1085 1266 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1267 break;
1268 case 8:
e85a1085 1269 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1270 break;
1271 }
1272done:
1273 return rc;
1274}
1275
9dac77fa 1276static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1277{
7129eeca 1278 long sv = 0, mask;
35c843c4 1279
9dac77fa 1280 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1281 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1282
9dac77fa
AK		 1283 if (ctxt->src.bytes == 2)
1284 sv = (s16)ctxt->src.val & (s16)mask;
1285 else if (ctxt->src.bytes == 4)
1286 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1287 else
1288 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1289
1c1c35ae
NA		 1290 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1291 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1292 }
ba7ff2b7
WY		 1293
1294 /* only subword offset */
9dac77fa 1295 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1296}
1297
dde7e6d1 1298static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1299 unsigned long addr, void *dest, unsigned size)
6aa8b732 1300{
dde7e6d1 1301 int rc;
9dac77fa 1302 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1303
f23b070e
XG		 1304 if (mc->pos < mc->end)
1305 goto read_cached;
6aa8b732 1306
f23b070e
XG		 1307 WARN_ON((mc->end + size) >= sizeof(mc->data));
1308
1309 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1310 &ctxt->exception);
1311 if (rc != X86EMUL_CONTINUE)
1312 return rc;
1313
1314 mc->end += size;
1315
1316read_cached:
1317 memcpy(dest, mc->data + mc->pos, size);
1318 mc->pos += size;
dde7e6d1
AK		 1319 return X86EMUL_CONTINUE;
1320}
6aa8b732 1321
3ca3ac4d
AK		 1322static int segmented_read(struct x86_emulate_ctxt *ctxt,
1323 struct segmented_address addr,
1324 void *data,
1325 unsigned size)
1326{
9fa088f4
AK		 1327 int rc;
1328 ulong linear;
1329
83b8795a 1330 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1331 if (rc != X86EMUL_CONTINUE)
1332 return rc;
7b105ca2 1333 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1334}
1335
1336static int segmented_write(struct x86_emulate_ctxt *ctxt,
1337 struct segmented_address addr,
1338 const void *data,
1339 unsigned size)
1340{
9fa088f4
AK		 1341 int rc;
1342 ulong linear;
1343
83b8795a 1344 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1345 if (rc != X86EMUL_CONTINUE)
1346 return rc;
0f65dd70
AK		 1347 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1348 &ctxt->exception);
3ca3ac4d
AK		 1349}
1350
1351static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1352 struct segmented_address addr,
1353 const void *orig_data, const void *data,
1354 unsigned size)
1355{
9fa088f4
AK		 1356 int rc;
1357 ulong linear;
1358
83b8795a 1359 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1360 if (rc != X86EMUL_CONTINUE)
1361 return rc;
0f65dd70
AK		 1362 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1363 size, &ctxt->exception);
3ca3ac4d
AK		 1364}
1365
dde7e6d1 1366static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1367 unsigned int size, unsigned short port,
1368 void *dest)
1369{
9dac77fa 1370 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1371
dde7e6d1 1372 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1373 unsigned int in_page, n;
9dac77fa 1374 unsigned int count = ctxt->rep_prefix ?
dd856efa 1375 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1376 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1377 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1378 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1379 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1380 if (n == 0)
1381 n = 1;
1382 rc->pos = rc->end = 0;
7b105ca2 1383 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1384 return 0;
1385 rc->end = n * size;
6aa8b732
AK		 1386 }
1387
e6e39f04
NA		 1388 if (ctxt->rep_prefix && (ctxt->d & String) &&
1389 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1390 ctxt->dst.data = rc->data + rc->pos;
1391 ctxt->dst.type = OP_MEM_STR;
1392 ctxt->dst.count = (rc->end - rc->pos) / size;
1393 rc->pos = rc->end;
1394 } else {
1395 memcpy(dest, rc->data + rc->pos, size);
1396 rc->pos += size;
1397 }
dde7e6d1
AK		 1398 return 1;
1399}
6aa8b732 1400
7f3d35fd
KW		 1401static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1402 u16 index, struct desc_struct *desc)
1403{
1404 struct desc_ptr dt;
1405 ulong addr;
1406
1407 ctxt->ops->get_idt(ctxt, &dt);
1408
1409 if (dt.size < index * 8 + 7)
1410 return emulate_gp(ctxt, index << 3 | 0x2);
1411
1412 addr = dt.address + index * 8;
1413 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1414 &ctxt->exception);
1415}
1416
dde7e6d1 1417static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1418 u16 selector, struct desc_ptr *dt)
1419{
0225fb50 1420 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1421 u32 base3 = 0;
7b105ca2 1422
dde7e6d1
AK		 1423 if (selector & 1 << 2) {
1424 struct desc_struct desc;
1aa36616
AK		 1425 u16 sel;
1426
dde7e6d1 1427 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1428 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1429 VCPU_SREG_LDTR))
dde7e6d1 1430 return;
e09d082c 1431
dde7e6d1 1432 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1433 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1434 } else
4bff1e86 1435 ops->get_gdt(ctxt, dt);
dde7e6d1 1436}
120df890 1437
dde7e6d1
AK		 1438/* allowed just for 8 bytes segments */
1439static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1440 u16 selector, struct desc_struct *desc,
1441 ulong *desc_addr_p)
dde7e6d1
AK		 1442{
1443 struct desc_ptr dt;
1444 u16 index = selector >> 3;
dde7e6d1 1445 ulong addr;
120df890 1446
7b105ca2 1447 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1448
35d3d4a1
AK		 1449 if (dt.size < index * 8 + 7)
1450 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1451
e919464b 1452 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1453 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1454 &ctxt->exception);
dde7e6d1 1455}
ef65c889 1456
dde7e6d1
AK		 1457/* allowed just for 8 bytes segments */
1458static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1459 u16 selector, struct desc_struct *desc)
1460{
1461 struct desc_ptr dt;
1462 u16 index = selector >> 3;
dde7e6d1 1463 ulong addr;
6aa8b732 1464
7b105ca2 1465 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1466
35d3d4a1
AK		 1467 if (dt.size < index * 8 + 7)
1468 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1469
dde7e6d1 1470 addr = dt.address + index * 8;
7b105ca2
TY		 1471 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1472 &ctxt->exception);
dde7e6d1 1473}
c7e75a3d 1474
5601d05b 1475/* Does not support long mode */
2356aaeb 1476static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1477 u16 selector, int seg, u8 cpl,
1478 bool in_task_switch,
1479 struct desc_struct *desc)
dde7e6d1 1480{
869be99c 1481 struct desc_struct seg_desc, old_desc;
2356aaeb 1482 u8 dpl, rpl;
dde7e6d1
AK		 1483 unsigned err_vec = GP_VECTOR;
1484 u32 err_code = 0;
1485 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1486 ulong desc_addr;
dde7e6d1 1487 int ret;
03ebebeb 1488 u16 dummy;
e37a75a1 1489 u32 base3 = 0;
69f55cb1 1490
dde7e6d1 1491 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1492
f8da94e9
KW		 1493 if (ctxt->mode == X86EMUL_MODE_REAL) {
1494 /* set real mode segment descriptor (keep limit etc. for
1495 * unreal mode) */
03ebebeb 1496 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1497 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1498 goto load;
f8da94e9
KW		 1499 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1500 /* VM86 needs a clean new segment descriptor */
1501 set_desc_base(&seg_desc, selector << 4);
1502 set_desc_limit(&seg_desc, 0xffff);
1503 seg_desc.type = 3;
1504 seg_desc.p = 1;
1505 seg_desc.s = 1;
1506 seg_desc.dpl = 3;
1507 goto load;
dde7e6d1
AK		 1508 }
1509
79d5b4c3 1510 rpl = selector & 3;
79d5b4c3
AK		 1511
1512 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1513 if ((seg == VCPU_SREG_CS
1514 || (seg == VCPU_SREG_SS
1515 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1516 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1517 && null_selector)
1518 goto exception;
1519
1520 /* TR should be in GDT only */
1521 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1522 goto exception;
1523
1524 if (null_selector) /* for NULL selector skip all following checks */
1525 goto load;
1526
e919464b 1527 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1528 if (ret != X86EMUL_CONTINUE)
1529 return ret;
1530
1531 err_code = selector & 0xfffc;
15fc0752 1532 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1533
fc058680 1534 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1535 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1536 goto exception;
1537
1538 if (!seg_desc.p) {
1539 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1540 goto exception;
1541 }
1542
dde7e6d1 1543 dpl = seg_desc.dpl;
dde7e6d1
AK		 1544
1545 switch (seg) {
1546 case VCPU_SREG_SS:
1547 /*
1548 * segment is not a writable data segment or segment
1549 * selector's RPL != CPL or segment selector's RPL != CPL
1550 */
1551 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1552 goto exception;
6aa8b732 1553 break;
dde7e6d1
AK		 1554 case VCPU_SREG_CS:
1555 if (!(seg_desc.type & 8))
1556 goto exception;
1557
1558 if (seg_desc.type & 4) {
1559 /* conforming */
1560 if (dpl > cpl)
1561 goto exception;
1562 } else {
1563 /* nonconforming */
1564 if (rpl > cpl || dpl != cpl)
1565 goto exception;
1566 }
040c8dc8
NA		 1567 /* in long-mode d/b must be clear if l is set */
1568 if (seg_desc.d && seg_desc.l) {
1569 u64 efer = 0;
1570
1571 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1572 if (efer & EFER_LMA)
1573 goto exception;
1574 }
1575
dde7e6d1
AK		 1576 /* CS(RPL) <- CPL */
1577 selector = (selector & 0xfffc) | cpl;
6aa8b732 1578 break;
dde7e6d1
AK		 1579 case VCPU_SREG_TR:
1580 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1581 goto exception;
869be99c
AK		 1582 old_desc = seg_desc;
1583 seg_desc.type |= 2; /* busy */
1584 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1585 sizeof(seg_desc), &ctxt->exception);
1586 if (ret != X86EMUL_CONTINUE)
1587 return ret;
dde7e6d1
AK		 1588 break;
1589 case VCPU_SREG_LDTR:
1590 if (seg_desc.s || seg_desc.type != 2)
1591 goto exception;
1592 break;
1593 default: /* DS, ES, FS, or GS */
4e62417b 1594 /*
dde7e6d1
AK		 1595 * segment is not a data or readable code segment or
1596 * ((segment is a data or nonconforming code segment)
1597 * and (both RPL and CPL > DPL))
4e62417b 1598 */
dde7e6d1
AK		 1599 if ((seg_desc.type & 0xa) == 0x8 ||
1600 (((seg_desc.type & 0xc) != 0xc) &&
1601 (rpl > dpl && cpl > dpl)))
1602 goto exception;
6aa8b732 1603 break;
dde7e6d1
AK		 1604 }
1605
1606 if (seg_desc.s) {
1607 /* mark segment as accessed */
1608 seg_desc.type |= 1;
7b105ca2 1609 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1610 if (ret != X86EMUL_CONTINUE)
1611 return ret;
e37a75a1
NA		 1612 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1613 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1614 sizeof(base3), &ctxt->exception);
1615 if (ret != X86EMUL_CONTINUE)
1616 return ret;
9a9abf6b
NA		 1617 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1618 ((u64)base3 << 32)))
1619 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1620 }
1621load:
e37a75a1 1622 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1623 if (desc)
1624 *desc = seg_desc;
dde7e6d1
AK		 1625 return X86EMUL_CONTINUE;
1626exception:
592f0858 1627 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1628}
1629
2356aaeb
PB		 1630static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1631 u16 selector, int seg)
1632{
1633 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1634 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1635}
1636
31be40b3
WY		 1637static void write_register_operand(struct operand *op)
1638{
1639 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1640 switch (op->bytes) {
1641 case 1:
1642 *(u8 *)op->addr.reg = (u8)op->val;
1643 break;
1644 case 2:
1645 *(u16 *)op->addr.reg = (u16)op->val;
1646 break;
1647 case 4:
1648 *op->addr.reg = (u32)op->val;
1649 break; /* 64b: zero-extend */
1650 case 8:
1651 *op->addr.reg = op->val;
1652 break;
1653 }
1654}
1655
fb32b1ed 1656static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1657{
fb32b1ed 1658 switch (op->type) {
dde7e6d1 1659 case OP_REG:
fb32b1ed 1660 write_register_operand(op);
6aa8b732 1661 break;
dde7e6d1 1662 case OP_MEM:
9dac77fa 1663 if (ctxt->lock_prefix)
f5f87dfb
PB		 1664 return segmented_cmpxchg(ctxt,
1665 op->addr.mem,
1666 &op->orig_val,
1667 &op->val,
1668 op->bytes);
1669 else
1670 return segmented_write(ctxt,
fb32b1ed 1671 op->addr.mem,
fb32b1ed
AK		 1672 &op->val,
1673 op->bytes);
a682e354 1674 break;
b3356bf0 1675 case OP_MEM_STR:
f5f87dfb
PB		 1676 return segmented_write(ctxt,
1677 op->addr.mem,
1678 op->data,
1679 op->bytes * op->count);
b3356bf0 1680 break;
1253791d 1681 case OP_XMM:
fb32b1ed 1682 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1683 break;
cbe2c9d3 1684 case OP_MM:
fb32b1ed 1685 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1686 break;
dde7e6d1
AK		 1687 case OP_NONE:
1688 /* no writeback */
414e6277 1689 break;
dde7e6d1 1690 default:
414e6277 1691 break;
6aa8b732 1692 }
dde7e6d1
AK		 1693 return X86EMUL_CONTINUE;
1694}
6aa8b732 1695
51ddff50 1696static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1697{
4179bb02 1698 struct segmented_address addr;
0dc8d10f 1699
5ad105e5 1700 rsp_increment(ctxt, -bytes);
dd856efa 1701 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1702 addr.seg = VCPU_SREG_SS;
1703
51ddff50
AK		 1704 return segmented_write(ctxt, addr, data, bytes);
1705}
1706
1707static int em_push(struct x86_emulate_ctxt *ctxt)
1708{
4179bb02 1709 /* Disable writeback. */
9dac77fa 1710 ctxt->dst.type = OP_NONE;
51ddff50 1711 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1712}
69f55cb1 1713
dde7e6d1 1714static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1715 void *dest, int len)
1716{
dde7e6d1 1717 int rc;
90de84f5 1718 struct segmented_address addr;
8b4caf66 1719
dd856efa 1720 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1721 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1722 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1723 if (rc != X86EMUL_CONTINUE)
1724 return rc;
1725
5ad105e5 1726 rsp_increment(ctxt, len);
dde7e6d1 1727 return rc;
8b4caf66
LV		 1728}
1729
c54fe504
TY		 1730static int em_pop(struct x86_emulate_ctxt *ctxt)
1731{
9dac77fa 1732 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1733}
1734
dde7e6d1 1735static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1736 void *dest, int len)
9de41573
GN		 1737{
1738 int rc;
dde7e6d1
AK		 1739 unsigned long val, change_mask;
1740 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1741 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1742
3b9be3bf 1743 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1744 if (rc != X86EMUL_CONTINUE)
1745 return rc;
9de41573 1746
dde7e6d1 1747 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1748 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1749
dde7e6d1
AK		 1750 switch(ctxt->mode) {
1751 case X86EMUL_MODE_PROT64:
1752 case X86EMUL_MODE_PROT32:
1753 case X86EMUL_MODE_PROT16:
1754 if (cpl == 0)
1755 change_mask |= EFLG_IOPL;
1756 if (cpl <= iopl)
1757 change_mask |= EFLG_IF;
1758 break;
1759 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1760 if (iopl < 3)
1761 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1762 change_mask |= EFLG_IF;
1763 break;
1764 default: /* real mode */
1765 change_mask |= (EFLG_IOPL | EFLG_IF);
1766 break;
9de41573 1767 }
dde7e6d1
AK		 1768
1769 *(unsigned long *)dest =
1770 (ctxt->eflags & ~change_mask) | (val & change_mask);
1771
1772 return rc;
9de41573
GN		 1773}
1774
62aaa2f0
TY		 1775static int em_popf(struct x86_emulate_ctxt *ctxt)
1776{
9dac77fa
AK		 1777 ctxt->dst.type = OP_REG;
1778 ctxt->dst.addr.reg = &ctxt->eflags;
1779 ctxt->dst.bytes = ctxt->op_bytes;
1780 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1781}
1782
612e89f0
AK		 1783static int em_enter(struct x86_emulate_ctxt *ctxt)
1784{
1785 int rc;
1786 unsigned frame_size = ctxt->src.val;
1787 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1788 ulong rbp;
612e89f0
AK		 1789
1790 if (nesting_level)
1791 return X86EMUL_UNHANDLEABLE;
1792
dd856efa
AK		 1793 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1794 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1795 if (rc != X86EMUL_CONTINUE)
1796 return rc;
dd856efa 1797 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1798 stack_mask(ctxt));
dd856efa
AK		 1799 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1800 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1801 stack_mask(ctxt));
1802 return X86EMUL_CONTINUE;
1803}
1804
f47cfa31
AK		 1805static int em_leave(struct x86_emulate_ctxt *ctxt)
1806{
dd856efa 1807 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1808 stack_mask(ctxt));
dd856efa 1809 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1810}
1811
1cd196ea 1812static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1813{
1cd196ea
AK		 1814 int seg = ctxt->src2.val;
1815
9dac77fa 1816 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1817 if (ctxt->op_bytes == 4) {
1818 rsp_increment(ctxt, -2);
1819 ctxt->op_bytes = 2;
1820 }
7b262e90 1821
4487b3b4 1822 return em_push(ctxt);
7b262e90
GN		 1823}
1824
1cd196ea 1825static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1826{
1cd196ea 1827 int seg = ctxt->src2.val;
dde7e6d1
AK		 1828 unsigned long selector;
1829 int rc;
38ba30ba 1830
9dac77fa 1831 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1832 if (rc != X86EMUL_CONTINUE)
1833 return rc;
1834
a5457e7b
PB		 1835 if (ctxt->modrm_reg == VCPU_SREG_SS)
1836 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1837
7b105ca2 1838 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1839 return rc;
38ba30ba
GN		 1840}
1841
b96a7fad 1842static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1843{
dd856efa 1844 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1845 int rc = X86EMUL_CONTINUE;
1846 int reg = VCPU_REGS_RAX;
38ba30ba 1847
dde7e6d1
AK		 1848 while (reg <= VCPU_REGS_RDI) {
1849 (reg == VCPU_REGS_RSP) ?
dd856efa 1850 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1851
4487b3b4 1852 rc = em_push(ctxt);
dde7e6d1
AK		 1853 if (rc != X86EMUL_CONTINUE)
1854 return rc;
38ba30ba 1855
dde7e6d1 1856 ++reg;
38ba30ba 1857 }
38ba30ba 1858
dde7e6d1 1859 return rc;
38ba30ba
GN		 1860}
1861
62aaa2f0
TY		 1862static int em_pushf(struct x86_emulate_ctxt *ctxt)
1863{
bc397a6c 1864 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1865 return em_push(ctxt);
1866}
1867
b96a7fad 1868static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1869{
dde7e6d1
AK		 1870 int rc = X86EMUL_CONTINUE;
1871 int reg = VCPU_REGS_RDI;
38ba30ba 1872
dde7e6d1
AK		 1873 while (reg >= VCPU_REGS_RAX) {
1874 if (reg == VCPU_REGS_RSP) {
5ad105e5 1875 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1876 --reg;
1877 }
38ba30ba 1878
dd856efa 1879 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1880 if (rc != X86EMUL_CONTINUE)
1881 break;
1882 --reg;
38ba30ba 1883 }
dde7e6d1 1884 return rc;
38ba30ba
GN		 1885}
1886
dd856efa 1887static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1888{
0225fb50 1889 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1890 int rc;
6e154e56
MG		 1891 struct desc_ptr dt;
1892 gva_t cs_addr;
1893 gva_t eip_addr;
1894 u16 cs, eip;
6e154e56
MG		 1895
1896 /* TODO: Add limit checks */
9dac77fa 1897 ctxt->src.val = ctxt->eflags;
4487b3b4 1898 rc = em_push(ctxt);
5c56e1cf
AK		 1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
6e154e56
MG		 1901
1902 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1903
9dac77fa 1904 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1905 rc = em_push(ctxt);
5c56e1cf
AK		 1906 if (rc != X86EMUL_CONTINUE)
1907 return rc;
6e154e56 1908
9dac77fa 1909 ctxt->src.val = ctxt->_eip;
4487b3b4 1910 rc = em_push(ctxt);
5c56e1cf
AK		 1911 if (rc != X86EMUL_CONTINUE)
1912 return rc;
1913
4bff1e86 1914 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1915
1916 eip_addr = dt.address + (irq << 2);
1917 cs_addr = dt.address + (irq << 2) + 2;
1918
0f65dd70 1919 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1920 if (rc != X86EMUL_CONTINUE)
1921 return rc;
1922
0f65dd70 1923 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1924 if (rc != X86EMUL_CONTINUE)
1925 return rc;
1926
7b105ca2 1927 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1928 if (rc != X86EMUL_CONTINUE)
1929 return rc;
1930
9dac77fa 1931 ctxt->_eip = eip;
6e154e56
MG		 1932
1933 return rc;
1934}
1935
dd856efa
AK		 1936int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1937{
1938 int rc;
1939
1940 invalidate_registers(ctxt);
1941 rc = __emulate_int_real(ctxt, irq);
1942 if (rc == X86EMUL_CONTINUE)
1943 writeback_registers(ctxt);
1944 return rc;
1945}
1946
7b105ca2 1947static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1948{
1949 switch(ctxt->mode) {
1950 case X86EMUL_MODE_REAL:
dd856efa 1951 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1952 case X86EMUL_MODE_VM86:
1953 case X86EMUL_MODE_PROT16:
1954 case X86EMUL_MODE_PROT32:
1955 case X86EMUL_MODE_PROT64:
1956 default:
1957 /* Protected mode interrupts unimplemented yet */
1958 return X86EMUL_UNHANDLEABLE;
1959 }
1960}
1961
7b105ca2 1962static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1963{
dde7e6d1
AK		 1964 int rc = X86EMUL_CONTINUE;
1965 unsigned long temp_eip = 0;
1966 unsigned long temp_eflags = 0;
1967 unsigned long cs = 0;
1968 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1969 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1970 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1971 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1972
dde7e6d1 1973 /* TODO: Add stack limit check */
38ba30ba 1974
9dac77fa 1975 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1976
dde7e6d1
AK		 1977 if (rc != X86EMUL_CONTINUE)
1978 return rc;
38ba30ba 1979
35d3d4a1
AK		 1980 if (temp_eip & ~0xffff)
1981 return emulate_gp(ctxt, 0);
38ba30ba 1982
9dac77fa 1983 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1984
dde7e6d1
AK		 1985 if (rc != X86EMUL_CONTINUE)
1986 return rc;
38ba30ba 1987
9dac77fa 1988 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1989
dde7e6d1
AK		 1990 if (rc != X86EMUL_CONTINUE)
1991 return rc;
38ba30ba 1992
7b105ca2 1993 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1994
dde7e6d1
AK		 1995 if (rc != X86EMUL_CONTINUE)
1996 return rc;
38ba30ba 1997
9dac77fa 1998 ctxt->_eip = temp_eip;
38ba30ba 1999
38ba30ba 2000
9dac77fa 2001 if (ctxt->op_bytes == 4)
dde7e6d1 2002 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2003 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2004 ctxt->eflags &= ~0xffff;
2005 ctxt->eflags |= temp_eflags;
38ba30ba 2006 }
dde7e6d1
AK		 2007
2008 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2009 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2010
2011 return rc;
38ba30ba
GN		 2012}
2013
e01991e7 2014static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2015{
dde7e6d1
AK		 2016 switch(ctxt->mode) {
2017 case X86EMUL_MODE_REAL:
7b105ca2 2018 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2019 case X86EMUL_MODE_VM86:
2020 case X86EMUL_MODE_PROT16:
2021 case X86EMUL_MODE_PROT32:
2022 case X86EMUL_MODE_PROT64:
c37eda13 2023 default:
dde7e6d1
AK		 2024 /* iret from protected mode unimplemented yet */
2025 return X86EMUL_UNHANDLEABLE;
c37eda13 2026 }
c37eda13
WY		 2027}
2028
d2f62766
TY		 2029static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2030{
d2f62766 2031 int rc;
d1442d85
NA		 2032 unsigned short sel, old_sel;
2033 struct desc_struct old_desc, new_desc;
2034 const struct x86_emulate_ops *ops = ctxt->ops;
2035 u8 cpl = ctxt->ops->cpl(ctxt);
2036
2037 /* Assignment of RIP may only fail in 64-bit mode */
2038 if (ctxt->mode == X86EMUL_MODE_PROT64)
2039 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2040 VCPU_SREG_CS);
d2f62766 2041
9dac77fa 2042 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2043
d1442d85
NA		 2044 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2045 &new_desc);
d2f62766
TY		 2046 if (rc != X86EMUL_CONTINUE)
2047 return rc;
2048
d50eaa18 2049 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2050 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2051 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2052 /* assigning eip failed; restore the old cs */
2053 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2054 return rc;
2055 }
2056 return rc;
d2f62766
TY		 2057}
2058
f7784046 2059static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2060{
f7784046
NA		 2061 return assign_eip_near(ctxt, ctxt->src.val);
2062}
8cdbd2c9 2063
f7784046
NA		 2064static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2065{
2066 int rc;
2067 long int old_eip;
2068
2069 old_eip = ctxt->_eip;
2070 rc = assign_eip_near(ctxt, ctxt->src.val);
2071 if (rc != X86EMUL_CONTINUE)
2072 return rc;
2073 ctxt->src.val = old_eip;
2074 rc = em_push(ctxt);
4179bb02 2075 return rc;
8cdbd2c9
LV		 2076}
2077
e0dac408 2078static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2079{
9dac77fa 2080 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2081
aaa05f24
NA		 2082 if (ctxt->dst.bytes == 16)
2083 return X86EMUL_UNHANDLEABLE;
2084
dd856efa
AK		 2085 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2086 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2087 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2088 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2089 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2090 } else {
dd856efa
AK		 2091 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2092 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2093
05f086f8 2094 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2095 }
1b30eaa8 2096 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2097}
2098
ebda02c2
TY		 2099static int em_ret(struct x86_emulate_ctxt *ctxt)
2100{
234f3ce4
NA		 2101 int rc;
2102 unsigned long eip;
2103
2104 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2105 if (rc != X86EMUL_CONTINUE)
2106 return rc;
2107
2108 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2109}
2110
e01991e7 2111static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2112{
a77ab5ea 2113 int rc;
d1442d85
NA		 2114 unsigned long eip, cs;
2115 u16 old_cs;
9e8919ae 2116 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2117 struct desc_struct old_desc, new_desc;
2118 const struct x86_emulate_ops *ops = ctxt->ops;
2119
2120 if (ctxt->mode == X86EMUL_MODE_PROT64)
2121 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2122 VCPU_SREG_CS);
a77ab5ea 2123
d1442d85 2124 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2125 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2126 return rc;
9dac77fa 2127 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2128 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2129 return rc;
9e8919ae
NA		 2130 /* Outer-privilege level return is not implemented */
2131 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2132 return X86EMUL_UNHANDLEABLE;
ab646f54 2133 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, false,
d1442d85
NA		 2134 &new_desc);
2135 if (rc != X86EMUL_CONTINUE)
2136 return rc;
d50eaa18 2137 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2138 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2139 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2140 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2141 }
a77ab5ea
AK		 2142 return rc;
2143}
2144
3261107e
BR		 2145static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2146{
2147 int rc;
2148
2149 rc = em_ret_far(ctxt);
2150 if (rc != X86EMUL_CONTINUE)
2151 return rc;
2152 rsp_increment(ctxt, ctxt->src.val);
2153 return X86EMUL_CONTINUE;
2154}
2155
e940b5c2
TY		 2156static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2157{
2158 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2159 ctxt->dst.orig_val = ctxt->dst.val;
2160 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2161 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2162 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2163 fastop(ctxt, em_cmp);
e940b5c2
TY		 2164
2165 if (ctxt->eflags & EFLG_ZF) {
2166 /* Success: write back to memory. */
2167 ctxt->dst.val = ctxt->src.orig_val;
2168 } else {
2169 /* Failure: write the value we saw to EAX. */
2170 ctxt->dst.type = OP_REG;
dd856efa 2171 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2172 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2173 }
2174 return X86EMUL_CONTINUE;
2175}
2176
d4b4325f 2177static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2178{
d4b4325f 2179 int seg = ctxt->src2.val;
09b5f4d3
WY		 2180 unsigned short sel;
2181 int rc;
2182
9dac77fa 2183 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2184
7b105ca2 2185 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2186 if (rc != X86EMUL_CONTINUE)
2187 return rc;
2188
9dac77fa 2189 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2190 return rc;
2191}
2192
7b105ca2 2193static void
e66bb2cc 2194setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2195 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2196{
e66bb2cc 2197 cs->l = 0; /* will be adjusted later */
79168fd1 2198 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2199 cs->g = 1; /* 4kb granularity */
79168fd1 2200 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2201 cs->type = 0x0b; /* Read, Execute, Accessed */
2202 cs->s = 1;
2203 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2204 cs->p = 1;
2205 cs->d = 1;
99245b50 2206 cs->avl = 0;
e66bb2cc 2207
79168fd1
GN		 2208 set_desc_base(ss, 0); /* flat segment */
2209 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2210 ss->g = 1; /* 4kb granularity */
2211 ss->s = 1;
2212 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2213 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2214 ss->dpl = 0;
79168fd1 2215 ss->p = 1;
99245b50
GN		 2216 ss->l = 0;
2217 ss->avl = 0;
e66bb2cc
AP		 2218}
2219
1a18a69b
AK		 2220static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2221{
2222 u32 eax, ebx, ecx, edx;
2223
2224 eax = ecx = 0;
0017f93a
AK		 2225 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2226 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2227 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2228 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2229}
2230
c2226fc9
SB		 2231static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2232{
0225fb50 2233 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2234 u32 eax, ebx, ecx, edx;
2235
2236 /*
2237 * syscall should always be enabled in longmode - so only become
2238 * vendor specific (cpuid) if other modes are active...
2239 */
2240 if (ctxt->mode == X86EMUL_MODE_PROT64)
2241 return true;
2242
2243 eax = 0x00000000;
2244 ecx = 0x00000000;
0017f93a
AK		 2245 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2246 /*
2247 * Intel ("GenuineIntel")
2248 * remark: Intel CPUs only support "syscall" in 64bit
2249 * longmode. Also an 64bit guest with a
2250 * 32bit compat-app running will #UD !! While this
2251 * behaviour can be fixed (by emulating) into AMD
2252 * response - CPUs of AMD can't behave like Intel.
2253 */
2254 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2255 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2256 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2257 return false;
2258
2259 /* AMD ("AuthenticAMD") */
2260 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2261 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2262 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2263 return true;
2264
2265 /* AMD ("AMDisbetter!") */
2266 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2267 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2268 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2269 return true;
c2226fc9
SB		 2270
2271 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2272 return false;
2273}
2274
e01991e7 2275static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2276{
0225fb50 2277 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2278 struct desc_struct cs, ss;
e66bb2cc 2279 u64 msr_data;
79168fd1 2280 u16 cs_sel, ss_sel;
c2ad2bb3 2281 u64 efer = 0;
e66bb2cc
AP		 2282
2283 /* syscall is not available in real mode */
2e901c4c 2284 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2285 ctxt->mode == X86EMUL_MODE_VM86)
2286 return emulate_ud(ctxt);
e66bb2cc 2287
c2226fc9
SB		 2288 if (!(em_syscall_is_enabled(ctxt)))
2289 return emulate_ud(ctxt);
2290
c2ad2bb3 2291 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2292 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2293
c2226fc9
SB		 2294 if (!(efer & EFER_SCE))
2295 return emulate_ud(ctxt);
2296
717746e3 2297 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2298 msr_data >>= 32;
79168fd1
GN		 2299 cs_sel = (u16)(msr_data & 0xfffc);
2300 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2301
c2ad2bb3 2302 if (efer & EFER_LMA) {
79168fd1 2303 cs.d = 0;
e66bb2cc
AP		 2304 cs.l = 1;
2305 }
1aa36616
AK		 2306 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2307 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2308
dd856efa 2309 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2310 if (efer & EFER_LMA) {
e66bb2cc 2311#ifdef CONFIG_X86_64
6c6cb69b 2312 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2313
717746e3 2314 ops->get_msr(ctxt,
3fb1b5db
GN		 2315 ctxt->mode == X86EMUL_MODE_PROT64 ?
2316 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2317 ctxt->_eip = msr_data;
e66bb2cc 2318
717746e3 2319 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2320 ctxt->eflags &= ~msr_data;
807c1425 2321 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2322#endif
2323 } else {
2324 /* legacy mode */
717746e3 2325 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2326 ctxt->_eip = (u32)msr_data;
e66bb2cc 2327
6c6cb69b 2328 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2329 }
2330
e54cfa97 2331 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2332}
2333
e01991e7 2334static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2335{
0225fb50 2336 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2337 struct desc_struct cs, ss;
8c604352 2338 u64 msr_data;
79168fd1 2339 u16 cs_sel, ss_sel;
c2ad2bb3 2340 u64 efer = 0;
8c604352 2341
7b105ca2 2342 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2343 /* inject #GP if in real mode */
35d3d4a1
AK		 2344 if (ctxt->mode == X86EMUL_MODE_REAL)
2345 return emulate_gp(ctxt, 0);
8c604352 2346
1a18a69b
AK		 2347 /*
2348 * Not recognized on AMD in compat mode (but is recognized in legacy
2349 * mode).
2350 */
2351 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2352 && !vendor_intel(ctxt))
2353 return emulate_ud(ctxt);
2354
b2c9d43e 2355 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2356 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2357 return X86EMUL_UNHANDLEABLE;
8c604352 2358
7b105ca2 2359 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2360
717746e3 2361 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2362 switch (ctxt->mode) {
2363 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2364 if ((msr_data & 0xfffc) == 0x0)
2365 return emulate_gp(ctxt, 0);
8c604352
AP		 2366 break;
2367 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2368 if (msr_data == 0x0)
2369 return emulate_gp(ctxt, 0);
8c604352 2370 break;
9d1b39a9
GN		 2371 default:
2372 break;
8c604352
AP		 2373 }
2374
6c6cb69b 2375 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2376 cs_sel = (u16)msr_data;
2377 cs_sel &= ~SELECTOR_RPL_MASK;
2378 ss_sel = cs_sel + 8;
2379 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2380 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2381 cs.d = 0;
8c604352
AP		 2382 cs.l = 1;
2383 }
2384
1aa36616
AK		 2385 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2386 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2387
717746e3 2388 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2389 ctxt->_eip = msr_data;
8c604352 2390
717746e3 2391 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2392 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2393
e54cfa97 2394 return X86EMUL_CONTINUE;
8c604352
AP		 2395}
2396
e01991e7 2397static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2398{
0225fb50 2399 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2400 struct desc_struct cs, ss;
234f3ce4 2401 u64 msr_data, rcx, rdx;
4668f050 2402 int usermode;
1249b96e 2403 u16 cs_sel = 0, ss_sel = 0;
4668f050 2404
a0044755
GN		 2405 /* inject #GP if in real mode or Virtual 8086 mode */
2406 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2407 ctxt->mode == X86EMUL_MODE_VM86)
2408 return emulate_gp(ctxt, 0);
4668f050 2409
7b105ca2 2410 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2411
9dac77fa 2412 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2413 usermode = X86EMUL_MODE_PROT64;
2414 else
2415 usermode = X86EMUL_MODE_PROT32;
2416
234f3ce4
NA		 2417 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2418 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2419
4668f050
AP		 2420 cs.dpl = 3;
2421 ss.dpl = 3;
717746e3 2422 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2423 switch (usermode) {
2424 case X86EMUL_MODE_PROT32:
79168fd1 2425 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2426 if ((msr_data & 0xfffc) == 0x0)
2427 return emulate_gp(ctxt, 0);
79168fd1 2428 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2429 rcx = (u32)rcx;
2430 rdx = (u32)rdx;
4668f050
AP		 2431 break;
2432 case X86EMUL_MODE_PROT64:
79168fd1 2433 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2434 if (msr_data == 0x0)
2435 return emulate_gp(ctxt, 0);
79168fd1
GN		 2436 ss_sel = cs_sel + 8;
2437 cs.d = 0;
4668f050 2438 cs.l = 1;
234f3ce4
NA		 2439 if (is_noncanonical_address(rcx) ||
2440 is_noncanonical_address(rdx))
2441 return emulate_gp(ctxt, 0);
4668f050
AP		 2442 break;
2443 }
79168fd1
GN		 2444 cs_sel |= SELECTOR_RPL_MASK;
2445 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2446
1aa36616
AK		 2447 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2448 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2449
234f3ce4
NA		 2450 ctxt->_eip = rdx;
2451 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2452
e54cfa97 2453 return X86EMUL_CONTINUE;
4668f050
AP		 2454}
2455
7b105ca2 2456static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2457{
2458 int iopl;
2459 if (ctxt->mode == X86EMUL_MODE_REAL)
2460 return false;
2461 if (ctxt->mode == X86EMUL_MODE_VM86)
2462 return true;
2463 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2464 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2465}
2466
2467static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2468 u16 port, u16 len)
2469{
0225fb50 2470 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2471 struct desc_struct tr_seg;
5601d05b 2472 u32 base3;
f850e2e6 2473 int r;
1aa36616 2474 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2475 unsigned mask = (1 << len) - 1;
5601d05b 2476 unsigned long base;
f850e2e6 2477
1aa36616 2478 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2479 if (!tr_seg.p)
f850e2e6 2480 return false;
79168fd1 2481 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2482 return false;
5601d05b
GN		 2483 base = get_desc_base(&tr_seg);
2484#ifdef CONFIG_X86_64
2485 base |= ((u64)base3) << 32;
2486#endif
0f65dd70 2487 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2488 if (r != X86EMUL_CONTINUE)
2489 return false;
79168fd1 2490 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2491 return false;
0f65dd70 2492 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2493 if (r != X86EMUL_CONTINUE)
2494 return false;
2495 if ((perm >> bit_idx) & mask)
2496 return false;
2497 return true;
2498}
2499
2500static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2501 u16 port, u16 len)
2502{
4fc40f07
GN		 2503 if (ctxt->perm_ok)
2504 return true;
2505
7b105ca2
TY		 2506 if (emulator_bad_iopl(ctxt))
2507 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2508 return false;
4fc40f07
GN		 2509
2510 ctxt->perm_ok = true;
2511
f850e2e6
GN		 2512 return true;
2513}
2514
38ba30ba 2515static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2516 struct tss_segment_16 *tss)
2517{
9dac77fa 2518 tss->ip = ctxt->_eip;
38ba30ba 2519 tss->flag = ctxt->eflags;
dd856efa
AK		 2520 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2521 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2522 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2523 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2524 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2525 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2526 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2527 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2528
1aa36616
AK		 2529 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2530 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2531 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2532 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2533 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2534}
2535
2536static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2537 struct tss_segment_16 *tss)
2538{
38ba30ba 2539 int ret;
2356aaeb 2540 u8 cpl;
38ba30ba 2541
9dac77fa 2542 ctxt->_eip = tss->ip;
38ba30ba 2543 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2544 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2545 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2546 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2547 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2548 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2549 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2550 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2551 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2552
2553 /*
2554 * SDM says that segment selectors are loaded before segment
2555 * descriptors
2556 */
1aa36616
AK		 2557 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2558 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2559 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2560 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2561 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2562
2356aaeb
PB		 2563 cpl = tss->cs & 3;
2564
38ba30ba 2565 /*
fc058680 2566 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2567 * it is handled in a context of new task
2568 */
d1442d85
NA		 2569 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2570 true, NULL);
38ba30ba
GN		 2571 if (ret != X86EMUL_CONTINUE)
2572 return ret;
d1442d85
NA		 2573 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2574 true, NULL);
38ba30ba
GN		 2575 if (ret != X86EMUL_CONTINUE)
2576 return ret;
d1442d85
NA		 2577 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2578 true, NULL);
38ba30ba
GN		 2579 if (ret != X86EMUL_CONTINUE)
2580 return ret;
d1442d85
NA		 2581 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2582 true, NULL);
38ba30ba
GN		 2583 if (ret != X86EMUL_CONTINUE)
2584 return ret;
d1442d85
NA		 2585 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2586 true, NULL);
38ba30ba
GN		 2587 if (ret != X86EMUL_CONTINUE)
2588 return ret;
2589
2590 return X86EMUL_CONTINUE;
2591}
2592
2593static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2594 u16 tss_selector, u16 old_tss_sel,
2595 ulong old_tss_base, struct desc_struct *new_desc)
2596{
0225fb50 2597 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2598 struct tss_segment_16 tss_seg;
2599 int ret;
bcc55cba 2600 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2601
0f65dd70 2602 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2603 &ctxt->exception);
db297e3d 2604 if (ret != X86EMUL_CONTINUE)
38ba30ba 2605 return ret;
38ba30ba 2606
7b105ca2 2607 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2608
0f65dd70 2609 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2610 &ctxt->exception);
db297e3d 2611 if (ret != X86EMUL_CONTINUE)
38ba30ba 2612 return ret;
38ba30ba 2613
0f65dd70 2614 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2615 &ctxt->exception);
db297e3d 2616 if (ret != X86EMUL_CONTINUE)
38ba30ba 2617 return ret;
38ba30ba
GN		 2618
2619 if (old_tss_sel != 0xffff) {
2620 tss_seg.prev_task_link = old_tss_sel;
2621
0f65dd70 2622 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2623 &tss_seg.prev_task_link,
2624 sizeof tss_seg.prev_task_link,
0f65dd70 2625 &ctxt->exception);
db297e3d 2626 if (ret != X86EMUL_CONTINUE)
38ba30ba 2627 return ret;
38ba30ba
GN		 2628 }
2629
7b105ca2 2630 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2631}
2632
2633static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2634 struct tss_segment_32 *tss)
2635{
5c7411e2 2636 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2637 tss->eip = ctxt->_eip;
38ba30ba 2638 tss->eflags = ctxt->eflags;
dd856efa
AK		 2639 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2640 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2641 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2642 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2643 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2644 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2645 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2646 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2647
1aa36616
AK		 2648 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2649 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2650 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2651 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2652 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2653 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2654}
2655
2656static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2657 struct tss_segment_32 *tss)
2658{
38ba30ba 2659 int ret;
2356aaeb 2660 u8 cpl;
38ba30ba 2661
7b105ca2 2662 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2663 return emulate_gp(ctxt, 0);
9dac77fa 2664 ctxt->_eip = tss->eip;
38ba30ba 2665 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2666
2667 /* General purpose registers */
dd856efa
AK		 2668 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2669 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2670 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2671 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2672 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2673 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2674 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2675 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2676
2677 /*
2678 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2679 * descriptors. This is important because CPL checks will
2680 * use CS.RPL.
38ba30ba 2681 */
1aa36616
AK		 2682 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2683 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2684 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2685 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2686 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2687 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2688 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2689
4cee4798
KW		 2690 /*
2691 * If we're switching between Protected Mode and VM86, we need to make
2692 * sure to update the mode before loading the segment descriptors so
2693 * that the selectors are interpreted correctly.
4cee4798 2694 */
2356aaeb 2695 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2696 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2697 cpl = 3;
2698 } else {
4cee4798 2699 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2700 cpl = tss->cs & 3;
2701 }
4cee4798 2702
38ba30ba
GN		 2703 /*
2704 * Now load segment descriptors. If fault happenes at this stage
2705 * it is handled in a context of new task
2706 */
d1442d85
NA		 2707 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2708 cpl, true, NULL);
38ba30ba
GN		 2709 if (ret != X86EMUL_CONTINUE)
2710 return ret;
d1442d85
NA		 2711 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2712 true, NULL);
38ba30ba
GN		 2713 if (ret != X86EMUL_CONTINUE)
2714 return ret;
d1442d85
NA		 2715 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2716 true, NULL);
38ba30ba
GN		 2717 if (ret != X86EMUL_CONTINUE)
2718 return ret;
d1442d85
NA		 2719 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2720 true, NULL);
38ba30ba
GN		 2721 if (ret != X86EMUL_CONTINUE)
2722 return ret;
d1442d85
NA		 2723 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2724 true, NULL);
38ba30ba
GN		 2725 if (ret != X86EMUL_CONTINUE)
2726 return ret;
d1442d85
NA		 2727 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2728 true, NULL);
38ba30ba
GN		 2729 if (ret != X86EMUL_CONTINUE)
2730 return ret;
d1442d85
NA		 2731 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2732 true, NULL);
38ba30ba
GN		 2733 if (ret != X86EMUL_CONTINUE)
2734 return ret;
2735
2736 return X86EMUL_CONTINUE;
2737}
2738
2739static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2740 u16 tss_selector, u16 old_tss_sel,
2741 ulong old_tss_base, struct desc_struct *new_desc)
2742{
0225fb50 2743 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2744 struct tss_segment_32 tss_seg;
2745 int ret;
bcc55cba 2746 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2747 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2748 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2749
0f65dd70 2750 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2751 &ctxt->exception);
db297e3d 2752 if (ret != X86EMUL_CONTINUE)
38ba30ba 2753 return ret;
38ba30ba 2754
7b105ca2 2755 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2756
5c7411e2
NA		 2757 /* Only GP registers and segment selectors are saved */
2758 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2759 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2760 if (ret != X86EMUL_CONTINUE)
38ba30ba 2761 return ret;
38ba30ba 2762
0f65dd70 2763 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2764 &ctxt->exception);
db297e3d 2765 if (ret != X86EMUL_CONTINUE)
38ba30ba 2766 return ret;
38ba30ba
GN		 2767
2768 if (old_tss_sel != 0xffff) {
2769 tss_seg.prev_task_link = old_tss_sel;
2770
0f65dd70 2771 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2772 &tss_seg.prev_task_link,
2773 sizeof tss_seg.prev_task_link,
0f65dd70 2774 &ctxt->exception);
db297e3d 2775 if (ret != X86EMUL_CONTINUE)
38ba30ba 2776 return ret;
38ba30ba
GN		 2777 }
2778
7b105ca2 2779 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2780}
2781
2782static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2783 u16 tss_selector, int idt_index, int reason,
e269fb21 2784 bool has_error_code, u32 error_code)
38ba30ba 2785{
0225fb50 2786 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2787 struct desc_struct curr_tss_desc, next_tss_desc;
2788 int ret;
1aa36616 2789 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2790 ulong old_tss_base =
4bff1e86 2791 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2792 u32 desc_limit;
e919464b 2793 ulong desc_addr;
38ba30ba
GN		 2794
2795 /* FIXME: old_tss_base == ~0 ? */
2796
e919464b 2797 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2798 if (ret != X86EMUL_CONTINUE)
2799 return ret;
e919464b 2800 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2801 if (ret != X86EMUL_CONTINUE)
2802 return ret;
2803
2804 /* FIXME: check that next_tss_desc is tss */
2805
7f3d35fd
KW		 2806 /*
2807 * Check privileges. The three cases are task switch caused by...
2808 *
2809 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2810 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2811 * 3. jmp/call to TSS/task-gate: No check is performed since the
2812 * hardware checks it before exiting.
7f3d35fd
KW		 2813 */
2814 if (reason == TASK_SWITCH_GATE) {
2815 if (idt_index != -1) {
2816 /* Software interrupts */
2817 struct desc_struct task_gate_desc;
2818 int dpl;
2819
2820 ret = read_interrupt_descriptor(ctxt, idt_index,
2821 &task_gate_desc);
2822 if (ret != X86EMUL_CONTINUE)
2823 return ret;
2824
2825 dpl = task_gate_desc.dpl;
2826 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2827 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2828 }
38ba30ba
GN		 2829 }
2830
ceffb459
GN		 2831 desc_limit = desc_limit_scaled(&next_tss_desc);
2832 if (!next_tss_desc.p ||
2833 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2834 desc_limit < 0x2b)) {
592f0858 2835 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2836 }
2837
2838 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2839 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2840 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2841 }
2842
2843 if (reason == TASK_SWITCH_IRET)
2844 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2845
2846 /* set back link to prev task only if NT bit is set in eflags
fc058680 2847 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2848 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2849 old_tss_sel = 0xffff;
2850
2851 if (next_tss_desc.type & 8)
7b105ca2 2852 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2853 old_tss_base, &next_tss_desc);
2854 else
7b105ca2 2855 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2856 old_tss_base, &next_tss_desc);
0760d448
JK		 2857 if (ret != X86EMUL_CONTINUE)
2858 return ret;
38ba30ba
GN		 2859
2860 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2861 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2862
2863 if (reason != TASK_SWITCH_IRET) {
2864 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2865 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2866 }
2867
717746e3 2868 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2869 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2870
e269fb21 2871 if (has_error_code) {
9dac77fa
AK		 2872 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2873 ctxt->lock_prefix = 0;
2874 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2875 ret = em_push(ctxt);
e269fb21
JK		 2876 }
2877
38ba30ba
GN		 2878 return ret;
2879}
2880
2881int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2882 u16 tss_selector, int idt_index, int reason,
e269fb21 2883 bool has_error_code, u32 error_code)
38ba30ba 2884{
38ba30ba
GN		 2885 int rc;
2886
dd856efa 2887 invalidate_registers(ctxt);
9dac77fa
AK		 2888 ctxt->_eip = ctxt->eip;
2889 ctxt->dst.type = OP_NONE;
38ba30ba 2890
7f3d35fd 2891 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2892 has_error_code, error_code);
38ba30ba 2893
dd856efa 2894 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2895 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2896 writeback_registers(ctxt);
2897 }
38ba30ba 2898
a0c0ab2f 2899 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2900}
2901
f3bd64c6
GN		 2902static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2903 struct operand *op)
a682e354 2904{
b3356bf0 2905 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2906
01485a22
PB		 2907 register_address_increment(ctxt, reg, df * op->bytes);
2908 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2909}
2910
7af04fc0
AK		 2911static int em_das(struct x86_emulate_ctxt *ctxt)
2912{
7af04fc0
AK		 2913 u8 al, old_al;
2914 bool af, cf, old_cf;
2915
2916 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2917 al = ctxt->dst.val;
7af04fc0
AK		 2918
2919 old_al = al;
2920 old_cf = cf;
2921 cf = false;
2922 af = ctxt->eflags & X86_EFLAGS_AF;
2923 if ((al & 0x0f) > 9 || af) {
2924 al -= 6;
2925 cf = old_cf | (al >= 250);
2926 af = true;
2927 } else {
2928 af = false;
2929 }
2930 if (old_al > 0x99 || old_cf) {
2931 al -= 0x60;
2932 cf = true;
2933 }
2934
9dac77fa 2935 ctxt->dst.val = al;
7af04fc0 2936 /* Set PF, ZF, SF */
9dac77fa
AK		 2937 ctxt->src.type = OP_IMM;
2938 ctxt->src.val = 0;
2939 ctxt->src.bytes = 1;
158de57f 2940 fastop(ctxt, em_or);
7af04fc0
AK		 2941 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2942 if (cf)
2943 ctxt->eflags |= X86_EFLAGS_CF;
2944 if (af)
2945 ctxt->eflags |= X86_EFLAGS_AF;
2946 return X86EMUL_CONTINUE;
2947}
2948
a035d5c6
PB		 2949static int em_aam(struct x86_emulate_ctxt *ctxt)
2950{
2951 u8 al, ah;
2952
2953 if (ctxt->src.val == 0)
2954 return emulate_de(ctxt);
2955
2956 al = ctxt->dst.val & 0xff;
2957 ah = al / ctxt->src.val;
2958 al %= ctxt->src.val;
2959
2960 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2961
2962 /* Set PF, ZF, SF */
2963 ctxt->src.type = OP_IMM;
2964 ctxt->src.val = 0;
2965 ctxt->src.bytes = 1;
2966 fastop(ctxt, em_or);
2967
2968 return X86EMUL_CONTINUE;
2969}
2970
7f662273
GN		 2971static int em_aad(struct x86_emulate_ctxt *ctxt)
2972{
2973 u8 al = ctxt->dst.val & 0xff;
2974 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2975
2976 al = (al + (ah * ctxt->src.val)) & 0xff;
2977
2978 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2979
f583c29b
GN		 2980 /* Set PF, ZF, SF */
2981 ctxt->src.type = OP_IMM;
2982 ctxt->src.val = 0;
2983 ctxt->src.bytes = 1;
2984 fastop(ctxt, em_or);
7f662273
GN		 2985
2986 return X86EMUL_CONTINUE;
2987}
2988
d4ddafcd
TY		 2989static int em_call(struct x86_emulate_ctxt *ctxt)
2990{
234f3ce4 2991 int rc;
d4ddafcd
TY		 2992 long rel = ctxt->src.val;
2993
2994 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2995 rc = jmp_rel(ctxt, rel);
2996 if (rc != X86EMUL_CONTINUE)
2997 return rc;
d4ddafcd
TY		 2998 return em_push(ctxt);
2999}
3000
0ef753b8
AK		 3001static int em_call_far(struct x86_emulate_ctxt *ctxt)
3002{
0ef753b8
AK		 3003 u16 sel, old_cs;
3004 ulong old_eip;
3005 int rc;
d1442d85
NA		 3006 struct desc_struct old_desc, new_desc;
3007 const struct x86_emulate_ops *ops = ctxt->ops;
3008 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3009
9dac77fa 3010 old_eip = ctxt->_eip;
d1442d85 3011 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3012
9dac77fa 3013 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3014 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3015 &new_desc);
3016 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3017 return X86EMUL_CONTINUE;
3018
d50eaa18 3019 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3020 if (rc != X86EMUL_CONTINUE)
3021 goto fail;
0ef753b8 3022
9dac77fa 3023 ctxt->src.val = old_cs;
4487b3b4 3024 rc = em_push(ctxt);
0ef753b8 3025 if (rc != X86EMUL_CONTINUE)
d1442d85 3026 goto fail;
0ef753b8 3027
9dac77fa 3028 ctxt->src.val = old_eip;
d1442d85
NA		 3029 rc = em_push(ctxt);
3030 /* If we failed, we tainted the memory, but the very least we should
3031 restore cs */
3032 if (rc != X86EMUL_CONTINUE)
3033 goto fail;
3034 return rc;
3035fail:
3036 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3037 return rc;
3038
0ef753b8
AK		 3039}
3040
40ece7c7
AK		 3041static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3042{
40ece7c7 3043 int rc;
234f3ce4 3044 unsigned long eip;
40ece7c7 3045
234f3ce4
NA		 3046 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3047 if (rc != X86EMUL_CONTINUE)
3048 return rc;
3049 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3050 if (rc != X86EMUL_CONTINUE)
3051 return rc;
5ad105e5 3052 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3053 return X86EMUL_CONTINUE;
3054}
3055
e4f973ae
TY		 3056static int em_xchg(struct x86_emulate_ctxt *ctxt)
3057{
e4f973ae 3058 /* Write back the register source. */
9dac77fa
AK		 3059 ctxt->src.val = ctxt->dst.val;
3060 write_register_operand(&ctxt->src);
e4f973ae
TY		 3061
3062 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3063 ctxt->dst.val = ctxt->src.orig_val;
3064 ctxt->lock_prefix = 1;
e4f973ae
TY		 3065 return X86EMUL_CONTINUE;
3066}
3067
5c82aa29
AK		 3068static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3069{
9dac77fa 3070 ctxt->dst.val = ctxt->src2.val;
4d758349 3071 return fastop(ctxt, em_imul);
5c82aa29
AK		 3072}
3073
61429142
AK		 3074static int em_cwd(struct x86_emulate_ctxt *ctxt)
3075{
9dac77fa
AK		 3076 ctxt->dst.type = OP_REG;
3077 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3078 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3079 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3080
3081 return X86EMUL_CONTINUE;
3082}
3083
48bb5d3c
AK		 3084static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3085{
48bb5d3c
AK		 3086 u64 tsc = 0;
3087
717746e3 3088 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3089 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3090 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3091 return X86EMUL_CONTINUE;
3092}
3093
222d21aa
AK		 3094static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3095{
3096 u64 pmc;
3097
dd856efa 3098 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3099 return emulate_gp(ctxt, 0);
dd856efa
AK		 3100 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3101 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3102 return X86EMUL_CONTINUE;
3103}
3104
b9eac5f4
AK		 3105static int em_mov(struct x86_emulate_ctxt *ctxt)
3106{
54cfdb3e 3107 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3108 return X86EMUL_CONTINUE;
3109}
3110
84cffe49
BP		 3111#define FFL(x) bit(X86_FEATURE_##x)
3112
3113static int em_movbe(struct x86_emulate_ctxt *ctxt)
3114{
3115 u32 ebx, ecx, edx, eax = 1;
3116 u16 tmp;
3117
3118 /*
3119 * Check MOVBE is set in the guest-visible CPUID leaf.
3120 */
3121 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3122 if (!(ecx & FFL(MOVBE)))
3123 return emulate_ud(ctxt);
3124
3125 switch (ctxt->op_bytes) {
3126 case 2:
3127 /*
3128 * From MOVBE definition: "...When the operand size is 16 bits,
3129 * the upper word of the destination register remains unchanged
3130 * ..."
3131 *
3132 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3133 * rules so we have to do the operation almost per hand.
3134 */
3135 tmp = (u16)ctxt->src.val;
3136 ctxt->dst.val &= ~0xffffUL;
3137 ctxt->dst.val |= (unsigned long)swab16(tmp);
3138 break;
3139 case 4:
3140 ctxt->dst.val = swab32((u32)ctxt->src.val);
3141 break;
3142 case 8:
3143 ctxt->dst.val = swab64(ctxt->src.val);
3144 break;
3145 default:
592f0858 3146 BUG();
84cffe49
BP		 3147 }
3148 return X86EMUL_CONTINUE;
3149}
3150
bc00f8d2
TY		 3151static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3152{
3153 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3154 return emulate_gp(ctxt, 0);
3155
3156 /* Disable writeback. */
3157 ctxt->dst.type = OP_NONE;
3158 return X86EMUL_CONTINUE;
3159}
3160
3161static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3162{
3163 unsigned long val;
3164
3165 if (ctxt->mode == X86EMUL_MODE_PROT64)
3166 val = ctxt->src.val & ~0ULL;
3167 else
3168 val = ctxt->src.val & ~0U;
3169
3170 /* #UD condition is already handled. */
3171 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3172 return emulate_gp(ctxt, 0);
3173
3174 /* Disable writeback. */
3175 ctxt->dst.type = OP_NONE;
3176 return X86EMUL_CONTINUE;
3177}
3178
e1e210b0
TY		 3179static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3180{
3181 u64 msr_data;
3182
dd856efa
AK		 3183 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3184 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3185 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3186 return emulate_gp(ctxt, 0);
3187
3188 return X86EMUL_CONTINUE;
3189}
3190
3191static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3192{
3193 u64 msr_data;
3194
dd856efa 3195 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3196 return emulate_gp(ctxt, 0);
3197
dd856efa
AK		 3198 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3199 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3200 return X86EMUL_CONTINUE;
3201}
3202
1bd5f469
TY		 3203static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3204{
9dac77fa 3205 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3206 return emulate_ud(ctxt);
3207
9dac77fa 3208 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3209 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3210 ctxt->dst.bytes = 2;
1bd5f469
TY		 3211 return X86EMUL_CONTINUE;
3212}
3213
3214static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3215{
9dac77fa 3216 u16 sel = ctxt->src.val;
1bd5f469 3217
9dac77fa 3218 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3219 return emulate_ud(ctxt);
3220
9dac77fa 3221 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3222 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3223
3224 /* Disable writeback. */
9dac77fa
AK		 3225 ctxt->dst.type = OP_NONE;
3226 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3227}
3228
a14e579f
AK		 3229static int em_lldt(struct x86_emulate_ctxt *ctxt)
3230{
3231 u16 sel = ctxt->src.val;
3232
3233 /* Disable writeback. */
3234 ctxt->dst.type = OP_NONE;
3235 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3236}
3237
80890006
AK		 3238static int em_ltr(struct x86_emulate_ctxt *ctxt)
3239{
3240 u16 sel = ctxt->src.val;
3241
3242 /* Disable writeback. */
3243 ctxt->dst.type = OP_NONE;
3244 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3245}
3246
38503911
AK		 3247static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3248{
9fa088f4
AK		 3249 int rc;
3250 ulong linear;
3251
9dac77fa 3252 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3253 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3254 ctxt->ops->invlpg(ctxt, linear);
38503911 3255 /* Disable writeback. */
9dac77fa 3256 ctxt->dst.type = OP_NONE;
38503911
AK		 3257 return X86EMUL_CONTINUE;
3258}
3259
2d04a05b
AK		 3260static int em_clts(struct x86_emulate_ctxt *ctxt)
3261{
3262 ulong cr0;
3263
3264 cr0 = ctxt->ops->get_cr(ctxt, 0);
3265 cr0 &= ~X86_CR0_TS;
3266 ctxt->ops->set_cr(ctxt, 0, cr0);
3267 return X86EMUL_CONTINUE;
3268}
3269
26d05cc7
AK		 3270static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3271{
0f54a321 3272 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3273
26d05cc7
AK		 3274 if (rc != X86EMUL_CONTINUE)
3275 return rc;
3276
3277 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3278 ctxt->_eip = ctxt->eip;
26d05cc7 3279 /* Disable writeback. */
9dac77fa 3280 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3281 return X86EMUL_CONTINUE;
3282}
3283
96051572
AK		 3284static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3285 void (*get)(struct x86_emulate_ctxt *ctxt,
3286 struct desc_ptr *ptr))
3287{
3288 struct desc_ptr desc_ptr;
3289
3290 if (ctxt->mode == X86EMUL_MODE_PROT64)
3291 ctxt->op_bytes = 8;
3292 get(ctxt, &desc_ptr);
3293 if (ctxt->op_bytes == 2) {
3294 ctxt->op_bytes = 4;
3295 desc_ptr.address &= 0x00ffffff;
3296 }
3297 /* Disable writeback. */
3298 ctxt->dst.type = OP_NONE;
3299 return segmented_write(ctxt, ctxt->dst.addr.mem,
3300 &desc_ptr, 2 + ctxt->op_bytes);
3301}
3302
3303static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3304{
3305 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3306}
3307
3308static int em_sidt(struct x86_emulate_ctxt *ctxt)
3309{
3310 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3311}
3312
5b7f6a1e 3313static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3314{
26d05cc7
AK		 3315 struct desc_ptr desc_ptr;
3316 int rc;
3317
510425ff
AK		 3318 if (ctxt->mode == X86EMUL_MODE_PROT64)
3319 ctxt->op_bytes = 8;
9dac77fa 3320 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3321 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3322 ctxt->op_bytes);
26d05cc7
AK		 3323 if (rc != X86EMUL_CONTINUE)
3324 return rc;
9a9abf6b
NA		 3325 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3326 is_noncanonical_address(desc_ptr.address))
3327 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3328 if (lgdt)
3329 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3330 else
3331 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3332 /* Disable writeback. */
9dac77fa 3333 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3334 return X86EMUL_CONTINUE;
3335}
3336
5b7f6a1e
NA		 3337static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3338{
3339 return em_lgdt_lidt(ctxt, true);
3340}
3341
5ef39c71 3342static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3343{
26d05cc7
AK		 3344 int rc;
3345
5ef39c71
AK		 3346 rc = ctxt->ops->fix_hypercall(ctxt);
3347
26d05cc7 3348 /* Disable writeback. */
9dac77fa 3349 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3350 return rc;
3351}
3352
3353static int em_lidt(struct x86_emulate_ctxt *ctxt)
3354{
5b7f6a1e 3355 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3356}
3357
3358static int em_smsw(struct x86_emulate_ctxt *ctxt)
3359{
32e94d06
NA		 3360 if (ctxt->dst.type == OP_MEM)
3361 ctxt->dst.bytes = 2;
9dac77fa 3362 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3363 return X86EMUL_CONTINUE;
3364}
3365
3366static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3367{
26d05cc7 3368 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3369 | (ctxt->src.val & 0x0f));
3370 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3371 return X86EMUL_CONTINUE;
3372}
3373
d06e03ad
TY		 3374static int em_loop(struct x86_emulate_ctxt *ctxt)
3375{
234f3ce4
NA		 3376 int rc = X86EMUL_CONTINUE;
3377
01485a22 3378 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3379 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3380 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3381 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3382
234f3ce4 3383 return rc;
d06e03ad
TY		 3384}
3385
3386static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3387{
234f3ce4
NA		 3388 int rc = X86EMUL_CONTINUE;
3389
dd856efa 3390 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3391 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3392
234f3ce4 3393 return rc;
d06e03ad
TY		 3394}
3395
d7841a4b
TY		 3396static int em_in(struct x86_emulate_ctxt *ctxt)
3397{
3398 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3399 &ctxt->dst.val))
3400 return X86EMUL_IO_NEEDED;
3401
3402 return X86EMUL_CONTINUE;
3403}
3404
3405static int em_out(struct x86_emulate_ctxt *ctxt)
3406{
3407 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3408 &ctxt->src.val, 1);
3409 /* Disable writeback. */
3410 ctxt->dst.type = OP_NONE;
3411 return X86EMUL_CONTINUE;
3412}
3413
f411e6cd
TY		 3414static int em_cli(struct x86_emulate_ctxt *ctxt)
3415{
3416 if (emulator_bad_iopl(ctxt))
3417 return emulate_gp(ctxt, 0);
3418
3419 ctxt->eflags &= ~X86_EFLAGS_IF;
3420 return X86EMUL_CONTINUE;
3421}
3422
3423static int em_sti(struct x86_emulate_ctxt *ctxt)
3424{
3425 if (emulator_bad_iopl(ctxt))
3426 return emulate_gp(ctxt, 0);
3427
3428 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3429 ctxt->eflags |= X86_EFLAGS_IF;
3430 return X86EMUL_CONTINUE;
3431}
3432
6d6eede4
AK		 3433static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3434{
3435 u32 eax, ebx, ecx, edx;
3436
dd856efa
AK		 3437 eax = reg_read(ctxt, VCPU_REGS_RAX);
3438 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3439 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3440 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3441 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3442 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3443 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3444 return X86EMUL_CONTINUE;
3445}
3446
98f73630
PB		 3447static int em_sahf(struct x86_emulate_ctxt *ctxt)
3448{
3449 u32 flags;
3450
3451 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3452 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3453
3454 ctxt->eflags &= ~0xffUL;
3455 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3456 return X86EMUL_CONTINUE;
3457}
3458
2dd7caa0
AK		 3459static int em_lahf(struct x86_emulate_ctxt *ctxt)
3460{
dd856efa
AK		 3461 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3462 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3463 return X86EMUL_CONTINUE;
3464}
3465
9299836e
AK		 3466static int em_bswap(struct x86_emulate_ctxt *ctxt)
3467{
3468 switch (ctxt->op_bytes) {
3469#ifdef CONFIG_X86_64
3470 case 8:
3471 asm("bswap %0" : "+r"(ctxt->dst.val));
3472 break;
3473#endif
3474 default:
3475 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3476 break;
3477 }
3478 return X86EMUL_CONTINUE;
3479}
3480
13e457e0
NA		 3481static int em_clflush(struct x86_emulate_ctxt *ctxt)
3482{
3483 /* emulating clflush regardless of cpuid */
3484 return X86EMUL_CONTINUE;
3485}
3486
cfec82cb
JR		 3487static bool valid_cr(int nr)
3488{
3489 switch (nr) {
3490 case 0:
3491 case 2 ... 4:
3492 case 8:
3493 return true;
3494 default:
3495 return false;
3496 }
3497}
3498
3499static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3500{
9dac77fa 3501 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3502 return emulate_ud(ctxt);
3503
3504 return X86EMUL_CONTINUE;
3505}
3506
3507static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3508{
9dac77fa
AK		 3509 u64 new_val = ctxt->src.val64;
3510 int cr = ctxt->modrm_reg;
c2ad2bb3 3511 u64 efer = 0;
cfec82cb
JR		 3512
3513 static u64 cr_reserved_bits[] = {
3514 0xffffffff00000000ULL,
3515 0, 0, 0, /* CR3 checked later */
3516 CR4_RESERVED_BITS,
3517 0, 0, 0,
3518 CR8_RESERVED_BITS,
3519 };
3520
3521 if (!valid_cr(cr))
3522 return emulate_ud(ctxt);
3523
3524 if (new_val & cr_reserved_bits[cr])
3525 return emulate_gp(ctxt, 0);
3526
3527 switch (cr) {
3528 case 0: {
c2ad2bb3 3529 u64 cr4;
cfec82cb
JR		 3530 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3531 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3532 return emulate_gp(ctxt, 0);
3533
717746e3
AK		 3534 cr4 = ctxt->ops->get_cr(ctxt, 4);
3535 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3536
3537 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3538 !(cr4 & X86_CR4_PAE))
3539 return emulate_gp(ctxt, 0);
3540
3541 break;
3542 }
3543 case 3: {
3544 u64 rsvd = 0;
3545
c2ad2bb3
AK		 3546 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3547 if (efer & EFER_LMA)
9d88fca7 3548 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3549
3550 if (new_val & rsvd)
3551 return emulate_gp(ctxt, 0);
3552
3553 break;
3554 }
3555 case 4: {
717746e3 3556 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3557
3558 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3559 return emulate_gp(ctxt, 0);
3560
3561 break;
3562 }
3563 }
3564
3565 return X86EMUL_CONTINUE;
3566}
3567
3b88e41a
JR		 3568static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3569{
3570 unsigned long dr7;
3571
717746e3 3572 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3573
3574 /* Check if DR7.Global_Enable is set */
3575 return dr7 & (1 << 13);
3576}
3577
3578static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3579{
9dac77fa 3580 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3581 u64 cr4;
3582
3583 if (dr > 7)
3584 return emulate_ud(ctxt);
3585
717746e3 3586 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3587 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3588 return emulate_ud(ctxt);
3589
6d2a0526
NA		 3590 if (check_dr7_gd(ctxt)) {
3591 ulong dr6;
3592
3593 ctxt->ops->get_dr(ctxt, 6, &dr6);
3594 dr6 &= ~15;
3595 dr6 |= DR6_BD | DR6_RTM;
3596 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3597 return emulate_db(ctxt);
6d2a0526 3598 }
3b88e41a
JR		 3599
3600 return X86EMUL_CONTINUE;
3601}
3602
3603static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3604{
9dac77fa
AK		 3605 u64 new_val = ctxt->src.val64;
3606 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3607
3608 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3609 return emulate_gp(ctxt, 0);
3610
3611 return check_dr_read(ctxt);
3612}
3613
01de8b09
JR		 3614static int check_svme(struct x86_emulate_ctxt *ctxt)
3615{
3616 u64 efer;
3617
717746e3 3618 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3619
3620 if (!(efer & EFER_SVME))
3621 return emulate_ud(ctxt);
3622
3623 return X86EMUL_CONTINUE;
3624}
3625
3626static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3627{
dd856efa 3628 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3629
3630 /* Valid physical address? */
d4224449 3631 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3632 return emulate_gp(ctxt, 0);
3633
3634 return check_svme(ctxt);
3635}
3636
d7eb8203
JR		 3637static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3638{
717746e3 3639 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3640
717746e3 3641 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3642 return emulate_ud(ctxt);
3643
3644 return X86EMUL_CONTINUE;
3645}
3646
8061252e
JR		 3647static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3648{
717746e3 3649 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3650 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3651
717746e3 3652 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3653 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3654 return emulate_gp(ctxt, 0);
3655
3656 return X86EMUL_CONTINUE;
3657}
3658
f6511935
JR		 3659static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3660{
9dac77fa
AK		 3661 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3662 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3663 return emulate_gp(ctxt, 0);
3664
3665 return X86EMUL_CONTINUE;
3666}
3667
3668static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3669{
9dac77fa
AK		 3670 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3671 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3672 return emulate_gp(ctxt, 0);
3673
3674 return X86EMUL_CONTINUE;
3675}
3676
73fba5f4 3677#define D(_y) { .flags = (_y) }
d40a6898
PB		 3678#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3679#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3680 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3681#define N D(NotImpl)
01de8b09 3682#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3683#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3684#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3685#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
045a282c 3686#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3687#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3688#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3689#define II(_f, _e, _i) \
d40a6898 3690 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3691#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3692 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3693 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3694#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3695
8d8f4e9f 3696#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3697#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3698#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3699#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3700#define I2bvIP(_f, _e, _i, _p) \
3701 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3702
fb864fbc
AK		 3703#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3704 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3705 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3706
0f54a321
NA		 3707static const struct opcode group7_rm0[] = {
3708 N,
3709 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3710 N, N, N, N, N, N,
3711};
3712
fd0a0d82 3713static const struct opcode group7_rm1[] = {
1c2545be
TY		 3714 DI(SrcNone | Priv, monitor),
3715 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3716 N, N, N, N, N, N,
3717};
3718
fd0a0d82 3719static const struct opcode group7_rm3[] = {
1c2545be 3720 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3721 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3722 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3723 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3724 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3725 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3726 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3727 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3728};
6230f7fc 3729
fd0a0d82 3730static const struct opcode group7_rm7[] = {
d7eb8203 3731 N,
1c2545be 3732 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3733 N, N, N, N, N, N,
3734};
d67fc27a 3735
fd0a0d82 3736static const struct opcode group1[] = {
fb864fbc
AK		 3737 F(Lock, em_add),
3738 F(Lock | PageTable, em_or),
3739 F(Lock, em_adc),
3740 F(Lock, em_sbb),
3741 F(Lock | PageTable, em_and),
3742 F(Lock, em_sub),
3743 F(Lock, em_xor),
3744 F(NoWrite, em_cmp),
73fba5f4
AK		 3745};
3746
fd0a0d82 3747static const struct opcode group1A[] = {
1c2545be 3748 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3749};
3750
007a3b54
AK		 3751static const struct opcode group2[] = {
3752 F(DstMem | ModRM, em_rol),
3753 F(DstMem | ModRM, em_ror),
3754 F(DstMem | ModRM, em_rcl),
3755 F(DstMem | ModRM, em_rcr),
3756 F(DstMem | ModRM, em_shl),
3757 F(DstMem | ModRM, em_shr),
3758 F(DstMem | ModRM, em_shl),
3759 F(DstMem | ModRM, em_sar),
3760};
3761
fd0a0d82 3762static const struct opcode group3[] = {
fb864fbc
AK		 3763 F(DstMem | SrcImm | NoWrite, em_test),
3764 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3765 F(DstMem | SrcNone | Lock, em_not),
3766 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3767 F(DstXacc | Src2Mem, em_mul_ex),
3768 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3769 F(DstXacc | Src2Mem, em_div_ex),
3770 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3771};
3772
fd0a0d82 3773static const struct opcode group4[] = {
95413dc4
AK		 3774 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3775 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3776 N, N, N, N, N, N,
3777};
3778
fd0a0d82 3779static const struct opcode group5[] = {
95413dc4
AK		 3780 F(DstMem | SrcNone | Lock, em_inc),
3781 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3782 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3783 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3784 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3785 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3786 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3787};
3788
fd0a0d82 3789static const struct opcode group6[] = {
1c2545be
TY		 3790 DI(Prot, sldt),
3791 DI(Prot, str),
a14e579f 3792 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3793 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3794 N, N, N, N,
3795};
3796
fd0a0d82 3797static const struct group_dual group7 = { {
606b1c3e
NA		 3798 II(Mov | DstMem, em_sgdt, sgdt),
3799 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3800 II(SrcMem | Priv, em_lgdt, lgdt),
3801 II(SrcMem | Priv, em_lidt, lidt),
3802 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3803 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3804 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3805}, {
0f54a321 3806 EXT(0, group7_rm0),
5ef39c71 3807 EXT(0, group7_rm1),
01de8b09 3808 N, EXT(0, group7_rm3),
1c2545be
TY		 3809 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3810 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3811 EXT(0, group7_rm7),
73fba5f4
AK		 3812} };
3813
fd0a0d82 3814static const struct opcode group8[] = {
73fba5f4 3815 N, N, N, N,
11c363ba
AK		 3816 F(DstMem | SrcImmByte | NoWrite, em_bt),
3817 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3818 F(DstMem | SrcImmByte | Lock, em_btr),
3819 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3820};
3821
fd0a0d82 3822static const struct group_dual group9 = { {
1c2545be 3823 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3824}, {
3825 N, N, N, N, N, N, N, N,
3826} };
3827
fd0a0d82 3828static const struct opcode group11[] = {
1c2545be 3829 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3830 X7(D(Undefined)),
a4d4a7c1
AK		 3831};
3832
13e457e0 3833static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3834 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3835};
3836
3837static const struct group_dual group15 = { {
3838 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3839}, {
3840 N, N, N, N, N, N, N, N,
3841} };
3842
fd0a0d82 3843static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3844 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3845};
3846
39f062ff
NA		 3847static const struct instr_dual instr_dual_0f_2b = {
3848 I(0, em_mov), N
3849};
3850
d5b77069 3851static const struct gprefix pfx_0f_2b = {
39f062ff 3852 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3853};
3854
27ce8258 3855static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3856 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3857};
3858
0a37027e
AW		 3859static const struct gprefix pfx_0f_e7 = {
3860 N, I(Sse, em_mov), N, N,
3861};
3862
045a282c
GN		 3863static const struct escape escape_d9 = { {
3864 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3865}, {
3866 /* 0xC0 - 0xC7 */
3867 N, N, N, N, N, N, N, N,
3868 /* 0xC8 - 0xCF */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xD0 - 0xC7 */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xD8 - 0xDF */
3873 N, N, N, N, N, N, N, N,
3874 /* 0xE0 - 0xE7 */
3875 N, N, N, N, N, N, N, N,
3876 /* 0xE8 - 0xEF */
3877 N, N, N, N, N, N, N, N,
3878 /* 0xF0 - 0xF7 */
3879 N, N, N, N, N, N, N, N,
3880 /* 0xF8 - 0xFF */
3881 N, N, N, N, N, N, N, N,
3882} };
3883
3884static const struct escape escape_db = { {
3885 N, N, N, N, N, N, N, N,
3886}, {
3887 /* 0xC0 - 0xC7 */
3888 N, N, N, N, N, N, N, N,
3889 /* 0xC8 - 0xCF */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xD0 - 0xC7 */
3892 N, N, N, N, N, N, N, N,
3893 /* 0xD8 - 0xDF */
3894 N, N, N, N, N, N, N, N,
3895 /* 0xE0 - 0xE7 */
3896 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3897 /* 0xE8 - 0xEF */
3898 N, N, N, N, N, N, N, N,
3899 /* 0xF0 - 0xF7 */
3900 N, N, N, N, N, N, N, N,
3901 /* 0xF8 - 0xFF */
3902 N, N, N, N, N, N, N, N,
3903} };
3904
3905static const struct escape escape_dd = { {
3906 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3907}, {
3908 /* 0xC0 - 0xC7 */
3909 N, N, N, N, N, N, N, N,
3910 /* 0xC8 - 0xCF */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xD0 - 0xC7 */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xD8 - 0xDF */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xE0 - 0xE7 */
3917 N, N, N, N, N, N, N, N,
3918 /* 0xE8 - 0xEF */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xF0 - 0xF7 */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xF8 - 0xFF */
3923 N, N, N, N, N, N, N, N,
3924} };
3925
39f062ff
NA		 3926static const struct instr_dual instr_dual_0f_c3 = {
3927 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3928};
3929
fd0a0d82 3930static const struct opcode opcode_table[256] = {
73fba5f4 3931 /* 0x00 - 0x07 */
fb864fbc 3932 F6ALU(Lock, em_add),
1cd196ea
AK		 3933 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3934 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3935 /* 0x08 - 0x0F */
fb864fbc 3936 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3937 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3938 N,
73fba5f4 3939 /* 0x10 - 0x17 */
fb864fbc 3940 F6ALU(Lock, em_adc),
1cd196ea
AK		 3941 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3942 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3943 /* 0x18 - 0x1F */
fb864fbc 3944 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3945 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3946 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3947 /* 0x20 - 0x27 */
fb864fbc 3948 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3949 /* 0x28 - 0x2F */
fb864fbc 3950 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3951 /* 0x30 - 0x37 */
fb864fbc 3952 F6ALU(Lock, em_xor), N, N,
73fba5f4 3953 /* 0x38 - 0x3F */
fb864fbc 3954 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3955 /* 0x40 - 0x4F */
95413dc4 3956 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3957 /* 0x50 - 0x57 */
63540382 3958 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3959 /* 0x58 - 0x5F */
c54fe504 3960 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3961 /* 0x60 - 0x67 */
b96a7fad
TY		 3962 I(ImplicitOps | Stack | No64, em_pusha),
3963 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3964 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3965 N, N, N, N,
3966 /* 0x68 - 0x6F */
d46164db
AK		 3967 I(SrcImm | Mov | Stack, em_push),
3968 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3969 I(SrcImmByte | Mov | Stack, em_push),
3970 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3971 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3972 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3973 /* 0x70 - 0x7F */
58b7075d 3974 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3975 /* 0x80 - 0x87 */
1c2545be
TY		 3976 G(ByteOp | DstMem | SrcImm, group1),
3977 G(DstMem | SrcImm, group1),
3978 G(ByteOp | DstMem | SrcImm | No64, group1),
3979 G(DstMem | SrcImmByte, group1),
fb864fbc 3980 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3981 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3982 /* 0x88 - 0x8F */
d5ae7ce8 3983 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3984 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3985 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3986 D(ModRM | SrcMem | NoAccess | DstReg),
3987 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3988 G(0, group1A),
73fba5f4 3989 /* 0x90 - 0x97 */
bf608f88 3990 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3991 /* 0x98 - 0x9F */
61429142 3992 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3993 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3994 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3995 II(ImplicitOps | Stack, em_popf, popf),
3996 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3997 /* 0xA0 - 0xA7 */
b9eac5f4 3998 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3999 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4000 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4001 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4002 /* 0xA8 - 0xAF */
fb864fbc 4003 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4004 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4005 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4006 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4007 /* 0xB0 - 0xB7 */
b9eac5f4 4008 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4009 /* 0xB8 - 0xBF */
5e2c6883 4010 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4011 /* 0xC0 - 0xC7 */
007a3b54 4012 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4013 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4014 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4015 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4016 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4017 G(ByteOp, group11), G(0, group11),
73fba5f4 4018 /* 0xC8 - 0xCF */
612e89f0 4019 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4020 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4021 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4022 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4023 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4024 /* 0xD0 - 0xD7 */
007a3b54
AK		 4025 G(Src2One | ByteOp, group2), G(Src2One, group2),
4026 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4027 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4028 I(DstAcc | SrcImmUByte | No64, em_aad),
4029 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4030 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4031 /* 0xD8 - 0xDF */
045a282c 4032 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4033 /* 0xE0 - 0xE7 */
58b7075d
NA		 4034 X3(I(SrcImmByte | NearBranch, em_loop)),
4035 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4036 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4037 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4038 /* 0xE8 - 0xEF */
58b7075d
NA		 4039 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4040 I(SrcImmFAddr | No64, em_jmp_far),
4041 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4042 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4043 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4044 /* 0xF0 - 0xF7 */
bf608f88 4045 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4046 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4047 G(ByteOp, group3), G(0, group3),
73fba5f4 4048 /* 0xF8 - 0xFF */
f411e6cd
TY		 4049 D(ImplicitOps), D(ImplicitOps),
4050 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4051 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4052};
4053
fd0a0d82 4054static const struct opcode twobyte_table[256] = {
73fba5f4 4055 /* 0x00 - 0x0F */
dee6bb70 4056 G(0, group6), GD(0, &group7), N, N,
b51e974f 4057 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4058 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4059 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4060 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4061 /* 0x10 - 0x1F */
103f98ea 4062 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4063 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4064 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4065 /* 0x20 - 0x2F */
9b88ae99
NA		 4066 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4067 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4068 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4069 check_cr_write),
4070 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4071 check_dr_write),
73fba5f4 4072 N, N, N, N,
27ce8258
IM		 4073 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4074 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4075 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4076 N, N, N, N,
73fba5f4 4077 /* 0x30 - 0x3F */
e1e210b0 4078 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4079 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4080 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4081 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4082 I(ImplicitOps | EmulateOnUD, em_sysenter),
4083 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4084 N, N,
73fba5f4
AK		 4085 N, N, N, N, N, N, N, N,
4086 /* 0x40 - 0x4F */
140bad89 4087 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4088 /* 0x50 - 0x5F */
4089 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4090 /* 0x60 - 0x6F */
aa97bb48
AK		 4091 N, N, N, N,
4092 N, N, N, N,
4093 N, N, N, N,
4094 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4095 /* 0x70 - 0x7F */
aa97bb48
AK		 4096 N, N, N, N,
4097 N, N, N, N,
4098 N, N, N, N,
4099 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4100 /* 0x80 - 0x8F */
58b7075d 4101 X16(D(SrcImm | NearBranch)),
73fba5f4 4102 /* 0x90 - 0x9F */
ee45b58e 4103 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4104 /* 0xA0 - 0xA7 */
1cd196ea 4105 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4106 II(ImplicitOps, em_cpuid, cpuid),
4107 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4108 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4109 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4110 /* 0xA8 - 0xAF */
1cd196ea 4111 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4112 DI(ImplicitOps, rsm),
11c363ba 4113 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4114 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4115 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4116 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4117 /* 0xB0 - 0xB7 */
e940b5c2 4118 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4119 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4120 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4121 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4122 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4123 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4124 /* 0xB8 - 0xBF */
4125 N, N,
ce7faab2 4126 G(BitOp, group8),
11c363ba
AK		 4127 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4128 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4129 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4130 /* 0xC0 - 0xC7 */
e47a5f5f 4131 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4132 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4133 N, N, N, GD(0, &group9),
9299836e
AK		 4134 /* 0xC8 - 0xCF */
4135 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4136 /* 0xD0 - 0xDF */
4137 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4138 /* 0xE0 - 0xEF */
0a37027e
AW		 4139 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4140 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4141 /* 0xF0 - 0xFF */
4142 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4143};
4144
39f062ff
NA		 4145static const struct instr_dual instr_dual_0f_38_f0 = {
4146 I(DstReg | SrcMem | Mov, em_movbe), N
4147};
4148
4149static const struct instr_dual instr_dual_0f_38_f1 = {
4150 I(DstMem | SrcReg | Mov, em_movbe), N
4151};
4152
0bc5eedb 4153static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4154 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4155};
4156
4157static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4158 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4159};
4160
4161/*
4162 * Insns below are selected by the prefix which indexed by the third opcode
4163 * byte.
4164 */
4165static const struct opcode opcode_map_0f_38[256] = {
4166 /* 0x00 - 0x7f */
4167 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4168 /* 0x80 - 0xef */
4169 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4170 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4171 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4172 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4173 /* 0xf2 - 0xff */
4174 N, N, X4(N), X8(N)
0bc5eedb
BP		 4175};
4176
73fba5f4
AK		 4177#undef D
4178#undef N
4179#undef G
4180#undef GD
4181#undef I
aa97bb48 4182#undef GP
01de8b09 4183#undef EXT
73fba5f4 4184
8d8f4e9f 4185#undef D2bv
f6511935 4186#undef D2bvIP
8d8f4e9f 4187#undef I2bv
d7841a4b 4188#undef I2bvIP
d67fc27a 4189#undef I6ALU
8d8f4e9f 4190
9dac77fa 4191static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4192{
4193 unsigned size;
4194
9dac77fa 4195 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4196 if (size == 8)
4197 size = 4;
4198 return size;
4199}
4200
4201static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4202 unsigned size, bool sign_extension)
4203{
39f21ee5
AK		 4204 int rc = X86EMUL_CONTINUE;
4205
4206 op->type = OP_IMM;
4207 op->bytes = size;
9dac77fa 4208 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4209 /* NB. Immediates are sign-extended as necessary. */
4210 switch (op->bytes) {
4211 case 1:
e85a1085 4212 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4213 break;
4214 case 2:
e85a1085 4215 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4216 break;
4217 case 4:
e85a1085 4218 op->val = insn_fetch(s32, ctxt);
39f21ee5 4219 break;
5e2c6883
NA		 4220 case 8:
4221 op->val = insn_fetch(s64, ctxt);
4222 break;
39f21ee5
AK		 4223 }
4224 if (!sign_extension) {
4225 switch (op->bytes) {
4226 case 1:
4227 op->val &= 0xff;
4228 break;
4229 case 2:
4230 op->val &= 0xffff;
4231 break;
4232 case 4:
4233 op->val &= 0xffffffff;
4234 break;
4235 }
4236 }
4237done:
4238 return rc;
4239}
4240
a9945549
AK		 4241static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4242 unsigned d)
4243{
4244 int rc = X86EMUL_CONTINUE;
4245
4246 switch (d) {
4247 case OpReg:
2adb5ad9 4248 decode_register_operand(ctxt, op);
a9945549
AK		 4249 break;
4250 case OpImmUByte:
608aabe3 4251 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4252 break;
4253 case OpMem:
41ddf978 4254 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4255 mem_common:
4256 *op = ctxt->memop;
4257 ctxt->memopp = op;
96888977 4258 if (ctxt->d & BitOp)
a9945549
AK		 4259 fetch_bit_operand(ctxt);
4260 op->orig_val = op->val;
4261 break;
41ddf978 4262 case OpMem64:
aaa05f24 4263 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4264 goto mem_common;
a9945549
AK		 4265 case OpAcc:
4266 op->type = OP_REG;
4267 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4268 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4269 fetch_register_operand(op);
4270 op->orig_val = op->val;
4271 break;
820207c8
AK		 4272 case OpAccLo:
4273 op->type = OP_REG;
4274 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4275 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4276 fetch_register_operand(op);
4277 op->orig_val = op->val;
4278 break;
4279 case OpAccHi:
4280 if (ctxt->d & ByteOp) {
4281 op->type = OP_NONE;
4282 break;
4283 }
4284 op->type = OP_REG;
4285 op->bytes = ctxt->op_bytes;
4286 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4287 fetch_register_operand(op);
4288 op->orig_val = op->val;
4289 break;
a9945549
AK		 4290 case OpDI:
4291 op->type = OP_MEM;
4292 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4293 op->addr.mem.ea =
01485a22 4294 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4295 op->addr.mem.seg = VCPU_SREG_ES;
4296 op->val = 0;
b3356bf0 4297 op->count = 1;
a9945549
AK		 4298 break;
4299 case OpDX:
4300 op->type = OP_REG;
4301 op->bytes = 2;
dd856efa 4302 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4303 fetch_register_operand(op);
4304 break;
4dd6a57d 4305 case OpCL:
d29b9d7e 4306 op->type = OP_IMM;
4dd6a57d 4307 op->bytes = 1;
dd856efa 4308 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4309 break;
4310 case OpImmByte:
4311 rc = decode_imm(ctxt, op, 1, true);
4312 break;
4313 case OpOne:
d29b9d7e 4314 op->type = OP_IMM;
4dd6a57d
AK		 4315 op->bytes = 1;
4316 op->val = 1;
4317 break;
4318 case OpImm:
4319 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4320 break;
5e2c6883
NA		 4321 case OpImm64:
4322 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4323 break;
28867cee
AK		 4324 case OpMem8:
4325 ctxt->memop.bytes = 1;
660696d1 4326 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4327 ctxt->memop.addr.reg = decode_register(ctxt,
4328 ctxt->modrm_rm, true);
660696d1
GN		 4329 fetch_register_operand(&ctxt->memop);
4330 }
28867cee 4331 goto mem_common;
0fe59128
AK		 4332 case OpMem16:
4333 ctxt->memop.bytes = 2;
4334 goto mem_common;
4335 case OpMem32:
4336 ctxt->memop.bytes = 4;
4337 goto mem_common;
4338 case OpImmU16:
4339 rc = decode_imm(ctxt, op, 2, false);
4340 break;
4341 case OpImmU:
4342 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4343 break;
4344 case OpSI:
4345 op->type = OP_MEM;
4346 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4347 op->addr.mem.ea =
01485a22 4348 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4349 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4350 op->val = 0;
b3356bf0 4351 op->count = 1;
0fe59128 4352 break;
7fa57952
PB		 4353 case OpXLat:
4354 op->type = OP_MEM;
4355 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4356 op->addr.mem.ea =
01485a22 4357 address_mask(ctxt,
7fa57952
PB		 4358 reg_read(ctxt, VCPU_REGS_RBX) +
4359 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4360 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4361 op->val = 0;
4362 break;
0fe59128
AK		 4363 case OpImmFAddr:
4364 op->type = OP_IMM;
4365 op->addr.mem.ea = ctxt->_eip;
4366 op->bytes = ctxt->op_bytes + 2;
4367 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4368 break;
4369 case OpMemFAddr:
4370 ctxt->memop.bytes = ctxt->op_bytes + 2;
4371 goto mem_common;
c191a7a0 4372 case OpES:
d29b9d7e 4373 op->type = OP_IMM;
c191a7a0
AK		 4374 op->val = VCPU_SREG_ES;
4375 break;
4376 case OpCS:
d29b9d7e 4377 op->type = OP_IMM;
c191a7a0
AK		 4378 op->val = VCPU_SREG_CS;
4379 break;
4380 case OpSS:
d29b9d7e 4381 op->type = OP_IMM;
c191a7a0
AK		 4382 op->val = VCPU_SREG_SS;
4383 break;
4384 case OpDS:
d29b9d7e 4385 op->type = OP_IMM;
c191a7a0
AK		 4386 op->val = VCPU_SREG_DS;
4387 break;
4388 case OpFS:
d29b9d7e 4389 op->type = OP_IMM;
c191a7a0
AK		 4390 op->val = VCPU_SREG_FS;
4391 break;
4392 case OpGS:
d29b9d7e 4393 op->type = OP_IMM;
c191a7a0
AK		 4394 op->val = VCPU_SREG_GS;
4395 break;
a9945549
AK		 4396 case OpImplicit:
4397 /* Special instructions do their own operand decoding. */
4398 default:
4399 op->type = OP_NONE; /* Disable writeback. */
4400 break;
4401 }
4402
4403done:
4404 return rc;
4405}
4406
ef5d75cc 4407int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4408{
dde7e6d1
AK		 4409 int rc = X86EMUL_CONTINUE;
4410 int mode = ctxt->mode;
46561646 4411 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4412 bool op_prefix = false;
573e80fe 4413 bool has_seg_override = false;
46561646 4414 struct opcode opcode;
dde7e6d1 4415
f09ed83e
AK		 4416 ctxt->memop.type = OP_NONE;
4417 ctxt->memopp = NULL;
9dac77fa 4418 ctxt->_eip = ctxt->eip;
17052f16
PB		 4419 ctxt->fetch.ptr = ctxt->fetch.data;
4420 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4421 ctxt->opcode_len = 1;
dc25e89e 4422 if (insn_len > 0)
9dac77fa 4423 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4424 else {
9506d57d 4425 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4426 if (rc != X86EMUL_CONTINUE)
4427 return rc;
4428 }
dde7e6d1
AK		 4429
4430 switch (mode) {
4431 case X86EMUL_MODE_REAL:
4432 case X86EMUL_MODE_VM86:
4433 case X86EMUL_MODE_PROT16:
4434 def_op_bytes = def_ad_bytes = 2;
4435 break;
4436 case X86EMUL_MODE_PROT32:
4437 def_op_bytes = def_ad_bytes = 4;
4438 break;
4439#ifdef CONFIG_X86_64
4440 case X86EMUL_MODE_PROT64:
4441 def_op_bytes = 4;
4442 def_ad_bytes = 8;
4443 break;
4444#endif
4445 default:
1d2887e2 4446 return EMULATION_FAILED;
dde7e6d1
AK		 4447 }
4448
9dac77fa
AK		 4449 ctxt->op_bytes = def_op_bytes;
4450 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4451
4452 /* Legacy prefixes. */
4453 for (;;) {
e85a1085 4454 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4455 case 0x66: /* operand-size override */
0d7cdee8 4456 op_prefix = true;
dde7e6d1 4457 /* switch between 2/4 bytes */
9dac77fa 4458 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4459 break;
4460 case 0x67: /* address-size override */
4461 if (mode == X86EMUL_MODE_PROT64)
4462 /* switch between 4/8 bytes */
9dac77fa 4463 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4464 else
4465 /* switch between 2/4 bytes */
9dac77fa 4466 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4467 break;
4468 case 0x26: /* ES override */
4469 case 0x2e: /* CS override */
4470 case 0x36: /* SS override */
4471 case 0x3e: /* DS override */
573e80fe
BD		 4472 has_seg_override = true;
4473 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4474 break;
4475 case 0x64: /* FS override */
4476 case 0x65: /* GS override */
573e80fe
BD		 4477 has_seg_override = true;
4478 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4479 break;
4480 case 0x40 ... 0x4f: /* REX */
4481 if (mode != X86EMUL_MODE_PROT64)
4482 goto done_prefixes;
9dac77fa 4483 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4484 continue;
4485 case 0xf0: /* LOCK */
9dac77fa 4486 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4487 break;
4488 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4489 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4490 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4491 break;
4492 default:
4493 goto done_prefixes;
4494 }
4495
4496 /* Any legacy prefix after a REX prefix nullifies its effect. */
4497
9dac77fa 4498 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4499 }
4500
4501done_prefixes:
4502
4503 /* REX prefix. */
9dac77fa
AK		 4504 if (ctxt->rex_prefix & 8)
4505 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4506
4507 /* Opcode byte(s). */
9dac77fa 4508 opcode = opcode_table[ctxt->b];
d3ad6243 4509 /* Two-byte opcode? */
9dac77fa 4510 if (ctxt->b == 0x0f) {
1ce19dc1 4511 ctxt->opcode_len = 2;
e85a1085 4512 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4513 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4514
4515 /* 0F_38 opcode map */
4516 if (ctxt->b == 0x38) {
4517 ctxt->opcode_len = 3;
4518 ctxt->b = insn_fetch(u8, ctxt);
4519 opcode = opcode_map_0f_38[ctxt->b];
4520 }
dde7e6d1 4521 }
9dac77fa 4522 ctxt->d = opcode.flags;
dde7e6d1 4523
9f4260e7
TY		 4524 if (ctxt->d & ModRM)
4525 ctxt->modrm = insn_fetch(u8, ctxt);
4526
7fe864dc
NA		 4527 /* vex-prefix instructions are not implemented */
4528 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4529 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4530 ctxt->d = NotImpl;
4531 }
4532
9dac77fa
AK		 4533 while (ctxt->d & GroupMask) {
4534 switch (ctxt->d & GroupMask) {
46561646 4535 case Group:
9dac77fa 4536 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4537 opcode = opcode.u.group[goffset];
4538 break;
4539 case GroupDual:
9dac77fa
AK		 4540 goffset = (ctxt->modrm >> 3) & 7;
4541 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4542 opcode = opcode.u.gdual->mod3[goffset];
4543 else
4544 opcode = opcode.u.gdual->mod012[goffset];
4545 break;
4546 case RMExt:
9dac77fa 4547 goffset = ctxt->modrm & 7;
01de8b09 4548 opcode = opcode.u.group[goffset];
46561646
AK		 4549 break;
4550 case Prefix:
9dac77fa 4551 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4552 return EMULATION_FAILED;
9dac77fa 4553 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4554 switch (simd_prefix) {
4555 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4556 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4557 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4558 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4559 }
4560 break;
045a282c
GN		 4561 case Escape:
4562 if (ctxt->modrm > 0xbf)
4563 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4564 else
4565 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4566 break;
39f062ff
NA		 4567 case InstrDual:
4568 if ((ctxt->modrm >> 6) == 3)
4569 opcode = opcode.u.idual->mod3;
4570 else
4571 opcode = opcode.u.idual->mod012;
4572 break;
46561646 4573 default:
1d2887e2 4574 return EMULATION_FAILED;
0d7cdee8 4575 }
46561646 4576
b1ea50b2 4577 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4578 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4579 }
4580
e24186e0
PB		 4581 /* Unrecognised? */
4582 if (ctxt->d == 0)
4583 return EMULATION_FAILED;
4584
9dac77fa 4585 ctxt->execute = opcode.u.execute;
dde7e6d1 4586
3a6095a0
NA		 4587 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4588 return EMULATION_FAILED;
4589
d40a6898 4590 if (unlikely(ctxt->d &
ed9aad21
NA		 4591 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4592 No16))) {
d40a6898
PB		 4593 /*
4594 * These are copied unconditionally here, and checked unconditionally
4595 * in x86_emulate_insn.
4596 */
4597 ctxt->check_perm = opcode.check_perm;
4598 ctxt->intercept = opcode.intercept;
dde7e6d1 4599
d40a6898
PB		 4600 if (ctxt->d & NotImpl)
4601 return EMULATION_FAILED;
d867162c 4602
58b7075d
NA		 4603 if (mode == X86EMUL_MODE_PROT64) {
4604 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4605 ctxt->op_bytes = 8;
4606 else if (ctxt->d & NearBranch)
4607 ctxt->op_bytes = 8;
4608 }
7f9b4b75 4609
d40a6898
PB		 4610 if (ctxt->d & Op3264) {
4611 if (mode == X86EMUL_MODE_PROT64)
4612 ctxt->op_bytes = 8;
4613 else
4614 ctxt->op_bytes = 4;
4615 }
4616
ed9aad21
NA		 4617 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4618 ctxt->op_bytes = 4;
4619
d40a6898
PB		 4620 if (ctxt->d & Sse)
4621 ctxt->op_bytes = 16;
4622 else if (ctxt->d & Mmx)
4623 ctxt->op_bytes = 8;
4624 }
1253791d 4625
dde7e6d1 4626 /* ModRM and SIB bytes. */
9dac77fa 4627 if (ctxt->d & ModRM) {
f09ed83e 4628 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4629 if (!has_seg_override) {
4630 has_seg_override = true;
4631 ctxt->seg_override = ctxt->modrm_seg;
4632 }
9dac77fa 4633 } else if (ctxt->d & MemAbs)
f09ed83e 4634 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637
573e80fe
BD		 4638 if (!has_seg_override)
4639 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4640
573e80fe 4641 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4642
dde7e6d1
AK		 4643 /*
4644 * Decode and fetch the source operand: register, memory
4645 * or immediate.
4646 */
0fe59128 4647 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4648 if (rc != X86EMUL_CONTINUE)
4649 goto done;
4650
dde7e6d1
AK		 4651 /*
4652 * Decode and fetch the second source operand: register, memory
4653 * or immediate.
4654 */
4dd6a57d 4655 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4656 if (rc != X86EMUL_CONTINUE)
4657 goto done;
4658
dde7e6d1 4659 /* Decode and fetch the destination operand: register or memory. */
a9945549 4660 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4661
41061cdb 4662 if (ctxt->rip_relative)
1c1c35ae
NA		 4663 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4664 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4665
a430c916 4666done:
1d2887e2 4667 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4668}
4669
1cb3f3ae
XG		 4670bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4671{
4672 return ctxt->d & PageTable;
4673}
4674
3e2f65d5
GN		 4675static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4676{
3e2f65d5
GN		 4677 /* The second termination condition only applies for REPE
4678 * and REPNE. Test if the repeat string operation prefix is
4679 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4680 * corresponding termination condition according to:
4681 * - if REPE/REPZ and ZF = 0 then done
4682 * - if REPNE/REPNZ and ZF = 1 then done
4683 */
9dac77fa
AK		 4684 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4685 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4686 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4687 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4688 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4689 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4690 return true;
4691
4692 return false;
4693}
4694
cbe2c9d3
AK		 4695static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4696{
4697 bool fault = false;
4698
4699 ctxt->ops->get_fpu(ctxt);
4700 asm volatile("1: fwait \n\t"
4701 "2: \n\t"
4702 ".pushsection .fixup,\"ax\" \n\t"
4703 "3: \n\t"
4704 "movb $1, %[fault] \n\t"
4705 "jmp 2b \n\t"
4706 ".popsection \n\t"
4707 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4708 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4709 ctxt->ops->put_fpu(ctxt);
4710
4711 if (unlikely(fault))
4712 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4713
4714 return X86EMUL_CONTINUE;
4715}
4716
4717static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4718 struct operand *op)
4719{
4720 if (op->type == OP_MM)
4721 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4722}
4723
e28bbd44
AK		 4724static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4725{
4726 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4727 if (!(ctxt->d & ByteOp))
4728 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4729 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4730 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4731 [fastop]"+S"(fop)
4732 : "c"(ctxt->src2.val));
e28bbd44 4733 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4734 if (!fop) /* exception is returned in fop variable */
4735 return emulate_de(ctxt);
e28bbd44
AK		 4736 return X86EMUL_CONTINUE;
4737}
dd856efa 4738
1498507a
BD		 4739void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4740{
573e80fe
BD		 4741 memset(&ctxt->rip_relative, 0,
4742 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4743
1498507a
BD		 4744 ctxt->io_read.pos = 0;
4745 ctxt->io_read.end = 0;
1498507a
BD		 4746 ctxt->mem_read.end = 0;
4747}
4748
7b105ca2 4749int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4750{
0225fb50 4751 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4752 int rc = X86EMUL_CONTINUE;
9dac77fa 4753 int saved_dst_type = ctxt->dst.type;
8b4caf66 4754
9dac77fa 4755 ctxt->mem_read.pos = 0;
310b5d30 4756
e24186e0
PB		 4757 /* LOCK prefix is allowed only with some instructions */
4758 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4759 rc = emulate_ud(ctxt);
1161624f
GN		 4760 goto done;
4761 }
4762
e24186e0 4763 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4764 rc = emulate_ud(ctxt);
d380a5e4
GN		 4765 goto done;
4766 }
4767
d40a6898
PB		 4768 if (unlikely(ctxt->d &
4769 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4770 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4771 (ctxt->d & Undefined)) {
4772 rc = emulate_ud(ctxt);
4773 goto done;
4774 }
1253791d 4775
d40a6898
PB		 4776 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4777 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4778 rc = emulate_ud(ctxt);
cbe2c9d3 4779 goto done;
d40a6898 4780 }
cbe2c9d3 4781
d40a6898
PB		 4782 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4783 rc = emulate_nm(ctxt);
c4f035c6 4784 goto done;
d40a6898 4785 }
c4f035c6 4786
d40a6898
PB		 4787 if (ctxt->d & Mmx) {
4788 rc = flush_pending_x87_faults(ctxt);
4789 if (rc != X86EMUL_CONTINUE)
4790 goto done;
4791 /*
4792 * Now that we know the fpu is exception safe, we can fetch
4793 * operands from it.
4794 */
4795 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4796 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4797 if (!(ctxt->d & Mov))
4798 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4799 }
e92805ac 4800
685bbf4a 4801 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4802 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4803 X86_ICPT_PRE_EXCEPT);
4804 if (rc != X86EMUL_CONTINUE)
4805 goto done;
4806 }
8ea7d6ae 4807
64a38292
NA		 4808 /* Instruction can only be executed in protected mode */
4809 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4810 rc = emulate_ud(ctxt);
4811 goto done;
4812 }
4813
d40a6898
PB		 4814 /* Privileged instruction can be executed only in CPL=0 */
4815 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4816 if (ctxt->d & PrivUD)
4817 rc = emulate_ud(ctxt);
4818 else
4819 rc = emulate_gp(ctxt, 0);
d09beabd 4820 goto done;
d40a6898 4821 }
d09beabd 4822
d40a6898 4823 /* Do instruction specific permission checks */
685bbf4a 4824 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4825 rc = ctxt->check_perm(ctxt);
4826 if (rc != X86EMUL_CONTINUE)
4827 goto done;
4828 }
4829
685bbf4a 4830 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4831 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4832 X86_ICPT_POST_EXCEPT);
4833 if (rc != X86EMUL_CONTINUE)
4834 goto done;
4835 }
4836
4837 if (ctxt->rep_prefix && (ctxt->d & String)) {
4838 /* All REP prefixes have the same first termination condition */
4839 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4840 ctxt->eip = ctxt->_eip;
4467c3f1 4841 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4842 goto done;
4843 }
b9fa9d6b 4844 }
b9fa9d6b
AK		 4845 }
4846
9dac77fa
AK		 4847 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4848 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4849 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4850 if (rc != X86EMUL_CONTINUE)
8b4caf66 4851 goto done;
9dac77fa 4852 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4853 }
4854
9dac77fa
AK		 4855 if (ctxt->src2.type == OP_MEM) {
4856 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4857 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4858 if (rc != X86EMUL_CONTINUE)
4859 goto done;
4860 }
4861
9dac77fa 4862 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4863 goto special_insn;
4864
4865
9dac77fa 4866 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4867 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4868 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4869 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4870 if (rc != X86EMUL_CONTINUE)
4871 goto done;
038e51de 4872 }
9dac77fa 4873 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4874
018a98db
AK		 4875special_insn:
4876
685bbf4a 4877 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4878 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4879 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4880 if (rc != X86EMUL_CONTINUE)
4881 goto done;
4882 }
4883
b9a1ecb9
NA		 4884 if (ctxt->rep_prefix && (ctxt->d & String))
4885 ctxt->eflags |= EFLG_RF;
4886 else
4887 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4888
9dac77fa 4889 if (ctxt->execute) {
e28bbd44
AK		 4890 if (ctxt->d & Fastop) {
4891 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4892 rc = fastop(ctxt, fop);
4893 if (rc != X86EMUL_CONTINUE)
4894 goto done;
4895 goto writeback;
4896 }
9dac77fa 4897 rc = ctxt->execute(ctxt);
ef65c889
AK		 4898 if (rc != X86EMUL_CONTINUE)
4899 goto done;
4900 goto writeback;
4901 }
4902
1ce19dc1 4903 if (ctxt->opcode_len == 2)
6aa8b732 4904 goto twobyte_insn;
0bc5eedb
BP		 4905 else if (ctxt->opcode_len == 3)
4906 goto threebyte_insn;
6aa8b732 4907
9dac77fa 4908 switch (ctxt->b) {
6aa8b732 4909 case 0x63: /* movsxd */
8b4caf66 4910 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4911 goto cannot_emulate;
9dac77fa 4912 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4913 break;
b2833e3c 4914 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4915 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4916 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4917 break;
7e0b54b1 4918 case 0x8d: /* lea r16/r32, m */
9dac77fa 4919 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4920 break;
3d9e77df 4921 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4922 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4923 ctxt->dst.type = OP_NONE;
4924 else
4925 rc = em_xchg(ctxt);
e4f973ae 4926 break;
e8b6fa70 4927 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4928 switch (ctxt->op_bytes) {
4929 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4930 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4931 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4932 }
4933 break;
6e154e56 4934 case 0xcc: /* int3 */
5c5df76b
TY		 4935 rc = emulate_int(ctxt, 3);
4936 break;
6e154e56 4937 case 0xcd: /* int n */
9dac77fa 4938 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4939 break;
4940 case 0xce: /* into */
5c5df76b
TY		 4941 if (ctxt->eflags & EFLG_OF)
4942 rc = emulate_int(ctxt, 4);
6e154e56 4943 break;
1a52e051 4944 case 0xe9: /* jmp rel */
db5b0762 4945 case 0xeb: /* jmp rel short */
234f3ce4 4946 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4947 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4948 break;
111de5d6 4949 case 0xf4: /* hlt */
6c3287f7 4950 ctxt->ops->halt(ctxt);
19fdfa0d 4951 break;
111de5d6
AK		 4952 case 0xf5: /* cmc */
4953 /* complement carry flag from eflags reg */
4954 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4955 break;
4956 case 0xf8: /* clc */
4957 ctxt->eflags &= ~EFLG_CF;
111de5d6 4958 break;
8744aa9a
MG		 4959 case 0xf9: /* stc */
4960 ctxt->eflags |= EFLG_CF;
4961 break;
fb4616f4
MG		 4962 case 0xfc: /* cld */
4963 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4964 break;
4965 case 0xfd: /* std */
4966 ctxt->eflags |= EFLG_DF;
fb4616f4 4967 break;
91269b8f
AK		 4968 default:
4969 goto cannot_emulate;
6aa8b732 4970 }
018a98db 4971
7d9ddaed
AK		 4972 if (rc != X86EMUL_CONTINUE)
4973 goto done;
4974
018a98db 4975writeback:
fb32b1ed
AK		 4976 if (ctxt->d & SrcWrite) {
4977 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4978 rc = writeback(ctxt, &ctxt->src);
4979 if (rc != X86EMUL_CONTINUE)
4980 goto done;
4981 }
ee212297
NA		 4982 if (!(ctxt->d & NoWrite)) {
4983 rc = writeback(ctxt, &ctxt->dst);
4984 if (rc != X86EMUL_CONTINUE)
4985 goto done;
4986 }
018a98db 4987
5cd21917
GN		 4988 /*
4989 * restore dst type in case the decoding will be reused
4990 * (happens for string instruction )
4991 */
9dac77fa 4992 ctxt->dst.type = saved_dst_type;
5cd21917 4993
9dac77fa 4994 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4995 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4996
9dac77fa 4997 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4998 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4999
9dac77fa 5000 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5001 unsigned int count;
9dac77fa 5002 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5003 if ((ctxt->d & SrcMask) == SrcSI)
5004 count = ctxt->src.count;
5005 else
5006 count = ctxt->dst.count;
01485a22 5007 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5008
d2ddd1c4
GN		 5009 if (!string_insn_completed(ctxt)) {
5010 /*
5011 * Re-enter guest when pio read ahead buffer is empty
5012 * or, if it is not used, after each 1024 iteration.
5013 */
dd856efa 5014 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5015 (r->end == 0 || r->end != r->pos)) {
5016 /*
5017 * Reset read cache. Usually happens before
5018 * decode, but since instruction is restarted
5019 * we have to do it here.
5020 */
9dac77fa 5021 ctxt->mem_read.end = 0;
dd856efa 5022 writeback_registers(ctxt);
d2ddd1c4
GN		 5023 return EMULATION_RESTART;
5024 }
5025 goto done; /* skip rip writeback */
0fa6ccbd 5026 }
b9a1ecb9 5027 ctxt->eflags &= ~EFLG_RF;
5cd21917 5028 }
d2ddd1c4 5029
9dac77fa 5030 ctxt->eip = ctxt->_eip;
018a98db
AK		 5031
5032done:
e0ad0b47
PB		 5033 if (rc == X86EMUL_PROPAGATE_FAULT) {
5034 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5035 ctxt->have_exception = true;
e0ad0b47 5036 }
775fde86
JR		 5037 if (rc == X86EMUL_INTERCEPTED)
5038 return EMULATION_INTERCEPTED;
5039
dd856efa
AK		 5040 if (rc == X86EMUL_CONTINUE)
5041 writeback_registers(ctxt);
5042
d2ddd1c4 5043 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5044
5045twobyte_insn:
9dac77fa 5046 switch (ctxt->b) {
018a98db 5047 case 0x09: /* wbinvd */
cfb22375 5048 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5049 break;
5050 case 0x08: /* invd */
018a98db
AK		 5051 case 0x0d: /* GrpP (prefetch) */
5052 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5053 case 0x1f: /* nop */
018a98db
AK		 5054 break;
5055 case 0x20: /* mov cr, reg */
9dac77fa 5056 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5057 break;
6aa8b732 5058 case 0x21: /* mov from dr to reg */
9dac77fa 5059 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5060 break;
6aa8b732 5061 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5062 if (test_cc(ctxt->b, ctxt->eflags))
5063 ctxt->dst.val = ctxt->src.val;
5064 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5065 ctxt->op_bytes != 4)
9dac77fa 5066 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5067 break;
b2833e3c 5068 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5069 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5070 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5071 break;
ee45b58e 5072 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5073 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5074 break;
6aa8b732 5075 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5076 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5077 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5078 : (u16) ctxt->src.val;
6aa8b732 5079 break;
6aa8b732 5080 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5081 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5082 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5083 (s16) ctxt->src.val;
6aa8b732 5084 break;
91269b8f
AK		 5085 default:
5086 goto cannot_emulate;
6aa8b732 5087 }
7d9ddaed 5088
0bc5eedb
BP		 5089threebyte_insn:
5090
7d9ddaed
AK		 5091 if (rc != X86EMUL_CONTINUE)
5092 goto done;
5093
6aa8b732
AK		 5094 goto writeback;
5095
5096cannot_emulate:
a0c0ab2f 5097 return EMULATION_FAILED;
6aa8b732 5098}
dd856efa
AK		 5099
5100void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5101{
5102 invalidate_registers(ctxt);
5103}
5104
5105void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5106{
5107 writeback_registers(ctxt);
5108}
Linux kernel - Deliverables
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