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KVM: x86 emulator: add support for writing back the source operand
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
0fe59128
AK		 64
65#define OpBits 5 /* Width of operand field */
b1ea50b2 66#define OpMask ((1ull << OpBits) - 1)
a9945549 67
6aa8b732
AK		 68/*
69 * Opcode effective-address decode tables.
70 * Note that we only emulate instructions that have at least one memory
71 * operand (excluding implicit stack references). We assume that stack
72 * references and instruction fetches will never occur in special memory
73 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
74 * not be handled.
75 */
76
77/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 78#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 79/* Destination operand type. */
a9945549
AK		 80#define DstShift 1
81#define ImplicitOps (OpImplicit << DstShift)
82#define DstReg (OpReg << DstShift)
83#define DstMem (OpMem << DstShift)
84#define DstAcc (OpAcc << DstShift)
85#define DstDI (OpDI << DstShift)
86#define DstMem64 (OpMem64 << DstShift)
87#define DstImmUByte (OpImmUByte << DstShift)
88#define DstDX (OpDX << DstShift)
89#define DstMask (OpMask << DstShift)
6aa8b732 90/* Source operand type. */
0fe59128
AK		 91#define SrcShift 6
92#define SrcNone (OpNone << SrcShift)
93#define SrcReg (OpReg << SrcShift)
94#define SrcMem (OpMem << SrcShift)
95#define SrcMem16 (OpMem16 << SrcShift)
96#define SrcMem32 (OpMem32 << SrcShift)
97#define SrcImm (OpImm << SrcShift)
98#define SrcImmByte (OpImmByte << SrcShift)
99#define SrcOne (OpOne << SrcShift)
100#define SrcImmUByte (OpImmUByte << SrcShift)
101#define SrcImmU (OpImmU << SrcShift)
102#define SrcSI (OpSI << SrcShift)
7fa57952 103#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 104#define SrcImmFAddr (OpImmFAddr << SrcShift)
105#define SrcMemFAddr (OpMemFAddr << SrcShift)
106#define SrcAcc (OpAcc << SrcShift)
107#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 108#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 109#define SrcDX (OpDX << SrcShift)
28867cee 110#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 111#define SrcMask (OpMask << SrcShift)
221192bd
MT		 112#define BitOp (1<<11)
113#define MemAbs (1<<12) /* Memory operand is absolute displacement */
114#define String (1<<13) /* String instruction (rep capable) */
115#define Stack (1<<14) /* Stack instruction (push/pop) */
116#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
117#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
118#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
119#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
120#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 121#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 122#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 123/* Generic ModRM decode. */
124#define ModRM (1<<19)
125/* Destination is only written; never read. */
126#define Mov (1<<20)
d8769fed 127/* Misc flags */
8ea7d6ae 128#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 129#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 130#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 131#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 132#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 133#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 134#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 135#define No64 (1<<28)
d5ae7ce8 136#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 137#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 138/* Source 2 operand type */
0b789eee 139#define Src2Shift (31)
4dd6a57d
AK		 140#define Src2None (OpNone << Src2Shift)
141#define Src2CL (OpCL << Src2Shift)
142#define Src2ImmByte (OpImmByte << Src2Shift)
143#define Src2One (OpOne << Src2Shift)
144#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 145#define Src2ES (OpES << Src2Shift)
146#define Src2CS (OpCS << Src2Shift)
147#define Src2SS (OpSS << Src2Shift)
148#define Src2DS (OpDS << Src2Shift)
149#define Src2FS (OpFS << Src2Shift)
150#define Src2GS (OpGS << Src2Shift)
4dd6a57d 151#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 152#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 153#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
154#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
155#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 156#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 157#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 158#define SrcWrite ((u64)1 << 46) /* Write back src operand */
6aa8b732 159
d0e53325
AK		 160#define X2(x...) x, x
161#define X3(x...) X2(x), x
162#define X4(x...) X2(x), X2(x)
163#define X5(x...) X4(x), x
164#define X6(x...) X4(x), X2(x)
165#define X7(x...) X4(x), X3(x)
166#define X8(x...) X4(x), X4(x)
167#define X16(x...) X8(x), X8(x)
83babbca 168
e28bbd44
AK		 169#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
170#define FASTOP_SIZE 8
171
172/*
173 * fastop functions have a special calling convention:
174 *
175 * dst: [rdx]:rax (in/out)
176 * src: rbx (in/out)
177 * src2: rcx (in)
178 * flags: rflags (in/out)
179 *
180 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
181 * different operand sizes can be reached by calculation, rather than a jump
182 * table (which would be bigger than the code).
183 *
184 * fastop functions are declared as taking a never-defined fastop parameter,
185 * so they can't be called from C directly.
186 */
187
188struct fastop;
189
d65b1dee 190struct opcode {
b1ea50b2
AK		 191 u64 flags : 56;
192 u64 intercept : 8;
120df890 193 union {
ef65c889 194 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 195 const struct opcode *group;
196 const struct group_dual *gdual;
197 const struct gprefix *gprefix;
045a282c 198 const struct escape *esc;
e28bbd44 199 void (*fastop)(struct fastop *fake);
120df890 200 } u;
d09beabd 201 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 202};
203
204struct group_dual {
205 struct opcode mod012[8];
206 struct opcode mod3[8];
d65b1dee
AK		 207};
208
0d7cdee8
AK		 209struct gprefix {
210 struct opcode pfx_no;
211 struct opcode pfx_66;
212 struct opcode pfx_f2;
213 struct opcode pfx_f3;
214};
215
045a282c
GN		 216struct escape {
217 struct opcode op[8];
218 struct opcode high[64];
219};
220
6aa8b732 221/* EFLAGS bit definitions. */
d4c6a154
GN		 222#define EFLG_ID (1<<21)
223#define EFLG_VIP (1<<20)
224#define EFLG_VIF (1<<19)
225#define EFLG_AC (1<<18)
b1d86143
AP		 226#define EFLG_VM (1<<17)
227#define EFLG_RF (1<<16)
d4c6a154
GN		 228#define EFLG_IOPL (3<<12)
229#define EFLG_NT (1<<14)
6aa8b732
AK		 230#define EFLG_OF (1<<11)
231#define EFLG_DF (1<<10)
b1d86143 232#define EFLG_IF (1<<9)
d4c6a154 233#define EFLG_TF (1<<8)
6aa8b732
AK		 234#define EFLG_SF (1<<7)
235#define EFLG_ZF (1<<6)
236#define EFLG_AF (1<<4)
237#define EFLG_PF (1<<2)
238#define EFLG_CF (1<<0)
239
62bd430e
MG		 240#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
241#define EFLG_RESERVED_ONE_MASK 2
242
dd856efa
AK		 243static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
244{
245 if (!(ctxt->regs_valid & (1 << nr))) {
246 ctxt->regs_valid |= 1 << nr;
247 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
248 }
249 return ctxt->_regs[nr];
250}
251
252static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
253{
254 ctxt->regs_valid |= 1 << nr;
255 ctxt->regs_dirty |= 1 << nr;
256 return &ctxt->_regs[nr];
257}
258
259static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
260{
261 reg_read(ctxt, nr);
262 return reg_write(ctxt, nr);
263}
264
265static void writeback_registers(struct x86_emulate_ctxt *ctxt)
266{
267 unsigned reg;
268
269 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
270 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
271}
272
273static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
274{
275 ctxt->regs_dirty = 0;
276 ctxt->regs_valid = 0;
277}
278
6aa8b732
AK		 279/*
280 * Instruction emulation:
281 * Most instructions are emulated directly via a fragment of inline assembly
282 * code. This allows us to save/restore EFLAGS and thus very easily pick up
283 * any modified flags.
284 */
285
05b3e0c2 286#if defined(CONFIG_X86_64)
6aa8b732
AK		 287#define _LO32 "k" /* force 32-bit operand */
288#define _STK "%%rsp" /* stack pointer */
289#elif defined(__i386__)
290#define _LO32 "" /* force 32-bit operand */
291#define _STK "%%esp" /* stack pointer */
292#endif
293
294/*
295 * These EFLAGS bits are restored from saved value during emulation, and
296 * any changes are written back to the saved value after emulation.
297 */
298#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
299
300/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 301#define _PRE_EFLAGS(_sav, _msk, _tmp) \
302 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
303 "movl %"_sav",%"_LO32 _tmp"; " \
304 "push %"_tmp"; " \
305 "push %"_tmp"; " \
306 "movl %"_msk",%"_LO32 _tmp"; " \
307 "andl %"_LO32 _tmp",("_STK"); " \
308 "pushf; " \
309 "notl %"_LO32 _tmp"; " \
310 "andl %"_LO32 _tmp",("_STK"); " \
311 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
312 "pop %"_tmp"; " \
313 "orl %"_LO32 _tmp",("_STK"); " \
314 "popf; " \
315 "pop %"_sav"; "
6aa8b732
AK		 316
317/* After executing instruction: write-back necessary bits in EFLAGS. */
318#define _POST_EFLAGS(_sav, _msk, _tmp) \
319 /* _sav |= EFLAGS & _msk; */ \
320 "pushf; " \
321 "pop %"_tmp"; " \
322 "andl %"_msk",%"_LO32 _tmp"; " \
323 "orl %"_LO32 _tmp",%"_sav"; "
324
dda96d8f
AK		 325#ifdef CONFIG_X86_64
326#define ON64(x) x
327#else
328#define ON64(x)
329#endif
330
a31b9cea 331#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 332 do { \
333 __asm__ __volatile__ ( \
334 _PRE_EFLAGS("0", "4", "2") \
335 _op _suffix " %"_x"3,%1; " \
336 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 337 : "=m" ((ctxt)->eflags), \
338 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 339 "=&r" (_tmp) \
a31b9cea 340 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 341 } while (0)
6b7ad61f
AK		 342
343
6aa8b732 344/* Raw emulation: instruction has two explicit operands. */
a31b9cea 345#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 346 do { \
347 unsigned long _tmp; \
348 \
a31b9cea 349 switch ((ctxt)->dst.bytes) { \
6b7ad61f 350 case 2: \
a31b9cea 351 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 352 break; \
353 case 4: \
a31b9cea 354 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 355 break; \
356 case 8: \
a31b9cea 357 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 358 break; \
359 } \
6aa8b732
AK		 360 } while (0)
361
a31b9cea 362#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 363 do { \
6b7ad61f 364 unsigned long _tmp; \
a31b9cea 365 switch ((ctxt)->dst.bytes) { \
6aa8b732 366 case 1: \
a31b9cea 367 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 368 break; \
369 default: \
a31b9cea 370 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 371 _wx, _wy, _lx, _ly, _qx, _qy); \
372 break; \
373 } \
374 } while (0)
375
376/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 377#define emulate_2op_SrcB(ctxt, _op) \
378 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 379
380/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 381#define emulate_2op_SrcV(ctxt, _op) \
382 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 383
384/* Source operand is word, long or quad sized. */
a31b9cea
AK		 385#define emulate_2op_SrcV_nobyte(ctxt, _op) \
386 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 387
d175226a 388/* Instruction has three operands and one operand is stored in ECX register */
29053a60 389#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 390 do { \
391 unsigned long _tmp; \
761441b9
AK		 392 _type _clv = (ctxt)->src2.val; \
393 _type _srcv = (ctxt)->src.val; \
394 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 395 \
396 __asm__ __volatile__ ( \
397 _PRE_EFLAGS("0", "5", "2") \
398 _op _suffix " %4,%1 \n" \
399 _POST_EFLAGS("0", "5", "2") \
761441b9 400 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 401 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
402 ); \
403 \
761441b9
AK		 404 (ctxt)->src2.val = (unsigned long) _clv; \
405 (ctxt)->src2.val = (unsigned long) _srcv; \
406 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 407 } while (0)
408
761441b9 409#define emulate_2op_cl(ctxt, _op) \
7295261c 410 do { \
761441b9 411 switch ((ctxt)->dst.bytes) { \
7295261c 412 case 2: \
29053a60 413 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 414 break; \
415 case 4: \
29053a60 416 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 417 break; \
418 case 8: \
29053a60 419 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 420 break; \
421 } \
d175226a
GT		 422 } while (0)
423
d1eef45d 424#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 425 do { \
426 unsigned long _tmp; \
427 \
dda96d8f
AK		 428 __asm__ __volatile__ ( \
429 _PRE_EFLAGS("0", "3", "2") \
430 _op _suffix " %1; " \
431 _POST_EFLAGS("0", "3", "2") \
d1eef45d 432 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 433 "=&r" (_tmp) \
434 : "i" (EFLAGS_MASK)); \
435 } while (0)
436
437/* Instruction has only one explicit operand (no source operand). */
d1eef45d 438#define emulate_1op(ctxt, _op) \
dda96d8f 439 do { \
d1eef45d
AK		 440 switch ((ctxt)->dst.bytes) { \
441 case 1: __emulate_1op(ctxt, _op, "b"); break; \
442 case 2: __emulate_1op(ctxt, _op, "w"); break; \
443 case 4: __emulate_1op(ctxt, _op, "l"); break; \
444 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 445 } \
446 } while (0)
447
4d758349
AK		 448static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
449
b7d491e7
AK		 450#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
451#define FOP_RET "ret \n\t"
452
453#define FOP_START(op) \
454 extern void em_##op(struct fastop *fake); \
455 asm(".pushsection .text, \"ax\" \n\t" \
456 ".global em_" #op " \n\t" \
457 FOP_ALIGN \
458 "em_" #op ": \n\t"
459
460#define FOP_END \
461 ".popsection")
462
0bdea068
AK		 463#define FOPNOP() FOP_ALIGN FOP_RET
464
b7d491e7
AK		 465#define FOP1E(op, dst) \
466 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
467
468#define FASTOP1(op) \
469 FOP_START(op) \
470 FOP1E(op##b, al) \
471 FOP1E(op##w, ax) \
472 FOP1E(op##l, eax) \
473 ON64(FOP1E(op##q, rax)) \
474 FOP_END
475
f7857f35
AK		 476#define FOP2E(op, dst, src) \
477 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
478
479#define FASTOP2(op) \
480 FOP_START(op) \
481 FOP2E(op##b, al, bl) \
482 FOP2E(op##w, ax, bx) \
483 FOP2E(op##l, eax, ebx) \
484 ON64(FOP2E(op##q, rax, rbx)) \
485 FOP_END
486
11c363ba
AK		 487/* 2 operand, word only */
488#define FASTOP2W(op) \
489 FOP_START(op) \
490 FOPNOP() \
491 FOP2E(op##w, ax, bx) \
492 FOP2E(op##l, eax, ebx) \
493 ON64(FOP2E(op##q, rax, rbx)) \
494 FOP_END
495
007a3b54
AK		 496/* 2 operand, src is CL */
497#define FASTOP2CL(op) \
498 FOP_START(op) \
499 FOP2E(op##b, al, cl) \
500 FOP2E(op##w, ax, cl) \
501 FOP2E(op##l, eax, cl) \
502 ON64(FOP2E(op##q, rax, cl)) \
503 FOP_END
504
0bdea068
AK		 505#define FOP3E(op, dst, src, src2) \
506 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
507
508/* 3-operand, word-only, src2=cl */
509#define FASTOP3WCL(op) \
510 FOP_START(op) \
511 FOPNOP() \
512 FOP3E(op##w, ax, bx, cl) \
513 FOP3E(op##l, eax, ebx, cl) \
514 ON64(FOP3E(op##q, rax, rbx, cl)) \
515 FOP_END
516
9ae9feba
AK		 517/* Special case for SETcc - 1 instruction per cc */
518#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
519
520FOP_START(setcc)
521FOP_SETCC(seto)
522FOP_SETCC(setno)
523FOP_SETCC(setc)
524FOP_SETCC(setnc)
525FOP_SETCC(setz)
526FOP_SETCC(setnz)
527FOP_SETCC(setbe)
528FOP_SETCC(setnbe)
529FOP_SETCC(sets)
530FOP_SETCC(setns)
531FOP_SETCC(setp)
532FOP_SETCC(setnp)
533FOP_SETCC(setl)
534FOP_SETCC(setnl)
535FOP_SETCC(setle)
536FOP_SETCC(setnle)
537FOP_END;
538
326f578f
PB		 539FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
540FOP_END;
541
e8f2b1d6 542#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 543 do { \
544 unsigned long _tmp; \
dd856efa
AK		 545 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
546 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 547 \
548 __asm__ __volatile__ ( \
549 _PRE_EFLAGS("0", "5", "1") \
550 "1: \n\t" \
551 _op _suffix " %6; " \
552 "2: \n\t" \
553 _POST_EFLAGS("0", "5", "1") \
554 ".pushsection .fixup,\"ax\" \n\t" \
555 "3: movb $1, %4 \n\t" \
556 "jmp 2b \n\t" \
557 ".popsection \n\t" \
558 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 559 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
560 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 561 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 562 } while (0)
563
3f9f53b0 564/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 565#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 566 do { \
e8f2b1d6 567 switch((ctxt)->src.bytes) { \
7295261c 568 case 1: \
e8f2b1d6 569 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 570 break; \
571 case 2: \
e8f2b1d6 572 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 573 break; \
574 case 4: \
e8f2b1d6 575 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 576 break; \
577 case 8: ON64( \
e8f2b1d6 578 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 579 break; \
580 } \
581 } while (0)
582
8a76d7f2
JR		 583static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
584 enum x86_intercept intercept,
585 enum x86_intercept_stage stage)
586{
587 struct x86_instruction_info info = {
588 .intercept = intercept,
9dac77fa
AK		 589 .rep_prefix = ctxt->rep_prefix,
590 .modrm_mod = ctxt->modrm_mod,
591 .modrm_reg = ctxt->modrm_reg,
592 .modrm_rm = ctxt->modrm_rm,
593 .src_val = ctxt->src.val64,
594 .src_bytes = ctxt->src.bytes,
595 .dst_bytes = ctxt->dst.bytes,
596 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 597 .next_rip = ctxt->eip,
598 };
599
2953538e 600 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 601}
602
f47cfa31
AK		 603static void assign_masked(ulong *dest, ulong src, ulong mask)
604{
605 *dest = (*dest & ~mask) | (src & mask);
606}
607
9dac77fa 608static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 609{
9dac77fa 610 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 611}
612
f47cfa31
AK		 613static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
614{
615 u16 sel;
616 struct desc_struct ss;
617
618 if (ctxt->mode == X86EMUL_MODE_PROT64)
619 return ~0UL;
620 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
621 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
622}
623
612e89f0
AK		 624static int stack_size(struct x86_emulate_ctxt *ctxt)
625{
626 return (__fls(stack_mask(ctxt)) + 1) >> 3;
627}
628
6aa8b732 629/* Access/update address held in a register, based on addressing mode. */
e4706772 630static inline unsigned long
9dac77fa 631address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 632{
9dac77fa 633 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 634 return reg;
635 else
9dac77fa 636 return reg & ad_mask(ctxt);
e4706772
HH		 637}
638
639static inline unsigned long
9dac77fa 640register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 641{
9dac77fa 642 return address_mask(ctxt, reg);
e4706772
HH		 643}
644
5ad105e5
AK		 645static void masked_increment(ulong *reg, ulong mask, int inc)
646{
647 assign_masked(reg, *reg + inc, mask);
648}
649
7a957275 650static inline void
9dac77fa 651register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 652{
5ad105e5
AK		 653 ulong mask;
654
9dac77fa 655 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 656 mask = ~0UL;
7a957275 657 else
5ad105e5
AK		 658 mask = ad_mask(ctxt);
659 masked_increment(reg, mask, inc);
660}
661
662static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
663{
dd856efa 664 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 665}
6aa8b732 666
9dac77fa 667static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 668{
9dac77fa 669 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 670}
098c937b 671
56697687
AK		 672static u32 desc_limit_scaled(struct desc_struct *desc)
673{
674 u32 limit = get_desc_limit(desc);
675
676 return desc->g ? (limit << 12) | 0xfff : limit;
677}
678
9dac77fa 679static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 680{
9dac77fa
AK		 681 ctxt->has_seg_override = true;
682 ctxt->seg_override = seg;
7a5b56df
AK		 683}
684
7b105ca2 685static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 686{
687 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
688 return 0;
689
7b105ca2 690 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 691}
692
9dac77fa 693static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 694{
9dac77fa 695 if (!ctxt->has_seg_override)
7a5b56df
AK		 696 return 0;
697
9dac77fa 698 return ctxt->seg_override;
7a5b56df
AK		 699}
700
35d3d4a1
AK		 701static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
702 u32 error, bool valid)
54b8486f 703{
da9cb575
AK		 704 ctxt->exception.vector = vec;
705 ctxt->exception.error_code = error;
706 ctxt->exception.error_code_valid = valid;
35d3d4a1 707 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 708}
709
3b88e41a
JR		 710static int emulate_db(struct x86_emulate_ctxt *ctxt)
711{
712 return emulate_exception(ctxt, DB_VECTOR, 0, false);
713}
714
35d3d4a1 715static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 716{
35d3d4a1 717 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 718}
719
618ff15d
AK		 720static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
721{
722 return emulate_exception(ctxt, SS_VECTOR, err, true);
723}
724
35d3d4a1 725static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 726{
35d3d4a1 727 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 728}
729
35d3d4a1 730static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 731{
35d3d4a1 732 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 733}
734
34d1f490
AK		 735static int emulate_de(struct x86_emulate_ctxt *ctxt)
736{
35d3d4a1 737 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 738}
739
1253791d
AK		 740static int emulate_nm(struct x86_emulate_ctxt *ctxt)
741{
742 return emulate_exception(ctxt, NM_VECTOR, 0, false);
743}
744
1aa36616
AK		 745static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
746{
747 u16 selector;
748 struct desc_struct desc;
749
750 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
751 return selector;
752}
753
754static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
755 unsigned seg)
756{
757 u16 dummy;
758 u32 base3;
759 struct desc_struct desc;
760
761 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
762 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
763}
764
1c11b376
AK		 765/*
766 * x86 defines three classes of vector instructions: explicitly
767 * aligned, explicitly unaligned, and the rest, which change behaviour
768 * depending on whether they're AVX encoded or not.
769 *
770 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
771 * subject to the same check.
772 */
773static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
774{
775 if (likely(size < 16))
776 return false;
777
778 if (ctxt->d & Aligned)
779 return true;
780 else if (ctxt->d & Unaligned)
781 return false;
782 else if (ctxt->d & Avx)
783 return false;
784 else
785 return true;
786}
787
3d9b938e 788static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 789 struct segmented_address addr,
3d9b938e 790 unsigned size, bool write, bool fetch,
52fd8b44
AK		 791 ulong *linear)
792{
618ff15d
AK		 793 struct desc_struct desc;
794 bool usable;
52fd8b44 795 ulong la;
618ff15d 796 u32 lim;
1aa36616 797 u16 sel;
3a78a4f4 798 unsigned cpl;
52fd8b44 799
7b105ca2 800 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 801 switch (ctxt->mode) {
618ff15d
AK		 802 case X86EMUL_MODE_PROT64:
803 if (((signed long)la << 16) >> 16 != la)
804 return emulate_gp(ctxt, 0);
805 break;
806 default:
1aa36616
AK		 807 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
808 addr.seg);
618ff15d
AK		 809 if (!usable)
810 goto bad;
58b7825b
GN		 811 /* code segment in protected mode or read-only data segment */
812 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
813 || !(desc.type & 2)) && write)
618ff15d
AK		 814 goto bad;
815 /* unreadable code segment */
3d9b938e 816 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 817 goto bad;
818 lim = desc_limit_scaled(&desc);
819 if ((desc.type & 8) || !(desc.type & 4)) {
820 /* expand-up segment */
821 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
822 goto bad;
823 } else {
fc058680 824 /* expand-down segment */
618ff15d
AK		 825 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
826 goto bad;
827 lim = desc.d ? 0xffffffff : 0xffff;
828 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
829 goto bad;
830 }
717746e3 831 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 832 if (!(desc.type & 8)) {
833 /* data segment */
834 if (cpl > desc.dpl)
835 goto bad;
836 } else if ((desc.type & 8) && !(desc.type & 4)) {
837 /* nonconforming code segment */
838 if (cpl != desc.dpl)
839 goto bad;
840 } else if ((desc.type & 8) && (desc.type & 4)) {
841 /* conforming code segment */
842 if (cpl < desc.dpl)
843 goto bad;
844 }
845 break;
846 }
9dac77fa 847 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 848 la &= (u32)-1;
1c11b376
AK		 849 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
850 return emulate_gp(ctxt, 0);
52fd8b44
AK		 851 *linear = la;
852 return X86EMUL_CONTINUE;
618ff15d
AK		 853bad:
854 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 855 return emulate_ss(ctxt, sel);
618ff15d 856 else
0afbe2f8 857 return emulate_gp(ctxt, sel);
52fd8b44
AK		 858}
859
3d9b938e
NE		 860static int linearize(struct x86_emulate_ctxt *ctxt,
861 struct segmented_address addr,
862 unsigned size, bool write,
863 ulong *linear)
864{
865 return __linearize(ctxt, addr, size, write, false, linear);
866}
867
868
3ca3ac4d
AK		 869static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
870 struct segmented_address addr,
871 void *data,
872 unsigned size)
873{
9fa088f4
AK		 874 int rc;
875 ulong linear;
876
83b8795a 877 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 878 if (rc != X86EMUL_CONTINUE)
879 return rc;
0f65dd70 880 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 881}
882
807941b1
TY		 883/*
884 * Fetch the next byte of the instruction being emulated which is pointed to
885 * by ctxt->_eip, then increment ctxt->_eip.
886 *
887 * Also prefetch the remaining bytes of the instruction without crossing page
888 * boundary if they are not in fetch_cache yet.
889 */
890static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 891{
9dac77fa 892 struct fetch_cache *fc = &ctxt->fetch;
62266869 893 int rc;
2fb53ad8 894 int size, cur_size;
62266869 895
807941b1 896 if (ctxt->_eip == fc->end) {
3d9b938e 897 unsigned long linear;
807941b1
TY		 898 struct segmented_address addr = { .seg = VCPU_SREG_CS,
899 .ea = ctxt->_eip };
2fb53ad8 900 cur_size = fc->end - fc->start;
807941b1
TY		 901 size = min(15UL - cur_size,
902 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 903 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 904 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 905 return rc;
ef5d75cc
TY		 906 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
907 size, &ctxt->exception);
7d88bb48 908 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 909 return rc;
2fb53ad8 910 fc->end += size;
62266869 911 }
807941b1
TY		 912 *dest = fc->data[ctxt->_eip - fc->start];
913 ctxt->_eip++;
3e2815e9 914 return X86EMUL_CONTINUE;
62266869
AK		 915}
916
917static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 918 void *dest, unsigned size)
62266869 919{
3e2815e9 920 int rc;
62266869 921
eb3c79e6 922 /* x86 instructions are limited to 15 bytes. */
7d88bb48 923 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 924 return X86EMUL_UNHANDLEABLE;
62266869 925 while (size--) {
807941b1 926 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 927 if (rc != X86EMUL_CONTINUE)
62266869
AK		 928 return rc;
929 }
3e2815e9 930 return X86EMUL_CONTINUE;
62266869
AK		 931}
932
67cbc90d 933/* Fetch next part of the instruction being emulated. */
e85a1085 934#define insn_fetch(_type, _ctxt) \
67cbc90d 935({ unsigned long _x; \
e85a1085 936 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 937 if (rc != X86EMUL_CONTINUE) \
938 goto done; \
67cbc90d
TY		 939 (_type)_x; \
940})
941
807941b1
TY		 942#define insn_fetch_arr(_arr, _size, _ctxt) \
943({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 944 if (rc != X86EMUL_CONTINUE) \
945 goto done; \
67cbc90d
TY		 946})
947
1e3c5cb0
RR		 948/*
949 * Given the 'reg' portion of a ModRM byte, and a register block, return a
950 * pointer into the block that addresses the relevant register.
951 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
952 */
dd856efa 953static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 954 int highbyte_regs)
6aa8b732
AK		 955{
956 void *p;
957
6aa8b732 958 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 959 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
960 else
961 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 962 return p;
963}
964
965static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 966 struct segmented_address addr,
6aa8b732
AK		 967 u16 *size, unsigned long *address, int op_bytes)
968{
969 int rc;
970
971 if (op_bytes == 2)
972 op_bytes = 3;
973 *address = 0;
3ca3ac4d 974 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 975 if (rc != X86EMUL_CONTINUE)
6aa8b732 976 return rc;
30b31ab6 977 addr.ea += 2;
3ca3ac4d 978 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 979 return rc;
980}
981
34b77652
AK		 982FASTOP2(add);
983FASTOP2(or);
984FASTOP2(adc);
985FASTOP2(sbb);
986FASTOP2(and);
987FASTOP2(sub);
988FASTOP2(xor);
989FASTOP2(cmp);
990FASTOP2(test);
991
992FASTOP3WCL(shld);
993FASTOP3WCL(shrd);
994
995FASTOP2W(imul);
996
997FASTOP1(not);
998FASTOP1(neg);
999FASTOP1(inc);
1000FASTOP1(dec);
1001
1002FASTOP2CL(rol);
1003FASTOP2CL(ror);
1004FASTOP2CL(rcl);
1005FASTOP2CL(rcr);
1006FASTOP2CL(shl);
1007FASTOP2CL(shr);
1008FASTOP2CL(sar);
1009
1010FASTOP2W(bsf);
1011FASTOP2W(bsr);
1012FASTOP2W(bt);
1013FASTOP2W(bts);
1014FASTOP2W(btr);
1015FASTOP2W(btc);
1016
9ae9feba 1017static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1018{
9ae9feba
AK		 1019 u8 rc;
1020 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1021
9ae9feba 1022 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1023 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1024 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1025 return rc;
bbe9abbd
NK		 1026}
1027
91ff3cb4
AK		 1028static void fetch_register_operand(struct operand *op)
1029{
1030 switch (op->bytes) {
1031 case 1:
1032 op->val = *(u8 *)op->addr.reg;
1033 break;
1034 case 2:
1035 op->val = *(u16 *)op->addr.reg;
1036 break;
1037 case 4:
1038 op->val = *(u32 *)op->addr.reg;
1039 break;
1040 case 8:
1041 op->val = *(u64 *)op->addr.reg;
1042 break;
1043 }
1044}
1045
1253791d
AK		 1046static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1047{
1048 ctxt->ops->get_fpu(ctxt);
1049 switch (reg) {
89a87c67
MK		 1050 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1051 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1052 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1053 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1054 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1055 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1056 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1057 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1058#ifdef CONFIG_X86_64
89a87c67
MK		 1059 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1060 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1061 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1062 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1063 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1064 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1065 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1066 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1067#endif
1068 default: BUG();
1069 }
1070 ctxt->ops->put_fpu(ctxt);
1071}
1072
1073static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1074 int reg)
1075{
1076 ctxt->ops->get_fpu(ctxt);
1077 switch (reg) {
89a87c67
MK		 1078 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1079 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1080 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1081 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1082 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1083 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1084 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1085 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1086#ifdef CONFIG_X86_64
89a87c67
MK		 1087 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1088 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1089 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1090 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1091 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1092 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1093 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1094 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1095#endif
1096 default: BUG();
1097 }
1098 ctxt->ops->put_fpu(ctxt);
1099}
1100
cbe2c9d3
AK		 1101static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1102{
1103 ctxt->ops->get_fpu(ctxt);
1104 switch (reg) {
1105 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1106 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1107 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1108 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1109 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1110 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1111 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1112 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1113 default: BUG();
1114 }
1115 ctxt->ops->put_fpu(ctxt);
1116}
1117
1118static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1119{
1120 ctxt->ops->get_fpu(ctxt);
1121 switch (reg) {
1122 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1123 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1124 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1125 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1126 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1127 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1128 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1129 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1130 default: BUG();
1131 }
1132 ctxt->ops->put_fpu(ctxt);
1133}
1134
045a282c
GN		 1135static int em_fninit(struct x86_emulate_ctxt *ctxt)
1136{
1137 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1138 return emulate_nm(ctxt);
1139
1140 ctxt->ops->get_fpu(ctxt);
1141 asm volatile("fninit");
1142 ctxt->ops->put_fpu(ctxt);
1143 return X86EMUL_CONTINUE;
1144}
1145
1146static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1147{
1148 u16 fcw;
1149
1150 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1151 return emulate_nm(ctxt);
1152
1153 ctxt->ops->get_fpu(ctxt);
1154 asm volatile("fnstcw %0": "+m"(fcw));
1155 ctxt->ops->put_fpu(ctxt);
1156
1157 /* force 2 byte destination */
1158 ctxt->dst.bytes = 2;
1159 ctxt->dst.val = fcw;
1160
1161 return X86EMUL_CONTINUE;
1162}
1163
1164static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1165{
1166 u16 fsw;
1167
1168 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1169 return emulate_nm(ctxt);
1170
1171 ctxt->ops->get_fpu(ctxt);
1172 asm volatile("fnstsw %0": "+m"(fsw));
1173 ctxt->ops->put_fpu(ctxt);
1174
1175 /* force 2 byte destination */
1176 ctxt->dst.bytes = 2;
1177 ctxt->dst.val = fsw;
1178
1179 return X86EMUL_CONTINUE;
1180}
1181
1253791d 1182static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1183 struct operand *op)
3c118e24 1184{
9dac77fa
AK		 1185 unsigned reg = ctxt->modrm_reg;
1186 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1187
9dac77fa
AK		 1188 if (!(ctxt->d & ModRM))
1189 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1190
9dac77fa 1191 if (ctxt->d & Sse) {
1253791d
AK		 1192 op->type = OP_XMM;
1193 op->bytes = 16;
1194 op->addr.xmm = reg;
1195 read_sse_reg(ctxt, &op->vec_val, reg);
1196 return;
1197 }
cbe2c9d3
AK		 1198 if (ctxt->d & Mmx) {
1199 reg &= 7;
1200 op->type = OP_MM;
1201 op->bytes = 8;
1202 op->addr.mm = reg;
1203 return;
1204 }
1253791d 1205
3c118e24 1206 op->type = OP_REG;
2adb5ad9 1207 if (ctxt->d & ByteOp) {
dd856efa 1208 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1209 op->bytes = 1;
1210 } else {
dd856efa 1211 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1212 op->bytes = ctxt->op_bytes;
3c118e24 1213 }
91ff3cb4 1214 fetch_register_operand(op);
3c118e24
AK		 1215 op->orig_val = op->val;
1216}
1217
a6e3407b
AK		 1218static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1219{
1220 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1221 ctxt->modrm_seg = VCPU_SREG_SS;
1222}
1223
1c73ef66 1224static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1225 struct operand *op)
1c73ef66 1226{
1c73ef66 1227 u8 sib;
f5b4edcd 1228 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1229 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1230 ulong modrm_ea = 0;
1c73ef66 1231
9dac77fa
AK		 1232 if (ctxt->rex_prefix) {
1233 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1234 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1235 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1236 }
1237
9dac77fa
AK		 1238 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1239 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1240 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1241 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1242
9dac77fa 1243 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1244 op->type = OP_REG;
9dac77fa 1245 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1246 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1247 if (ctxt->d & Sse) {
1253791d
AK		 1248 op->type = OP_XMM;
1249 op->bytes = 16;
9dac77fa
AK		 1250 op->addr.xmm = ctxt->modrm_rm;
1251 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1252 return rc;
1253 }
cbe2c9d3
AK		 1254 if (ctxt->d & Mmx) {
1255 op->type = OP_MM;
1256 op->bytes = 8;
1257 op->addr.xmm = ctxt->modrm_rm & 7;
1258 return rc;
1259 }
2dbd0dd7 1260 fetch_register_operand(op);
1c73ef66
AK		 1261 return rc;
1262 }
1263
2dbd0dd7
AK		 1264 op->type = OP_MEM;
1265
9dac77fa 1266 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1267 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1268 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1269 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1270 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1271
1272 /* 16-bit ModR/M decode. */
9dac77fa 1273 switch (ctxt->modrm_mod) {
1c73ef66 1274 case 0:
9dac77fa 1275 if (ctxt->modrm_rm == 6)
e85a1085 1276 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1277 break;
1278 case 1:
e85a1085 1279 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1280 break;
1281 case 2:
e85a1085 1282 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1283 break;
1284 }
9dac77fa 1285 switch (ctxt->modrm_rm) {
1c73ef66 1286 case 0:
2dbd0dd7 1287 modrm_ea += bx + si;
1c73ef66
AK		 1288 break;
1289 case 1:
2dbd0dd7 1290 modrm_ea += bx + di;
1c73ef66
AK		 1291 break;
1292 case 2:
2dbd0dd7 1293 modrm_ea += bp + si;
1c73ef66
AK		 1294 break;
1295 case 3:
2dbd0dd7 1296 modrm_ea += bp + di;
1c73ef66
AK		 1297 break;
1298 case 4:
2dbd0dd7 1299 modrm_ea += si;
1c73ef66
AK		 1300 break;
1301 case 5:
2dbd0dd7 1302 modrm_ea += di;
1c73ef66
AK		 1303 break;
1304 case 6:
9dac77fa 1305 if (ctxt->modrm_mod != 0)
2dbd0dd7 1306 modrm_ea += bp;
1c73ef66
AK		 1307 break;
1308 case 7:
2dbd0dd7 1309 modrm_ea += bx;
1c73ef66
AK		 1310 break;
1311 }
9dac77fa
AK		 1312 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1313 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1314 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1315 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1316 } else {
1317 /* 32/64-bit ModR/M decode. */
9dac77fa 1318 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1319 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1320 index_reg |= (sib >> 3) & 7;
1321 base_reg |= sib & 7;
1322 scale = sib >> 6;
1323
9dac77fa 1324 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1325 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1326 else {
dd856efa 1327 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1328 adjust_modrm_seg(ctxt, base_reg);
1329 }
dc71d0f1 1330 if (index_reg != 4)
dd856efa 1331 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1332 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1333 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1334 ctxt->rip_relative = 1;
a6e3407b
AK		 1335 } else {
1336 base_reg = ctxt->modrm_rm;
dd856efa 1337 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1338 adjust_modrm_seg(ctxt, base_reg);
1339 }
9dac77fa 1340 switch (ctxt->modrm_mod) {
1c73ef66 1341 case 0:
9dac77fa 1342 if (ctxt->modrm_rm == 5)
e85a1085 1343 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1344 break;
1345 case 1:
e85a1085 1346 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1347 break;
1348 case 2:
e85a1085 1349 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1350 break;
1351 }
1352 }
90de84f5 1353 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1354done:
1355 return rc;
1356}
1357
1358static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1359 struct operand *op)
1c73ef66 1360{
3e2815e9 1361 int rc = X86EMUL_CONTINUE;
1c73ef66 1362
2dbd0dd7 1363 op->type = OP_MEM;
9dac77fa 1364 switch (ctxt->ad_bytes) {
1c73ef66 1365 case 2:
e85a1085 1366 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1367 break;
1368 case 4:
e85a1085 1369 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1370 break;
1371 case 8:
e85a1085 1372 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1373 break;
1374 }
1375done:
1376 return rc;
1377}
1378
9dac77fa 1379static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1380{
7129eeca 1381 long sv = 0, mask;
35c843c4 1382
9dac77fa
AK		 1383 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1384 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1385
9dac77fa
AK		 1386 if (ctxt->src.bytes == 2)
1387 sv = (s16)ctxt->src.val & (s16)mask;
1388 else if (ctxt->src.bytes == 4)
1389 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1390
9dac77fa 1391 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1392 }
ba7ff2b7
WY		 1393
1394 /* only subword offset */
9dac77fa 1395 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1396}
1397
dde7e6d1 1398static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1399 unsigned long addr, void *dest, unsigned size)
6aa8b732 1400{
dde7e6d1 1401 int rc;
9dac77fa 1402 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1403
f23b070e
XG		 1404 if (mc->pos < mc->end)
1405 goto read_cached;
6aa8b732 1406
f23b070e
XG		 1407 WARN_ON((mc->end + size) >= sizeof(mc->data));
1408
1409 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1410 &ctxt->exception);
1411 if (rc != X86EMUL_CONTINUE)
1412 return rc;
1413
1414 mc->end += size;
1415
1416read_cached:
1417 memcpy(dest, mc->data + mc->pos, size);
1418 mc->pos += size;
dde7e6d1
AK		 1419 return X86EMUL_CONTINUE;
1420}
6aa8b732 1421
3ca3ac4d
AK		 1422static int segmented_read(struct x86_emulate_ctxt *ctxt,
1423 struct segmented_address addr,
1424 void *data,
1425 unsigned size)
1426{
9fa088f4
AK		 1427 int rc;
1428 ulong linear;
1429
83b8795a 1430 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1431 if (rc != X86EMUL_CONTINUE)
1432 return rc;
7b105ca2 1433 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1434}
1435
1436static int segmented_write(struct x86_emulate_ctxt *ctxt,
1437 struct segmented_address addr,
1438 const void *data,
1439 unsigned size)
1440{
9fa088f4
AK		 1441 int rc;
1442 ulong linear;
1443
83b8795a 1444 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1445 if (rc != X86EMUL_CONTINUE)
1446 return rc;
0f65dd70
AK		 1447 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1448 &ctxt->exception);
3ca3ac4d
AK		 1449}
1450
1451static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1452 struct segmented_address addr,
1453 const void *orig_data, const void *data,
1454 unsigned size)
1455{
9fa088f4
AK		 1456 int rc;
1457 ulong linear;
1458
83b8795a 1459 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1460 if (rc != X86EMUL_CONTINUE)
1461 return rc;
0f65dd70
AK		 1462 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1463 size, &ctxt->exception);
3ca3ac4d
AK		 1464}
1465
dde7e6d1 1466static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1467 unsigned int size, unsigned short port,
1468 void *dest)
1469{
9dac77fa 1470 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1471
dde7e6d1 1472 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1473 unsigned int in_page, n;
9dac77fa 1474 unsigned int count = ctxt->rep_prefix ?
dd856efa 1475 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1476 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1477 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1478 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1479 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1480 count);
1481 if (n == 0)
1482 n = 1;
1483 rc->pos = rc->end = 0;
7b105ca2 1484 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1485 return 0;
1486 rc->end = n * size;
6aa8b732
AK		 1487 }
1488
b3356bf0
GN		 1489 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1490 ctxt->dst.data = rc->data + rc->pos;
1491 ctxt->dst.type = OP_MEM_STR;
1492 ctxt->dst.count = (rc->end - rc->pos) / size;
1493 rc->pos = rc->end;
1494 } else {
1495 memcpy(dest, rc->data + rc->pos, size);
1496 rc->pos += size;
1497 }
dde7e6d1
AK		 1498 return 1;
1499}
6aa8b732 1500
7f3d35fd
KW		 1501static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1502 u16 index, struct desc_struct *desc)
1503{
1504 struct desc_ptr dt;
1505 ulong addr;
1506
1507 ctxt->ops->get_idt(ctxt, &dt);
1508
1509 if (dt.size < index * 8 + 7)
1510 return emulate_gp(ctxt, index << 3 | 0x2);
1511
1512 addr = dt.address + index * 8;
1513 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1514 &ctxt->exception);
1515}
1516
dde7e6d1 1517static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1518 u16 selector, struct desc_ptr *dt)
1519{
0225fb50 1520 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1521
dde7e6d1
AK		 1522 if (selector & 1 << 2) {
1523 struct desc_struct desc;
1aa36616
AK		 1524 u16 sel;
1525
dde7e6d1 1526 memset (dt, 0, sizeof *dt);
1aa36616 1527 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1528 return;
e09d082c 1529
dde7e6d1
AK		 1530 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1531 dt->address = get_desc_base(&desc);
1532 } else
4bff1e86 1533 ops->get_gdt(ctxt, dt);
dde7e6d1 1534}
120df890 1535
dde7e6d1
AK		 1536/* allowed just for 8 bytes segments */
1537static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1538 u16 selector, struct desc_struct *desc,
1539 ulong *desc_addr_p)
dde7e6d1
AK		 1540{
1541 struct desc_ptr dt;
1542 u16 index = selector >> 3;
dde7e6d1 1543 ulong addr;
120df890 1544
7b105ca2 1545 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1546
35d3d4a1
AK		 1547 if (dt.size < index * 8 + 7)
1548 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1549
e919464b 1550 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1551 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1552 &ctxt->exception);
dde7e6d1 1553}
ef65c889 1554
dde7e6d1
AK		 1555/* allowed just for 8 bytes segments */
1556static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1557 u16 selector, struct desc_struct *desc)
1558{
1559 struct desc_ptr dt;
1560 u16 index = selector >> 3;
dde7e6d1 1561 ulong addr;
6aa8b732 1562
7b105ca2 1563 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1564
35d3d4a1
AK		 1565 if (dt.size < index * 8 + 7)
1566 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1567
dde7e6d1 1568 addr = dt.address + index * 8;
7b105ca2
TY		 1569 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1570 &ctxt->exception);
dde7e6d1 1571}
c7e75a3d 1572
5601d05b 1573/* Does not support long mode */
dde7e6d1 1574static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1575 u16 selector, int seg)
1576{
869be99c 1577 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1578 u8 dpl, rpl, cpl;
1579 unsigned err_vec = GP_VECTOR;
1580 u32 err_code = 0;
1581 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1582 ulong desc_addr;
dde7e6d1 1583 int ret;
03ebebeb 1584 u16 dummy;
69f55cb1 1585
dde7e6d1 1586 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1587
f8da94e9
KW		 1588 if (ctxt->mode == X86EMUL_MODE_REAL) {
1589 /* set real mode segment descriptor (keep limit etc. for
1590 * unreal mode) */
03ebebeb 1591 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1592 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1593 goto load;
f8da94e9
KW		 1594 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1595 /* VM86 needs a clean new segment descriptor */
1596 set_desc_base(&seg_desc, selector << 4);
1597 set_desc_limit(&seg_desc, 0xffff);
1598 seg_desc.type = 3;
1599 seg_desc.p = 1;
1600 seg_desc.s = 1;
1601 seg_desc.dpl = 3;
1602 goto load;
dde7e6d1
AK		 1603 }
1604
79d5b4c3
AK		 1605 rpl = selector & 3;
1606 cpl = ctxt->ops->cpl(ctxt);
1607
1608 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1609 if ((seg == VCPU_SREG_CS
1610 || (seg == VCPU_SREG_SS
1611 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1612 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1613 && null_selector)
1614 goto exception;
1615
1616 /* TR should be in GDT only */
1617 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1618 goto exception;
1619
1620 if (null_selector) /* for NULL selector skip all following checks */
1621 goto load;
1622
e919464b 1623 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1624 if (ret != X86EMUL_CONTINUE)
1625 return ret;
1626
1627 err_code = selector & 0xfffc;
1628 err_vec = GP_VECTOR;
1629
fc058680 1630 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1631 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1632 goto exception;
1633
1634 if (!seg_desc.p) {
1635 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1636 goto exception;
1637 }
1638
dde7e6d1 1639 dpl = seg_desc.dpl;
dde7e6d1
AK		 1640
1641 switch (seg) {
1642 case VCPU_SREG_SS:
1643 /*
1644 * segment is not a writable data segment or segment
1645 * selector's RPL != CPL or segment selector's RPL != CPL
1646 */
1647 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1648 goto exception;
6aa8b732 1649 break;
dde7e6d1
AK		 1650 case VCPU_SREG_CS:
1651 if (!(seg_desc.type & 8))
1652 goto exception;
1653
1654 if (seg_desc.type & 4) {
1655 /* conforming */
1656 if (dpl > cpl)
1657 goto exception;
1658 } else {
1659 /* nonconforming */
1660 if (rpl > cpl || dpl != cpl)
1661 goto exception;
1662 }
1663 /* CS(RPL) <- CPL */
1664 selector = (selector & 0xfffc) | cpl;
6aa8b732 1665 break;
dde7e6d1
AK		 1666 case VCPU_SREG_TR:
1667 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1668 goto exception;
869be99c
AK		 1669 old_desc = seg_desc;
1670 seg_desc.type |= 2; /* busy */
1671 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1672 sizeof(seg_desc), &ctxt->exception);
1673 if (ret != X86EMUL_CONTINUE)
1674 return ret;
dde7e6d1
AK		 1675 break;
1676 case VCPU_SREG_LDTR:
1677 if (seg_desc.s || seg_desc.type != 2)
1678 goto exception;
1679 break;
1680 default: /* DS, ES, FS, or GS */
4e62417b 1681 /*
dde7e6d1
AK		 1682 * segment is not a data or readable code segment or
1683 * ((segment is a data or nonconforming code segment)
1684 * and (both RPL and CPL > DPL))
4e62417b 1685 */
dde7e6d1
AK		 1686 if ((seg_desc.type & 0xa) == 0x8 ||
1687 (((seg_desc.type & 0xc) != 0xc) &&
1688 (rpl > dpl && cpl > dpl)))
1689 goto exception;
6aa8b732 1690 break;
dde7e6d1
AK		 1691 }
1692
1693 if (seg_desc.s) {
1694 /* mark segment as accessed */
1695 seg_desc.type |= 1;
7b105ca2 1696 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1697 if (ret != X86EMUL_CONTINUE)
1698 return ret;
1699 }
1700load:
7b105ca2 1701 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1702 return X86EMUL_CONTINUE;
1703exception:
1704 emulate_exception(ctxt, err_vec, err_code, true);
1705 return X86EMUL_PROPAGATE_FAULT;
1706}
1707
31be40b3
WY		 1708static void write_register_operand(struct operand *op)
1709{
1710 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1711 switch (op->bytes) {
1712 case 1:
1713 *(u8 *)op->addr.reg = (u8)op->val;
1714 break;
1715 case 2:
1716 *(u16 *)op->addr.reg = (u16)op->val;
1717 break;
1718 case 4:
1719 *op->addr.reg = (u32)op->val;
1720 break; /* 64b: zero-extend */
1721 case 8:
1722 *op->addr.reg = op->val;
1723 break;
1724 }
1725}
1726
fb32b1ed 1727static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1728{
1729 int rc;
dde7e6d1 1730
fb32b1ed 1731 switch (op->type) {
dde7e6d1 1732 case OP_REG:
fb32b1ed 1733 write_register_operand(op);
6aa8b732 1734 break;
dde7e6d1 1735 case OP_MEM:
9dac77fa 1736 if (ctxt->lock_prefix)
3ca3ac4d 1737 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1738 op->addr.mem,
1739 &op->orig_val,
1740 &op->val,
1741 op->bytes);
341de7e3 1742 else
3ca3ac4d 1743 rc = segmented_write(ctxt,
fb32b1ed
AK		 1744 op->addr.mem,
1745 &op->val,
1746 op->bytes);
dde7e6d1
AK		 1747 if (rc != X86EMUL_CONTINUE)
1748 return rc;
a682e354 1749 break;
b3356bf0
GN		 1750 case OP_MEM_STR:
1751 rc = segmented_write(ctxt,
fb32b1ed
AK		 1752 op->addr.mem,
1753 op->data,
1754 op->bytes * op->count);
b3356bf0
GN		 1755 if (rc != X86EMUL_CONTINUE)
1756 return rc;
1757 break;
1253791d 1758 case OP_XMM:
fb32b1ed 1759 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1760 break;
cbe2c9d3 1761 case OP_MM:
fb32b1ed 1762 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1763 break;
dde7e6d1
AK		 1764 case OP_NONE:
1765 /* no writeback */
414e6277 1766 break;
dde7e6d1 1767 default:
414e6277 1768 break;
6aa8b732 1769 }
dde7e6d1
AK		 1770 return X86EMUL_CONTINUE;
1771}
6aa8b732 1772
51ddff50 1773static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1774{
4179bb02 1775 struct segmented_address addr;
0dc8d10f 1776
5ad105e5 1777 rsp_increment(ctxt, -bytes);
dd856efa 1778 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1779 addr.seg = VCPU_SREG_SS;
1780
51ddff50
AK		 1781 return segmented_write(ctxt, addr, data, bytes);
1782}
1783
1784static int em_push(struct x86_emulate_ctxt *ctxt)
1785{
4179bb02 1786 /* Disable writeback. */
9dac77fa 1787 ctxt->dst.type = OP_NONE;
51ddff50 1788 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1789}
69f55cb1 1790
dde7e6d1 1791static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1792 void *dest, int len)
1793{
dde7e6d1 1794 int rc;
90de84f5 1795 struct segmented_address addr;
8b4caf66 1796
dd856efa 1797 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1798 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1799 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1800 if (rc != X86EMUL_CONTINUE)
1801 return rc;
1802
5ad105e5 1803 rsp_increment(ctxt, len);
dde7e6d1 1804 return rc;
8b4caf66
LV		 1805}
1806
c54fe504
TY		 1807static int em_pop(struct x86_emulate_ctxt *ctxt)
1808{
9dac77fa 1809 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1810}
1811
dde7e6d1 1812static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1813 void *dest, int len)
9de41573
GN		 1814{
1815 int rc;
dde7e6d1
AK		 1816 unsigned long val, change_mask;
1817 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1818 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1819
3b9be3bf 1820 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1821 if (rc != X86EMUL_CONTINUE)
1822 return rc;
9de41573 1823
dde7e6d1
AK		 1824 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1825 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1826
dde7e6d1
AK		 1827 switch(ctxt->mode) {
1828 case X86EMUL_MODE_PROT64:
1829 case X86EMUL_MODE_PROT32:
1830 case X86EMUL_MODE_PROT16:
1831 if (cpl == 0)
1832 change_mask |= EFLG_IOPL;
1833 if (cpl <= iopl)
1834 change_mask |= EFLG_IF;
1835 break;
1836 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1837 if (iopl < 3)
1838 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1839 change_mask |= EFLG_IF;
1840 break;
1841 default: /* real mode */
1842 change_mask |= (EFLG_IOPL | EFLG_IF);
1843 break;
9de41573 1844 }
dde7e6d1
AK		 1845
1846 *(unsigned long *)dest =
1847 (ctxt->eflags & ~change_mask) | (val & change_mask);
1848
1849 return rc;
9de41573
GN		 1850}
1851
62aaa2f0
TY		 1852static int em_popf(struct x86_emulate_ctxt *ctxt)
1853{
9dac77fa
AK		 1854 ctxt->dst.type = OP_REG;
1855 ctxt->dst.addr.reg = &ctxt->eflags;
1856 ctxt->dst.bytes = ctxt->op_bytes;
1857 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1858}
1859
612e89f0
AK		 1860static int em_enter(struct x86_emulate_ctxt *ctxt)
1861{
1862 int rc;
1863 unsigned frame_size = ctxt->src.val;
1864 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1865 ulong rbp;
612e89f0
AK		 1866
1867 if (nesting_level)
1868 return X86EMUL_UNHANDLEABLE;
1869
dd856efa
AK		 1870 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1871 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1872 if (rc != X86EMUL_CONTINUE)
1873 return rc;
dd856efa 1874 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1875 stack_mask(ctxt));
dd856efa
AK		 1876 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1877 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1878 stack_mask(ctxt));
1879 return X86EMUL_CONTINUE;
1880}
1881
f47cfa31
AK		 1882static int em_leave(struct x86_emulate_ctxt *ctxt)
1883{
dd856efa 1884 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1885 stack_mask(ctxt));
dd856efa 1886 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1887}
1888
1cd196ea 1889static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1890{
1cd196ea
AK		 1891 int seg = ctxt->src2.val;
1892
9dac77fa 1893 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1894
4487b3b4 1895 return em_push(ctxt);
7b262e90
GN		 1896}
1897
1cd196ea 1898static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1899{
1cd196ea 1900 int seg = ctxt->src2.val;
dde7e6d1
AK		 1901 unsigned long selector;
1902 int rc;
38ba30ba 1903
9dac77fa 1904 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1905 if (rc != X86EMUL_CONTINUE)
1906 return rc;
1907
7b105ca2 1908 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1909 return rc;
38ba30ba
GN		 1910}
1911
b96a7fad 1912static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1913{
dd856efa 1914 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1915 int rc = X86EMUL_CONTINUE;
1916 int reg = VCPU_REGS_RAX;
38ba30ba 1917
dde7e6d1
AK		 1918 while (reg <= VCPU_REGS_RDI) {
1919 (reg == VCPU_REGS_RSP) ?
dd856efa 1920 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1921
4487b3b4 1922 rc = em_push(ctxt);
dde7e6d1
AK		 1923 if (rc != X86EMUL_CONTINUE)
1924 return rc;
38ba30ba 1925
dde7e6d1 1926 ++reg;
38ba30ba 1927 }
38ba30ba 1928
dde7e6d1 1929 return rc;
38ba30ba
GN		 1930}
1931
62aaa2f0
TY		 1932static int em_pushf(struct x86_emulate_ctxt *ctxt)
1933{
9dac77fa 1934 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1935 return em_push(ctxt);
1936}
1937
b96a7fad 1938static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1939{
dde7e6d1
AK		 1940 int rc = X86EMUL_CONTINUE;
1941 int reg = VCPU_REGS_RDI;
38ba30ba 1942
dde7e6d1
AK		 1943 while (reg >= VCPU_REGS_RAX) {
1944 if (reg == VCPU_REGS_RSP) {
5ad105e5 1945 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1946 --reg;
1947 }
38ba30ba 1948
dd856efa 1949 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1950 if (rc != X86EMUL_CONTINUE)
1951 break;
1952 --reg;
38ba30ba 1953 }
dde7e6d1 1954 return rc;
38ba30ba
GN		 1955}
1956
dd856efa 1957static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1958{
0225fb50 1959 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1960 int rc;
6e154e56
MG		 1961 struct desc_ptr dt;
1962 gva_t cs_addr;
1963 gva_t eip_addr;
1964 u16 cs, eip;
6e154e56
MG		 1965
1966 /* TODO: Add limit checks */
9dac77fa 1967 ctxt->src.val = ctxt->eflags;
4487b3b4 1968 rc = em_push(ctxt);
5c56e1cf
AK		 1969 if (rc != X86EMUL_CONTINUE)
1970 return rc;
6e154e56
MG		 1971
1972 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1973
9dac77fa 1974 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1975 rc = em_push(ctxt);
5c56e1cf
AK		 1976 if (rc != X86EMUL_CONTINUE)
1977 return rc;
6e154e56 1978
9dac77fa 1979 ctxt->src.val = ctxt->_eip;
4487b3b4 1980 rc = em_push(ctxt);
5c56e1cf
AK		 1981 if (rc != X86EMUL_CONTINUE)
1982 return rc;
1983
4bff1e86 1984 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1985
1986 eip_addr = dt.address + (irq << 2);
1987 cs_addr = dt.address + (irq << 2) + 2;
1988
0f65dd70 1989 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1990 if (rc != X86EMUL_CONTINUE)
1991 return rc;
1992
0f65dd70 1993 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1994 if (rc != X86EMUL_CONTINUE)
1995 return rc;
1996
7b105ca2 1997 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1998 if (rc != X86EMUL_CONTINUE)
1999 return rc;
2000
9dac77fa 2001 ctxt->_eip = eip;
6e154e56
MG		 2002
2003 return rc;
2004}
2005
dd856efa
AK		 2006int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2007{
2008 int rc;
2009
2010 invalidate_registers(ctxt);
2011 rc = __emulate_int_real(ctxt, irq);
2012 if (rc == X86EMUL_CONTINUE)
2013 writeback_registers(ctxt);
2014 return rc;
2015}
2016
7b105ca2 2017static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2018{
2019 switch(ctxt->mode) {
2020 case X86EMUL_MODE_REAL:
dd856efa 2021 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2022 case X86EMUL_MODE_VM86:
2023 case X86EMUL_MODE_PROT16:
2024 case X86EMUL_MODE_PROT32:
2025 case X86EMUL_MODE_PROT64:
2026 default:
2027 /* Protected mode interrupts unimplemented yet */
2028 return X86EMUL_UNHANDLEABLE;
2029 }
2030}
2031
7b105ca2 2032static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2033{
dde7e6d1
AK		 2034 int rc = X86EMUL_CONTINUE;
2035 unsigned long temp_eip = 0;
2036 unsigned long temp_eflags = 0;
2037 unsigned long cs = 0;
2038 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2039 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2040 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2041 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2042
dde7e6d1 2043 /* TODO: Add stack limit check */
38ba30ba 2044
9dac77fa 2045 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2046
dde7e6d1
AK		 2047 if (rc != X86EMUL_CONTINUE)
2048 return rc;
38ba30ba 2049
35d3d4a1
AK		 2050 if (temp_eip & ~0xffff)
2051 return emulate_gp(ctxt, 0);
38ba30ba 2052
9dac77fa 2053 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2054
dde7e6d1
AK		 2055 if (rc != X86EMUL_CONTINUE)
2056 return rc;
38ba30ba 2057
9dac77fa 2058 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2059
dde7e6d1
AK		 2060 if (rc != X86EMUL_CONTINUE)
2061 return rc;
38ba30ba 2062
7b105ca2 2063 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2064
dde7e6d1
AK		 2065 if (rc != X86EMUL_CONTINUE)
2066 return rc;
38ba30ba 2067
9dac77fa 2068 ctxt->_eip = temp_eip;
38ba30ba 2069
38ba30ba 2070
9dac77fa 2071 if (ctxt->op_bytes == 4)
dde7e6d1 2072 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2073 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2074 ctxt->eflags &= ~0xffff;
2075 ctxt->eflags |= temp_eflags;
38ba30ba 2076 }
dde7e6d1
AK		 2077
2078 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2079 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2080
2081 return rc;
38ba30ba
GN		 2082}
2083
e01991e7 2084static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2085{
dde7e6d1
AK		 2086 switch(ctxt->mode) {
2087 case X86EMUL_MODE_REAL:
7b105ca2 2088 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2089 case X86EMUL_MODE_VM86:
2090 case X86EMUL_MODE_PROT16:
2091 case X86EMUL_MODE_PROT32:
2092 case X86EMUL_MODE_PROT64:
c37eda13 2093 default:
dde7e6d1
AK		 2094 /* iret from protected mode unimplemented yet */
2095 return X86EMUL_UNHANDLEABLE;
c37eda13 2096 }
c37eda13
WY		 2097}
2098
d2f62766
TY		 2099static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2100{
d2f62766
TY		 2101 int rc;
2102 unsigned short sel;
2103
9dac77fa 2104 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2105
7b105ca2 2106 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2107 if (rc != X86EMUL_CONTINUE)
2108 return rc;
2109
9dac77fa
AK		 2110 ctxt->_eip = 0;
2111 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2112 return X86EMUL_CONTINUE;
2113}
2114
3329ece1
AK		 2115static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2116{
2117 u8 ex = 0;
2118
2119 emulate_1op_rax_rdx(ctxt, "mul", ex);
2120 return X86EMUL_CONTINUE;
2121}
2122
2123static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2124{
2125 u8 ex = 0;
2126
2127 emulate_1op_rax_rdx(ctxt, "imul", ex);
2128 return X86EMUL_CONTINUE;
2129}
2130
2131static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2132{
34d1f490 2133 u8 de = 0;
8cdbd2c9 2134
3329ece1
AK		 2135 emulate_1op_rax_rdx(ctxt, "div", de);
2136 if (de)
2137 return emulate_de(ctxt);
2138 return X86EMUL_CONTINUE;
2139}
2140
2141static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2142{
2143 u8 de = 0;
2144
2145 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2146 if (de)
2147 return emulate_de(ctxt);
8c5eee30 2148 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2149}
2150
51187683 2151static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2152{
4179bb02 2153 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2154
9dac77fa 2155 switch (ctxt->modrm_reg) {
d19292e4
MG		 2156 case 2: /* call near abs */ {
2157 long int old_eip;
9dac77fa
AK		 2158 old_eip = ctxt->_eip;
2159 ctxt->_eip = ctxt->src.val;
2160 ctxt->src.val = old_eip;
4487b3b4 2161 rc = em_push(ctxt);
d19292e4
MG		 2162 break;
2163 }
8cdbd2c9 2164 case 4: /* jmp abs */
9dac77fa 2165 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2166 break;
d2f62766
TY		 2167 case 5: /* jmp far */
2168 rc = em_jmp_far(ctxt);
2169 break;
8cdbd2c9 2170 case 6: /* push */
4487b3b4 2171 rc = em_push(ctxt);
8cdbd2c9 2172 break;
8cdbd2c9 2173 }
4179bb02 2174 return rc;
8cdbd2c9
LV		 2175}
2176
e0dac408 2177static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2178{
9dac77fa 2179 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2180
dd856efa
AK		 2181 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2182 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2183 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2184 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2185 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2186 } else {
dd856efa
AK		 2187 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2188 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2189
05f086f8 2190 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2191 }
1b30eaa8 2192 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2193}
2194
ebda02c2
TY		 2195static int em_ret(struct x86_emulate_ctxt *ctxt)
2196{
9dac77fa
AK		 2197 ctxt->dst.type = OP_REG;
2198 ctxt->dst.addr.reg = &ctxt->_eip;
2199 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2200 return em_pop(ctxt);
2201}
2202
e01991e7 2203static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2204{
a77ab5ea
AK		 2205 int rc;
2206 unsigned long cs;
2207
9dac77fa 2208 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2209 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2210 return rc;
9dac77fa
AK		 2211 if (ctxt->op_bytes == 4)
2212 ctxt->_eip = (u32)ctxt->_eip;
2213 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2214 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2215 return rc;
7b105ca2 2216 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2217 return rc;
2218}
2219
e940b5c2
TY		 2220static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2221{
2222 /* Save real source value, then compare EAX against destination. */
2223 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2224 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2225 fastop(ctxt, em_cmp);
e940b5c2
TY		 2226
2227 if (ctxt->eflags & EFLG_ZF) {
2228 /* Success: write back to memory. */
2229 ctxt->dst.val = ctxt->src.orig_val;
2230 } else {
2231 /* Failure: write the value we saw to EAX. */
2232 ctxt->dst.type = OP_REG;
dd856efa 2233 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2234 }
2235 return X86EMUL_CONTINUE;
2236}
2237
d4b4325f 2238static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2239{
d4b4325f 2240 int seg = ctxt->src2.val;
09b5f4d3
WY		 2241 unsigned short sel;
2242 int rc;
2243
9dac77fa 2244 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2245
7b105ca2 2246 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2247 if (rc != X86EMUL_CONTINUE)
2248 return rc;
2249
9dac77fa 2250 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2251 return rc;
2252}
2253
7b105ca2 2254static void
e66bb2cc 2255setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2256 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2257{
e66bb2cc 2258 cs->l = 0; /* will be adjusted later */
79168fd1 2259 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2260 cs->g = 1; /* 4kb granularity */
79168fd1 2261 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2262 cs->type = 0x0b; /* Read, Execute, Accessed */
2263 cs->s = 1;
2264 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2265 cs->p = 1;
2266 cs->d = 1;
99245b50 2267 cs->avl = 0;
e66bb2cc 2268
79168fd1
GN		 2269 set_desc_base(ss, 0); /* flat segment */
2270 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2271 ss->g = 1; /* 4kb granularity */
2272 ss->s = 1;
2273 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2274 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2275 ss->dpl = 0;
79168fd1 2276 ss->p = 1;
99245b50
GN		 2277 ss->l = 0;
2278 ss->avl = 0;
e66bb2cc
AP		 2279}
2280
1a18a69b
AK		 2281static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2282{
2283 u32 eax, ebx, ecx, edx;
2284
2285 eax = ecx = 0;
0017f93a
AK		 2286 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2287 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2288 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2289 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2290}
2291
c2226fc9
SB		 2292static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2293{
0225fb50 2294 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2295 u32 eax, ebx, ecx, edx;
2296
2297 /*
2298 * syscall should always be enabled in longmode - so only become
2299 * vendor specific (cpuid) if other modes are active...
2300 */
2301 if (ctxt->mode == X86EMUL_MODE_PROT64)
2302 return true;
2303
2304 eax = 0x00000000;
2305 ecx = 0x00000000;
0017f93a
AK		 2306 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2307 /*
2308 * Intel ("GenuineIntel")
2309 * remark: Intel CPUs only support "syscall" in 64bit
2310 * longmode. Also an 64bit guest with a
2311 * 32bit compat-app running will #UD !! While this
2312 * behaviour can be fixed (by emulating) into AMD
2313 * response - CPUs of AMD can't behave like Intel.
2314 */
2315 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2316 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2317 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2318 return false;
2319
2320 /* AMD ("AuthenticAMD") */
2321 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2322 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2323 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2324 return true;
2325
2326 /* AMD ("AMDisbetter!") */
2327 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2328 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2329 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2330 return true;
c2226fc9
SB		 2331
2332 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2333 return false;
2334}
2335
e01991e7 2336static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2337{
0225fb50 2338 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2339 struct desc_struct cs, ss;
e66bb2cc 2340 u64 msr_data;
79168fd1 2341 u16 cs_sel, ss_sel;
c2ad2bb3 2342 u64 efer = 0;
e66bb2cc
AP		 2343
2344 /* syscall is not available in real mode */
2e901c4c 2345 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2346 ctxt->mode == X86EMUL_MODE_VM86)
2347 return emulate_ud(ctxt);
e66bb2cc 2348
c2226fc9
SB		 2349 if (!(em_syscall_is_enabled(ctxt)))
2350 return emulate_ud(ctxt);
2351
c2ad2bb3 2352 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2353 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2354
c2226fc9
SB		 2355 if (!(efer & EFER_SCE))
2356 return emulate_ud(ctxt);
2357
717746e3 2358 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2359 msr_data >>= 32;
79168fd1
GN		 2360 cs_sel = (u16)(msr_data & 0xfffc);
2361 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2362
c2ad2bb3 2363 if (efer & EFER_LMA) {
79168fd1 2364 cs.d = 0;
e66bb2cc
AP		 2365 cs.l = 1;
2366 }
1aa36616
AK		 2367 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2368 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2369
dd856efa 2370 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2371 if (efer & EFER_LMA) {
e66bb2cc 2372#ifdef CONFIG_X86_64
dd856efa 2373 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2374
717746e3 2375 ops->get_msr(ctxt,
3fb1b5db
GN		 2376 ctxt->mode == X86EMUL_MODE_PROT64 ?
2377 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2378 ctxt->_eip = msr_data;
e66bb2cc 2379
717746e3 2380 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2381 ctxt->eflags &= ~(msr_data | EFLG_RF);
2382#endif
2383 } else {
2384 /* legacy mode */
717746e3 2385 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2386 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2387
2388 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2389 }
2390
e54cfa97 2391 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2392}
2393
e01991e7 2394static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2395{
0225fb50 2396 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2397 struct desc_struct cs, ss;
8c604352 2398 u64 msr_data;
79168fd1 2399 u16 cs_sel, ss_sel;
c2ad2bb3 2400 u64 efer = 0;
8c604352 2401
7b105ca2 2402 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2403 /* inject #GP if in real mode */
35d3d4a1
AK		 2404 if (ctxt->mode == X86EMUL_MODE_REAL)
2405 return emulate_gp(ctxt, 0);
8c604352 2406
1a18a69b
AK		 2407 /*
2408 * Not recognized on AMD in compat mode (but is recognized in legacy
2409 * mode).
2410 */
2411 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2412 && !vendor_intel(ctxt))
2413 return emulate_ud(ctxt);
2414
8c604352
AP		 2415 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2416 * Therefore, we inject an #UD.
2417 */
35d3d4a1
AK		 2418 if (ctxt->mode == X86EMUL_MODE_PROT64)
2419 return emulate_ud(ctxt);
8c604352 2420
7b105ca2 2421 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2422
717746e3 2423 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2424 switch (ctxt->mode) {
2425 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2426 if ((msr_data & 0xfffc) == 0x0)
2427 return emulate_gp(ctxt, 0);
8c604352
AP		 2428 break;
2429 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2430 if (msr_data == 0x0)
2431 return emulate_gp(ctxt, 0);
8c604352 2432 break;
9d1b39a9
GN		 2433 default:
2434 break;
8c604352
AP		 2435 }
2436
2437 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2438 cs_sel = (u16)msr_data;
2439 cs_sel &= ~SELECTOR_RPL_MASK;
2440 ss_sel = cs_sel + 8;
2441 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2442 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2443 cs.d = 0;
8c604352
AP		 2444 cs.l = 1;
2445 }
2446
1aa36616
AK		 2447 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2448 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2449
717746e3 2450 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2451 ctxt->_eip = msr_data;
8c604352 2452
717746e3 2453 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2454 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2455
e54cfa97 2456 return X86EMUL_CONTINUE;
8c604352
AP		 2457}
2458
e01991e7 2459static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2460{
0225fb50 2461 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2462 struct desc_struct cs, ss;
4668f050
AP		 2463 u64 msr_data;
2464 int usermode;
1249b96e 2465 u16 cs_sel = 0, ss_sel = 0;
4668f050 2466
a0044755
GN		 2467 /* inject #GP if in real mode or Virtual 8086 mode */
2468 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2469 ctxt->mode == X86EMUL_MODE_VM86)
2470 return emulate_gp(ctxt, 0);
4668f050 2471
7b105ca2 2472 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2473
9dac77fa 2474 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2475 usermode = X86EMUL_MODE_PROT64;
2476 else
2477 usermode = X86EMUL_MODE_PROT32;
2478
2479 cs.dpl = 3;
2480 ss.dpl = 3;
717746e3 2481 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2482 switch (usermode) {
2483 case X86EMUL_MODE_PROT32:
79168fd1 2484 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2485 if ((msr_data & 0xfffc) == 0x0)
2486 return emulate_gp(ctxt, 0);
79168fd1 2487 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2488 break;
2489 case X86EMUL_MODE_PROT64:
79168fd1 2490 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2491 if (msr_data == 0x0)
2492 return emulate_gp(ctxt, 0);
79168fd1
GN		 2493 ss_sel = cs_sel + 8;
2494 cs.d = 0;
4668f050
AP		 2495 cs.l = 1;
2496 break;
2497 }
79168fd1
GN		 2498 cs_sel |= SELECTOR_RPL_MASK;
2499 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2500
1aa36616
AK		 2501 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2502 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2503
dd856efa
AK		 2504 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2505 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2506
e54cfa97 2507 return X86EMUL_CONTINUE;
4668f050
AP		 2508}
2509
7b105ca2 2510static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2511{
2512 int iopl;
2513 if (ctxt->mode == X86EMUL_MODE_REAL)
2514 return false;
2515 if (ctxt->mode == X86EMUL_MODE_VM86)
2516 return true;
2517 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2518 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2519}
2520
2521static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2522 u16 port, u16 len)
2523{
0225fb50 2524 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2525 struct desc_struct tr_seg;
5601d05b 2526 u32 base3;
f850e2e6 2527 int r;
1aa36616 2528 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2529 unsigned mask = (1 << len) - 1;
5601d05b 2530 unsigned long base;
f850e2e6 2531
1aa36616 2532 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2533 if (!tr_seg.p)
f850e2e6 2534 return false;
79168fd1 2535 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2536 return false;
5601d05b
GN		 2537 base = get_desc_base(&tr_seg);
2538#ifdef CONFIG_X86_64
2539 base |= ((u64)base3) << 32;
2540#endif
0f65dd70 2541 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2542 if (r != X86EMUL_CONTINUE)
2543 return false;
79168fd1 2544 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2545 return false;
0f65dd70 2546 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2547 if (r != X86EMUL_CONTINUE)
2548 return false;
2549 if ((perm >> bit_idx) & mask)
2550 return false;
2551 return true;
2552}
2553
2554static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2555 u16 port, u16 len)
2556{
4fc40f07
GN		 2557 if (ctxt->perm_ok)
2558 return true;
2559
7b105ca2
TY		 2560 if (emulator_bad_iopl(ctxt))
2561 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2562 return false;
4fc40f07
GN		 2563
2564 ctxt->perm_ok = true;
2565
f850e2e6
GN		 2566 return true;
2567}
2568
38ba30ba 2569static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2570 struct tss_segment_16 *tss)
2571{
9dac77fa 2572 tss->ip = ctxt->_eip;
38ba30ba 2573 tss->flag = ctxt->eflags;
dd856efa
AK		 2574 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2575 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2576 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2577 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2578 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2579 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2580 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2581 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2582
1aa36616
AK		 2583 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2584 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2585 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2586 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2587 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2588}
2589
2590static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2591 struct tss_segment_16 *tss)
2592{
38ba30ba
GN		 2593 int ret;
2594
9dac77fa 2595 ctxt->_eip = tss->ip;
38ba30ba 2596 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2597 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2598 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2599 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2600 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2601 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2602 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2603 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2604 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2605
2606 /*
2607 * SDM says that segment selectors are loaded before segment
2608 * descriptors
2609 */
1aa36616
AK		 2610 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2611 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2612 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2613 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2614 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2615
2616 /*
fc058680 2617 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2618 * it is handled in a context of new task
2619 */
7b105ca2 2620 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
7b105ca2 2623 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
7b105ca2 2626 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
7b105ca2 2629 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2630 if (ret != X86EMUL_CONTINUE)
2631 return ret;
7b105ca2 2632 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2633 if (ret != X86EMUL_CONTINUE)
2634 return ret;
2635
2636 return X86EMUL_CONTINUE;
2637}
2638
2639static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2640 u16 tss_selector, u16 old_tss_sel,
2641 ulong old_tss_base, struct desc_struct *new_desc)
2642{
0225fb50 2643 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2644 struct tss_segment_16 tss_seg;
2645 int ret;
bcc55cba 2646 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2647
0f65dd70 2648 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2649 &ctxt->exception);
db297e3d 2650 if (ret != X86EMUL_CONTINUE)
38ba30ba 2651 /* FIXME: need to provide precise fault address */
38ba30ba 2652 return ret;
38ba30ba 2653
7b105ca2 2654 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2655
0f65dd70 2656 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2657 &ctxt->exception);
db297e3d 2658 if (ret != X86EMUL_CONTINUE)
38ba30ba 2659 /* FIXME: need to provide precise fault address */
38ba30ba 2660 return ret;
38ba30ba 2661
0f65dd70 2662 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2663 &ctxt->exception);
db297e3d 2664 if (ret != X86EMUL_CONTINUE)
38ba30ba 2665 /* FIXME: need to provide precise fault address */
38ba30ba 2666 return ret;
38ba30ba
GN		 2667
2668 if (old_tss_sel != 0xffff) {
2669 tss_seg.prev_task_link = old_tss_sel;
2670
0f65dd70 2671 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2672 &tss_seg.prev_task_link,
2673 sizeof tss_seg.prev_task_link,
0f65dd70 2674 &ctxt->exception);
db297e3d 2675 if (ret != X86EMUL_CONTINUE)
38ba30ba 2676 /* FIXME: need to provide precise fault address */
38ba30ba 2677 return ret;
38ba30ba
GN		 2678 }
2679
7b105ca2 2680 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2681}
2682
2683static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2684 struct tss_segment_32 *tss)
2685{
7b105ca2 2686 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2687 tss->eip = ctxt->_eip;
38ba30ba 2688 tss->eflags = ctxt->eflags;
dd856efa
AK		 2689 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2690 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2691 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2692 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2693 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2694 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2695 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2696 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2697
1aa36616
AK		 2698 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2699 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2700 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2701 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2702 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2703 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2704 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2705}
2706
2707static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2708 struct tss_segment_32 *tss)
2709{
38ba30ba
GN		 2710 int ret;
2711
7b105ca2 2712 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2713 return emulate_gp(ctxt, 0);
9dac77fa 2714 ctxt->_eip = tss->eip;
38ba30ba 2715 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2716
2717 /* General purpose registers */
dd856efa
AK		 2718 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2719 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2720 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2721 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2722 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2723 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2724 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2725 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2726
2727 /*
2728 * SDM says that segment selectors are loaded before segment
2729 * descriptors
2730 */
1aa36616
AK		 2731 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2732 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2733 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2734 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2735 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2736 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2737 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2738
4cee4798
KW		 2739 /*
2740 * If we're switching between Protected Mode and VM86, we need to make
2741 * sure to update the mode before loading the segment descriptors so
2742 * that the selectors are interpreted correctly.
2743 *
2744 * Need to get rflags to the vcpu struct immediately because it
2745 * influences the CPL which is checked at least when loading the segment
2746 * descriptors and when pushing an error code to the new kernel stack.
2747 *
2748 * TODO Introduce a separate ctxt->ops->set_cpl callback
2749 */
2750 if (ctxt->eflags & X86_EFLAGS_VM)
2751 ctxt->mode = X86EMUL_MODE_VM86;
2752 else
2753 ctxt->mode = X86EMUL_MODE_PROT32;
2754
2755 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2756
38ba30ba
GN		 2757 /*
2758 * Now load segment descriptors. If fault happenes at this stage
2759 * it is handled in a context of new task
2760 */
7b105ca2 2761 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2762 if (ret != X86EMUL_CONTINUE)
2763 return ret;
7b105ca2 2764 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2765 if (ret != X86EMUL_CONTINUE)
2766 return ret;
7b105ca2 2767 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2768 if (ret != X86EMUL_CONTINUE)
2769 return ret;
7b105ca2 2770 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2771 if (ret != X86EMUL_CONTINUE)
2772 return ret;
7b105ca2 2773 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2774 if (ret != X86EMUL_CONTINUE)
2775 return ret;
7b105ca2 2776 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2777 if (ret != X86EMUL_CONTINUE)
2778 return ret;
7b105ca2 2779 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2780 if (ret != X86EMUL_CONTINUE)
2781 return ret;
2782
2783 return X86EMUL_CONTINUE;
2784}
2785
2786static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2787 u16 tss_selector, u16 old_tss_sel,
2788 ulong old_tss_base, struct desc_struct *new_desc)
2789{
0225fb50 2790 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2791 struct tss_segment_32 tss_seg;
2792 int ret;
bcc55cba 2793 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2794
0f65dd70 2795 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2796 &ctxt->exception);
db297e3d 2797 if (ret != X86EMUL_CONTINUE)
38ba30ba 2798 /* FIXME: need to provide precise fault address */
38ba30ba 2799 return ret;
38ba30ba 2800
7b105ca2 2801 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2802
0f65dd70 2803 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2804 &ctxt->exception);
db297e3d 2805 if (ret != X86EMUL_CONTINUE)
38ba30ba 2806 /* FIXME: need to provide precise fault address */
38ba30ba 2807 return ret;
38ba30ba 2808
0f65dd70 2809 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2810 &ctxt->exception);
db297e3d 2811 if (ret != X86EMUL_CONTINUE)
38ba30ba 2812 /* FIXME: need to provide precise fault address */
38ba30ba 2813 return ret;
38ba30ba
GN		 2814
2815 if (old_tss_sel != 0xffff) {
2816 tss_seg.prev_task_link = old_tss_sel;
2817
0f65dd70 2818 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2819 &tss_seg.prev_task_link,
2820 sizeof tss_seg.prev_task_link,
0f65dd70 2821 &ctxt->exception);
db297e3d 2822 if (ret != X86EMUL_CONTINUE)
38ba30ba 2823 /* FIXME: need to provide precise fault address */
38ba30ba 2824 return ret;
38ba30ba
GN		 2825 }
2826
7b105ca2 2827 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2828}
2829
2830static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2831 u16 tss_selector, int idt_index, int reason,
e269fb21 2832 bool has_error_code, u32 error_code)
38ba30ba 2833{
0225fb50 2834 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2835 struct desc_struct curr_tss_desc, next_tss_desc;
2836 int ret;
1aa36616 2837 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2838 ulong old_tss_base =
4bff1e86 2839 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2840 u32 desc_limit;
e919464b 2841 ulong desc_addr;
38ba30ba
GN		 2842
2843 /* FIXME: old_tss_base == ~0 ? */
2844
e919464b 2845 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2846 if (ret != X86EMUL_CONTINUE)
2847 return ret;
e919464b 2848 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2849 if (ret != X86EMUL_CONTINUE)
2850 return ret;
2851
2852 /* FIXME: check that next_tss_desc is tss */
2853
7f3d35fd
KW		 2854 /*
2855 * Check privileges. The three cases are task switch caused by...
2856 *
2857 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2858 * 2. Exception/IRQ/iret: No check is performed
fc058680 2859 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2860 */
2861 if (reason == TASK_SWITCH_GATE) {
2862 if (idt_index != -1) {
2863 /* Software interrupts */
2864 struct desc_struct task_gate_desc;
2865 int dpl;
2866
2867 ret = read_interrupt_descriptor(ctxt, idt_index,
2868 &task_gate_desc);
2869 if (ret != X86EMUL_CONTINUE)
2870 return ret;
2871
2872 dpl = task_gate_desc.dpl;
2873 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2874 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2875 }
2876 } else if (reason != TASK_SWITCH_IRET) {
2877 int dpl = next_tss_desc.dpl;
2878 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2879 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2880 }
2881
7f3d35fd 2882
ceffb459
GN		 2883 desc_limit = desc_limit_scaled(&next_tss_desc);
2884 if (!next_tss_desc.p ||
2885 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2886 desc_limit < 0x2b)) {
54b8486f 2887 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2888 return X86EMUL_PROPAGATE_FAULT;
2889 }
2890
2891 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2892 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2893 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2894 }
2895
2896 if (reason == TASK_SWITCH_IRET)
2897 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2898
2899 /* set back link to prev task only if NT bit is set in eflags
fc058680 2900 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2901 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2902 old_tss_sel = 0xffff;
2903
2904 if (next_tss_desc.type & 8)
7b105ca2 2905 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2906 old_tss_base, &next_tss_desc);
2907 else
7b105ca2 2908 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2909 old_tss_base, &next_tss_desc);
0760d448
JK		 2910 if (ret != X86EMUL_CONTINUE)
2911 return ret;
38ba30ba
GN		 2912
2913 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2914 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2915
2916 if (reason != TASK_SWITCH_IRET) {
2917 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2918 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2919 }
2920
717746e3 2921 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2922 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2923
e269fb21 2924 if (has_error_code) {
9dac77fa
AK		 2925 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2926 ctxt->lock_prefix = 0;
2927 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2928 ret = em_push(ctxt);
e269fb21
JK		 2929 }
2930
38ba30ba
GN		 2931 return ret;
2932}
2933
2934int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2935 u16 tss_selector, int idt_index, int reason,
e269fb21 2936 bool has_error_code, u32 error_code)
38ba30ba 2937{
38ba30ba
GN		 2938 int rc;
2939
dd856efa 2940 invalidate_registers(ctxt);
9dac77fa
AK		 2941 ctxt->_eip = ctxt->eip;
2942 ctxt->dst.type = OP_NONE;
38ba30ba 2943
7f3d35fd 2944 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2945 has_error_code, error_code);
38ba30ba 2946
dd856efa 2947 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2948 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2949 writeback_registers(ctxt);
2950 }
38ba30ba 2951
a0c0ab2f 2952 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2953}
2954
f3bd64c6
GN		 2955static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2956 struct operand *op)
a682e354 2957{
b3356bf0 2958 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2959
dd856efa
AK		 2960 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2961 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2962}
2963
7af04fc0
AK		 2964static int em_das(struct x86_emulate_ctxt *ctxt)
2965{
7af04fc0
AK		 2966 u8 al, old_al;
2967 bool af, cf, old_cf;
2968
2969 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2970 al = ctxt->dst.val;
7af04fc0
AK		 2971
2972 old_al = al;
2973 old_cf = cf;
2974 cf = false;
2975 af = ctxt->eflags & X86_EFLAGS_AF;
2976 if ((al & 0x0f) > 9 || af) {
2977 al -= 6;
2978 cf = old_cf | (al >= 250);
2979 af = true;
2980 } else {
2981 af = false;
2982 }
2983 if (old_al > 0x99 || old_cf) {
2984 al -= 0x60;
2985 cf = true;
2986 }
2987
9dac77fa 2988 ctxt->dst.val = al;
7af04fc0 2989 /* Set PF, ZF, SF */
9dac77fa
AK		 2990 ctxt->src.type = OP_IMM;
2991 ctxt->src.val = 0;
2992 ctxt->src.bytes = 1;
158de57f 2993 fastop(ctxt, em_or);
7af04fc0
AK		 2994 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2995 if (cf)
2996 ctxt->eflags |= X86_EFLAGS_CF;
2997 if (af)
2998 ctxt->eflags |= X86_EFLAGS_AF;
2999 return X86EMUL_CONTINUE;
3000}
3001
a035d5c6
PB		 3002static int em_aam(struct x86_emulate_ctxt *ctxt)
3003{
3004 u8 al, ah;
3005
3006 if (ctxt->src.val == 0)
3007 return emulate_de(ctxt);
3008
3009 al = ctxt->dst.val & 0xff;
3010 ah = al / ctxt->src.val;
3011 al %= ctxt->src.val;
3012
3013 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3014
3015 /* Set PF, ZF, SF */
3016 ctxt->src.type = OP_IMM;
3017 ctxt->src.val = 0;
3018 ctxt->src.bytes = 1;
3019 fastop(ctxt, em_or);
3020
3021 return X86EMUL_CONTINUE;
3022}
3023
7f662273
GN		 3024static int em_aad(struct x86_emulate_ctxt *ctxt)
3025{
3026 u8 al = ctxt->dst.val & 0xff;
3027 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3028
3029 al = (al + (ah * ctxt->src.val)) & 0xff;
3030
3031 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3032
f583c29b
GN		 3033 /* Set PF, ZF, SF */
3034 ctxt->src.type = OP_IMM;
3035 ctxt->src.val = 0;
3036 ctxt->src.bytes = 1;
3037 fastop(ctxt, em_or);
7f662273
GN		 3038
3039 return X86EMUL_CONTINUE;
3040}
3041
d4ddafcd
TY		 3042static int em_call(struct x86_emulate_ctxt *ctxt)
3043{
3044 long rel = ctxt->src.val;
3045
3046 ctxt->src.val = (unsigned long)ctxt->_eip;
3047 jmp_rel(ctxt, rel);
3048 return em_push(ctxt);
3049}
3050
0ef753b8
AK		 3051static int em_call_far(struct x86_emulate_ctxt *ctxt)
3052{
0ef753b8
AK		 3053 u16 sel, old_cs;
3054 ulong old_eip;
3055 int rc;
3056
1aa36616 3057 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 3058 old_eip = ctxt->_eip;
0ef753b8 3059
9dac77fa 3060 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3061 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3062 return X86EMUL_CONTINUE;
3063
9dac77fa
AK		 3064 ctxt->_eip = 0;
3065 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3066
9dac77fa 3067 ctxt->src.val = old_cs;
4487b3b4 3068 rc = em_push(ctxt);
0ef753b8
AK		 3069 if (rc != X86EMUL_CONTINUE)
3070 return rc;
3071
9dac77fa 3072 ctxt->src.val = old_eip;
4487b3b4 3073 return em_push(ctxt);
0ef753b8
AK		 3074}
3075
40ece7c7
AK		 3076static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3077{
40ece7c7
AK		 3078 int rc;
3079
9dac77fa
AK		 3080 ctxt->dst.type = OP_REG;
3081 ctxt->dst.addr.reg = &ctxt->_eip;
3082 ctxt->dst.bytes = ctxt->op_bytes;
3083 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3084 if (rc != X86EMUL_CONTINUE)
3085 return rc;
5ad105e5 3086 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3087 return X86EMUL_CONTINUE;
3088}
3089
e4f973ae
TY		 3090static int em_xchg(struct x86_emulate_ctxt *ctxt)
3091{
e4f973ae 3092 /* Write back the register source. */
9dac77fa
AK		 3093 ctxt->src.val = ctxt->dst.val;
3094 write_register_operand(&ctxt->src);
e4f973ae
TY		 3095
3096 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3097 ctxt->dst.val = ctxt->src.orig_val;
3098 ctxt->lock_prefix = 1;
e4f973ae
TY		 3099 return X86EMUL_CONTINUE;
3100}
3101
5c82aa29
AK		 3102static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3103{
9dac77fa 3104 ctxt->dst.val = ctxt->src2.val;
4d758349 3105 return fastop(ctxt, em_imul);
5c82aa29
AK		 3106}
3107
61429142
AK		 3108static int em_cwd(struct x86_emulate_ctxt *ctxt)
3109{
9dac77fa
AK		 3110 ctxt->dst.type = OP_REG;
3111 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3112 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3113 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3114
3115 return X86EMUL_CONTINUE;
3116}
3117
48bb5d3c
AK		 3118static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3119{
48bb5d3c
AK		 3120 u64 tsc = 0;
3121
717746e3 3122 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3123 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3124 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3125 return X86EMUL_CONTINUE;
3126}
3127
222d21aa
AK		 3128static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3129{
3130 u64 pmc;
3131
dd856efa 3132 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3133 return emulate_gp(ctxt, 0);
dd856efa
AK		 3134 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3135 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3136 return X86EMUL_CONTINUE;
3137}
3138
b9eac5f4
AK		 3139static int em_mov(struct x86_emulate_ctxt *ctxt)
3140{
49597d81 3141 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3142 return X86EMUL_CONTINUE;
3143}
3144
bc00f8d2
TY		 3145static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3146{
3147 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3148 return emulate_gp(ctxt, 0);
3149
3150 /* Disable writeback. */
3151 ctxt->dst.type = OP_NONE;
3152 return X86EMUL_CONTINUE;
3153}
3154
3155static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3156{
3157 unsigned long val;
3158
3159 if (ctxt->mode == X86EMUL_MODE_PROT64)
3160 val = ctxt->src.val & ~0ULL;
3161 else
3162 val = ctxt->src.val & ~0U;
3163
3164 /* #UD condition is already handled. */
3165 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3166 return emulate_gp(ctxt, 0);
3167
3168 /* Disable writeback. */
3169 ctxt->dst.type = OP_NONE;
3170 return X86EMUL_CONTINUE;
3171}
3172
e1e210b0
TY		 3173static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3174{
3175 u64 msr_data;
3176
dd856efa
AK		 3177 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3178 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3179 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3180 return emulate_gp(ctxt, 0);
3181
3182 return X86EMUL_CONTINUE;
3183}
3184
3185static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3186{
3187 u64 msr_data;
3188
dd856efa 3189 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3190 return emulate_gp(ctxt, 0);
3191
dd856efa
AK		 3192 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3193 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3194 return X86EMUL_CONTINUE;
3195}
3196
1bd5f469
TY		 3197static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3198{
9dac77fa 3199 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3200 return emulate_ud(ctxt);
3201
9dac77fa 3202 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3203 return X86EMUL_CONTINUE;
3204}
3205
3206static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3207{
9dac77fa 3208 u16 sel = ctxt->src.val;
1bd5f469 3209
9dac77fa 3210 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3211 return emulate_ud(ctxt);
3212
9dac77fa 3213 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3214 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3215
3216 /* Disable writeback. */
9dac77fa
AK		 3217 ctxt->dst.type = OP_NONE;
3218 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3219}
3220
a14e579f
AK		 3221static int em_lldt(struct x86_emulate_ctxt *ctxt)
3222{
3223 u16 sel = ctxt->src.val;
3224
3225 /* Disable writeback. */
3226 ctxt->dst.type = OP_NONE;
3227 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3228}
3229
80890006
AK		 3230static int em_ltr(struct x86_emulate_ctxt *ctxt)
3231{
3232 u16 sel = ctxt->src.val;
3233
3234 /* Disable writeback. */
3235 ctxt->dst.type = OP_NONE;
3236 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3237}
3238
38503911
AK		 3239static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3240{
9fa088f4
AK		 3241 int rc;
3242 ulong linear;
3243
9dac77fa 3244 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3245 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3246 ctxt->ops->invlpg(ctxt, linear);
38503911 3247 /* Disable writeback. */
9dac77fa 3248 ctxt->dst.type = OP_NONE;
38503911
AK		 3249 return X86EMUL_CONTINUE;
3250}
3251
2d04a05b
AK		 3252static int em_clts(struct x86_emulate_ctxt *ctxt)
3253{
3254 ulong cr0;
3255
3256 cr0 = ctxt->ops->get_cr(ctxt, 0);
3257 cr0 &= ~X86_CR0_TS;
3258 ctxt->ops->set_cr(ctxt, 0, cr0);
3259 return X86EMUL_CONTINUE;
3260}
3261
26d05cc7
AK		 3262static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3263{
26d05cc7
AK		 3264 int rc;
3265
9dac77fa 3266 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3267 return X86EMUL_UNHANDLEABLE;
3268
3269 rc = ctxt->ops->fix_hypercall(ctxt);
3270 if (rc != X86EMUL_CONTINUE)
3271 return rc;
3272
3273 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3274 ctxt->_eip = ctxt->eip;
26d05cc7 3275 /* Disable writeback. */
9dac77fa 3276 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3277 return X86EMUL_CONTINUE;
3278}
3279
96051572
AK		 3280static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3281 void (*get)(struct x86_emulate_ctxt *ctxt,
3282 struct desc_ptr *ptr))
3283{
3284 struct desc_ptr desc_ptr;
3285
3286 if (ctxt->mode == X86EMUL_MODE_PROT64)
3287 ctxt->op_bytes = 8;
3288 get(ctxt, &desc_ptr);
3289 if (ctxt->op_bytes == 2) {
3290 ctxt->op_bytes = 4;
3291 desc_ptr.address &= 0x00ffffff;
3292 }
3293 /* Disable writeback. */
3294 ctxt->dst.type = OP_NONE;
3295 return segmented_write(ctxt, ctxt->dst.addr.mem,
3296 &desc_ptr, 2 + ctxt->op_bytes);
3297}
3298
3299static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3300{
3301 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3302}
3303
3304static int em_sidt(struct x86_emulate_ctxt *ctxt)
3305{
3306 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3307}
3308
26d05cc7
AK		 3309static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3310{
26d05cc7
AK		 3311 struct desc_ptr desc_ptr;
3312 int rc;
3313
510425ff
AK		 3314 if (ctxt->mode == X86EMUL_MODE_PROT64)
3315 ctxt->op_bytes = 8;
9dac77fa 3316 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3317 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3318 ctxt->op_bytes);
26d05cc7
AK		 3319 if (rc != X86EMUL_CONTINUE)
3320 return rc;
3321 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3322 /* Disable writeback. */
9dac77fa 3323 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3324 return X86EMUL_CONTINUE;
3325}
3326
5ef39c71 3327static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3328{
26d05cc7
AK		 3329 int rc;
3330
5ef39c71
AK		 3331 rc = ctxt->ops->fix_hypercall(ctxt);
3332
26d05cc7 3333 /* Disable writeback. */
9dac77fa 3334 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3335 return rc;
3336}
3337
3338static int em_lidt(struct x86_emulate_ctxt *ctxt)
3339{
26d05cc7
AK		 3340 struct desc_ptr desc_ptr;
3341 int rc;
3342
510425ff
AK		 3343 if (ctxt->mode == X86EMUL_MODE_PROT64)
3344 ctxt->op_bytes = 8;
9dac77fa 3345 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3346 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3347 ctxt->op_bytes);
26d05cc7
AK		 3348 if (rc != X86EMUL_CONTINUE)
3349 return rc;
3350 ctxt->ops->set_idt(ctxt, &desc_ptr);
3351 /* Disable writeback. */
9dac77fa 3352 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3353 return X86EMUL_CONTINUE;
3354}
3355
3356static int em_smsw(struct x86_emulate_ctxt *ctxt)
3357{
9dac77fa
AK		 3358 ctxt->dst.bytes = 2;
3359 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3360 return X86EMUL_CONTINUE;
3361}
3362
3363static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3364{
26d05cc7 3365 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3366 | (ctxt->src.val & 0x0f));
3367 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3368 return X86EMUL_CONTINUE;
3369}
3370
d06e03ad
TY		 3371static int em_loop(struct x86_emulate_ctxt *ctxt)
3372{
dd856efa
AK		 3373 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3374 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3375 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3376 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3377
3378 return X86EMUL_CONTINUE;
3379}
3380
3381static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3382{
dd856efa 3383 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3384 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3385
3386 return X86EMUL_CONTINUE;
3387}
3388
d7841a4b
TY		 3389static int em_in(struct x86_emulate_ctxt *ctxt)
3390{
3391 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3392 &ctxt->dst.val))
3393 return X86EMUL_IO_NEEDED;
3394
3395 return X86EMUL_CONTINUE;
3396}
3397
3398static int em_out(struct x86_emulate_ctxt *ctxt)
3399{
3400 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3401 &ctxt->src.val, 1);
3402 /* Disable writeback. */
3403 ctxt->dst.type = OP_NONE;
3404 return X86EMUL_CONTINUE;
3405}
3406
f411e6cd
TY		 3407static int em_cli(struct x86_emulate_ctxt *ctxt)
3408{
3409 if (emulator_bad_iopl(ctxt))
3410 return emulate_gp(ctxt, 0);
3411
3412 ctxt->eflags &= ~X86_EFLAGS_IF;
3413 return X86EMUL_CONTINUE;
3414}
3415
3416static int em_sti(struct x86_emulate_ctxt *ctxt)
3417{
3418 if (emulator_bad_iopl(ctxt))
3419 return emulate_gp(ctxt, 0);
3420
3421 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3422 ctxt->eflags |= X86_EFLAGS_IF;
3423 return X86EMUL_CONTINUE;
3424}
3425
6d6eede4
AK		 3426static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3427{
3428 u32 eax, ebx, ecx, edx;
3429
dd856efa
AK		 3430 eax = reg_read(ctxt, VCPU_REGS_RAX);
3431 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3432 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3433 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3434 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3435 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3436 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3437 return X86EMUL_CONTINUE;
3438}
3439
2dd7caa0
AK		 3440static int em_lahf(struct x86_emulate_ctxt *ctxt)
3441{
dd856efa
AK		 3442 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3443 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3444 return X86EMUL_CONTINUE;
3445}
3446
9299836e
AK		 3447static int em_bswap(struct x86_emulate_ctxt *ctxt)
3448{
3449 switch (ctxt->op_bytes) {
3450#ifdef CONFIG_X86_64
3451 case 8:
3452 asm("bswap %0" : "+r"(ctxt->dst.val));
3453 break;
3454#endif
3455 default:
3456 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3457 break;
3458 }
3459 return X86EMUL_CONTINUE;
3460}
3461
cfec82cb
JR		 3462static bool valid_cr(int nr)
3463{
3464 switch (nr) {
3465 case 0:
3466 case 2 ... 4:
3467 case 8:
3468 return true;
3469 default:
3470 return false;
3471 }
3472}
3473
3474static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3475{
9dac77fa 3476 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3477 return emulate_ud(ctxt);
3478
3479 return X86EMUL_CONTINUE;
3480}
3481
3482static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3483{
9dac77fa
AK		 3484 u64 new_val = ctxt->src.val64;
3485 int cr = ctxt->modrm_reg;
c2ad2bb3 3486 u64 efer = 0;
cfec82cb
JR		 3487
3488 static u64 cr_reserved_bits[] = {
3489 0xffffffff00000000ULL,
3490 0, 0, 0, /* CR3 checked later */
3491 CR4_RESERVED_BITS,
3492 0, 0, 0,
3493 CR8_RESERVED_BITS,
3494 };
3495
3496 if (!valid_cr(cr))
3497 return emulate_ud(ctxt);
3498
3499 if (new_val & cr_reserved_bits[cr])
3500 return emulate_gp(ctxt, 0);
3501
3502 switch (cr) {
3503 case 0: {
c2ad2bb3 3504 u64 cr4;
cfec82cb
JR		 3505 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3506 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3507 return emulate_gp(ctxt, 0);
3508
717746e3
AK		 3509 cr4 = ctxt->ops->get_cr(ctxt, 4);
3510 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3511
3512 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3513 !(cr4 & X86_CR4_PAE))
3514 return emulate_gp(ctxt, 0);
3515
3516 break;
3517 }
3518 case 3: {
3519 u64 rsvd = 0;
3520
c2ad2bb3
AK		 3521 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3522 if (efer & EFER_LMA)
cfec82cb 3523 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3524 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3525 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3526 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3527 rsvd = CR3_NONPAE_RESERVED_BITS;
3528
3529 if (new_val & rsvd)
3530 return emulate_gp(ctxt, 0);
3531
3532 break;
3533 }
3534 case 4: {
717746e3 3535 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3536
3537 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3538 return emulate_gp(ctxt, 0);
3539
3540 break;
3541 }
3542 }
3543
3544 return X86EMUL_CONTINUE;
3545}
3546
3b88e41a
JR		 3547static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3548{
3549 unsigned long dr7;
3550
717746e3 3551 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3552
3553 /* Check if DR7.Global_Enable is set */
3554 return dr7 & (1 << 13);
3555}
3556
3557static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3558{
9dac77fa 3559 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3560 u64 cr4;
3561
3562 if (dr > 7)
3563 return emulate_ud(ctxt);
3564
717746e3 3565 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3566 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3567 return emulate_ud(ctxt);
3568
3569 if (check_dr7_gd(ctxt))
3570 return emulate_db(ctxt);
3571
3572 return X86EMUL_CONTINUE;
3573}
3574
3575static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3576{
9dac77fa
AK		 3577 u64 new_val = ctxt->src.val64;
3578 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3579
3580 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3581 return emulate_gp(ctxt, 0);
3582
3583 return check_dr_read(ctxt);
3584}
3585
01de8b09
JR		 3586static int check_svme(struct x86_emulate_ctxt *ctxt)
3587{
3588 u64 efer;
3589
717746e3 3590 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3591
3592 if (!(efer & EFER_SVME))
3593 return emulate_ud(ctxt);
3594
3595 return X86EMUL_CONTINUE;
3596}
3597
3598static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3599{
dd856efa 3600 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3601
3602 /* Valid physical address? */
d4224449 3603 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3604 return emulate_gp(ctxt, 0);
3605
3606 return check_svme(ctxt);
3607}
3608
d7eb8203
JR		 3609static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3610{
717746e3 3611 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3612
717746e3 3613 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3614 return emulate_ud(ctxt);
3615
3616 return X86EMUL_CONTINUE;
3617}
3618
8061252e
JR		 3619static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3620{
717746e3 3621 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3622 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3623
717746e3 3624 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3625 (rcx > 3))
3626 return emulate_gp(ctxt, 0);
3627
3628 return X86EMUL_CONTINUE;
3629}
3630
f6511935
JR		 3631static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3632{
9dac77fa
AK		 3633 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3634 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3635 return emulate_gp(ctxt, 0);
3636
3637 return X86EMUL_CONTINUE;
3638}
3639
3640static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3641{
9dac77fa
AK		 3642 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3643 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3644 return emulate_gp(ctxt, 0);
3645
3646 return X86EMUL_CONTINUE;
3647}
3648
73fba5f4 3649#define D(_y) { .flags = (_y) }
c4f035c6 3650#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3651#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3652 .check_perm = (_p) }
0b789eee 3653#define N D(NotImpl)
01de8b09 3654#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3655#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3656#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3657#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3658#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3659#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3660#define II(_f, _e, _i) \
3661 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3662#define IIP(_f, _e, _i, _p) \
3663 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3664 .check_perm = (_p) }
aa97bb48 3665#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3666
8d8f4e9f 3667#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3668#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3669#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3670#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3671#define I2bvIP(_f, _e, _i, _p) \
3672 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3673
fb864fbc
AK		 3674#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3675 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3676 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3677
fd0a0d82 3678static const struct opcode group7_rm1[] = {
1c2545be
TY		 3679 DI(SrcNone | Priv, monitor),
3680 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3681 N, N, N, N, N, N,
3682};
3683
fd0a0d82 3684static const struct opcode group7_rm3[] = {
1c2545be
TY		 3685 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3686 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3687 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3688 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3689 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3690 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3691 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3692 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3693};
6230f7fc 3694
fd0a0d82 3695static const struct opcode group7_rm7[] = {
d7eb8203 3696 N,
1c2545be 3697 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3698 N, N, N, N, N, N,
3699};
d67fc27a 3700
fd0a0d82 3701static const struct opcode group1[] = {
fb864fbc
AK		 3702 F(Lock, em_add),
3703 F(Lock | PageTable, em_or),
3704 F(Lock, em_adc),
3705 F(Lock, em_sbb),
3706 F(Lock | PageTable, em_and),
3707 F(Lock, em_sub),
3708 F(Lock, em_xor),
3709 F(NoWrite, em_cmp),
73fba5f4
AK		 3710};
3711
fd0a0d82 3712static const struct opcode group1A[] = {
1c2545be 3713 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3714};
3715
007a3b54
AK		 3716static const struct opcode group2[] = {
3717 F(DstMem | ModRM, em_rol),
3718 F(DstMem | ModRM, em_ror),
3719 F(DstMem | ModRM, em_rcl),
3720 F(DstMem | ModRM, em_rcr),
3721 F(DstMem | ModRM, em_shl),
3722 F(DstMem | ModRM, em_shr),
3723 F(DstMem | ModRM, em_shl),
3724 F(DstMem | ModRM, em_sar),
3725};
3726
fd0a0d82 3727static const struct opcode group3[] = {
fb864fbc
AK		 3728 F(DstMem | SrcImm | NoWrite, em_test),
3729 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3730 F(DstMem | SrcNone | Lock, em_not),
3731 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3732 I(SrcMem, em_mul_ex),
3733 I(SrcMem, em_imul_ex),
3734 I(SrcMem, em_div_ex),
3735 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3736};
3737
fd0a0d82 3738static const struct opcode group4[] = {
95413dc4
AK		 3739 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3740 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3741 N, N, N, N, N, N,
3742};
3743
fd0a0d82 3744static const struct opcode group5[] = {
95413dc4
AK		 3745 F(DstMem | SrcNone | Lock, em_inc),
3746 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3747 I(SrcMem | Stack, em_grp45),
3748 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3749 I(SrcMem | Stack, em_grp45),
3750 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3751 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3752};
3753
fd0a0d82 3754static const struct opcode group6[] = {
1c2545be
TY		 3755 DI(Prot, sldt),
3756 DI(Prot, str),
a14e579f 3757 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3758 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3759 N, N, N, N,
3760};
3761
fd0a0d82 3762static const struct group_dual group7 = { {
96051572
AK		 3763 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3764 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3765 II(SrcMem | Priv, em_lgdt, lgdt),
3766 II(SrcMem | Priv, em_lidt, lidt),
3767 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3768 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3769 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3770}, {
1c2545be 3771 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3772 EXT(0, group7_rm1),
01de8b09 3773 N, EXT(0, group7_rm3),
1c2545be
TY		 3774 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3775 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3776 EXT(0, group7_rm7),
73fba5f4
AK		 3777} };
3778
fd0a0d82 3779static const struct opcode group8[] = {
73fba5f4 3780 N, N, N, N,
11c363ba
AK		 3781 F(DstMem | SrcImmByte | NoWrite, em_bt),
3782 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3783 F(DstMem | SrcImmByte | Lock, em_btr),
3784 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3785};
3786
fd0a0d82 3787static const struct group_dual group9 = { {
1c2545be 3788 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3789}, {
3790 N, N, N, N, N, N, N, N,
3791} };
3792
fd0a0d82 3793static const struct opcode group11[] = {
1c2545be 3794 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3795 X7(D(Undefined)),
a4d4a7c1
AK		 3796};
3797
fd0a0d82 3798static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3799 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3800};
3801
fd0a0d82 3802static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3803 I(0, em_mov), N, N, N,
3804};
3805
045a282c
GN		 3806static const struct escape escape_d9 = { {
3807 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3808}, {
3809 /* 0xC0 - 0xC7 */
3810 N, N, N, N, N, N, N, N,
3811 /* 0xC8 - 0xCF */
3812 N, N, N, N, N, N, N, N,
3813 /* 0xD0 - 0xC7 */
3814 N, N, N, N, N, N, N, N,
3815 /* 0xD8 - 0xDF */
3816 N, N, N, N, N, N, N, N,
3817 /* 0xE0 - 0xE7 */
3818 N, N, N, N, N, N, N, N,
3819 /* 0xE8 - 0xEF */
3820 N, N, N, N, N, N, N, N,
3821 /* 0xF0 - 0xF7 */
3822 N, N, N, N, N, N, N, N,
3823 /* 0xF8 - 0xFF */
3824 N, N, N, N, N, N, N, N,
3825} };
3826
3827static const struct escape escape_db = { {
3828 N, N, N, N, N, N, N, N,
3829}, {
3830 /* 0xC0 - 0xC7 */
3831 N, N, N, N, N, N, N, N,
3832 /* 0xC8 - 0xCF */
3833 N, N, N, N, N, N, N, N,
3834 /* 0xD0 - 0xC7 */
3835 N, N, N, N, N, N, N, N,
3836 /* 0xD8 - 0xDF */
3837 N, N, N, N, N, N, N, N,
3838 /* 0xE0 - 0xE7 */
3839 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3840 /* 0xE8 - 0xEF */
3841 N, N, N, N, N, N, N, N,
3842 /* 0xF0 - 0xF7 */
3843 N, N, N, N, N, N, N, N,
3844 /* 0xF8 - 0xFF */
3845 N, N, N, N, N, N, N, N,
3846} };
3847
3848static const struct escape escape_dd = { {
3849 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3850}, {
3851 /* 0xC0 - 0xC7 */
3852 N, N, N, N, N, N, N, N,
3853 /* 0xC8 - 0xCF */
3854 N, N, N, N, N, N, N, N,
3855 /* 0xD0 - 0xC7 */
3856 N, N, N, N, N, N, N, N,
3857 /* 0xD8 - 0xDF */
3858 N, N, N, N, N, N, N, N,
3859 /* 0xE0 - 0xE7 */
3860 N, N, N, N, N, N, N, N,
3861 /* 0xE8 - 0xEF */
3862 N, N, N, N, N, N, N, N,
3863 /* 0xF0 - 0xF7 */
3864 N, N, N, N, N, N, N, N,
3865 /* 0xF8 - 0xFF */
3866 N, N, N, N, N, N, N, N,
3867} };
3868
fd0a0d82 3869static const struct opcode opcode_table[256] = {
73fba5f4 3870 /* 0x00 - 0x07 */
fb864fbc 3871 F6ALU(Lock, em_add),
1cd196ea
AK		 3872 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3873 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3874 /* 0x08 - 0x0F */
fb864fbc 3875 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3876 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3877 N,
73fba5f4 3878 /* 0x10 - 0x17 */
fb864fbc 3879 F6ALU(Lock, em_adc),
1cd196ea
AK		 3880 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3881 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3882 /* 0x18 - 0x1F */
fb864fbc 3883 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3884 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3885 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3886 /* 0x20 - 0x27 */
fb864fbc 3887 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3888 /* 0x28 - 0x2F */
fb864fbc 3889 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3890 /* 0x30 - 0x37 */
fb864fbc 3891 F6ALU(Lock, em_xor), N, N,
73fba5f4 3892 /* 0x38 - 0x3F */
fb864fbc 3893 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3894 /* 0x40 - 0x4F */
95413dc4 3895 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3896 /* 0x50 - 0x57 */
63540382 3897 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3898 /* 0x58 - 0x5F */
c54fe504 3899 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3900 /* 0x60 - 0x67 */
b96a7fad
TY		 3901 I(ImplicitOps | Stack | No64, em_pusha),
3902 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3903 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3904 N, N, N, N,
3905 /* 0x68 - 0x6F */
d46164db
AK		 3906 I(SrcImm | Mov | Stack, em_push),
3907 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3908 I(SrcImmByte | Mov | Stack, em_push),
3909 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3910 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3911 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3912 /* 0x70 - 0x7F */
3913 X16(D(SrcImmByte)),
3914 /* 0x80 - 0x87 */
1c2545be
TY		 3915 G(ByteOp | DstMem | SrcImm, group1),
3916 G(DstMem | SrcImm, group1),
3917 G(ByteOp | DstMem | SrcImm | No64, group1),
3918 G(DstMem | SrcImmByte, group1),
fb864fbc 3919 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3920 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3921 /* 0x88 - 0x8F */
d5ae7ce8 3922 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3923 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3924 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3925 D(ModRM | SrcMem | NoAccess | DstReg),
3926 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3927 G(0, group1A),
73fba5f4 3928 /* 0x90 - 0x97 */
bf608f88 3929 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3930 /* 0x98 - 0x9F */
61429142 3931 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3932 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3933 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3934 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3935 /* 0xA0 - 0xA7 */
b9eac5f4 3936 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3937 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3938 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3939 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3940 /* 0xA8 - 0xAF */
fb864fbc 3941 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3942 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3943 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3944 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3945 /* 0xB0 - 0xB7 */
b9eac5f4 3946 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3947 /* 0xB8 - 0xBF */
5e2c6883 3948 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3949 /* 0xC0 - 0xC7 */
007a3b54 3950 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3951 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3952 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3953 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3954 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3955 G(ByteOp, group11), G(0, group11),
73fba5f4 3956 /* 0xC8 - 0xCF */
612e89f0
AK		 3957 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3958 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3959 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3960 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3961 /* 0xD0 - 0xD7 */
007a3b54
AK		 3962 G(Src2One | ByteOp, group2), G(Src2One, group2),
3963 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3964 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3965 I(DstAcc | SrcImmUByte | No64, em_aad),
3966 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3967 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3968 /* 0xD8 - 0xDF */
045a282c 3969 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3970 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3971 X3(I(SrcImmByte, em_loop)),
3972 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3973 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3974 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3975 /* 0xE8 - 0xEF */
d4ddafcd 3976 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3977 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3978 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3979 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3980 /* 0xF0 - 0xF7 */
bf608f88 3981 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3982 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3983 G(ByteOp, group3), G(0, group3),
73fba5f4 3984 /* 0xF8 - 0xFF */
f411e6cd
TY		 3985 D(ImplicitOps), D(ImplicitOps),
3986 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3987 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3988};
3989
fd0a0d82 3990static const struct opcode twobyte_table[256] = {
73fba5f4 3991 /* 0x00 - 0x0F */
dee6bb70 3992 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3993 N, I(ImplicitOps | VendorSpecific, em_syscall),
3994 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3995 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3996 N, D(ImplicitOps | ModRM), N, N,
3997 /* 0x10 - 0x1F */
3998 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3999 /* 0x20 - 0x2F */
cfec82cb 4000 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 4001 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 4002 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4003 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 4004 N, N, N, N,
3e114eb4
AK		 4005 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4006 N, N, N, N,
73fba5f4 4007 /* 0x30 - 0x3F */
e1e210b0 4008 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4009 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4010 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4011 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 4012 I(ImplicitOps | VendorSpecific, em_sysenter),
4013 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 4014 N, N,
73fba5f4
AK		 4015 N, N, N, N, N, N, N, N,
4016 /* 0x40 - 0x4F */
4017 X16(D(DstReg | SrcMem | ModRM | Mov)),
4018 /* 0x50 - 0x5F */
4019 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4020 /* 0x60 - 0x6F */
aa97bb48
AK		 4021 N, N, N, N,
4022 N, N, N, N,
4023 N, N, N, N,
4024 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4025 /* 0x70 - 0x7F */
aa97bb48
AK		 4026 N, N, N, N,
4027 N, N, N, N,
4028 N, N, N, N,
4029 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4030 /* 0x80 - 0x8F */
4031 X16(D(SrcImm)),
4032 /* 0x90 - 0x9F */
ee45b58e 4033 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4034 /* 0xA0 - 0xA7 */
1cd196ea 4035 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4036 II(ImplicitOps, em_cpuid, cpuid),
4037 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4038 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4039 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4040 /* 0xA8 - 0xAF */
1cd196ea 4041 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4042 DI(ImplicitOps, rsm),
11c363ba 4043 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4044 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4045 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 4046 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4047 /* 0xB0 - 0xB7 */
e940b5c2 4048 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4049 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4050 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4051 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4052 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4053 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4054 /* 0xB8 - 0xBF */
4055 N, N,
ce7faab2 4056 G(BitOp, group8),
11c363ba
AK		 4057 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4058 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4059 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4060 /* 0xC0 - 0xC7 */
739ae406 4061 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4062 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4063 N, N, N, GD(0, &group9),
9299836e
AK		 4064 /* 0xC8 - 0xCF */
4065 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4066 /* 0xD0 - 0xDF */
4067 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4068 /* 0xE0 - 0xEF */
4069 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4070 /* 0xF0 - 0xFF */
4071 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4072};
4073
4074#undef D
4075#undef N
4076#undef G
4077#undef GD
4078#undef I
aa97bb48 4079#undef GP
01de8b09 4080#undef EXT
73fba5f4 4081
8d8f4e9f 4082#undef D2bv
f6511935 4083#undef D2bvIP
8d8f4e9f 4084#undef I2bv
d7841a4b 4085#undef I2bvIP
d67fc27a 4086#undef I6ALU
8d8f4e9f 4087
9dac77fa 4088static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4089{
4090 unsigned size;
4091
9dac77fa 4092 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4093 if (size == 8)
4094 size = 4;
4095 return size;
4096}
4097
4098static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4099 unsigned size, bool sign_extension)
4100{
39f21ee5
AK		 4101 int rc = X86EMUL_CONTINUE;
4102
4103 op->type = OP_IMM;
4104 op->bytes = size;
9dac77fa 4105 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4106 /* NB. Immediates are sign-extended as necessary. */
4107 switch (op->bytes) {
4108 case 1:
e85a1085 4109 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4110 break;
4111 case 2:
e85a1085 4112 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4113 break;
4114 case 4:
e85a1085 4115 op->val = insn_fetch(s32, ctxt);
39f21ee5 4116 break;
5e2c6883
NA		 4117 case 8:
4118 op->val = insn_fetch(s64, ctxt);
4119 break;
39f21ee5
AK		 4120 }
4121 if (!sign_extension) {
4122 switch (op->bytes) {
4123 case 1:
4124 op->val &= 0xff;
4125 break;
4126 case 2:
4127 op->val &= 0xffff;
4128 break;
4129 case 4:
4130 op->val &= 0xffffffff;
4131 break;
4132 }
4133 }
4134done:
4135 return rc;
4136}
4137
a9945549
AK		 4138static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4139 unsigned d)
4140{
4141 int rc = X86EMUL_CONTINUE;
4142
4143 switch (d) {
4144 case OpReg:
2adb5ad9 4145 decode_register_operand(ctxt, op);
a9945549
AK		 4146 break;
4147 case OpImmUByte:
608aabe3 4148 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4149 break;
4150 case OpMem:
41ddf978 4151 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4152 mem_common:
4153 *op = ctxt->memop;
4154 ctxt->memopp = op;
4155 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4156 fetch_bit_operand(ctxt);
4157 op->orig_val = op->val;
4158 break;
41ddf978
AK		 4159 case OpMem64:
4160 ctxt->memop.bytes = 8;
4161 goto mem_common;
a9945549
AK		 4162 case OpAcc:
4163 op->type = OP_REG;
4164 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4165 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4166 fetch_register_operand(op);
4167 op->orig_val = op->val;
4168 break;
4169 case OpDI:
4170 op->type = OP_MEM;
4171 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4172 op->addr.mem.ea =
dd856efa 4173 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4174 op->addr.mem.seg = VCPU_SREG_ES;
4175 op->val = 0;
b3356bf0 4176 op->count = 1;
a9945549
AK		 4177 break;
4178 case OpDX:
4179 op->type = OP_REG;
4180 op->bytes = 2;
dd856efa 4181 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4182 fetch_register_operand(op);
4183 break;
4dd6a57d
AK		 4184 case OpCL:
4185 op->bytes = 1;
dd856efa 4186 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4187 break;
4188 case OpImmByte:
4189 rc = decode_imm(ctxt, op, 1, true);
4190 break;
4191 case OpOne:
4192 op->bytes = 1;
4193 op->val = 1;
4194 break;
4195 case OpImm:
4196 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4197 break;
5e2c6883
NA		 4198 case OpImm64:
4199 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4200 break;
28867cee
AK		 4201 case OpMem8:
4202 ctxt->memop.bytes = 1;
660696d1
GN		 4203 if (ctxt->memop.type == OP_REG) {
4204 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4205 fetch_register_operand(&ctxt->memop);
4206 }
28867cee 4207 goto mem_common;
0fe59128
AK		 4208 case OpMem16:
4209 ctxt->memop.bytes = 2;
4210 goto mem_common;
4211 case OpMem32:
4212 ctxt->memop.bytes = 4;
4213 goto mem_common;
4214 case OpImmU16:
4215 rc = decode_imm(ctxt, op, 2, false);
4216 break;
4217 case OpImmU:
4218 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4219 break;
4220 case OpSI:
4221 op->type = OP_MEM;
4222 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4223 op->addr.mem.ea =
dd856efa 4224 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4225 op->addr.mem.seg = seg_override(ctxt);
4226 op->val = 0;
b3356bf0 4227 op->count = 1;
0fe59128 4228 break;
7fa57952
PB		 4229 case OpXLat:
4230 op->type = OP_MEM;
4231 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4232 op->addr.mem.ea =
4233 register_address(ctxt,
4234 reg_read(ctxt, VCPU_REGS_RBX) +
4235 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4236 op->addr.mem.seg = seg_override(ctxt);
4237 op->val = 0;
4238 break;
0fe59128
AK		 4239 case OpImmFAddr:
4240 op->type = OP_IMM;
4241 op->addr.mem.ea = ctxt->_eip;
4242 op->bytes = ctxt->op_bytes + 2;
4243 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4244 break;
4245 case OpMemFAddr:
4246 ctxt->memop.bytes = ctxt->op_bytes + 2;
4247 goto mem_common;
c191a7a0
AK		 4248 case OpES:
4249 op->val = VCPU_SREG_ES;
4250 break;
4251 case OpCS:
4252 op->val = VCPU_SREG_CS;
4253 break;
4254 case OpSS:
4255 op->val = VCPU_SREG_SS;
4256 break;
4257 case OpDS:
4258 op->val = VCPU_SREG_DS;
4259 break;
4260 case OpFS:
4261 op->val = VCPU_SREG_FS;
4262 break;
4263 case OpGS:
4264 op->val = VCPU_SREG_GS;
4265 break;
a9945549
AK		 4266 case OpImplicit:
4267 /* Special instructions do their own operand decoding. */
4268 default:
4269 op->type = OP_NONE; /* Disable writeback. */
4270 break;
4271 }
4272
4273done:
4274 return rc;
4275}
4276
ef5d75cc 4277int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4278{
dde7e6d1
AK		 4279 int rc = X86EMUL_CONTINUE;
4280 int mode = ctxt->mode;
46561646 4281 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4282 bool op_prefix = false;
46561646 4283 struct opcode opcode;
dde7e6d1 4284
f09ed83e
AK		 4285 ctxt->memop.type = OP_NONE;
4286 ctxt->memopp = NULL;
9dac77fa
AK		 4287 ctxt->_eip = ctxt->eip;
4288 ctxt->fetch.start = ctxt->_eip;
4289 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4290 if (insn_len > 0)
9dac77fa 4291 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4292
4293 switch (mode) {
4294 case X86EMUL_MODE_REAL:
4295 case X86EMUL_MODE_VM86:
4296 case X86EMUL_MODE_PROT16:
4297 def_op_bytes = def_ad_bytes = 2;
4298 break;
4299 case X86EMUL_MODE_PROT32:
4300 def_op_bytes = def_ad_bytes = 4;
4301 break;
4302#ifdef CONFIG_X86_64
4303 case X86EMUL_MODE_PROT64:
4304 def_op_bytes = 4;
4305 def_ad_bytes = 8;
4306 break;
4307#endif
4308 default:
1d2887e2 4309 return EMULATION_FAILED;
dde7e6d1
AK		 4310 }
4311
9dac77fa
AK		 4312 ctxt->op_bytes = def_op_bytes;
4313 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4314
4315 /* Legacy prefixes. */
4316 for (;;) {
e85a1085 4317 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4318 case 0x66: /* operand-size override */
0d7cdee8 4319 op_prefix = true;
dde7e6d1 4320 /* switch between 2/4 bytes */
9dac77fa 4321 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4322 break;
4323 case 0x67: /* address-size override */
4324 if (mode == X86EMUL_MODE_PROT64)
4325 /* switch between 4/8 bytes */
9dac77fa 4326 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4327 else
4328 /* switch between 2/4 bytes */
9dac77fa 4329 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4330 break;
4331 case 0x26: /* ES override */
4332 case 0x2e: /* CS override */
4333 case 0x36: /* SS override */
4334 case 0x3e: /* DS override */
9dac77fa 4335 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4336 break;
4337 case 0x64: /* FS override */
4338 case 0x65: /* GS override */
9dac77fa 4339 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4340 break;
4341 case 0x40 ... 0x4f: /* REX */
4342 if (mode != X86EMUL_MODE_PROT64)
4343 goto done_prefixes;
9dac77fa 4344 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4345 continue;
4346 case 0xf0: /* LOCK */
9dac77fa 4347 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4348 break;
4349 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4350 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4351 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4352 break;
4353 default:
4354 goto done_prefixes;
4355 }
4356
4357 /* Any legacy prefix after a REX prefix nullifies its effect. */
4358
9dac77fa 4359 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4360 }
4361
4362done_prefixes:
4363
4364 /* REX prefix. */
9dac77fa
AK		 4365 if (ctxt->rex_prefix & 8)
4366 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4367
4368 /* Opcode byte(s). */
9dac77fa 4369 opcode = opcode_table[ctxt->b];
d3ad6243 4370 /* Two-byte opcode? */
9dac77fa
AK		 4371 if (ctxt->b == 0x0f) {
4372 ctxt->twobyte = 1;
e85a1085 4373 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4374 opcode = twobyte_table[ctxt->b];
dde7e6d1 4375 }
9dac77fa 4376 ctxt->d = opcode.flags;
dde7e6d1 4377
9f4260e7
TY		 4378 if (ctxt->d & ModRM)
4379 ctxt->modrm = insn_fetch(u8, ctxt);
4380
9dac77fa
AK		 4381 while (ctxt->d & GroupMask) {
4382 switch (ctxt->d & GroupMask) {
46561646 4383 case Group:
9dac77fa 4384 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4385 opcode = opcode.u.group[goffset];
4386 break;
4387 case GroupDual:
9dac77fa
AK		 4388 goffset = (ctxt->modrm >> 3) & 7;
4389 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4390 opcode = opcode.u.gdual->mod3[goffset];
4391 else
4392 opcode = opcode.u.gdual->mod012[goffset];
4393 break;
4394 case RMExt:
9dac77fa 4395 goffset = ctxt->modrm & 7;
01de8b09 4396 opcode = opcode.u.group[goffset];
46561646
AK		 4397 break;
4398 case Prefix:
9dac77fa 4399 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4400 return EMULATION_FAILED;
9dac77fa 4401 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4402 switch (simd_prefix) {
4403 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4404 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4405 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4406 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4407 }
4408 break;
045a282c
GN		 4409 case Escape:
4410 if (ctxt->modrm > 0xbf)
4411 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4412 else
4413 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4414 break;
46561646 4415 default:
1d2887e2 4416 return EMULATION_FAILED;
0d7cdee8 4417 }
46561646 4418
b1ea50b2 4419 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4420 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4421 }
4422
9dac77fa
AK		 4423 ctxt->execute = opcode.u.execute;
4424 ctxt->check_perm = opcode.check_perm;
4425 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4426
4427 /* Unrecognised? */
1146a78b 4428 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4429 return EMULATION_FAILED;
dde7e6d1 4430
9dac77fa 4431 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4432 return EMULATION_FAILED;
d867162c 4433
9dac77fa
AK		 4434 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4435 ctxt->op_bytes = 8;
dde7e6d1 4436
9dac77fa 4437 if (ctxt->d & Op3264) {
7f9b4b75 4438 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4439 ctxt->op_bytes = 8;
7f9b4b75 4440 else
9dac77fa 4441 ctxt->op_bytes = 4;
7f9b4b75
AK		 4442 }
4443
9dac77fa
AK		 4444 if (ctxt->d & Sse)
4445 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4446 else if (ctxt->d & Mmx)
4447 ctxt->op_bytes = 8;
1253791d 4448
dde7e6d1 4449 /* ModRM and SIB bytes. */
9dac77fa 4450 if (ctxt->d & ModRM) {
f09ed83e 4451 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4452 if (!ctxt->has_seg_override)
4453 set_seg_override(ctxt, ctxt->modrm_seg);
4454 } else if (ctxt->d & MemAbs)
f09ed83e 4455 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4456 if (rc != X86EMUL_CONTINUE)
4457 goto done;
4458
9dac77fa
AK		 4459 if (!ctxt->has_seg_override)
4460 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4461
f09ed83e 4462 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4463
f09ed83e
AK		 4464 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4465 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4466
dde7e6d1
AK		 4467 /*
4468 * Decode and fetch the source operand: register, memory
4469 * or immediate.
4470 */
0fe59128 4471 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4472 if (rc != X86EMUL_CONTINUE)
4473 goto done;
4474
dde7e6d1
AK		 4475 /*
4476 * Decode and fetch the second source operand: register, memory
4477 * or immediate.
4478 */
4dd6a57d 4479 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4480 if (rc != X86EMUL_CONTINUE)
4481 goto done;
4482
dde7e6d1 4483 /* Decode and fetch the destination operand: register or memory. */
a9945549 4484 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4485
4486done:
f09ed83e
AK		 4487 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4488 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4489
1d2887e2 4490 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4491}
4492
1cb3f3ae
XG		 4493bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4494{
4495 return ctxt->d & PageTable;
4496}
4497
3e2f65d5
GN		 4498static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4499{
3e2f65d5
GN		 4500 /* The second termination condition only applies for REPE
4501 * and REPNE. Test if the repeat string operation prefix is
4502 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4503 * corresponding termination condition according to:
4504 * - if REPE/REPZ and ZF = 0 then done
4505 * - if REPNE/REPNZ and ZF = 1 then done
4506 */
9dac77fa
AK		 4507 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4508 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4509 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4510 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4511 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4512 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4513 return true;
4514
4515 return false;
4516}
4517
cbe2c9d3
AK		 4518static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4519{
4520 bool fault = false;
4521
4522 ctxt->ops->get_fpu(ctxt);
4523 asm volatile("1: fwait \n\t"
4524 "2: \n\t"
4525 ".pushsection .fixup,\"ax\" \n\t"
4526 "3: \n\t"
4527 "movb $1, %[fault] \n\t"
4528 "jmp 2b \n\t"
4529 ".popsection \n\t"
4530 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4531 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4532 ctxt->ops->put_fpu(ctxt);
4533
4534 if (unlikely(fault))
4535 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4536
4537 return X86EMUL_CONTINUE;
4538}
4539
4540static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4541 struct operand *op)
4542{
4543 if (op->type == OP_MM)
4544 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4545}
4546
e28bbd44
AK		 4547static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4548{
4549 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4550 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4551 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4552 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4553 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4554 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4555 return X86EMUL_CONTINUE;
4556}
dd856efa 4557
7b105ca2 4558int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4559{
0225fb50 4560 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4561 int rc = X86EMUL_CONTINUE;
9dac77fa 4562 int saved_dst_type = ctxt->dst.type;
8b4caf66 4563
9dac77fa 4564 ctxt->mem_read.pos = 0;
310b5d30 4565
1146a78b
GN		 4566 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4567 (ctxt->d & Undefined)) {
35d3d4a1 4568 rc = emulate_ud(ctxt);
1161624f
GN		 4569 goto done;
4570 }
4571
d380a5e4 4572 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4573 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4574 rc = emulate_ud(ctxt);
d380a5e4
GN		 4575 goto done;
4576 }
4577
9dac77fa 4578 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4579 rc = emulate_ud(ctxt);
081bca0e
AK		 4580 goto done;
4581 }
4582
cbe2c9d3
AK		 4583 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4584 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4585 rc = emulate_ud(ctxt);
4586 goto done;
4587 }
4588
cbe2c9d3 4589 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4590 rc = emulate_nm(ctxt);
4591 goto done;
4592 }
4593
cbe2c9d3
AK		 4594 if (ctxt->d & Mmx) {
4595 rc = flush_pending_x87_faults(ctxt);
4596 if (rc != X86EMUL_CONTINUE)
4597 goto done;
4598 /*
4599 * Now that we know the fpu is exception safe, we can fetch
4600 * operands from it.
4601 */
4602 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4603 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4604 if (!(ctxt->d & Mov))
4605 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4606 }
4607
9dac77fa
AK		 4608 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4609 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4610 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4611 if (rc != X86EMUL_CONTINUE)
4612 goto done;
4613 }
4614
e92805ac 4615 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4616 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4617 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4618 goto done;
4619 }
4620
8ea7d6ae 4621 /* Instruction can only be executed in protected mode */
9d1b39a9 4622 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4623 rc = emulate_ud(ctxt);
4624 goto done;
4625 }
4626
d09beabd 4627 /* Do instruction specific permission checks */
9dac77fa
AK		 4628 if (ctxt->check_perm) {
4629 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4630 if (rc != X86EMUL_CONTINUE)
4631 goto done;
4632 }
4633
9dac77fa
AK		 4634 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4635 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4636 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4637 if (rc != X86EMUL_CONTINUE)
4638 goto done;
4639 }
4640
9dac77fa 4641 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4642 /* All REP prefixes have the same first termination condition */
dd856efa 4643 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4644 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4645 goto done;
4646 }
b9fa9d6b
AK		 4647 }
4648
9dac77fa
AK		 4649 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4650 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4651 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4652 if (rc != X86EMUL_CONTINUE)
8b4caf66 4653 goto done;
9dac77fa 4654 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4655 }
4656
9dac77fa
AK		 4657 if (ctxt->src2.type == OP_MEM) {
4658 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4659 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4660 if (rc != X86EMUL_CONTINUE)
4661 goto done;
4662 }
4663
9dac77fa 4664 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4665 goto special_insn;
4666
4667
9dac77fa 4668 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4669 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4670 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4671 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4672 if (rc != X86EMUL_CONTINUE)
4673 goto done;
038e51de 4674 }
9dac77fa 4675 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4676
018a98db
AK		 4677special_insn:
4678
9dac77fa
AK		 4679 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4680 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4681 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4682 if (rc != X86EMUL_CONTINUE)
4683 goto done;
4684 }
4685
9dac77fa 4686 if (ctxt->execute) {
e28bbd44
AK		 4687 if (ctxt->d & Fastop) {
4688 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4689 rc = fastop(ctxt, fop);
4690 if (rc != X86EMUL_CONTINUE)
4691 goto done;
4692 goto writeback;
4693 }
9dac77fa 4694 rc = ctxt->execute(ctxt);
ef65c889
AK		 4695 if (rc != X86EMUL_CONTINUE)
4696 goto done;
4697 goto writeback;
4698 }
4699
9dac77fa 4700 if (ctxt->twobyte)
6aa8b732
AK		 4701 goto twobyte_insn;
4702
9dac77fa 4703 switch (ctxt->b) {
6aa8b732 4704 case 0x63: /* movsxd */
8b4caf66 4705 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4706 goto cannot_emulate;
9dac77fa 4707 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4708 break;
b2833e3c 4709 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4710 if (test_cc(ctxt->b, ctxt->eflags))
4711 jmp_rel(ctxt, ctxt->src.val);
018a98db 4712 break;
7e0b54b1 4713 case 0x8d: /* lea r16/r32, m */
9dac77fa 4714 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4715 break;
3d9e77df 4716 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4717 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4718 break;
e4f973ae
TY		 4719 rc = em_xchg(ctxt);
4720 break;
e8b6fa70 4721 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4722 switch (ctxt->op_bytes) {
4723 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4724 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4725 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4726 }
4727 break;
6e154e56 4728 case 0xcc: /* int3 */
5c5df76b
TY		 4729 rc = emulate_int(ctxt, 3);
4730 break;
6e154e56 4731 case 0xcd: /* int n */
9dac77fa 4732 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4733 break;
4734 case 0xce: /* into */
5c5df76b
TY		 4735 if (ctxt->eflags & EFLG_OF)
4736 rc = emulate_int(ctxt, 4);
6e154e56 4737 break;
1a52e051 4738 case 0xe9: /* jmp rel */
db5b0762 4739 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4740 jmp_rel(ctxt, ctxt->src.val);
4741 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4742 break;
111de5d6 4743 case 0xf4: /* hlt */
6c3287f7 4744 ctxt->ops->halt(ctxt);
19fdfa0d 4745 break;
111de5d6
AK		 4746 case 0xf5: /* cmc */
4747 /* complement carry flag from eflags reg */
4748 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4749 break;
4750 case 0xf8: /* clc */
4751 ctxt->eflags &= ~EFLG_CF;
111de5d6 4752 break;
8744aa9a
MG		 4753 case 0xf9: /* stc */
4754 ctxt->eflags |= EFLG_CF;
4755 break;
fb4616f4
MG		 4756 case 0xfc: /* cld */
4757 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4758 break;
4759 case 0xfd: /* std */
4760 ctxt->eflags |= EFLG_DF;
fb4616f4 4761 break;
91269b8f
AK		 4762 default:
4763 goto cannot_emulate;
6aa8b732 4764 }
018a98db 4765
7d9ddaed
AK		 4766 if (rc != X86EMUL_CONTINUE)
4767 goto done;
4768
018a98db 4769writeback:
fb32b1ed
AK		 4770 if (!(ctxt->d & NoWrite)) {
4771 rc = writeback(ctxt, &ctxt->dst);
4772 if (rc != X86EMUL_CONTINUE)
4773 goto done;
4774 }
4775 if (ctxt->d & SrcWrite) {
4776 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4777 rc = writeback(ctxt, &ctxt->src);
4778 if (rc != X86EMUL_CONTINUE)
4779 goto done;
4780 }
018a98db 4781
5cd21917
GN		 4782 /*
4783 * restore dst type in case the decoding will be reused
4784 * (happens for string instruction )
4785 */
9dac77fa 4786 ctxt->dst.type = saved_dst_type;
5cd21917 4787
9dac77fa 4788 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4789 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4790
9dac77fa 4791 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4792 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4793
9dac77fa 4794 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4795 unsigned int count;
9dac77fa 4796 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4797 if ((ctxt->d & SrcMask) == SrcSI)
4798 count = ctxt->src.count;
4799 else
4800 count = ctxt->dst.count;
4801 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4802 -count);
3e2f65d5 4803
d2ddd1c4
GN		 4804 if (!string_insn_completed(ctxt)) {
4805 /*
4806 * Re-enter guest when pio read ahead buffer is empty
4807 * or, if it is not used, after each 1024 iteration.
4808 */
dd856efa 4809 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4810 (r->end == 0 || r->end != r->pos)) {
4811 /*
4812 * Reset read cache. Usually happens before
4813 * decode, but since instruction is restarted
4814 * we have to do it here.
4815 */
9dac77fa 4816 ctxt->mem_read.end = 0;
dd856efa 4817 writeback_registers(ctxt);
d2ddd1c4
GN		 4818 return EMULATION_RESTART;
4819 }
4820 goto done; /* skip rip writeback */
0fa6ccbd 4821 }
5cd21917 4822 }
d2ddd1c4 4823
9dac77fa 4824 ctxt->eip = ctxt->_eip;
018a98db
AK		 4825
4826done:
da9cb575
AK		 4827 if (rc == X86EMUL_PROPAGATE_FAULT)
4828 ctxt->have_exception = true;
775fde86
JR		 4829 if (rc == X86EMUL_INTERCEPTED)
4830 return EMULATION_INTERCEPTED;
4831
dd856efa
AK		 4832 if (rc == X86EMUL_CONTINUE)
4833 writeback_registers(ctxt);
4834
d2ddd1c4 4835 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4836
4837twobyte_insn:
9dac77fa 4838 switch (ctxt->b) {
018a98db 4839 case 0x09: /* wbinvd */
cfb22375 4840 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4841 break;
4842 case 0x08: /* invd */
018a98db
AK		 4843 case 0x0d: /* GrpP (prefetch) */
4844 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4845 break;
4846 case 0x20: /* mov cr, reg */
9dac77fa 4847 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4848 break;
6aa8b732 4849 case 0x21: /* mov from dr to reg */
9dac77fa 4850 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4851 break;
6aa8b732 4852 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4853 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4854 if (!test_cc(ctxt->b, ctxt->eflags))
4855 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4856 break;
b2833e3c 4857 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4858 if (test_cc(ctxt->b, ctxt->eflags))
4859 jmp_rel(ctxt, ctxt->src.val);
018a98db 4860 break;
ee45b58e 4861 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4862 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4863 break;
2a7c5b8b
GC		 4864 case 0xae: /* clflush */
4865 break;
6aa8b732 4866 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4867 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4868 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4869 : (u16) ctxt->src.val;
6aa8b732 4870 break;
6aa8b732 4871 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4872 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4873 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4874 (s16) ctxt->src.val;
6aa8b732 4875 break;
92f738a5 4876 case 0xc0 ... 0xc1: /* xadd */
158de57f 4877 fastop(ctxt, em_add);
92f738a5 4878 /* Write back the register source. */
9dac77fa
AK		 4879 ctxt->src.val = ctxt->dst.orig_val;
4880 write_register_operand(&ctxt->src);
92f738a5 4881 break;
a012e65a 4882 case 0xc3: /* movnti */
9dac77fa
AK		 4883 ctxt->dst.bytes = ctxt->op_bytes;
4884 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4885 (u64) ctxt->src.val;
a012e65a 4886 break;
91269b8f
AK		 4887 default:
4888 goto cannot_emulate;
6aa8b732 4889 }
7d9ddaed
AK		 4890
4891 if (rc != X86EMUL_CONTINUE)
4892 goto done;
4893
6aa8b732
AK		 4894 goto writeback;
4895
4896cannot_emulate:
a0c0ab2f 4897 return EMULATION_FAILED;
6aa8b732 4898}
dd856efa
AK		 4899
4900void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4901{
4902 invalidate_registers(ctxt);
4903}
4904
4905void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4906{
4907 writeback_registers(ctxt);
4908}
Linux kernel - Deliverables
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