Commit | Line | Data |
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7837699f SY |
1 | /* |
2 | * 8253/8254 interval timer emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2006 Intel Corporation | |
6 | * Copyright (c) 2007 Keir Fraser, XenSource Inc | |
7 | * Copyright (c) 2008 Intel Corporation | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
7837699f SY |
9 | * |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Sheng Yang <sheng.yang@intel.com> | |
30 | * Based on QEMU and Xen. | |
31 | */ | |
32 | ||
a78d9626 JP |
33 | #define pr_fmt(fmt) "pit: " fmt |
34 | ||
7837699f | 35 | #include <linux/kvm_host.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
7837699f | 37 | |
49df6397 | 38 | #include "ioapic.h" |
7837699f SY |
39 | #include "irq.h" |
40 | #include "i8254.h" | |
9ed96e87 | 41 | #include "x86.h" |
7837699f SY |
42 | |
43 | #ifndef CONFIG_X86_64 | |
6f6d6a1a | 44 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) |
7837699f SY |
45 | #else |
46 | #define mod_64(x, y) ((x) % (y)) | |
47 | #endif | |
48 | ||
49 | #define RW_STATE_LSB 1 | |
50 | #define RW_STATE_MSB 2 | |
51 | #define RW_STATE_WORD0 3 | |
52 | #define RW_STATE_WORD1 4 | |
53 | ||
54 | /* Compute with 96 bit intermediate result: (a*b)/c */ | |
55 | static u64 muldiv64(u64 a, u32 b, u32 c) | |
56 | { | |
57 | union { | |
58 | u64 ll; | |
59 | struct { | |
60 | u32 low, high; | |
61 | } l; | |
62 | } u, res; | |
63 | u64 rl, rh; | |
64 | ||
65 | u.ll = a; | |
66 | rl = (u64)u.l.low * (u64)b; | |
67 | rh = (u64)u.l.high * (u64)b; | |
68 | rh += (rl >> 32); | |
6f6d6a1a RZ |
69 | res.l.high = div64_u64(rh, c); |
70 | res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c); | |
7837699f SY |
71 | return res.ll; |
72 | } | |
73 | ||
74 | static void pit_set_gate(struct kvm *kvm, int channel, u32 val) | |
75 | { | |
76 | struct kvm_kpit_channel_state *c = | |
77 | &kvm->arch.vpit->pit_state.channels[channel]; | |
78 | ||
79 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
80 | ||
81 | switch (c->mode) { | |
82 | default: | |
83 | case 0: | |
84 | case 4: | |
85 | /* XXX: just disable/enable counting */ | |
86 | break; | |
87 | case 1: | |
88 | case 2: | |
89 | case 3: | |
90 | case 5: | |
91 | /* Restart counting on rising edge. */ | |
92 | if (c->gate < val) | |
93 | c->count_load_time = ktime_get(); | |
94 | break; | |
95 | } | |
96 | ||
97 | c->gate = val; | |
98 | } | |
99 | ||
8b2cf73c | 100 | static int pit_get_gate(struct kvm *kvm, int channel) |
7837699f SY |
101 | { |
102 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
103 | ||
104 | return kvm->arch.vpit->pit_state.channels[channel].gate; | |
105 | } | |
106 | ||
fd668423 MT |
107 | static s64 __kpit_elapsed(struct kvm *kvm) |
108 | { | |
109 | s64 elapsed; | |
110 | ktime_t remaining; | |
111 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; | |
112 | ||
26ef1924 | 113 | if (!ps->period) |
0ff77873 MT |
114 | return 0; |
115 | ||
ede2ccc5 MT |
116 | /* |
117 | * The Counter does not stop when it reaches zero. In | |
118 | * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to | |
119 | * the highest count, either FFFF hex for binary counting | |
120 | * or 9999 for BCD counting, and continues counting. | |
121 | * Modes 2 and 3 are periodic; the Counter reloads | |
122 | * itself with the initial count and continues counting | |
123 | * from there. | |
124 | */ | |
26ef1924 AK |
125 | remaining = hrtimer_get_remaining(&ps->timer); |
126 | elapsed = ps->period - ktime_to_ns(remaining); | |
fd668423 MT |
127 | |
128 | return elapsed; | |
129 | } | |
130 | ||
131 | static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c, | |
132 | int channel) | |
133 | { | |
134 | if (channel == 0) | |
135 | return __kpit_elapsed(kvm); | |
136 | ||
137 | return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time)); | |
138 | } | |
139 | ||
7837699f SY |
140 | static int pit_get_count(struct kvm *kvm, int channel) |
141 | { | |
142 | struct kvm_kpit_channel_state *c = | |
143 | &kvm->arch.vpit->pit_state.channels[channel]; | |
144 | s64 d, t; | |
145 | int counter; | |
146 | ||
147 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
148 | ||
fd668423 | 149 | t = kpit_elapsed(kvm, c, channel); |
7837699f SY |
150 | d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC); |
151 | ||
152 | switch (c->mode) { | |
153 | case 0: | |
154 | case 1: | |
155 | case 4: | |
156 | case 5: | |
157 | counter = (c->count - d) & 0xffff; | |
158 | break; | |
159 | case 3: | |
160 | /* XXX: may be incorrect for odd counts */ | |
161 | counter = c->count - (mod_64((2 * d), c->count)); | |
162 | break; | |
163 | default: | |
164 | counter = c->count - mod_64(d, c->count); | |
165 | break; | |
166 | } | |
167 | return counter; | |
168 | } | |
169 | ||
170 | static int pit_get_out(struct kvm *kvm, int channel) | |
171 | { | |
172 | struct kvm_kpit_channel_state *c = | |
173 | &kvm->arch.vpit->pit_state.channels[channel]; | |
174 | s64 d, t; | |
175 | int out; | |
176 | ||
177 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
178 | ||
fd668423 | 179 | t = kpit_elapsed(kvm, c, channel); |
7837699f SY |
180 | d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC); |
181 | ||
182 | switch (c->mode) { | |
183 | default: | |
184 | case 0: | |
185 | out = (d >= c->count); | |
186 | break; | |
187 | case 1: | |
188 | out = (d < c->count); | |
189 | break; | |
190 | case 2: | |
191 | out = ((mod_64(d, c->count) == 0) && (d != 0)); | |
192 | break; | |
193 | case 3: | |
194 | out = (mod_64(d, c->count) < ((c->count + 1) >> 1)); | |
195 | break; | |
196 | case 4: | |
197 | case 5: | |
198 | out = (d == c->count); | |
199 | break; | |
200 | } | |
201 | ||
202 | return out; | |
203 | } | |
204 | ||
205 | static void pit_latch_count(struct kvm *kvm, int channel) | |
206 | { | |
207 | struct kvm_kpit_channel_state *c = | |
208 | &kvm->arch.vpit->pit_state.channels[channel]; | |
209 | ||
210 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
211 | ||
212 | if (!c->count_latched) { | |
213 | c->latched_count = pit_get_count(kvm, channel); | |
214 | c->count_latched = c->rw_mode; | |
215 | } | |
216 | } | |
217 | ||
218 | static void pit_latch_status(struct kvm *kvm, int channel) | |
219 | { | |
220 | struct kvm_kpit_channel_state *c = | |
221 | &kvm->arch.vpit->pit_state.channels[channel]; | |
222 | ||
223 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
224 | ||
225 | if (!c->status_latched) { | |
226 | /* TODO: Return NULL COUNT (bit 6). */ | |
227 | c->status = ((pit_get_out(kvm, channel) << 7) | | |
228 | (c->rw_mode << 4) | | |
229 | (c->mode << 1) | | |
230 | c->bcd); | |
231 | c->status_latched = 1; | |
232 | } | |
233 | } | |
234 | ||
ee032c99 | 235 | static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian) |
3cf57fed MT |
236 | { |
237 | struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state, | |
238 | irq_ack_notifier); | |
33572ac0 CL |
239 | int value; |
240 | ||
241 | spin_lock(&ps->inject_lock); | |
26ef1924 | 242 | value = atomic_dec_return(&ps->pending); |
33572ac0 CL |
243 | if (value < 0) |
244 | /* spurious acks can be generated if, for example, the | |
245 | * PIC is being reset. Handle it gracefully here | |
246 | */ | |
26ef1924 | 247 | atomic_inc(&ps->pending); |
33572ac0 CL |
248 | else if (value > 0) |
249 | /* in this case, we had multiple outstanding pit interrupts | |
250 | * that we needed to inject. Reinject | |
251 | */ | |
b6ddf05f | 252 | queue_kthread_work(&ps->pit->worker, &ps->pit->expired); |
3cf57fed | 253 | ps->irq_ack = 1; |
33572ac0 | 254 | spin_unlock(&ps->inject_lock); |
3cf57fed MT |
255 | } |
256 | ||
2f599714 MT |
257 | void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu) |
258 | { | |
259 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
260 | struct hrtimer *timer; | |
261 | ||
c5af89b6 | 262 | if (!kvm_vcpu_is_bsp(vcpu) || !pit) |
2f599714 MT |
263 | return; |
264 | ||
26ef1924 | 265 | timer = &pit->pit_state.timer; |
2febc839 | 266 | mutex_lock(&pit->pit_state.lock); |
2f599714 | 267 | if (hrtimer_cancel(timer)) |
beb20d52 | 268 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
2febc839 | 269 | mutex_unlock(&pit->pit_state.lock); |
2f599714 MT |
270 | } |
271 | ||
33572ac0 | 272 | static void destroy_pit_timer(struct kvm_pit *pit) |
7837699f | 273 | { |
26ef1924 | 274 | hrtimer_cancel(&pit->pit_state.timer); |
b6ddf05f | 275 | flush_kthread_work(&pit->expired); |
7837699f SY |
276 | } |
277 | ||
b6ddf05f | 278 | static void pit_do_work(struct kthread_work *work) |
33572ac0 CL |
279 | { |
280 | struct kvm_pit *pit = container_of(work, struct kvm_pit, expired); | |
281 | struct kvm *kvm = pit->kvm; | |
282 | struct kvm_vcpu *vcpu; | |
283 | int i; | |
284 | struct kvm_kpit_state *ps = &pit->pit_state; | |
285 | int inject = 0; | |
286 | ||
287 | /* Try to inject pending interrupts when | |
288 | * last one has been acked. | |
289 | */ | |
290 | spin_lock(&ps->inject_lock); | |
291 | if (ps->irq_ack) { | |
292 | ps->irq_ack = 0; | |
293 | inject = 1; | |
294 | } | |
295 | spin_unlock(&ps->inject_lock); | |
296 | if (inject) { | |
aa2fbe6d YZ |
297 | kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1, false); |
298 | kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0, false); | |
33572ac0 CL |
299 | |
300 | /* | |
301 | * Provides NMI watchdog support via Virtual Wire mode. | |
302 | * The route is: PIT -> PIC -> LVT0 in NMI mode. | |
303 | * | |
304 | * Note: Our Virtual Wire implementation is simplified, only | |
305 | * propagating PIT interrupts to all VCPUs when they have set | |
306 | * LVT0 to NMI delivery. Other PIC interrupts are just sent to | |
307 | * VCPU0, and only if its LVT0 is in EXTINT mode. | |
308 | */ | |
42720138 | 309 | if (atomic_read(&kvm->arch.vapics_in_nmi_mode) > 0) |
33572ac0 CL |
310 | kvm_for_each_vcpu(i, vcpu, kvm) |
311 | kvm_apic_nmi_wd_deliver(vcpu); | |
312 | } | |
313 | } | |
314 | ||
315 | static enum hrtimer_restart pit_timer_fn(struct hrtimer *data) | |
316 | { | |
26ef1924 AK |
317 | struct kvm_kpit_state *ps = container_of(data, struct kvm_kpit_state, timer); |
318 | struct kvm_pit *pt = ps->kvm->arch.vpit; | |
33572ac0 | 319 | |
26ef1924 AK |
320 | if (ps->reinject || !atomic_read(&ps->pending)) { |
321 | atomic_inc(&ps->pending); | |
b6ddf05f | 322 | queue_kthread_work(&pt->worker, &pt->expired); |
33572ac0 CL |
323 | } |
324 | ||
26ef1924 AK |
325 | if (ps->is_periodic) { |
326 | hrtimer_add_expires_ns(&ps->timer, ps->period); | |
33572ac0 CL |
327 | return HRTIMER_RESTART; |
328 | } else | |
329 | return HRTIMER_NORESTART; | |
330 | } | |
331 | ||
0924ab2c | 332 | static void create_pit_timer(struct kvm *kvm, u32 val, int is_period) |
7837699f | 333 | { |
0924ab2c | 334 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; |
7837699f SY |
335 | s64 interval; |
336 | ||
49df6397 SR |
337 | if (!ioapic_in_kernel(kvm) || |
338 | ps->flags & KVM_PIT_FLAGS_HPET_LEGACY) | |
0924ab2c JK |
339 | return; |
340 | ||
7837699f SY |
341 | interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ); |
342 | ||
a78d9626 | 343 | pr_debug("create pit timer, interval is %llu nsec\n", interval); |
7837699f SY |
344 | |
345 | /* TODO The new value only affected after the retriggered */ | |
26ef1924 | 346 | hrtimer_cancel(&ps->timer); |
b6ddf05f | 347 | flush_kthread_work(&ps->pit->expired); |
26ef1924 | 348 | ps->period = interval; |
d3c7b77d MT |
349 | ps->is_periodic = is_period; |
350 | ||
26ef1924 AK |
351 | ps->timer.function = pit_timer_fn; |
352 | ps->kvm = ps->pit->kvm; | |
d3c7b77d | 353 | |
26ef1924 | 354 | atomic_set(&ps->pending, 0); |
3cf57fed | 355 | ps->irq_ack = 1; |
7837699f | 356 | |
9ed96e87 MT |
357 | /* |
358 | * Do not allow the guest to program periodic timers with small | |
359 | * interval, since the hrtimers are not throttled by the host | |
360 | * scheduler. | |
361 | */ | |
362 | if (ps->is_periodic) { | |
363 | s64 min_period = min_timer_period_us * 1000LL; | |
364 | ||
365 | if (ps->period < min_period) { | |
366 | pr_info_ratelimited( | |
367 | "kvm: requested %lld ns " | |
368 | "i8254 timer period limited to %lld ns\n", | |
369 | ps->period, min_period); | |
370 | ps->period = min_period; | |
371 | } | |
372 | } | |
373 | ||
26ef1924 | 374 | hrtimer_start(&ps->timer, ktime_add_ns(ktime_get(), interval), |
7837699f SY |
375 | HRTIMER_MODE_ABS); |
376 | } | |
377 | ||
378 | static void pit_load_count(struct kvm *kvm, int channel, u32 val) | |
379 | { | |
380 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; | |
381 | ||
382 | WARN_ON(!mutex_is_locked(&ps->lock)); | |
383 | ||
a78d9626 | 384 | pr_debug("load_count val is %d, channel is %d\n", val, channel); |
7837699f SY |
385 | |
386 | /* | |
ede2ccc5 MT |
387 | * The largest possible initial count is 0; this is equivalent |
388 | * to 216 for binary counting and 104 for BCD counting. | |
7837699f SY |
389 | */ |
390 | if (val == 0) | |
391 | val = 0x10000; | |
392 | ||
7837699f SY |
393 | ps->channels[channel].count = val; |
394 | ||
fd668423 MT |
395 | if (channel != 0) { |
396 | ps->channels[channel].count_load_time = ktime_get(); | |
7837699f | 397 | return; |
fd668423 | 398 | } |
7837699f SY |
399 | |
400 | /* Two types of timer | |
401 | * mode 1 is one shot, mode 2 is period, otherwise del timer */ | |
402 | switch (ps->channels[0].mode) { | |
ede2ccc5 | 403 | case 0: |
7837699f | 404 | case 1: |
ece15bab MT |
405 | /* FIXME: enhance mode 4 precision */ |
406 | case 4: | |
a647795e | 407 | create_pit_timer(kvm, val, 0); |
7837699f SY |
408 | break; |
409 | case 2: | |
f6975545 | 410 | case 3: |
a647795e | 411 | create_pit_timer(kvm, val, 1); |
7837699f SY |
412 | break; |
413 | default: | |
33572ac0 | 414 | destroy_pit_timer(kvm->arch.vpit); |
7837699f SY |
415 | } |
416 | } | |
417 | ||
e9f42757 | 418 | void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start) |
e0f63cb9 | 419 | { |
e9f42757 BK |
420 | u8 saved_mode; |
421 | if (hpet_legacy_start) { | |
422 | /* save existing mode for later reenablement */ | |
423 | saved_mode = kvm->arch.vpit->pit_state.channels[0].mode; | |
424 | kvm->arch.vpit->pit_state.channels[0].mode = 0xff; /* disable timer */ | |
425 | pit_load_count(kvm, channel, val); | |
426 | kvm->arch.vpit->pit_state.channels[0].mode = saved_mode; | |
427 | } else { | |
428 | pit_load_count(kvm, channel, val); | |
429 | } | |
e0f63cb9 SY |
430 | } |
431 | ||
d76685c4 GH |
432 | static inline struct kvm_pit *dev_to_pit(struct kvm_io_device *dev) |
433 | { | |
434 | return container_of(dev, struct kvm_pit, dev); | |
435 | } | |
436 | ||
437 | static inline struct kvm_pit *speaker_to_pit(struct kvm_io_device *dev) | |
438 | { | |
439 | return container_of(dev, struct kvm_pit, speaker_dev); | |
440 | } | |
441 | ||
bda9020e MT |
442 | static inline int pit_in_range(gpa_t addr) |
443 | { | |
444 | return ((addr >= KVM_PIT_BASE_ADDRESS) && | |
445 | (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH)); | |
446 | } | |
447 | ||
e32edf4f NN |
448 | static int pit_ioport_write(struct kvm_vcpu *vcpu, |
449 | struct kvm_io_device *this, | |
bda9020e | 450 | gpa_t addr, int len, const void *data) |
7837699f | 451 | { |
d76685c4 | 452 | struct kvm_pit *pit = dev_to_pit(this); |
7837699f SY |
453 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
454 | struct kvm *kvm = pit->kvm; | |
455 | int channel, access; | |
456 | struct kvm_kpit_channel_state *s; | |
457 | u32 val = *(u32 *) data; | |
bda9020e MT |
458 | if (!pit_in_range(addr)) |
459 | return -EOPNOTSUPP; | |
7837699f SY |
460 | |
461 | val &= 0xff; | |
462 | addr &= KVM_PIT_CHANNEL_MASK; | |
463 | ||
464 | mutex_lock(&pit_state->lock); | |
465 | ||
466 | if (val != 0) | |
a78d9626 JP |
467 | pr_debug("write addr is 0x%x, len is %d, val is 0x%x\n", |
468 | (unsigned int)addr, len, val); | |
7837699f SY |
469 | |
470 | if (addr == 3) { | |
471 | channel = val >> 6; | |
472 | if (channel == 3) { | |
473 | /* Read-Back Command. */ | |
474 | for (channel = 0; channel < 3; channel++) { | |
475 | s = &pit_state->channels[channel]; | |
476 | if (val & (2 << channel)) { | |
477 | if (!(val & 0x20)) | |
478 | pit_latch_count(kvm, channel); | |
479 | if (!(val & 0x10)) | |
480 | pit_latch_status(kvm, channel); | |
481 | } | |
482 | } | |
483 | } else { | |
484 | /* Select Counter <channel>. */ | |
485 | s = &pit_state->channels[channel]; | |
486 | access = (val >> 4) & KVM_PIT_CHANNEL_MASK; | |
487 | if (access == 0) { | |
488 | pit_latch_count(kvm, channel); | |
489 | } else { | |
490 | s->rw_mode = access; | |
491 | s->read_state = access; | |
492 | s->write_state = access; | |
493 | s->mode = (val >> 1) & 7; | |
494 | if (s->mode > 5) | |
495 | s->mode -= 4; | |
496 | s->bcd = val & 1; | |
497 | } | |
498 | } | |
499 | } else { | |
500 | /* Write Count. */ | |
501 | s = &pit_state->channels[addr]; | |
502 | switch (s->write_state) { | |
503 | default: | |
504 | case RW_STATE_LSB: | |
505 | pit_load_count(kvm, addr, val); | |
506 | break; | |
507 | case RW_STATE_MSB: | |
508 | pit_load_count(kvm, addr, val << 8); | |
509 | break; | |
510 | case RW_STATE_WORD0: | |
511 | s->write_latch = val; | |
512 | s->write_state = RW_STATE_WORD1; | |
513 | break; | |
514 | case RW_STATE_WORD1: | |
515 | pit_load_count(kvm, addr, s->write_latch | (val << 8)); | |
516 | s->write_state = RW_STATE_WORD0; | |
517 | break; | |
518 | } | |
519 | } | |
520 | ||
521 | mutex_unlock(&pit_state->lock); | |
bda9020e | 522 | return 0; |
7837699f SY |
523 | } |
524 | ||
e32edf4f NN |
525 | static int pit_ioport_read(struct kvm_vcpu *vcpu, |
526 | struct kvm_io_device *this, | |
bda9020e | 527 | gpa_t addr, int len, void *data) |
7837699f | 528 | { |
d76685c4 | 529 | struct kvm_pit *pit = dev_to_pit(this); |
7837699f SY |
530 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
531 | struct kvm *kvm = pit->kvm; | |
532 | int ret, count; | |
533 | struct kvm_kpit_channel_state *s; | |
bda9020e MT |
534 | if (!pit_in_range(addr)) |
535 | return -EOPNOTSUPP; | |
7837699f SY |
536 | |
537 | addr &= KVM_PIT_CHANNEL_MASK; | |
ee73f656 MT |
538 | if (addr == 3) |
539 | return 0; | |
540 | ||
7837699f SY |
541 | s = &pit_state->channels[addr]; |
542 | ||
543 | mutex_lock(&pit_state->lock); | |
544 | ||
545 | if (s->status_latched) { | |
546 | s->status_latched = 0; | |
547 | ret = s->status; | |
548 | } else if (s->count_latched) { | |
549 | switch (s->count_latched) { | |
550 | default: | |
551 | case RW_STATE_LSB: | |
552 | ret = s->latched_count & 0xff; | |
553 | s->count_latched = 0; | |
554 | break; | |
555 | case RW_STATE_MSB: | |
556 | ret = s->latched_count >> 8; | |
557 | s->count_latched = 0; | |
558 | break; | |
559 | case RW_STATE_WORD0: | |
560 | ret = s->latched_count & 0xff; | |
561 | s->count_latched = RW_STATE_MSB; | |
562 | break; | |
563 | } | |
564 | } else { | |
565 | switch (s->read_state) { | |
566 | default: | |
567 | case RW_STATE_LSB: | |
568 | count = pit_get_count(kvm, addr); | |
569 | ret = count & 0xff; | |
570 | break; | |
571 | case RW_STATE_MSB: | |
572 | count = pit_get_count(kvm, addr); | |
573 | ret = (count >> 8) & 0xff; | |
574 | break; | |
575 | case RW_STATE_WORD0: | |
576 | count = pit_get_count(kvm, addr); | |
577 | ret = count & 0xff; | |
578 | s->read_state = RW_STATE_WORD1; | |
579 | break; | |
580 | case RW_STATE_WORD1: | |
581 | count = pit_get_count(kvm, addr); | |
582 | ret = (count >> 8) & 0xff; | |
583 | s->read_state = RW_STATE_WORD0; | |
584 | break; | |
585 | } | |
586 | } | |
587 | ||
588 | if (len > sizeof(ret)) | |
589 | len = sizeof(ret); | |
590 | memcpy(data, (char *)&ret, len); | |
591 | ||
592 | mutex_unlock(&pit_state->lock); | |
bda9020e | 593 | return 0; |
7837699f SY |
594 | } |
595 | ||
e32edf4f NN |
596 | static int speaker_ioport_write(struct kvm_vcpu *vcpu, |
597 | struct kvm_io_device *this, | |
bda9020e | 598 | gpa_t addr, int len, const void *data) |
7837699f | 599 | { |
d76685c4 | 600 | struct kvm_pit *pit = speaker_to_pit(this); |
7837699f SY |
601 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
602 | struct kvm *kvm = pit->kvm; | |
603 | u32 val = *(u32 *) data; | |
bda9020e MT |
604 | if (addr != KVM_SPEAKER_BASE_ADDRESS) |
605 | return -EOPNOTSUPP; | |
7837699f SY |
606 | |
607 | mutex_lock(&pit_state->lock); | |
608 | pit_state->speaker_data_on = (val >> 1) & 1; | |
609 | pit_set_gate(kvm, 2, val & 1); | |
610 | mutex_unlock(&pit_state->lock); | |
bda9020e | 611 | return 0; |
7837699f SY |
612 | } |
613 | ||
e32edf4f NN |
614 | static int speaker_ioport_read(struct kvm_vcpu *vcpu, |
615 | struct kvm_io_device *this, | |
616 | gpa_t addr, int len, void *data) | |
7837699f | 617 | { |
d76685c4 | 618 | struct kvm_pit *pit = speaker_to_pit(this); |
7837699f SY |
619 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
620 | struct kvm *kvm = pit->kvm; | |
621 | unsigned int refresh_clock; | |
622 | int ret; | |
bda9020e MT |
623 | if (addr != KVM_SPEAKER_BASE_ADDRESS) |
624 | return -EOPNOTSUPP; | |
7837699f SY |
625 | |
626 | /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */ | |
627 | refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1; | |
628 | ||
629 | mutex_lock(&pit_state->lock); | |
630 | ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) | | |
631 | (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4)); | |
632 | if (len > sizeof(ret)) | |
633 | len = sizeof(ret); | |
634 | memcpy(data, (char *)&ret, len); | |
635 | mutex_unlock(&pit_state->lock); | |
bda9020e | 636 | return 0; |
7837699f SY |
637 | } |
638 | ||
308b0f23 | 639 | void kvm_pit_reset(struct kvm_pit *pit) |
7837699f SY |
640 | { |
641 | int i; | |
308b0f23 SY |
642 | struct kvm_kpit_channel_state *c; |
643 | ||
644 | mutex_lock(&pit->pit_state.lock); | |
e9f42757 | 645 | pit->pit_state.flags = 0; |
308b0f23 SY |
646 | for (i = 0; i < 3; i++) { |
647 | c = &pit->pit_state.channels[i]; | |
648 | c->mode = 0xff; | |
649 | c->gate = (i != 2); | |
650 | pit_load_count(pit->kvm, i, 0); | |
651 | } | |
652 | mutex_unlock(&pit->pit_state.lock); | |
653 | ||
26ef1924 | 654 | atomic_set(&pit->pit_state.pending, 0); |
3cf57fed | 655 | pit->pit_state.irq_ack = 1; |
308b0f23 SY |
656 | } |
657 | ||
4780c659 AK |
658 | static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask) |
659 | { | |
660 | struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier); | |
661 | ||
662 | if (!mask) { | |
26ef1924 | 663 | atomic_set(&pit->pit_state.pending, 0); |
4780c659 AK |
664 | pit->pit_state.irq_ack = 1; |
665 | } | |
666 | } | |
667 | ||
d76685c4 GH |
668 | static const struct kvm_io_device_ops pit_dev_ops = { |
669 | .read = pit_ioport_read, | |
670 | .write = pit_ioport_write, | |
d76685c4 GH |
671 | }; |
672 | ||
673 | static const struct kvm_io_device_ops speaker_dev_ops = { | |
674 | .read = speaker_ioport_read, | |
675 | .write = speaker_ioport_write, | |
d76685c4 GH |
676 | }; |
677 | ||
79fac95e | 678 | /* Caller must hold slots_lock */ |
c5ff41ce | 679 | struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags) |
308b0f23 | 680 | { |
7837699f SY |
681 | struct kvm_pit *pit; |
682 | struct kvm_kpit_state *pit_state; | |
b6ddf05f JK |
683 | struct pid *pid; |
684 | pid_t pid_nr; | |
090b7aff | 685 | int ret; |
7837699f SY |
686 | |
687 | pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL); | |
688 | if (!pit) | |
689 | return NULL; | |
690 | ||
5550af4d | 691 | pit->irq_source_id = kvm_request_irq_source_id(kvm); |
e17d1dc0 AK |
692 | if (pit->irq_source_id < 0) { |
693 | kfree(pit); | |
5550af4d | 694 | return NULL; |
e17d1dc0 | 695 | } |
5550af4d | 696 | |
7837699f SY |
697 | mutex_init(&pit->pit_state.lock); |
698 | mutex_lock(&pit->pit_state.lock); | |
33572ac0 CL |
699 | spin_lock_init(&pit->pit_state.inject_lock); |
700 | ||
b6ddf05f JK |
701 | pid = get_pid(task_tgid(current)); |
702 | pid_nr = pid_vnr(pid); | |
703 | put_pid(pid); | |
704 | ||
705 | init_kthread_worker(&pit->worker); | |
706 | pit->worker_task = kthread_run(kthread_worker_fn, &pit->worker, | |
707 | "kvm-pit/%d", pid_nr); | |
708 | if (IS_ERR(pit->worker_task)) { | |
673813e8 | 709 | mutex_unlock(&pit->pit_state.lock); |
6b5d7a9f | 710 | kvm_free_irq_source_id(kvm, pit->irq_source_id); |
33572ac0 CL |
711 | kfree(pit); |
712 | return NULL; | |
713 | } | |
b6ddf05f | 714 | init_kthread_work(&pit->expired, pit_do_work); |
7837699f | 715 | |
7837699f SY |
716 | kvm->arch.vpit = pit; |
717 | pit->kvm = kvm; | |
718 | ||
719 | pit_state = &pit->pit_state; | |
720 | pit_state->pit = pit; | |
26ef1924 | 721 | hrtimer_init(&pit_state->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); |
3cf57fed MT |
722 | pit_state->irq_ack_notifier.gsi = 0; |
723 | pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq; | |
724 | kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier); | |
26ef1924 | 725 | pit_state->reinject = true; |
7837699f SY |
726 | mutex_unlock(&pit->pit_state.lock); |
727 | ||
308b0f23 | 728 | kvm_pit_reset(pit); |
7837699f | 729 | |
4780c659 AK |
730 | pit->mask_notifier.func = pit_mask_notifer; |
731 | kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier); | |
732 | ||
6b66ac1a | 733 | kvm_iodevice_init(&pit->dev, &pit_dev_ops); |
743eeb0b SL |
734 | ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, KVM_PIT_BASE_ADDRESS, |
735 | KVM_PIT_MEM_LENGTH, &pit->dev); | |
090b7aff GH |
736 | if (ret < 0) |
737 | goto fail; | |
6b66ac1a GH |
738 | |
739 | if (flags & KVM_PIT_SPEAKER_DUMMY) { | |
740 | kvm_iodevice_init(&pit->speaker_dev, &speaker_dev_ops); | |
e93f8a0f | 741 | ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, |
743eeb0b SL |
742 | KVM_SPEAKER_BASE_ADDRESS, 4, |
743 | &pit->speaker_dev); | |
090b7aff GH |
744 | if (ret < 0) |
745 | goto fail_unregister; | |
6b66ac1a GH |
746 | } |
747 | ||
7837699f | 748 | return pit; |
090b7aff GH |
749 | |
750 | fail_unregister: | |
e93f8a0f | 751 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &pit->dev); |
090b7aff GH |
752 | |
753 | fail: | |
d225f53b WY |
754 | kvm_unregister_irq_mask_notifier(kvm, 0, &pit->mask_notifier); |
755 | kvm_unregister_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier); | |
756 | kvm_free_irq_source_id(kvm, pit->irq_source_id); | |
b6ddf05f | 757 | kthread_stop(pit->worker_task); |
090b7aff GH |
758 | kfree(pit); |
759 | return NULL; | |
7837699f SY |
760 | } |
761 | ||
762 | void kvm_free_pit(struct kvm *kvm) | |
763 | { | |
764 | struct hrtimer *timer; | |
765 | ||
766 | if (kvm->arch.vpit) { | |
aea924f6 XG |
767 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &kvm->arch.vpit->dev); |
768 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, | |
769 | &kvm->arch.vpit->speaker_dev); | |
4780c659 AK |
770 | kvm_unregister_irq_mask_notifier(kvm, 0, |
771 | &kvm->arch.vpit->mask_notifier); | |
84fde248 GN |
772 | kvm_unregister_irq_ack_notifier(kvm, |
773 | &kvm->arch.vpit->pit_state.irq_ack_notifier); | |
7837699f | 774 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
26ef1924 | 775 | timer = &kvm->arch.vpit->pit_state.timer; |
7837699f | 776 | hrtimer_cancel(timer); |
b6ddf05f JK |
777 | flush_kthread_work(&kvm->arch.vpit->expired); |
778 | kthread_stop(kvm->arch.vpit->worker_task); | |
5550af4d | 779 | kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id); |
7837699f SY |
780 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
781 | kfree(kvm->arch.vpit); | |
782 | } | |
783 | } |