[deliverable/linux.git] / arch / x86 / kvm / i8254.c

/*
 * 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2006 Intel Corporation
 * Copyright (c) 2007 Keir Fraser, XenSource Inc
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 * Authors:
 *   Sheng Yang <sheng.yang@intel.com>
 *   Based on QEMU and Xen.
 */

#include <linux/kvm_host.h>

#include "irq.h"
#include "i8254.h"

#ifndef CONFIG_X86_64
#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
#else
#define mod_64(x, y) ((x) % (y))
#endif

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

/* Compute with 96 bit intermediate result: (a*b)/c */
static u64 muldiv64(u64 a, u32 b, u32 c)
{
	union {
		u64 ll;
		struct {
			u32 low, high;
		} l;
	} u, res;
	u64 rl, rh;

	u.ll = a;
	rl = (u64)u.l.low * (u64)b;
	rh = (u64)u.l.high * (u64)b;
	rh += (rl >> 32);
	res.l.high = div64_u64(rh, c);
	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
	return res.ll;
}

static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	switch (c->mode) {
	default:
	case 0:
	case 4:
		/* XXX: just disable/enable counting */
		break;
	case 1:
	case 2:
	case 3:
	case 5:
		/* Restart counting on rising edge. */
		if (c->gate < val)
			c->count_load_time = ktime_get();
		break;
	}

	c->gate = val;
}

static int pit_get_gate(struct kvm *kvm, int channel)
{
	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	return kvm->arch.vpit->pit_state.channels[channel].gate;
}

static int pit_get_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int counter;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	case 0:
	case 1:
	case 4:
	case 5:
		counter = (c->count - d) & 0xffff;
		break;
	case 3:
		/* XXX: may be incorrect for odd counts */
		counter = c->count - (mod_64((2 * d), c->count));
		break;
	default:
		counter = c->count - mod_64(d, c->count);
		break;
	}
	return counter;
}

static int pit_get_out(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];
	s64 d, t;
	int out;

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);

	switch (c->mode) {
	default:
	case 0:
		out = (d >= c->count);
		break;
	case 1:
		out = (d < c->count);
		break;
	case 2:
		out = ((mod_64(d, c->count) == 0) && (d != 0));
		break;
	case 3:
		out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
		break;
	case 4:
	case 5:
		out = (d == c->count);
		break;
	}

	return out;
}

static void pit_latch_count(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->count_latched) {
		c->latched_count = pit_get_count(kvm, channel);
		c->count_latched = c->rw_mode;
	}
}

static void pit_latch_status(struct kvm *kvm, int channel)
{
	struct kvm_kpit_channel_state *c =
		&kvm->arch.vpit->pit_state.channels[channel];

	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));

	if (!c->status_latched) {
		/* TODO: Return NULL COUNT (bit 6). */
		c->status = ((pit_get_out(kvm, channel) << 7) |
				(c->rw_mode << 4) |
				(c->mode << 1) |
				c->bcd);
		c->status_latched = 1;
	}
}

static int __pit_timer_fn(struct kvm_kpit_state *ps)
{
	struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
	struct kvm_kpit_timer *pt = &ps->pit_timer;

	if (!atomic_inc_and_test(&pt->pending))
		set_bit(KVM_REQ_PENDING_TIMER, &vcpu0->requests);

	if (!pt->reinject)
		atomic_set(&pt->pending, 1);

	if (vcpu0 && waitqueue_active(&vcpu0->wq))
		wake_up_interruptible(&vcpu0->wq);

	hrtimer_add_expires_ns(&pt->timer, pt->period);
	pt->scheduled = hrtimer_get_expires_ns(&pt->timer);
	if (pt->period)
		ps->channels[0].count_load_time = ktime_get();

	return (pt->period == 0 ? 0 : 1);
}

int pit_has_pending_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;

	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
		return atomic_read(&pit->pit_state.pit_timer.pending);
	return 0;
}

static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
{
	struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
						 irq_ack_notifier);
	spin_lock(&ps->inject_lock);
	if (atomic_dec_return(&ps->pit_timer.pending) < 0)
		atomic_inc(&ps->pit_timer.pending);
	ps->irq_ack = 1;
	spin_unlock(&ps->inject_lock);
}

static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
{
	struct kvm_kpit_state *ps;
	int restart_timer = 0;

	ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);

	restart_timer = __pit_timer_fn(ps);

	if (restart_timer)
		return HRTIMER_RESTART;
	else
		return HRTIMER_NORESTART;
}

void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct hrtimer *timer;

	if (vcpu->vcpu_id != 0 || !pit)
		return;

	timer = &pit->pit_state.pit_timer.timer;
	if (hrtimer_cancel(timer))
		hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
}

static void destroy_pit_timer(struct kvm_kpit_timer *pt)
{
	pr_debug("pit: execute del timer!\n");
	hrtimer_cancel(&pt->timer);
}

static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
{
	struct kvm_kpit_timer *pt = &ps->pit_timer;
	s64 interval;

	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);

	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);

	/* TODO The new value only affected after the retriggered */
	hrtimer_cancel(&pt->timer);
	pt->period = (is_period == 0) ? 0 : interval;
	pt->timer.function = pit_timer_fn;
	atomic_set(&pt->pending, 0);
	ps->irq_ack = 1;

	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
		      HRTIMER_MODE_ABS);
}

static void pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;

	WARN_ON(!mutex_is_locked(&ps->lock));

	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);

	/*
	 * Though spec said the state of 8254 is undefined after power-up,
	 * seems some tricky OS like Windows XP depends on IRQ0 interrupt
	 * when booting up.
	 * So here setting initialize rate for it, and not a specific number
	 */
	if (val == 0)
		val = 0x10000;

	ps->channels[channel].count_load_time = ktime_get();
	ps->channels[channel].count = val;

	if (channel != 0)
		return;

	/* Two types of timer
	 * mode 1 is one shot, mode 2 is period, otherwise del timer */
	switch (ps->channels[0].mode) {
	case 1:
        /* FIXME: enhance mode 4 precision */
	case 4:
		create_pit_timer(ps, val, 0);
		break;
	case 2:
	case 3:
		create_pit_timer(ps, val, 1);
		break;
	default:
		destroy_pit_timer(&ps->pit_timer);
	}
}

void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
{
	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	pit_load_count(kvm, channel, val);
	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
}

static void pit_ioport_write(struct kvm_io_device *this,
			     gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int channel, access;
	struct kvm_kpit_channel_state *s;
	u32 val = *(u32 *) data;

	val  &= 0xff;
	addr &= KVM_PIT_CHANNEL_MASK;

	mutex_lock(&pit_state->lock);

	if (val != 0)
		pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
			  (unsigned int)addr, len, val);

	if (addr == 3) {
		channel = val >> 6;
		if (channel == 3) {
			/* Read-Back Command. */
			for (channel = 0; channel < 3; channel++) {
				s = &pit_state->channels[channel];
				if (val & (2 << channel)) {
					if (!(val & 0x20))
						pit_latch_count(kvm, channel);
					if (!(val & 0x10))
						pit_latch_status(kvm, channel);
				}
			}
		} else {
			/* Select Counter <channel>. */
			s = &pit_state->channels[channel];
			access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
			if (access == 0) {
				pit_latch_count(kvm, channel);
			} else {
				s->rw_mode = access;
				s->read_state = access;
				s->write_state = access;
				s->mode = (val >> 1) & 7;
				if (s->mode > 5)
					s->mode -= 4;
				s->bcd = val & 1;
			}
		}
	} else {
		/* Write Count. */
		s = &pit_state->channels[addr];
		switch (s->write_state) {
		default:
		case RW_STATE_LSB:
			pit_load_count(kvm, addr, val);
			break;
		case RW_STATE_MSB:
			pit_load_count(kvm, addr, val << 8);
			break;
		case RW_STATE_WORD0:
			s->write_latch = val;
			s->write_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			pit_load_count(kvm, addr, s->write_latch | (val << 8));
			s->write_state = RW_STATE_WORD0;
			break;
		}
	}

	mutex_unlock(&pit_state->lock);
}

static void pit_ioport_read(struct kvm_io_device *this,
			    gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	int ret, count;
	struct kvm_kpit_channel_state *s;

	addr &= KVM_PIT_CHANNEL_MASK;
	s = &pit_state->channels[addr];

	mutex_lock(&pit_state->lock);

	if (s->status_latched) {
		s->status_latched = 0;
		ret = s->status;
	} else if (s->count_latched) {
		switch (s->count_latched) {
		default:
		case RW_STATE_LSB:
			ret = s->latched_count & 0xff;
			s->count_latched = 0;
			break;
		case RW_STATE_MSB:
			ret = s->latched_count >> 8;
			s->count_latched = 0;
			break;
		case RW_STATE_WORD0:
			ret = s->latched_count & 0xff;
			s->count_latched = RW_STATE_MSB;
			break;
		}
	} else {
		switch (s->read_state) {
		default:
		case RW_STATE_LSB:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			break;
		case RW_STATE_MSB:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			break;
		case RW_STATE_WORD0:
			count = pit_get_count(kvm, addr);
			ret = count & 0xff;
			s->read_state = RW_STATE_WORD1;
			break;
		case RW_STATE_WORD1:
			count = pit_get_count(kvm, addr);
			ret = (count >> 8) & 0xff;
			s->read_state = RW_STATE_WORD0;
			break;
		}
	}

	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);

	mutex_unlock(&pit_state->lock);
}

static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
			int len, int is_write)
{
	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
		(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
}

static void speaker_ioport_write(struct kvm_io_device *this,
				 gpa_t addr, int len, const void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	u32 val = *(u32 *) data;

	mutex_lock(&pit_state->lock);
	pit_state->speaker_data_on = (val >> 1) & 1;
	pit_set_gate(kvm, 2, val & 1);
	mutex_unlock(&pit_state->lock);
}

static void speaker_ioport_read(struct kvm_io_device *this,
				gpa_t addr, int len, void *data)
{
	struct kvm_pit *pit = (struct kvm_pit *)this->private;
	struct kvm_kpit_state *pit_state = &pit->pit_state;
	struct kvm *kvm = pit->kvm;
	unsigned int refresh_clock;
	int ret;

	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;

	mutex_lock(&pit_state->lock);
	ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
		(pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
	if (len > sizeof(ret))
		len = sizeof(ret);
	memcpy(data, (char *)&ret, len);
	mutex_unlock(&pit_state->lock);
}

static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
			    int len, int is_write)
{
	return (addr == KVM_SPEAKER_BASE_ADDRESS);
}

void kvm_pit_reset(struct kvm_pit *pit)
{
	int i;
	struct kvm_kpit_channel_state *c;

	mutex_lock(&pit->pit_state.lock);
	for (i = 0; i < 3; i++) {
		c = &pit->pit_state.channels[i];
		c->mode = 0xff;
		c->gate = (i != 2);
		pit_load_count(pit->kvm, i, 0);
	}
	mutex_unlock(&pit->pit_state.lock);

	atomic_set(&pit->pit_state.pit_timer.pending, 0);
	pit->pit_state.irq_ack = 1;
}

struct kvm_pit *kvm_create_pit(struct kvm *kvm)
{
	struct kvm_pit *pit;
	struct kvm_kpit_state *pit_state;

	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	if (!pit)
		return NULL;

	pit->irq_source_id = kvm_request_irq_source_id(kvm);
	if (pit->irq_source_id < 0) {
		kfree(pit);
		return NULL;
	}

	mutex_init(&pit->pit_state.lock);
	mutex_lock(&pit->pit_state.lock);
	spin_lock_init(&pit->pit_state.inject_lock);

	/* Initialize PIO device */
	pit->dev.read = pit_ioport_read;
	pit->dev.write = pit_ioport_write;
	pit->dev.in_range = pit_in_range;
	pit->dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);

	pit->speaker_dev.read = speaker_ioport_read;
	pit->speaker_dev.write = speaker_ioport_write;
	pit->speaker_dev.in_range = speaker_in_range;
	pit->speaker_dev.private = pit;
	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);

	kvm->arch.vpit = pit;
	pit->kvm = kvm;

	pit_state = &pit->pit_state;
	pit_state->pit = pit;
	hrtimer_init(&pit_state->pit_timer.timer,
		     CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	pit_state->irq_ack_notifier.gsi = 0;
	pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
	kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
	pit_state->pit_timer.reinject = true;
	mutex_unlock(&pit->pit_state.lock);

	kvm_pit_reset(pit);

	return pit;
}

void kvm_free_pit(struct kvm *kvm)
{
	struct hrtimer *timer;

	if (kvm->arch.vpit) {
		mutex_lock(&kvm->arch.vpit->pit_state.lock);
		timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
		hrtimer_cancel(timer);
		kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
		mutex_unlock(&kvm->arch.vpit->pit_state.lock);
		kfree(kvm->arch.vpit);
	}
}

static void __inject_pit_timer_intr(struct kvm *kvm)
{
	struct kvm_vcpu *vcpu;
	int i;

	mutex_lock(&kvm->lock);
	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
	mutex_unlock(&kvm->lock);

	/*
	 * Provides NMI watchdog support via Virtual Wire mode.
	 * The route is: PIT -> PIC -> LVT0 in NMI mode.
	 *
	 * Note: Our Virtual Wire implementation is simplified, only
	 * propagating PIT interrupts to all VCPUs when they have set
	 * LVT0 to NMI delivery. Other PIC interrupts are just sent to
	 * VCPU0, and only if its LVT0 is in EXTINT mode.
	 */
	if (kvm->arch.vapics_in_nmi_mode > 0)
		for (i = 0; i < KVM_MAX_VCPUS; ++i) {
			vcpu = kvm->vcpus[i];
			if (vcpu)
				kvm_apic_nmi_wd_deliver(vcpu);
		}
}

void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
{
	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	struct kvm *kvm = vcpu->kvm;
	struct kvm_kpit_state *ps;

	if (vcpu && pit) {
		int inject = 0;
		ps = &pit->pit_state;

		/* Try to inject pending interrupts when
		 * last one has been acked.
		 */
		spin_lock(&ps->inject_lock);
		if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
			ps->irq_ack = 0;
			inject = 1;
		}
		spin_unlock(&ps->inject_lock);
		if (inject)
			__inject_pit_timer_intr(kvm);
	}
}
Commit	Line	Data
7837699f SY	1	/*
	2	* 8253/8254 interval timer emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2006 Intel Corporation
	6	* Copyright (c) 2007 Keir Fraser, XenSource Inc
	7	* Copyright (c) 2008 Intel Corporation
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*
	27	* Authors:
	28	* Sheng Yang <sheng.yang@intel.com>
	29	* Based on QEMU and Xen.
	30	*/
	31
	32	#include <linux/kvm_host.h>
	33
	34	#include "irq.h"
	35	#include "i8254.h"
	36
	37	#ifndef CONFIG_X86_64
6f6d6a1a	38	#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
7837699f SY	39	#else
	40	#define mod_64(x, y) ((x) % (y))
	41	#endif
	42
	43	#define RW_STATE_LSB 1
	44	#define RW_STATE_MSB 2
	45	#define RW_STATE_WORD0 3
	46	#define RW_STATE_WORD1 4
	47
	48	/* Compute with 96 bit intermediate result: (ab)/c /
	49	static u64 muldiv64(u64 a, u32 b, u32 c)
	50	{
	51	union {
	52	u64 ll;
	53	struct {
	54	u32 low, high;
	55	} l;
	56	} u, res;
	57	u64 rl, rh;
	58
	59	u.ll = a;
	60	rl = (u64)u.l.low * (u64)b;
	61	rh = (u64)u.l.high * (u64)b;
	62	rh += (rl >> 32);
6f6d6a1a RZ	63	res.l.high = div64_u64(rh, c);
6f6d6a1a RZ	64	res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
7837699f SY	65	return res.ll;
	66	}
	67
	68	static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
	69	{
	70	struct kvm_kpit_channel_state *c =
	71	&kvm->arch.vpit->pit_state.channels[channel];
	72
	73	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	74
	75	switch (c->mode) {
	76	default:
	77	case 0:
	78	case 4:
	79	/* XXX: just disable/enable counting */
	80	break;
	81	case 1:
	82	case 2:
	83	case 3:
	84	case 5:
	85	/* Restart counting on rising edge. */
	86	if (c->gate < val)
	87	c->count_load_time = ktime_get();
	88	break;
	89	}
	90
	91	c->gate = val;
	92	}
	93
8b2cf73c	94	static int pit_get_gate(struct kvm *kvm, int channel)
7837699f SY	95	{
	96	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	97
	98	return kvm->arch.vpit->pit_state.channels[channel].gate;
	99	}
	100
	101	static int pit_get_count(struct kvm *kvm, int channel)
	102	{
	103	struct kvm_kpit_channel_state *c =
	104	&kvm->arch.vpit->pit_state.channels[channel];
	105	s64 d, t;
	106	int counter;
	107
	108	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	109
	110	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	111	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	112
	113	switch (c->mode) {
	114	case 0:
	115	case 1:
	116	case 4:
	117	case 5:
	118	counter = (c->count - d) & 0xffff;
	119	break;
	120	case 3:
	121	/* XXX: may be incorrect for odd counts */
	122	counter = c->count - (mod_64((2 * d), c->count));
	123	break;
	124	default:
	125	counter = c->count - mod_64(d, c->count);
	126	break;
	127	}
	128	return counter;
	129	}
	130
	131	static int pit_get_out(struct kvm *kvm, int channel)
	132	{
	133	struct kvm_kpit_channel_state *c =
	134	&kvm->arch.vpit->pit_state.channels[channel];
	135	s64 d, t;
	136	int out;
	137
	138	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
	139
	140	t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
	141	d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
	142
	143	switch (c->mode) {
	144	default:
	145	case 0:
	146	out = (d >= c->count);
	147	break;
	148	case 1:
	149	out = (d < c->count);
	150	break;
	151	case 2:
	152	out = ((mod_64(d, c->count) == 0) && (d != 0));
	153	break;
	154	case 3:
	155	out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
	156	break;
	157	case 4:
	158	case 5:
159	out = (d == c->count);
160	break;
161	}
162
163	return out;
164	}
165
166	static void pit_latch_count(struct kvm *kvm, int channel)
167	{
168	struct kvm_kpit_channel_state *c =
169	&kvm->arch.vpit->pit_state.channels[channel];
170
171	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
172
173	if (!c->count_latched) {
174	c->latched_count = pit_get_count(kvm, channel);
175	c->count_latched = c->rw_mode;
176	}
177	}
178
179	static void pit_latch_status(struct kvm *kvm, int channel)
180	{
181	struct kvm_kpit_channel_state *c =
182	&kvm->arch.vpit->pit_state.channels[channel];
183
184	WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
185
186	if (!c->status_latched) {
187	/* TODO: Return NULL COUNT (bit 6). */
188	c->status = ((pit_get_out(kvm, channel) << 7) \|
189	(c->rw_mode << 4) \|
190	(c->mode << 1) \|
191	c->bcd);
192	c->status_latched = 1;
193	}
194	}
195
8b2cf73c	196	static int __pit_timer_fn(struct kvm_kpit_state *ps)
7837699f SY	197	{
	198	struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
	199	struct kvm_kpit_timer *pt = &ps->pit_timer;
	200
622395a9	201	if (!atomic_inc_and_test(&pt->pending))
06e05645	202	set_bit(KVM_REQ_PENDING_TIMER, &vcpu0->requests);
d7690175	203
52d939a0 MT	204	if (!pt->reinject)
	205	atomic_set(&pt->pending, 1);
	206
d7690175	207	if (vcpu0 && waitqueue_active(&vcpu0->wq))
622395a9	208	wake_up_interruptible(&vcpu0->wq);
7837699f	209
beb20d52	210	hrtimer_add_expires_ns(&pt->timer, pt->period);
651dab42	211	pt->scheduled = hrtimer_get_expires_ns(&pt->timer);
3cf57fed	212	if (pt->period)
d2a8284e	213	ps->channels[0].count_load_time = ktime_get();
7837699f SY	214
	215	return (pt->period == 0 ? 0 : 1);
	216	}
	217
3d80840d MT	218	int pit_has_pending_timer(struct kvm_vcpu *vcpu)
	219	{
	220	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	221
3cf57fed	222	if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
3d80840d	223	return atomic_read(&pit->pit_state.pit_timer.pending);
3d80840d MT	224	return 0;
	225	}
	226
ee032c99	227	static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
3cf57fed MT	228	{
	229	struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
	230	irq_ack_notifier);
	231	spin_lock(&ps->inject_lock);
	232	if (atomic_dec_return(&ps->pit_timer.pending) < 0)
dc7404ce	233	atomic_inc(&ps->pit_timer.pending);
3cf57fed MT	234	ps->irq_ack = 1;
	235	spin_unlock(&ps->inject_lock);
	236	}
	237
7837699f SY	238	static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
	239	{
	240	struct kvm_kpit_state *ps;
	241	int restart_timer = 0;
	242
	243	ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);
	244
	245	restart_timer = __pit_timer_fn(ps);
	246
	247	if (restart_timer)
	248	return HRTIMER_RESTART;
	249	else
	250	return HRTIMER_NORESTART;
	251	}
	252
2f599714 MT	253	void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
	254	{
	255	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	256	struct hrtimer *timer;
	257
	258	if (vcpu->vcpu_id != 0 \|\| !pit)
	259	return;
	260
	261	timer = &pit->pit_state.pit_timer.timer;
	262	if (hrtimer_cancel(timer))
beb20d52	263	hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
2f599714 MT	264	}
2f599714 MT	265
7837699f SY	266	static void destroy_pit_timer(struct kvm_kpit_timer *pt)
	267	{
	268	pr_debug("pit: execute del timer!\n");
	269	hrtimer_cancel(&pt->timer);
	270	}
	271
3cf57fed	272	static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
7837699f	273	{
3cf57fed	274	struct kvm_kpit_timer *pt = &ps->pit_timer;
7837699f SY	275	s64 interval;
	276
	277	interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
	278
	279	pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
	280
	281	/* TODO The new value only affected after the retriggered */
	282	hrtimer_cancel(&pt->timer);
	283	pt->period = (is_period == 0) ? 0 : interval;
	284	pt->timer.function = pit_timer_fn;
	285	atomic_set(&pt->pending, 0);
3cf57fed	286	ps->irq_ack = 1;
7837699f SY	287
	288	hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
	289	HRTIMER_MODE_ABS);
	290	}
	291
	292	static void pit_load_count(struct kvm *kvm, int channel, u32 val)
	293	{
	294	struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
	295
	296	WARN_ON(!mutex_is_locked(&ps->lock));
	297
	298	pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
	299
	300	/*
	301	* Though spec said the state of 8254 is undefined after power-up,
	302	* seems some tricky OS like Windows XP depends on IRQ0 interrupt
	303	* when booting up.
	304	* So here setting initialize rate for it, and not a specific number
	305	*/
	306	if (val == 0)
	307	val = 0x10000;
	308
	309	ps->channels[channel].count_load_time = ktime_get();
	310	ps->channels[channel].count = val;
	311
	312	if (channel != 0)
	313	return;
	314
	315	/* Two types of timer
	316	* mode 1 is one shot, mode 2 is period, otherwise del timer */
	317	switch (ps->channels[0].mode) {
	318	case 1:
ece15bab MT	319	/* FIXME: enhance mode 4 precision */
ece15bab MT	320	case 4:
3cf57fed	321	create_pit_timer(ps, val, 0);
7837699f SY	322	break;
7837699f SY	323	case 2:
f6975545	324	case 3:
3cf57fed	325	create_pit_timer(ps, val, 1);
7837699f SY	326	break;
	327	default:
	328	destroy_pit_timer(&ps->pit_timer);
	329	}
	330	}
	331
e0f63cb9 SY	332	void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
	333	{
	334	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	335	pit_load_count(kvm, channel, val);
	336	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	337	}
	338
7837699f SY	339	static void pit_ioport_write(struct kvm_io_device *this,
	340	gpa_t addr, int len, const void *data)
	341	{
	342	struct kvm_pit pit = (struct kvm_pit )this->private;
	343	struct kvm_kpit_state *pit_state = &pit->pit_state;
	344	struct kvm *kvm = pit->kvm;
	345	int channel, access;
	346	struct kvm_kpit_channel_state *s;
	347	u32 val = (u32 ) data;
	348
	349	val &= 0xff;
	350	addr &= KVM_PIT_CHANNEL_MASK;
	351
	352	mutex_lock(&pit_state->lock);
	353
	354	if (val != 0)
	355	pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
	356	(unsigned int)addr, len, val);
	357
	358	if (addr == 3) {
	359	channel = val >> 6;
	360	if (channel == 3) {
	361	/* Read-Back Command. */
	362	for (channel = 0; channel < 3; channel++) {
	363	s = &pit_state->channels[channel];
	364	if (val & (2 << channel)) {
	365	if (!(val & 0x20))
	366	pit_latch_count(kvm, channel);
	367	if (!(val & 0x10))
	368	pit_latch_status(kvm, channel);
	369	}
	370	}
	371	} else {
	372	/* Select Counter <channel>. */
	373	s = &pit_state->channels[channel];
	374	access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
	375	if (access == 0) {
	376	pit_latch_count(kvm, channel);
	377	} else {
	378	s->rw_mode = access;
	379	s->read_state = access;
	380	s->write_state = access;
	381	s->mode = (val >> 1) & 7;
	382	if (s->mode > 5)
	383	s->mode -= 4;
	384	s->bcd = val & 1;
	385	}
	386	}
	387	} else {
	388	/* Write Count. */
	389	s = &pit_state->channels[addr];
	390	switch (s->write_state) {
	391	default:
	392	case RW_STATE_LSB:
	393	pit_load_count(kvm, addr, val);
	394	break;
	395	case RW_STATE_MSB:
	396	pit_load_count(kvm, addr, val << 8);
	397	break;
	398	case RW_STATE_WORD0:
	399	s->write_latch = val;
	400	s->write_state = RW_STATE_WORD1;
	401	break;
	402	case RW_STATE_WORD1:
403	pit_load_count(kvm, addr, s->write_latch \| (val << 8));
404	s->write_state = RW_STATE_WORD0;
405	break;
406	}
407	}
408
409	mutex_unlock(&pit_state->lock);
410	}
411
412	static void pit_ioport_read(struct kvm_io_device *this,
413	gpa_t addr, int len, void *data)
414	{
415	struct kvm_pit pit = (struct kvm_pit )this->private;
416	struct kvm_kpit_state *pit_state = &pit->pit_state;
417	struct kvm *kvm = pit->kvm;
418	int ret, count;
419	struct kvm_kpit_channel_state *s;
420
421	addr &= KVM_PIT_CHANNEL_MASK;
422	s = &pit_state->channels[addr];
423
424	mutex_lock(&pit_state->lock);
425
426	if (s->status_latched) {
427	s->status_latched = 0;
428	ret = s->status;
429	} else if (s->count_latched) {
430	switch (s->count_latched) {
431	default:
432	case RW_STATE_LSB:
433	ret = s->latched_count & 0xff;
434	s->count_latched = 0;
435	break;
436	case RW_STATE_MSB:
437	ret = s->latched_count >> 8;
438	s->count_latched = 0;
439	break;
440	case RW_STATE_WORD0:
441	ret = s->latched_count & 0xff;
442	s->count_latched = RW_STATE_MSB;
443	break;
444	}
445	} else {
446	switch (s->read_state) {
447	default:
448	case RW_STATE_LSB:
449	count = pit_get_count(kvm, addr);
450	ret = count & 0xff;
451	break;
452	case RW_STATE_MSB:
453	count = pit_get_count(kvm, addr);
454	ret = (count >> 8) & 0xff;
455	break;
456	case RW_STATE_WORD0:
457	count = pit_get_count(kvm, addr);
458	ret = count & 0xff;
459	s->read_state = RW_STATE_WORD1;
460	break;
461	case RW_STATE_WORD1:
462	count = pit_get_count(kvm, addr);
463	ret = (count >> 8) & 0xff;
464	s->read_state = RW_STATE_WORD0;
465	break;
466	}
467	}
468
469	if (len > sizeof(ret))
470	len = sizeof(ret);
471	memcpy(data, (char *)&ret, len);
472
473	mutex_unlock(&pit_state->lock);
474	}
475
92760499 LV	476	static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	477	int len, int is_write)
7837699f SY	478	{
	479	return ((addr >= KVM_PIT_BASE_ADDRESS) &&
	480	(addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
	481	}
	482
	483	static void speaker_ioport_write(struct kvm_io_device *this,
	484	gpa_t addr, int len, const void *data)
	485	{
	486	struct kvm_pit pit = (struct kvm_pit )this->private;
	487	struct kvm_kpit_state *pit_state = &pit->pit_state;
	488	struct kvm *kvm = pit->kvm;
	489	u32 val = (u32 ) data;
	490
	491	mutex_lock(&pit_state->lock);
	492	pit_state->speaker_data_on = (val >> 1) & 1;
	493	pit_set_gate(kvm, 2, val & 1);
	494	mutex_unlock(&pit_state->lock);
	495	}
	496
	497	static void speaker_ioport_read(struct kvm_io_device *this,
	498	gpa_t addr, int len, void *data)
	499	{
	500	struct kvm_pit pit = (struct kvm_pit )this->private;
	501	struct kvm_kpit_state *pit_state = &pit->pit_state;
	502	struct kvm *kvm = pit->kvm;
	503	unsigned int refresh_clock;
	504	int ret;
	505
	506	/* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
	507	refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
	508
	509	mutex_lock(&pit_state->lock);
	510	ret = ((pit_state->speaker_data_on << 1) \| pit_get_gate(kvm, 2) \|
	511	(pit_get_out(kvm, 2) << 5) \| (refresh_clock << 4));
	512	if (len > sizeof(ret))
	513	len = sizeof(ret);
	514	memcpy(data, (char *)&ret, len);
	515	mutex_unlock(&pit_state->lock);
	516	}
	517
92760499 LV	518	static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
92760499 LV	519	int len, int is_write)
7837699f SY	520	{
	521	return (addr == KVM_SPEAKER_BASE_ADDRESS);
	522	}
	523
308b0f23	524	void kvm_pit_reset(struct kvm_pit *pit)
7837699f SY	525	{
7837699f SY	526	int i;
308b0f23 SY	527	struct kvm_kpit_channel_state *c;
	528
	529	mutex_lock(&pit->pit_state.lock);
	530	for (i = 0; i < 3; i++) {
	531	c = &pit->pit_state.channels[i];
	532	c->mode = 0xff;
	533	c->gate = (i != 2);
	534	pit_load_count(pit->kvm, i, 0);
	535	}
	536	mutex_unlock(&pit->pit_state.lock);
	537
	538	atomic_set(&pit->pit_state.pit_timer.pending, 0);
3cf57fed	539	pit->pit_state.irq_ack = 1;
308b0f23 SY	540	}
	541
	542	struct kvm_pit kvm_create_pit(struct kvm kvm)
	543	{
7837699f SY	544	struct kvm_pit *pit;
7837699f SY	545	struct kvm_kpit_state *pit_state;
7837699f SY	546
	547	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
	548	if (!pit)
	549	return NULL;
	550
5550af4d	551	pit->irq_source_id = kvm_request_irq_source_id(kvm);
e17d1dc0 AK	552	if (pit->irq_source_id < 0) {
e17d1dc0 AK	553	kfree(pit);
5550af4d	554	return NULL;
e17d1dc0	555	}
5550af4d	556
7837699f SY	557	mutex_init(&pit->pit_state.lock);
7837699f SY	558	mutex_lock(&pit->pit_state.lock);
3cf57fed	559	spin_lock_init(&pit->pit_state.inject_lock);
7837699f SY	560
	561	/* Initialize PIO device */
	562	pit->dev.read = pit_ioport_read;
	563	pit->dev.write = pit_ioport_write;
	564	pit->dev.in_range = pit_in_range;
	565	pit->dev.private = pit;
	566	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
	567
	568	pit->speaker_dev.read = speaker_ioport_read;
	569	pit->speaker_dev.write = speaker_ioport_write;
	570	pit->speaker_dev.in_range = speaker_in_range;
	571	pit->speaker_dev.private = pit;
	572	kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
	573
	574	kvm->arch.vpit = pit;
	575	pit->kvm = kvm;
	576
	577	pit_state = &pit->pit_state;
	578	pit_state->pit = pit;
	579	hrtimer_init(&pit_state->pit_timer.timer,
	580	CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
3cf57fed MT	581	pit_state->irq_ack_notifier.gsi = 0;
	582	pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
	583	kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
52d939a0	584	pit_state->pit_timer.reinject = true;
7837699f SY	585	mutex_unlock(&pit->pit_state.lock);
7837699f SY	586
308b0f23	587	kvm_pit_reset(pit);
7837699f SY	588
	589	return pit;
	590	}
	591
	592	void kvm_free_pit(struct kvm *kvm)
	593	{
	594	struct hrtimer *timer;
	595
	596	if (kvm->arch.vpit) {
	597	mutex_lock(&kvm->arch.vpit->pit_state.lock);
	598	timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
	599	hrtimer_cancel(timer);
5550af4d	600	kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
7837699f SY	601	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
	602	kfree(kvm->arch.vpit);
	603	}
	604	}
	605
8b2cf73c	606	static void __inject_pit_timer_intr(struct kvm *kvm)
7837699f	607	{
23930f95 JK	608	struct kvm_vcpu *vcpu;
	609	int i;
	610
7837699f	611	mutex_lock(&kvm->lock);
5550af4d SY	612	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
5550af4d SY	613	kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
7837699f	614	mutex_unlock(&kvm->lock);
23930f95 JK	615
23930f95 JK	616	/*
8fdb2351 JK	617	* Provides NMI watchdog support via Virtual Wire mode.
	618	* The route is: PIT -> PIC -> LVT0 in NMI mode.
	619	*
	620	* Note: Our Virtual Wire implementation is simplified, only
	621	* propagating PIT interrupts to all VCPUs when they have set
	622	* LVT0 to NMI delivery. Other PIC interrupts are just sent to
	623	* VCPU0, and only if its LVT0 is in EXTINT mode.
23930f95	624	*/
cc6e462c JK	625	if (kvm->arch.vapics_in_nmi_mode > 0)
	626	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
	627	vcpu = kvm->vcpus[i];
	628	if (vcpu)
	629	kvm_apic_nmi_wd_deliver(vcpu);
	630	}
7837699f SY	631	}
	632
	633	void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
	634	{
	635	struct kvm_pit *pit = vcpu->kvm->arch.vpit;
	636	struct kvm *kvm = vcpu->kvm;
	637	struct kvm_kpit_state *ps;
	638
	639	if (vcpu && pit) {
3cf57fed	640	int inject = 0;
7837699f SY	641	ps = &pit->pit_state;
7837699f SY	642
3cf57fed MT	643	/* Try to inject pending interrupts when
	644	* last one has been acked.
	645	*/
	646	spin_lock(&ps->inject_lock);
	647	if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
	648	ps->irq_ack = 0;
	649	inject = 1;
7837699f	650	}
3cf57fed MT	651	spin_unlock(&ps->inject_lock);
	652	if (inject)
	653	__inject_pit_timer_intr(kvm);
7837699f SY	654	}
7837699f SY	655	}