[deliverable/linux.git] / arch / x86 / kvm / i8259.c

/*
 * 8259 interrupt controller emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2007 Intel Corporation
 * Copyright 2009 Red Hat, Inc. and/or its affilates.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *   Port from Qemu.
 */
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include "irq.h"

#include <linux/kvm_host.h>
#include "trace.h"

static void pic_irq_request(struct kvm *kvm, int level);

static void pic_lock(struct kvm_pic *s)
	__acquires(&s->lock)
{
	raw_spin_lock(&s->lock);
}

static void pic_unlock(struct kvm_pic *s)
	__releases(&s->lock)
{
	bool wakeup = s->wakeup_needed;
	struct kvm_vcpu *vcpu, *found = NULL;
	int i;

	s->wakeup_needed = false;

	raw_spin_unlock(&s->lock);

	if (wakeup) {
		kvm_for_each_vcpu(i, vcpu, s->kvm) {
			if (kvm_apic_accept_pic_intr(vcpu)) {
				found = vcpu;
				break;
			}
		}

		if (!found)
			found = s->kvm->bsp_vcpu;

		kvm_vcpu_kick(found);
	}
}

static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
{
	s->isr &= ~(1 << irq);
	s->isr_ack |= (1 << irq);
	if (s != &s->pics_state->pics[0])
		irq += 8;
	/*
	 * We are dropping lock while calling ack notifiers since ack
	 * notifier callbacks for assigned devices call into PIC recursively.
	 * Other interrupt may be delivered to PIC while lock is dropped but
	 * it should be safe since PIC state is already updated at this stage.
	 */
	pic_unlock(s->pics_state);
	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
	pic_lock(s->pics_state);
}

void kvm_pic_clear_isr_ack(struct kvm *kvm)
{
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	s->pics[0].isr_ack = 0xff;
	s->pics[1].isr_ack = 0xff;
	pic_unlock(s);
}

/*
 * set irq level. If an edge is detected, then the IRR is set to 1
 */
static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
{
	int mask, ret = 1;
	mask = 1 << irq;
	if (s->elcr & mask)	/* level triggered */
		if (level) {
			ret = !(s->irr & mask);
			s->irr |= mask;
			s->last_irr |= mask;
		} else {
			s->irr &= ~mask;
			s->last_irr &= ~mask;
		}
	else	/* edge triggered */
		if (level) {
			if ((s->last_irr & mask) == 0) {
				ret = !(s->irr & mask);
				s->irr |= mask;
			}
			s->last_irr |= mask;
		} else
			s->last_irr &= ~mask;

	return (s->imr & mask) ? -1 : ret;
}

/*
 * return the highest priority found in mask (highest = smallest
 * number). Return 8 if no irq
 */
static inline int get_priority(struct kvm_kpic_state *s, int mask)
{
	int priority;
	if (mask == 0)
		return 8;
	priority = 0;
	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
		priority++;
	return priority;
}

/*
 * return the pic wanted interrupt. return -1 if none
 */
static int pic_get_irq(struct kvm_kpic_state *s)
{
	int mask, cur_priority, priority;

	mask = s->irr & ~s->imr;
	priority = get_priority(s, mask);
	if (priority == 8)
		return -1;
	/*
	 * compute current priority. If special fully nested mode on the
	 * master, the IRQ coming from the slave is not taken into account
	 * for the priority computation.
	 */
	mask = s->isr;
	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
		mask &= ~(1 << 2);
	cur_priority = get_priority(s, mask);
	if (priority < cur_priority)
		/*
		 * higher priority found: an irq should be generated
		 */
		return (priority + s->priority_add) & 7;
	else
		return -1;
}

/*
 * raise irq to CPU if necessary. must be called every time the active
 * irq may change
 */
static void pic_update_irq(struct kvm_pic *s)
{
	int irq2, irq;

	irq2 = pic_get_irq(&s->pics[1]);
	if (irq2 >= 0) {
		/*
		 * if irq request by slave pic, signal master PIC
		 */
		pic_set_irq1(&s->pics[0], 2, 1);
		pic_set_irq1(&s->pics[0], 2, 0);
	}
	irq = pic_get_irq(&s->pics[0]);
	pic_irq_request(s->kvm, irq >= 0);
}

void kvm_pic_update_irq(struct kvm_pic *s)
{
	pic_lock(s);
	pic_update_irq(s);
	pic_unlock(s);
}

int kvm_pic_set_irq(void *opaque, int irq, int level)
{
	struct kvm_pic *s = opaque;
	int ret = -1;

	pic_lock(s);
	if (irq >= 0 && irq < PIC_NUM_PINS) {
		ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
		pic_update_irq(s);
		trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
				      s->pics[irq >> 3].imr, ret == 0);
	}
	pic_unlock(s);

	return ret;
}

/*
 * acknowledge interrupt 'irq'
 */
static inline void pic_intack(struct kvm_kpic_state *s, int irq)
{
	s->isr |= 1 << irq;
	/*
	 * We don't clear a level sensitive interrupt here
	 */
	if (!(s->elcr & (1 << irq)))
		s->irr &= ~(1 << irq);

	if (s->auto_eoi) {
		if (s->rotate_on_auto_eoi)
			s->priority_add = (irq + 1) & 7;
		pic_clear_isr(s, irq);
	}

}

int kvm_pic_read_irq(struct kvm *kvm)
{
	int irq, irq2, intno;
	struct kvm_pic *s = pic_irqchip(kvm);

	pic_lock(s);
	irq = pic_get_irq(&s->pics[0]);
	if (irq >= 0) {
		pic_intack(&s->pics[0], irq);
		if (irq == 2) {
			irq2 = pic_get_irq(&s->pics[1]);
			if (irq2 >= 0)
				pic_intack(&s->pics[1], irq2);
			else
				/*
				 * spurious IRQ on slave controller
				 */
				irq2 = 7;
			intno = s->pics[1].irq_base + irq2;
			irq = irq2 + 8;
		} else
			intno = s->pics[0].irq_base + irq;
	} else {
		/*
		 * spurious IRQ on host controller
		 */
		irq = 7;
		intno = s->pics[0].irq_base + irq;
	}
	pic_update_irq(s);
	pic_unlock(s);

	return intno;
}

void kvm_pic_reset(struct kvm_kpic_state *s)
{
	int irq;
	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
	u8 irr = s->irr, isr = s->imr;

	s->last_irr = 0;
	s->irr = 0;
	s->imr = 0;
	s->isr = 0;
	s->isr_ack = 0xff;
	s->priority_add = 0;
	s->irq_base = 0;
	s->read_reg_select = 0;
	s->poll = 0;
	s->special_mask = 0;
	s->init_state = 0;
	s->auto_eoi = 0;
	s->rotate_on_auto_eoi = 0;
	s->special_fully_nested_mode = 0;
	s->init4 = 0;

	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
		if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
			if (irr & (1 << irq) || isr & (1 << irq)) {
				pic_clear_isr(s, irq);
			}
	}
}

static void pic_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	int priority, cmd, irq;

	addr &= 1;
	if (addr == 0) {
		if (val & 0x10) {
			kvm_pic_reset(s);	/* init */
			/*
			 * deassert a pending interrupt
			 */
			pic_irq_request(s->pics_state->kvm, 0);
			s->init_state = 1;
			s->init4 = val & 1;
			if (val & 0x02)
				printk(KERN_ERR "single mode not supported");
			if (val & 0x08)
				printk(KERN_ERR
				       "level sensitive irq not supported");
		} else if (val & 0x08) {
			if (val & 0x04)
				s->poll = 1;
			if (val & 0x02)
				s->read_reg_select = val & 1;
			if (val & 0x40)
				s->special_mask = (val >> 5) & 1;
		} else {
			cmd = val >> 5;
			switch (cmd) {
			case 0:
			case 4:
				s->rotate_on_auto_eoi = cmd >> 2;
				break;
			case 1:	/* end of interrupt */
			case 5:
				priority = get_priority(s, s->isr);
				if (priority != 8) {
					irq = (priority + s->priority_add) & 7;
					if (cmd == 5)
						s->priority_add = (irq + 1) & 7;
					pic_clear_isr(s, irq);
					pic_update_irq(s->pics_state);
				}
				break;
			case 3:
				irq = val & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			case 6:
				s->priority_add = (val + 1) & 7;
				pic_update_irq(s->pics_state);
				break;
			case 7:
				irq = val & 7;
				s->priority_add = (irq + 1) & 7;
				pic_clear_isr(s, irq);
				pic_update_irq(s->pics_state);
				break;
			default:
				break;	/* no operation */
			}
		}
	} else
		switch (s->init_state) {
		case 0:		/* normal mode */
			s->imr = val;
			pic_update_irq(s->pics_state);
			break;
		case 1:
			s->irq_base = val & 0xf8;
			s->init_state = 2;
			break;
		case 2:
			if (s->init4)
				s->init_state = 3;
			else
				s->init_state = 0;
			break;
		case 3:
			s->special_fully_nested_mode = (val >> 4) & 1;
			s->auto_eoi = (val >> 1) & 1;
			s->init_state = 0;
			break;
		}
}

static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
{
	int ret;

	ret = pic_get_irq(s);
	if (ret >= 0) {
		if (addr1 >> 7) {
			s->pics_state->pics[0].isr &= ~(1 << 2);
			s->pics_state->pics[0].irr &= ~(1 << 2);
		}
		s->irr &= ~(1 << ret);
		pic_clear_isr(s, ret);
		if (addr1 >> 7 || ret != 2)
			pic_update_irq(s->pics_state);
	} else {
		ret = 0x07;
		pic_update_irq(s->pics_state);
	}

	return ret;
}

static u32 pic_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	unsigned int addr;
	int ret;

	addr = addr1;
	addr &= 1;
	if (s->poll) {
		ret = pic_poll_read(s, addr1);
		s->poll = 0;
	} else
		if (addr == 0)
			if (s->read_reg_select)
				ret = s->isr;
			else
				ret = s->irr;
		else
			ret = s->imr;
	return ret;
}

static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
{
	struct kvm_kpic_state *s = opaque;
	s->elcr = val & s->elcr_mask;
}

static u32 elcr_ioport_read(void *opaque, u32 addr1)
{
	struct kvm_kpic_state *s = opaque;
	return s->elcr;
}

static int picdev_in_range(gpa_t addr)
{
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
	case 0x4d0:
	case 0x4d1:
		return 1;
	default:
		return 0;
	}
}

static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
{
	return container_of(dev, struct kvm_pic, dev);
}

static int picdev_write(struct kvm_io_device *this,
			 gpa_t addr, int len, const void *val)
{
	struct kvm_pic *s = to_pic(this);
	unsigned char data = *(unsigned char *)val;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte write\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		pic_ioport_write(&s->pics[addr >> 7], addr, data);
		break;
	case 0x4d0:
	case 0x4d1:
		elcr_ioport_write(&s->pics[addr & 1], addr, data);
		break;
	}
	pic_unlock(s);
	return 0;
}

static int picdev_read(struct kvm_io_device *this,
		       gpa_t addr, int len, void *val)
{
	struct kvm_pic *s = to_pic(this);
	unsigned char data = 0;
	if (!picdev_in_range(addr))
		return -EOPNOTSUPP;

	if (len != 1) {
		if (printk_ratelimit())
			printk(KERN_ERR "PIC: non byte read\n");
		return 0;
	}
	pic_lock(s);
	switch (addr) {
	case 0x20:
	case 0x21:
	case 0xa0:
	case 0xa1:
		data = pic_ioport_read(&s->pics[addr >> 7], addr);
		break;
	case 0x4d0:
	case 0x4d1:
		data = elcr_ioport_read(&s->pics[addr & 1], addr);
		break;
	}
	*(unsigned char *)val = data;
	pic_unlock(s);
	return 0;
}

/*
 * callback when PIC0 irq status changed
 */
static void pic_irq_request(struct kvm *kvm, int level)
{
	struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
	struct kvm_pic *s = pic_irqchip(kvm);
	int irq = pic_get_irq(&s->pics[0]);

	s->output = level;
	if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
		s->pics[0].isr_ack &= ~(1 << irq);
		s->wakeup_needed = true;
	}
}

static const struct kvm_io_device_ops picdev_ops = {
	.read     = picdev_read,
	.write    = picdev_write,
};

struct kvm_pic *kvm_create_pic(struct kvm *kvm)
{
	struct kvm_pic *s;
	int ret;

	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	if (!s)
		return NULL;
	raw_spin_lock_init(&s->lock);
	s->kvm = kvm;
	s->pics[0].elcr_mask = 0xf8;
	s->pics[1].elcr_mask = 0xde;
	s->pics[0].pics_state = s;
	s->pics[1].pics_state = s;

	/*
	 * Initialize PIO device
	 */
	kvm_iodevice_init(&s->dev, &picdev_ops);
	mutex_lock(&kvm->slots_lock);
	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
	mutex_unlock(&kvm->slots_lock);
	if (ret < 0) {
		kfree(s);
		return NULL;
	}

	return s;
}

void kvm_destroy_pic(struct kvm *kvm)
{
	struct kvm_pic *vpic = kvm->arch.vpic;

	if (vpic) {
		kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
		kvm->arch.vpic = NULL;
		kfree(vpic);
	}
}
Commit	Line	Data
85f455f7 ED	1	/*
	2	* 8259 interrupt controller emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2007 Intel Corporation
221d059d	6	* Copyright 2009 Red Hat, Inc. and/or its affilates.
85f455f7 ED	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	* Authors:
	26	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	27	* Port from Qemu.
	28	*/
	29	#include <linux/mm.h>
5a0e3ad6	30	#include <linux/slab.h>
3f353858	31	#include <linux/bitops.h>
85f455f7	32	#include "irq.h"
edf88417 AK	33
edf88417 AK	34	#include <linux/kvm_host.h>
1000ff8d	35	#include "trace.h"
85f455f7	36
073d4613 AK	37	static void pic_irq_request(struct kvm *kvm, int level);
073d4613 AK	38
50a085bd JK	39	static void pic_lock(struct kvm_pic *s)
	40	__acquires(&s->lock)
	41	{
	42	raw_spin_lock(&s->lock);
	43	}
	44
	45	static void pic_unlock(struct kvm_pic *s)
	46	__releases(&s->lock)
	47	{
	48	bool wakeup = s->wakeup_needed;
529df65e CL	49	struct kvm_vcpu vcpu, found = NULL;
529df65e CL	50	int i;
50a085bd JK	51
	52	s->wakeup_needed = false;
	53
	54	raw_spin_unlock(&s->lock);
	55
	56	if (wakeup) {
529df65e CL	57	kvm_for_each_vcpu(i, vcpu, s->kvm) {
	58	if (kvm_apic_accept_pic_intr(vcpu)) {
	59	found = vcpu;
	60	break;
	61	}
	62	}
	63
	64	if (!found)
	65	found = s->kvm->bsp_vcpu;
	66
	67	kvm_vcpu_kick(found);
50a085bd JK	68	}
	69	}
	70
7edd0ce0 AK	71	static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
	72	{
	73	s->isr &= ~(1 << irq);
e4825800	74	s->isr_ack \|= (1 << irq);
938396a2 GN	75	if (s != &s->pics_state->pics[0])
938396a2 GN	76	irq += 8;
eba0226b GN	77	/*
	78	* We are dropping lock while calling ack notifiers since ack
	79	* notifier callbacks for assigned devices call into PIC recursively.
	80	* Other interrupt may be delivered to PIC while lock is dropped but
	81	* it should be safe since PIC state is already updated at this stage.
	82	*/
50a085bd	83	pic_unlock(s->pics_state);
938396a2	84	kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
50a085bd	85	pic_lock(s->pics_state);
e4825800 MT	86	}
	87
	88	void kvm_pic_clear_isr_ack(struct kvm *kvm)
	89	{
	90	struct kvm_pic *s = pic_irqchip(kvm);
fa8273e9	91
50a085bd	92	pic_lock(s);
e4825800 MT	93	s->pics[0].isr_ack = 0xff;
e4825800 MT	94	s->pics[1].isr_ack = 0xff;
50a085bd	95	pic_unlock(s);
7edd0ce0 AK	96	}
7edd0ce0 AK	97
85f455f7 ED	98	/*
	99	* set irq level. If an edge is detected, then the IRR is set to 1
	100	*/
4925663a	101	static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
85f455f7	102	{
4925663a	103	int mask, ret = 1;
85f455f7 ED	104	mask = 1 << irq;
	105	if (s->elcr & mask) /* level triggered */
	106	if (level) {
4925663a	107	ret = !(s->irr & mask);
85f455f7 ED	108	s->irr \|= mask;
	109	s->last_irr \|= mask;
	110	} else {
	111	s->irr &= ~mask;
	112	s->last_irr &= ~mask;
	113	}
	114	else /* edge triggered */
	115	if (level) {
4925663a GN	116	if ((s->last_irr & mask) == 0) {
4925663a GN	117	ret = !(s->irr & mask);
85f455f7	118	s->irr \|= mask;
4925663a	119	}
85f455f7 ED	120	s->last_irr \|= mask;
	121	} else
	122	s->last_irr &= ~mask;
4925663a GN	123
4925663a GN	124	return (s->imr & mask) ? -1 : ret;
85f455f7 ED	125	}
	126
	127	/*
	128	* return the highest priority found in mask (highest = smallest
	129	* number). Return 8 if no irq
	130	*/
	131	static inline int get_priority(struct kvm_kpic_state *s, int mask)
	132	{
	133	int priority;
	134	if (mask == 0)
	135	return 8;
	136	priority = 0;
	137	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	138	priority++;
	139	return priority;
	140	}
	141
	142	/*
	143	* return the pic wanted interrupt. return -1 if none
	144	*/
	145	static int pic_get_irq(struct kvm_kpic_state *s)
	146	{
	147	int mask, cur_priority, priority;
	148
	149	mask = s->irr & ~s->imr;
	150	priority = get_priority(s, mask);
	151	if (priority == 8)
	152	return -1;
	153	/*
	154	* compute current priority. If special fully nested mode on the
	155	* master, the IRQ coming from the slave is not taken into account
	156	* for the priority computation.
	157	*/
	158	mask = s->isr;
	159	if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
	160	mask &= ~(1 << 2);
	161	cur_priority = get_priority(s, mask);
	162	if (priority < cur_priority)
	163	/*
	164	* higher priority found: an irq should be generated
	165	*/
	166	return (priority + s->priority_add) & 7;
	167	else
	168	return -1;
	169	}
	170
	171	/*
	172	* raise irq to CPU if necessary. must be called every time the active
	173	* irq may change
	174	*/
	175	static void pic_update_irq(struct kvm_pic *s)
	176	{
	177	int irq2, irq;
	178
	179	irq2 = pic_get_irq(&s->pics[1]);
	180	if (irq2 >= 0) {
	181	/*
	182	* if irq request by slave pic, signal master PIC
	183	*/
	184	pic_set_irq1(&s->pics[0], 2, 1);
	185	pic_set_irq1(&s->pics[0], 2, 0);
	186	}
	187	irq = pic_get_irq(&s->pics[0]);
36633f32	188	pic_irq_request(s->kvm, irq >= 0);
85f455f7 ED	189	}
85f455f7 ED	190
6ceb9d79 HQ	191	void kvm_pic_update_irq(struct kvm_pic *s)
6ceb9d79 HQ	192	{
50a085bd	193	pic_lock(s);
6ceb9d79	194	pic_update_irq(s);
50a085bd	195	pic_unlock(s);
6ceb9d79 HQ	196	}
6ceb9d79 HQ	197
4925663a	198	int kvm_pic_set_irq(void *opaque, int irq, int level)
85f455f7 ED	199	{
85f455f7 ED	200	struct kvm_pic *s = opaque;
4925663a	201	int ret = -1;
85f455f7	202
50a085bd	203	pic_lock(s);
c65bbfa1	204	if (irq >= 0 && irq < PIC_NUM_PINS) {
4925663a	205	ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
c65bbfa1	206	pic_update_irq(s);
1000ff8d GN	207	trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
1000ff8d GN	208	s->pics[irq >> 3].imr, ret == 0);
c65bbfa1	209	}
50a085bd	210	pic_unlock(s);
4925663a GN	211
4925663a GN	212	return ret;
85f455f7 ED	213	}
	214
	215	/*
	216	* acknowledge interrupt 'irq'
	217	*/
	218	static inline void pic_intack(struct kvm_kpic_state *s, int irq)
	219	{
7edd0ce0	220	s->isr \|= 1 << irq;
85f455f7 ED	221	/*
	222	* We don't clear a level sensitive interrupt here
	223	*/
	224	if (!(s->elcr & (1 << irq)))
	225	s->irr &= ~(1 << irq);
eba0226b GN	226
	227	if (s->auto_eoi) {
	228	if (s->rotate_on_auto_eoi)
	229	s->priority_add = (irq + 1) & 7;
	230	pic_clear_isr(s, irq);
	231	}
	232
85f455f7 ED	233	}
85f455f7 ED	234
f5244726	235	int kvm_pic_read_irq(struct kvm *kvm)
85f455f7 ED	236	{
85f455f7 ED	237	int irq, irq2, intno;
f5244726	238	struct kvm_pic *s = pic_irqchip(kvm);
85f455f7	239
50a085bd	240	pic_lock(s);
85f455f7 ED	241	irq = pic_get_irq(&s->pics[0]);
	242	if (irq >= 0) {
	243	pic_intack(&s->pics[0], irq);
	244	if (irq == 2) {
	245	irq2 = pic_get_irq(&s->pics[1]);
	246	if (irq2 >= 0)
	247	pic_intack(&s->pics[1], irq2);
	248	else
	249	/*
	250	* spurious IRQ on slave controller
	251	*/
	252	irq2 = 7;
	253	intno = s->pics[1].irq_base + irq2;
	254	irq = irq2 + 8;
	255	} else
	256	intno = s->pics[0].irq_base + irq;
	257	} else {
	258	/*
	259	* spurious IRQ on host controller
	260	*/
	261	irq = 7;
	262	intno = s->pics[0].irq_base + irq;
	263	}
	264	pic_update_irq(s);
50a085bd	265	pic_unlock(s);
85f455f7 ED	266
	267	return intno;
	268	}
	269
2fcceae1	270	void kvm_pic_reset(struct kvm_kpic_state *s)
85f455f7	271	{
79c727d4	272	int irq;
073d4613	273	struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
79c727d4	274	u8 irr = s->irr, isr = s->imr;
f5244726	275
85f455f7 ED	276	s->last_irr = 0;
	277	s->irr = 0;
	278	s->imr = 0;
	279	s->isr = 0;
e4825800	280	s->isr_ack = 0xff;
85f455f7 ED	281	s->priority_add = 0;
	282	s->irq_base = 0;
	283	s->read_reg_select = 0;
	284	s->poll = 0;
	285	s->special_mask = 0;
	286	s->init_state = 0;
	287	s->auto_eoi = 0;
	288	s->rotate_on_auto_eoi = 0;
	289	s->special_fully_nested_mode = 0;
	290	s->init4 = 0;
79c727d4 GN	291
	292	for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
	293	if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
	294	if (irr & (1 << irq) \|\| isr & (1 << irq)) {
	295	pic_clear_isr(s, irq);
	296	}
	297	}
85f455f7 ED	298	}
	299
	300	static void pic_ioport_write(void *opaque, u32 addr, u32 val)
	301	{
	302	struct kvm_kpic_state *s = opaque;
	303	int priority, cmd, irq;
	304
	305	addr &= 1;
	306	if (addr == 0) {
	307	if (val & 0x10) {
2fcceae1	308	kvm_pic_reset(s); /* init */
85f455f7 ED	309	/*
	310	* deassert a pending interrupt
	311	*/
073d4613	312	pic_irq_request(s->pics_state->kvm, 0);
85f455f7 ED	313	s->init_state = 1;
	314	s->init4 = val & 1;
	315	if (val & 0x02)
	316	printk(KERN_ERR "single mode not supported");
	317	if (val & 0x08)
	318	printk(KERN_ERR
	319	"level sensitive irq not supported");
	320	} else if (val & 0x08) {
	321	if (val & 0x04)
	322	s->poll = 1;
	323	if (val & 0x02)
	324	s->read_reg_select = val & 1;
	325	if (val & 0x40)
	326	s->special_mask = (val >> 5) & 1;
	327	} else {
	328	cmd = val >> 5;
	329	switch (cmd) {
	330	case 0:
	331	case 4:
	332	s->rotate_on_auto_eoi = cmd >> 2;
	333	break;
	334	case 1: /* end of interrupt */
	335	case 5:
	336	priority = get_priority(s, s->isr);
	337	if (priority != 8) {
	338	irq = (priority + s->priority_add) & 7;
85f455f7 ED	339	if (cmd == 5)
85f455f7 ED	340	s->priority_add = (irq + 1) & 7;
eba0226b	341	pic_clear_isr(s, irq);
85f455f7 ED	342	pic_update_irq(s->pics_state);
	343	}
	344	break;
	345	case 3:
	346	irq = val & 7;
7edd0ce0	347	pic_clear_isr(s, irq);
85f455f7 ED	348	pic_update_irq(s->pics_state);
	349	break;
	350	case 6:
	351	s->priority_add = (val + 1) & 7;
	352	pic_update_irq(s->pics_state);
	353	break;
	354	case 7:
	355	irq = val & 7;
85f455f7	356	s->priority_add = (irq + 1) & 7;
7edd0ce0	357	pic_clear_isr(s, irq);
85f455f7 ED	358	pic_update_irq(s->pics_state);
	359	break;
	360	default:
	361	break; /* no operation */
	362	}
	363	}
	364	} else
	365	switch (s->init_state) {
	366	case 0: /* normal mode */
	367	s->imr = val;
	368	pic_update_irq(s->pics_state);
	369	break;
	370	case 1:
	371	s->irq_base = val & 0xf8;
	372	s->init_state = 2;
	373	break;
	374	case 2:
	375	if (s->init4)
	376	s->init_state = 3;
	377	else
	378	s->init_state = 0;
	379	break;
	380	case 3:
	381	s->special_fully_nested_mode = (val >> 4) & 1;
	382	s->auto_eoi = (val >> 1) & 1;
	383	s->init_state = 0;
	384	break;
	385	}
	386	}
	387
	388	static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
	389	{
	390	int ret;
	391
	392	ret = pic_get_irq(s);
	393	if (ret >= 0) {
	394	if (addr1 >> 7) {
	395	s->pics_state->pics[0].isr &= ~(1 << 2);
	396	s->pics_state->pics[0].irr &= ~(1 << 2);
	397	}
	398	s->irr &= ~(1 << ret);
7edd0ce0	399	pic_clear_isr(s, ret);
85f455f7 ED	400	if (addr1 >> 7 \|\| ret != 2)
	401	pic_update_irq(s->pics_state);
	402	} else {
	403	ret = 0x07;
	404	pic_update_irq(s->pics_state);
	405	}
	406
	407	return ret;
	408	}
	409
	410	static u32 pic_ioport_read(void *opaque, u32 addr1)
	411	{
	412	struct kvm_kpic_state *s = opaque;
	413	unsigned int addr;
	414	int ret;
	415
	416	addr = addr1;
	417	addr &= 1;
	418	if (s->poll) {
	419	ret = pic_poll_read(s, addr1);
	420	s->poll = 0;
	421	} else
	422	if (addr == 0)
	423	if (s->read_reg_select)
	424	ret = s->isr;
	425	else
	426	ret = s->irr;
	427	else
	428	ret = s->imr;
	429	return ret;
	430	}
	431
	432	static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
	433	{
	434	struct kvm_kpic_state *s = opaque;
	435	s->elcr = val & s->elcr_mask;
	436	}
	437
	438	static u32 elcr_ioport_read(void *opaque, u32 addr1)
	439	{
	440	struct kvm_kpic_state *s = opaque;
	441	return s->elcr;
	442	}
	443
bda9020e	444	static int picdev_in_range(gpa_t addr)
85f455f7 ED	445	{
	446	switch (addr) {
	447	case 0x20:
	448	case 0x21:
	449	case 0xa0:
	450	case 0xa1:
	451	case 0x4d0:
	452	case 0x4d1:
	453	return 1;
	454	default:
	455	return 0;
	456	}
	457	}
	458
d76685c4 GH	459	static inline struct kvm_pic to_pic(struct kvm_io_device dev)
	460	{
	461	return container_of(dev, struct kvm_pic, dev);
	462	}
	463
bda9020e	464	static int picdev_write(struct kvm_io_device *this,
85f455f7 ED	465	gpa_t addr, int len, const void *val)
85f455f7 ED	466	{
d76685c4	467	struct kvm_pic *s = to_pic(this);
85f455f7	468	unsigned char data = (unsigned char )val;
bda9020e MT	469	if (!picdev_in_range(addr))
bda9020e MT	470	return -EOPNOTSUPP;
85f455f7 ED	471
	472	if (len != 1) {
	473	if (printk_ratelimit())
	474	printk(KERN_ERR "PIC: non byte write\n");
bda9020e	475	return 0;
85f455f7	476	}
50a085bd	477	pic_lock(s);
85f455f7 ED	478	switch (addr) {
	479	case 0x20:
	480	case 0x21:
	481	case 0xa0:
	482	case 0xa1:
	483	pic_ioport_write(&s->pics[addr >> 7], addr, data);
	484	break;
	485	case 0x4d0:
	486	case 0x4d1:
	487	elcr_ioport_write(&s->pics[addr & 1], addr, data);
	488	break;
	489	}
50a085bd	490	pic_unlock(s);
bda9020e	491	return 0;
85f455f7 ED	492	}
85f455f7 ED	493
bda9020e MT	494	static int picdev_read(struct kvm_io_device *this,
bda9020e MT	495	gpa_t addr, int len, void *val)
85f455f7	496	{
d76685c4	497	struct kvm_pic *s = to_pic(this);
85f455f7	498	unsigned char data = 0;
bda9020e MT	499	if (!picdev_in_range(addr))
bda9020e MT	500	return -EOPNOTSUPP;
85f455f7 ED	501
	502	if (len != 1) {
	503	if (printk_ratelimit())
	504	printk(KERN_ERR "PIC: non byte read\n");
bda9020e	505	return 0;
85f455f7	506	}
50a085bd	507	pic_lock(s);
85f455f7 ED	508	switch (addr) {
	509	case 0x20:
	510	case 0x21:
	511	case 0xa0:
	512	case 0xa1:
	513	data = pic_ioport_read(&s->pics[addr >> 7], addr);
	514	break;
	515	case 0x4d0:
	516	case 0x4d1:
	517	data = elcr_ioport_read(&s->pics[addr & 1], addr);
	518	break;
	519	}
	520	(unsigned char )val = data;
50a085bd	521	pic_unlock(s);
bda9020e	522	return 0;
85f455f7 ED	523	}
	524
	525	/*
	526	* callback when PIC0 irq status changed
	527	*/
073d4613	528	static void pic_irq_request(struct kvm *kvm, int level)
85f455f7	529	{
c5af89b6	530	struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
e4825800 MT	531	struct kvm_pic *s = pic_irqchip(kvm);
e4825800 MT	532	int irq = pic_get_irq(&s->pics[0]);
85f455f7	533
e4825800 MT	534	s->output = level;
	535	if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
	536	s->pics[0].isr_ack &= ~(1 << irq);
50a085bd	537	s->wakeup_needed = true;
e4825800	538	}
85f455f7 ED	539	}
85f455f7 ED	540
d76685c4 GH	541	static const struct kvm_io_device_ops picdev_ops = {
	542	.read = picdev_read,
	543	.write = picdev_write,
d76685c4 GH	544	};
d76685c4 GH	545
85f455f7 ED	546	struct kvm_pic kvm_create_pic(struct kvm kvm)
	547	{
	548	struct kvm_pic *s;
090b7aff GH	549	int ret;
090b7aff GH	550
85f455f7 ED	551	s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
	552	if (!s)
	553	return NULL;
fa8273e9	554	raw_spin_lock_init(&s->lock);
3f353858	555	s->kvm = kvm;
85f455f7 ED	556	s->pics[0].elcr_mask = 0xf8;
85f455f7 ED	557	s->pics[1].elcr_mask = 0xde;
85f455f7 ED	558	s->pics[0].pics_state = s;
	559	s->pics[1].pics_state = s;
	560
	561	/*
	562	* Initialize PIO device
	563	*/
d76685c4	564	kvm_iodevice_init(&s->dev, &picdev_ops);
79fac95e	565	mutex_lock(&kvm->slots_lock);
e93f8a0f	566	ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
79fac95e	567	mutex_unlock(&kvm->slots_lock);
090b7aff GH	568	if (ret < 0) {
	569	kfree(s);
	570	return NULL;
	571	}
	572
85f455f7 ED	573	return s;
85f455f7 ED	574	}
72bb2fcd WY	575
	576	void kvm_destroy_pic(struct kvm *kvm)
	577	{
	578	struct kvm_pic *vpic = kvm->arch.vpic;
	579
	580	if (vpic) {
	581	kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
	582	kvm->arch.vpic = NULL;
	583	kfree(vpic);
	584	}
	585	}