Commit | Line | Data |
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1fd4f2a5 ED |
1 | /* |
2 | * Copyright (C) 2001 MandrakeSoft S.A. | |
221d059d | 3 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
1fd4f2a5 ED |
4 | * |
5 | * MandrakeSoft S.A. | |
6 | * 43, rue d'Aboukir | |
7 | * 75002 Paris - France | |
8 | * http://www.linux-mandrake.com/ | |
9 | * http://www.mandrakesoft.com/ | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU Lesser General Public | |
22 | * License along with this library; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | * Yunhong Jiang <yunhong.jiang@intel.com> | |
26 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
27 | * Based on Xen 3.1 code. | |
28 | */ | |
29 | ||
edf88417 | 30 | #include <linux/kvm_host.h> |
1fd4f2a5 ED |
31 | #include <linux/kvm.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/highmem.h> | |
34 | #include <linux/smp.h> | |
35 | #include <linux/hrtimer.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
c7c9c56c | 38 | #include <linux/export.h> |
1fd4f2a5 | 39 | #include <asm/processor.h> |
1fd4f2a5 ED |
40 | #include <asm/page.h> |
41 | #include <asm/current.h> | |
1000ff8d | 42 | #include <trace/events/kvm.h> |
82470196 ZX |
43 | |
44 | #include "ioapic.h" | |
45 | #include "lapic.h" | |
f5244726 | 46 | #include "irq.h" |
82470196 | 47 | |
e25e3ed5 LV |
48 | #if 0 |
49 | #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) | |
50 | #else | |
1fd4f2a5 | 51 | #define ioapic_debug(fmt, arg...) |
e25e3ed5 | 52 | #endif |
0b10a1c8 | 53 | static int ioapic_service(struct kvm_ioapic *vioapic, int irq, |
aa2fbe6d | 54 | bool line_status); |
1fd4f2a5 ED |
55 | |
56 | static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, | |
57 | unsigned long addr, | |
58 | unsigned long length) | |
59 | { | |
60 | unsigned long result = 0; | |
61 | ||
62 | switch (ioapic->ioregsel) { | |
63 | case IOAPIC_REG_VERSION: | |
64 | result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) | |
65 | | (IOAPIC_VERSION_ID & 0xff)); | |
66 | break; | |
67 | ||
68 | case IOAPIC_REG_APIC_ID: | |
69 | case IOAPIC_REG_ARB_ID: | |
70 | result = ((ioapic->id & 0xf) << 24); | |
71 | break; | |
72 | ||
73 | default: | |
74 | { | |
75 | u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; | |
76 | u64 redir_content; | |
77 | ||
a2c118bf AH |
78 | if (redir_index < IOAPIC_NUM_PINS) |
79 | redir_content = | |
80 | ioapic->redirtbl[redir_index].bits; | |
81 | else | |
82 | redir_content = ~0ULL; | |
1fd4f2a5 | 83 | |
1fd4f2a5 ED |
84 | result = (ioapic->ioregsel & 0x1) ? |
85 | (redir_content >> 32) & 0xffffffff : | |
86 | redir_content & 0xffffffff; | |
87 | break; | |
88 | } | |
89 | } | |
90 | ||
91 | return result; | |
92 | } | |
93 | ||
10606919 YZ |
94 | static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) |
95 | { | |
96 | ioapic->rtc_status.pending_eoi = 0; | |
97 | bitmap_zero(ioapic->rtc_status.dest_map, KVM_MAX_VCPUS); | |
98 | } | |
99 | ||
4009b249 PB |
100 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); |
101 | ||
102 | static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic) | |
103 | { | |
104 | if (WARN_ON(ioapic->rtc_status.pending_eoi < 0)) | |
105 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
106 | } | |
107 | ||
10606919 YZ |
108 | static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) |
109 | { | |
110 | bool new_val, old_val; | |
111 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
112 | union kvm_ioapic_redirect_entry *e; | |
113 | ||
114 | e = &ioapic->redirtbl[RTC_GSI]; | |
115 | if (!kvm_apic_match_dest(vcpu, NULL, 0, e->fields.dest_id, | |
116 | e->fields.dest_mode)) | |
117 | return; | |
118 | ||
119 | new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector); | |
120 | old_val = test_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
121 | ||
122 | if (new_val == old_val) | |
123 | return; | |
124 | ||
125 | if (new_val) { | |
126 | __set_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
127 | ioapic->rtc_status.pending_eoi++; | |
128 | } else { | |
129 | __clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map); | |
130 | ioapic->rtc_status.pending_eoi--; | |
4009b249 | 131 | rtc_status_pending_eoi_check_valid(ioapic); |
10606919 | 132 | } |
10606919 YZ |
133 | } |
134 | ||
135 | void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu) | |
136 | { | |
137 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
138 | ||
139 | spin_lock(&ioapic->lock); | |
140 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
141 | spin_unlock(&ioapic->lock); | |
142 | } | |
143 | ||
144 | static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic) | |
145 | { | |
146 | struct kvm_vcpu *vcpu; | |
147 | int i; | |
148 | ||
149 | if (RTC_GSI >= IOAPIC_NUM_PINS) | |
150 | return; | |
151 | ||
152 | rtc_irq_eoi_tracking_reset(ioapic); | |
153 | kvm_for_each_vcpu(i, vcpu, ioapic->kvm) | |
154 | __rtc_irq_eoi_tracking_restore_one(vcpu); | |
155 | } | |
156 | ||
2c2bf011 YZ |
157 | static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu) |
158 | { | |
4009b249 | 159 | if (test_and_clear_bit(vcpu->vcpu_id, ioapic->rtc_status.dest_map)) { |
2c2bf011 | 160 | --ioapic->rtc_status.pending_eoi; |
4009b249 PB |
161 | rtc_status_pending_eoi_check_valid(ioapic); |
162 | } | |
2c2bf011 YZ |
163 | } |
164 | ||
165 | static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic) | |
166 | { | |
167 | if (ioapic->rtc_status.pending_eoi > 0) | |
168 | return true; /* coalesced */ | |
169 | ||
170 | return false; | |
171 | } | |
172 | ||
44847dea PB |
173 | static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq, |
174 | int irq_level, bool line_status) | |
175 | { | |
176 | union kvm_ioapic_redirect_entry entry; | |
177 | u32 mask = 1 << irq; | |
178 | u32 old_irr; | |
179 | int edge, ret; | |
180 | ||
181 | entry = ioapic->redirtbl[irq]; | |
182 | edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG); | |
183 | ||
184 | if (!irq_level) { | |
185 | ioapic->irr &= ~mask; | |
186 | ret = 1; | |
187 | goto out; | |
188 | } | |
189 | ||
190 | /* | |
191 | * Return 0 for coalesced interrupts; for edge-triggered interrupts, | |
192 | * this only happens if a previous edge has not been delivered due | |
193 | * do masking. For level interrupts, the remote_irr field tells | |
194 | * us if the interrupt is waiting for an EOI. | |
195 | * | |
196 | * RTC is special: it is edge-triggered, but userspace likes to know | |
197 | * if it has been already ack-ed via EOI because coalesced RTC | |
198 | * interrupts lead to time drift in Windows guests. So we track | |
199 | * EOI manually for the RTC interrupt. | |
200 | */ | |
201 | if (irq == RTC_GSI && line_status && | |
202 | rtc_irq_check_coalesced(ioapic)) { | |
203 | ret = 0; | |
204 | goto out; | |
205 | } | |
206 | ||
207 | old_irr = ioapic->irr; | |
208 | ioapic->irr |= mask; | |
209 | if ((edge && old_irr == ioapic->irr) || | |
210 | (!edge && entry.fields.remote_irr)) { | |
211 | ret = 0; | |
212 | goto out; | |
213 | } | |
214 | ||
215 | ret = ioapic_service(ioapic, irq, line_status); | |
216 | ||
217 | out: | |
218 | trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0); | |
219 | return ret; | |
220 | } | |
221 | ||
673f7b42 PB |
222 | static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr) |
223 | { | |
224 | u32 idx; | |
225 | ||
226 | rtc_irq_eoi_tracking_reset(ioapic); | |
227 | for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS) | |
228 | ioapic_set_irq(ioapic, idx, 1, true); | |
229 | ||
230 | kvm_rtc_eoi_tracking_restore_all(ioapic); | |
231 | } | |
232 | ||
233 | ||
46a929bc AK |
234 | static void update_handled_vectors(struct kvm_ioapic *ioapic) |
235 | { | |
236 | DECLARE_BITMAP(handled_vectors, 256); | |
237 | int i; | |
238 | ||
239 | memset(handled_vectors, 0, sizeof(handled_vectors)); | |
240 | for (i = 0; i < IOAPIC_NUM_PINS; ++i) | |
241 | __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors); | |
242 | memcpy(ioapic->handled_vectors, handled_vectors, | |
243 | sizeof(handled_vectors)); | |
244 | smp_wmb(); | |
245 | } | |
246 | ||
cf9e65b7 YZ |
247 | void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap, |
248 | u32 *tmr) | |
c7c9c56c YZ |
249 | { |
250 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; | |
251 | union kvm_ioapic_redirect_entry *e; | |
c7c9c56c YZ |
252 | int index; |
253 | ||
254 | spin_lock(&ioapic->lock); | |
c7c9c56c YZ |
255 | for (index = 0; index < IOAPIC_NUM_PINS; index++) { |
256 | e = &ioapic->redirtbl[index]; | |
0f6c0a74 PB |
257 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG || |
258 | kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) || | |
259 | index == RTC_GSI) { | |
44944d4d | 260 | if (kvm_apic_match_dest(vcpu, NULL, 0, |
cf9e65b7 YZ |
261 | e->fields.dest_id, e->fields.dest_mode)) { |
262 | __set_bit(e->fields.vector, | |
263 | (unsigned long *)eoi_exit_bitmap); | |
264 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG) | |
265 | __set_bit(e->fields.vector, | |
266 | (unsigned long *)tmr); | |
267 | } | |
c7c9c56c YZ |
268 | } |
269 | } | |
270 | spin_unlock(&ioapic->lock); | |
271 | } | |
c7c9c56c | 272 | |
3d81bc7e | 273 | void kvm_vcpu_request_scan_ioapic(struct kvm *kvm) |
c7c9c56c YZ |
274 | { |
275 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
276 | ||
3d81bc7e | 277 | if (!ioapic) |
c7c9c56c | 278 | return; |
3d81bc7e | 279 | kvm_make_scan_ioapic_request(kvm); |
c7c9c56c YZ |
280 | } |
281 | ||
1fd4f2a5 ED |
282 | static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val) |
283 | { | |
284 | unsigned index; | |
75858a84 | 285 | bool mask_before, mask_after; |
70f93dae | 286 | union kvm_ioapic_redirect_entry *e; |
1fd4f2a5 ED |
287 | |
288 | switch (ioapic->ioregsel) { | |
289 | case IOAPIC_REG_VERSION: | |
290 | /* Writes are ignored. */ | |
291 | break; | |
292 | ||
293 | case IOAPIC_REG_APIC_ID: | |
294 | ioapic->id = (val >> 24) & 0xf; | |
295 | break; | |
296 | ||
297 | case IOAPIC_REG_ARB_ID: | |
298 | break; | |
299 | ||
300 | default: | |
301 | index = (ioapic->ioregsel - 0x10) >> 1; | |
302 | ||
e25e3ed5 | 303 | ioapic_debug("change redir index %x val %x\n", index, val); |
1fd4f2a5 ED |
304 | if (index >= IOAPIC_NUM_PINS) |
305 | return; | |
70f93dae GN |
306 | e = &ioapic->redirtbl[index]; |
307 | mask_before = e->fields.mask; | |
1fd4f2a5 | 308 | if (ioapic->ioregsel & 1) { |
70f93dae GN |
309 | e->bits &= 0xffffffff; |
310 | e->bits |= (u64) val << 32; | |
1fd4f2a5 | 311 | } else { |
70f93dae GN |
312 | e->bits &= ~0xffffffffULL; |
313 | e->bits |= (u32) val; | |
314 | e->fields.remote_irr = 0; | |
1fd4f2a5 | 315 | } |
46a929bc | 316 | update_handled_vectors(ioapic); |
70f93dae | 317 | mask_after = e->fields.mask; |
75858a84 | 318 | if (mask_before != mask_after) |
4a994358 | 319 | kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after); |
70f93dae | 320 | if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG |
b4a2f5e7 | 321 | && ioapic->irr & (1 << index)) |
aa2fbe6d | 322 | ioapic_service(ioapic, index, false); |
3d81bc7e | 323 | kvm_vcpu_request_scan_ioapic(ioapic->kvm); |
1fd4f2a5 ED |
324 | break; |
325 | } | |
326 | } | |
327 | ||
0b10a1c8 | 328 | static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status) |
a53c17d2 | 329 | { |
58c2dde1 GN |
330 | union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq]; |
331 | struct kvm_lapic_irq irqe; | |
2c2bf011 | 332 | int ret; |
a53c17d2 | 333 | |
0b10a1c8 PB |
334 | if (entry->fields.mask) |
335 | return -1; | |
336 | ||
a53c17d2 GN |
337 | ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x " |
338 | "vector=%x trig_mode=%x\n", | |
a38f84ca | 339 | entry->fields.dest_id, entry->fields.dest_mode, |
58c2dde1 GN |
340 | entry->fields.delivery_mode, entry->fields.vector, |
341 | entry->fields.trig_mode); | |
342 | ||
343 | irqe.dest_id = entry->fields.dest_id; | |
344 | irqe.vector = entry->fields.vector; | |
345 | irqe.dest_mode = entry->fields.dest_mode; | |
346 | irqe.trig_mode = entry->fields.trig_mode; | |
347 | irqe.delivery_mode = entry->fields.delivery_mode << 8; | |
348 | irqe.level = 1; | |
349 | irqe.shorthand = 0; | |
a53c17d2 | 350 | |
0bc830b0 PB |
351 | if (irqe.trig_mode == IOAPIC_EDGE_TRIG) |
352 | ioapic->irr &= ~(1 << irq); | |
353 | ||
2c2bf011 | 354 | if (irq == RTC_GSI && line_status) { |
4009b249 PB |
355 | /* |
356 | * pending_eoi cannot ever become negative (see | |
357 | * rtc_status_pending_eoi_check_valid) and the caller | |
358 | * ensures that it is only called if it is >= zero, namely | |
359 | * if rtc_irq_check_coalesced returns false). | |
360 | */ | |
2c2bf011 YZ |
361 | BUG_ON(ioapic->rtc_status.pending_eoi != 0); |
362 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, | |
363 | ioapic->rtc_status.dest_map); | |
5678de3f | 364 | ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret); |
2c2bf011 YZ |
365 | } else |
366 | ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL); | |
367 | ||
0b10a1c8 PB |
368 | if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG) |
369 | entry->fields.remote_irr = 1; | |
370 | ||
2c2bf011 | 371 | return ret; |
a53c17d2 GN |
372 | } |
373 | ||
1a577b72 | 374 | int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id, |
aa2fbe6d | 375 | int level, bool line_status) |
1fd4f2a5 | 376 | { |
28a6fdab MT |
377 | int ret, irq_level; |
378 | ||
379 | BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS); | |
1fd4f2a5 | 380 | |
46a47b1e | 381 | spin_lock(&ioapic->lock); |
28a6fdab MT |
382 | irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq], |
383 | irq_source_id, level); | |
44847dea | 384 | ret = ioapic_set_irq(ioapic, irq, irq_level, line_status); |
2c2bf011 | 385 | |
46a47b1e | 386 | spin_unlock(&ioapic->lock); |
eba0226b | 387 | |
4925663a | 388 | return ret; |
1fd4f2a5 ED |
389 | } |
390 | ||
1a577b72 MT |
391 | void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id) |
392 | { | |
393 | int i; | |
394 | ||
395 | spin_lock(&ioapic->lock); | |
396 | for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) | |
397 | __clear_bit(irq_source_id, &ioapic->irq_states[i]); | |
398 | spin_unlock(&ioapic->lock); | |
399 | } | |
400 | ||
184564ef ZH |
401 | static void kvm_ioapic_eoi_inject_work(struct work_struct *work) |
402 | { | |
403 | int i; | |
404 | struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic, | |
405 | eoi_inject.work); | |
406 | spin_lock(&ioapic->lock); | |
407 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
408 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
409 | ||
410 | if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG) | |
411 | continue; | |
412 | ||
413 | if (ioapic->irr & (1 << i) && !ent->fields.remote_irr) | |
414 | ioapic_service(ioapic, i, false); | |
415 | } | |
416 | spin_unlock(&ioapic->lock); | |
417 | } | |
418 | ||
419 | #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000 | |
420 | ||
1fcc7890 YZ |
421 | static void __kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, |
422 | struct kvm_ioapic *ioapic, int vector, int trigger_mode) | |
1fd4f2a5 | 423 | { |
eba0226b | 424 | int i; |
c806a6ad | 425 | struct kvm_lapic *apic = vcpu->arch.apic; |
eba0226b GN |
426 | |
427 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
428 | union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i]; | |
1fd4f2a5 | 429 | |
eba0226b GN |
430 | if (ent->fields.vector != vector) |
431 | continue; | |
1fd4f2a5 | 432 | |
2c2bf011 YZ |
433 | if (i == RTC_GSI) |
434 | rtc_irq_eoi(ioapic, vcpu); | |
eba0226b GN |
435 | /* |
436 | * We are dropping lock while calling ack notifiers because ack | |
437 | * notifier callbacks for assigned devices call into IOAPIC | |
438 | * recursively. Since remote_irr is cleared only after call | |
439 | * to notifiers if the same vector will be delivered while lock | |
440 | * is dropped it will be put into irr and will be delivered | |
441 | * after ack notifier returns. | |
442 | */ | |
46a47b1e | 443 | spin_unlock(&ioapic->lock); |
eba0226b | 444 | kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i); |
46a47b1e | 445 | spin_lock(&ioapic->lock); |
eba0226b | 446 | |
c806a6ad RK |
447 | if (trigger_mode != IOAPIC_LEVEL_TRIG || |
448 | kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) | |
eba0226b | 449 | continue; |
f5244726 | 450 | |
f5244726 MT |
451 | ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG); |
452 | ent->fields.remote_irr = 0; | |
184564ef ZH |
453 | if (!ent->fields.mask && (ioapic->irr & (1 << i))) { |
454 | ++ioapic->irq_eoi[i]; | |
455 | if (ioapic->irq_eoi[i] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) { | |
456 | /* | |
457 | * Real hardware does not deliver the interrupt | |
458 | * immediately during eoi broadcast, and this | |
459 | * lets a buggy guest make slow progress | |
460 | * even if it does not correctly handle a | |
461 | * level-triggered interrupt. Emulate this | |
462 | * behavior if we detect an interrupt storm. | |
463 | */ | |
464 | schedule_delayed_work(&ioapic->eoi_inject, HZ / 100); | |
465 | ioapic->irq_eoi[i] = 0; | |
466 | trace_kvm_ioapic_delayed_eoi_inj(ent->bits); | |
467 | } else { | |
468 | ioapic_service(ioapic, i, false); | |
469 | } | |
470 | } else { | |
471 | ioapic->irq_eoi[i] = 0; | |
472 | } | |
f5244726 | 473 | } |
1fd4f2a5 ED |
474 | } |
475 | ||
a0c9a822 MT |
476 | bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector) |
477 | { | |
478 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
479 | smp_rmb(); | |
480 | return test_bit(vector, ioapic->handled_vectors); | |
481 | } | |
482 | ||
1fcc7890 | 483 | void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode) |
4fa6b9c5 | 484 | { |
1fcc7890 | 485 | struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic; |
4fa6b9c5 | 486 | |
46a47b1e | 487 | spin_lock(&ioapic->lock); |
1fcc7890 | 488 | __kvm_ioapic_update_eoi(vcpu, ioapic, vector, trigger_mode); |
46a47b1e | 489 | spin_unlock(&ioapic->lock); |
4fa6b9c5 AK |
490 | } |
491 | ||
d76685c4 GH |
492 | static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev) |
493 | { | |
494 | return container_of(dev, struct kvm_ioapic, dev); | |
495 | } | |
496 | ||
bda9020e | 497 | static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr) |
1fd4f2a5 | 498 | { |
1fd4f2a5 ED |
499 | return ((addr >= ioapic->base_address && |
500 | (addr < ioapic->base_address + IOAPIC_MEM_LENGTH))); | |
501 | } | |
502 | ||
bda9020e MT |
503 | static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len, |
504 | void *val) | |
1fd4f2a5 | 505 | { |
d76685c4 | 506 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 507 | u32 result; |
bda9020e MT |
508 | if (!ioapic_in_range(ioapic, addr)) |
509 | return -EOPNOTSUPP; | |
1fd4f2a5 | 510 | |
e25e3ed5 | 511 | ioapic_debug("addr %lx\n", (unsigned long)addr); |
1fd4f2a5 ED |
512 | ASSERT(!(addr & 0xf)); /* check alignment */ |
513 | ||
514 | addr &= 0xff; | |
46a47b1e | 515 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
516 | switch (addr) { |
517 | case IOAPIC_REG_SELECT: | |
518 | result = ioapic->ioregsel; | |
519 | break; | |
520 | ||
521 | case IOAPIC_REG_WINDOW: | |
522 | result = ioapic_read_indirect(ioapic, addr, len); | |
523 | break; | |
524 | ||
525 | default: | |
526 | result = 0; | |
527 | break; | |
528 | } | |
46a47b1e | 529 | spin_unlock(&ioapic->lock); |
eba0226b | 530 | |
1fd4f2a5 ED |
531 | switch (len) { |
532 | case 8: | |
533 | *(u64 *) val = result; | |
534 | break; | |
535 | case 1: | |
536 | case 2: | |
537 | case 4: | |
538 | memcpy(val, (char *)&result, len); | |
539 | break; | |
540 | default: | |
541 | printk(KERN_WARNING "ioapic: wrong length %d\n", len); | |
542 | } | |
bda9020e | 543 | return 0; |
1fd4f2a5 ED |
544 | } |
545 | ||
bda9020e MT |
546 | static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, |
547 | const void *val) | |
1fd4f2a5 | 548 | { |
d76685c4 | 549 | struct kvm_ioapic *ioapic = to_ioapic(this); |
1fd4f2a5 | 550 | u32 data; |
bda9020e MT |
551 | if (!ioapic_in_range(ioapic, addr)) |
552 | return -EOPNOTSUPP; | |
1fd4f2a5 | 553 | |
e25e3ed5 LV |
554 | ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n", |
555 | (void*)addr, len, val); | |
1fd4f2a5 | 556 | ASSERT(!(addr & 0xf)); /* check alignment */ |
60eead79 | 557 | |
d77fe635 JS |
558 | switch (len) { |
559 | case 8: | |
560 | case 4: | |
1fd4f2a5 | 561 | data = *(u32 *) val; |
d77fe635 JS |
562 | break; |
563 | case 2: | |
564 | data = *(u16 *) val; | |
565 | break; | |
566 | case 1: | |
567 | data = *(u8 *) val; | |
568 | break; | |
569 | default: | |
1fd4f2a5 | 570 | printk(KERN_WARNING "ioapic: Unsupported size %d\n", len); |
eba0226b | 571 | return 0; |
1fd4f2a5 ED |
572 | } |
573 | ||
574 | addr &= 0xff; | |
46a47b1e | 575 | spin_lock(&ioapic->lock); |
1fd4f2a5 ED |
576 | switch (addr) { |
577 | case IOAPIC_REG_SELECT: | |
d77fe635 | 578 | ioapic->ioregsel = data & 0xFF; /* 8-bit register */ |
1fd4f2a5 ED |
579 | break; |
580 | ||
581 | case IOAPIC_REG_WINDOW: | |
582 | ioapic_write_indirect(ioapic, data); | |
583 | break; | |
584 | ||
585 | default: | |
586 | break; | |
587 | } | |
46a47b1e | 588 | spin_unlock(&ioapic->lock); |
bda9020e | 589 | return 0; |
1fd4f2a5 ED |
590 | } |
591 | ||
7940876e | 592 | static void kvm_ioapic_reset(struct kvm_ioapic *ioapic) |
8c392696 ED |
593 | { |
594 | int i; | |
595 | ||
184564ef | 596 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
8c392696 ED |
597 | for (i = 0; i < IOAPIC_NUM_PINS; i++) |
598 | ioapic->redirtbl[i].fields.mask = 1; | |
599 | ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS; | |
600 | ioapic->ioregsel = 0; | |
601 | ioapic->irr = 0; | |
602 | ioapic->id = 0; | |
184564ef | 603 | memset(ioapic->irq_eoi, 0x00, IOAPIC_NUM_PINS); |
10606919 | 604 | rtc_irq_eoi_tracking_reset(ioapic); |
46a929bc | 605 | update_handled_vectors(ioapic); |
8c392696 ED |
606 | } |
607 | ||
d76685c4 GH |
608 | static const struct kvm_io_device_ops ioapic_mmio_ops = { |
609 | .read = ioapic_mmio_read, | |
610 | .write = ioapic_mmio_write, | |
d76685c4 GH |
611 | }; |
612 | ||
1fd4f2a5 ED |
613 | int kvm_ioapic_init(struct kvm *kvm) |
614 | { | |
615 | struct kvm_ioapic *ioapic; | |
090b7aff | 616 | int ret; |
1fd4f2a5 ED |
617 | |
618 | ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL); | |
619 | if (!ioapic) | |
620 | return -ENOMEM; | |
46a47b1e | 621 | spin_lock_init(&ioapic->lock); |
184564ef | 622 | INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work); |
d7deeeb0 | 623 | kvm->arch.vioapic = ioapic; |
8c392696 | 624 | kvm_ioapic_reset(ioapic); |
d76685c4 | 625 | kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops); |
1fd4f2a5 | 626 | ioapic->kvm = kvm; |
79fac95e | 627 | mutex_lock(&kvm->slots_lock); |
743eeb0b SL |
628 | ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address, |
629 | IOAPIC_MEM_LENGTH, &ioapic->dev); | |
79fac95e | 630 | mutex_unlock(&kvm->slots_lock); |
1ae77bad WY |
631 | if (ret < 0) { |
632 | kvm->arch.vioapic = NULL; | |
090b7aff | 633 | kfree(ioapic); |
1ae77bad | 634 | } |
090b7aff GH |
635 | |
636 | return ret; | |
1fd4f2a5 | 637 | } |
75858a84 | 638 | |
72bb2fcd WY |
639 | void kvm_ioapic_destroy(struct kvm *kvm) |
640 | { | |
641 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; | |
642 | ||
184564ef | 643 | cancel_delayed_work_sync(&ioapic->eoi_inject); |
72bb2fcd WY |
644 | if (ioapic) { |
645 | kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev); | |
646 | kvm->arch.vioapic = NULL; | |
647 | kfree(ioapic); | |
648 | } | |
649 | } | |
650 | ||
eba0226b GN |
651 | int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) |
652 | { | |
653 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
654 | if (!ioapic) | |
655 | return -EINVAL; | |
656 | ||
46a47b1e | 657 | spin_lock(&ioapic->lock); |
eba0226b | 658 | memcpy(state, ioapic, sizeof(struct kvm_ioapic_state)); |
46a47b1e | 659 | spin_unlock(&ioapic->lock); |
eba0226b GN |
660 | return 0; |
661 | } | |
662 | ||
663 | int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state) | |
664 | { | |
665 | struct kvm_ioapic *ioapic = ioapic_irqchip(kvm); | |
666 | if (!ioapic) | |
667 | return -EINVAL; | |
668 | ||
46a47b1e | 669 | spin_lock(&ioapic->lock); |
eba0226b | 670 | memcpy(ioapic, state, sizeof(struct kvm_ioapic_state)); |
673f7b42 | 671 | ioapic->irr = 0; |
46a929bc | 672 | update_handled_vectors(ioapic); |
3d81bc7e | 673 | kvm_vcpu_request_scan_ioapic(kvm); |
673f7b42 | 674 | kvm_ioapic_inject_all(ioapic, state->irr); |
46a47b1e | 675 | spin_unlock(&ioapic->lock); |
eba0226b GN |
676 | return 0; |
677 | } |