[deliverable/linux.git] / arch / x86 / kvm / irq_comm.c

/*
 * irq_comm.c: Common API for in kernel interrupt controller
 * Copyright (c) 2007, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 * Authors:
 *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
 *
 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
 */

#include <linux/kvm_host.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <trace/events/kvm.h>

#include <asm/msidef.h>

#include "irq.h"

#include "ioapic.h"

#include "lapic.h"

static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
			   struct kvm *kvm, int irq_source_id, int level,
			   bool line_status)
{
	struct kvm_pic *pic = pic_irqchip(kvm);
	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
}

static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
			      struct kvm *kvm, int irq_source_id, int level,
			      bool line_status)
{
	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
				line_status);
}

int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
		struct kvm_lapic_irq *irq, unsigned long *dest_map)
{
	int i, r = -1;
	struct kvm_vcpu *vcpu, *lowest = NULL;

	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
			kvm_lowest_prio_delivery(irq)) {
		printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
		irq->delivery_mode = APIC_DM_FIXED;
	}

	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
		return r;

	kvm_for_each_vcpu(i, vcpu, kvm) {
		if (!kvm_apic_present(vcpu))
			continue;

		if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
					irq->dest_id, irq->dest_mode))
			continue;

		if (!kvm_lowest_prio_delivery(irq)) {
			if (r < 0)
				r = 0;
			r += kvm_apic_set_irq(vcpu, irq, dest_map);
		} else if (kvm_lapic_enabled(vcpu)) {
			if (!lowest)
				lowest = vcpu;
			else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
				lowest = vcpu;
		}
	}

	if (lowest)
		r = kvm_apic_set_irq(lowest, irq, dest_map);

	return r;
}

void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
		     struct kvm_lapic_irq *irq)
{
	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);

	irq->dest_id = (e->msi.address_lo &
			MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
	irq->vector = (e->msi.data &
			MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
	irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	irq->delivery_mode = e->msi.data & 0x700;
	irq->msi_redir_hint = ((e->msi.address_lo
		& MSI_ADDR_REDIRECTION_LOWPRI) > 0);
	irq->level = 1;
	irq->shorthand = 0;
}
EXPORT_SYMBOL_GPL(kvm_set_msi_irq);

int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
		struct kvm *kvm, int irq_source_id, int level, bool line_status)
{
	struct kvm_lapic_irq irq;

	if (!level)
		return -1;

	kvm_set_msi_irq(e, &irq);

	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
}


int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
			      struct kvm *kvm, int irq_source_id, int level,
			      bool line_status)
{
	struct kvm_lapic_irq irq;
	int r;

	if (unlikely(e->type != KVM_IRQ_ROUTING_MSI))
		return -EWOULDBLOCK;

	kvm_set_msi_irq(e, &irq);

	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
		return r;
	else
		return -EWOULDBLOCK;
}

int kvm_request_irq_source_id(struct kvm *kvm)
{
	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
	int irq_source_id;

	mutex_lock(&kvm->irq_lock);
	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);

	if (irq_source_id >= BITS_PER_LONG) {
		printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
		irq_source_id = -EFAULT;
		goto unlock;
	}

	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
	set_bit(irq_source_id, bitmap);
unlock:
	mutex_unlock(&kvm->irq_lock);

	return irq_source_id;
}

void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
{
	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);

	mutex_lock(&kvm->irq_lock);
	if (irq_source_id < 0 ||
	    irq_source_id >= BITS_PER_LONG) {
		printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
		goto unlock;
	}
	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
	if (!ioapic_in_kernel(kvm))
		goto unlock;

	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
	kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
unlock:
	mutex_unlock(&kvm->irq_lock);
}

void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
				    struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	kimn->irq = irq;
	hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
	mutex_unlock(&kvm->irq_lock);
}

void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
				      struct kvm_irq_mask_notifier *kimn)
{
	mutex_lock(&kvm->irq_lock);
	hlist_del_rcu(&kimn->link);
	mutex_unlock(&kvm->irq_lock);
	synchronize_srcu(&kvm->irq_srcu);
}

void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
			     bool mask)
{
	struct kvm_irq_mask_notifier *kimn;
	int idx, gsi;

	idx = srcu_read_lock(&kvm->irq_srcu);
	gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
	if (gsi != -1)
		hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
			if (kimn->irq == gsi)
				kimn->func(kimn, mask);
	srcu_read_unlock(&kvm->irq_srcu, idx);
}

int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e,
			  const struct kvm_irq_routing_entry *ue)
{
	int r = -EINVAL;
	int delta;
	unsigned max_pin;

	switch (ue->type) {
	case KVM_IRQ_ROUTING_IRQCHIP:
		delta = 0;
		switch (ue->u.irqchip.irqchip) {
		case KVM_IRQCHIP_PIC_MASTER:
			e->set = kvm_set_pic_irq;
			max_pin = PIC_NUM_PINS;
			break;
		case KVM_IRQCHIP_PIC_SLAVE:
			e->set = kvm_set_pic_irq;
			max_pin = PIC_NUM_PINS;
			delta = 8;
			break;
		case KVM_IRQCHIP_IOAPIC:
			max_pin = KVM_IOAPIC_NUM_PINS;
			e->set = kvm_set_ioapic_irq;
			break;
		default:
			goto out;
		}
		e->irqchip.irqchip = ue->u.irqchip.irqchip;
		e->irqchip.pin = ue->u.irqchip.pin + delta;
		if (e->irqchip.pin >= max_pin)
			goto out;
		break;
	case KVM_IRQ_ROUTING_MSI:
		e->set = kvm_set_msi;
		e->msi.address_lo = ue->u.msi.address_lo;
		e->msi.address_hi = ue->u.msi.address_hi;
		e->msi.data = ue->u.msi.data;
		break;
	default:
		goto out;
	}

	r = 0;
out:
	return r;
}

bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
			     struct kvm_vcpu **dest_vcpu)
{
	int i, r = 0;
	struct kvm_vcpu *vcpu;

	if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu))
		return true;

	kvm_for_each_vcpu(i, vcpu, kvm) {
		if (!kvm_apic_present(vcpu))
			continue;

		if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand,
					irq->dest_id, irq->dest_mode))
			continue;

		if (++r == 2)
			return false;

		*dest_vcpu = vcpu;
	}

	return r == 1;
}
EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu);

#define IOAPIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)

#define PIC_ROUTING_ENTRY(irq) \
	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP,	\
	  .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
#define ROUTING_ENTRY2(irq) \
	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)

static const struct kvm_irq_routing_entry default_routing[] = {
	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
};

int kvm_setup_default_irq_routing(struct kvm *kvm)
{
	return kvm_set_irq_routing(kvm, default_routing,
				   ARRAY_SIZE(default_routing), 0);
}

static const struct kvm_irq_routing_entry empty_routing[] = {};

int kvm_setup_empty_irq_routing(struct kvm *kvm)
{
	return kvm_set_irq_routing(kvm, empty_routing, 0, 0);
}

void kvm_arch_irq_routing_update(struct kvm *kvm)
{
	if (ioapic_in_kernel(kvm) || !irqchip_in_kernel(kvm))
		return;
	kvm_make_scan_ioapic_request(kvm);
}

void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
{
	struct kvm *kvm = vcpu->kvm;
	struct kvm_kernel_irq_routing_entry *entry;
	struct kvm_irq_routing_table *table;
	u32 i, nr_ioapic_pins;
	int idx;

	/* kvm->irq_routing must be read after clearing
	 * KVM_SCAN_IOAPIC. */
	smp_mb();
	idx = srcu_read_lock(&kvm->irq_srcu);
	table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
	nr_ioapic_pins = min_t(u32, table->nr_rt_entries,
			       kvm->arch.nr_reserved_ioapic_pins);
	for (i = 0; i < nr_ioapic_pins; ++i) {
		hlist_for_each_entry(entry, &table->map[i], link) {
			u32 dest_id, dest_mode;
			bool level;

			if (entry->type != KVM_IRQ_ROUTING_MSI)
				continue;
			dest_id = (entry->msi.address_lo >> 12) & 0xff;
			dest_mode = (entry->msi.address_lo >> 2) & 0x1;
			level = entry->msi.data & MSI_DATA_TRIGGER_LEVEL;
			if (level && kvm_apic_match_dest(vcpu, NULL, 0,
						dest_id, dest_mode)) {
				u32 vector = entry->msi.data & 0xff;

				__set_bit(vector,
					  (unsigned long *) eoi_exit_bitmap);
			}
		}
	}
	srcu_read_unlock(&kvm->irq_srcu, idx);
}
Commit	Line	Data
3de42dc0 XZ	1	/*
	2	* irq_comm.c: Common API for in kernel interrupt controller
	3	* Copyright (c) 2007, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	16	* Place - Suite 330, Boston, MA 02111-1307 USA.
	17	* Authors:
	18	* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
	19	*
9611c187	20	* Copyright 2010 Red Hat, Inc. and/or its affiliates.
3de42dc0 XZ	21	*/
	22
	23	#include <linux/kvm_host.h>
5a0e3ad6	24	#include <linux/slab.h>
c7c9c56c	25	#include <linux/export.h>
229456fc	26	#include <trace/events/kvm.h>
79950e10	27
79950e10	28	#include <asm/msidef.h>
79950e10	29
3de42dc0 XZ	30	#include "irq.h"
	31
	32	#include "ioapic.h"
	33
d1ebdbf9 JS	34	#include "lapic.h"
d1ebdbf9 JS	35
4925663a	36	static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d YZ	37	struct kvm *kvm, int irq_source_id, int level,
aa2fbe6d YZ	38	bool line_status)
399ec807	39	{
1a6e4a8c	40	struct kvm_pic *pic = pic_irqchip(kvm);
1a577b72	41	return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
399ec807 AK	42	}
399ec807 AK	43
4925663a	44	static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d YZ	45	struct kvm *kvm, int irq_source_id, int level,
aa2fbe6d YZ	46	bool line_status)
399ec807	47	{
1a6e4a8c	48	struct kvm_ioapic *ioapic = kvm->arch.vioapic;
aa2fbe6d YZ	49	return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
aa2fbe6d YZ	50	line_status);
399ec807 AK	51	}
399ec807 AK	52
58c2dde1	53	int kvm_irq_delivery_to_apic(struct kvm kvm, struct kvm_lapic src,
b4f2225c	54	struct kvm_lapic_irq irq, unsigned long dest_map)
58c2dde1 GN	55	{
	56	int i, r = -1;
	57	struct kvm_vcpu vcpu, lowest = NULL;
	58
	59	if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
d1ebdbf9	60	kvm_lowest_prio_delivery(irq)) {
343f94fe	61	printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
1e08ec4a GN	62	irq->delivery_mode = APIC_DM_FIXED;
	63	}
	64
b4f2225c	65	if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
1e08ec4a	66	return r;
343f94fe	67
988a2cae GN	68	kvm_for_each_vcpu(i, vcpu, kvm) {
988a2cae GN	69	if (!kvm_apic_present(vcpu))
343f94fe GN	70	continue;
343f94fe GN	71
58c2dde1 GN	72	if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
58c2dde1 GN	73	irq->dest_id, irq->dest_mode))
343f94fe GN	74	continue;
343f94fe GN	75
d1ebdbf9	76	if (!kvm_lowest_prio_delivery(irq)) {
58c2dde1 GN	77	if (r < 0)
58c2dde1 GN	78	r = 0;
b4f2225c	79	r += kvm_apic_set_irq(vcpu, irq, dest_map);
aefd18f0	80	} else if (kvm_lapic_enabled(vcpu)) {
58c2dde1 GN	81	if (!lowest)
	82	lowest = vcpu;
	83	else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
	84	lowest = vcpu;
e1035715	85	}
343f94fe GN	86	}
343f94fe GN	87
58c2dde1	88	if (lowest)
b4f2225c	89	r = kvm_apic_set_irq(lowest, irq, dest_map);
58c2dde1 GN	90
58c2dde1 GN	91	return r;
116191b6 SY	92	}
116191b6 SY	93
d84f1e07 FW	94	void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
d84f1e07 FW	95	struct kvm_lapic_irq *irq)
01f21880 MT	96	{
	97	trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);
	98
	99	irq->dest_id = (e->msi.address_lo &
	100	MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
	101	irq->vector = (e->msi.data &
	102	MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
	103	irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
	104	irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
	105	irq->delivery_mode = e->msi.data & 0x700;
93bbf0b8 JS	106	irq->msi_redir_hint = ((e->msi.address_lo
93bbf0b8 JS	107	& MSI_ADDR_REDIRECTION_LOWPRI) > 0);
01f21880 MT	108	irq->level = 1;
01f21880 MT	109	irq->shorthand = 0;
01f21880	110	}
d84f1e07	111	EXPORT_SYMBOL_GPL(kvm_set_msi_irq);
01f21880	112
bd2b53b2	113	int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
aa2fbe6d	114	struct kvm *kvm, int irq_source_id, int level, bool line_status)
79950e10	115	{
58c2dde1	116	struct kvm_lapic_irq irq;
79950e10	117
1a6e4a8c GN	118	if (!level)
	119	return -1;
	120
01f21880	121	kvm_set_msi_irq(e, &irq);
116191b6	122
b4f2225c	123	return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
79950e10 SY	124	}
79950e10 SY	125
01f21880	126
b97e6de9 PB	127	int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
	128	struct kvm *kvm, int irq_source_id, int level,
	129	bool line_status)
01f21880 MT	130	{
	131	struct kvm_lapic_irq irq;
	132	int r;
	133
b97e6de9 PB	134	if (unlikely(e->type != KVM_IRQ_ROUTING_MSI))
	135	return -EWOULDBLOCK;
	136
01f21880 MT	137	kvm_set_msi_irq(e, &irq);
01f21880 MT	138
b4f2225c	139	if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
01f21880 MT	140	return r;
	141	else
	142	return -EWOULDBLOCK;
	143	}
	144
5550af4d SY	145	int kvm_request_irq_source_id(struct kvm *kvm)
	146	{
	147	unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
fa40a821 MT	148	int irq_source_id;
	149
	150	mutex_lock(&kvm->irq_lock);
cd5a2685	151	irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
61552367	152
cd5a2685	153	if (irq_source_id >= BITS_PER_LONG) {
5550af4d	154	printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
0c6ddceb JS	155	irq_source_id = -EFAULT;
0c6ddceb JS	156	goto unlock;
61552367 MM	157	}
	158
	159	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
7a84428a	160	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
61552367	161	set_bit(irq_source_id, bitmap);
0c6ddceb	162	unlock:
fa40a821	163	mutex_unlock(&kvm->irq_lock);
61552367	164
5550af4d SY	165	return irq_source_id;
	166	}
	167
	168	void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
	169	{
61552367	170	ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
7a84428a	171	ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
61552367	172
fa40a821	173	mutex_lock(&kvm->irq_lock);
61552367	174	if (irq_source_id < 0 \|\|
cd5a2685	175	irq_source_id >= BITS_PER_LONG) {
5550af4d	176	printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
0c6ddceb	177	goto unlock;
5550af4d	178	}
e50212bb	179	clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
49df6397	180	if (!ioapic_in_kernel(kvm))
e50212bb MT	181	goto unlock;
e50212bb MT	182
1a577b72	183	kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
1a577b72	184	kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
0c6ddceb	185	unlock:
fa40a821	186	mutex_unlock(&kvm->irq_lock);
5550af4d	187	}
75858a84 AK	188
	189	void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
	190	struct kvm_irq_mask_notifier *kimn)
	191	{
fa40a821	192	mutex_lock(&kvm->irq_lock);
75858a84	193	kimn->irq = irq;
6ef768fa	194	hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
fa40a821	195	mutex_unlock(&kvm->irq_lock);
75858a84 AK	196	}
	197
	198	void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
	199	struct kvm_irq_mask_notifier *kimn)
	200	{
fa40a821	201	mutex_lock(&kvm->irq_lock);
280aa177	202	hlist_del_rcu(&kimn->link);
fa40a821	203	mutex_unlock(&kvm->irq_lock);
719d93cd	204	synchronize_srcu(&kvm->irq_srcu);
75858a84 AK	205	}
75858a84 AK	206
4a994358 GN	207	void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
4a994358 GN	208	bool mask)
75858a84 AK	209	{
75858a84 AK	210	struct kvm_irq_mask_notifier *kimn;
719d93cd	211	int idx, gsi;
75858a84	212
719d93cd	213	idx = srcu_read_lock(&kvm->irq_srcu);
9957c86d	214	gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
4a994358	215	if (gsi != -1)
6ef768fa	216	hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
4a994358 GN	217	if (kimn->irq == gsi)
4a994358 GN	218	kimn->func(kimn, mask);
719d93cd	219	srcu_read_unlock(&kvm->irq_srcu, idx);
75858a84 AK	220	}
75858a84 AK	221
8ba918d4	222	int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e,
e8cde093	223	const struct kvm_irq_routing_entry *ue)
399ec807 AK	224	{
	225	int r = -EINVAL;
	226	int delta;
d72118ce	227	unsigned max_pin;
46e624b9	228
399ec807 AK	229	switch (ue->type) {
	230	case KVM_IRQ_ROUTING_IRQCHIP:
	231	delta = 0;
	232	switch (ue->u.irqchip.irqchip) {
	233	case KVM_IRQCHIP_PIC_MASTER:
	234	e->set = kvm_set_pic_irq;
93b6547e	235	max_pin = PIC_NUM_PINS;
399ec807 AK	236	break;
399ec807 AK	237	case KVM_IRQCHIP_PIC_SLAVE:
4925663a	238	e->set = kvm_set_pic_irq;
93b6547e	239	max_pin = PIC_NUM_PINS;
399ec807 AK	240	delta = 8;
	241	break;
	242	case KVM_IRQCHIP_IOAPIC:
d72118ce	243	max_pin = KVM_IOAPIC_NUM_PINS;
efbc100c	244	e->set = kvm_set_ioapic_irq;
399ec807 AK	245	break;
	246	default:
	247	goto out;
	248	}
	249	e->irqchip.irqchip = ue->u.irqchip.irqchip;
	250	e->irqchip.pin = ue->u.irqchip.pin + delta;
d72118ce	251	if (e->irqchip.pin >= max_pin)
3e71f88b	252	goto out;
399ec807	253	break;
79950e10 SY	254	case KVM_IRQ_ROUTING_MSI:
	255	e->set = kvm_set_msi;
	256	e->msi.address_lo = ue->u.msi.address_lo;
	257	e->msi.address_hi = ue->u.msi.address_hi;
	258	e->msi.data = ue->u.msi.data;
	259	break;
399ec807 AK	260	default:
	261	goto out;
	262	}
46e624b9	263
399ec807 AK	264	r = 0;
	265	out:
	266	return r;
	267	}
	268
8feb4a04 FW	269	bool kvm_intr_is_single_vcpu(struct kvm kvm, struct kvm_lapic_irq irq,
	270	struct kvm_vcpu **dest_vcpu)
	271	{
	272	int i, r = 0;
	273	struct kvm_vcpu *vcpu;
	274
	275	if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu))
	276	return true;
	277
	278	kvm_for_each_vcpu(i, vcpu, kvm) {
	279	if (!kvm_apic_present(vcpu))
	280	continue;
	281
	282	if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand,
	283	irq->dest_id, irq->dest_mode))
	284	continue;
	285
	286	if (++r == 2)
	287	return false;
	288
	289	*dest_vcpu = vcpu;
	290	}
	291
	292	return r == 1;
	293	}
	294	EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu);
	295
399ec807 AK	296	#define IOAPIC_ROUTING_ENTRY(irq) \
399ec807 AK	297	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
25f97ff4	298	.u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
399ec807 AK	299	#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
399ec807 AK	300
3bf58e9a	301	#define PIC_ROUTING_ENTRY(irq) \
399ec807	302	{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
25f97ff4	303	.u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
3bf58e9a	304	#define ROUTING_ENTRY2(irq) \
399ec807	305	IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
399ec807 AK	306
	307	static const struct kvm_irq_routing_entry default_routing[] = {
	308	ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
	309	ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
	310	ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
	311	ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
	312	ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
	313	ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
	314	ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
	315	ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
	316	ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
	317	ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
	318	ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
	319	ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
399ec807 AK	320	};
	321
	322	int kvm_setup_default_irq_routing(struct kvm *kvm)
	323	{
	324	return kvm_set_irq_routing(kvm, default_routing,
	325	ARRAY_SIZE(default_routing), 0);
	326	}
49df6397 SR	327
	328	static const struct kvm_irq_routing_entry empty_routing[] = {};
	329
	330	int kvm_setup_empty_irq_routing(struct kvm *kvm)
	331	{
	332	return kvm_set_irq_routing(kvm, empty_routing, 0, 0);
	333	}
b053b2ae SR	334
	335	void kvm_arch_irq_routing_update(struct kvm *kvm)
	336	{
	337	if (ioapic_in_kernel(kvm) \|\| !irqchip_in_kernel(kvm))
	338	return;
	339	kvm_make_scan_ioapic_request(kvm);
	340	}
	341
	342	void kvm_scan_ioapic_routes(struct kvm_vcpu vcpu, u64 eoi_exit_bitmap)
	343	{
	344	struct kvm *kvm = vcpu->kvm;
	345	struct kvm_kernel_irq_routing_entry *entry;
	346	struct kvm_irq_routing_table *table;
	347	u32 i, nr_ioapic_pins;
	348	int idx;
	349
	350	/* kvm->irq_routing must be read after clearing
	351	* KVM_SCAN_IOAPIC. */
	352	smp_mb();
	353	idx = srcu_read_lock(&kvm->irq_srcu);
	354	table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
	355	nr_ioapic_pins = min_t(u32, table->nr_rt_entries,
	356	kvm->arch.nr_reserved_ioapic_pins);
	357	for (i = 0; i < nr_ioapic_pins; ++i) {
	358	hlist_for_each_entry(entry, &table->map[i], link) {
	359	u32 dest_id, dest_mode;
13db7734	360	bool level;
b053b2ae SR	361
	362	if (entry->type != KVM_IRQ_ROUTING_MSI)
	363	continue;
	364	dest_id = (entry->msi.address_lo >> 12) & 0xff;
	365	dest_mode = (entry->msi.address_lo >> 2) & 0x1;
13db7734 RK	366	level = entry->msi.data & MSI_DATA_TRIGGER_LEVEL;
	367	if (level && kvm_apic_match_dest(vcpu, NULL, 0,
	368	dest_id, dest_mode)) {
b053b2ae SR	369	u32 vector = entry->msi.data & 0xff;
	370
	371	__set_bit(vector,
	372	(unsigned long *) eoi_exit_bitmap);
	373	}
	374	}
	375	}
	376	srcu_read_unlock(&kvm->irq_srcu, idx);
	377	}