Commit | Line | Data |
---|---|---|
3de42dc0 XZ |
1 | /* |
2 | * irq_comm.c: Common API for in kernel interrupt controller | |
3 | * Copyright (c) 2007, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * Authors: | |
18 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
19 | * | |
9611c187 | 20 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
3de42dc0 XZ |
21 | */ |
22 | ||
23 | #include <linux/kvm_host.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c7c9c56c | 25 | #include <linux/export.h> |
229456fc | 26 | #include <trace/events/kvm.h> |
79950e10 | 27 | |
79950e10 | 28 | #include <asm/msidef.h> |
79950e10 | 29 | |
3de42dc0 XZ |
30 | #include "irq.h" |
31 | ||
32 | #include "ioapic.h" | |
33 | ||
d1ebdbf9 JS |
34 | #include "lapic.h" |
35 | ||
4925663a | 36 | static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d YZ |
37 | struct kvm *kvm, int irq_source_id, int level, |
38 | bool line_status) | |
399ec807 | 39 | { |
1a6e4a8c | 40 | struct kvm_pic *pic = pic_irqchip(kvm); |
1a577b72 | 41 | return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level); |
399ec807 AK |
42 | } |
43 | ||
4925663a | 44 | static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d YZ |
45 | struct kvm *kvm, int irq_source_id, int level, |
46 | bool line_status) | |
399ec807 | 47 | { |
1a6e4a8c | 48 | struct kvm_ioapic *ioapic = kvm->arch.vioapic; |
aa2fbe6d YZ |
49 | return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level, |
50 | line_status); | |
399ec807 AK |
51 | } |
52 | ||
58c2dde1 | 53 | int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src, |
b4f2225c | 54 | struct kvm_lapic_irq *irq, unsigned long *dest_map) |
58c2dde1 GN |
55 | { |
56 | int i, r = -1; | |
57 | struct kvm_vcpu *vcpu, *lowest = NULL; | |
58 | ||
59 | if (irq->dest_mode == 0 && irq->dest_id == 0xff && | |
d1ebdbf9 | 60 | kvm_lowest_prio_delivery(irq)) { |
343f94fe | 61 | printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n"); |
1e08ec4a GN |
62 | irq->delivery_mode = APIC_DM_FIXED; |
63 | } | |
64 | ||
b4f2225c | 65 | if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map)) |
1e08ec4a | 66 | return r; |
343f94fe | 67 | |
988a2cae GN |
68 | kvm_for_each_vcpu(i, vcpu, kvm) { |
69 | if (!kvm_apic_present(vcpu)) | |
343f94fe GN |
70 | continue; |
71 | ||
58c2dde1 GN |
72 | if (!kvm_apic_match_dest(vcpu, src, irq->shorthand, |
73 | irq->dest_id, irq->dest_mode)) | |
343f94fe GN |
74 | continue; |
75 | ||
d1ebdbf9 | 76 | if (!kvm_lowest_prio_delivery(irq)) { |
58c2dde1 GN |
77 | if (r < 0) |
78 | r = 0; | |
b4f2225c | 79 | r += kvm_apic_set_irq(vcpu, irq, dest_map); |
aefd18f0 | 80 | } else if (kvm_lapic_enabled(vcpu)) { |
58c2dde1 GN |
81 | if (!lowest) |
82 | lowest = vcpu; | |
83 | else if (kvm_apic_compare_prio(vcpu, lowest) < 0) | |
84 | lowest = vcpu; | |
e1035715 | 85 | } |
343f94fe GN |
86 | } |
87 | ||
58c2dde1 | 88 | if (lowest) |
b4f2225c | 89 | r = kvm_apic_set_irq(lowest, irq, dest_map); |
58c2dde1 GN |
90 | |
91 | return r; | |
116191b6 SY |
92 | } |
93 | ||
01f21880 MT |
94 | static inline void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e, |
95 | struct kvm_lapic_irq *irq) | |
96 | { | |
97 | trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data); | |
98 | ||
99 | irq->dest_id = (e->msi.address_lo & | |
100 | MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; | |
101 | irq->vector = (e->msi.data & | |
102 | MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; | |
103 | irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo; | |
104 | irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data; | |
105 | irq->delivery_mode = e->msi.data & 0x700; | |
93bbf0b8 JS |
106 | irq->msi_redir_hint = ((e->msi.address_lo |
107 | & MSI_ADDR_REDIRECTION_LOWPRI) > 0); | |
01f21880 MT |
108 | irq->level = 1; |
109 | irq->shorthand = 0; | |
01f21880 MT |
110 | } |
111 | ||
bd2b53b2 | 112 | int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, |
aa2fbe6d | 113 | struct kvm *kvm, int irq_source_id, int level, bool line_status) |
79950e10 | 114 | { |
58c2dde1 | 115 | struct kvm_lapic_irq irq; |
79950e10 | 116 | |
1a6e4a8c GN |
117 | if (!level) |
118 | return -1; | |
119 | ||
01f21880 | 120 | kvm_set_msi_irq(e, &irq); |
116191b6 | 121 | |
b4f2225c | 122 | return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL); |
79950e10 SY |
123 | } |
124 | ||
01f21880 MT |
125 | |
126 | static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e, | |
127 | struct kvm *kvm) | |
128 | { | |
129 | struct kvm_lapic_irq irq; | |
130 | int r; | |
131 | ||
132 | kvm_set_msi_irq(e, &irq); | |
133 | ||
b4f2225c | 134 | if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL)) |
01f21880 MT |
135 | return r; |
136 | else | |
137 | return -EWOULDBLOCK; | |
138 | } | |
139 | ||
01f21880 MT |
140 | /* |
141 | * Deliver an IRQ in an atomic context if we can, or return a failure, | |
142 | * user can retry in a process context. | |
143 | * Return value: | |
144 | * -EWOULDBLOCK - Can't deliver in atomic context: retry in a process context. | |
145 | * Other values - No need to retry. | |
146 | */ | |
147 | int kvm_set_irq_inatomic(struct kvm *kvm, int irq_source_id, u32 irq, int level) | |
148 | { | |
8ba918d4 | 149 | struct kvm_kernel_irq_routing_entry entries[KVM_NR_IRQCHIPS]; |
01f21880 MT |
150 | struct kvm_kernel_irq_routing_entry *e; |
151 | int ret = -EINVAL; | |
719d93cd | 152 | int idx; |
01f21880 MT |
153 | |
154 | trace_kvm_set_irq(irq, level, irq_source_id); | |
155 | ||
156 | /* | |
157 | * Injection into either PIC or IOAPIC might need to scan all CPUs, | |
158 | * which would need to be retried from thread context; when same GSI | |
159 | * is connected to both PIC and IOAPIC, we'd have to report a | |
160 | * partial failure here. | |
161 | * Since there's no easy way to do this, we only support injecting MSI | |
162 | * which is limited to 1:1 GSI mapping. | |
163 | */ | |
719d93cd | 164 | idx = srcu_read_lock(&kvm->irq_srcu); |
9957c86d | 165 | if (kvm_irq_map_gsi(kvm, entries, irq) > 0) { |
8ba918d4 PM |
166 | e = &entries[0]; |
167 | if (likely(e->type == KVM_IRQ_ROUTING_MSI)) | |
168 | ret = kvm_set_msi_inatomic(e, kvm); | |
169 | else | |
170 | ret = -EWOULDBLOCK; | |
171 | } | |
719d93cd | 172 | srcu_read_unlock(&kvm->irq_srcu, idx); |
01f21880 MT |
173 | return ret; |
174 | } | |
175 | ||
5550af4d SY |
176 | int kvm_request_irq_source_id(struct kvm *kvm) |
177 | { | |
178 | unsigned long *bitmap = &kvm->arch.irq_sources_bitmap; | |
fa40a821 MT |
179 | int irq_source_id; |
180 | ||
181 | mutex_lock(&kvm->irq_lock); | |
cd5a2685 | 182 | irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG); |
61552367 | 183 | |
cd5a2685 | 184 | if (irq_source_id >= BITS_PER_LONG) { |
5550af4d | 185 | printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n"); |
0c6ddceb JS |
186 | irq_source_id = -EFAULT; |
187 | goto unlock; | |
61552367 MM |
188 | } |
189 | ||
190 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); | |
7a84428a | 191 | ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID); |
61552367 | 192 | set_bit(irq_source_id, bitmap); |
0c6ddceb | 193 | unlock: |
fa40a821 | 194 | mutex_unlock(&kvm->irq_lock); |
61552367 | 195 | |
5550af4d SY |
196 | return irq_source_id; |
197 | } | |
198 | ||
199 | void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id) | |
200 | { | |
61552367 | 201 | ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID); |
7a84428a | 202 | ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID); |
61552367 | 203 | |
fa40a821 | 204 | mutex_lock(&kvm->irq_lock); |
61552367 | 205 | if (irq_source_id < 0 || |
cd5a2685 | 206 | irq_source_id >= BITS_PER_LONG) { |
5550af4d | 207 | printk(KERN_ERR "kvm: IRQ source ID out of range!\n"); |
0c6ddceb | 208 | goto unlock; |
5550af4d | 209 | } |
e50212bb | 210 | clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap); |
49df6397 | 211 | if (!ioapic_in_kernel(kvm)) |
e50212bb MT |
212 | goto unlock; |
213 | ||
1a577b72 | 214 | kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id); |
1a577b72 | 215 | kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id); |
0c6ddceb | 216 | unlock: |
fa40a821 | 217 | mutex_unlock(&kvm->irq_lock); |
5550af4d | 218 | } |
75858a84 AK |
219 | |
220 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
221 | struct kvm_irq_mask_notifier *kimn) | |
222 | { | |
fa40a821 | 223 | mutex_lock(&kvm->irq_lock); |
75858a84 | 224 | kimn->irq = irq; |
6ef768fa | 225 | hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list); |
fa40a821 | 226 | mutex_unlock(&kvm->irq_lock); |
75858a84 AK |
227 | } |
228 | ||
229 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
230 | struct kvm_irq_mask_notifier *kimn) | |
231 | { | |
fa40a821 | 232 | mutex_lock(&kvm->irq_lock); |
280aa177 | 233 | hlist_del_rcu(&kimn->link); |
fa40a821 | 234 | mutex_unlock(&kvm->irq_lock); |
719d93cd | 235 | synchronize_srcu(&kvm->irq_srcu); |
75858a84 AK |
236 | } |
237 | ||
4a994358 GN |
238 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, |
239 | bool mask) | |
75858a84 AK |
240 | { |
241 | struct kvm_irq_mask_notifier *kimn; | |
719d93cd | 242 | int idx, gsi; |
75858a84 | 243 | |
719d93cd | 244 | idx = srcu_read_lock(&kvm->irq_srcu); |
9957c86d | 245 | gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin); |
4a994358 | 246 | if (gsi != -1) |
6ef768fa | 247 | hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link) |
4a994358 GN |
248 | if (kimn->irq == gsi) |
249 | kimn->func(kimn, mask); | |
719d93cd | 250 | srcu_read_unlock(&kvm->irq_srcu, idx); |
75858a84 AK |
251 | } |
252 | ||
8ba918d4 | 253 | int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e, |
e8cde093 | 254 | const struct kvm_irq_routing_entry *ue) |
399ec807 AK |
255 | { |
256 | int r = -EINVAL; | |
257 | int delta; | |
d72118ce | 258 | unsigned max_pin; |
46e624b9 | 259 | |
399ec807 AK |
260 | switch (ue->type) { |
261 | case KVM_IRQ_ROUTING_IRQCHIP: | |
262 | delta = 0; | |
263 | switch (ue->u.irqchip.irqchip) { | |
264 | case KVM_IRQCHIP_PIC_MASTER: | |
265 | e->set = kvm_set_pic_irq; | |
93b6547e | 266 | max_pin = PIC_NUM_PINS; |
399ec807 AK |
267 | break; |
268 | case KVM_IRQCHIP_PIC_SLAVE: | |
4925663a | 269 | e->set = kvm_set_pic_irq; |
93b6547e | 270 | max_pin = PIC_NUM_PINS; |
399ec807 AK |
271 | delta = 8; |
272 | break; | |
273 | case KVM_IRQCHIP_IOAPIC: | |
d72118ce | 274 | max_pin = KVM_IOAPIC_NUM_PINS; |
efbc100c | 275 | e->set = kvm_set_ioapic_irq; |
399ec807 AK |
276 | break; |
277 | default: | |
278 | goto out; | |
279 | } | |
280 | e->irqchip.irqchip = ue->u.irqchip.irqchip; | |
281 | e->irqchip.pin = ue->u.irqchip.pin + delta; | |
d72118ce | 282 | if (e->irqchip.pin >= max_pin) |
3e71f88b | 283 | goto out; |
399ec807 | 284 | break; |
79950e10 SY |
285 | case KVM_IRQ_ROUTING_MSI: |
286 | e->set = kvm_set_msi; | |
287 | e->msi.address_lo = ue->u.msi.address_lo; | |
288 | e->msi.address_hi = ue->u.msi.address_hi; | |
289 | e->msi.data = ue->u.msi.data; | |
290 | break; | |
399ec807 AK |
291 | default: |
292 | goto out; | |
293 | } | |
46e624b9 | 294 | |
399ec807 AK |
295 | r = 0; |
296 | out: | |
297 | return r; | |
298 | } | |
299 | ||
399ec807 AK |
300 | #define IOAPIC_ROUTING_ENTRY(irq) \ |
301 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ | |
25f97ff4 | 302 | .u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } } |
399ec807 AK |
303 | #define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq) |
304 | ||
3bf58e9a | 305 | #define PIC_ROUTING_ENTRY(irq) \ |
399ec807 | 306 | { .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \ |
25f97ff4 | 307 | .u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } } |
3bf58e9a | 308 | #define ROUTING_ENTRY2(irq) \ |
399ec807 | 309 | IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq) |
399ec807 AK |
310 | |
311 | static const struct kvm_irq_routing_entry default_routing[] = { | |
312 | ROUTING_ENTRY2(0), ROUTING_ENTRY2(1), | |
313 | ROUTING_ENTRY2(2), ROUTING_ENTRY2(3), | |
314 | ROUTING_ENTRY2(4), ROUTING_ENTRY2(5), | |
315 | ROUTING_ENTRY2(6), ROUTING_ENTRY2(7), | |
316 | ROUTING_ENTRY2(8), ROUTING_ENTRY2(9), | |
317 | ROUTING_ENTRY2(10), ROUTING_ENTRY2(11), | |
318 | ROUTING_ENTRY2(12), ROUTING_ENTRY2(13), | |
319 | ROUTING_ENTRY2(14), ROUTING_ENTRY2(15), | |
320 | ROUTING_ENTRY1(16), ROUTING_ENTRY1(17), | |
321 | ROUTING_ENTRY1(18), ROUTING_ENTRY1(19), | |
322 | ROUTING_ENTRY1(20), ROUTING_ENTRY1(21), | |
323 | ROUTING_ENTRY1(22), ROUTING_ENTRY1(23), | |
399ec807 AK |
324 | }; |
325 | ||
326 | int kvm_setup_default_irq_routing(struct kvm *kvm) | |
327 | { | |
328 | return kvm_set_irq_routing(kvm, default_routing, | |
329 | ARRAY_SIZE(default_routing), 0); | |
330 | } | |
49df6397 SR |
331 | |
332 | static const struct kvm_irq_routing_entry empty_routing[] = {}; | |
333 | ||
334 | int kvm_setup_empty_irq_routing(struct kvm *kvm) | |
335 | { | |
336 | return kvm_set_irq_routing(kvm, empty_routing, 0, 0); | |
337 | } | |
b053b2ae SR |
338 | |
339 | void kvm_arch_irq_routing_update(struct kvm *kvm) | |
340 | { | |
341 | if (ioapic_in_kernel(kvm) || !irqchip_in_kernel(kvm)) | |
342 | return; | |
343 | kvm_make_scan_ioapic_request(kvm); | |
344 | } | |
345 | ||
346 | void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) | |
347 | { | |
348 | struct kvm *kvm = vcpu->kvm; | |
349 | struct kvm_kernel_irq_routing_entry *entry; | |
350 | struct kvm_irq_routing_table *table; | |
351 | u32 i, nr_ioapic_pins; | |
352 | int idx; | |
353 | ||
354 | /* kvm->irq_routing must be read after clearing | |
355 | * KVM_SCAN_IOAPIC. */ | |
356 | smp_mb(); | |
357 | idx = srcu_read_lock(&kvm->irq_srcu); | |
358 | table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); | |
359 | nr_ioapic_pins = min_t(u32, table->nr_rt_entries, | |
360 | kvm->arch.nr_reserved_ioapic_pins); | |
361 | for (i = 0; i < nr_ioapic_pins; ++i) { | |
362 | hlist_for_each_entry(entry, &table->map[i], link) { | |
363 | u32 dest_id, dest_mode; | |
364 | ||
365 | if (entry->type != KVM_IRQ_ROUTING_MSI) | |
366 | continue; | |
367 | dest_id = (entry->msi.address_lo >> 12) & 0xff; | |
368 | dest_mode = (entry->msi.address_lo >> 2) & 0x1; | |
369 | if (kvm_apic_match_dest(vcpu, NULL, 0, dest_id, | |
370 | dest_mode)) { | |
371 | u32 vector = entry->msi.data & 0xff; | |
372 | ||
373 | __set_bit(vector, | |
374 | (unsigned long *) eoi_exit_bitmap); | |
375 | } | |
376 | } | |
377 | } | |
378 | srcu_read_unlock(&kvm->irq_srcu, idx); | |
379 | } |