Commit | Line | Data |
---|---|---|
97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
5c919412 | 44 | #include "hyperv.h" |
97222cc8 | 45 | |
b682b814 MT |
46 | #ifndef CONFIG_X86_64 |
47 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
48 | #else | |
49 | #define mod_64(x, y) ((x) % (y)) | |
50 | #endif | |
51 | ||
97222cc8 ED |
52 | #define PRId64 "d" |
53 | #define PRIx64 "llx" | |
54 | #define PRIu64 "u" | |
55 | #define PRIo64 "o" | |
56 | ||
57 | #define APIC_BUS_CYCLE_NS 1 | |
58 | ||
59 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
60 | #define apic_debug(fmt, arg...) | |
61 | ||
97222cc8 | 62 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 63 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
64 | #define LAPIC_MMIO_LENGTH (1 << 12) |
65 | /* followed define is not in apicdef.h */ | |
66 | #define APIC_SHORT_MASK 0xc0000 | |
67 | #define APIC_DEST_NOSHORT 0x0 | |
68 | #define APIC_DEST_MASK 0x800 | |
69 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 70 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 71 | |
394457a9 NA |
72 | #define APIC_BROADCAST 0xFF |
73 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
74 | ||
a0c9a822 MT |
75 | static inline int apic_test_vector(int vec, void *bitmap) |
76 | { | |
77 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
78 | } | |
79 | ||
10606919 YZ |
80 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
81 | { | |
82 | struct kvm_lapic *apic = vcpu->arch.apic; | |
83 | ||
84 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
85 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
86 | } | |
87 | ||
97222cc8 ED |
88 | static inline void apic_clear_vector(int vec, void *bitmap) |
89 | { | |
90 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
91 | } | |
92 | ||
8680b94b MT |
93 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
94 | { | |
95 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
96 | } | |
97 | ||
98 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
99 | { | |
100 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
101 | } | |
102 | ||
c5cc421b | 103 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
104 | struct static_key_deferred apic_sw_disabled __read_mostly; |
105 | ||
97222cc8 ED |
106 | static inline int apic_enabled(struct kvm_lapic *apic) |
107 | { | |
c48f1496 | 108 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
109 | } |
110 | ||
97222cc8 ED |
111 | #define LVT_MASK \ |
112 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
113 | ||
114 | #define LINT_MASK \ | |
115 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
116 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
117 | ||
3548a259 RK |
118 | /* The logical map is definitely wrong if we have multiple |
119 | * modes at the same time. (Physical map is always right.) | |
120 | */ | |
121 | static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map) | |
122 | { | |
123 | return !(map->mode & (map->mode - 1)); | |
124 | } | |
125 | ||
3b5a5ffa RK |
126 | static inline void |
127 | apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid) | |
128 | { | |
129 | unsigned lid_bits; | |
130 | ||
131 | BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4); | |
132 | BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8); | |
133 | BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16); | |
134 | lid_bits = map->mode; | |
135 | ||
136 | *cid = dest_id >> lid_bits; | |
137 | *lid = dest_id & ((1 << lid_bits) - 1); | |
138 | } | |
139 | ||
1e08ec4a GN |
140 | static void recalculate_apic_map(struct kvm *kvm) |
141 | { | |
142 | struct kvm_apic_map *new, *old = NULL; | |
143 | struct kvm_vcpu *vcpu; | |
144 | int i; | |
145 | ||
146 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
147 | ||
148 | mutex_lock(&kvm->arch.apic_map_lock); | |
149 | ||
150 | if (!new) | |
151 | goto out; | |
152 | ||
173beedc NA |
153 | kvm_for_each_vcpu(i, vcpu, kvm) { |
154 | struct kvm_lapic *apic = vcpu->arch.apic; | |
155 | u16 cid, lid; | |
25995e5b | 156 | u32 ldr, aid; |
1e08ec4a | 157 | |
df04d1d1 RK |
158 | if (!kvm_apic_present(vcpu)) |
159 | continue; | |
160 | ||
25995e5b | 161 | aid = kvm_apic_id(apic); |
dfb95954 | 162 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
1e08ec4a | 163 | |
25995e5b RK |
164 | if (aid < ARRAY_SIZE(new->phys_map)) |
165 | new->phys_map[aid] = apic; | |
3548a259 | 166 | |
3b5a5ffa RK |
167 | if (apic_x2apic_mode(apic)) { |
168 | new->mode |= KVM_APIC_MODE_X2APIC; | |
169 | } else if (ldr) { | |
170 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 171 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
172 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
173 | else | |
174 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
175 | } | |
176 | ||
177 | if (!kvm_apic_logical_map_valid(new)) | |
3548a259 RK |
178 | continue; |
179 | ||
3b5a5ffa RK |
180 | apic_logical_id(new, ldr, &cid, &lid); |
181 | ||
25995e5b | 182 | if (lid && cid < ARRAY_SIZE(new->logical_map)) |
1e08ec4a GN |
183 | new->logical_map[cid][ffs(lid) - 1] = apic; |
184 | } | |
185 | out: | |
186 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
187 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
188 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
189 | mutex_unlock(&kvm->arch.apic_map_lock); | |
190 | ||
191 | if (old) | |
192 | kfree_rcu(old, rcu); | |
c7c9c56c | 193 | |
b053b2ae | 194 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
195 | } |
196 | ||
1e1b6c26 NA |
197 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
198 | { | |
e462755c | 199 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 200 | |
1e6e2755 | 201 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
202 | |
203 | if (enabled != apic->sw_enabled) { | |
204 | apic->sw_enabled = enabled; | |
205 | if (enabled) { | |
1e1b6c26 NA |
206 | static_key_slow_dec_deferred(&apic_sw_disabled); |
207 | recalculate_apic_map(apic->vcpu->kvm); | |
208 | } else | |
209 | static_key_slow_inc(&apic_sw_disabled.key); | |
210 | } | |
211 | } | |
212 | ||
1e08ec4a GN |
213 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) |
214 | { | |
1e6e2755 | 215 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
1e08ec4a GN |
216 | recalculate_apic_map(apic->vcpu->kvm); |
217 | } | |
218 | ||
219 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
220 | { | |
1e6e2755 | 221 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
1e08ec4a GN |
222 | recalculate_apic_map(apic->vcpu->kvm); |
223 | } | |
224 | ||
257b9a5f RK |
225 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id) |
226 | { | |
227 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
228 | ||
1e6e2755 SS |
229 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
230 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); | |
257b9a5f RK |
231 | recalculate_apic_map(apic->vcpu->kvm); |
232 | } | |
233 | ||
97222cc8 ED |
234 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
235 | { | |
dfb95954 | 236 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
237 | } |
238 | ||
239 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
240 | { | |
dfb95954 | 241 | return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
242 | } |
243 | ||
a3e06bbe LJ |
244 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
245 | { | |
f30ebc31 | 246 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
247 | } |
248 | ||
97222cc8 ED |
249 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
250 | { | |
f30ebc31 | 251 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
252 | } |
253 | ||
254 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
255 | { | |
f30ebc31 | 256 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
257 | } |
258 | ||
cc6e462c JK |
259 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
260 | { | |
261 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
262 | } | |
263 | ||
fc61b800 GN |
264 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
265 | { | |
266 | struct kvm_lapic *apic = vcpu->arch.apic; | |
267 | struct kvm_cpuid_entry2 *feat; | |
268 | u32 v = APIC_VERSION; | |
269 | ||
bce87cce | 270 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
271 | return; |
272 | ||
273 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
274 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
275 | v |= APIC_LVR_DIRECTED_EOI; | |
1e6e2755 | 276 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
277 | } |
278 | ||
1e6e2755 | 279 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 280 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
281 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
282 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
283 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
284 | LVT_MASK /* LVTERR */ | |
285 | }; | |
286 | ||
287 | static int find_highest_vector(void *bitmap) | |
288 | { | |
ecba9a52 TY |
289 | int vec; |
290 | u32 *reg; | |
97222cc8 | 291 | |
ecba9a52 TY |
292 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
293 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
294 | reg = bitmap + REG_POS(vec); | |
295 | if (*reg) | |
296 | return fls(*reg) - 1 + vec; | |
297 | } | |
97222cc8 | 298 | |
ecba9a52 | 299 | return -1; |
97222cc8 ED |
300 | } |
301 | ||
8680b94b MT |
302 | static u8 count_vectors(void *bitmap) |
303 | { | |
ecba9a52 TY |
304 | int vec; |
305 | u32 *reg; | |
8680b94b | 306 | u8 count = 0; |
ecba9a52 TY |
307 | |
308 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
309 | reg = bitmap + REG_POS(vec); | |
310 | count += hweight32(*reg); | |
311 | } | |
312 | ||
8680b94b MT |
313 | return count; |
314 | } | |
315 | ||
705699a1 | 316 | void __kvm_apic_update_irr(u32 *pir, void *regs) |
a20ed54d YZ |
317 | { |
318 | u32 i, pir_val; | |
a20ed54d YZ |
319 | |
320 | for (i = 0; i <= 7; i++) { | |
321 | pir_val = xchg(&pir[i], 0); | |
322 | if (pir_val) | |
705699a1 | 323 | *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val; |
a20ed54d YZ |
324 | } |
325 | } | |
705699a1 WV |
326 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
327 | ||
328 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) | |
329 | { | |
330 | struct kvm_lapic *apic = vcpu->arch.apic; | |
331 | ||
332 | __kvm_apic_update_irr(pir, apic->regs); | |
c77f3fab RK |
333 | |
334 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
705699a1 | 335 | } |
a20ed54d YZ |
336 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
337 | ||
33e4c686 | 338 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 339 | { |
33e4c686 | 340 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
341 | } |
342 | ||
343 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
344 | { | |
345 | int result; | |
346 | ||
c7c9c56c YZ |
347 | /* |
348 | * Note that irr_pending is just a hint. It will be always | |
349 | * true with virtual interrupt delivery enabled. | |
350 | */ | |
33e4c686 GN |
351 | if (!apic->irr_pending) |
352 | return -1; | |
353 | ||
d62caabb AS |
354 | if (apic->vcpu->arch.apicv_active) |
355 | kvm_x86_ops->sync_pir_to_irr(apic->vcpu); | |
33e4c686 | 356 | result = apic_search_irr(apic); |
97222cc8 ED |
357 | ASSERT(result == -1 || result >= 16); |
358 | ||
359 | return result; | |
360 | } | |
361 | ||
33e4c686 GN |
362 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
363 | { | |
56cc2406 WL |
364 | struct kvm_vcpu *vcpu; |
365 | ||
366 | vcpu = apic->vcpu; | |
367 | ||
d62caabb | 368 | if (unlikely(vcpu->arch.apicv_active)) { |
56cc2406 | 369 | /* try to update RVI */ |
f210f757 | 370 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
56cc2406 | 371 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f210f757 NA |
372 | } else { |
373 | apic->irr_pending = false; | |
374 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
375 | if (apic_search_irr(apic) != -1) | |
376 | apic->irr_pending = true; | |
56cc2406 | 377 | } |
33e4c686 GN |
378 | } |
379 | ||
8680b94b MT |
380 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
381 | { | |
56cc2406 WL |
382 | struct kvm_vcpu *vcpu; |
383 | ||
384 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
385 | return; | |
386 | ||
387 | vcpu = apic->vcpu; | |
fc57ac2c | 388 | |
8680b94b | 389 | /* |
56cc2406 WL |
390 | * With APIC virtualization enabled, all caching is disabled |
391 | * because the processor can modify ISR under the hood. Instead | |
392 | * just set SVI. | |
8680b94b | 393 | */ |
d62caabb | 394 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 395 | kvm_x86_ops->hwapic_isr_update(vcpu, vec); |
56cc2406 WL |
396 | else { |
397 | ++apic->isr_count; | |
398 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
399 | /* | |
400 | * ISR (in service register) bit is set when injecting an interrupt. | |
401 | * The highest vector is injected. Thus the latest bit set matches | |
402 | * the highest bit in ISR. | |
403 | */ | |
404 | apic->highest_isr_cache = vec; | |
405 | } | |
8680b94b MT |
406 | } |
407 | ||
fc57ac2c PB |
408 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
409 | { | |
410 | int result; | |
411 | ||
412 | /* | |
413 | * Note that isr_count is always 1, and highest_isr_cache | |
414 | * is always -1, with APIC virtualization enabled. | |
415 | */ | |
416 | if (!apic->isr_count) | |
417 | return -1; | |
418 | if (likely(apic->highest_isr_cache != -1)) | |
419 | return apic->highest_isr_cache; | |
420 | ||
421 | result = find_highest_vector(apic->regs + APIC_ISR); | |
422 | ASSERT(result == -1 || result >= 16); | |
423 | ||
424 | return result; | |
425 | } | |
426 | ||
8680b94b MT |
427 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
428 | { | |
fc57ac2c PB |
429 | struct kvm_vcpu *vcpu; |
430 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
431 | return; | |
432 | ||
433 | vcpu = apic->vcpu; | |
434 | ||
435 | /* | |
436 | * We do get here for APIC virtualization enabled if the guest | |
437 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
438 | * to trigger a new interrupt delivery by writing the SVI field; | |
439 | * on the other hand isr_count and highest_isr_cache are unused | |
440 | * and must be left alone. | |
441 | */ | |
d62caabb | 442 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 443 | kvm_x86_ops->hwapic_isr_update(vcpu, |
fc57ac2c PB |
444 | apic_find_highest_isr(apic)); |
445 | else { | |
8680b94b | 446 | --apic->isr_count; |
fc57ac2c PB |
447 | BUG_ON(apic->isr_count < 0); |
448 | apic->highest_isr_cache = -1; | |
449 | } | |
8680b94b MT |
450 | } |
451 | ||
6e5d865c YS |
452 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
453 | { | |
33e4c686 GN |
454 | /* This may race with setting of irr in __apic_accept_irq() and |
455 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
456 | * will cause vmexit immediately and the value will be recalculated | |
457 | * on the next vmentry. | |
458 | */ | |
f8543d6a | 459 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 460 | } |
6e5d865c | 461 | |
6da7e3f6 | 462 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 463 | int vector, int level, int trig_mode, |
9e4aabe2 | 464 | struct dest_map *dest_map); |
6da7e3f6 | 465 | |
b4f2225c | 466 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 467 | struct dest_map *dest_map) |
97222cc8 | 468 | { |
ad312c7c | 469 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 470 | |
58c2dde1 | 471 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 472 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
473 | } |
474 | ||
ae7a2a3f MT |
475 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
476 | { | |
477 | ||
478 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
479 | sizeof(val)); | |
480 | } | |
481 | ||
482 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
483 | { | |
484 | ||
485 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
486 | sizeof(*val)); | |
487 | } | |
488 | ||
489 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
490 | { | |
491 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
492 | } | |
493 | ||
494 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
495 | { | |
496 | u8 val; | |
497 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
498 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 499 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
500 | return val & 0x1; |
501 | } | |
502 | ||
503 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
504 | { | |
505 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
506 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 507 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
508 | return; |
509 | } | |
510 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
511 | } | |
512 | ||
513 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
514 | { | |
515 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
516 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 517 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
518 | return; |
519 | } | |
520 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
521 | } | |
522 | ||
97222cc8 ED |
523 | static void apic_update_ppr(struct kvm_lapic *apic) |
524 | { | |
3842d135 | 525 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
526 | int isr; |
527 | ||
dfb95954 SS |
528 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
529 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
530 | isr = apic_find_highest_isr(apic); |
531 | isrv = (isr != -1) ? isr : 0; | |
532 | ||
533 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
534 | ppr = tpr & 0xff; | |
535 | else | |
536 | ppr = isrv & 0xf0; | |
537 | ||
538 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
539 | apic, ppr, isr, isrv); | |
540 | ||
3842d135 | 541 | if (old_ppr != ppr) { |
1e6e2755 | 542 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
83bcacb1 AK |
543 | if (ppr < old_ppr) |
544 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 545 | } |
97222cc8 ED |
546 | } |
547 | ||
548 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
549 | { | |
1e6e2755 | 550 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
551 | apic_update_ppr(apic); |
552 | } | |
553 | ||
03d2249e | 554 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 555 | { |
03d2249e RK |
556 | if (apic_x2apic_mode(apic)) |
557 | return mda == X2APIC_BROADCAST; | |
558 | ||
559 | return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST; | |
394457a9 NA |
560 | } |
561 | ||
03d2249e | 562 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 563 | { |
03d2249e RK |
564 | if (kvm_apic_broadcast(apic, mda)) |
565 | return true; | |
566 | ||
567 | if (apic_x2apic_mode(apic)) | |
568 | return mda == kvm_apic_id(apic); | |
569 | ||
570 | return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic)); | |
97222cc8 ED |
571 | } |
572 | ||
52c233a4 | 573 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 574 | { |
0105d1a5 GN |
575 | u32 logical_id; |
576 | ||
394457a9 | 577 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 578 | return true; |
394457a9 | 579 | |
dfb95954 | 580 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 581 | |
9368b567 | 582 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
583 | return ((logical_id >> 16) == (mda >> 16)) |
584 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 585 | |
9368b567 | 586 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
03d2249e | 587 | mda = GET_APIC_DEST_FIELD(mda); |
97222cc8 | 588 | |
dfb95954 | 589 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 590 | case APIC_DFR_FLAT: |
9368b567 | 591 | return (logical_id & mda) != 0; |
97222cc8 | 592 | case APIC_DFR_CLUSTER: |
9368b567 RK |
593 | return ((logical_id >> 4) == (mda >> 4)) |
594 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 595 | default: |
7712de87 | 596 | apic_debug("Bad DFR vcpu %d: %08x\n", |
dfb95954 | 597 | apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); |
9368b567 | 598 | return false; |
97222cc8 | 599 | } |
97222cc8 ED |
600 | } |
601 | ||
03d2249e RK |
602 | /* KVM APIC implementation has two quirks |
603 | * - dest always begins at 0 while xAPIC MDA has offset 24, | |
604 | * - IOxAPIC messages have to be delivered (directly) to x2APIC. | |
605 | */ | |
606 | static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source, | |
607 | struct kvm_lapic *target) | |
608 | { | |
609 | bool ipi = source != NULL; | |
610 | bool x2apic_mda = apic_x2apic_mode(ipi ? source : target); | |
611 | ||
612 | if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda) | |
613 | return X2APIC_BROADCAST; | |
614 | ||
615 | return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id); | |
616 | } | |
617 | ||
52c233a4 | 618 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 619 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 620 | { |
ad312c7c | 621 | struct kvm_lapic *target = vcpu->arch.apic; |
03d2249e | 622 | u32 mda = kvm_apic_mda(dest, source, target); |
97222cc8 ED |
623 | |
624 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 625 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
626 | target, source, dest, dest_mode, short_hand); |
627 | ||
bd371396 | 628 | ASSERT(target); |
97222cc8 ED |
629 | switch (short_hand) { |
630 | case APIC_DEST_NOSHORT: | |
3697f302 | 631 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 632 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 633 | else |
03d2249e | 634 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 635 | case APIC_DEST_SELF: |
9368b567 | 636 | return target == source; |
97222cc8 | 637 | case APIC_DEST_ALLINC: |
9368b567 | 638 | return true; |
97222cc8 | 639 | case APIC_DEST_ALLBUT: |
9368b567 | 640 | return target != source; |
97222cc8 | 641 | default: |
7712de87 JK |
642 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
643 | short_hand); | |
9368b567 | 644 | return false; |
97222cc8 | 645 | } |
97222cc8 | 646 | } |
1e6e2755 | 647 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 648 | |
52004014 FW |
649 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
650 | const unsigned long *bitmap, u32 bitmap_size) | |
651 | { | |
652 | u32 mod; | |
653 | int i, idx = -1; | |
654 | ||
655 | mod = vector % dest_vcpus; | |
656 | ||
657 | for (i = 0; i <= mod; i++) { | |
658 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
659 | BUG_ON(idx == bitmap_size); | |
660 | } | |
661 | ||
662 | return idx; | |
663 | } | |
664 | ||
4efd805f RK |
665 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
666 | { | |
667 | if (!kvm->arch.disabled_lapic_found) { | |
668 | kvm->arch.disabled_lapic_found = true; | |
669 | printk(KERN_INFO | |
670 | "Disabled LAPIC found during irq injection\n"); | |
671 | } | |
672 | } | |
673 | ||
1e08ec4a | 674 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
9e4aabe2 | 675 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) |
1e08ec4a GN |
676 | { |
677 | struct kvm_apic_map *map; | |
678 | unsigned long bitmap = 1; | |
679 | struct kvm_lapic **dst; | |
680 | int i; | |
bea15428 | 681 | bool ret, x2apic_ipi; |
1e08ec4a GN |
682 | |
683 | *r = -1; | |
684 | ||
685 | if (irq->shorthand == APIC_DEST_SELF) { | |
b4f2225c | 686 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); |
1e08ec4a GN |
687 | return true; |
688 | } | |
689 | ||
690 | if (irq->shorthand) | |
691 | return false; | |
692 | ||
bea15428 | 693 | x2apic_ipi = src && apic_x2apic_mode(src); |
9ea369b0 RK |
694 | if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST)) |
695 | return false; | |
696 | ||
bea15428 | 697 | ret = true; |
1e08ec4a GN |
698 | rcu_read_lock(); |
699 | map = rcu_dereference(kvm->arch.apic_map); | |
700 | ||
bea15428 PB |
701 | if (!map) { |
702 | ret = false; | |
1e08ec4a | 703 | goto out; |
bea15428 | 704 | } |
698f9755 | 705 | |
3697f302 | 706 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { |
fa834e91 RK |
707 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) |
708 | goto out; | |
709 | ||
710 | dst = &map->phys_map[irq->dest_id]; | |
1e08ec4a | 711 | } else { |
3548a259 RK |
712 | u16 cid; |
713 | ||
714 | if (!kvm_apic_logical_map_valid(map)) { | |
715 | ret = false; | |
716 | goto out; | |
717 | } | |
718 | ||
3b5a5ffa | 719 | apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap); |
45c3094a RK |
720 | |
721 | if (cid >= ARRAY_SIZE(map->logical_map)) | |
722 | goto out; | |
1e08ec4a | 723 | |
45c3094a | 724 | dst = map->logical_map[cid]; |
1e08ec4a | 725 | |
52004014 FW |
726 | if (!kvm_lowest_prio_delivery(irq)) |
727 | goto set_irq; | |
728 | ||
729 | if (!kvm_vector_hashing_enabled()) { | |
1e08ec4a GN |
730 | int l = -1; |
731 | for_each_set_bit(i, &bitmap, 16) { | |
732 | if (!dst[i]) | |
733 | continue; | |
734 | if (l < 0) | |
735 | l = i; | |
52004014 FW |
736 | else if (kvm_apic_compare_prio(dst[i]->vcpu, |
737 | dst[l]->vcpu) < 0) | |
1e08ec4a GN |
738 | l = i; |
739 | } | |
1e08ec4a | 740 | bitmap = (l >= 0) ? 1 << l : 0; |
52004014 FW |
741 | } else { |
742 | int idx; | |
743 | unsigned int dest_vcpus; | |
744 | ||
745 | dest_vcpus = hweight16(bitmap); | |
746 | if (dest_vcpus == 0) | |
747 | goto out; | |
748 | ||
749 | idx = kvm_vector_to_index(irq->vector, | |
750 | dest_vcpus, &bitmap, 16); | |
751 | ||
4efd805f RK |
752 | if (!dst[idx]) { |
753 | kvm_apic_disabled_lapic_found(kvm); | |
52004014 FW |
754 | goto out; |
755 | } | |
756 | ||
757 | bitmap = (idx >= 0) ? 1 << idx : 0; | |
1e08ec4a GN |
758 | } |
759 | } | |
760 | ||
52004014 | 761 | set_irq: |
1e08ec4a GN |
762 | for_each_set_bit(i, &bitmap, 16) { |
763 | if (!dst[i]) | |
764 | continue; | |
765 | if (*r < 0) | |
766 | *r = 0; | |
b4f2225c | 767 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); |
1e08ec4a | 768 | } |
1e08ec4a GN |
769 | out: |
770 | rcu_read_unlock(); | |
771 | return ret; | |
772 | } | |
773 | ||
6228a0da FW |
774 | /* |
775 | * This routine tries to handler interrupts in posted mode, here is how | |
776 | * it deals with different cases: | |
777 | * - For single-destination interrupts, handle it in posted mode | |
778 | * - Else if vector hashing is enabled and it is a lowest-priority | |
779 | * interrupt, handle it in posted mode and use the following mechanism | |
780 | * to find the destinaiton vCPU. | |
781 | * 1. For lowest-priority interrupts, store all the possible | |
782 | * destination vCPUs in an array. | |
783 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
784 | * the right destination vCPU in the array for the lowest-priority | |
785 | * interrupt. | |
786 | * - Otherwise, use remapped mode to inject the interrupt. | |
787 | */ | |
8feb4a04 FW |
788 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
789 | struct kvm_vcpu **dest_vcpu) | |
790 | { | |
791 | struct kvm_apic_map *map; | |
792 | bool ret = false; | |
793 | struct kvm_lapic *dst = NULL; | |
794 | ||
795 | if (irq->shorthand) | |
796 | return false; | |
797 | ||
798 | rcu_read_lock(); | |
799 | map = rcu_dereference(kvm->arch.apic_map); | |
800 | ||
801 | if (!map) | |
802 | goto out; | |
803 | ||
804 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { | |
805 | if (irq->dest_id == 0xFF) | |
806 | goto out; | |
807 | ||
808 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) | |
809 | goto out; | |
810 | ||
811 | dst = map->phys_map[irq->dest_id]; | |
812 | if (dst && kvm_apic_present(dst->vcpu)) | |
813 | *dest_vcpu = dst->vcpu; | |
814 | else | |
815 | goto out; | |
816 | } else { | |
817 | u16 cid; | |
818 | unsigned long bitmap = 1; | |
819 | int i, r = 0; | |
820 | ||
821 | if (!kvm_apic_logical_map_valid(map)) | |
822 | goto out; | |
823 | ||
824 | apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap); | |
825 | ||
826 | if (cid >= ARRAY_SIZE(map->logical_map)) | |
827 | goto out; | |
828 | ||
6228a0da FW |
829 | if (kvm_vector_hashing_enabled() && |
830 | kvm_lowest_prio_delivery(irq)) { | |
831 | int idx; | |
832 | unsigned int dest_vcpus; | |
833 | ||
834 | dest_vcpus = hweight16(bitmap); | |
835 | if (dest_vcpus == 0) | |
8feb4a04 | 836 | goto out; |
8feb4a04 | 837 | |
6228a0da FW |
838 | idx = kvm_vector_to_index(irq->vector, dest_vcpus, |
839 | &bitmap, 16); | |
840 | ||
6228a0da | 841 | dst = map->logical_map[cid][idx]; |
4efd805f RK |
842 | if (!dst) { |
843 | kvm_apic_disabled_lapic_found(kvm); | |
6228a0da FW |
844 | goto out; |
845 | } | |
846 | ||
8feb4a04 | 847 | *dest_vcpu = dst->vcpu; |
6228a0da FW |
848 | } else { |
849 | for_each_set_bit(i, &bitmap, 16) { | |
850 | dst = map->logical_map[cid][i]; | |
851 | if (++r == 2) | |
852 | goto out; | |
853 | } | |
854 | ||
855 | if (dst && kvm_apic_present(dst->vcpu)) | |
856 | *dest_vcpu = dst->vcpu; | |
857 | else | |
858 | goto out; | |
859 | } | |
8feb4a04 FW |
860 | } |
861 | ||
862 | ret = true; | |
863 | out: | |
864 | rcu_read_unlock(); | |
865 | return ret; | |
866 | } | |
867 | ||
97222cc8 ED |
868 | /* |
869 | * Add a pending IRQ into lapic. | |
870 | * Return 1 if successfully added and 0 if discarded. | |
871 | */ | |
872 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 873 | int vector, int level, int trig_mode, |
9e4aabe2 | 874 | struct dest_map *dest_map) |
97222cc8 | 875 | { |
6da7e3f6 | 876 | int result = 0; |
c5ec1534 | 877 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 878 | |
a183b638 PB |
879 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
880 | trig_mode, vector); | |
97222cc8 | 881 | switch (delivery_mode) { |
97222cc8 | 882 | case APIC_DM_LOWEST: |
e1035715 GN |
883 | vcpu->arch.apic_arb_prio++; |
884 | case APIC_DM_FIXED: | |
bdaffe1d PB |
885 | if (unlikely(trig_mode && !level)) |
886 | break; | |
887 | ||
97222cc8 ED |
888 | /* FIXME add logic for vcpu on reset */ |
889 | if (unlikely(!apic_enabled(apic))) | |
890 | break; | |
891 | ||
11f5cc05 JK |
892 | result = 1; |
893 | ||
9daa5007 | 894 | if (dest_map) { |
9e4aabe2 | 895 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
896 | dest_map->vectors[vcpu->vcpu_id] = vector; |
897 | } | |
a5d36f82 | 898 | |
bdaffe1d PB |
899 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
900 | if (trig_mode) | |
1e6e2755 | 901 | kvm_lapic_set_vector(vector, apic->regs + APIC_TMR); |
bdaffe1d PB |
902 | else |
903 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
904 | } | |
905 | ||
d62caabb | 906 | if (vcpu->arch.apicv_active) |
5a71785d | 907 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 | 908 | else { |
1e6e2755 | 909 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
910 | |
911 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
912 | kvm_vcpu_kick(vcpu); | |
913 | } | |
97222cc8 ED |
914 | break; |
915 | ||
916 | case APIC_DM_REMRD: | |
24d2166b R |
917 | result = 1; |
918 | vcpu->arch.pv.pv_unhalted = 1; | |
919 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
920 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
921 | break; |
922 | ||
923 | case APIC_DM_SMI: | |
64d60670 PB |
924 | result = 1; |
925 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
926 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 927 | break; |
3419ffc8 | 928 | |
97222cc8 | 929 | case APIC_DM_NMI: |
6da7e3f6 | 930 | result = 1; |
3419ffc8 | 931 | kvm_inject_nmi(vcpu); |
26df99c6 | 932 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
933 | break; |
934 | ||
935 | case APIC_DM_INIT: | |
a52315e1 | 936 | if (!trig_mode || level) { |
6da7e3f6 | 937 | result = 1; |
66450a21 JK |
938 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
939 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
940 | /* make sure pending_events is visible before sending | |
941 | * the request */ | |
942 | smp_wmb(); | |
3842d135 | 943 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
944 | kvm_vcpu_kick(vcpu); |
945 | } else { | |
1b10bf31 JK |
946 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
947 | vcpu->vcpu_id); | |
c5ec1534 | 948 | } |
97222cc8 ED |
949 | break; |
950 | ||
951 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
952 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
953 | vcpu->vcpu_id, vector); | |
66450a21 JK |
954 | result = 1; |
955 | apic->sipi_vector = vector; | |
956 | /* make sure sipi_vector is visible for the receiver */ | |
957 | smp_wmb(); | |
958 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
959 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
960 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
961 | break; |
962 | ||
23930f95 JK |
963 | case APIC_DM_EXTINT: |
964 | /* | |
965 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
966 | * before NMI watchdog was enabled. Already handled by | |
967 | * kvm_apic_accept_pic_intr(). | |
968 | */ | |
969 | break; | |
970 | ||
97222cc8 ED |
971 | default: |
972 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
973 | delivery_mode); | |
974 | break; | |
975 | } | |
976 | return result; | |
977 | } | |
978 | ||
e1035715 | 979 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 980 | { |
e1035715 | 981 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
982 | } |
983 | ||
3bb345f3 PB |
984 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
985 | { | |
6308630b | 986 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
987 | } |
988 | ||
c7c9c56c YZ |
989 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
990 | { | |
7543a635 SR |
991 | int trigger_mode; |
992 | ||
993 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
994 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
995 | return; | |
3bb345f3 | 996 | |
7543a635 SR |
997 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
998 | if (irqchip_split(apic->vcpu->kvm)) { | |
999 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
1000 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
1001 | return; | |
c7c9c56c | 1002 | } |
7543a635 SR |
1003 | |
1004 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
1005 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
1006 | else | |
1007 | trigger_mode = IOAPIC_EDGE_TRIG; | |
1008 | ||
1009 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
1010 | } |
1011 | ||
ae7a2a3f | 1012 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
1013 | { |
1014 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
1015 | |
1016 | trace_kvm_eoi(apic, vector); | |
1017 | ||
97222cc8 ED |
1018 | /* |
1019 | * Not every write EOI will has corresponding ISR, | |
1020 | * one example is when Kernel check timer on setup_IO_APIC | |
1021 | */ | |
1022 | if (vector == -1) | |
ae7a2a3f | 1023 | return vector; |
97222cc8 | 1024 | |
8680b94b | 1025 | apic_clear_isr(vector, apic); |
97222cc8 ED |
1026 | apic_update_ppr(apic); |
1027 | ||
5c919412 AS |
1028 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
1029 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
1030 | ||
c7c9c56c | 1031 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 1032 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1033 | return vector; |
97222cc8 ED |
1034 | } |
1035 | ||
c7c9c56c YZ |
1036 | /* |
1037 | * this interface assumes a trap-like exit, which has already finished | |
1038 | * desired side effect including vISR and vPPR update. | |
1039 | */ | |
1040 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1041 | { | |
1042 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1043 | ||
1044 | trace_kvm_eoi(apic, vector); | |
1045 | ||
1046 | kvm_ioapic_send_eoi(apic, vector); | |
1047 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1048 | } | |
1049 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1050 | ||
97222cc8 ED |
1051 | static void apic_send_ipi(struct kvm_lapic *apic) |
1052 | { | |
dfb95954 SS |
1053 | u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR); |
1054 | u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 1055 | struct kvm_lapic_irq irq; |
97222cc8 | 1056 | |
58c2dde1 GN |
1057 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1058 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1059 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1060 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1061 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1062 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1063 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1064 | if (apic_x2apic_mode(apic)) |
1065 | irq.dest_id = icr_high; | |
1066 | else | |
1067 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1068 | |
1000ff8d GN |
1069 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1070 | ||
97222cc8 ED |
1071 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
1072 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
1073 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
1074 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 1075 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 1076 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 1077 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 1078 | |
b4f2225c | 1079 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1080 | } |
1081 | ||
1082 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1083 | { | |
b682b814 MT |
1084 | ktime_t remaining; |
1085 | s64 ns; | |
9da8f4e8 | 1086 | u32 tmcct; |
97222cc8 ED |
1087 | |
1088 | ASSERT(apic != NULL); | |
1089 | ||
9da8f4e8 | 1090 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1091 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1092 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1093 | return 0; |
1094 | ||
ace15464 | 1095 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
1096 | if (ktime_to_ns(remaining) < 0) |
1097 | remaining = ktime_set(0, 0); | |
1098 | ||
d3c7b77d MT |
1099 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1100 | tmcct = div64_u64(ns, | |
1101 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1102 | |
1103 | return tmcct; | |
1104 | } | |
1105 | ||
b209749f AK |
1106 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1107 | { | |
1108 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1109 | struct kvm_run *run = vcpu->run; | |
1110 | ||
a8eeb04a | 1111 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1112 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1113 | run->tpr_access.is_write = write; |
1114 | } | |
1115 | ||
1116 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1117 | { | |
1118 | if (apic->vcpu->arch.tpr_access_reporting) | |
1119 | __report_tpr_access(apic, write); | |
1120 | } | |
1121 | ||
97222cc8 ED |
1122 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1123 | { | |
1124 | u32 val = 0; | |
1125 | ||
1126 | if (offset >= LAPIC_MMIO_LENGTH) | |
1127 | return 0; | |
1128 | ||
1129 | switch (offset) { | |
0105d1a5 GN |
1130 | case APIC_ID: |
1131 | if (apic_x2apic_mode(apic)) | |
1132 | val = kvm_apic_id(apic); | |
1133 | else | |
1134 | val = kvm_apic_id(apic) << 24; | |
1135 | break; | |
97222cc8 | 1136 | case APIC_ARBPRI: |
7712de87 | 1137 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1138 | break; |
1139 | ||
1140 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1141 | if (apic_lvtt_tscdeadline(apic)) |
1142 | return 0; | |
1143 | ||
97222cc8 ED |
1144 | val = apic_get_tmcct(apic); |
1145 | break; | |
4a4541a4 AK |
1146 | case APIC_PROCPRI: |
1147 | apic_update_ppr(apic); | |
dfb95954 | 1148 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1149 | break; |
b209749f AK |
1150 | case APIC_TASKPRI: |
1151 | report_tpr_access(apic, false); | |
1152 | /* fall thru */ | |
97222cc8 | 1153 | default: |
dfb95954 | 1154 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1155 | break; |
1156 | } | |
1157 | ||
1158 | return val; | |
1159 | } | |
1160 | ||
d76685c4 GH |
1161 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1162 | { | |
1163 | return container_of(dev, struct kvm_lapic, dev); | |
1164 | } | |
1165 | ||
1e6e2755 | 1166 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1167 | void *data) |
97222cc8 | 1168 | { |
97222cc8 ED |
1169 | unsigned char alignment = offset & 0xf; |
1170 | u32 result; | |
d5b0b5b1 | 1171 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1172 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1173 | |
1174 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1175 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1176 | offset, len); | |
0105d1a5 | 1177 | return 1; |
97222cc8 | 1178 | } |
0105d1a5 GN |
1179 | |
1180 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1181 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1182 | offset); | |
0105d1a5 GN |
1183 | return 1; |
1184 | } | |
1185 | ||
97222cc8 ED |
1186 | result = __apic_read(apic, offset & ~0xf); |
1187 | ||
229456fc MT |
1188 | trace_kvm_apic_read(offset, result); |
1189 | ||
97222cc8 ED |
1190 | switch (len) { |
1191 | case 1: | |
1192 | case 2: | |
1193 | case 4: | |
1194 | memcpy(data, (char *)&result + alignment, len); | |
1195 | break; | |
1196 | default: | |
1197 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1198 | "should be 1,2, or 4 instead\n", len); | |
1199 | break; | |
1200 | } | |
bda9020e | 1201 | return 0; |
97222cc8 | 1202 | } |
1e6e2755 | 1203 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1204 | |
0105d1a5 GN |
1205 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1206 | { | |
c48f1496 | 1207 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1208 | addr >= apic->base_address && |
1209 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1210 | } | |
1211 | ||
e32edf4f | 1212 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1213 | gpa_t address, int len, void *data) |
1214 | { | |
1215 | struct kvm_lapic *apic = to_lapic(this); | |
1216 | u32 offset = address - apic->base_address; | |
1217 | ||
1218 | if (!apic_mmio_in_range(apic, address)) | |
1219 | return -EOPNOTSUPP; | |
1220 | ||
1e6e2755 | 1221 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1222 | |
1223 | return 0; | |
1224 | } | |
1225 | ||
97222cc8 ED |
1226 | static void update_divide_count(struct kvm_lapic *apic) |
1227 | { | |
1228 | u32 tmp1, tmp2, tdcr; | |
1229 | ||
dfb95954 | 1230 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1231 | tmp1 = tdcr & 0xf; |
1232 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1233 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1234 | |
1235 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1236 | apic->divide_count); |
97222cc8 ED |
1237 | } |
1238 | ||
b6ac0695 RK |
1239 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1240 | { | |
dfb95954 | 1241 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1242 | apic->lapic_timer.timer_mode_mask; |
1243 | ||
1244 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
1245 | apic->lapic_timer.timer_mode = timer_mode; | |
1246 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1247 | } | |
1248 | } | |
1249 | ||
5d87db71 RK |
1250 | static void apic_timer_expired(struct kvm_lapic *apic) |
1251 | { | |
1252 | struct kvm_vcpu *vcpu = apic->vcpu; | |
8577370f | 1253 | struct swait_queue_head *q = &vcpu->wq; |
d0659d94 | 1254 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1255 | |
5d87db71 RK |
1256 | if (atomic_read(&apic->lapic_timer.pending)) |
1257 | return; | |
1258 | ||
1259 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1260 | kvm_set_pending_timer(vcpu); |
5d87db71 | 1261 | |
8577370f MT |
1262 | if (swait_active(q)) |
1263 | swake_up(q); | |
d0659d94 MT |
1264 | |
1265 | if (apic_lvtt_tscdeadline(apic)) | |
1266 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1267 | } | |
1268 | ||
1269 | /* | |
1270 | * On APICv, this test will cause a busy wait | |
1271 | * during a higher-priority task. | |
1272 | */ | |
1273 | ||
1274 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1275 | { | |
1276 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1277 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1278 | |
1279 | if (kvm_apic_hw_enabled(apic)) { | |
1280 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1281 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1282 | |
d62caabb | 1283 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1284 | bitmap = apic->regs + APIC_IRR; |
1285 | ||
1286 | if (apic_test_vector(vec, bitmap)) | |
1287 | return true; | |
d0659d94 MT |
1288 | } |
1289 | return false; | |
1290 | } | |
1291 | ||
1292 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1293 | { | |
1294 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1295 | u64 guest_tsc, tsc_deadline; | |
1296 | ||
bce87cce | 1297 | if (!lapic_in_kernel(vcpu)) |
d0659d94 MT |
1298 | return; |
1299 | ||
1300 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1301 | return; | |
1302 | ||
1303 | if (!lapic_timer_int_injected(vcpu)) | |
1304 | return; | |
1305 | ||
1306 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1307 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1308 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1309 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1310 | |
1311 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1312 | if (guest_tsc < tsc_deadline) | |
b606f189 MT |
1313 | __delay(min(tsc_deadline - guest_tsc, |
1314 | nsec_to_cycles(vcpu, lapic_timer_advance_ns))); | |
5d87db71 RK |
1315 | } |
1316 | ||
97222cc8 ED |
1317 | static void start_apic_timer(struct kvm_lapic *apic) |
1318 | { | |
a3e06bbe | 1319 | ktime_t now; |
d0659d94 | 1320 | |
d3c7b77d | 1321 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1322 | |
a3e06bbe | 1323 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 1324 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 1325 | now = apic->lapic_timer.timer.base->get_time(); |
dfb95954 | 1326 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
1327 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
1328 | ||
1329 | if (!apic->lapic_timer.period) | |
1330 | return; | |
1331 | /* | |
1332 | * Do not allow the guest to program periodic timers with small | |
1333 | * interval, since the hrtimers are not throttled by the host | |
1334 | * scheduler. | |
1335 | */ | |
1336 | if (apic_lvtt_period(apic)) { | |
1337 | s64 min_period = min_timer_period_us * 1000LL; | |
1338 | ||
1339 | if (apic->lapic_timer.period < min_period) { | |
1340 | pr_info_ratelimited( | |
1341 | "kvm: vcpu %i: requested %lld ns " | |
1342 | "lapic timer period limited to %lld ns\n", | |
1343 | apic->vcpu->vcpu_id, | |
1344 | apic->lapic_timer.period, min_period); | |
1345 | apic->lapic_timer.period = min_period; | |
1346 | } | |
9bc5791d | 1347 | } |
0b975a3c | 1348 | |
a3e06bbe LJ |
1349 | hrtimer_start(&apic->lapic_timer.timer, |
1350 | ktime_add_ns(now, apic->lapic_timer.period), | |
61abdbe0 | 1351 | HRTIMER_MODE_ABS_PINNED); |
97222cc8 | 1352 | |
a3e06bbe | 1353 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1354 | PRIx64 ", " |
1355 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1356 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1357 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
dfb95954 | 1358 | kvm_lapic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1359 | apic->lapic_timer.period, |
97222cc8 | 1360 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1361 | apic->lapic_timer.period))); |
a3e06bbe LJ |
1362 | } else if (apic_lvtt_tscdeadline(apic)) { |
1363 | /* lapic timer in tsc deadline mode */ | |
1364 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1365 | u64 ns = 0; | |
d0659d94 | 1366 | ktime_t expire; |
a3e06bbe | 1367 | struct kvm_vcpu *vcpu = apic->vcpu; |
cc578287 | 1368 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; |
a3e06bbe LJ |
1369 | unsigned long flags; |
1370 | ||
1371 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1372 | return; | |
1373 | ||
1374 | local_irq_save(flags); | |
1375 | ||
1376 | now = apic->lapic_timer.timer.base->get_time(); | |
4ba76538 | 1377 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
a3e06bbe LJ |
1378 | if (likely(tscdeadline > guest_tsc)) { |
1379 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1380 | do_div(ns, this_tsc_khz); | |
d0659d94 MT |
1381 | expire = ktime_add_ns(now, ns); |
1382 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1e0ad70c | 1383 | hrtimer_start(&apic->lapic_timer.timer, |
61abdbe0 | 1384 | expire, HRTIMER_MODE_ABS_PINNED); |
1e0ad70c RK |
1385 | } else |
1386 | apic_timer_expired(apic); | |
a3e06bbe LJ |
1387 | |
1388 | local_irq_restore(flags); | |
1389 | } | |
97222cc8 ED |
1390 | } |
1391 | ||
cc6e462c JK |
1392 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1393 | { | |
59fd1323 | 1394 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1395 | |
59fd1323 RK |
1396 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1397 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1398 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1399 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1400 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1401 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1402 | } else |
1403 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1404 | } | |
cc6e462c JK |
1405 | } |
1406 | ||
1e6e2755 | 1407 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1408 | { |
0105d1a5 | 1409 | int ret = 0; |
97222cc8 | 1410 | |
0105d1a5 | 1411 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1412 | |
0105d1a5 | 1413 | switch (reg) { |
97222cc8 | 1414 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1415 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1416 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1417 | else |
1418 | ret = 1; | |
97222cc8 ED |
1419 | break; |
1420 | ||
1421 | case APIC_TASKPRI: | |
b209749f | 1422 | report_tpr_access(apic, true); |
97222cc8 ED |
1423 | apic_set_tpr(apic, val & 0xff); |
1424 | break; | |
1425 | ||
1426 | case APIC_EOI: | |
1427 | apic_set_eoi(apic); | |
1428 | break; | |
1429 | ||
1430 | case APIC_LDR: | |
0105d1a5 | 1431 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1432 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1433 | else |
1434 | ret = 1; | |
97222cc8 ED |
1435 | break; |
1436 | ||
1437 | case APIC_DFR: | |
1e08ec4a | 1438 | if (!apic_x2apic_mode(apic)) { |
1e6e2755 | 1439 | kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1440 | recalculate_apic_map(apic->vcpu->kvm); |
1441 | } else | |
0105d1a5 | 1442 | ret = 1; |
97222cc8 ED |
1443 | break; |
1444 | ||
fc61b800 GN |
1445 | case APIC_SPIV: { |
1446 | u32 mask = 0x3ff; | |
dfb95954 | 1447 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1448 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1449 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1450 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1451 | int i; | |
1452 | u32 lvt_val; | |
1453 | ||
1e6e2755 | 1454 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 1455 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 1456 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 1457 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
1458 | lvt_val | APIC_LVT_MASKED); |
1459 | } | |
b6ac0695 | 1460 | apic_update_lvtt(apic); |
d3c7b77d | 1461 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1462 | |
1463 | } | |
1464 | break; | |
fc61b800 | 1465 | } |
97222cc8 ED |
1466 | case APIC_ICR: |
1467 | /* No delay here, so we always clear the pending bit */ | |
1e6e2755 | 1468 | kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); |
97222cc8 ED |
1469 | apic_send_ipi(apic); |
1470 | break; | |
1471 | ||
1472 | case APIC_ICR2: | |
0105d1a5 GN |
1473 | if (!apic_x2apic_mode(apic)) |
1474 | val &= 0xff000000; | |
1e6e2755 | 1475 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
1476 | break; |
1477 | ||
23930f95 | 1478 | case APIC_LVT0: |
cc6e462c | 1479 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1480 | case APIC_LVTTHMR: |
1481 | case APIC_LVTPC: | |
97222cc8 ED |
1482 | case APIC_LVT1: |
1483 | case APIC_LVTERR: | |
1484 | /* TODO: Check vector */ | |
c48f1496 | 1485 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1486 | val |= APIC_LVT_MASKED; |
1487 | ||
0105d1a5 | 1488 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1e6e2755 | 1489 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 ED |
1490 | |
1491 | break; | |
1492 | ||
b6ac0695 | 1493 | case APIC_LVTT: |
c48f1496 | 1494 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1495 | val |= APIC_LVT_MASKED; |
1496 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 1497 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 1498 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1499 | break; |
1500 | ||
97222cc8 | 1501 | case APIC_TMICT: |
a3e06bbe LJ |
1502 | if (apic_lvtt_tscdeadline(apic)) |
1503 | break; | |
1504 | ||
d3c7b77d | 1505 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 1506 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 1507 | start_apic_timer(apic); |
0105d1a5 | 1508 | break; |
97222cc8 ED |
1509 | |
1510 | case APIC_TDCR: | |
1511 | if (val & 4) | |
7712de87 | 1512 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
1e6e2755 | 1513 | kvm_lapic_set_reg(apic, APIC_TDCR, val); |
97222cc8 ED |
1514 | update_divide_count(apic); |
1515 | break; | |
1516 | ||
0105d1a5 GN |
1517 | case APIC_ESR: |
1518 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1519 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1520 | ret = 1; |
1521 | } | |
1522 | break; | |
1523 | ||
1524 | case APIC_SELF_IPI: | |
1525 | if (apic_x2apic_mode(apic)) { | |
1e6e2755 | 1526 | kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); |
0105d1a5 GN |
1527 | } else |
1528 | ret = 1; | |
1529 | break; | |
97222cc8 | 1530 | default: |
0105d1a5 | 1531 | ret = 1; |
97222cc8 ED |
1532 | break; |
1533 | } | |
0105d1a5 GN |
1534 | if (ret) |
1535 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1536 | return ret; | |
1537 | } | |
1e6e2755 | 1538 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 1539 | |
e32edf4f | 1540 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1541 | gpa_t address, int len, const void *data) |
1542 | { | |
1543 | struct kvm_lapic *apic = to_lapic(this); | |
1544 | unsigned int offset = address - apic->base_address; | |
1545 | u32 val; | |
1546 | ||
1547 | if (!apic_mmio_in_range(apic, address)) | |
1548 | return -EOPNOTSUPP; | |
1549 | ||
1550 | /* | |
1551 | * APIC register must be aligned on 128-bits boundary. | |
1552 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1553 | * Refer SDM 8.4.1 | |
1554 | */ | |
1555 | if (len != 4 || (offset & 0xf)) { | |
1556 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1557 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1558 | return 0; |
0105d1a5 GN |
1559 | } |
1560 | ||
1561 | val = *(u32*)data; | |
1562 | ||
1563 | /* too common printing */ | |
1564 | if (offset != APIC_EOI) | |
1565 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1566 | "0x%x\n", __func__, offset, len, val); | |
1567 | ||
1e6e2755 | 1568 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 1569 | |
bda9020e | 1570 | return 0; |
97222cc8 ED |
1571 | } |
1572 | ||
58fbbf26 KT |
1573 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1574 | { | |
1e6e2755 | 1575 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
1576 | } |
1577 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1578 | ||
83d4c286 YZ |
1579 | /* emulate APIC access in a trap manner */ |
1580 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1581 | { | |
1582 | u32 val = 0; | |
1583 | ||
1584 | /* hw has done the conditional check and inst decode */ | |
1585 | offset &= 0xff0; | |
1586 | ||
1e6e2755 | 1587 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
1588 | |
1589 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 1590 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
1591 | } |
1592 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1593 | ||
d589444e | 1594 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1595 | { |
f8c1ea10 GN |
1596 | struct kvm_lapic *apic = vcpu->arch.apic; |
1597 | ||
ad312c7c | 1598 | if (!vcpu->arch.apic) |
97222cc8 ED |
1599 | return; |
1600 | ||
f8c1ea10 | 1601 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1602 | |
c5cc421b GN |
1603 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1604 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1605 | ||
e462755c | 1606 | if (!apic->sw_enabled) |
f8c1ea10 | 1607 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1608 | |
f8c1ea10 GN |
1609 | if (apic->regs) |
1610 | free_page((unsigned long)apic->regs); | |
1611 | ||
1612 | kfree(apic); | |
97222cc8 ED |
1613 | } |
1614 | ||
1615 | /* | |
1616 | *---------------------------------------------------------------------- | |
1617 | * LAPIC interface | |
1618 | *---------------------------------------------------------------------- | |
1619 | */ | |
1620 | ||
a3e06bbe LJ |
1621 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1622 | { | |
1623 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1624 | |
bce87cce | 1625 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1626 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1627 | return 0; |
1628 | ||
1629 | return apic->lapic_timer.tscdeadline; | |
1630 | } | |
1631 | ||
1632 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1633 | { | |
1634 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1635 | |
bce87cce | 1636 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1637 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1638 | return; |
1639 | ||
1640 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1641 | apic->lapic_timer.tscdeadline = data; | |
1642 | start_apic_timer(apic); | |
1643 | } | |
1644 | ||
97222cc8 ED |
1645 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1646 | { | |
ad312c7c | 1647 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1648 | |
b93463aa | 1649 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 1650 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1651 | } |
1652 | ||
1653 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1654 | { | |
97222cc8 ED |
1655 | u64 tpr; |
1656 | ||
dfb95954 | 1657 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1658 | |
1659 | return (tpr & 0xf0) >> 4; | |
1660 | } | |
1661 | ||
1662 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1663 | { | |
8d14695f | 1664 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1665 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1666 | |
1667 | if (!apic) { | |
1668 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1669 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1670 | return; |
1671 | } | |
c5af89b6 | 1672 | |
e66d2ae7 JK |
1673 | vcpu->arch.apic_base = value; |
1674 | ||
c5cc421b | 1675 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1676 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
c5cc421b GN |
1677 | if (value & MSR_IA32_APICBASE_ENABLE) |
1678 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1679 | else | |
1680 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1681 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1682 | } |
1683 | ||
8d14695f YZ |
1684 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1685 | if (value & X2APIC_ENABLE) { | |
257b9a5f | 1686 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); |
8d14695f YZ |
1687 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); |
1688 | } else | |
1689 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1690 | } |
8d14695f | 1691 | |
ad312c7c | 1692 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1693 | MSR_IA32_APICBASE_BASE; |
1694 | ||
db324fe6 NA |
1695 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1696 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1697 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1698 | ||
97222cc8 ED |
1699 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1700 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1701 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1702 | |
1703 | } | |
1704 | ||
d28bc9dd | 1705 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 ED |
1706 | { |
1707 | struct kvm_lapic *apic; | |
1708 | int i; | |
1709 | ||
b8688d51 | 1710 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1711 | |
1712 | ASSERT(vcpu); | |
ad312c7c | 1713 | apic = vcpu->arch.apic; |
97222cc8 ED |
1714 | ASSERT(apic != NULL); |
1715 | ||
1716 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1717 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1718 | |
d28bc9dd NA |
1719 | if (!init_event) |
1720 | kvm_apic_set_id(apic, vcpu->vcpu_id); | |
fc61b800 | 1721 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 1722 | |
1e6e2755 SS |
1723 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
1724 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 1725 | apic_update_lvtt(apic); |
0da029ed | 1726 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) |
1e6e2755 | 1727 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 1728 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 1729 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 1730 | |
1e6e2755 | 1731 | kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); |
f8c1ea10 | 1732 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 1733 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
1734 | if (!apic_x2apic_mode(apic)) |
1735 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
1736 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
1737 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
1738 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
1739 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
1740 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 1741 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
1742 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
1743 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1744 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 1745 | } |
d62caabb AS |
1746 | apic->irr_pending = vcpu->arch.apicv_active; |
1747 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 1748 | apic->highest_isr_cache = -1; |
b33ac88b | 1749 | update_divide_count(apic); |
d3c7b77d | 1750 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1751 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1752 | kvm_lapic_set_base(vcpu, |
1753 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1754 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1755 | apic_update_ppr(apic); |
1756 | ||
e1035715 | 1757 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1758 | vcpu->arch.apic_attention = 0; |
e1035715 | 1759 | |
98eff52a | 1760 | apic_debug("%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1761 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1762 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1763 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1764 | } |
1765 | ||
97222cc8 ED |
1766 | /* |
1767 | *---------------------------------------------------------------------- | |
1768 | * timer interface | |
1769 | *---------------------------------------------------------------------- | |
1770 | */ | |
1b9778da | 1771 | |
2a6eac96 | 1772 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1773 | { |
d3c7b77d | 1774 | return apic_lvtt_period(apic); |
97222cc8 ED |
1775 | } |
1776 | ||
3d80840d MT |
1777 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1778 | { | |
54e9818f | 1779 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1780 | |
1e3161b4 | 1781 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 1782 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
1783 | |
1784 | return 0; | |
1785 | } | |
1786 | ||
89342082 | 1787 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1788 | { |
dfb95954 | 1789 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 1790 | int vector, mode, trig_mode; |
23930f95 | 1791 | |
c48f1496 | 1792 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1793 | vector = reg & APIC_VECTOR_MASK; |
1794 | mode = reg & APIC_MODE_MASK; | |
1795 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1796 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1797 | NULL); | |
23930f95 JK |
1798 | } |
1799 | return 0; | |
1800 | } | |
1b9778da | 1801 | |
8fdb2351 | 1802 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1803 | { |
8fdb2351 JK |
1804 | struct kvm_lapic *apic = vcpu->arch.apic; |
1805 | ||
1806 | if (apic) | |
1807 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1808 | } |
1809 | ||
d76685c4 GH |
1810 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1811 | .read = apic_mmio_read, | |
1812 | .write = apic_mmio_write, | |
d76685c4 GH |
1813 | }; |
1814 | ||
e9d90d47 AK |
1815 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1816 | { | |
1817 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 1818 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 1819 | |
5d87db71 | 1820 | apic_timer_expired(apic); |
e9d90d47 | 1821 | |
2a6eac96 | 1822 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1823 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1824 | return HRTIMER_RESTART; | |
1825 | } else | |
1826 | return HRTIMER_NORESTART; | |
1827 | } | |
1828 | ||
97222cc8 ED |
1829 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1830 | { | |
1831 | struct kvm_lapic *apic; | |
1832 | ||
1833 | ASSERT(vcpu != NULL); | |
1834 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1835 | ||
1836 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1837 | if (!apic) | |
1838 | goto nomem; | |
1839 | ||
ad312c7c | 1840 | vcpu->arch.apic = apic; |
97222cc8 | 1841 | |
afc20184 TY |
1842 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1843 | if (!apic->regs) { | |
97222cc8 ED |
1844 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1845 | vcpu->vcpu_id); | |
d589444e | 1846 | goto nomem_free_apic; |
97222cc8 | 1847 | } |
97222cc8 ED |
1848 | apic->vcpu = vcpu; |
1849 | ||
d3c7b77d | 1850 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
61abdbe0 | 1851 | HRTIMER_MODE_ABS_PINNED); |
e9d90d47 | 1852 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1853 | |
c5cc421b GN |
1854 | /* |
1855 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1856 | * thinking that APIC satet has changed. | |
1857 | */ | |
1858 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1859 | kvm_lapic_set_base(vcpu, |
1860 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1861 | |
f8c1ea10 | 1862 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d28bc9dd | 1863 | kvm_lapic_reset(vcpu, false); |
d76685c4 | 1864 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1865 | |
1866 | return 0; | |
d589444e RR |
1867 | nomem_free_apic: |
1868 | kfree(apic); | |
97222cc8 | 1869 | nomem: |
97222cc8 ED |
1870 | return -ENOMEM; |
1871 | } | |
97222cc8 ED |
1872 | |
1873 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1874 | { | |
ad312c7c | 1875 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1876 | int highest_irr; |
1877 | ||
f8543d6a | 1878 | if (!apic_enabled(apic)) |
97222cc8 ED |
1879 | return -1; |
1880 | ||
6e5d865c | 1881 | apic_update_ppr(apic); |
97222cc8 ED |
1882 | highest_irr = apic_find_highest_irr(apic); |
1883 | if ((highest_irr == -1) || | |
dfb95954 | 1884 | ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1885 | return -1; |
1886 | return highest_irr; | |
1887 | } | |
1888 | ||
40487c68 QH |
1889 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1890 | { | |
dfb95954 | 1891 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1892 | int r = 0; |
1893 | ||
c48f1496 | 1894 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1895 | r = 1; |
1896 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1897 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1898 | r = 1; | |
40487c68 QH |
1899 | return r; |
1900 | } | |
1901 | ||
1b9778da ED |
1902 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1903 | { | |
ad312c7c | 1904 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1905 | |
54e9818f | 1906 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
f1ed0450 | 1907 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
1908 | if (apic_lvtt_tscdeadline(apic)) |
1909 | apic->lapic_timer.tscdeadline = 0; | |
f1ed0450 | 1910 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
1911 | } |
1912 | } | |
1913 | ||
97222cc8 ED |
1914 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1915 | { | |
1916 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1917 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1918 | |
1919 | if (vector == -1) | |
1920 | return -1; | |
1921 | ||
56cc2406 WL |
1922 | /* |
1923 | * We get here even with APIC virtualization enabled, if doing | |
1924 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
1925 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
1926 | * because the process would deliver it through the IDT. | |
1927 | */ | |
1928 | ||
8680b94b | 1929 | apic_set_isr(vector, apic); |
97222cc8 ED |
1930 | apic_update_ppr(apic); |
1931 | apic_clear_irr(vector, apic); | |
5c919412 AS |
1932 | |
1933 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { | |
1934 | apic_clear_isr(vector, apic); | |
1935 | apic_update_ppr(apic); | |
1936 | } | |
1937 | ||
97222cc8 ED |
1938 | return vector; |
1939 | } | |
96ad2cc6 | 1940 | |
64eb0620 GN |
1941 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1942 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1943 | { |
ad312c7c | 1944 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1945 | |
5dbc8f3f | 1946 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1947 | /* set SPIV separately to get count of SW disabled APICs right */ |
1948 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1949 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1950 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1951 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1952 | kvm_apic_set_version(vcpu); |
1953 | ||
96ad2cc6 | 1954 | apic_update_ppr(apic); |
d3c7b77d | 1955 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 1956 | apic_update_lvtt(apic); |
dfb95954 | 1957 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
1958 | update_divide_count(apic); |
1959 | start_apic_timer(apic); | |
6e24a6ef | 1960 | apic->irr_pending = true; |
d62caabb | 1961 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 1962 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 1963 | apic->highest_isr_cache = -1; |
d62caabb | 1964 | if (vcpu->arch.apicv_active) { |
be8ca170 SS |
1965 | if (kvm_x86_ops->apicv_post_state_restore) |
1966 | kvm_x86_ops->apicv_post_state_restore(vcpu); | |
4114c27d WW |
1967 | kvm_x86_ops->hwapic_irr_update(vcpu, |
1968 | apic_find_highest_irr(apic)); | |
67c9dddc | 1969 | kvm_x86_ops->hwapic_isr_update(vcpu, |
b4eef9b3 | 1970 | apic_find_highest_isr(apic)); |
d62caabb | 1971 | } |
3842d135 | 1972 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
1973 | if (ioapic_in_kernel(vcpu->kvm)) |
1974 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
1975 | |
1976 | vcpu->arch.apic_arb_prio = 0; | |
96ad2cc6 | 1977 | } |
a3d7f85f | 1978 | |
2f52d58c | 1979 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1980 | { |
a3d7f85f ED |
1981 | struct hrtimer *timer; |
1982 | ||
bce87cce | 1983 | if (!lapic_in_kernel(vcpu)) |
a3d7f85f ED |
1984 | return; |
1985 | ||
54e9818f | 1986 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 1987 | if (hrtimer_cancel(timer)) |
61abdbe0 | 1988 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); |
a3d7f85f | 1989 | } |
b93463aa | 1990 | |
ae7a2a3f MT |
1991 | /* |
1992 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
1993 | * | |
1994 | * Detect whether guest triggered PV EOI since the | |
1995 | * last entry. If yes, set EOI on guests's behalf. | |
1996 | * Clear PV EOI in guest memory in any case. | |
1997 | */ | |
1998 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
1999 | struct kvm_lapic *apic) | |
2000 | { | |
2001 | bool pending; | |
2002 | int vector; | |
2003 | /* | |
2004 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2005 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2006 | * | |
2007 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2008 | * -> host disabled PV EOI. | |
2009 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2010 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2011 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2012 | * -> host enabled PV EOI, guest executed EOI. | |
2013 | */ | |
2014 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2015 | pending = pv_eoi_get_pending(vcpu); | |
2016 | /* | |
2017 | * Clear pending bit in any case: it will be set again on vmentry. | |
2018 | * While this might not be ideal from performance point of view, | |
2019 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2020 | */ | |
2021 | pv_eoi_clr_pending(vcpu); | |
2022 | if (pending) | |
2023 | return; | |
2024 | vector = apic_set_eoi(apic); | |
2025 | trace_kvm_pv_eoi(apic, vector); | |
2026 | } | |
2027 | ||
b93463aa AK |
2028 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2029 | { | |
2030 | u32 data; | |
b93463aa | 2031 | |
ae7a2a3f MT |
2032 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2033 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2034 | ||
41383771 | 2035 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2036 | return; |
2037 | ||
603242a8 NK |
2038 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2039 | sizeof(u32))) | |
2040 | return; | |
b93463aa AK |
2041 | |
2042 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2043 | } | |
2044 | ||
ae7a2a3f MT |
2045 | /* |
2046 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2047 | * | |
2048 | * Detect whether it's safe to enable PV EOI and | |
2049 | * if yes do so. | |
2050 | */ | |
2051 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2052 | struct kvm_lapic *apic) | |
2053 | { | |
2054 | if (!pv_eoi_enabled(vcpu) || | |
2055 | /* IRR set or many bits in ISR: could be nested. */ | |
2056 | apic->irr_pending || | |
2057 | /* Cache not set: could be safe but we don't bother. */ | |
2058 | apic->highest_isr_cache == -1 || | |
2059 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2060 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2061 | /* |
2062 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2063 | * so we need not do anything here. | |
2064 | */ | |
2065 | return; | |
2066 | } | |
2067 | ||
2068 | pv_eoi_set_pending(apic->vcpu); | |
2069 | } | |
2070 | ||
b93463aa AK |
2071 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2072 | { | |
2073 | u32 data, tpr; | |
2074 | int max_irr, max_isr; | |
ae7a2a3f | 2075 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2076 | |
ae7a2a3f MT |
2077 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2078 | ||
41383771 | 2079 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2080 | return; |
2081 | ||
dfb95954 | 2082 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2083 | max_irr = apic_find_highest_irr(apic); |
2084 | if (max_irr < 0) | |
2085 | max_irr = 0; | |
2086 | max_isr = apic_find_highest_isr(apic); | |
2087 | if (max_isr < 0) | |
2088 | max_isr = 0; | |
2089 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2090 | ||
fda4e2e8 AH |
2091 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2092 | sizeof(u32)); | |
b93463aa AK |
2093 | } |
2094 | ||
fda4e2e8 | 2095 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2096 | { |
fda4e2e8 AH |
2097 | if (vapic_addr) { |
2098 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2099 | &vcpu->arch.apic->vapic_cache, | |
2100 | vapic_addr, sizeof(u32))) | |
2101 | return -EINVAL; | |
41383771 | 2102 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2103 | } else { |
41383771 | 2104 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2105 | } |
2106 | ||
2107 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2108 | return 0; | |
b93463aa | 2109 | } |
0105d1a5 GN |
2110 | |
2111 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2112 | { | |
2113 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2114 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2115 | ||
35754c98 | 2116 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2117 | return 1; |
2118 | ||
c69d3d9b NA |
2119 | if (reg == APIC_ICR2) |
2120 | return 1; | |
2121 | ||
0105d1a5 | 2122 | /* if this is ICR write vector before command */ |
decdc283 | 2123 | if (reg == APIC_ICR) |
1e6e2755 SS |
2124 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2125 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2126 | } |
2127 | ||
2128 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2129 | { | |
2130 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2131 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2132 | ||
35754c98 | 2133 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2134 | return 1; |
2135 | ||
c69d3d9b NA |
2136 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2137 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2138 | reg); | |
2139 | return 1; | |
2140 | } | |
2141 | ||
1e6e2755 | 2142 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2143 | return 1; |
decdc283 | 2144 | if (reg == APIC_ICR) |
1e6e2755 | 2145 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2146 | |
2147 | *data = (((u64)high) << 32) | low; | |
2148 | ||
2149 | return 0; | |
2150 | } | |
10388a07 GN |
2151 | |
2152 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2153 | { | |
2154 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2155 | ||
bce87cce | 2156 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2157 | return 1; |
2158 | ||
2159 | /* if this is ICR write vector before command */ | |
2160 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2161 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2162 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2163 | } |
2164 | ||
2165 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2166 | { | |
2167 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2168 | u32 low, high = 0; | |
2169 | ||
bce87cce | 2170 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2171 | return 1; |
2172 | ||
1e6e2755 | 2173 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2174 | return 1; |
2175 | if (reg == APIC_ICR) | |
1e6e2755 | 2176 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2177 | |
2178 | *data = (((u64)high) << 32) | low; | |
2179 | ||
2180 | return 0; | |
2181 | } | |
ae7a2a3f MT |
2182 | |
2183 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2184 | { | |
2185 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2186 | if (!IS_ALIGNED(addr, 4)) | |
2187 | return 1; | |
2188 | ||
2189 | vcpu->arch.pv_eoi.msr_val = data; | |
2190 | if (!pv_eoi_enabled(vcpu)) | |
2191 | return 0; | |
2192 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
8f964525 | 2193 | addr, sizeof(u8)); |
ae7a2a3f | 2194 | } |
c5cc421b | 2195 | |
66450a21 JK |
2196 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2197 | { | |
2198 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2199 | u8 sipi_vector; |
299018f4 | 2200 | unsigned long pe; |
66450a21 | 2201 | |
bce87cce | 2202 | if (!lapic_in_kernel(vcpu) || !apic->pending_events) |
66450a21 JK |
2203 | return; |
2204 | ||
cd7764fe PB |
2205 | /* |
2206 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2207 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2208 | * and delay processing of INIT until the next RSM. | |
2209 | */ | |
2210 | if (is_smm(vcpu)) { | |
2211 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2212 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2213 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2214 | return; | |
2215 | } | |
299018f4 | 2216 | |
cd7764fe | 2217 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2218 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd NA |
2219 | kvm_lapic_reset(vcpu, true); |
2220 | kvm_vcpu_reset(vcpu, true); | |
66450a21 JK |
2221 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2222 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2223 | else | |
2224 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2225 | } | |
299018f4 | 2226 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2227 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2228 | /* evaluate pending_events before reading the vector */ | |
2229 | smp_rmb(); | |
2230 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2231 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2232 | vcpu->vcpu_id, sipi_vector); |
2233 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2234 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2235 | } | |
2236 | } | |
2237 | ||
c5cc421b GN |
2238 | void kvm_lapic_init(void) |
2239 | { | |
2240 | /* do not patch jump label more than once per second */ | |
2241 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2242 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2243 | } |