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KVM: add "new" argument to kvm_arch_commit_memory_region
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
3548a259
RK		 136/* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
3b5a5ffa
RK		 144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
1e08ec4a
GN		 158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
173beedc
NA		 171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
25995e5b 174 u32 ldr, aid;
1e08ec4a 175
df04d1d1
RK		 176 if (!kvm_apic_present(vcpu))
177 continue;
178
25995e5b 179 aid = kvm_apic_id(apic);
1e08ec4a 180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
1e08ec4a 181
25995e5b
RK		 182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
3548a259 184
3b5a5ffa
RK		 185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
3548a259
RK		 196 continue;
197
3b5a5ffa
RK		 198 apic_logical_id(new, ldr, &cid, &lid);
199
25995e5b 200 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
c7c9c56c 211
3d81bc7e 212 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 213}
214
1e1b6c26
NA		 215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
e462755c 217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 218
219 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
1e1b6c26
NA		 224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
1e08ec4a
GN		 231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
97222cc8
ED		 243static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
244{
c48f1496 245 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 246}
247
248static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
249{
c48f1496 250 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 251}
252
a3e06bbe
LJ		 253static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
254{
f30ebc31 255 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 256}
257
97222cc8
ED		 258static inline int apic_lvtt_period(struct kvm_lapic *apic)
259{
f30ebc31 260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 261}
262
263static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
264{
f30ebc31 265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 266}
267
cc6e462c
JK		 268static inline int apic_lvt_nmi_mode(u32 lvt_val)
269{
270 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
271}
272
fc61b800
GN		 273void kvm_apic_set_version(struct kvm_vcpu *vcpu)
274{
275 struct kvm_lapic *apic = vcpu->arch.apic;
276 struct kvm_cpuid_entry2 *feat;
277 u32 v = APIC_VERSION;
278
c48f1496 279 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 280 return;
281
282 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
283 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
284 v |= APIC_LVR_DIRECTED_EOI;
285 apic_set_reg(apic, APIC_LVR, v);
286}
287
f1d24831 288static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 289 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 290 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
291 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
292 LINT_MASK, LINT_MASK, /* LVT0-1 */
293 LVT_MASK /* LVTERR */
294};
295
296static int find_highest_vector(void *bitmap)
297{
ecba9a52
TY		 298 int vec;
299 u32 *reg;
97222cc8 300
ecba9a52
TY		 301 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
302 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
303 reg = bitmap + REG_POS(vec);
304 if (*reg)
305 return fls(*reg) - 1 + vec;
306 }
97222cc8 307
ecba9a52 308 return -1;
97222cc8
ED		 309}
310
8680b94b
MT		 311static u8 count_vectors(void *bitmap)
312{
ecba9a52
TY		 313 int vec;
314 u32 *reg;
8680b94b 315 u8 count = 0;
ecba9a52
TY		 316
317 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
318 reg = bitmap + REG_POS(vec);
319 count += hweight32(*reg);
320 }
321
8680b94b
MT		 322 return count;
323}
324
705699a1 325void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 326{
327 u32 i, pir_val;
a20ed54d
YZ		 328
329 for (i = 0; i <= 7; i++) {
330 pir_val = xchg(&pir[i], 0);
331 if (pir_val)
705699a1 332 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 333 }
334}
705699a1
WV		 335EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
336
337void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
338{
339 struct kvm_lapic *apic = vcpu->arch.apic;
340
341 __kvm_apic_update_irr(pir, apic->regs);
342}
a20ed54d
YZ		 343EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
344
11f5cc05 345static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 346{
11f5cc05 347 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 348 /*
349 * irr_pending must be true if any interrupt is pending; set it after
350 * APIC_IRR to avoid race with apic_clear_irr
351 */
352 apic->irr_pending = true;
97222cc8
ED		 353}
354
33e4c686 355static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 356{
33e4c686 357 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 358}
359
360static inline int apic_find_highest_irr(struct kvm_lapic *apic)
361{
362 int result;
363
c7c9c56c
YZ		 364 /*
365 * Note that irr_pending is just a hint. It will be always
366 * true with virtual interrupt delivery enabled.
367 */
33e4c686
GN		 368 if (!apic->irr_pending)
369 return -1;
370
5a71785d 371 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 372 result = apic_search_irr(apic);
97222cc8
ED		 373 ASSERT(result == -1 || result >= 16);
374
375 return result;
376}
377
33e4c686
GN		 378static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
379{
56cc2406
WL		 380 struct kvm_vcpu *vcpu;
381
382 vcpu = apic->vcpu;
383
f210f757 384 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 385 /* try to update RVI */
f210f757 386 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 387 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 388 } else {
389 apic->irr_pending = false;
390 apic_clear_vector(vec, apic->regs + APIC_IRR);
391 if (apic_search_irr(apic) != -1)
392 apic->irr_pending = true;
56cc2406 393 }
33e4c686
GN		 394}
395
8680b94b
MT		 396static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
397{
56cc2406
WL		 398 struct kvm_vcpu *vcpu;
399
400 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
401 return;
402
403 vcpu = apic->vcpu;
fc57ac2c 404
8680b94b 405 /*
56cc2406
WL		 406 * With APIC virtualization enabled, all caching is disabled
407 * because the processor can modify ISR under the hood. Instead
408 * just set SVI.
8680b94b 409 */
b4eef9b3 410 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 411 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
412 else {
413 ++apic->isr_count;
414 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
415 /*
416 * ISR (in service register) bit is set when injecting an interrupt.
417 * The highest vector is injected. Thus the latest bit set matches
418 * the highest bit in ISR.
419 */
420 apic->highest_isr_cache = vec;
421 }
8680b94b
MT		 422}
423
fc57ac2c
PB		 424static inline int apic_find_highest_isr(struct kvm_lapic *apic)
425{
426 int result;
427
428 /*
429 * Note that isr_count is always 1, and highest_isr_cache
430 * is always -1, with APIC virtualization enabled.
431 */
432 if (!apic->isr_count)
433 return -1;
434 if (likely(apic->highest_isr_cache != -1))
435 return apic->highest_isr_cache;
436
437 result = find_highest_vector(apic->regs + APIC_ISR);
438 ASSERT(result == -1 || result >= 16);
439
440 return result;
441}
442
8680b94b
MT		 443static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
444{
fc57ac2c
PB		 445 struct kvm_vcpu *vcpu;
446 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
447 return;
448
449 vcpu = apic->vcpu;
450
451 /*
452 * We do get here for APIC virtualization enabled if the guest
453 * uses the Hyper-V APIC enlightenment. In this case we may need
454 * to trigger a new interrupt delivery by writing the SVI field;
455 * on the other hand isr_count and highest_isr_cache are unused
456 * and must be left alone.
457 */
b4eef9b3 458 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 459 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
460 apic_find_highest_isr(apic));
461 else {
8680b94b 462 --apic->isr_count;
fc57ac2c
PB		 463 BUG_ON(apic->isr_count < 0);
464 apic->highest_isr_cache = -1;
465 }
8680b94b
MT		 466}
467
6e5d865c
YS		 468int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
469{
6e5d865c
YS		 470 int highest_irr;
471
33e4c686
GN		 472 /* This may race with setting of irr in __apic_accept_irq() and
473 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
474 * will cause vmexit immediately and the value will be recalculated
475 * on the next vmentry.
476 */
c48f1496 477 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 478 return 0;
54e9818f 479 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 480
481 return highest_irr;
482}
6e5d865c 483
6da7e3f6 484static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 485 int vector, int level, int trig_mode,
486 unsigned long *dest_map);
6da7e3f6 487
b4f2225c
YZ		 488int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
489 unsigned long *dest_map)
97222cc8 490{
ad312c7c 491 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 492
58c2dde1 493 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 494 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 495}
496
ae7a2a3f
MT		 497static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
498{
499
500 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
501 sizeof(val));
502}
503
504static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
505{
506
507 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
508 sizeof(*val));
509}
510
511static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
512{
513 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
514}
515
516static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
517{
518 u8 val;
519 if (pv_eoi_get_user(vcpu, &val) < 0)
520 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 521 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 522 return val & 0x1;
523}
524
525static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
526{
527 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
528 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 529 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 530 return;
531 }
532 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
533}
534
535static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
536{
537 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
538 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 539 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 540 return;
541 }
542 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
543}
544
cf9e65b7
YZ		 545void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
546{
547 struct kvm_lapic *apic = vcpu->arch.apic;
548 int i;
549
550 for (i = 0; i < 8; i++)
551 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
552}
553
97222cc8
ED		 554static void apic_update_ppr(struct kvm_lapic *apic)
555{
3842d135 556 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 557 int isr;
558
c48f1496
GN		 559 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
560 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 561 isr = apic_find_highest_isr(apic);
562 isrv = (isr != -1) ? isr : 0;
563
564 if ((tpr & 0xf0) >= (isrv & 0xf0))
565 ppr = tpr & 0xff;
566 else
567 ppr = isrv & 0xf0;
568
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic, ppr, isr, isrv);
571
3842d135
AK		 572 if (old_ppr != ppr) {
573 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 574 if (ppr < old_ppr)
575 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 576 }
97222cc8
ED		 577}
578
579static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
580{
581 apic_set_reg(apic, APIC_TASKPRI, tpr);
582 apic_update_ppr(apic);
583}
584
03d2249e 585static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 586{
03d2249e
RK		 587 if (apic_x2apic_mode(apic))
588 return mda == X2APIC_BROADCAST;
589
590 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 591}
592
03d2249e 593static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 594{
03d2249e
RK		 595 if (kvm_apic_broadcast(apic, mda))
596 return true;
597
598 if (apic_x2apic_mode(apic))
599 return mda == kvm_apic_id(apic);
600
601 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 602}
603
52c233a4 604static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 605{
0105d1a5
GN		 606 u32 logical_id;
607
394457a9 608 if (kvm_apic_broadcast(apic, mda))
9368b567 609 return true;
394457a9 610
9368b567 611 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 612
9368b567 613 if (apic_x2apic_mode(apic))
8a395363
RK		 614 return ((logical_id >> 16) == (mda >> 16))
615 && (logical_id & mda & 0xffff) != 0;
97222cc8 616
9368b567 617 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 618 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 619
c48f1496 620 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 621 case APIC_DFR_FLAT:
9368b567 622 return (logical_id & mda) != 0;
97222cc8 623 case APIC_DFR_CLUSTER:
9368b567
RK		 624 return ((logical_id >> 4) == (mda >> 4))
625 && (logical_id & mda & 0xf) != 0;
97222cc8 626 default:
7712de87 627 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 628 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 629 return false;
97222cc8 630 }
97222cc8
ED		 631}
632
03d2249e
RK		 633/* KVM APIC implementation has two quirks
634 * - dest always begins at 0 while xAPIC MDA has offset 24,
635 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
636 */
637static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
638 struct kvm_lapic *target)
639{
640 bool ipi = source != NULL;
641 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
642
643 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
644 return X2APIC_BROADCAST;
645
646 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
647}
648
52c233a4 649bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 650 int short_hand, unsigned int dest, int dest_mode)
97222cc8 651{
ad312c7c 652 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 653 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 654
655 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 656 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 657 target, source, dest, dest_mode, short_hand);
658
bd371396 659 ASSERT(target);
97222cc8
ED		 660 switch (short_hand) {
661 case APIC_DEST_NOSHORT:
3697f302 662 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 663 return kvm_apic_match_physical_addr(target, mda);
343f94fe 664 else
03d2249e 665 return kvm_apic_match_logical_addr(target, mda);
97222cc8 666 case APIC_DEST_SELF:
9368b567 667 return target == source;
97222cc8 668 case APIC_DEST_ALLINC:
9368b567 669 return true;
97222cc8 670 case APIC_DEST_ALLBUT:
9368b567 671 return target != source;
97222cc8 672 default:
7712de87
JK		 673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
674 short_hand);
9368b567 675 return false;
97222cc8 676 }
97222cc8
ED		 677}
678
1e08ec4a 679bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 680 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 681{
682 struct kvm_apic_map *map;
683 unsigned long bitmap = 1;
684 struct kvm_lapic **dst;
685 int i;
bea15428 686 bool ret, x2apic_ipi;
1e08ec4a
GN		 687
688 *r = -1;
689
690 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 691 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 692 return true;
693 }
694
695 if (irq->shorthand)
696 return false;
697
bea15428 698 x2apic_ipi = src && apic_x2apic_mode(src);
9ea369b0
RK		 699 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
700 return false;
701
bea15428 702 ret = true;
1e08ec4a
GN		 703 rcu_read_lock();
704 map = rcu_dereference(kvm->arch.apic_map);
705
bea15428
PB		 706 if (!map) {
707 ret = false;
1e08ec4a 708 goto out;
bea15428 709 }
698f9755 710
3697f302 711 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 712 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
713 goto out;
714
715 dst = &map->phys_map[irq->dest_id];
1e08ec4a 716 } else {
3548a259
RK		 717 u16 cid;
718
719 if (!kvm_apic_logical_map_valid(map)) {
720 ret = false;
721 goto out;
722 }
723
3b5a5ffa 724 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
45c3094a
RK		 725
726 if (cid >= ARRAY_SIZE(map->logical_map))
727 goto out;
1e08ec4a 728
45c3094a 729 dst = map->logical_map[cid];
1e08ec4a 730
d1ebdbf9 731 if (kvm_lowest_prio_delivery(irq)) {
1e08ec4a
GN		 732 int l = -1;
733 for_each_set_bit(i, &bitmap, 16) {
734 if (!dst[i])
735 continue;
736 if (l < 0)
737 l = i;
738 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
739 l = i;
740 }
741
742 bitmap = (l >= 0) ? 1 << l : 0;
743 }
744 }
745
746 for_each_set_bit(i, &bitmap, 16) {
747 if (!dst[i])
748 continue;
749 if (*r < 0)
750 *r = 0;
b4f2225c 751 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 752 }
1e08ec4a
GN		 753out:
754 rcu_read_unlock();
755 return ret;
756}
757
97222cc8
ED		 758/*
759 * Add a pending IRQ into lapic.
760 * Return 1 if successfully added and 0 if discarded.
761 */
762static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 763 int vector, int level, int trig_mode,
764 unsigned long *dest_map)
97222cc8 765{
6da7e3f6 766 int result = 0;
c5ec1534 767 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 768
a183b638
PB		 769 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
770 trig_mode, vector);
97222cc8 771 switch (delivery_mode) {
97222cc8 772 case APIC_DM_LOWEST:
e1035715
GN		 773 vcpu->arch.apic_arb_prio++;
774 case APIC_DM_FIXED:
97222cc8
ED		 775 /* FIXME add logic for vcpu on reset */
776 if (unlikely(!apic_enabled(apic)))
777 break;
778
11f5cc05
JK		 779 result = 1;
780
b4f2225c
YZ		 781 if (dest_map)
782 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 783
11f5cc05 784 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 785 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 786 else {
787 apic_set_irr(vector, apic);
5a71785d
YZ		 788
789 kvm_make_request(KVM_REQ_EVENT, vcpu);
790 kvm_vcpu_kick(vcpu);
791 }
97222cc8
ED		 792 break;
793
794 case APIC_DM_REMRD:
24d2166b
R		 795 result = 1;
796 vcpu->arch.pv.pv_unhalted = 1;
797 kvm_make_request(KVM_REQ_EVENT, vcpu);
798 kvm_vcpu_kick(vcpu);
97222cc8
ED		 799 break;
800
801 case APIC_DM_SMI:
7712de87 802 apic_debug("Ignoring guest SMI\n");
97222cc8 803 break;
3419ffc8 804
97222cc8 805 case APIC_DM_NMI:
6da7e3f6 806 result = 1;
3419ffc8 807 kvm_inject_nmi(vcpu);
26df99c6 808 kvm_vcpu_kick(vcpu);
97222cc8
ED		 809 break;
810
811 case APIC_DM_INIT:
a52315e1 812 if (!trig_mode || level) {
6da7e3f6 813 result = 1;
66450a21
JK		 814 /* assumes that there are only KVM_APIC_INIT/SIPI */
815 apic->pending_events = (1UL << KVM_APIC_INIT);
816 /* make sure pending_events is visible before sending
817 * the request */
818 smp_wmb();
3842d135 819 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 820 kvm_vcpu_kick(vcpu);
821 } else {
1b10bf31
JK		 822 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
823 vcpu->vcpu_id);
c5ec1534 824 }
97222cc8
ED		 825 break;
826
827 case APIC_DM_STARTUP:
1b10bf31
JK		 828 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
829 vcpu->vcpu_id, vector);
66450a21
JK		 830 result = 1;
831 apic->sipi_vector = vector;
832 /* make sure sipi_vector is visible for the receiver */
833 smp_wmb();
834 set_bit(KVM_APIC_SIPI, &apic->pending_events);
835 kvm_make_request(KVM_REQ_EVENT, vcpu);
836 kvm_vcpu_kick(vcpu);
97222cc8
ED		 837 break;
838
23930f95
JK		 839 case APIC_DM_EXTINT:
840 /*
841 * Should only be called by kvm_apic_local_deliver() with LVT0,
842 * before NMI watchdog was enabled. Already handled by
843 * kvm_apic_accept_pic_intr().
844 */
845 break;
846
97222cc8
ED		 847 default:
848 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
849 delivery_mode);
850 break;
851 }
852 return result;
853}
854
e1035715 855int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 856{
e1035715 857 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 858}
859
c7c9c56c
YZ		 860static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
861{
c806a6ad 862 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
c7c9c56c
YZ		 863 int trigger_mode;
864 if (apic_test_vector(vector, apic->regs + APIC_TMR))
865 trigger_mode = IOAPIC_LEVEL_TRIG;
866 else
867 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 868 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 869 }
870}
871
ae7a2a3f 872static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 873{
874 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 875
876 trace_kvm_eoi(apic, vector);
877
97222cc8
ED		 878 /*
879 * Not every write EOI will has corresponding ISR,
880 * one example is when Kernel check timer on setup_IO_APIC
881 */
882 if (vector == -1)
ae7a2a3f 883 return vector;
97222cc8 884
8680b94b 885 apic_clear_isr(vector, apic);
97222cc8
ED		 886 apic_update_ppr(apic);
887
c7c9c56c 888 kvm_ioapic_send_eoi(apic, vector);
3842d135 889 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 890 return vector;
97222cc8
ED		 891}
892
c7c9c56c
YZ		 893/*
894 * this interface assumes a trap-like exit, which has already finished
895 * desired side effect including vISR and vPPR update.
896 */
897void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
898{
899 struct kvm_lapic *apic = vcpu->arch.apic;
900
901 trace_kvm_eoi(apic, vector);
902
903 kvm_ioapic_send_eoi(apic, vector);
904 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
905}
906EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
907
97222cc8
ED		 908static void apic_send_ipi(struct kvm_lapic *apic)
909{
c48f1496
GN		 910 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
911 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 912 struct kvm_lapic_irq irq;
97222cc8 913
58c2dde1
GN		 914 irq.vector = icr_low & APIC_VECTOR_MASK;
915 irq.delivery_mode = icr_low & APIC_MODE_MASK;
916 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 917 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 918 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
919 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 920 irq.msi_redir_hint = false;
0105d1a5
GN		 921 if (apic_x2apic_mode(apic))
922 irq.dest_id = icr_high;
923 else
924 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 925
1000ff8d
GN		 926 trace_kvm_apic_ipi(icr_low, irq.dest_id);
927
97222cc8
ED		 928 apic_debug("icr_high 0x%x, icr_low 0x%x, "
929 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 930 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
931 "msi_redir_hint 0x%x\n",
9b5843dd 932 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 933 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 934 irq.vector, irq.msi_redir_hint);
58c2dde1 935
b4f2225c 936 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 937}
938
939static u32 apic_get_tmcct(struct kvm_lapic *apic)
940{
b682b814
MT		 941 ktime_t remaining;
942 s64 ns;
9da8f4e8 943 u32 tmcct;
97222cc8
ED		 944
945 ASSERT(apic != NULL);
946
9da8f4e8 947 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 948 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
949 apic->lapic_timer.period == 0)
9da8f4e8
KP		 950 return 0;
951
ace15464 952 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 953 if (ktime_to_ns(remaining) < 0)
954 remaining = ktime_set(0, 0);
955
d3c7b77d
MT		 956 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
957 tmcct = div64_u64(ns,
958 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 959
960 return tmcct;
961}
962
b209749f
AK		 963static void __report_tpr_access(struct kvm_lapic *apic, bool write)
964{
965 struct kvm_vcpu *vcpu = apic->vcpu;
966 struct kvm_run *run = vcpu->run;
967
a8eeb04a 968 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 969 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 970 run->tpr_access.is_write = write;
971}
972
973static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
974{
975 if (apic->vcpu->arch.tpr_access_reporting)
976 __report_tpr_access(apic, write);
977}
978
97222cc8
ED		 979static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
980{
981 u32 val = 0;
982
983 if (offset >= LAPIC_MMIO_LENGTH)
984 return 0;
985
986 switch (offset) {
0105d1a5
GN		 987 case APIC_ID:
988 if (apic_x2apic_mode(apic))
989 val = kvm_apic_id(apic);
990 else
991 val = kvm_apic_id(apic) << 24;
992 break;
97222cc8 993 case APIC_ARBPRI:
7712de87 994 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 995 break;
996
997 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 998 if (apic_lvtt_tscdeadline(apic))
999 return 0;
1000
97222cc8
ED		 1001 val = apic_get_tmcct(apic);
1002 break;
4a4541a4
AK		 1003 case APIC_PROCPRI:
1004 apic_update_ppr(apic);
c48f1496 1005 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1006 break;
b209749f
AK		 1007 case APIC_TASKPRI:
1008 report_tpr_access(apic, false);
1009 /* fall thru */
97222cc8 1010 default:
c48f1496 1011 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1012 break;
1013 }
1014
1015 return val;
1016}
1017
d76685c4
GH		 1018static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1019{
1020 return container_of(dev, struct kvm_lapic, dev);
1021}
1022
0105d1a5
GN		 1023static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1024 void *data)
97222cc8 1025{
97222cc8
ED		 1026 unsigned char alignment = offset & 0xf;
1027 u32 result;
d5b0b5b1 1028 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1029 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1030
1031 if ((alignment + len) > 4) {
4088bb3c
GN		 1032 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1033 offset, len);
0105d1a5 1034 return 1;
97222cc8 1035 }
0105d1a5
GN		 1036
1037 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1038 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1039 offset);
0105d1a5
GN		 1040 return 1;
1041 }
1042
97222cc8
ED		 1043 result = __apic_read(apic, offset & ~0xf);
1044
229456fc
MT		 1045 trace_kvm_apic_read(offset, result);
1046
97222cc8
ED		 1047 switch (len) {
1048 case 1:
1049 case 2:
1050 case 4:
1051 memcpy(data, (char *)&result + alignment, len);
1052 break;
1053 default:
1054 printk(KERN_ERR "Local APIC read with len = %x, "
1055 "should be 1,2, or 4 instead\n", len);
1056 break;
1057 }
bda9020e 1058 return 0;
97222cc8
ED		 1059}
1060
0105d1a5
GN		 1061static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1062{
c48f1496 1063 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1064 addr >= apic->base_address &&
1065 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1066}
1067
e32edf4f 1068static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1069 gpa_t address, int len, void *data)
1070{
1071 struct kvm_lapic *apic = to_lapic(this);
1072 u32 offset = address - apic->base_address;
1073
1074 if (!apic_mmio_in_range(apic, address))
1075 return -EOPNOTSUPP;
1076
1077 apic_reg_read(apic, offset, len, data);
1078
1079 return 0;
1080}
1081
97222cc8
ED		 1082static void update_divide_count(struct kvm_lapic *apic)
1083{
1084 u32 tmp1, tmp2, tdcr;
1085
c48f1496 1086 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1087 tmp1 = tdcr & 0xf;
1088 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1089 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1090
1091 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1092 apic->divide_count);
97222cc8
ED		 1093}
1094
5d87db71
RK		 1095static void apic_timer_expired(struct kvm_lapic *apic)
1096{
1097 struct kvm_vcpu *vcpu = apic->vcpu;
1098 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1099 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1100
5d87db71
RK		 1101 if (atomic_read(&apic->lapic_timer.pending))
1102 return;
1103
1104 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1105 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1106
1107 if (waitqueue_active(q))
1108 wake_up_interruptible(q);
d0659d94
MT		 1109
1110 if (apic_lvtt_tscdeadline(apic))
1111 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1112}
1113
1114/*
1115 * On APICv, this test will cause a busy wait
1116 * during a higher-priority task.
1117 */
1118
1119static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1120{
1121 struct kvm_lapic *apic = vcpu->arch.apic;
1122 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1123
1124 if (kvm_apic_hw_enabled(apic)) {
1125 int vec = reg & APIC_VECTOR_MASK;
f9339860 1126 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1127
f9339860
MT		 1128 if (kvm_x86_ops->deliver_posted_interrupt)
1129 bitmap = apic->regs + APIC_IRR;
1130
1131 if (apic_test_vector(vec, bitmap))
1132 return true;
d0659d94
MT		 1133 }
1134 return false;
1135}
1136
1137void wait_lapic_expire(struct kvm_vcpu *vcpu)
1138{
1139 struct kvm_lapic *apic = vcpu->arch.apic;
1140 u64 guest_tsc, tsc_deadline;
1141
1142 if (!kvm_vcpu_has_lapic(vcpu))
1143 return;
1144
1145 if (apic->lapic_timer.expired_tscdeadline == 0)
1146 return;
1147
1148 if (!lapic_timer_int_injected(vcpu))
1149 return;
1150
1151 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1152 apic->lapic_timer.expired_tscdeadline = 0;
1153 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
6c19b753 1154 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1155
1156 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1157 if (guest_tsc < tsc_deadline)
1158 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1159}
1160
97222cc8
ED		 1161static void start_apic_timer(struct kvm_lapic *apic)
1162{
a3e06bbe 1163 ktime_t now;
d0659d94 1164
d3c7b77d 1165 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1166
a3e06bbe 1167 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1168 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1169 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1170 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1171 * APIC_BUS_CYCLE_NS * apic->divide_count;
1172
1173 if (!apic->lapic_timer.period)
1174 return;
1175 /*
1176 * Do not allow the guest to program periodic timers with small
1177 * interval, since the hrtimers are not throttled by the host
1178 * scheduler.
1179 */
1180 if (apic_lvtt_period(apic)) {
1181 s64 min_period = min_timer_period_us * 1000LL;
1182
1183 if (apic->lapic_timer.period < min_period) {
1184 pr_info_ratelimited(
1185 "kvm: vcpu %i: requested %lld ns "
1186 "lapic timer period limited to %lld ns\n",
1187 apic->vcpu->vcpu_id,
1188 apic->lapic_timer.period, min_period);
1189 apic->lapic_timer.period = min_period;
1190 }
9bc5791d 1191 }
0b975a3c 1192
a3e06bbe
LJ		 1193 hrtimer_start(&apic->lapic_timer.timer,
1194 ktime_add_ns(now, apic->lapic_timer.period),
1195 HRTIMER_MODE_ABS);
97222cc8 1196
a3e06bbe 1197 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1198 PRIx64 ", "
1199 "timer initial count 0x%x, period %lldns, "
b8688d51 1200 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1201 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1202 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1203 apic->lapic_timer.period,
97222cc8 1204 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1205 apic->lapic_timer.period)));
a3e06bbe
LJ		 1206 } else if (apic_lvtt_tscdeadline(apic)) {
1207 /* lapic timer in tsc deadline mode */
1208 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1209 u64 ns = 0;
d0659d94 1210 ktime_t expire;
a3e06bbe 1211 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1212 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1213 unsigned long flags;
1214
1215 if (unlikely(!tscdeadline || !this_tsc_khz))
1216 return;
1217
1218 local_irq_save(flags);
1219
1220 now = apic->lapic_timer.timer.base->get_time();
886b470c 1221 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1222 if (likely(tscdeadline > guest_tsc)) {
1223 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1224 do_div(ns, this_tsc_khz);
d0659d94
MT		 1225 expire = ktime_add_ns(now, ns);
1226 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1227 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1228 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1229 } else
1230 apic_timer_expired(apic);
a3e06bbe
LJ		 1231
1232 local_irq_restore(flags);
1233 }
97222cc8
ED		 1234}
1235
cc6e462c
JK		 1236static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1237{
c48f1496 1238 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1239
1240 if (apic_lvt_nmi_mode(lvt0_val)) {
1241 if (!nmi_wd_enabled) {
1242 apic_debug("Receive NMI setting on APIC_LVT0 "
1243 "for cpu %d\n", apic->vcpu->vcpu_id);
1244 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1245 }
1246 } else if (nmi_wd_enabled)
1247 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1248}
1249
0105d1a5 1250static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1251{
0105d1a5 1252 int ret = 0;
97222cc8 1253
0105d1a5 1254 trace_kvm_apic_write(reg, val);
97222cc8 1255
0105d1a5 1256 switch (reg) {
97222cc8 1257 case APIC_ID: /* Local APIC ID */
0105d1a5 1258 if (!apic_x2apic_mode(apic))
1e08ec4a 1259 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1260 else
1261 ret = 1;
97222cc8
ED		 1262 break;
1263
1264 case APIC_TASKPRI:
b209749f 1265 report_tpr_access(apic, true);
97222cc8
ED		 1266 apic_set_tpr(apic, val & 0xff);
1267 break;
1268
1269 case APIC_EOI:
1270 apic_set_eoi(apic);
1271 break;
1272
1273 case APIC_LDR:
0105d1a5 1274 if (!apic_x2apic_mode(apic))
1e08ec4a 1275 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1276 else
1277 ret = 1;
97222cc8
ED		 1278 break;
1279
1280 case APIC_DFR:
1e08ec4a 1281 if (!apic_x2apic_mode(apic)) {
0105d1a5 1282 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1283 recalculate_apic_map(apic->vcpu->kvm);
1284 } else
0105d1a5 1285 ret = 1;
97222cc8
ED		 1286 break;
1287
fc61b800
GN		 1288 case APIC_SPIV: {
1289 u32 mask = 0x3ff;
c48f1496 1290 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1291 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1292 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1293 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1294 int i;
1295 u32 lvt_val;
1296
1297 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1298 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1299 APIC_LVTT + 0x10 * i);
1300 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1301 lvt_val | APIC_LVT_MASKED);
1302 }
d3c7b77d 1303 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1304
1305 }
1306 break;
fc61b800 1307 }
97222cc8
ED		 1308 case APIC_ICR:
1309 /* No delay here, so we always clear the pending bit */
1310 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1311 apic_send_ipi(apic);
1312 break;
1313
1314 case APIC_ICR2:
0105d1a5
GN		 1315 if (!apic_x2apic_mode(apic))
1316 val &= 0xff000000;
1317 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1318 break;
1319
23930f95 1320 case APIC_LVT0:
cc6e462c 1321 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1322 case APIC_LVTTHMR:
1323 case APIC_LVTPC:
97222cc8
ED		 1324 case APIC_LVT1:
1325 case APIC_LVTERR:
1326 /* TODO: Check vector */
c48f1496 1327 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1328 val |= APIC_LVT_MASKED;
1329
0105d1a5
GN		 1330 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1331 apic_set_reg(apic, reg, val);
97222cc8
ED		 1332
1333 break;
1334
a323b409
RK		 1335 case APIC_LVTT: {
1336 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1337
1338 if (apic->lapic_timer.timer_mode != timer_mode) {
1339 apic->lapic_timer.timer_mode = timer_mode;
a3e06bbe 1340 hrtimer_cancel(&apic->lapic_timer.timer);
a323b409 1341 }
a3e06bbe 1342
c48f1496 1343 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1344 val |= APIC_LVT_MASKED;
1345 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1346 apic_set_reg(apic, APIC_LVTT, val);
1347 break;
a323b409 1348 }
a3e06bbe 1349
97222cc8 1350 case APIC_TMICT:
a3e06bbe
LJ		 1351 if (apic_lvtt_tscdeadline(apic))
1352 break;
1353
d3c7b77d 1354 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1355 apic_set_reg(apic, APIC_TMICT, val);
1356 start_apic_timer(apic);
0105d1a5 1357 break;
97222cc8
ED		 1358
1359 case APIC_TDCR:
1360 if (val & 4)
7712de87 1361 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1362 apic_set_reg(apic, APIC_TDCR, val);
1363 update_divide_count(apic);
1364 break;
1365
0105d1a5
GN		 1366 case APIC_ESR:
1367 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1368 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1369 ret = 1;
1370 }
1371 break;
1372
1373 case APIC_SELF_IPI:
1374 if (apic_x2apic_mode(apic)) {
1375 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1376 } else
1377 ret = 1;
1378 break;
97222cc8 1379 default:
0105d1a5 1380 ret = 1;
97222cc8
ED		 1381 break;
1382 }
0105d1a5
GN		 1383 if (ret)
1384 apic_debug("Local APIC Write to read-only register %x\n", reg);
1385 return ret;
1386}
1387
e32edf4f 1388static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1389 gpa_t address, int len, const void *data)
1390{
1391 struct kvm_lapic *apic = to_lapic(this);
1392 unsigned int offset = address - apic->base_address;
1393 u32 val;
1394
1395 if (!apic_mmio_in_range(apic, address))
1396 return -EOPNOTSUPP;
1397
1398 /*
1399 * APIC register must be aligned on 128-bits boundary.
1400 * 32/64/128 bits registers must be accessed thru 32 bits.
1401 * Refer SDM 8.4.1
1402 */
1403 if (len != 4 || (offset & 0xf)) {
1404 /* Don't shout loud, $infamous_os would cause only noise. */
1405 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1406 return 0;
0105d1a5
GN		 1407 }
1408
1409 val = *(u32*)data;
1410
1411 /* too common printing */
1412 if (offset != APIC_EOI)
1413 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1414 "0x%x\n", __func__, offset, len, val);
1415
1416 apic_reg_write(apic, offset & 0xff0, val);
1417
bda9020e 1418 return 0;
97222cc8
ED		 1419}
1420
58fbbf26
KT		 1421void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1422{
c48f1496 1423 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1424 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1425}
1426EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1427
83d4c286
YZ		 1428/* emulate APIC access in a trap manner */
1429void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1430{
1431 u32 val = 0;
1432
1433 /* hw has done the conditional check and inst decode */
1434 offset &= 0xff0;
1435
1436 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1437
1438 /* TODO: optimize to just emulate side effect w/o one more write */
1439 apic_reg_write(vcpu->arch.apic, offset, val);
1440}
1441EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1442
d589444e 1443void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1444{
f8c1ea10
GN		 1445 struct kvm_lapic *apic = vcpu->arch.apic;
1446
ad312c7c 1447 if (!vcpu->arch.apic)
97222cc8
ED		 1448 return;
1449
f8c1ea10 1450 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1451
c5cc421b
GN		 1452 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1453 static_key_slow_dec_deferred(&apic_hw_disabled);
1454
e462755c 1455 if (!apic->sw_enabled)
f8c1ea10 1456 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1457
f8c1ea10
GN		 1458 if (apic->regs)
1459 free_page((unsigned long)apic->regs);
1460
1461 kfree(apic);
97222cc8
ED		 1462}
1463
1464/*
1465 *----------------------------------------------------------------------
1466 * LAPIC interface
1467 *----------------------------------------------------------------------
1468 */
1469
a3e06bbe
LJ		 1470u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1471{
1472 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1473
c48f1496 1474 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1475 apic_lvtt_period(apic))
a3e06bbe
LJ		 1476 return 0;
1477
1478 return apic->lapic_timer.tscdeadline;
1479}
1480
1481void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1482{
1483 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1484
c48f1496 1485 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1486 apic_lvtt_period(apic))
a3e06bbe
LJ		 1487 return;
1488
1489 hrtimer_cancel(&apic->lapic_timer.timer);
1490 apic->lapic_timer.tscdeadline = data;
1491 start_apic_timer(apic);
1492}
1493
97222cc8
ED		 1494void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1495{
ad312c7c 1496 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1497
c48f1496 1498 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1499 return;
54e9818f 1500
b93463aa 1501 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1502 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1503}
1504
1505u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1506{
97222cc8
ED		 1507 u64 tpr;
1508
c48f1496 1509 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1510 return 0;
54e9818f 1511
c48f1496 1512 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1513
1514 return (tpr & 0xf0) >> 4;
1515}
1516
1517void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1518{
8d14695f 1519 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1520 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1521
1522 if (!apic) {
1523 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1524 vcpu->arch.apic_base = value;
97222cc8
ED		 1525 return;
1526 }
c5af89b6 1527
e66d2ae7
JK		 1528 vcpu->arch.apic_base = value;
1529
c5cc421b 1530 /* update jump label if enable bit changes */
0dce7cd6 1531 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1532 if (value & MSR_IA32_APICBASE_ENABLE)
1533 static_key_slow_dec_deferred(&apic_hw_disabled);
1534 else
1535 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1536 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1537 }
1538
8d14695f
YZ		 1539 if ((old_value ^ value) & X2APIC_ENABLE) {
1540 if (value & X2APIC_ENABLE) {
1541 u32 id = kvm_apic_id(apic);
1542 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1543 kvm_apic_set_ldr(apic, ldr);
1544 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1545 } else
1546 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1547 }
8d14695f 1548
ad312c7c 1549 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1550 MSR_IA32_APICBASE_BASE;
1551
db324fe6
NA		 1552 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1553 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1554 pr_warn_once("APIC base relocation is unsupported by KVM");
1555
97222cc8
ED		 1556 /* with FSB delivery interrupt, we can restart APIC functionality */
1557 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1558 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1559
1560}
1561
d28bc9dd 1562void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8
ED		 1563{
1564 struct kvm_lapic *apic;
1565 int i;
1566
b8688d51 1567 apic_debug("%s\n", __func__);
97222cc8
ED		 1568
1569 ASSERT(vcpu);
ad312c7c 1570 apic = vcpu->arch.apic;
97222cc8
ED		 1571 ASSERT(apic != NULL);
1572
1573 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1574 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1575
d28bc9dd
NA		 1576 if (!init_event)
1577 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1578 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1579
1580 for (i = 0; i < APIC_LVT_NUM; i++)
1581 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
a323b409 1582 apic->lapic_timer.timer_mode = 0;
90de4a18
NA		 1583 if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_LINT0_REENABLED))
1584 apic_set_reg(apic, APIC_LVT0,
1585 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1586
1587 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1588 apic_set_spiv(apic, 0xff);
97222cc8 1589 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1590 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1591 apic_set_reg(apic, APIC_ESR, 0);
1592 apic_set_reg(apic, APIC_ICR, 0);
1593 apic_set_reg(apic, APIC_ICR2, 0);
1594 apic_set_reg(apic, APIC_TDCR, 0);
1595 apic_set_reg(apic, APIC_TMICT, 0);
1596 for (i = 0; i < 8; i++) {
1597 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1598 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1599 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1600 }
c7c9c56c 1601 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
f563db4b 1602 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
8680b94b 1603 apic->highest_isr_cache = -1;
b33ac88b 1604 update_divide_count(apic);
d3c7b77d 1605 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1606 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1607 kvm_lapic_set_base(vcpu,
1608 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1609 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1610 apic_update_ppr(apic);
1611
e1035715 1612 vcpu->arch.apic_arb_prio = 0;
41383771 1613 vcpu->arch.apic_attention = 0;
e1035715 1614
98eff52a 1615 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1616 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1617 vcpu, kvm_apic_id(apic),
ad312c7c 1618 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1619}
1620
97222cc8
ED		 1621/*
1622 *----------------------------------------------------------------------
1623 * timer interface
1624 *----------------------------------------------------------------------
1625 */
1b9778da 1626
2a6eac96 1627static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1628{
d3c7b77d 1629 return apic_lvtt_period(apic);
97222cc8
ED		 1630}
1631
3d80840d
MT		 1632int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1633{
54e9818f 1634 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1635
c48f1496 1636 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1637 apic_lvt_enabled(apic, APIC_LVTT))
1638 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1639
1640 return 0;
1641}
1642
89342082 1643int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1644{
c48f1496 1645 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1646 int vector, mode, trig_mode;
23930f95 1647
c48f1496 1648 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1649 vector = reg & APIC_VECTOR_MASK;
1650 mode = reg & APIC_MODE_MASK;
1651 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1652 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1653 NULL);
23930f95
JK		 1654 }
1655 return 0;
1656}
1b9778da 1657
8fdb2351 1658void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1659{
8fdb2351
JK		 1660 struct kvm_lapic *apic = vcpu->arch.apic;
1661
1662 if (apic)
1663 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1664}
1665
d76685c4
GH		 1666static const struct kvm_io_device_ops apic_mmio_ops = {
1667 .read = apic_mmio_read,
1668 .write = apic_mmio_write,
d76685c4
GH		 1669};
1670
e9d90d47
AK		 1671static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1672{
1673 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1674 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1675
5d87db71 1676 apic_timer_expired(apic);
e9d90d47 1677
2a6eac96 1678 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1679 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1680 return HRTIMER_RESTART;
1681 } else
1682 return HRTIMER_NORESTART;
1683}
1684
97222cc8
ED		 1685int kvm_create_lapic(struct kvm_vcpu *vcpu)
1686{
1687 struct kvm_lapic *apic;
1688
1689 ASSERT(vcpu != NULL);
1690 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1691
1692 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1693 if (!apic)
1694 goto nomem;
1695
ad312c7c 1696 vcpu->arch.apic = apic;
97222cc8 1697
afc20184
TY		 1698 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1699 if (!apic->regs) {
97222cc8
ED		 1700 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1701 vcpu->vcpu_id);
d589444e 1702 goto nomem_free_apic;
97222cc8 1703 }
97222cc8
ED		 1704 apic->vcpu = vcpu;
1705
d3c7b77d
MT		 1706 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1707 HRTIMER_MODE_ABS);
e9d90d47 1708 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1709
c5cc421b
GN		 1710 /*
1711 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1712 * thinking that APIC satet has changed.
1713 */
1714 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1715 kvm_lapic_set_base(vcpu,
1716 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1717
f8c1ea10 1718 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d28bc9dd 1719 kvm_lapic_reset(vcpu, false);
d76685c4 1720 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1721
1722 return 0;
d589444e
RR		 1723nomem_free_apic:
1724 kfree(apic);
97222cc8 1725nomem:
97222cc8
ED		 1726 return -ENOMEM;
1727}
97222cc8
ED		 1728
1729int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1730{
ad312c7c 1731 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1732 int highest_irr;
1733
c48f1496 1734 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1735 return -1;
1736
6e5d865c 1737 apic_update_ppr(apic);
97222cc8
ED		 1738 highest_irr = apic_find_highest_irr(apic);
1739 if ((highest_irr == -1) ||
c48f1496 1740 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1741 return -1;
1742 return highest_irr;
1743}
1744
40487c68
QH		 1745int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1746{
c48f1496 1747 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1748 int r = 0;
1749
c48f1496 1750 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1751 r = 1;
1752 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1753 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1754 r = 1;
40487c68
QH		 1755 return r;
1756}
1757
1b9778da
ED		 1758void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1759{
ad312c7c 1760 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1761
c48f1496 1762 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1763 return;
1764
1765 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1766 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1767 if (apic_lvtt_tscdeadline(apic))
1768 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1769 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1770 }
1771}
1772
97222cc8
ED		 1773int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1774{
1775 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1776 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1777
1778 if (vector == -1)
1779 return -1;
1780
56cc2406
WL		 1781 /*
1782 * We get here even with APIC virtualization enabled, if doing
1783 * nested virtualization and L1 runs with the "acknowledge interrupt
1784 * on exit" mode. Then we cannot inject the interrupt via RVI,
1785 * because the process would deliver it through the IDT.
1786 */
1787
8680b94b 1788 apic_set_isr(vector, apic);
97222cc8
ED		 1789 apic_update_ppr(apic);
1790 apic_clear_irr(vector, apic);
1791 return vector;
1792}
96ad2cc6 1793
64eb0620
GN		 1794void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1795 struct kvm_lapic_state *s)
96ad2cc6 1796{
ad312c7c 1797 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1798
5dbc8f3f 1799 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1800 /* set SPIV separately to get count of SW disabled APICs right */
1801 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1802 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1803 /* call kvm_apic_set_id() to put apic into apic_map */
1804 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1805 kvm_apic_set_version(vcpu);
1806
96ad2cc6 1807 apic_update_ppr(apic);
d3c7b77d 1808 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1809 update_divide_count(apic);
1810 start_apic_timer(apic);
6e24a6ef 1811 apic->irr_pending = true;
f563db4b 1812 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
c7c9c56c 1813 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1814 apic->highest_isr_cache = -1;
4114c27d
WW		 1815 if (kvm_x86_ops->hwapic_irr_update)
1816 kvm_x86_ops->hwapic_irr_update(vcpu,
1817 apic_find_highest_irr(apic));
b4eef9b3
TC		 1818 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1819 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1820 apic_find_highest_isr(apic));
3842d135 1821 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1822 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1823}
a3d7f85f 1824
2f52d58c 1825void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1826{
a3d7f85f
ED		 1827 struct hrtimer *timer;
1828
c48f1496 1829 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1830 return;
1831
54e9818f 1832 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1833 if (hrtimer_cancel(timer))
beb20d52 1834 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1835}
b93463aa 1836
ae7a2a3f
MT		 1837/*
1838 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1839 *
1840 * Detect whether guest triggered PV EOI since the
1841 * last entry. If yes, set EOI on guests's behalf.
1842 * Clear PV EOI in guest memory in any case.
1843 */
1844static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1845 struct kvm_lapic *apic)
1846{
1847 bool pending;
1848 int vector;
1849 /*
1850 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1851 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1852 *
1853 * KVM_APIC_PV_EOI_PENDING is unset:
1854 * -> host disabled PV EOI.
1855 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1856 * -> host enabled PV EOI, guest did not execute EOI yet.
1857 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1858 * -> host enabled PV EOI, guest executed EOI.
1859 */
1860 BUG_ON(!pv_eoi_enabled(vcpu));
1861 pending = pv_eoi_get_pending(vcpu);
1862 /*
1863 * Clear pending bit in any case: it will be set again on vmentry.
1864 * While this might not be ideal from performance point of view,
1865 * this makes sure pv eoi is only enabled when we know it's safe.
1866 */
1867 pv_eoi_clr_pending(vcpu);
1868 if (pending)
1869 return;
1870 vector = apic_set_eoi(apic);
1871 trace_kvm_pv_eoi(apic, vector);
1872}
1873
b93463aa
AK		 1874void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1875{
1876 u32 data;
b93463aa 1877
ae7a2a3f
MT		 1878 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1879 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1880
41383771 1881 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1882 return;
1883
fda4e2e8
AH		 1884 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1885 sizeof(u32));
b93463aa
AK		 1886
1887 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1888}
1889
ae7a2a3f
MT		 1890/*
1891 * apic_sync_pv_eoi_to_guest - called before vmentry
1892 *
1893 * Detect whether it's safe to enable PV EOI and
1894 * if yes do so.
1895 */
1896static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1897 struct kvm_lapic *apic)
1898{
1899 if (!pv_eoi_enabled(vcpu) ||
1900 /* IRR set or many bits in ISR: could be nested. */
1901 apic->irr_pending ||
1902 /* Cache not set: could be safe but we don't bother. */
1903 apic->highest_isr_cache == -1 ||
1904 /* Need EOI to update ioapic. */
1905 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1906 /*
1907 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1908 * so we need not do anything here.
1909 */
1910 return;
1911 }
1912
1913 pv_eoi_set_pending(apic->vcpu);
1914}
1915
b93463aa
AK		 1916void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1917{
1918 u32 data, tpr;
1919 int max_irr, max_isr;
ae7a2a3f 1920 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1921
ae7a2a3f
MT		 1922 apic_sync_pv_eoi_to_guest(vcpu, apic);
1923
41383771 1924 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1925 return;
1926
c48f1496 1927 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1928 max_irr = apic_find_highest_irr(apic);
1929 if (max_irr < 0)
1930 max_irr = 0;
1931 max_isr = apic_find_highest_isr(apic);
1932 if (max_isr < 0)
1933 max_isr = 0;
1934 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1935
fda4e2e8
AH		 1936 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1937 sizeof(u32));
b93463aa
AK		 1938}
1939
fda4e2e8 1940int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1941{
fda4e2e8
AH		 1942 if (vapic_addr) {
1943 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1944 &vcpu->arch.apic->vapic_cache,
1945 vapic_addr, sizeof(u32)))
1946 return -EINVAL;
41383771 1947 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1948 } else {
41383771 1949 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1950 }
1951
1952 vcpu->arch.apic->vapic_addr = vapic_addr;
1953 return 0;
b93463aa 1954}
0105d1a5
GN		 1955
1956int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1957{
1958 struct kvm_lapic *apic = vcpu->arch.apic;
1959 u32 reg = (msr - APIC_BASE_MSR) << 4;
1960
1961 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1962 return 1;
1963
c69d3d9b
NA		 1964 if (reg == APIC_ICR2)
1965 return 1;
1966
0105d1a5 1967 /* if this is ICR write vector before command */
decdc283 1968 if (reg == APIC_ICR)
0105d1a5
GN		 1969 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1970 return apic_reg_write(apic, reg, (u32)data);
1971}
1972
1973int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1974{
1975 struct kvm_lapic *apic = vcpu->arch.apic;
1976 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1977
1978 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1979 return 1;
1980
c69d3d9b
NA		 1981 if (reg == APIC_DFR || reg == APIC_ICR2) {
1982 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1983 reg);
1984 return 1;
1985 }
1986
0105d1a5
GN		 1987 if (apic_reg_read(apic, reg, 4, &low))
1988 return 1;
decdc283 1989 if (reg == APIC_ICR)
0105d1a5
GN		 1990 apic_reg_read(apic, APIC_ICR2, 4, &high);
1991
1992 *data = (((u64)high) << 32) | low;
1993
1994 return 0;
1995}
10388a07
GN		 1996
1997int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1998{
1999 struct kvm_lapic *apic = vcpu->arch.apic;
2000
c48f1496 2001 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2002 return 1;
2003
2004 /* if this is ICR write vector before command */
2005 if (reg == APIC_ICR)
2006 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2007 return apic_reg_write(apic, reg, (u32)data);
2008}
2009
2010int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2011{
2012 struct kvm_lapic *apic = vcpu->arch.apic;
2013 u32 low, high = 0;
2014
c48f1496 2015 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2016 return 1;
2017
2018 if (apic_reg_read(apic, reg, 4, &low))
2019 return 1;
2020 if (reg == APIC_ICR)
2021 apic_reg_read(apic, APIC_ICR2, 4, &high);
2022
2023 *data = (((u64)high) << 32) | low;
2024
2025 return 0;
2026}
ae7a2a3f
MT		 2027
2028int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2029{
2030 u64 addr = data & ~KVM_MSR_ENABLED;
2031 if (!IS_ALIGNED(addr, 4))
2032 return 1;
2033
2034 vcpu->arch.pv_eoi.msr_val = data;
2035 if (!pv_eoi_enabled(vcpu))
2036 return 0;
2037 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2038 addr, sizeof(u8));
ae7a2a3f 2039}
c5cc421b 2040
66450a21
JK		 2041void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2042{
2043 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2044 u8 sipi_vector;
299018f4 2045 unsigned long pe;
66450a21 2046
299018f4 2047 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2048 return;
2049
299018f4
GN		 2050 pe = xchg(&apic->pending_events, 0);
2051
2052 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd
NA		 2053 kvm_lapic_reset(vcpu, true);
2054 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2055 if (kvm_vcpu_is_bsp(apic->vcpu))
2056 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2057 else
2058 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2059 }
299018f4 2060 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2061 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2062 /* evaluate pending_events before reading the vector */
2063 smp_rmb();
2064 sipi_vector = apic->sipi_vector;
98eff52a 2065 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2066 vcpu->vcpu_id, sipi_vector);
2067 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2069 }
2070}
2071
c5cc421b
GN		 2072void kvm_lapic_init(void)
2073{
2074 /* do not patch jump label more than once per second */
2075 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2076 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2077}
Linux kernel - Deliverables
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