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KVM: x86: use correct APIC ID on x2APIC transition
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
3548a259
RK		 136/* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
3b5a5ffa
RK		 144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
1e08ec4a
GN		 158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
173beedc
NA		 171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
25995e5b 174 u32 ldr, aid;
1e08ec4a 175
df04d1d1
RK		 176 if (!kvm_apic_present(vcpu))
177 continue;
178
25995e5b 179 aid = kvm_apic_id(apic);
1e08ec4a 180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
1e08ec4a 181
25995e5b
RK		 182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
3548a259 184
3b5a5ffa
RK		 185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
3548a259
RK		 196 continue;
197
3b5a5ffa
RK		 198 apic_logical_id(new, ldr, &cid, &lid);
199
25995e5b 200 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
c7c9c56c 211
3d81bc7e 212 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 213}
214
1e1b6c26
NA		 215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
e462755c 217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 218
219 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
1e1b6c26
NA		 224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
1e08ec4a
GN		 231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
257b9a5f
RK		 243static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
244{
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
246
247 apic_set_reg(apic, APIC_ID, id << 24);
248 apic_set_reg(apic, APIC_LDR, ldr);
249 recalculate_apic_map(apic->vcpu->kvm);
250}
251
97222cc8
ED		 252static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
253{
c48f1496 254 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 255}
256
257static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
258{
c48f1496 259 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 260}
261
a3e06bbe
LJ		 262static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
263{
f30ebc31 264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 265}
266
97222cc8
ED		 267static inline int apic_lvtt_period(struct kvm_lapic *apic)
268{
f30ebc31 269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 270}
271
272static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
273{
f30ebc31 274 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 275}
276
cc6e462c
JK		 277static inline int apic_lvt_nmi_mode(u32 lvt_val)
278{
279 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
280}
281
fc61b800
GN		 282void kvm_apic_set_version(struct kvm_vcpu *vcpu)
283{
284 struct kvm_lapic *apic = vcpu->arch.apic;
285 struct kvm_cpuid_entry2 *feat;
286 u32 v = APIC_VERSION;
287
c48f1496 288 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 289 return;
290
291 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293 v |= APIC_LVR_DIRECTED_EOI;
294 apic_set_reg(apic, APIC_LVR, v);
295}
296
f1d24831 297static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 298 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 299 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
300 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
301 LINT_MASK, LINT_MASK, /* LVT0-1 */
302 LVT_MASK /* LVTERR */
303};
304
305static int find_highest_vector(void *bitmap)
306{
ecba9a52
TY		 307 int vec;
308 u32 *reg;
97222cc8 309
ecba9a52
TY		 310 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
313 if (*reg)
314 return fls(*reg) - 1 + vec;
315 }
97222cc8 316
ecba9a52 317 return -1;
97222cc8
ED		 318}
319
8680b94b
MT		 320static u8 count_vectors(void *bitmap)
321{
ecba9a52
TY		 322 int vec;
323 u32 *reg;
8680b94b 324 u8 count = 0;
ecba9a52
TY		 325
326 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327 reg = bitmap + REG_POS(vec);
328 count += hweight32(*reg);
329 }
330
8680b94b
MT		 331 return count;
332}
333
705699a1 334void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 335{
336 u32 i, pir_val;
a20ed54d
YZ		 337
338 for (i = 0; i <= 7; i++) {
339 pir_val = xchg(&pir[i], 0);
340 if (pir_val)
705699a1 341 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 342 }
343}
705699a1
WV		 344EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
345
346void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
347{
348 struct kvm_lapic *apic = vcpu->arch.apic;
349
350 __kvm_apic_update_irr(pir, apic->regs);
351}
a20ed54d
YZ		 352EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
353
11f5cc05 354static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 355{
11f5cc05 356 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 357 /*
358 * irr_pending must be true if any interrupt is pending; set it after
359 * APIC_IRR to avoid race with apic_clear_irr
360 */
361 apic->irr_pending = true;
97222cc8
ED		 362}
363
33e4c686 364static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 365{
33e4c686 366 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 367}
368
369static inline int apic_find_highest_irr(struct kvm_lapic *apic)
370{
371 int result;
372
c7c9c56c
YZ		 373 /*
374 * Note that irr_pending is just a hint. It will be always
375 * true with virtual interrupt delivery enabled.
376 */
33e4c686
GN		 377 if (!apic->irr_pending)
378 return -1;
379
5a71785d 380 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 381 result = apic_search_irr(apic);
97222cc8
ED		 382 ASSERT(result == -1 || result >= 16);
383
384 return result;
385}
386
33e4c686
GN		 387static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
388{
56cc2406
WL		 389 struct kvm_vcpu *vcpu;
390
391 vcpu = apic->vcpu;
392
f210f757 393 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 394 /* try to update RVI */
f210f757 395 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 396 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 397 } else {
398 apic->irr_pending = false;
399 apic_clear_vector(vec, apic->regs + APIC_IRR);
400 if (apic_search_irr(apic) != -1)
401 apic->irr_pending = true;
56cc2406 402 }
33e4c686
GN		 403}
404
8680b94b
MT		 405static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
406{
56cc2406
WL		 407 struct kvm_vcpu *vcpu;
408
409 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
410 return;
411
412 vcpu = apic->vcpu;
fc57ac2c 413
8680b94b 414 /*
56cc2406
WL		 415 * With APIC virtualization enabled, all caching is disabled
416 * because the processor can modify ISR under the hood. Instead
417 * just set SVI.
8680b94b 418 */
b4eef9b3 419 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 420 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
421 else {
422 ++apic->isr_count;
423 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
424 /*
425 * ISR (in service register) bit is set when injecting an interrupt.
426 * The highest vector is injected. Thus the latest bit set matches
427 * the highest bit in ISR.
428 */
429 apic->highest_isr_cache = vec;
430 }
8680b94b
MT		 431}
432
fc57ac2c
PB		 433static inline int apic_find_highest_isr(struct kvm_lapic *apic)
434{
435 int result;
436
437 /*
438 * Note that isr_count is always 1, and highest_isr_cache
439 * is always -1, with APIC virtualization enabled.
440 */
441 if (!apic->isr_count)
442 return -1;
443 if (likely(apic->highest_isr_cache != -1))
444 return apic->highest_isr_cache;
445
446 result = find_highest_vector(apic->regs + APIC_ISR);
447 ASSERT(result == -1 || result >= 16);
448
449 return result;
450}
451
8680b94b
MT		 452static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
453{
fc57ac2c
PB		 454 struct kvm_vcpu *vcpu;
455 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
456 return;
457
458 vcpu = apic->vcpu;
459
460 /*
461 * We do get here for APIC virtualization enabled if the guest
462 * uses the Hyper-V APIC enlightenment. In this case we may need
463 * to trigger a new interrupt delivery by writing the SVI field;
464 * on the other hand isr_count and highest_isr_cache are unused
465 * and must be left alone.
466 */
b4eef9b3 467 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 468 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
469 apic_find_highest_isr(apic));
470 else {
8680b94b 471 --apic->isr_count;
fc57ac2c
PB		 472 BUG_ON(apic->isr_count < 0);
473 apic->highest_isr_cache = -1;
474 }
8680b94b
MT		 475}
476
6e5d865c
YS		 477int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
478{
6e5d865c
YS		 479 int highest_irr;
480
33e4c686
GN		 481 /* This may race with setting of irr in __apic_accept_irq() and
482 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
483 * will cause vmexit immediately and the value will be recalculated
484 * on the next vmentry.
485 */
c48f1496 486 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 487 return 0;
54e9818f 488 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 489
490 return highest_irr;
491}
6e5d865c 492
6da7e3f6 493static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 494 int vector, int level, int trig_mode,
495 unsigned long *dest_map);
6da7e3f6 496
b4f2225c
YZ		 497int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
498 unsigned long *dest_map)
97222cc8 499{
ad312c7c 500 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 501
58c2dde1 502 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 503 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 504}
505
ae7a2a3f
MT		 506static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
507{
508
509 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
510 sizeof(val));
511}
512
513static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
514{
515
516 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
517 sizeof(*val));
518}
519
520static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
521{
522 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
523}
524
525static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
526{
527 u8 val;
528 if (pv_eoi_get_user(vcpu, &val) < 0)
529 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 530 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 531 return val & 0x1;
532}
533
534static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
535{
536 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
537 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 538 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 539 return;
540 }
541 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
542}
543
544static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
545{
546 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
547 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 548 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 549 return;
550 }
551 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
552}
553
cf9e65b7
YZ		 554void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
555{
556 struct kvm_lapic *apic = vcpu->arch.apic;
557 int i;
558
559 for (i = 0; i < 8; i++)
560 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
561}
562
97222cc8
ED		 563static void apic_update_ppr(struct kvm_lapic *apic)
564{
3842d135 565 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 566 int isr;
567
c48f1496
GN		 568 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
569 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 570 isr = apic_find_highest_isr(apic);
571 isrv = (isr != -1) ? isr : 0;
572
573 if ((tpr & 0xf0) >= (isrv & 0xf0))
574 ppr = tpr & 0xff;
575 else
576 ppr = isrv & 0xf0;
577
578 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
579 apic, ppr, isr, isrv);
580
3842d135
AK		 581 if (old_ppr != ppr) {
582 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 583 if (ppr < old_ppr)
584 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 585 }
97222cc8
ED		 586}
587
588static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
589{
590 apic_set_reg(apic, APIC_TASKPRI, tpr);
591 apic_update_ppr(apic);
592}
593
03d2249e 594static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 595{
03d2249e
RK		 596 if (apic_x2apic_mode(apic))
597 return mda == X2APIC_BROADCAST;
598
599 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 600}
601
03d2249e 602static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 603{
03d2249e
RK		 604 if (kvm_apic_broadcast(apic, mda))
605 return true;
606
607 if (apic_x2apic_mode(apic))
608 return mda == kvm_apic_id(apic);
609
610 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 611}
612
52c233a4 613static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 614{
0105d1a5
GN		 615 u32 logical_id;
616
394457a9 617 if (kvm_apic_broadcast(apic, mda))
9368b567 618 return true;
394457a9 619
9368b567 620 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 621
9368b567 622 if (apic_x2apic_mode(apic))
8a395363
RK		 623 return ((logical_id >> 16) == (mda >> 16))
624 && (logical_id & mda & 0xffff) != 0;
97222cc8 625
9368b567 626 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 627 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 628
c48f1496 629 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 630 case APIC_DFR_FLAT:
9368b567 631 return (logical_id & mda) != 0;
97222cc8 632 case APIC_DFR_CLUSTER:
9368b567
RK		 633 return ((logical_id >> 4) == (mda >> 4))
634 && (logical_id & mda & 0xf) != 0;
97222cc8 635 default:
7712de87 636 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 637 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 638 return false;
97222cc8 639 }
97222cc8
ED		 640}
641
03d2249e
RK		 642/* KVM APIC implementation has two quirks
643 * - dest always begins at 0 while xAPIC MDA has offset 24,
644 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
645 */
646static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
647 struct kvm_lapic *target)
648{
649 bool ipi = source != NULL;
650 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
651
652 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
653 return X2APIC_BROADCAST;
654
655 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
656}
657
52c233a4 658bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 659 int short_hand, unsigned int dest, int dest_mode)
97222cc8 660{
ad312c7c 661 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 662 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 663
664 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 665 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 666 target, source, dest, dest_mode, short_hand);
667
bd371396 668 ASSERT(target);
97222cc8
ED		 669 switch (short_hand) {
670 case APIC_DEST_NOSHORT:
3697f302 671 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 672 return kvm_apic_match_physical_addr(target, mda);
343f94fe 673 else
03d2249e 674 return kvm_apic_match_logical_addr(target, mda);
97222cc8 675 case APIC_DEST_SELF:
9368b567 676 return target == source;
97222cc8 677 case APIC_DEST_ALLINC:
9368b567 678 return true;
97222cc8 679 case APIC_DEST_ALLBUT:
9368b567 680 return target != source;
97222cc8 681 default:
7712de87
JK		 682 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
683 short_hand);
9368b567 684 return false;
97222cc8 685 }
97222cc8
ED		 686}
687
1e08ec4a 688bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 689 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 690{
691 struct kvm_apic_map *map;
692 unsigned long bitmap = 1;
693 struct kvm_lapic **dst;
694 int i;
bea15428 695 bool ret, x2apic_ipi;
1e08ec4a
GN		 696
697 *r = -1;
698
699 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 700 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 701 return true;
702 }
703
704 if (irq->shorthand)
705 return false;
706
bea15428 707 x2apic_ipi = src && apic_x2apic_mode(src);
9ea369b0
RK		 708 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
709 return false;
710
bea15428 711 ret = true;
1e08ec4a
GN		 712 rcu_read_lock();
713 map = rcu_dereference(kvm->arch.apic_map);
714
bea15428
PB		 715 if (!map) {
716 ret = false;
1e08ec4a 717 goto out;
bea15428 718 }
698f9755 719
3697f302 720 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 721 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
722 goto out;
723
724 dst = &map->phys_map[irq->dest_id];
1e08ec4a 725 } else {
3548a259
RK		 726 u16 cid;
727
728 if (!kvm_apic_logical_map_valid(map)) {
729 ret = false;
730 goto out;
731 }
732
3b5a5ffa 733 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
45c3094a
RK		 734
735 if (cid >= ARRAY_SIZE(map->logical_map))
736 goto out;
1e08ec4a 737
45c3094a 738 dst = map->logical_map[cid];
1e08ec4a 739
d1ebdbf9 740 if (kvm_lowest_prio_delivery(irq)) {
1e08ec4a
GN		 741 int l = -1;
742 for_each_set_bit(i, &bitmap, 16) {
743 if (!dst[i])
744 continue;
745 if (l < 0)
746 l = i;
747 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
748 l = i;
749 }
750
751 bitmap = (l >= 0) ? 1 << l : 0;
752 }
753 }
754
755 for_each_set_bit(i, &bitmap, 16) {
756 if (!dst[i])
757 continue;
758 if (*r < 0)
759 *r = 0;
b4f2225c 760 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 761 }
1e08ec4a
GN		 762out:
763 rcu_read_unlock();
764 return ret;
765}
766
97222cc8
ED		 767/*
768 * Add a pending IRQ into lapic.
769 * Return 1 if successfully added and 0 if discarded.
770 */
771static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 772 int vector, int level, int trig_mode,
773 unsigned long *dest_map)
97222cc8 774{
6da7e3f6 775 int result = 0;
c5ec1534 776 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 777
a183b638
PB		 778 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
779 trig_mode, vector);
97222cc8 780 switch (delivery_mode) {
97222cc8 781 case APIC_DM_LOWEST:
e1035715
GN		 782 vcpu->arch.apic_arb_prio++;
783 case APIC_DM_FIXED:
97222cc8
ED		 784 /* FIXME add logic for vcpu on reset */
785 if (unlikely(!apic_enabled(apic)))
786 break;
787
11f5cc05
JK		 788 result = 1;
789
b4f2225c
YZ		 790 if (dest_map)
791 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 792
11f5cc05 793 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 794 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 795 else {
796 apic_set_irr(vector, apic);
5a71785d
YZ		 797
798 kvm_make_request(KVM_REQ_EVENT, vcpu);
799 kvm_vcpu_kick(vcpu);
800 }
97222cc8
ED		 801 break;
802
803 case APIC_DM_REMRD:
24d2166b
R		 804 result = 1;
805 vcpu->arch.pv.pv_unhalted = 1;
806 kvm_make_request(KVM_REQ_EVENT, vcpu);
807 kvm_vcpu_kick(vcpu);
97222cc8
ED		 808 break;
809
810 case APIC_DM_SMI:
7712de87 811 apic_debug("Ignoring guest SMI\n");
97222cc8 812 break;
3419ffc8 813
97222cc8 814 case APIC_DM_NMI:
6da7e3f6 815 result = 1;
3419ffc8 816 kvm_inject_nmi(vcpu);
26df99c6 817 kvm_vcpu_kick(vcpu);
97222cc8
ED		 818 break;
819
820 case APIC_DM_INIT:
a52315e1 821 if (!trig_mode || level) {
6da7e3f6 822 result = 1;
66450a21
JK		 823 /* assumes that there are only KVM_APIC_INIT/SIPI */
824 apic->pending_events = (1UL << KVM_APIC_INIT);
825 /* make sure pending_events is visible before sending
826 * the request */
827 smp_wmb();
3842d135 828 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 829 kvm_vcpu_kick(vcpu);
830 } else {
1b10bf31
JK		 831 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
832 vcpu->vcpu_id);
c5ec1534 833 }
97222cc8
ED		 834 break;
835
836 case APIC_DM_STARTUP:
1b10bf31
JK		 837 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
838 vcpu->vcpu_id, vector);
66450a21
JK		 839 result = 1;
840 apic->sipi_vector = vector;
841 /* make sure sipi_vector is visible for the receiver */
842 smp_wmb();
843 set_bit(KVM_APIC_SIPI, &apic->pending_events);
844 kvm_make_request(KVM_REQ_EVENT, vcpu);
845 kvm_vcpu_kick(vcpu);
97222cc8
ED		 846 break;
847
23930f95
JK		 848 case APIC_DM_EXTINT:
849 /*
850 * Should only be called by kvm_apic_local_deliver() with LVT0,
851 * before NMI watchdog was enabled. Already handled by
852 * kvm_apic_accept_pic_intr().
853 */
854 break;
855
97222cc8
ED		 856 default:
857 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
858 delivery_mode);
859 break;
860 }
861 return result;
862}
863
e1035715 864int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 865{
e1035715 866 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 867}
868
c7c9c56c
YZ		 869static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
870{
c806a6ad 871 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
c7c9c56c
YZ		 872 int trigger_mode;
873 if (apic_test_vector(vector, apic->regs + APIC_TMR))
874 trigger_mode = IOAPIC_LEVEL_TRIG;
875 else
876 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 877 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 878 }
879}
880
ae7a2a3f 881static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 882{
883 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 884
885 trace_kvm_eoi(apic, vector);
886
97222cc8
ED		 887 /*
888 * Not every write EOI will has corresponding ISR,
889 * one example is when Kernel check timer on setup_IO_APIC
890 */
891 if (vector == -1)
ae7a2a3f 892 return vector;
97222cc8 893
8680b94b 894 apic_clear_isr(vector, apic);
97222cc8
ED		 895 apic_update_ppr(apic);
896
c7c9c56c 897 kvm_ioapic_send_eoi(apic, vector);
3842d135 898 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 899 return vector;
97222cc8
ED		 900}
901
c7c9c56c
YZ		 902/*
903 * this interface assumes a trap-like exit, which has already finished
904 * desired side effect including vISR and vPPR update.
905 */
906void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
907{
908 struct kvm_lapic *apic = vcpu->arch.apic;
909
910 trace_kvm_eoi(apic, vector);
911
912 kvm_ioapic_send_eoi(apic, vector);
913 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
914}
915EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
916
97222cc8
ED		 917static void apic_send_ipi(struct kvm_lapic *apic)
918{
c48f1496
GN		 919 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
920 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 921 struct kvm_lapic_irq irq;
97222cc8 922
58c2dde1
GN		 923 irq.vector = icr_low & APIC_VECTOR_MASK;
924 irq.delivery_mode = icr_low & APIC_MODE_MASK;
925 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 926 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 927 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
928 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 929 irq.msi_redir_hint = false;
0105d1a5
GN		 930 if (apic_x2apic_mode(apic))
931 irq.dest_id = icr_high;
932 else
933 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 934
1000ff8d
GN		 935 trace_kvm_apic_ipi(icr_low, irq.dest_id);
936
97222cc8
ED		 937 apic_debug("icr_high 0x%x, icr_low 0x%x, "
938 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 939 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
940 "msi_redir_hint 0x%x\n",
9b5843dd 941 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 942 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 943 irq.vector, irq.msi_redir_hint);
58c2dde1 944
b4f2225c 945 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 946}
947
948static u32 apic_get_tmcct(struct kvm_lapic *apic)
949{
b682b814
MT		 950 ktime_t remaining;
951 s64 ns;
9da8f4e8 952 u32 tmcct;
97222cc8
ED		 953
954 ASSERT(apic != NULL);
955
9da8f4e8 956 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 957 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
958 apic->lapic_timer.period == 0)
9da8f4e8
KP		 959 return 0;
960
ace15464 961 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 962 if (ktime_to_ns(remaining) < 0)
963 remaining = ktime_set(0, 0);
964
d3c7b77d
MT		 965 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
966 tmcct = div64_u64(ns,
967 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 968
969 return tmcct;
970}
971
b209749f
AK		 972static void __report_tpr_access(struct kvm_lapic *apic, bool write)
973{
974 struct kvm_vcpu *vcpu = apic->vcpu;
975 struct kvm_run *run = vcpu->run;
976
a8eeb04a 977 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 978 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 979 run->tpr_access.is_write = write;
980}
981
982static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
983{
984 if (apic->vcpu->arch.tpr_access_reporting)
985 __report_tpr_access(apic, write);
986}
987
97222cc8
ED		 988static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
989{
990 u32 val = 0;
991
992 if (offset >= LAPIC_MMIO_LENGTH)
993 return 0;
994
995 switch (offset) {
0105d1a5
GN		 996 case APIC_ID:
997 if (apic_x2apic_mode(apic))
998 val = kvm_apic_id(apic);
999 else
1000 val = kvm_apic_id(apic) << 24;
1001 break;
97222cc8 1002 case APIC_ARBPRI:
7712de87 1003 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 1004 break;
1005
1006 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1007 if (apic_lvtt_tscdeadline(apic))
1008 return 0;
1009
97222cc8
ED		 1010 val = apic_get_tmcct(apic);
1011 break;
4a4541a4
AK		 1012 case APIC_PROCPRI:
1013 apic_update_ppr(apic);
c48f1496 1014 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1015 break;
b209749f
AK		 1016 case APIC_TASKPRI:
1017 report_tpr_access(apic, false);
1018 /* fall thru */
97222cc8 1019 default:
c48f1496 1020 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1021 break;
1022 }
1023
1024 return val;
1025}
1026
d76685c4
GH		 1027static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1028{
1029 return container_of(dev, struct kvm_lapic, dev);
1030}
1031
0105d1a5
GN		 1032static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1033 void *data)
97222cc8 1034{
97222cc8
ED		 1035 unsigned char alignment = offset & 0xf;
1036 u32 result;
d5b0b5b1 1037 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1038 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1039
1040 if ((alignment + len) > 4) {
4088bb3c
GN		 1041 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1042 offset, len);
0105d1a5 1043 return 1;
97222cc8 1044 }
0105d1a5
GN		 1045
1046 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1047 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1048 offset);
0105d1a5
GN		 1049 return 1;
1050 }
1051
97222cc8
ED		 1052 result = __apic_read(apic, offset & ~0xf);
1053
229456fc
MT		 1054 trace_kvm_apic_read(offset, result);
1055
97222cc8
ED		 1056 switch (len) {
1057 case 1:
1058 case 2:
1059 case 4:
1060 memcpy(data, (char *)&result + alignment, len);
1061 break;
1062 default:
1063 printk(KERN_ERR "Local APIC read with len = %x, "
1064 "should be 1,2, or 4 instead\n", len);
1065 break;
1066 }
bda9020e 1067 return 0;
97222cc8
ED		 1068}
1069
0105d1a5
GN		 1070static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1071{
c48f1496 1072 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1073 addr >= apic->base_address &&
1074 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1075}
1076
e32edf4f 1077static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1078 gpa_t address, int len, void *data)
1079{
1080 struct kvm_lapic *apic = to_lapic(this);
1081 u32 offset = address - apic->base_address;
1082
1083 if (!apic_mmio_in_range(apic, address))
1084 return -EOPNOTSUPP;
1085
1086 apic_reg_read(apic, offset, len, data);
1087
1088 return 0;
1089}
1090
97222cc8
ED		 1091static void update_divide_count(struct kvm_lapic *apic)
1092{
1093 u32 tmp1, tmp2, tdcr;
1094
c48f1496 1095 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1096 tmp1 = tdcr & 0xf;
1097 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1098 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1099
1100 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1101 apic->divide_count);
97222cc8
ED		 1102}
1103
5d87db71
RK		 1104static void apic_timer_expired(struct kvm_lapic *apic)
1105{
1106 struct kvm_vcpu *vcpu = apic->vcpu;
1107 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1108 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1109
5d87db71
RK		 1110 if (atomic_read(&apic->lapic_timer.pending))
1111 return;
1112
1113 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1114 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1115
1116 if (waitqueue_active(q))
1117 wake_up_interruptible(q);
d0659d94
MT		 1118
1119 if (apic_lvtt_tscdeadline(apic))
1120 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1121}
1122
1123/*
1124 * On APICv, this test will cause a busy wait
1125 * during a higher-priority task.
1126 */
1127
1128static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1129{
1130 struct kvm_lapic *apic = vcpu->arch.apic;
1131 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1132
1133 if (kvm_apic_hw_enabled(apic)) {
1134 int vec = reg & APIC_VECTOR_MASK;
f9339860 1135 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1136
f9339860
MT		 1137 if (kvm_x86_ops->deliver_posted_interrupt)
1138 bitmap = apic->regs + APIC_IRR;
1139
1140 if (apic_test_vector(vec, bitmap))
1141 return true;
d0659d94
MT		 1142 }
1143 return false;
1144}
1145
1146void wait_lapic_expire(struct kvm_vcpu *vcpu)
1147{
1148 struct kvm_lapic *apic = vcpu->arch.apic;
1149 u64 guest_tsc, tsc_deadline;
1150
1151 if (!kvm_vcpu_has_lapic(vcpu))
1152 return;
1153
1154 if (apic->lapic_timer.expired_tscdeadline == 0)
1155 return;
1156
1157 if (!lapic_timer_int_injected(vcpu))
1158 return;
1159
1160 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1161 apic->lapic_timer.expired_tscdeadline = 0;
1162 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
6c19b753 1163 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1164
1165 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1166 if (guest_tsc < tsc_deadline)
1167 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1168}
1169
97222cc8
ED		 1170static void start_apic_timer(struct kvm_lapic *apic)
1171{
a3e06bbe 1172 ktime_t now;
d0659d94 1173
d3c7b77d 1174 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1175
a3e06bbe 1176 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1177 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1178 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1179 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1180 * APIC_BUS_CYCLE_NS * apic->divide_count;
1181
1182 if (!apic->lapic_timer.period)
1183 return;
1184 /*
1185 * Do not allow the guest to program periodic timers with small
1186 * interval, since the hrtimers are not throttled by the host
1187 * scheduler.
1188 */
1189 if (apic_lvtt_period(apic)) {
1190 s64 min_period = min_timer_period_us * 1000LL;
1191
1192 if (apic->lapic_timer.period < min_period) {
1193 pr_info_ratelimited(
1194 "kvm: vcpu %i: requested %lld ns "
1195 "lapic timer period limited to %lld ns\n",
1196 apic->vcpu->vcpu_id,
1197 apic->lapic_timer.period, min_period);
1198 apic->lapic_timer.period = min_period;
1199 }
9bc5791d 1200 }
0b975a3c 1201
a3e06bbe
LJ		 1202 hrtimer_start(&apic->lapic_timer.timer,
1203 ktime_add_ns(now, apic->lapic_timer.period),
1204 HRTIMER_MODE_ABS);
97222cc8 1205
a3e06bbe 1206 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1207 PRIx64 ", "
1208 "timer initial count 0x%x, period %lldns, "
b8688d51 1209 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1210 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1211 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1212 apic->lapic_timer.period,
97222cc8 1213 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1214 apic->lapic_timer.period)));
a3e06bbe
LJ		 1215 } else if (apic_lvtt_tscdeadline(apic)) {
1216 /* lapic timer in tsc deadline mode */
1217 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1218 u64 ns = 0;
d0659d94 1219 ktime_t expire;
a3e06bbe 1220 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1221 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1222 unsigned long flags;
1223
1224 if (unlikely(!tscdeadline || !this_tsc_khz))
1225 return;
1226
1227 local_irq_save(flags);
1228
1229 now = apic->lapic_timer.timer.base->get_time();
886b470c 1230 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1231 if (likely(tscdeadline > guest_tsc)) {
1232 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1233 do_div(ns, this_tsc_khz);
d0659d94
MT		 1234 expire = ktime_add_ns(now, ns);
1235 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1236 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1237 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1238 } else
1239 apic_timer_expired(apic);
a3e06bbe
LJ		 1240
1241 local_irq_restore(flags);
1242 }
97222cc8
ED		 1243}
1244
cc6e462c
JK		 1245static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1246{
c48f1496 1247 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1248
1249 if (apic_lvt_nmi_mode(lvt0_val)) {
1250 if (!nmi_wd_enabled) {
1251 apic_debug("Receive NMI setting on APIC_LVT0 "
1252 "for cpu %d\n", apic->vcpu->vcpu_id);
1253 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1254 }
1255 } else if (nmi_wd_enabled)
1256 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1257}
1258
0105d1a5 1259static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1260{
0105d1a5 1261 int ret = 0;
97222cc8 1262
0105d1a5 1263 trace_kvm_apic_write(reg, val);
97222cc8 1264
0105d1a5 1265 switch (reg) {
97222cc8 1266 case APIC_ID: /* Local APIC ID */
0105d1a5 1267 if (!apic_x2apic_mode(apic))
1e08ec4a 1268 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1269 else
1270 ret = 1;
97222cc8
ED		 1271 break;
1272
1273 case APIC_TASKPRI:
b209749f 1274 report_tpr_access(apic, true);
97222cc8
ED		 1275 apic_set_tpr(apic, val & 0xff);
1276 break;
1277
1278 case APIC_EOI:
1279 apic_set_eoi(apic);
1280 break;
1281
1282 case APIC_LDR:
0105d1a5 1283 if (!apic_x2apic_mode(apic))
1e08ec4a 1284 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1285 else
1286 ret = 1;
97222cc8
ED		 1287 break;
1288
1289 case APIC_DFR:
1e08ec4a 1290 if (!apic_x2apic_mode(apic)) {
0105d1a5 1291 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1292 recalculate_apic_map(apic->vcpu->kvm);
1293 } else
0105d1a5 1294 ret = 1;
97222cc8
ED		 1295 break;
1296
fc61b800
GN		 1297 case APIC_SPIV: {
1298 u32 mask = 0x3ff;
c48f1496 1299 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1300 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1301 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1302 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1303 int i;
1304 u32 lvt_val;
1305
1306 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1307 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1308 APIC_LVTT + 0x10 * i);
1309 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1310 lvt_val | APIC_LVT_MASKED);
1311 }
d3c7b77d 1312 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1313
1314 }
1315 break;
fc61b800 1316 }
97222cc8
ED		 1317 case APIC_ICR:
1318 /* No delay here, so we always clear the pending bit */
1319 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1320 apic_send_ipi(apic);
1321 break;
1322
1323 case APIC_ICR2:
0105d1a5
GN		 1324 if (!apic_x2apic_mode(apic))
1325 val &= 0xff000000;
1326 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1327 break;
1328
23930f95 1329 case APIC_LVT0:
cc6e462c 1330 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1331 case APIC_LVTTHMR:
1332 case APIC_LVTPC:
97222cc8
ED		 1333 case APIC_LVT1:
1334 case APIC_LVTERR:
1335 /* TODO: Check vector */
c48f1496 1336 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1337 val |= APIC_LVT_MASKED;
1338
0105d1a5
GN		 1339 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1340 apic_set_reg(apic, reg, val);
97222cc8
ED		 1341
1342 break;
1343
a323b409
RK		 1344 case APIC_LVTT: {
1345 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1346
1347 if (apic->lapic_timer.timer_mode != timer_mode) {
1348 apic->lapic_timer.timer_mode = timer_mode;
a3e06bbe 1349 hrtimer_cancel(&apic->lapic_timer.timer);
a323b409 1350 }
a3e06bbe 1351
c48f1496 1352 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1353 val |= APIC_LVT_MASKED;
1354 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1355 apic_set_reg(apic, APIC_LVTT, val);
1356 break;
a323b409 1357 }
a3e06bbe 1358
97222cc8 1359 case APIC_TMICT:
a3e06bbe
LJ		 1360 if (apic_lvtt_tscdeadline(apic))
1361 break;
1362
d3c7b77d 1363 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1364 apic_set_reg(apic, APIC_TMICT, val);
1365 start_apic_timer(apic);
0105d1a5 1366 break;
97222cc8
ED		 1367
1368 case APIC_TDCR:
1369 if (val & 4)
7712de87 1370 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1371 apic_set_reg(apic, APIC_TDCR, val);
1372 update_divide_count(apic);
1373 break;
1374
0105d1a5
GN		 1375 case APIC_ESR:
1376 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1377 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1378 ret = 1;
1379 }
1380 break;
1381
1382 case APIC_SELF_IPI:
1383 if (apic_x2apic_mode(apic)) {
1384 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1385 } else
1386 ret = 1;
1387 break;
97222cc8 1388 default:
0105d1a5 1389 ret = 1;
97222cc8
ED		 1390 break;
1391 }
0105d1a5
GN		 1392 if (ret)
1393 apic_debug("Local APIC Write to read-only register %x\n", reg);
1394 return ret;
1395}
1396
e32edf4f 1397static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1398 gpa_t address, int len, const void *data)
1399{
1400 struct kvm_lapic *apic = to_lapic(this);
1401 unsigned int offset = address - apic->base_address;
1402 u32 val;
1403
1404 if (!apic_mmio_in_range(apic, address))
1405 return -EOPNOTSUPP;
1406
1407 /*
1408 * APIC register must be aligned on 128-bits boundary.
1409 * 32/64/128 bits registers must be accessed thru 32 bits.
1410 * Refer SDM 8.4.1
1411 */
1412 if (len != 4 || (offset & 0xf)) {
1413 /* Don't shout loud, $infamous_os would cause only noise. */
1414 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1415 return 0;
0105d1a5
GN		 1416 }
1417
1418 val = *(u32*)data;
1419
1420 /* too common printing */
1421 if (offset != APIC_EOI)
1422 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1423 "0x%x\n", __func__, offset, len, val);
1424
1425 apic_reg_write(apic, offset & 0xff0, val);
1426
bda9020e 1427 return 0;
97222cc8
ED		 1428}
1429
58fbbf26
KT		 1430void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1431{
c48f1496 1432 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1433 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1434}
1435EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1436
83d4c286
YZ		 1437/* emulate APIC access in a trap manner */
1438void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1439{
1440 u32 val = 0;
1441
1442 /* hw has done the conditional check and inst decode */
1443 offset &= 0xff0;
1444
1445 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1446
1447 /* TODO: optimize to just emulate side effect w/o one more write */
1448 apic_reg_write(vcpu->arch.apic, offset, val);
1449}
1450EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1451
d589444e 1452void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1453{
f8c1ea10
GN		 1454 struct kvm_lapic *apic = vcpu->arch.apic;
1455
ad312c7c 1456 if (!vcpu->arch.apic)
97222cc8
ED		 1457 return;
1458
f8c1ea10 1459 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1460
c5cc421b
GN		 1461 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1462 static_key_slow_dec_deferred(&apic_hw_disabled);
1463
e462755c 1464 if (!apic->sw_enabled)
f8c1ea10 1465 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1466
f8c1ea10
GN		 1467 if (apic->regs)
1468 free_page((unsigned long)apic->regs);
1469
1470 kfree(apic);
97222cc8
ED		 1471}
1472
1473/*
1474 *----------------------------------------------------------------------
1475 * LAPIC interface
1476 *----------------------------------------------------------------------
1477 */
1478
a3e06bbe
LJ		 1479u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1480{
1481 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1482
c48f1496 1483 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1484 apic_lvtt_period(apic))
a3e06bbe
LJ		 1485 return 0;
1486
1487 return apic->lapic_timer.tscdeadline;
1488}
1489
1490void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1491{
1492 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1493
c48f1496 1494 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1495 apic_lvtt_period(apic))
a3e06bbe
LJ		 1496 return;
1497
1498 hrtimer_cancel(&apic->lapic_timer.timer);
1499 apic->lapic_timer.tscdeadline = data;
1500 start_apic_timer(apic);
1501}
1502
97222cc8
ED		 1503void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1504{
ad312c7c 1505 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1506
c48f1496 1507 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1508 return;
54e9818f 1509
b93463aa 1510 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1511 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1512}
1513
1514u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1515{
97222cc8
ED		 1516 u64 tpr;
1517
c48f1496 1518 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1519 return 0;
54e9818f 1520
c48f1496 1521 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1522
1523 return (tpr & 0xf0) >> 4;
1524}
1525
1526void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1527{
8d14695f 1528 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1529 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1530
1531 if (!apic) {
1532 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1533 vcpu->arch.apic_base = value;
97222cc8
ED		 1534 return;
1535 }
c5af89b6 1536
e66d2ae7
JK		 1537 vcpu->arch.apic_base = value;
1538
c5cc421b 1539 /* update jump label if enable bit changes */
0dce7cd6 1540 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1541 if (value & MSR_IA32_APICBASE_ENABLE)
1542 static_key_slow_dec_deferred(&apic_hw_disabled);
1543 else
1544 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1545 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1546 }
1547
8d14695f
YZ		 1548 if ((old_value ^ value) & X2APIC_ENABLE) {
1549 if (value & X2APIC_ENABLE) {
257b9a5f 1550 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
8d14695f
YZ		 1551 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1552 } else
1553 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1554 }
8d14695f 1555
ad312c7c 1556 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1557 MSR_IA32_APICBASE_BASE;
1558
db324fe6
NA		 1559 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1560 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1561 pr_warn_once("APIC base relocation is unsupported by KVM");
1562
97222cc8
ED		 1563 /* with FSB delivery interrupt, we can restart APIC functionality */
1564 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1565 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1566
1567}
1568
d28bc9dd 1569void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8
ED		 1570{
1571 struct kvm_lapic *apic;
1572 int i;
1573
b8688d51 1574 apic_debug("%s\n", __func__);
97222cc8
ED		 1575
1576 ASSERT(vcpu);
ad312c7c 1577 apic = vcpu->arch.apic;
97222cc8
ED		 1578 ASSERT(apic != NULL);
1579
1580 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1581 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1582
d28bc9dd
NA		 1583 if (!init_event)
1584 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1585 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1586
1587 for (i = 0; i < APIC_LVT_NUM; i++)
1588 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
a323b409 1589 apic->lapic_timer.timer_mode = 0;
90de4a18
NA		 1590 if (!(vcpu->kvm->arch.disabled_quirks & KVM_QUIRK_LINT0_REENABLED))
1591 apic_set_reg(apic, APIC_LVT0,
1592 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1593
1594 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1595 apic_set_spiv(apic, 0xff);
97222cc8 1596 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1597 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1598 apic_set_reg(apic, APIC_ESR, 0);
1599 apic_set_reg(apic, APIC_ICR, 0);
1600 apic_set_reg(apic, APIC_ICR2, 0);
1601 apic_set_reg(apic, APIC_TDCR, 0);
1602 apic_set_reg(apic, APIC_TMICT, 0);
1603 for (i = 0; i < 8; i++) {
1604 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1605 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1606 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1607 }
c7c9c56c 1608 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
f563db4b 1609 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
8680b94b 1610 apic->highest_isr_cache = -1;
b33ac88b 1611 update_divide_count(apic);
d3c7b77d 1612 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1613 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1614 kvm_lapic_set_base(vcpu,
1615 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1616 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1617 apic_update_ppr(apic);
1618
e1035715 1619 vcpu->arch.apic_arb_prio = 0;
41383771 1620 vcpu->arch.apic_attention = 0;
e1035715 1621
98eff52a 1622 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1623 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1624 vcpu, kvm_apic_id(apic),
ad312c7c 1625 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1626}
1627
97222cc8
ED		 1628/*
1629 *----------------------------------------------------------------------
1630 * timer interface
1631 *----------------------------------------------------------------------
1632 */
1b9778da 1633
2a6eac96 1634static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1635{
d3c7b77d 1636 return apic_lvtt_period(apic);
97222cc8
ED		 1637}
1638
3d80840d
MT		 1639int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1640{
54e9818f 1641 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1642
c48f1496 1643 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1644 apic_lvt_enabled(apic, APIC_LVTT))
1645 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1646
1647 return 0;
1648}
1649
89342082 1650int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1651{
c48f1496 1652 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1653 int vector, mode, trig_mode;
23930f95 1654
c48f1496 1655 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1656 vector = reg & APIC_VECTOR_MASK;
1657 mode = reg & APIC_MODE_MASK;
1658 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1659 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1660 NULL);
23930f95
JK		 1661 }
1662 return 0;
1663}
1b9778da 1664
8fdb2351 1665void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1666{
8fdb2351
JK		 1667 struct kvm_lapic *apic = vcpu->arch.apic;
1668
1669 if (apic)
1670 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1671}
1672
d76685c4
GH		 1673static const struct kvm_io_device_ops apic_mmio_ops = {
1674 .read = apic_mmio_read,
1675 .write = apic_mmio_write,
d76685c4
GH		 1676};
1677
e9d90d47
AK		 1678static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1679{
1680 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1681 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1682
5d87db71 1683 apic_timer_expired(apic);
e9d90d47 1684
2a6eac96 1685 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1686 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1687 return HRTIMER_RESTART;
1688 } else
1689 return HRTIMER_NORESTART;
1690}
1691
97222cc8
ED		 1692int kvm_create_lapic(struct kvm_vcpu *vcpu)
1693{
1694 struct kvm_lapic *apic;
1695
1696 ASSERT(vcpu != NULL);
1697 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1698
1699 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1700 if (!apic)
1701 goto nomem;
1702
ad312c7c 1703 vcpu->arch.apic = apic;
97222cc8 1704
afc20184
TY		 1705 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1706 if (!apic->regs) {
97222cc8
ED		 1707 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1708 vcpu->vcpu_id);
d589444e 1709 goto nomem_free_apic;
97222cc8 1710 }
97222cc8
ED		 1711 apic->vcpu = vcpu;
1712
d3c7b77d
MT		 1713 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1714 HRTIMER_MODE_ABS);
e9d90d47 1715 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1716
c5cc421b
GN		 1717 /*
1718 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1719 * thinking that APIC satet has changed.
1720 */
1721 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1722 kvm_lapic_set_base(vcpu,
1723 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1724
f8c1ea10 1725 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d28bc9dd 1726 kvm_lapic_reset(vcpu, false);
d76685c4 1727 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1728
1729 return 0;
d589444e
RR		 1730nomem_free_apic:
1731 kfree(apic);
97222cc8 1732nomem:
97222cc8
ED		 1733 return -ENOMEM;
1734}
97222cc8
ED		 1735
1736int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1737{
ad312c7c 1738 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1739 int highest_irr;
1740
c48f1496 1741 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1742 return -1;
1743
6e5d865c 1744 apic_update_ppr(apic);
97222cc8
ED		 1745 highest_irr = apic_find_highest_irr(apic);
1746 if ((highest_irr == -1) ||
c48f1496 1747 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1748 return -1;
1749 return highest_irr;
1750}
1751
40487c68
QH		 1752int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1753{
c48f1496 1754 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1755 int r = 0;
1756
c48f1496 1757 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1758 r = 1;
1759 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1760 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1761 r = 1;
40487c68
QH		 1762 return r;
1763}
1764
1b9778da
ED		 1765void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1766{
ad312c7c 1767 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1768
c48f1496 1769 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1770 return;
1771
1772 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1773 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1774 if (apic_lvtt_tscdeadline(apic))
1775 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1776 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1777 }
1778}
1779
97222cc8
ED		 1780int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1781{
1782 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1783 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1784
1785 if (vector == -1)
1786 return -1;
1787
56cc2406
WL		 1788 /*
1789 * We get here even with APIC virtualization enabled, if doing
1790 * nested virtualization and L1 runs with the "acknowledge interrupt
1791 * on exit" mode. Then we cannot inject the interrupt via RVI,
1792 * because the process would deliver it through the IDT.
1793 */
1794
8680b94b 1795 apic_set_isr(vector, apic);
97222cc8
ED		 1796 apic_update_ppr(apic);
1797 apic_clear_irr(vector, apic);
1798 return vector;
1799}
96ad2cc6 1800
64eb0620
GN		 1801void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1802 struct kvm_lapic_state *s)
96ad2cc6 1803{
ad312c7c 1804 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1805
5dbc8f3f 1806 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1807 /* set SPIV separately to get count of SW disabled APICs right */
1808 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1809 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1810 /* call kvm_apic_set_id() to put apic into apic_map */
1811 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1812 kvm_apic_set_version(vcpu);
1813
96ad2cc6 1814 apic_update_ppr(apic);
d3c7b77d 1815 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1816 update_divide_count(apic);
1817 start_apic_timer(apic);
6e24a6ef 1818 apic->irr_pending = true;
f563db4b 1819 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
c7c9c56c 1820 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1821 apic->highest_isr_cache = -1;
4114c27d
WW		 1822 if (kvm_x86_ops->hwapic_irr_update)
1823 kvm_x86_ops->hwapic_irr_update(vcpu,
1824 apic_find_highest_irr(apic));
b4eef9b3
TC		 1825 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1826 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1827 apic_find_highest_isr(apic));
3842d135 1828 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1829 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1830}
a3d7f85f 1831
2f52d58c 1832void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1833{
a3d7f85f
ED		 1834 struct hrtimer *timer;
1835
c48f1496 1836 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1837 return;
1838
54e9818f 1839 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1840 if (hrtimer_cancel(timer))
beb20d52 1841 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1842}
b93463aa 1843
ae7a2a3f
MT		 1844/*
1845 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1846 *
1847 * Detect whether guest triggered PV EOI since the
1848 * last entry. If yes, set EOI on guests's behalf.
1849 * Clear PV EOI in guest memory in any case.
1850 */
1851static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1852 struct kvm_lapic *apic)
1853{
1854 bool pending;
1855 int vector;
1856 /*
1857 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1858 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1859 *
1860 * KVM_APIC_PV_EOI_PENDING is unset:
1861 * -> host disabled PV EOI.
1862 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1863 * -> host enabled PV EOI, guest did not execute EOI yet.
1864 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1865 * -> host enabled PV EOI, guest executed EOI.
1866 */
1867 BUG_ON(!pv_eoi_enabled(vcpu));
1868 pending = pv_eoi_get_pending(vcpu);
1869 /*
1870 * Clear pending bit in any case: it will be set again on vmentry.
1871 * While this might not be ideal from performance point of view,
1872 * this makes sure pv eoi is only enabled when we know it's safe.
1873 */
1874 pv_eoi_clr_pending(vcpu);
1875 if (pending)
1876 return;
1877 vector = apic_set_eoi(apic);
1878 trace_kvm_pv_eoi(apic, vector);
1879}
1880
b93463aa
AK		 1881void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1882{
1883 u32 data;
b93463aa 1884
ae7a2a3f
MT		 1885 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1886 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1887
41383771 1888 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1889 return;
1890
fda4e2e8
AH		 1891 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1892 sizeof(u32));
b93463aa
AK		 1893
1894 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1895}
1896
ae7a2a3f
MT		 1897/*
1898 * apic_sync_pv_eoi_to_guest - called before vmentry
1899 *
1900 * Detect whether it's safe to enable PV EOI and
1901 * if yes do so.
1902 */
1903static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1904 struct kvm_lapic *apic)
1905{
1906 if (!pv_eoi_enabled(vcpu) ||
1907 /* IRR set or many bits in ISR: could be nested. */
1908 apic->irr_pending ||
1909 /* Cache not set: could be safe but we don't bother. */
1910 apic->highest_isr_cache == -1 ||
1911 /* Need EOI to update ioapic. */
1912 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1913 /*
1914 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1915 * so we need not do anything here.
1916 */
1917 return;
1918 }
1919
1920 pv_eoi_set_pending(apic->vcpu);
1921}
1922
b93463aa
AK		 1923void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1924{
1925 u32 data, tpr;
1926 int max_irr, max_isr;
ae7a2a3f 1927 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1928
ae7a2a3f
MT		 1929 apic_sync_pv_eoi_to_guest(vcpu, apic);
1930
41383771 1931 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1932 return;
1933
c48f1496 1934 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1935 max_irr = apic_find_highest_irr(apic);
1936 if (max_irr < 0)
1937 max_irr = 0;
1938 max_isr = apic_find_highest_isr(apic);
1939 if (max_isr < 0)
1940 max_isr = 0;
1941 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1942
fda4e2e8
AH		 1943 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1944 sizeof(u32));
b93463aa
AK		 1945}
1946
fda4e2e8 1947int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1948{
fda4e2e8
AH		 1949 if (vapic_addr) {
1950 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1951 &vcpu->arch.apic->vapic_cache,
1952 vapic_addr, sizeof(u32)))
1953 return -EINVAL;
41383771 1954 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1955 } else {
41383771 1956 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1957 }
1958
1959 vcpu->arch.apic->vapic_addr = vapic_addr;
1960 return 0;
b93463aa 1961}
0105d1a5
GN		 1962
1963int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1964{
1965 struct kvm_lapic *apic = vcpu->arch.apic;
1966 u32 reg = (msr - APIC_BASE_MSR) << 4;
1967
1968 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1969 return 1;
1970
c69d3d9b
NA		 1971 if (reg == APIC_ICR2)
1972 return 1;
1973
0105d1a5 1974 /* if this is ICR write vector before command */
decdc283 1975 if (reg == APIC_ICR)
0105d1a5
GN		 1976 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1977 return apic_reg_write(apic, reg, (u32)data);
1978}
1979
1980int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1981{
1982 struct kvm_lapic *apic = vcpu->arch.apic;
1983 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1984
1985 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1986 return 1;
1987
c69d3d9b
NA		 1988 if (reg == APIC_DFR || reg == APIC_ICR2) {
1989 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1990 reg);
1991 return 1;
1992 }
1993
0105d1a5
GN		 1994 if (apic_reg_read(apic, reg, 4, &low))
1995 return 1;
decdc283 1996 if (reg == APIC_ICR)
0105d1a5
GN		 1997 apic_reg_read(apic, APIC_ICR2, 4, &high);
1998
1999 *data = (((u64)high) << 32) | low;
2000
2001 return 0;
2002}
10388a07
GN		 2003
2004int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2005{
2006 struct kvm_lapic *apic = vcpu->arch.apic;
2007
c48f1496 2008 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2009 return 1;
2010
2011 /* if this is ICR write vector before command */
2012 if (reg == APIC_ICR)
2013 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2014 return apic_reg_write(apic, reg, (u32)data);
2015}
2016
2017int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2018{
2019 struct kvm_lapic *apic = vcpu->arch.apic;
2020 u32 low, high = 0;
2021
c48f1496 2022 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2023 return 1;
2024
2025 if (apic_reg_read(apic, reg, 4, &low))
2026 return 1;
2027 if (reg == APIC_ICR)
2028 apic_reg_read(apic, APIC_ICR2, 4, &high);
2029
2030 *data = (((u64)high) << 32) | low;
2031
2032 return 0;
2033}
ae7a2a3f
MT		 2034
2035int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2036{
2037 u64 addr = data & ~KVM_MSR_ENABLED;
2038 if (!IS_ALIGNED(addr, 4))
2039 return 1;
2040
2041 vcpu->arch.pv_eoi.msr_val = data;
2042 if (!pv_eoi_enabled(vcpu))
2043 return 0;
2044 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2045 addr, sizeof(u8));
ae7a2a3f 2046}
c5cc421b 2047
66450a21
JK		 2048void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2049{
2050 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2051 u8 sipi_vector;
299018f4 2052 unsigned long pe;
66450a21 2053
299018f4 2054 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2055 return;
2056
299018f4
GN		 2057 pe = xchg(&apic->pending_events, 0);
2058
2059 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd
NA		 2060 kvm_lapic_reset(vcpu, true);
2061 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2062 if (kvm_vcpu_is_bsp(apic->vcpu))
2063 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2064 else
2065 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2066 }
299018f4 2067 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2068 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2069 /* evaluate pending_events before reading the vector */
2070 smp_rmb();
2071 sipi_vector = apic->sipi_vector;
98eff52a 2072 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2073 vcpu->vcpu_id, sipi_vector);
2074 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2075 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2076 }
2077}
2078
c5cc421b
GN		 2079void kvm_lapic_init(void)
2080{
2081 /* do not patch jump label more than once per second */
2082 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2083 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2084}
Linux kernel - Deliverables
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