Commit | Line | Data |
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97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
8 | * | |
9 | * Authors: | |
10 | * Dor Laor <dor.laor@qumranet.com> | |
11 | * Gregory Haskins <ghaskins@novell.com> | |
12 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
13 | * | |
14 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | */ | |
19 | ||
edf88417 | 20 | #include <linux/kvm_host.h> |
97222cc8 ED |
21 | #include <linux/kvm.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/highmem.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/hrtimer.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/module.h> | |
6f6d6a1a | 28 | #include <linux/math64.h> |
97222cc8 ED |
29 | #include <asm/processor.h> |
30 | #include <asm/msr.h> | |
31 | #include <asm/page.h> | |
32 | #include <asm/current.h> | |
33 | #include <asm/apicdef.h> | |
34 | #include <asm/atomic.h> | |
5fdbf976 | 35 | #include "kvm_cache_regs.h" |
97222cc8 ED |
36 | #include "irq.h" |
37 | ||
38 | #define PRId64 "d" | |
39 | #define PRIx64 "llx" | |
40 | #define PRIu64 "u" | |
41 | #define PRIo64 "o" | |
42 | ||
43 | #define APIC_BUS_CYCLE_NS 1 | |
44 | ||
45 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
46 | #define apic_debug(fmt, arg...) | |
47 | ||
48 | #define APIC_LVT_NUM 6 | |
49 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
50 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
51 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
52 | /* followed define is not in apicdef.h */ | |
53 | #define APIC_SHORT_MASK 0xc0000 | |
54 | #define APIC_DEST_NOSHORT 0x0 | |
55 | #define APIC_DEST_MASK 0x800 | |
56 | #define MAX_APIC_VECTOR 256 | |
57 | ||
58 | #define VEC_POS(v) ((v) & (32 - 1)) | |
59 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 60 | |
97222cc8 ED |
61 | static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off) |
62 | { | |
63 | return *((u32 *) (apic->regs + reg_off)); | |
64 | } | |
65 | ||
66 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) | |
67 | { | |
68 | *((u32 *) (apic->regs + reg_off)) = val; | |
69 | } | |
70 | ||
71 | static inline int apic_test_and_set_vector(int vec, void *bitmap) | |
72 | { | |
73 | return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
74 | } | |
75 | ||
76 | static inline int apic_test_and_clear_vector(int vec, void *bitmap) | |
77 | { | |
78 | return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
79 | } | |
80 | ||
81 | static inline void apic_set_vector(int vec, void *bitmap) | |
82 | { | |
83 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
84 | } | |
85 | ||
86 | static inline void apic_clear_vector(int vec, void *bitmap) | |
87 | { | |
88 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
89 | } | |
90 | ||
91 | static inline int apic_hw_enabled(struct kvm_lapic *apic) | |
92 | { | |
ad312c7c | 93 | return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; |
97222cc8 ED |
94 | } |
95 | ||
96 | static inline int apic_sw_enabled(struct kvm_lapic *apic) | |
97 | { | |
98 | return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED; | |
99 | } | |
100 | ||
101 | static inline int apic_enabled(struct kvm_lapic *apic) | |
102 | { | |
103 | return apic_sw_enabled(apic) && apic_hw_enabled(apic); | |
104 | } | |
105 | ||
106 | #define LVT_MASK \ | |
107 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
108 | ||
109 | #define LINT_MASK \ | |
110 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
111 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
112 | ||
113 | static inline int kvm_apic_id(struct kvm_lapic *apic) | |
114 | { | |
115 | return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff; | |
116 | } | |
117 | ||
118 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) | |
119 | { | |
120 | return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); | |
121 | } | |
122 | ||
123 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
124 | { | |
125 | return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; | |
126 | } | |
127 | ||
128 | static inline int apic_lvtt_period(struct kvm_lapic *apic) | |
129 | { | |
130 | return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC; | |
131 | } | |
132 | ||
133 | static unsigned int apic_lvt_mask[APIC_LVT_NUM] = { | |
134 | LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */ | |
135 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ | |
136 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
137 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
138 | LVT_MASK /* LVTERR */ | |
139 | }; | |
140 | ||
141 | static int find_highest_vector(void *bitmap) | |
142 | { | |
143 | u32 *word = bitmap; | |
144 | int word_offset = MAX_APIC_VECTOR >> 5; | |
145 | ||
146 | while ((word_offset != 0) && (word[(--word_offset) << 2] == 0)) | |
147 | continue; | |
148 | ||
149 | if (likely(!word_offset && !word[0])) | |
150 | return -1; | |
151 | else | |
152 | return fls(word[word_offset << 2]) - 1 + (word_offset << 5); | |
153 | } | |
154 | ||
155 | static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) | |
156 | { | |
157 | return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); | |
158 | } | |
159 | ||
160 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) | |
161 | { | |
162 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
163 | } | |
164 | ||
165 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
166 | { | |
167 | int result; | |
168 | ||
169 | result = find_highest_vector(apic->regs + APIC_IRR); | |
170 | ASSERT(result == -1 || result >= 16); | |
171 | ||
172 | return result; | |
173 | } | |
174 | ||
6e5d865c YS |
175 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
176 | { | |
ad312c7c | 177 | struct kvm_lapic *apic = vcpu->arch.apic; |
6e5d865c YS |
178 | int highest_irr; |
179 | ||
180 | if (!apic) | |
181 | return 0; | |
182 | highest_irr = apic_find_highest_irr(apic); | |
183 | ||
184 | return highest_irr; | |
185 | } | |
186 | EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr); | |
187 | ||
8be5453f | 188 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig) |
97222cc8 | 189 | { |
ad312c7c | 190 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 191 | |
97222cc8 ED |
192 | if (!apic_test_and_set_irr(vec, apic)) { |
193 | /* a new pending irq is set in IRR */ | |
194 | if (trig) | |
195 | apic_set_vector(vec, apic->regs + APIC_TMR); | |
196 | else | |
197 | apic_clear_vector(vec, apic->regs + APIC_TMR); | |
198 | kvm_vcpu_kick(apic->vcpu); | |
199 | return 1; | |
200 | } | |
201 | return 0; | |
202 | } | |
203 | ||
204 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) | |
205 | { | |
206 | int result; | |
207 | ||
208 | result = find_highest_vector(apic->regs + APIC_ISR); | |
209 | ASSERT(result == -1 || result >= 16); | |
210 | ||
211 | return result; | |
212 | } | |
213 | ||
214 | static void apic_update_ppr(struct kvm_lapic *apic) | |
215 | { | |
216 | u32 tpr, isrv, ppr; | |
217 | int isr; | |
218 | ||
219 | tpr = apic_get_reg(apic, APIC_TASKPRI); | |
220 | isr = apic_find_highest_isr(apic); | |
221 | isrv = (isr != -1) ? isr : 0; | |
222 | ||
223 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
224 | ppr = tpr & 0xff; | |
225 | else | |
226 | ppr = isrv & 0xf0; | |
227 | ||
228 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
229 | apic, ppr, isr, isrv); | |
230 | ||
231 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
232 | } | |
233 | ||
234 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
235 | { | |
236 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
237 | apic_update_ppr(apic); | |
238 | } | |
239 | ||
240 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) | |
241 | { | |
242 | return kvm_apic_id(apic) == dest; | |
243 | } | |
244 | ||
245 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) | |
246 | { | |
247 | int result = 0; | |
248 | u8 logical_id; | |
249 | ||
250 | logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR)); | |
251 | ||
252 | switch (apic_get_reg(apic, APIC_DFR)) { | |
253 | case APIC_DFR_FLAT: | |
254 | if (logical_id & mda) | |
255 | result = 1; | |
256 | break; | |
257 | case APIC_DFR_CLUSTER: | |
258 | if (((logical_id >> 4) == (mda >> 0x4)) | |
259 | && (logical_id & mda & 0xf)) | |
260 | result = 1; | |
261 | break; | |
262 | default: | |
263 | printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n", | |
264 | apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR)); | |
265 | break; | |
266 | } | |
267 | ||
268 | return result; | |
269 | } | |
270 | ||
271 | static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, | |
272 | int short_hand, int dest, int dest_mode) | |
273 | { | |
274 | int result = 0; | |
ad312c7c | 275 | struct kvm_lapic *target = vcpu->arch.apic; |
97222cc8 ED |
276 | |
277 | apic_debug("target %p, source %p, dest 0x%x, " | |
278 | "dest_mode 0x%x, short_hand 0x%x", | |
279 | target, source, dest, dest_mode, short_hand); | |
280 | ||
281 | ASSERT(!target); | |
282 | switch (short_hand) { | |
283 | case APIC_DEST_NOSHORT: | |
284 | if (dest_mode == 0) { | |
285 | /* Physical mode. */ | |
286 | if ((dest == 0xFF) || (dest == kvm_apic_id(target))) | |
287 | result = 1; | |
288 | } else | |
289 | /* Logical mode. */ | |
290 | result = kvm_apic_match_logical_addr(target, dest); | |
291 | break; | |
292 | case APIC_DEST_SELF: | |
293 | if (target == source) | |
294 | result = 1; | |
295 | break; | |
296 | case APIC_DEST_ALLINC: | |
297 | result = 1; | |
298 | break; | |
299 | case APIC_DEST_ALLBUT: | |
300 | if (target != source) | |
301 | result = 1; | |
302 | break; | |
303 | default: | |
304 | printk(KERN_WARNING "Bad dest shorthand value %x\n", | |
305 | short_hand); | |
306 | break; | |
307 | } | |
308 | ||
309 | return result; | |
310 | } | |
311 | ||
312 | /* | |
313 | * Add a pending IRQ into lapic. | |
314 | * Return 1 if successfully added and 0 if discarded. | |
315 | */ | |
316 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
317 | int vector, int level, int trig_mode) | |
318 | { | |
c5ec1534 HQ |
319 | int orig_irr, result = 0; |
320 | struct kvm_vcpu *vcpu = apic->vcpu; | |
97222cc8 ED |
321 | |
322 | switch (delivery_mode) { | |
323 | case APIC_DM_FIXED: | |
324 | case APIC_DM_LOWEST: | |
325 | /* FIXME add logic for vcpu on reset */ | |
326 | if (unlikely(!apic_enabled(apic))) | |
327 | break; | |
328 | ||
1b9778da ED |
329 | orig_irr = apic_test_and_set_irr(vector, apic); |
330 | if (orig_irr && trig_mode) { | |
97222cc8 ED |
331 | apic_debug("level trig mode repeatedly for vector %d", |
332 | vector); | |
333 | break; | |
334 | } | |
335 | ||
336 | if (trig_mode) { | |
337 | apic_debug("level trig mode for vector %d", vector); | |
338 | apic_set_vector(vector, apic->regs + APIC_TMR); | |
339 | } else | |
340 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
341 | ||
d7690175 | 342 | kvm_vcpu_kick(vcpu); |
97222cc8 | 343 | |
1b9778da | 344 | result = (orig_irr == 0); |
97222cc8 ED |
345 | break; |
346 | ||
347 | case APIC_DM_REMRD: | |
348 | printk(KERN_DEBUG "Ignoring delivery mode 3\n"); | |
349 | break; | |
350 | ||
351 | case APIC_DM_SMI: | |
352 | printk(KERN_DEBUG "Ignoring guest SMI\n"); | |
353 | break; | |
3419ffc8 | 354 | |
97222cc8 | 355 | case APIC_DM_NMI: |
3419ffc8 | 356 | kvm_inject_nmi(vcpu); |
26df99c6 | 357 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
358 | break; |
359 | ||
360 | case APIC_DM_INIT: | |
c5ec1534 | 361 | if (level) { |
a4535290 | 362 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
c5ec1534 HQ |
363 | printk(KERN_DEBUG |
364 | "INIT on a runnable vcpu %d\n", | |
365 | vcpu->vcpu_id); | |
a4535290 | 366 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; |
c5ec1534 HQ |
367 | kvm_vcpu_kick(vcpu); |
368 | } else { | |
1b10bf31 JK |
369 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
370 | vcpu->vcpu_id); | |
c5ec1534 | 371 | } |
97222cc8 ED |
372 | break; |
373 | ||
374 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
375 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
376 | vcpu->vcpu_id, vector); | |
a4535290 | 377 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
ad312c7c | 378 | vcpu->arch.sipi_vector = vector; |
a4535290 | 379 | vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED; |
d7690175 | 380 | kvm_vcpu_kick(vcpu); |
c5ec1534 | 381 | } |
97222cc8 ED |
382 | break; |
383 | ||
23930f95 JK |
384 | case APIC_DM_EXTINT: |
385 | /* | |
386 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
387 | * before NMI watchdog was enabled. Already handled by | |
388 | * kvm_apic_accept_pic_intr(). | |
389 | */ | |
390 | break; | |
391 | ||
97222cc8 ED |
392 | default: |
393 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
394 | delivery_mode); | |
395 | break; | |
396 | } | |
397 | return result; | |
398 | } | |
399 | ||
8be5453f | 400 | static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector, |
97222cc8 ED |
401 | unsigned long bitmap) |
402 | { | |
932f72ad HQ |
403 | int last; |
404 | int next; | |
e4d47f40 | 405 | struct kvm_lapic *apic = NULL; |
932f72ad | 406 | |
bfc6d222 | 407 | last = kvm->arch.round_robin_prev_vcpu; |
932f72ad HQ |
408 | next = last; |
409 | ||
410 | do { | |
411 | if (++next == KVM_MAX_VCPUS) | |
412 | next = 0; | |
413 | if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap)) | |
414 | continue; | |
ad312c7c | 415 | apic = kvm->vcpus[next]->arch.apic; |
932f72ad HQ |
416 | if (apic && apic_enabled(apic)) |
417 | break; | |
418 | apic = NULL; | |
419 | } while (next != last); | |
bfc6d222 | 420 | kvm->arch.round_robin_prev_vcpu = next; |
932f72ad | 421 | |
e4d47f40 QH |
422 | if (!apic) |
423 | printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n"); | |
97222cc8 | 424 | |
932f72ad | 425 | return apic; |
97222cc8 ED |
426 | } |
427 | ||
8be5453f ZX |
428 | struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector, |
429 | unsigned long bitmap) | |
430 | { | |
431 | struct kvm_lapic *apic; | |
432 | ||
433 | apic = kvm_apic_round_robin(kvm, vector, bitmap); | |
434 | if (apic) | |
435 | return apic->vcpu; | |
436 | return NULL; | |
437 | } | |
438 | ||
97222cc8 ED |
439 | static void apic_set_eoi(struct kvm_lapic *apic) |
440 | { | |
441 | int vector = apic_find_highest_isr(apic); | |
f5244726 | 442 | int trigger_mode; |
97222cc8 ED |
443 | /* |
444 | * Not every write EOI will has corresponding ISR, | |
445 | * one example is when Kernel check timer on setup_IO_APIC | |
446 | */ | |
447 | if (vector == -1) | |
448 | return; | |
449 | ||
450 | apic_clear_vector(vector, apic->regs + APIC_ISR); | |
451 | apic_update_ppr(apic); | |
452 | ||
453 | if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR)) | |
f5244726 MT |
454 | trigger_mode = IOAPIC_LEVEL_TRIG; |
455 | else | |
456 | trigger_mode = IOAPIC_EDGE_TRIG; | |
457 | kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode); | |
97222cc8 ED |
458 | } |
459 | ||
460 | static void apic_send_ipi(struct kvm_lapic *apic) | |
461 | { | |
462 | u32 icr_low = apic_get_reg(apic, APIC_ICR); | |
463 | u32 icr_high = apic_get_reg(apic, APIC_ICR2); | |
464 | ||
465 | unsigned int dest = GET_APIC_DEST_FIELD(icr_high); | |
466 | unsigned int short_hand = icr_low & APIC_SHORT_MASK; | |
467 | unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG; | |
468 | unsigned int level = icr_low & APIC_INT_ASSERT; | |
469 | unsigned int dest_mode = icr_low & APIC_DEST_MASK; | |
470 | unsigned int delivery_mode = icr_low & APIC_MODE_MASK; | |
471 | unsigned int vector = icr_low & APIC_VECTOR_MASK; | |
472 | ||
8be5453f | 473 | struct kvm_vcpu *target; |
97222cc8 ED |
474 | struct kvm_vcpu *vcpu; |
475 | unsigned long lpr_map = 0; | |
476 | int i; | |
477 | ||
478 | apic_debug("icr_high 0x%x, icr_low 0x%x, " | |
479 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
480 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", | |
481 | icr_high, icr_low, short_hand, dest, | |
482 | trig_mode, level, dest_mode, delivery_mode, vector); | |
483 | ||
484 | for (i = 0; i < KVM_MAX_VCPUS; i++) { | |
485 | vcpu = apic->vcpu->kvm->vcpus[i]; | |
486 | if (!vcpu) | |
487 | continue; | |
488 | ||
ad312c7c | 489 | if (vcpu->arch.apic && |
97222cc8 ED |
490 | apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) { |
491 | if (delivery_mode == APIC_DM_LOWEST) | |
492 | set_bit(vcpu->vcpu_id, &lpr_map); | |
493 | else | |
ad312c7c | 494 | __apic_accept_irq(vcpu->arch.apic, delivery_mode, |
97222cc8 ED |
495 | vector, level, trig_mode); |
496 | } | |
497 | } | |
498 | ||
499 | if (delivery_mode == APIC_DM_LOWEST) { | |
8be5453f | 500 | target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map); |
97222cc8 | 501 | if (target != NULL) |
ad312c7c | 502 | __apic_accept_irq(target->arch.apic, delivery_mode, |
97222cc8 ED |
503 | vector, level, trig_mode); |
504 | } | |
505 | } | |
506 | ||
507 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
508 | { | |
9da8f4e8 KP |
509 | u64 counter_passed; |
510 | ktime_t passed, now; | |
511 | u32 tmcct; | |
97222cc8 ED |
512 | |
513 | ASSERT(apic != NULL); | |
514 | ||
9da8f4e8 KP |
515 | now = apic->timer.dev.base->get_time(); |
516 | tmcct = apic_get_reg(apic, APIC_TMICT); | |
517 | ||
518 | /* if initial count is 0, current count should also be 0 */ | |
519 | if (tmcct == 0) | |
520 | return 0; | |
521 | ||
97222cc8 ED |
522 | if (unlikely(ktime_to_ns(now) <= |
523 | ktime_to_ns(apic->timer.last_update))) { | |
524 | /* Wrap around */ | |
525 | passed = ktime_add(( { | |
526 | (ktime_t) { | |
527 | .tv64 = KTIME_MAX - | |
528 | (apic->timer.last_update).tv64}; } | |
529 | ), now); | |
530 | apic_debug("time elapsed\n"); | |
531 | } else | |
532 | passed = ktime_sub(now, apic->timer.last_update); | |
533 | ||
6f6d6a1a RZ |
534 | counter_passed = div64_u64(ktime_to_ns(passed), |
535 | (APIC_BUS_CYCLE_NS * apic->timer.divide_count)); | |
97222cc8 | 536 | |
9da8f4e8 KP |
537 | if (counter_passed > tmcct) { |
538 | if (unlikely(!apic_lvtt_period(apic))) { | |
539 | /* one-shot timers stick at 0 until reset */ | |
97222cc8 | 540 | tmcct = 0; |
9da8f4e8 KP |
541 | } else { |
542 | /* | |
543 | * periodic timers reset to APIC_TMICT when they | |
544 | * hit 0. The while loop simulates this happening N | |
545 | * times. (counter_passed %= tmcct) would also work, | |
546 | * but might be slower or not work on 32-bit?? | |
547 | */ | |
548 | while (counter_passed > tmcct) | |
549 | counter_passed -= tmcct; | |
550 | tmcct -= counter_passed; | |
551 | } | |
552 | } else { | |
553 | tmcct -= counter_passed; | |
97222cc8 ED |
554 | } |
555 | ||
556 | return tmcct; | |
557 | } | |
558 | ||
b209749f AK |
559 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
560 | { | |
561 | struct kvm_vcpu *vcpu = apic->vcpu; | |
562 | struct kvm_run *run = vcpu->run; | |
563 | ||
564 | set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests); | |
5fdbf976 | 565 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
566 | run->tpr_access.is_write = write; |
567 | } | |
568 | ||
569 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
570 | { | |
571 | if (apic->vcpu->arch.tpr_access_reporting) | |
572 | __report_tpr_access(apic, write); | |
573 | } | |
574 | ||
97222cc8 ED |
575 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
576 | { | |
577 | u32 val = 0; | |
578 | ||
c7bf23ba JR |
579 | KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); |
580 | ||
97222cc8 ED |
581 | if (offset >= LAPIC_MMIO_LENGTH) |
582 | return 0; | |
583 | ||
584 | switch (offset) { | |
585 | case APIC_ARBPRI: | |
586 | printk(KERN_WARNING "Access APIC ARBPRI register " | |
587 | "which is for P6\n"); | |
588 | break; | |
589 | ||
590 | case APIC_TMCCT: /* Timer CCR */ | |
591 | val = apic_get_tmcct(apic); | |
592 | break; | |
593 | ||
b209749f AK |
594 | case APIC_TASKPRI: |
595 | report_tpr_access(apic, false); | |
596 | /* fall thru */ | |
97222cc8 | 597 | default: |
6e5d865c | 598 | apic_update_ppr(apic); |
97222cc8 ED |
599 | val = apic_get_reg(apic, offset); |
600 | break; | |
601 | } | |
602 | ||
603 | return val; | |
604 | } | |
605 | ||
606 | static void apic_mmio_read(struct kvm_io_device *this, | |
607 | gpa_t address, int len, void *data) | |
608 | { | |
609 | struct kvm_lapic *apic = (struct kvm_lapic *)this->private; | |
610 | unsigned int offset = address - apic->base_address; | |
611 | unsigned char alignment = offset & 0xf; | |
612 | u32 result; | |
613 | ||
614 | if ((alignment + len) > 4) { | |
615 | printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d", | |
616 | (unsigned long)address, len); | |
617 | return; | |
618 | } | |
619 | result = __apic_read(apic, offset & ~0xf); | |
620 | ||
621 | switch (len) { | |
622 | case 1: | |
623 | case 2: | |
624 | case 4: | |
625 | memcpy(data, (char *)&result + alignment, len); | |
626 | break; | |
627 | default: | |
628 | printk(KERN_ERR "Local APIC read with len = %x, " | |
629 | "should be 1,2, or 4 instead\n", len); | |
630 | break; | |
631 | } | |
632 | } | |
633 | ||
634 | static void update_divide_count(struct kvm_lapic *apic) | |
635 | { | |
636 | u32 tmp1, tmp2, tdcr; | |
637 | ||
638 | tdcr = apic_get_reg(apic, APIC_TDCR); | |
639 | tmp1 = tdcr & 0xf; | |
640 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
641 | apic->timer.divide_count = 0x1 << (tmp2 & 0x7); | |
642 | ||
643 | apic_debug("timer divide count is 0x%x\n", | |
644 | apic->timer.divide_count); | |
645 | } | |
646 | ||
647 | static void start_apic_timer(struct kvm_lapic *apic) | |
648 | { | |
649 | ktime_t now = apic->timer.dev.base->get_time(); | |
650 | ||
651 | apic->timer.last_update = now; | |
652 | ||
653 | apic->timer.period = apic_get_reg(apic, APIC_TMICT) * | |
654 | APIC_BUS_CYCLE_NS * apic->timer.divide_count; | |
655 | atomic_set(&apic->timer.pending, 0); | |
0b975a3c AK |
656 | |
657 | if (!apic->timer.period) | |
658 | return; | |
659 | ||
97222cc8 ED |
660 | hrtimer_start(&apic->timer.dev, |
661 | ktime_add_ns(now, apic->timer.period), | |
662 | HRTIMER_MODE_ABS); | |
663 | ||
664 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" | |
665 | PRIx64 ", " | |
666 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 667 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 ED |
668 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
669 | apic_get_reg(apic, APIC_TMICT), | |
670 | apic->timer.period, | |
671 | ktime_to_ns(ktime_add_ns(now, | |
672 | apic->timer.period))); | |
673 | } | |
674 | ||
675 | static void apic_mmio_write(struct kvm_io_device *this, | |
676 | gpa_t address, int len, const void *data) | |
677 | { | |
678 | struct kvm_lapic *apic = (struct kvm_lapic *)this->private; | |
679 | unsigned int offset = address - apic->base_address; | |
680 | unsigned char alignment = offset & 0xf; | |
681 | u32 val; | |
682 | ||
683 | /* | |
684 | * APIC register must be aligned on 128-bits boundary. | |
685 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
686 | * Refer SDM 8.4.1 | |
687 | */ | |
688 | if (len != 4 || alignment) { | |
1b10bf31 JK |
689 | /* Don't shout loud, $infamous_os would cause only noise. */ |
690 | apic_debug("apic write: bad size=%d %lx\n", | |
691 | len, (long)address); | |
97222cc8 ED |
692 | return; |
693 | } | |
694 | ||
695 | val = *(u32 *) data; | |
696 | ||
697 | /* too common printing */ | |
698 | if (offset != APIC_EOI) | |
699 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
b8688d51 | 700 | "0x%x\n", __func__, offset, len, val); |
97222cc8 ED |
701 | |
702 | offset &= 0xff0; | |
703 | ||
c7bf23ba JR |
704 | KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler); |
705 | ||
97222cc8 ED |
706 | switch (offset) { |
707 | case APIC_ID: /* Local APIC ID */ | |
708 | apic_set_reg(apic, APIC_ID, val); | |
709 | break; | |
710 | ||
711 | case APIC_TASKPRI: | |
b209749f | 712 | report_tpr_access(apic, true); |
97222cc8 ED |
713 | apic_set_tpr(apic, val & 0xff); |
714 | break; | |
715 | ||
716 | case APIC_EOI: | |
717 | apic_set_eoi(apic); | |
718 | break; | |
719 | ||
720 | case APIC_LDR: | |
721 | apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK); | |
722 | break; | |
723 | ||
724 | case APIC_DFR: | |
725 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); | |
726 | break; | |
727 | ||
728 | case APIC_SPIV: | |
729 | apic_set_reg(apic, APIC_SPIV, val & 0x3ff); | |
730 | if (!(val & APIC_SPIV_APIC_ENABLED)) { | |
731 | int i; | |
732 | u32 lvt_val; | |
733 | ||
734 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
735 | lvt_val = apic_get_reg(apic, | |
736 | APIC_LVTT + 0x10 * i); | |
737 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
738 | lvt_val | APIC_LVT_MASKED); | |
739 | } | |
740 | atomic_set(&apic->timer.pending, 0); | |
741 | ||
742 | } | |
743 | break; | |
744 | ||
745 | case APIC_ICR: | |
746 | /* No delay here, so we always clear the pending bit */ | |
747 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
748 | apic_send_ipi(apic); | |
749 | break; | |
750 | ||
751 | case APIC_ICR2: | |
752 | apic_set_reg(apic, APIC_ICR2, val & 0xff000000); | |
753 | break; | |
754 | ||
23930f95 JK |
755 | case APIC_LVT0: |
756 | if (val == APIC_DM_NMI) | |
757 | apic_debug("Receive NMI setting on APIC_LVT0 " | |
758 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
97222cc8 ED |
759 | case APIC_LVTT: |
760 | case APIC_LVTTHMR: | |
761 | case APIC_LVTPC: | |
97222cc8 ED |
762 | case APIC_LVT1: |
763 | case APIC_LVTERR: | |
764 | /* TODO: Check vector */ | |
765 | if (!apic_sw_enabled(apic)) | |
766 | val |= APIC_LVT_MASKED; | |
767 | ||
768 | val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4]; | |
769 | apic_set_reg(apic, offset, val); | |
770 | ||
771 | break; | |
772 | ||
773 | case APIC_TMICT: | |
774 | hrtimer_cancel(&apic->timer.dev); | |
775 | apic_set_reg(apic, APIC_TMICT, val); | |
776 | start_apic_timer(apic); | |
777 | return; | |
778 | ||
779 | case APIC_TDCR: | |
780 | if (val & 4) | |
781 | printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val); | |
782 | apic_set_reg(apic, APIC_TDCR, val); | |
783 | update_divide_count(apic); | |
784 | break; | |
785 | ||
786 | default: | |
787 | apic_debug("Local APIC Write to read-only register %x\n", | |
788 | offset); | |
789 | break; | |
790 | } | |
791 | ||
792 | } | |
793 | ||
92760499 LV |
794 | static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr, |
795 | int len, int size) | |
97222cc8 ED |
796 | { |
797 | struct kvm_lapic *apic = (struct kvm_lapic *)this->private; | |
798 | int ret = 0; | |
799 | ||
800 | ||
801 | if (apic_hw_enabled(apic) && | |
802 | (addr >= apic->base_address) && | |
803 | (addr < (apic->base_address + LAPIC_MMIO_LENGTH))) | |
804 | ret = 1; | |
805 | ||
806 | return ret; | |
807 | } | |
808 | ||
d589444e | 809 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 810 | { |
ad312c7c | 811 | if (!vcpu->arch.apic) |
97222cc8 ED |
812 | return; |
813 | ||
ad312c7c | 814 | hrtimer_cancel(&vcpu->arch.apic->timer.dev); |
97222cc8 | 815 | |
ad312c7c ZX |
816 | if (vcpu->arch.apic->regs_page) |
817 | __free_page(vcpu->arch.apic->regs_page); | |
97222cc8 | 818 | |
ad312c7c | 819 | kfree(vcpu->arch.apic); |
97222cc8 ED |
820 | } |
821 | ||
822 | /* | |
823 | *---------------------------------------------------------------------- | |
824 | * LAPIC interface | |
825 | *---------------------------------------------------------------------- | |
826 | */ | |
827 | ||
828 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) | |
829 | { | |
ad312c7c | 830 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
831 | |
832 | if (!apic) | |
833 | return; | |
b93463aa AK |
834 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
835 | | (apic_get_reg(apic, APIC_TASKPRI) & 4)); | |
97222cc8 | 836 | } |
ec7cf690 | 837 | EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr); |
97222cc8 ED |
838 | |
839 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
840 | { | |
ad312c7c | 841 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
842 | u64 tpr; |
843 | ||
844 | if (!apic) | |
845 | return 0; | |
846 | tpr = (u64) apic_get_reg(apic, APIC_TASKPRI); | |
847 | ||
848 | return (tpr & 0xf0) >> 4; | |
849 | } | |
6e5d865c | 850 | EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8); |
97222cc8 ED |
851 | |
852 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
853 | { | |
ad312c7c | 854 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
855 | |
856 | if (!apic) { | |
857 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 858 | vcpu->arch.apic_base = value; |
97222cc8 ED |
859 | return; |
860 | } | |
861 | if (apic->vcpu->vcpu_id) | |
862 | value &= ~MSR_IA32_APICBASE_BSP; | |
863 | ||
ad312c7c ZX |
864 | vcpu->arch.apic_base = value; |
865 | apic->base_address = apic->vcpu->arch.apic_base & | |
97222cc8 ED |
866 | MSR_IA32_APICBASE_BASE; |
867 | ||
868 | /* with FSB delivery interrupt, we can restart APIC functionality */ | |
869 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 870 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
871 | |
872 | } | |
873 | ||
874 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu) | |
875 | { | |
ad312c7c | 876 | return vcpu->arch.apic_base; |
97222cc8 ED |
877 | } |
878 | EXPORT_SYMBOL_GPL(kvm_lapic_get_base); | |
879 | ||
c5ec1534 | 880 | void kvm_lapic_reset(struct kvm_vcpu *vcpu) |
97222cc8 ED |
881 | { |
882 | struct kvm_lapic *apic; | |
883 | int i; | |
884 | ||
b8688d51 | 885 | apic_debug("%s\n", __func__); |
97222cc8 ED |
886 | |
887 | ASSERT(vcpu); | |
ad312c7c | 888 | apic = vcpu->arch.apic; |
97222cc8 ED |
889 | ASSERT(apic != NULL); |
890 | ||
891 | /* Stop the timer in case it's a reset to an active apic */ | |
892 | hrtimer_cancel(&apic->timer.dev); | |
893 | ||
894 | apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24); | |
895 | apic_set_reg(apic, APIC_LVR, APIC_VERSION); | |
896 | ||
897 | for (i = 0; i < APIC_LVT_NUM; i++) | |
898 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
40487c68 QH |
899 | apic_set_reg(apic, APIC_LVT0, |
900 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
97222cc8 ED |
901 | |
902 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
903 | apic_set_reg(apic, APIC_SPIV, 0xff); | |
904 | apic_set_reg(apic, APIC_TASKPRI, 0); | |
905 | apic_set_reg(apic, APIC_LDR, 0); | |
906 | apic_set_reg(apic, APIC_ESR, 0); | |
907 | apic_set_reg(apic, APIC_ICR, 0); | |
908 | apic_set_reg(apic, APIC_ICR2, 0); | |
909 | apic_set_reg(apic, APIC_TDCR, 0); | |
910 | apic_set_reg(apic, APIC_TMICT, 0); | |
911 | for (i = 0; i < 8; i++) { | |
912 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
913 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
914 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
915 | } | |
b33ac88b | 916 | update_divide_count(apic); |
97222cc8 ED |
917 | atomic_set(&apic->timer.pending, 0); |
918 | if (vcpu->vcpu_id == 0) | |
ad312c7c | 919 | vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; |
97222cc8 ED |
920 | apic_update_ppr(apic); |
921 | ||
922 | apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" | |
b8688d51 | 923 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 924 | vcpu, kvm_apic_id(apic), |
ad312c7c | 925 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 | 926 | } |
c5ec1534 | 927 | EXPORT_SYMBOL_GPL(kvm_lapic_reset); |
97222cc8 ED |
928 | |
929 | int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
930 | { | |
ad312c7c | 931 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
932 | int ret = 0; |
933 | ||
934 | if (!apic) | |
935 | return 0; | |
936 | ret = apic_enabled(apic); | |
937 | ||
938 | return ret; | |
939 | } | |
6e5d865c | 940 | EXPORT_SYMBOL_GPL(kvm_lapic_enabled); |
97222cc8 ED |
941 | |
942 | /* | |
943 | *---------------------------------------------------------------------- | |
944 | * timer interface | |
945 | *---------------------------------------------------------------------- | |
946 | */ | |
1b9778da ED |
947 | |
948 | /* TODO: make sure __apic_timer_fn runs in current pCPU */ | |
97222cc8 ED |
949 | static int __apic_timer_fn(struct kvm_lapic *apic) |
950 | { | |
97222cc8 | 951 | int result = 0; |
1b9778da | 952 | wait_queue_head_t *q = &apic->vcpu->wq; |
97222cc8 | 953 | |
622395a9 MT |
954 | if(!atomic_inc_and_test(&apic->timer.pending)) |
955 | set_bit(KVM_REQ_PENDING_TIMER, &apic->vcpu->requests); | |
d7690175 | 956 | if (waitqueue_active(q)) |
1b9778da | 957 | wake_up_interruptible(q); |
d7690175 | 958 | |
97222cc8 | 959 | if (apic_lvtt_period(apic)) { |
97222cc8 | 960 | result = 1; |
beb20d52 | 961 | hrtimer_add_expires_ns(&apic->timer.dev, apic->timer.period); |
97222cc8 | 962 | } |
97222cc8 ED |
963 | return result; |
964 | } | |
965 | ||
3d80840d MT |
966 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
967 | { | |
968 | struct kvm_lapic *lapic = vcpu->arch.apic; | |
969 | ||
54aaacee | 970 | if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT)) |
3d80840d MT |
971 | return atomic_read(&lapic->timer.pending); |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
23930f95 | 976 | int kvm_apic_local_deliver(struct kvm_vcpu *vcpu, int lvt_type) |
1b9778da | 977 | { |
23930f95 JK |
978 | struct kvm_lapic *apic = vcpu->arch.apic; |
979 | int vector, mode, trig_mode; | |
980 | u32 reg; | |
981 | ||
982 | if (apic && apic_enabled(apic)) { | |
983 | reg = apic_get_reg(apic, lvt_type); | |
984 | vector = reg & APIC_VECTOR_MASK; | |
985 | mode = reg & APIC_MODE_MASK; | |
986 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
987 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode); | |
988 | } | |
989 | return 0; | |
990 | } | |
1b9778da | 991 | |
23930f95 JK |
992 | static inline int __inject_apic_timer_irq(struct kvm_lapic *apic) |
993 | { | |
994 | return kvm_apic_local_deliver(apic->vcpu, APIC_LVTT); | |
1b9778da ED |
995 | } |
996 | ||
97222cc8 ED |
997 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
998 | { | |
999 | struct kvm_lapic *apic; | |
1000 | int restart_timer = 0; | |
1001 | ||
1002 | apic = container_of(data, struct kvm_lapic, timer.dev); | |
1003 | ||
1004 | restart_timer = __apic_timer_fn(apic); | |
1005 | ||
1006 | if (restart_timer) | |
1007 | return HRTIMER_RESTART; | |
1008 | else | |
1009 | return HRTIMER_NORESTART; | |
1010 | } | |
1011 | ||
1012 | int kvm_create_lapic(struct kvm_vcpu *vcpu) | |
1013 | { | |
1014 | struct kvm_lapic *apic; | |
1015 | ||
1016 | ASSERT(vcpu != NULL); | |
1017 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1018 | ||
1019 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1020 | if (!apic) | |
1021 | goto nomem; | |
1022 | ||
ad312c7c | 1023 | vcpu->arch.apic = apic; |
97222cc8 ED |
1024 | |
1025 | apic->regs_page = alloc_page(GFP_KERNEL); | |
1026 | if (apic->regs_page == NULL) { | |
1027 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", | |
1028 | vcpu->vcpu_id); | |
d589444e | 1029 | goto nomem_free_apic; |
97222cc8 ED |
1030 | } |
1031 | apic->regs = page_address(apic->regs_page); | |
1032 | memset(apic->regs, 0, PAGE_SIZE); | |
1033 | apic->vcpu = vcpu; | |
1034 | ||
1035 | hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); | |
1036 | apic->timer.dev.function = apic_timer_fn; | |
1037 | apic->base_address = APIC_DEFAULT_PHYS_BASE; | |
ad312c7c | 1038 | vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE; |
97222cc8 | 1039 | |
c5ec1534 | 1040 | kvm_lapic_reset(vcpu); |
97222cc8 ED |
1041 | apic->dev.read = apic_mmio_read; |
1042 | apic->dev.write = apic_mmio_write; | |
1043 | apic->dev.in_range = apic_mmio_range; | |
1044 | apic->dev.private = apic; | |
1045 | ||
1046 | return 0; | |
d589444e RR |
1047 | nomem_free_apic: |
1048 | kfree(apic); | |
97222cc8 | 1049 | nomem: |
97222cc8 ED |
1050 | return -ENOMEM; |
1051 | } | |
1052 | EXPORT_SYMBOL_GPL(kvm_create_lapic); | |
1053 | ||
1054 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1055 | { | |
ad312c7c | 1056 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1057 | int highest_irr; |
1058 | ||
1059 | if (!apic || !apic_enabled(apic)) | |
1060 | return -1; | |
1061 | ||
6e5d865c | 1062 | apic_update_ppr(apic); |
97222cc8 ED |
1063 | highest_irr = apic_find_highest_irr(apic); |
1064 | if ((highest_irr == -1) || | |
1065 | ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI))) | |
1066 | return -1; | |
1067 | return highest_irr; | |
1068 | } | |
1069 | ||
40487c68 QH |
1070 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1071 | { | |
ad312c7c | 1072 | u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1073 | int r = 0; |
1074 | ||
1075 | if (vcpu->vcpu_id == 0) { | |
ad312c7c | 1076 | if (!apic_hw_enabled(vcpu->arch.apic)) |
40487c68 QH |
1077 | r = 1; |
1078 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1079 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1080 | r = 1; | |
1081 | } | |
1082 | return r; | |
1083 | } | |
1084 | ||
1b9778da ED |
1085 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1086 | { | |
ad312c7c | 1087 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da ED |
1088 | |
1089 | if (apic && apic_lvt_enabled(apic, APIC_LVTT) && | |
1090 | atomic_read(&apic->timer.pending) > 0) { | |
1091 | if (__inject_apic_timer_irq(apic)) | |
1092 | atomic_dec(&apic->timer.pending); | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec) | |
1097 | { | |
ad312c7c | 1098 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da ED |
1099 | |
1100 | if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec) | |
1101 | apic->timer.last_update = ktime_add_ns( | |
1102 | apic->timer.last_update, | |
1103 | apic->timer.period); | |
1104 | } | |
1105 | ||
97222cc8 ED |
1106 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1107 | { | |
1108 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1109 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1110 | |
1111 | if (vector == -1) | |
1112 | return -1; | |
1113 | ||
1114 | apic_set_vector(vector, apic->regs + APIC_ISR); | |
1115 | apic_update_ppr(apic); | |
1116 | apic_clear_irr(vector, apic); | |
1117 | return vector; | |
1118 | } | |
96ad2cc6 ED |
1119 | |
1120 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu) | |
1121 | { | |
ad312c7c | 1122 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1123 | |
ad312c7c | 1124 | apic->base_address = vcpu->arch.apic_base & |
96ad2cc6 ED |
1125 | MSR_IA32_APICBASE_BASE; |
1126 | apic_set_reg(apic, APIC_LVR, APIC_VERSION); | |
1127 | apic_update_ppr(apic); | |
1128 | hrtimer_cancel(&apic->timer.dev); | |
1129 | update_divide_count(apic); | |
1130 | start_apic_timer(apic); | |
1131 | } | |
a3d7f85f | 1132 | |
2f52d58c | 1133 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1134 | { |
ad312c7c | 1135 | struct kvm_lapic *apic = vcpu->arch.apic; |
a3d7f85f ED |
1136 | struct hrtimer *timer; |
1137 | ||
1138 | if (!apic) | |
1139 | return; | |
1140 | ||
1141 | timer = &apic->timer.dev; | |
1142 | if (hrtimer_cancel(timer)) | |
beb20d52 | 1143 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1144 | } |
b93463aa AK |
1145 | |
1146 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) | |
1147 | { | |
1148 | u32 data; | |
1149 | void *vapic; | |
1150 | ||
1151 | if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) | |
1152 | return; | |
1153 | ||
1154 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); | |
1155 | data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); | |
1156 | kunmap_atomic(vapic, KM_USER0); | |
1157 | ||
1158 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1159 | } | |
1160 | ||
1161 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) | |
1162 | { | |
1163 | u32 data, tpr; | |
1164 | int max_irr, max_isr; | |
1165 | struct kvm_lapic *apic; | |
1166 | void *vapic; | |
1167 | ||
1168 | if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr) | |
1169 | return; | |
1170 | ||
1171 | apic = vcpu->arch.apic; | |
1172 | tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff; | |
1173 | max_irr = apic_find_highest_irr(apic); | |
1174 | if (max_irr < 0) | |
1175 | max_irr = 0; | |
1176 | max_isr = apic_find_highest_isr(apic); | |
1177 | if (max_isr < 0) | |
1178 | max_isr = 0; | |
1179 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
1180 | ||
1181 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0); | |
1182 | *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; | |
1183 | kunmap_atomic(vapic, KM_USER0); | |
1184 | } | |
1185 | ||
1186 | void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) | |
1187 | { | |
1188 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1189 | return; | |
1190 | ||
1191 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
1192 | } |