Commit | Line | Data |
---|---|---|
97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
60063497 | 36 | #include <linux/atomic.h> |
c5cc421b | 37 | #include <linux/jump_label.h> |
5fdbf976 | 38 | #include "kvm_cache_regs.h" |
97222cc8 | 39 | #include "irq.h" |
229456fc | 40 | #include "trace.h" |
fc61b800 | 41 | #include "x86.h" |
00b27a3e | 42 | #include "cpuid.h" |
97222cc8 | 43 | |
b682b814 MT |
44 | #ifndef CONFIG_X86_64 |
45 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
46 | #else | |
47 | #define mod_64(x, y) ((x) % (y)) | |
48 | #endif | |
49 | ||
97222cc8 ED |
50 | #define PRId64 "d" |
51 | #define PRIx64 "llx" | |
52 | #define PRIu64 "u" | |
53 | #define PRIo64 "o" | |
54 | ||
55 | #define APIC_BUS_CYCLE_NS 1 | |
56 | ||
57 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
58 | #define apic_debug(fmt, arg...) | |
59 | ||
60 | #define APIC_LVT_NUM 6 | |
61 | /* 14 is the version for Xeon and Pentium 8.4.8*/ | |
62 | #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16)) | |
63 | #define LAPIC_MMIO_LENGTH (1 << 12) | |
64 | /* followed define is not in apicdef.h */ | |
65 | #define APIC_SHORT_MASK 0xc0000 | |
66 | #define APIC_DEST_NOSHORT 0x0 | |
67 | #define APIC_DEST_MASK 0x800 | |
68 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 69 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 ED |
70 | |
71 | #define VEC_POS(v) ((v) & (32 - 1)) | |
72 | #define REG_POS(v) (((v) >> 5) << 4) | |
ad312c7c | 73 | |
9bc5791d JK |
74 | static unsigned int min_timer_period_us = 500; |
75 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); | |
76 | ||
97222cc8 ED |
77 | static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
78 | { | |
79 | *((u32 *) (apic->regs + reg_off)) = val; | |
80 | } | |
81 | ||
82 | static inline int apic_test_and_set_vector(int vec, void *bitmap) | |
83 | { | |
84 | return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
85 | } | |
86 | ||
87 | static inline int apic_test_and_clear_vector(int vec, void *bitmap) | |
88 | { | |
89 | return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
90 | } | |
91 | ||
a0c9a822 MT |
92 | static inline int apic_test_vector(int vec, void *bitmap) |
93 | { | |
94 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
95 | } | |
96 | ||
97222cc8 ED |
97 | static inline void apic_set_vector(int vec, void *bitmap) |
98 | { | |
99 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
100 | } | |
101 | ||
102 | static inline void apic_clear_vector(int vec, void *bitmap) | |
103 | { | |
104 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
105 | } | |
106 | ||
8680b94b MT |
107 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
108 | { | |
109 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
110 | } | |
111 | ||
112 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
113 | { | |
114 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
115 | } | |
116 | ||
c5cc421b | 117 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
118 | struct static_key_deferred apic_sw_disabled __read_mostly; |
119 | ||
120 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) | |
121 | { | |
c48f1496 | 122 | if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) { |
f8c1ea10 GN |
123 | if (val & APIC_SPIV_APIC_ENABLED) |
124 | static_key_slow_dec_deferred(&apic_sw_disabled); | |
125 | else | |
126 | static_key_slow_inc(&apic_sw_disabled.key); | |
127 | } | |
128 | apic_set_reg(apic, APIC_SPIV, val); | |
129 | } | |
130 | ||
97222cc8 ED |
131 | static inline int apic_enabled(struct kvm_lapic *apic) |
132 | { | |
c48f1496 | 133 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
134 | } |
135 | ||
97222cc8 ED |
136 | #define LVT_MASK \ |
137 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
138 | ||
139 | #define LINT_MASK \ | |
140 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
141 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
142 | ||
143 | static inline int kvm_apic_id(struct kvm_lapic *apic) | |
144 | { | |
c48f1496 | 145 | return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff; |
97222cc8 ED |
146 | } |
147 | ||
1e08ec4a GN |
148 | static void recalculate_apic_map(struct kvm *kvm) |
149 | { | |
150 | struct kvm_apic_map *new, *old = NULL; | |
151 | struct kvm_vcpu *vcpu; | |
152 | int i; | |
153 | ||
154 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
155 | ||
156 | mutex_lock(&kvm->arch.apic_map_lock); | |
157 | ||
158 | if (!new) | |
159 | goto out; | |
160 | ||
161 | new->ldr_bits = 8; | |
162 | /* flat mode is default */ | |
163 | new->cid_shift = 8; | |
164 | new->cid_mask = 0; | |
165 | new->lid_mask = 0xff; | |
166 | ||
167 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
168 | struct kvm_lapic *apic = vcpu->arch.apic; | |
169 | u16 cid, lid; | |
170 | u32 ldr; | |
171 | ||
172 | if (!kvm_apic_present(vcpu)) | |
173 | continue; | |
174 | ||
175 | /* | |
176 | * All APICs have to be configured in the same mode by an OS. | |
177 | * We take advatage of this while building logical id loockup | |
178 | * table. After reset APICs are in xapic/flat mode, so if we | |
179 | * find apic with different setting we assume this is the mode | |
180 | * OS wants all apics to be in; build lookup table accordingly. | |
181 | */ | |
182 | if (apic_x2apic_mode(apic)) { | |
183 | new->ldr_bits = 32; | |
184 | new->cid_shift = 16; | |
185 | new->cid_mask = new->lid_mask = 0xffff; | |
186 | } else if (kvm_apic_sw_enabled(apic) && | |
187 | !new->cid_mask /* flat mode */ && | |
188 | kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_CLUSTER) { | |
189 | new->cid_shift = 4; | |
190 | new->cid_mask = 0xf; | |
191 | new->lid_mask = 0xf; | |
192 | } | |
193 | ||
194 | new->phys_map[kvm_apic_id(apic)] = apic; | |
195 | ||
196 | ldr = kvm_apic_get_reg(apic, APIC_LDR); | |
197 | cid = apic_cluster_id(new, ldr); | |
198 | lid = apic_logical_id(new, ldr); | |
199 | ||
200 | if (lid) | |
201 | new->logical_map[cid][ffs(lid) - 1] = apic; | |
202 | } | |
203 | out: | |
204 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
205 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
206 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
207 | mutex_unlock(&kvm->arch.apic_map_lock); | |
208 | ||
209 | if (old) | |
210 | kfree_rcu(old, rcu); | |
c7c9c56c YZ |
211 | |
212 | kvm_ioapic_make_eoibitmap_request(kvm); | |
1e08ec4a GN |
213 | } |
214 | ||
215 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) | |
216 | { | |
217 | apic_set_reg(apic, APIC_ID, id << 24); | |
218 | recalculate_apic_map(apic->vcpu->kvm); | |
219 | } | |
220 | ||
221 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
222 | { | |
223 | apic_set_reg(apic, APIC_LDR, id); | |
224 | recalculate_apic_map(apic->vcpu->kvm); | |
225 | } | |
226 | ||
97222cc8 ED |
227 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
228 | { | |
c48f1496 | 229 | return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
230 | } |
231 | ||
232 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
233 | { | |
c48f1496 | 234 | return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
235 | } |
236 | ||
a3e06bbe LJ |
237 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
238 | { | |
c48f1496 | 239 | return ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
240 | apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT); |
241 | } | |
242 | ||
97222cc8 ED |
243 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
244 | { | |
c48f1496 | 245 | return ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
246 | apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC); |
247 | } | |
248 | ||
249 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
250 | { | |
c48f1496 | 251 | return ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
252 | apic->lapic_timer.timer_mode_mask) == |
253 | APIC_LVT_TIMER_TSCDEADLINE); | |
97222cc8 ED |
254 | } |
255 | ||
cc6e462c JK |
256 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
257 | { | |
258 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
259 | } | |
260 | ||
fc61b800 GN |
261 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
262 | { | |
263 | struct kvm_lapic *apic = vcpu->arch.apic; | |
264 | struct kvm_cpuid_entry2 *feat; | |
265 | u32 v = APIC_VERSION; | |
266 | ||
c48f1496 | 267 | if (!kvm_vcpu_has_lapic(vcpu)) |
fc61b800 GN |
268 | return; |
269 | ||
270 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
271 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
272 | v |= APIC_LVR_DIRECTED_EOI; | |
273 | apic_set_reg(apic, APIC_LVR, v); | |
274 | } | |
275 | ||
f1d24831 | 276 | static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = { |
a3e06bbe | 277 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
278 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
279 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
280 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
281 | LVT_MASK /* LVTERR */ | |
282 | }; | |
283 | ||
284 | static int find_highest_vector(void *bitmap) | |
285 | { | |
ecba9a52 TY |
286 | int vec; |
287 | u32 *reg; | |
97222cc8 | 288 | |
ecba9a52 TY |
289 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
290 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
291 | reg = bitmap + REG_POS(vec); | |
292 | if (*reg) | |
293 | return fls(*reg) - 1 + vec; | |
294 | } | |
97222cc8 | 295 | |
ecba9a52 | 296 | return -1; |
97222cc8 ED |
297 | } |
298 | ||
8680b94b MT |
299 | static u8 count_vectors(void *bitmap) |
300 | { | |
ecba9a52 TY |
301 | int vec; |
302 | u32 *reg; | |
8680b94b | 303 | u8 count = 0; |
ecba9a52 TY |
304 | |
305 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
306 | reg = bitmap + REG_POS(vec); | |
307 | count += hweight32(*reg); | |
308 | } | |
309 | ||
8680b94b MT |
310 | return count; |
311 | } | |
312 | ||
97222cc8 ED |
313 | static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic) |
314 | { | |
33e4c686 | 315 | apic->irr_pending = true; |
97222cc8 ED |
316 | return apic_test_and_set_vector(vec, apic->regs + APIC_IRR); |
317 | } | |
318 | ||
33e4c686 | 319 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 320 | { |
33e4c686 | 321 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
322 | } |
323 | ||
324 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
325 | { | |
326 | int result; | |
327 | ||
c7c9c56c YZ |
328 | /* |
329 | * Note that irr_pending is just a hint. It will be always | |
330 | * true with virtual interrupt delivery enabled. | |
331 | */ | |
33e4c686 GN |
332 | if (!apic->irr_pending) |
333 | return -1; | |
334 | ||
335 | result = apic_search_irr(apic); | |
97222cc8 ED |
336 | ASSERT(result == -1 || result >= 16); |
337 | ||
338 | return result; | |
339 | } | |
340 | ||
33e4c686 GN |
341 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
342 | { | |
343 | apic->irr_pending = false; | |
344 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
345 | if (apic_search_irr(apic) != -1) | |
346 | apic->irr_pending = true; | |
347 | } | |
348 | ||
8680b94b MT |
349 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
350 | { | |
351 | if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
352 | ++apic->isr_count; | |
353 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
354 | /* | |
355 | * ISR (in service register) bit is set when injecting an interrupt. | |
356 | * The highest vector is injected. Thus the latest bit set matches | |
357 | * the highest bit in ISR. | |
358 | */ | |
359 | apic->highest_isr_cache = vec; | |
360 | } | |
361 | ||
362 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) | |
363 | { | |
364 | if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
365 | --apic->isr_count; | |
366 | BUG_ON(apic->isr_count < 0); | |
367 | apic->highest_isr_cache = -1; | |
368 | } | |
369 | ||
6e5d865c YS |
370 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
371 | { | |
6e5d865c YS |
372 | int highest_irr; |
373 | ||
33e4c686 GN |
374 | /* This may race with setting of irr in __apic_accept_irq() and |
375 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
376 | * will cause vmexit immediately and the value will be recalculated | |
377 | * on the next vmentry. | |
378 | */ | |
c48f1496 | 379 | if (!kvm_vcpu_has_lapic(vcpu)) |
6e5d865c | 380 | return 0; |
54e9818f | 381 | highest_irr = apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c YS |
382 | |
383 | return highest_irr; | |
384 | } | |
6e5d865c | 385 | |
6da7e3f6 GN |
386 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
387 | int vector, int level, int trig_mode); | |
388 | ||
58c2dde1 | 389 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq) |
97222cc8 | 390 | { |
ad312c7c | 391 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 392 | |
58c2dde1 GN |
393 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
394 | irq->level, irq->trig_mode); | |
97222cc8 ED |
395 | } |
396 | ||
ae7a2a3f MT |
397 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
398 | { | |
399 | ||
400 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
401 | sizeof(val)); | |
402 | } | |
403 | ||
404 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
405 | { | |
406 | ||
407 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
408 | sizeof(*val)); | |
409 | } | |
410 | ||
411 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
412 | { | |
413 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
414 | } | |
415 | ||
416 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
417 | { | |
418 | u8 val; | |
419 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
420 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
421 | (unsigned long long)vcpi->arch.pv_eoi.msr_val); | |
422 | return val & 0x1; | |
423 | } | |
424 | ||
425 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
426 | { | |
427 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
428 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
429 | (unsigned long long)vcpi->arch.pv_eoi.msr_val); | |
430 | return; | |
431 | } | |
432 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
433 | } | |
434 | ||
435 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
436 | { | |
437 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
438 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
439 | (unsigned long long)vcpi->arch.pv_eoi.msr_val); | |
440 | return; | |
441 | } | |
442 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
443 | } | |
444 | ||
97222cc8 ED |
445 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
446 | { | |
447 | int result; | |
c7c9c56c YZ |
448 | |
449 | /* Note that isr_count is always 1 with vid enabled */ | |
8680b94b MT |
450 | if (!apic->isr_count) |
451 | return -1; | |
452 | if (likely(apic->highest_isr_cache != -1)) | |
453 | return apic->highest_isr_cache; | |
97222cc8 ED |
454 | |
455 | result = find_highest_vector(apic->regs + APIC_ISR); | |
456 | ASSERT(result == -1 || result >= 16); | |
457 | ||
458 | return result; | |
459 | } | |
460 | ||
461 | static void apic_update_ppr(struct kvm_lapic *apic) | |
462 | { | |
3842d135 | 463 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
464 | int isr; |
465 | ||
c48f1496 GN |
466 | old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI); |
467 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
468 | isr = apic_find_highest_isr(apic); |
469 | isrv = (isr != -1) ? isr : 0; | |
470 | ||
471 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
472 | ppr = tpr & 0xff; | |
473 | else | |
474 | ppr = isrv & 0xf0; | |
475 | ||
476 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
477 | apic, ppr, isr, isrv); | |
478 | ||
3842d135 AK |
479 | if (old_ppr != ppr) { |
480 | apic_set_reg(apic, APIC_PROCPRI, ppr); | |
83bcacb1 AK |
481 | if (ppr < old_ppr) |
482 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 483 | } |
97222cc8 ED |
484 | } |
485 | ||
486 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
487 | { | |
488 | apic_set_reg(apic, APIC_TASKPRI, tpr); | |
489 | apic_update_ppr(apic); | |
490 | } | |
491 | ||
492 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest) | |
493 | { | |
343f94fe | 494 | return dest == 0xff || kvm_apic_id(apic) == dest; |
97222cc8 ED |
495 | } |
496 | ||
497 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda) | |
498 | { | |
499 | int result = 0; | |
0105d1a5 GN |
500 | u32 logical_id; |
501 | ||
502 | if (apic_x2apic_mode(apic)) { | |
c48f1496 | 503 | logical_id = kvm_apic_get_reg(apic, APIC_LDR); |
0105d1a5 GN |
504 | return logical_id & mda; |
505 | } | |
97222cc8 | 506 | |
c48f1496 | 507 | logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR)); |
97222cc8 | 508 | |
c48f1496 | 509 | switch (kvm_apic_get_reg(apic, APIC_DFR)) { |
97222cc8 ED |
510 | case APIC_DFR_FLAT: |
511 | if (logical_id & mda) | |
512 | result = 1; | |
513 | break; | |
514 | case APIC_DFR_CLUSTER: | |
515 | if (((logical_id >> 4) == (mda >> 0x4)) | |
516 | && (logical_id & mda & 0xf)) | |
517 | result = 1; | |
518 | break; | |
519 | default: | |
7712de87 | 520 | apic_debug("Bad DFR vcpu %d: %08x\n", |
c48f1496 | 521 | apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR)); |
97222cc8 ED |
522 | break; |
523 | } | |
524 | ||
525 | return result; | |
526 | } | |
527 | ||
343f94fe | 528 | int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
97222cc8 ED |
529 | int short_hand, int dest, int dest_mode) |
530 | { | |
531 | int result = 0; | |
ad312c7c | 532 | struct kvm_lapic *target = vcpu->arch.apic; |
97222cc8 ED |
533 | |
534 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 535 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
536 | target, source, dest, dest_mode, short_hand); |
537 | ||
bd371396 | 538 | ASSERT(target); |
97222cc8 ED |
539 | switch (short_hand) { |
540 | case APIC_DEST_NOSHORT: | |
343f94fe | 541 | if (dest_mode == 0) |
97222cc8 | 542 | /* Physical mode. */ |
343f94fe GN |
543 | result = kvm_apic_match_physical_addr(target, dest); |
544 | else | |
97222cc8 ED |
545 | /* Logical mode. */ |
546 | result = kvm_apic_match_logical_addr(target, dest); | |
547 | break; | |
548 | case APIC_DEST_SELF: | |
343f94fe | 549 | result = (target == source); |
97222cc8 ED |
550 | break; |
551 | case APIC_DEST_ALLINC: | |
552 | result = 1; | |
553 | break; | |
554 | case APIC_DEST_ALLBUT: | |
343f94fe | 555 | result = (target != source); |
97222cc8 ED |
556 | break; |
557 | default: | |
7712de87 JK |
558 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
559 | short_hand); | |
97222cc8 ED |
560 | break; |
561 | } | |
562 | ||
563 | return result; | |
564 | } | |
565 | ||
1e08ec4a GN |
566 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
567 | struct kvm_lapic_irq *irq, int *r) | |
568 | { | |
569 | struct kvm_apic_map *map; | |
570 | unsigned long bitmap = 1; | |
571 | struct kvm_lapic **dst; | |
572 | int i; | |
573 | bool ret = false; | |
574 | ||
575 | *r = -1; | |
576 | ||
577 | if (irq->shorthand == APIC_DEST_SELF) { | |
578 | *r = kvm_apic_set_irq(src->vcpu, irq); | |
579 | return true; | |
580 | } | |
581 | ||
582 | if (irq->shorthand) | |
583 | return false; | |
584 | ||
585 | rcu_read_lock(); | |
586 | map = rcu_dereference(kvm->arch.apic_map); | |
587 | ||
588 | if (!map) | |
589 | goto out; | |
590 | ||
591 | if (irq->dest_mode == 0) { /* physical mode */ | |
592 | if (irq->delivery_mode == APIC_DM_LOWEST || | |
593 | irq->dest_id == 0xff) | |
594 | goto out; | |
595 | dst = &map->phys_map[irq->dest_id & 0xff]; | |
596 | } else { | |
597 | u32 mda = irq->dest_id << (32 - map->ldr_bits); | |
598 | ||
599 | dst = map->logical_map[apic_cluster_id(map, mda)]; | |
600 | ||
601 | bitmap = apic_logical_id(map, mda); | |
602 | ||
603 | if (irq->delivery_mode == APIC_DM_LOWEST) { | |
604 | int l = -1; | |
605 | for_each_set_bit(i, &bitmap, 16) { | |
606 | if (!dst[i]) | |
607 | continue; | |
608 | if (l < 0) | |
609 | l = i; | |
610 | else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0) | |
611 | l = i; | |
612 | } | |
613 | ||
614 | bitmap = (l >= 0) ? 1 << l : 0; | |
615 | } | |
616 | } | |
617 | ||
618 | for_each_set_bit(i, &bitmap, 16) { | |
619 | if (!dst[i]) | |
620 | continue; | |
621 | if (*r < 0) | |
622 | *r = 0; | |
623 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq); | |
624 | } | |
625 | ||
626 | ret = true; | |
627 | out: | |
628 | rcu_read_unlock(); | |
629 | return ret; | |
630 | } | |
631 | ||
97222cc8 ED |
632 | /* |
633 | * Add a pending IRQ into lapic. | |
634 | * Return 1 if successfully added and 0 if discarded. | |
635 | */ | |
636 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
637 | int vector, int level, int trig_mode) | |
638 | { | |
6da7e3f6 | 639 | int result = 0; |
c5ec1534 | 640 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 ED |
641 | |
642 | switch (delivery_mode) { | |
97222cc8 | 643 | case APIC_DM_LOWEST: |
e1035715 GN |
644 | vcpu->arch.apic_arb_prio++; |
645 | case APIC_DM_FIXED: | |
97222cc8 ED |
646 | /* FIXME add logic for vcpu on reset */ |
647 | if (unlikely(!apic_enabled(apic))) | |
648 | break; | |
649 | ||
a5d36f82 AK |
650 | if (trig_mode) { |
651 | apic_debug("level trig mode for vector %d", vector); | |
652 | apic_set_vector(vector, apic->regs + APIC_TMR); | |
653 | } else | |
654 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
655 | ||
6da7e3f6 | 656 | result = !apic_test_and_set_irr(vector, apic); |
1000ff8d | 657 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
4da74896 | 658 | trig_mode, vector, !result); |
6da7e3f6 GN |
659 | if (!result) { |
660 | if (trig_mode) | |
661 | apic_debug("level trig mode repeatedly for " | |
662 | "vector %d", vector); | |
97222cc8 ED |
663 | break; |
664 | } | |
665 | ||
3842d135 | 666 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
d7690175 | 667 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
668 | break; |
669 | ||
670 | case APIC_DM_REMRD: | |
7712de87 | 671 | apic_debug("Ignoring delivery mode 3\n"); |
97222cc8 ED |
672 | break; |
673 | ||
674 | case APIC_DM_SMI: | |
7712de87 | 675 | apic_debug("Ignoring guest SMI\n"); |
97222cc8 | 676 | break; |
3419ffc8 | 677 | |
97222cc8 | 678 | case APIC_DM_NMI: |
6da7e3f6 | 679 | result = 1; |
3419ffc8 | 680 | kvm_inject_nmi(vcpu); |
26df99c6 | 681 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
682 | break; |
683 | ||
684 | case APIC_DM_INIT: | |
a52315e1 | 685 | if (!trig_mode || level) { |
6da7e3f6 | 686 | result = 1; |
66450a21 JK |
687 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
688 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
689 | /* make sure pending_events is visible before sending | |
690 | * the request */ | |
691 | smp_wmb(); | |
3842d135 | 692 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
693 | kvm_vcpu_kick(vcpu); |
694 | } else { | |
1b10bf31 JK |
695 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
696 | vcpu->vcpu_id); | |
c5ec1534 | 697 | } |
97222cc8 ED |
698 | break; |
699 | ||
700 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
701 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
702 | vcpu->vcpu_id, vector); | |
66450a21 JK |
703 | result = 1; |
704 | apic->sipi_vector = vector; | |
705 | /* make sure sipi_vector is visible for the receiver */ | |
706 | smp_wmb(); | |
707 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
708 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
709 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
710 | break; |
711 | ||
23930f95 JK |
712 | case APIC_DM_EXTINT: |
713 | /* | |
714 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
715 | * before NMI watchdog was enabled. Already handled by | |
716 | * kvm_apic_accept_pic_intr(). | |
717 | */ | |
718 | break; | |
719 | ||
97222cc8 ED |
720 | default: |
721 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
722 | delivery_mode); | |
723 | break; | |
724 | } | |
725 | return result; | |
726 | } | |
727 | ||
e1035715 | 728 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 729 | { |
e1035715 | 730 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
731 | } |
732 | ||
c7c9c56c YZ |
733 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
734 | { | |
735 | if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) && | |
736 | kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) { | |
737 | int trigger_mode; | |
738 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
739 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
740 | else | |
741 | trigger_mode = IOAPIC_EDGE_TRIG; | |
742 | kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode); | |
743 | } | |
744 | } | |
745 | ||
ae7a2a3f | 746 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
747 | { |
748 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
749 | |
750 | trace_kvm_eoi(apic, vector); | |
751 | ||
97222cc8 ED |
752 | /* |
753 | * Not every write EOI will has corresponding ISR, | |
754 | * one example is when Kernel check timer on setup_IO_APIC | |
755 | */ | |
756 | if (vector == -1) | |
ae7a2a3f | 757 | return vector; |
97222cc8 | 758 | |
8680b94b | 759 | apic_clear_isr(vector, apic); |
97222cc8 ED |
760 | apic_update_ppr(apic); |
761 | ||
c7c9c56c | 762 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 763 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 764 | return vector; |
97222cc8 ED |
765 | } |
766 | ||
c7c9c56c YZ |
767 | /* |
768 | * this interface assumes a trap-like exit, which has already finished | |
769 | * desired side effect including vISR and vPPR update. | |
770 | */ | |
771 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
772 | { | |
773 | struct kvm_lapic *apic = vcpu->arch.apic; | |
774 | ||
775 | trace_kvm_eoi(apic, vector); | |
776 | ||
777 | kvm_ioapic_send_eoi(apic, vector); | |
778 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
779 | } | |
780 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
781 | ||
97222cc8 ED |
782 | static void apic_send_ipi(struct kvm_lapic *apic) |
783 | { | |
c48f1496 GN |
784 | u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR); |
785 | u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 786 | struct kvm_lapic_irq irq; |
97222cc8 | 787 | |
58c2dde1 GN |
788 | irq.vector = icr_low & APIC_VECTOR_MASK; |
789 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
790 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
791 | irq.level = icr_low & APIC_INT_ASSERT; | |
792 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; | |
793 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
0105d1a5 GN |
794 | if (apic_x2apic_mode(apic)) |
795 | irq.dest_id = icr_high; | |
796 | else | |
797 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 798 | |
1000ff8d GN |
799 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
800 | ||
97222cc8 ED |
801 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
802 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
803 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n", | |
9b5843dd | 804 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 GN |
805 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
806 | irq.vector); | |
807 | ||
808 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq); | |
97222cc8 ED |
809 | } |
810 | ||
811 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
812 | { | |
b682b814 MT |
813 | ktime_t remaining; |
814 | s64 ns; | |
9da8f4e8 | 815 | u32 tmcct; |
97222cc8 ED |
816 | |
817 | ASSERT(apic != NULL); | |
818 | ||
9da8f4e8 | 819 | /* if initial count is 0, current count should also be 0 */ |
c48f1496 | 820 | if (kvm_apic_get_reg(apic, APIC_TMICT) == 0) |
9da8f4e8 KP |
821 | return 0; |
822 | ||
ace15464 | 823 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
824 | if (ktime_to_ns(remaining) < 0) |
825 | remaining = ktime_set(0, 0); | |
826 | ||
d3c7b77d MT |
827 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
828 | tmcct = div64_u64(ns, | |
829 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
830 | |
831 | return tmcct; | |
832 | } | |
833 | ||
b209749f AK |
834 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
835 | { | |
836 | struct kvm_vcpu *vcpu = apic->vcpu; | |
837 | struct kvm_run *run = vcpu->run; | |
838 | ||
a8eeb04a | 839 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 840 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
841 | run->tpr_access.is_write = write; |
842 | } | |
843 | ||
844 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
845 | { | |
846 | if (apic->vcpu->arch.tpr_access_reporting) | |
847 | __report_tpr_access(apic, write); | |
848 | } | |
849 | ||
97222cc8 ED |
850 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
851 | { | |
852 | u32 val = 0; | |
853 | ||
854 | if (offset >= LAPIC_MMIO_LENGTH) | |
855 | return 0; | |
856 | ||
857 | switch (offset) { | |
0105d1a5 GN |
858 | case APIC_ID: |
859 | if (apic_x2apic_mode(apic)) | |
860 | val = kvm_apic_id(apic); | |
861 | else | |
862 | val = kvm_apic_id(apic) << 24; | |
863 | break; | |
97222cc8 | 864 | case APIC_ARBPRI: |
7712de87 | 865 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
866 | break; |
867 | ||
868 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
869 | if (apic_lvtt_tscdeadline(apic)) |
870 | return 0; | |
871 | ||
97222cc8 ED |
872 | val = apic_get_tmcct(apic); |
873 | break; | |
4a4541a4 AK |
874 | case APIC_PROCPRI: |
875 | apic_update_ppr(apic); | |
c48f1496 | 876 | val = kvm_apic_get_reg(apic, offset); |
4a4541a4 | 877 | break; |
b209749f AK |
878 | case APIC_TASKPRI: |
879 | report_tpr_access(apic, false); | |
880 | /* fall thru */ | |
97222cc8 | 881 | default: |
c48f1496 | 882 | val = kvm_apic_get_reg(apic, offset); |
97222cc8 ED |
883 | break; |
884 | } | |
885 | ||
886 | return val; | |
887 | } | |
888 | ||
d76685c4 GH |
889 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
890 | { | |
891 | return container_of(dev, struct kvm_lapic, dev); | |
892 | } | |
893 | ||
0105d1a5 GN |
894 | static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
895 | void *data) | |
97222cc8 | 896 | { |
97222cc8 ED |
897 | unsigned char alignment = offset & 0xf; |
898 | u32 result; | |
d5b0b5b1 | 899 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 900 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
901 | |
902 | if ((alignment + len) > 4) { | |
4088bb3c GN |
903 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
904 | offset, len); | |
0105d1a5 | 905 | return 1; |
97222cc8 | 906 | } |
0105d1a5 GN |
907 | |
908 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
909 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
910 | offset); | |
0105d1a5 GN |
911 | return 1; |
912 | } | |
913 | ||
97222cc8 ED |
914 | result = __apic_read(apic, offset & ~0xf); |
915 | ||
229456fc MT |
916 | trace_kvm_apic_read(offset, result); |
917 | ||
97222cc8 ED |
918 | switch (len) { |
919 | case 1: | |
920 | case 2: | |
921 | case 4: | |
922 | memcpy(data, (char *)&result + alignment, len); | |
923 | break; | |
924 | default: | |
925 | printk(KERN_ERR "Local APIC read with len = %x, " | |
926 | "should be 1,2, or 4 instead\n", len); | |
927 | break; | |
928 | } | |
bda9020e | 929 | return 0; |
97222cc8 ED |
930 | } |
931 | ||
0105d1a5 GN |
932 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
933 | { | |
c48f1496 | 934 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
935 | addr >= apic->base_address && |
936 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
937 | } | |
938 | ||
939 | static int apic_mmio_read(struct kvm_io_device *this, | |
940 | gpa_t address, int len, void *data) | |
941 | { | |
942 | struct kvm_lapic *apic = to_lapic(this); | |
943 | u32 offset = address - apic->base_address; | |
944 | ||
945 | if (!apic_mmio_in_range(apic, address)) | |
946 | return -EOPNOTSUPP; | |
947 | ||
948 | apic_reg_read(apic, offset, len, data); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
97222cc8 ED |
953 | static void update_divide_count(struct kvm_lapic *apic) |
954 | { | |
955 | u32 tmp1, tmp2, tdcr; | |
956 | ||
c48f1496 | 957 | tdcr = kvm_apic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
958 | tmp1 = tdcr & 0xf; |
959 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 960 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
961 | |
962 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 963 | apic->divide_count); |
97222cc8 ED |
964 | } |
965 | ||
966 | static void start_apic_timer(struct kvm_lapic *apic) | |
967 | { | |
a3e06bbe | 968 | ktime_t now; |
d3c7b77d | 969 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 970 | |
a3e06bbe | 971 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 972 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 973 | now = apic->lapic_timer.timer.base->get_time(); |
c48f1496 | 974 | apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
975 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
976 | ||
977 | if (!apic->lapic_timer.period) | |
978 | return; | |
979 | /* | |
980 | * Do not allow the guest to program periodic timers with small | |
981 | * interval, since the hrtimers are not throttled by the host | |
982 | * scheduler. | |
983 | */ | |
984 | if (apic_lvtt_period(apic)) { | |
985 | s64 min_period = min_timer_period_us * 1000LL; | |
986 | ||
987 | if (apic->lapic_timer.period < min_period) { | |
988 | pr_info_ratelimited( | |
989 | "kvm: vcpu %i: requested %lld ns " | |
990 | "lapic timer period limited to %lld ns\n", | |
991 | apic->vcpu->vcpu_id, | |
992 | apic->lapic_timer.period, min_period); | |
993 | apic->lapic_timer.period = min_period; | |
994 | } | |
9bc5791d | 995 | } |
0b975a3c | 996 | |
a3e06bbe LJ |
997 | hrtimer_start(&apic->lapic_timer.timer, |
998 | ktime_add_ns(now, apic->lapic_timer.period), | |
999 | HRTIMER_MODE_ABS); | |
97222cc8 | 1000 | |
a3e06bbe | 1001 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1002 | PRIx64 ", " |
1003 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1004 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1005 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
c48f1496 | 1006 | kvm_apic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1007 | apic->lapic_timer.period, |
97222cc8 | 1008 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1009 | apic->lapic_timer.period))); |
a3e06bbe LJ |
1010 | } else if (apic_lvtt_tscdeadline(apic)) { |
1011 | /* lapic timer in tsc deadline mode */ | |
1012 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1013 | u64 ns = 0; | |
1014 | struct kvm_vcpu *vcpu = apic->vcpu; | |
cc578287 | 1015 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; |
a3e06bbe LJ |
1016 | unsigned long flags; |
1017 | ||
1018 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1019 | return; | |
1020 | ||
1021 | local_irq_save(flags); | |
1022 | ||
1023 | now = apic->lapic_timer.timer.base->get_time(); | |
886b470c | 1024 | guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc()); |
a3e06bbe LJ |
1025 | if (likely(tscdeadline > guest_tsc)) { |
1026 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1027 | do_div(ns, this_tsc_khz); | |
1028 | } | |
1029 | hrtimer_start(&apic->lapic_timer.timer, | |
1030 | ktime_add_ns(now, ns), HRTIMER_MODE_ABS); | |
1031 | ||
1032 | local_irq_restore(flags); | |
1033 | } | |
97222cc8 ED |
1034 | } |
1035 | ||
cc6e462c JK |
1036 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1037 | { | |
c48f1496 | 1038 | int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0)); |
cc6e462c JK |
1039 | |
1040 | if (apic_lvt_nmi_mode(lvt0_val)) { | |
1041 | if (!nmi_wd_enabled) { | |
1042 | apic_debug("Receive NMI setting on APIC_LVT0 " | |
1043 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
1044 | apic->vcpu->kvm->arch.vapics_in_nmi_mode++; | |
1045 | } | |
1046 | } else if (nmi_wd_enabled) | |
1047 | apic->vcpu->kvm->arch.vapics_in_nmi_mode--; | |
1048 | } | |
1049 | ||
0105d1a5 | 1050 | static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1051 | { |
0105d1a5 | 1052 | int ret = 0; |
97222cc8 | 1053 | |
0105d1a5 | 1054 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1055 | |
0105d1a5 | 1056 | switch (reg) { |
97222cc8 | 1057 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1058 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1059 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1060 | else |
1061 | ret = 1; | |
97222cc8 ED |
1062 | break; |
1063 | ||
1064 | case APIC_TASKPRI: | |
b209749f | 1065 | report_tpr_access(apic, true); |
97222cc8 ED |
1066 | apic_set_tpr(apic, val & 0xff); |
1067 | break; | |
1068 | ||
1069 | case APIC_EOI: | |
1070 | apic_set_eoi(apic); | |
1071 | break; | |
1072 | ||
1073 | case APIC_LDR: | |
0105d1a5 | 1074 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1075 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1076 | else |
1077 | ret = 1; | |
97222cc8 ED |
1078 | break; |
1079 | ||
1080 | case APIC_DFR: | |
1e08ec4a | 1081 | if (!apic_x2apic_mode(apic)) { |
0105d1a5 | 1082 | apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1083 | recalculate_apic_map(apic->vcpu->kvm); |
1084 | } else | |
0105d1a5 | 1085 | ret = 1; |
97222cc8 ED |
1086 | break; |
1087 | ||
fc61b800 GN |
1088 | case APIC_SPIV: { |
1089 | u32 mask = 0x3ff; | |
c48f1496 | 1090 | if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1091 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1092 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1093 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1094 | int i; | |
1095 | u32 lvt_val; | |
1096 | ||
1097 | for (i = 0; i < APIC_LVT_NUM; i++) { | |
c48f1496 | 1098 | lvt_val = kvm_apic_get_reg(apic, |
97222cc8 ED |
1099 | APIC_LVTT + 0x10 * i); |
1100 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, | |
1101 | lvt_val | APIC_LVT_MASKED); | |
1102 | } | |
d3c7b77d | 1103 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1104 | |
1105 | } | |
1106 | break; | |
fc61b800 | 1107 | } |
97222cc8 ED |
1108 | case APIC_ICR: |
1109 | /* No delay here, so we always clear the pending bit */ | |
1110 | apic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); | |
1111 | apic_send_ipi(apic); | |
1112 | break; | |
1113 | ||
1114 | case APIC_ICR2: | |
0105d1a5 GN |
1115 | if (!apic_x2apic_mode(apic)) |
1116 | val &= 0xff000000; | |
1117 | apic_set_reg(apic, APIC_ICR2, val); | |
97222cc8 ED |
1118 | break; |
1119 | ||
23930f95 | 1120 | case APIC_LVT0: |
cc6e462c | 1121 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1122 | case APIC_LVTTHMR: |
1123 | case APIC_LVTPC: | |
97222cc8 ED |
1124 | case APIC_LVT1: |
1125 | case APIC_LVTERR: | |
1126 | /* TODO: Check vector */ | |
c48f1496 | 1127 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1128 | val |= APIC_LVT_MASKED; |
1129 | ||
0105d1a5 GN |
1130 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1131 | apic_set_reg(apic, reg, val); | |
97222cc8 ED |
1132 | |
1133 | break; | |
1134 | ||
a3e06bbe | 1135 | case APIC_LVTT: |
c48f1496 | 1136 | if ((kvm_apic_get_reg(apic, APIC_LVTT) & |
a3e06bbe LJ |
1137 | apic->lapic_timer.timer_mode_mask) != |
1138 | (val & apic->lapic_timer.timer_mode_mask)) | |
1139 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1140 | ||
c48f1496 | 1141 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1142 | val |= APIC_LVT_MASKED; |
1143 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1144 | apic_set_reg(apic, APIC_LVTT, val); | |
1145 | break; | |
1146 | ||
97222cc8 | 1147 | case APIC_TMICT: |
a3e06bbe LJ |
1148 | if (apic_lvtt_tscdeadline(apic)) |
1149 | break; | |
1150 | ||
d3c7b77d | 1151 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 ED |
1152 | apic_set_reg(apic, APIC_TMICT, val); |
1153 | start_apic_timer(apic); | |
0105d1a5 | 1154 | break; |
97222cc8 ED |
1155 | |
1156 | case APIC_TDCR: | |
1157 | if (val & 4) | |
7712de87 | 1158 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
97222cc8 ED |
1159 | apic_set_reg(apic, APIC_TDCR, val); |
1160 | update_divide_count(apic); | |
1161 | break; | |
1162 | ||
0105d1a5 GN |
1163 | case APIC_ESR: |
1164 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1165 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1166 | ret = 1; |
1167 | } | |
1168 | break; | |
1169 | ||
1170 | case APIC_SELF_IPI: | |
1171 | if (apic_x2apic_mode(apic)) { | |
1172 | apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); | |
1173 | } else | |
1174 | ret = 1; | |
1175 | break; | |
97222cc8 | 1176 | default: |
0105d1a5 | 1177 | ret = 1; |
97222cc8 ED |
1178 | break; |
1179 | } | |
0105d1a5 GN |
1180 | if (ret) |
1181 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1182 | return ret; | |
1183 | } | |
1184 | ||
1185 | static int apic_mmio_write(struct kvm_io_device *this, | |
1186 | gpa_t address, int len, const void *data) | |
1187 | { | |
1188 | struct kvm_lapic *apic = to_lapic(this); | |
1189 | unsigned int offset = address - apic->base_address; | |
1190 | u32 val; | |
1191 | ||
1192 | if (!apic_mmio_in_range(apic, address)) | |
1193 | return -EOPNOTSUPP; | |
1194 | ||
1195 | /* | |
1196 | * APIC register must be aligned on 128-bits boundary. | |
1197 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1198 | * Refer SDM 8.4.1 | |
1199 | */ | |
1200 | if (len != 4 || (offset & 0xf)) { | |
1201 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1202 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1203 | return 0; |
0105d1a5 GN |
1204 | } |
1205 | ||
1206 | val = *(u32*)data; | |
1207 | ||
1208 | /* too common printing */ | |
1209 | if (offset != APIC_EOI) | |
1210 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1211 | "0x%x\n", __func__, offset, len, val); | |
1212 | ||
1213 | apic_reg_write(apic, offset & 0xff0, val); | |
1214 | ||
bda9020e | 1215 | return 0; |
97222cc8 ED |
1216 | } |
1217 | ||
58fbbf26 KT |
1218 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1219 | { | |
c48f1496 | 1220 | if (kvm_vcpu_has_lapic(vcpu)) |
58fbbf26 KT |
1221 | apic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
1222 | } | |
1223 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1224 | ||
83d4c286 YZ |
1225 | /* emulate APIC access in a trap manner */ |
1226 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1227 | { | |
1228 | u32 val = 0; | |
1229 | ||
1230 | /* hw has done the conditional check and inst decode */ | |
1231 | offset &= 0xff0; | |
1232 | ||
1233 | apic_reg_read(vcpu->arch.apic, offset, 4, &val); | |
1234 | ||
1235 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1236 | apic_reg_write(vcpu->arch.apic, offset, val); | |
1237 | } | |
1238 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1239 | ||
d589444e | 1240 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1241 | { |
f8c1ea10 GN |
1242 | struct kvm_lapic *apic = vcpu->arch.apic; |
1243 | ||
ad312c7c | 1244 | if (!vcpu->arch.apic) |
97222cc8 ED |
1245 | return; |
1246 | ||
f8c1ea10 | 1247 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1248 | |
c5cc421b GN |
1249 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1250 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1251 | ||
c48f1496 | 1252 | if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED)) |
f8c1ea10 | 1253 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1254 | |
f8c1ea10 GN |
1255 | if (apic->regs) |
1256 | free_page((unsigned long)apic->regs); | |
1257 | ||
1258 | kfree(apic); | |
97222cc8 ED |
1259 | } |
1260 | ||
1261 | /* | |
1262 | *---------------------------------------------------------------------- | |
1263 | * LAPIC interface | |
1264 | *---------------------------------------------------------------------- | |
1265 | */ | |
1266 | ||
a3e06bbe LJ |
1267 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1268 | { | |
1269 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1270 | |
c48f1496 | 1271 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1272 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1273 | return 0; |
1274 | ||
1275 | return apic->lapic_timer.tscdeadline; | |
1276 | } | |
1277 | ||
1278 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1279 | { | |
1280 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1281 | |
c48f1496 | 1282 | if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1283 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1284 | return; |
1285 | ||
1286 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1287 | apic->lapic_timer.tscdeadline = data; | |
1288 | start_apic_timer(apic); | |
1289 | } | |
1290 | ||
97222cc8 ED |
1291 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1292 | { | |
ad312c7c | 1293 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1294 | |
c48f1496 | 1295 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1296 | return; |
54e9818f | 1297 | |
b93463aa | 1298 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
c48f1496 | 1299 | | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1300 | } |
1301 | ||
1302 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1303 | { | |
97222cc8 ED |
1304 | u64 tpr; |
1305 | ||
c48f1496 | 1306 | if (!kvm_vcpu_has_lapic(vcpu)) |
97222cc8 | 1307 | return 0; |
54e9818f | 1308 | |
c48f1496 | 1309 | tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1310 | |
1311 | return (tpr & 0xf0) >> 4; | |
1312 | } | |
1313 | ||
1314 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1315 | { | |
8d14695f | 1316 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1317 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1318 | |
1319 | if (!apic) { | |
1320 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1321 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1322 | return; |
1323 | } | |
c5af89b6 | 1324 | |
c5cc421b GN |
1325 | /* update jump label if enable bit changes */ |
1326 | if ((vcpu->arch.apic_base ^ value) & MSR_IA32_APICBASE_ENABLE) { | |
1327 | if (value & MSR_IA32_APICBASE_ENABLE) | |
1328 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1329 | else | |
1330 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1331 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1332 | } |
1333 | ||
c5af89b6 | 1334 | if (!kvm_vcpu_is_bsp(apic->vcpu)) |
97222cc8 ED |
1335 | value &= ~MSR_IA32_APICBASE_BSP; |
1336 | ||
ad312c7c | 1337 | vcpu->arch.apic_base = value; |
8d14695f YZ |
1338 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1339 | if (value & X2APIC_ENABLE) { | |
1340 | u32 id = kvm_apic_id(apic); | |
1341 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
1342 | kvm_apic_set_ldr(apic, ldr); | |
1343 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); | |
1344 | } else | |
1345 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1346 | } |
8d14695f | 1347 | |
ad312c7c | 1348 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1349 | MSR_IA32_APICBASE_BASE; |
1350 | ||
1351 | /* with FSB delivery interrupt, we can restart APIC functionality */ | |
1352 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1353 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1354 | |
1355 | } | |
1356 | ||
c5ec1534 | 1357 | void kvm_lapic_reset(struct kvm_vcpu *vcpu) |
97222cc8 ED |
1358 | { |
1359 | struct kvm_lapic *apic; | |
1360 | int i; | |
1361 | ||
b8688d51 | 1362 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1363 | |
1364 | ASSERT(vcpu); | |
ad312c7c | 1365 | apic = vcpu->arch.apic; |
97222cc8 ED |
1366 | ASSERT(apic != NULL); |
1367 | ||
1368 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1369 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1370 | |
1e08ec4a | 1371 | kvm_apic_set_id(apic, vcpu->vcpu_id); |
fc61b800 | 1372 | kvm_apic_set_version(apic->vcpu); |
97222cc8 ED |
1373 | |
1374 | for (i = 0; i < APIC_LVT_NUM; i++) | |
1375 | apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
40487c68 QH |
1376 | apic_set_reg(apic, APIC_LVT0, |
1377 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); | |
97222cc8 ED |
1378 | |
1379 | apic_set_reg(apic, APIC_DFR, 0xffffffffU); | |
f8c1ea10 | 1380 | apic_set_spiv(apic, 0xff); |
97222cc8 | 1381 | apic_set_reg(apic, APIC_TASKPRI, 0); |
1e08ec4a | 1382 | kvm_apic_set_ldr(apic, 0); |
97222cc8 ED |
1383 | apic_set_reg(apic, APIC_ESR, 0); |
1384 | apic_set_reg(apic, APIC_ICR, 0); | |
1385 | apic_set_reg(apic, APIC_ICR2, 0); | |
1386 | apic_set_reg(apic, APIC_TDCR, 0); | |
1387 | apic_set_reg(apic, APIC_TMICT, 0); | |
1388 | for (i = 0; i < 8; i++) { | |
1389 | apic_set_reg(apic, APIC_IRR + 0x10 * i, 0); | |
1390 | apic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1391 | apic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
1392 | } | |
c7c9c56c YZ |
1393 | apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm); |
1394 | apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm); | |
8680b94b | 1395 | apic->highest_isr_cache = -1; |
b33ac88b | 1396 | update_divide_count(apic); |
d3c7b77d | 1397 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1398 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1399 | kvm_lapic_set_base(vcpu, |
1400 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1401 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1402 | apic_update_ppr(apic); |
1403 | ||
e1035715 | 1404 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1405 | vcpu->arch.apic_attention = 0; |
e1035715 | 1406 | |
97222cc8 | 1407 | apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1408 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1409 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1410 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1411 | } |
1412 | ||
97222cc8 ED |
1413 | /* |
1414 | *---------------------------------------------------------------------- | |
1415 | * timer interface | |
1416 | *---------------------------------------------------------------------- | |
1417 | */ | |
1b9778da | 1418 | |
2a6eac96 | 1419 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1420 | { |
d3c7b77d | 1421 | return apic_lvtt_period(apic); |
97222cc8 ED |
1422 | } |
1423 | ||
3d80840d MT |
1424 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1425 | { | |
54e9818f | 1426 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1427 | |
c48f1496 | 1428 | if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) && |
54e9818f GN |
1429 | apic_lvt_enabled(apic, APIC_LVTT)) |
1430 | return atomic_read(&apic->lapic_timer.pending); | |
3d80840d MT |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
89342082 | 1435 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1436 | { |
c48f1496 | 1437 | u32 reg = kvm_apic_get_reg(apic, lvt_type); |
23930f95 | 1438 | int vector, mode, trig_mode; |
23930f95 | 1439 | |
c48f1496 | 1440 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1441 | vector = reg & APIC_VECTOR_MASK; |
1442 | mode = reg & APIC_MODE_MASK; | |
1443 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
1444 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode); | |
1445 | } | |
1446 | return 0; | |
1447 | } | |
1b9778da | 1448 | |
8fdb2351 | 1449 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1450 | { |
8fdb2351 JK |
1451 | struct kvm_lapic *apic = vcpu->arch.apic; |
1452 | ||
1453 | if (apic) | |
1454 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1455 | } |
1456 | ||
d76685c4 GH |
1457 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1458 | .read = apic_mmio_read, | |
1459 | .write = apic_mmio_write, | |
d76685c4 GH |
1460 | }; |
1461 | ||
e9d90d47 AK |
1462 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1463 | { | |
1464 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 AK |
1465 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
1466 | struct kvm_vcpu *vcpu = apic->vcpu; | |
e9d90d47 AK |
1467 | wait_queue_head_t *q = &vcpu->wq; |
1468 | ||
1469 | /* | |
1470 | * There is a race window between reading and incrementing, but we do | |
1471 | * not care about potentially losing timer events in the !reinject | |
1472 | * case anyway. Note: KVM_REQ_PENDING_TIMER is implicitly checked | |
1473 | * in vcpu_enter_guest. | |
1474 | */ | |
2a6eac96 | 1475 | if (!atomic_read(&ktimer->pending)) { |
e9d90d47 AK |
1476 | atomic_inc(&ktimer->pending); |
1477 | /* FIXME: this code should not know anything about vcpus */ | |
1478 | kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu); | |
1479 | } | |
1480 | ||
1481 | if (waitqueue_active(q)) | |
1482 | wake_up_interruptible(q); | |
1483 | ||
2a6eac96 | 1484 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1485 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1486 | return HRTIMER_RESTART; | |
1487 | } else | |
1488 | return HRTIMER_NORESTART; | |
1489 | } | |
1490 | ||
97222cc8 ED |
1491 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1492 | { | |
1493 | struct kvm_lapic *apic; | |
1494 | ||
1495 | ASSERT(vcpu != NULL); | |
1496 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1497 | ||
1498 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1499 | if (!apic) | |
1500 | goto nomem; | |
1501 | ||
ad312c7c | 1502 | vcpu->arch.apic = apic; |
97222cc8 | 1503 | |
afc20184 TY |
1504 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1505 | if (!apic->regs) { | |
97222cc8 ED |
1506 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1507 | vcpu->vcpu_id); | |
d589444e | 1508 | goto nomem_free_apic; |
97222cc8 | 1509 | } |
97222cc8 ED |
1510 | apic->vcpu = vcpu; |
1511 | ||
d3c7b77d MT |
1512 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
1513 | HRTIMER_MODE_ABS); | |
e9d90d47 | 1514 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1515 | |
c5cc421b GN |
1516 | /* |
1517 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1518 | * thinking that APIC satet has changed. | |
1519 | */ | |
1520 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1521 | kvm_lapic_set_base(vcpu, |
1522 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1523 | |
f8c1ea10 | 1524 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
c5ec1534 | 1525 | kvm_lapic_reset(vcpu); |
d76685c4 | 1526 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1527 | |
1528 | return 0; | |
d589444e RR |
1529 | nomem_free_apic: |
1530 | kfree(apic); | |
97222cc8 | 1531 | nomem: |
97222cc8 ED |
1532 | return -ENOMEM; |
1533 | } | |
97222cc8 ED |
1534 | |
1535 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1536 | { | |
ad312c7c | 1537 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1538 | int highest_irr; |
1539 | ||
c48f1496 | 1540 | if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic)) |
97222cc8 ED |
1541 | return -1; |
1542 | ||
6e5d865c | 1543 | apic_update_ppr(apic); |
97222cc8 ED |
1544 | highest_irr = apic_find_highest_irr(apic); |
1545 | if ((highest_irr == -1) || | |
c48f1496 | 1546 | ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1547 | return -1; |
1548 | return highest_irr; | |
1549 | } | |
1550 | ||
40487c68 QH |
1551 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1552 | { | |
c48f1496 | 1553 | u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1554 | int r = 0; |
1555 | ||
c48f1496 | 1556 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1557 | r = 1; |
1558 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1559 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1560 | r = 1; | |
40487c68 QH |
1561 | return r; |
1562 | } | |
1563 | ||
1b9778da ED |
1564 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1565 | { | |
ad312c7c | 1566 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1567 | |
c48f1496 | 1568 | if (!kvm_vcpu_has_lapic(vcpu)) |
54e9818f GN |
1569 | return; |
1570 | ||
1571 | if (atomic_read(&apic->lapic_timer.pending) > 0) { | |
8fdb2351 | 1572 | if (kvm_apic_local_deliver(apic, APIC_LVTT)) |
d3c7b77d | 1573 | atomic_dec(&apic->lapic_timer.pending); |
1b9778da ED |
1574 | } |
1575 | } | |
1576 | ||
97222cc8 ED |
1577 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1578 | { | |
1579 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1580 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1581 | |
1582 | if (vector == -1) | |
1583 | return -1; | |
1584 | ||
8680b94b | 1585 | apic_set_isr(vector, apic); |
97222cc8 ED |
1586 | apic_update_ppr(apic); |
1587 | apic_clear_irr(vector, apic); | |
1588 | return vector; | |
1589 | } | |
96ad2cc6 | 1590 | |
64eb0620 GN |
1591 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1592 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1593 | { |
ad312c7c | 1594 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1595 | |
5dbc8f3f | 1596 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1597 | /* set SPIV separately to get count of SW disabled APICs right */ |
1598 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1599 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1600 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1601 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1602 | kvm_apic_set_version(vcpu); |
1603 | ||
96ad2cc6 | 1604 | apic_update_ppr(apic); |
d3c7b77d | 1605 | hrtimer_cancel(&apic->lapic_timer.timer); |
96ad2cc6 ED |
1606 | update_divide_count(apic); |
1607 | start_apic_timer(apic); | |
6e24a6ef | 1608 | apic->irr_pending = true; |
c7c9c56c YZ |
1609 | apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ? |
1610 | 1 : count_vectors(apic->regs + APIC_ISR); | |
8680b94b | 1611 | apic->highest_isr_cache = -1; |
c7c9c56c | 1612 | kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic)); |
3842d135 | 1613 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
96ad2cc6 | 1614 | } |
a3d7f85f | 1615 | |
2f52d58c | 1616 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 1617 | { |
a3d7f85f ED |
1618 | struct hrtimer *timer; |
1619 | ||
c48f1496 | 1620 | if (!kvm_vcpu_has_lapic(vcpu)) |
a3d7f85f ED |
1621 | return; |
1622 | ||
54e9818f | 1623 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 1624 | if (hrtimer_cancel(timer)) |
beb20d52 | 1625 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
a3d7f85f | 1626 | } |
b93463aa | 1627 | |
ae7a2a3f MT |
1628 | /* |
1629 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
1630 | * | |
1631 | * Detect whether guest triggered PV EOI since the | |
1632 | * last entry. If yes, set EOI on guests's behalf. | |
1633 | * Clear PV EOI in guest memory in any case. | |
1634 | */ | |
1635 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
1636 | struct kvm_lapic *apic) | |
1637 | { | |
1638 | bool pending; | |
1639 | int vector; | |
1640 | /* | |
1641 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
1642 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
1643 | * | |
1644 | * KVM_APIC_PV_EOI_PENDING is unset: | |
1645 | * -> host disabled PV EOI. | |
1646 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
1647 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
1648 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
1649 | * -> host enabled PV EOI, guest executed EOI. | |
1650 | */ | |
1651 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
1652 | pending = pv_eoi_get_pending(vcpu); | |
1653 | /* | |
1654 | * Clear pending bit in any case: it will be set again on vmentry. | |
1655 | * While this might not be ideal from performance point of view, | |
1656 | * this makes sure pv eoi is only enabled when we know it's safe. | |
1657 | */ | |
1658 | pv_eoi_clr_pending(vcpu); | |
1659 | if (pending) | |
1660 | return; | |
1661 | vector = apic_set_eoi(apic); | |
1662 | trace_kvm_pv_eoi(apic, vector); | |
1663 | } | |
1664 | ||
b93463aa AK |
1665 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
1666 | { | |
1667 | u32 data; | |
1668 | void *vapic; | |
1669 | ||
ae7a2a3f MT |
1670 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
1671 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
1672 | ||
41383771 | 1673 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1674 | return; |
1675 | ||
8fd75e12 | 1676 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page); |
b93463aa | 1677 | data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)); |
8fd75e12 | 1678 | kunmap_atomic(vapic); |
b93463aa AK |
1679 | |
1680 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
1681 | } | |
1682 | ||
ae7a2a3f MT |
1683 | /* |
1684 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
1685 | * | |
1686 | * Detect whether it's safe to enable PV EOI and | |
1687 | * if yes do so. | |
1688 | */ | |
1689 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
1690 | struct kvm_lapic *apic) | |
1691 | { | |
1692 | if (!pv_eoi_enabled(vcpu) || | |
1693 | /* IRR set or many bits in ISR: could be nested. */ | |
1694 | apic->irr_pending || | |
1695 | /* Cache not set: could be safe but we don't bother. */ | |
1696 | apic->highest_isr_cache == -1 || | |
1697 | /* Need EOI to update ioapic. */ | |
1698 | kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) { | |
1699 | /* | |
1700 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
1701 | * so we need not do anything here. | |
1702 | */ | |
1703 | return; | |
1704 | } | |
1705 | ||
1706 | pv_eoi_set_pending(apic->vcpu); | |
1707 | } | |
1708 | ||
b93463aa AK |
1709 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
1710 | { | |
1711 | u32 data, tpr; | |
1712 | int max_irr, max_isr; | |
ae7a2a3f | 1713 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa AK |
1714 | void *vapic; |
1715 | ||
ae7a2a3f MT |
1716 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
1717 | ||
41383771 | 1718 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
1719 | return; |
1720 | ||
c48f1496 | 1721 | tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
1722 | max_irr = apic_find_highest_irr(apic); |
1723 | if (max_irr < 0) | |
1724 | max_irr = 0; | |
1725 | max_isr = apic_find_highest_isr(apic); | |
1726 | if (max_isr < 0) | |
1727 | max_isr = 0; | |
1728 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
1729 | ||
8fd75e12 | 1730 | vapic = kmap_atomic(vcpu->arch.apic->vapic_page); |
b93463aa | 1731 | *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data; |
8fd75e12 | 1732 | kunmap_atomic(vapic); |
b93463aa AK |
1733 | } |
1734 | ||
1735 | void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) | |
1736 | { | |
b93463aa | 1737 | vcpu->arch.apic->vapic_addr = vapic_addr; |
41383771 GN |
1738 | if (vapic_addr) |
1739 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); | |
1740 | else | |
1741 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); | |
b93463aa | 1742 | } |
0105d1a5 GN |
1743 | |
1744 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
1745 | { | |
1746 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1747 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
1748 | ||
1749 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1750 | return 1; | |
1751 | ||
1752 | /* if this is ICR write vector before command */ | |
1753 | if (msr == 0x830) | |
1754 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
1755 | return apic_reg_write(apic, reg, (u32)data); | |
1756 | } | |
1757 | ||
1758 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
1759 | { | |
1760 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1761 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
1762 | ||
1763 | if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic)) | |
1764 | return 1; | |
1765 | ||
1766 | if (apic_reg_read(apic, reg, 4, &low)) | |
1767 | return 1; | |
1768 | if (msr == 0x830) | |
1769 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
1770 | ||
1771 | *data = (((u64)high) << 32) | low; | |
1772 | ||
1773 | return 0; | |
1774 | } | |
10388a07 GN |
1775 | |
1776 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
1777 | { | |
1778 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1779 | ||
c48f1496 | 1780 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
1781 | return 1; |
1782 | ||
1783 | /* if this is ICR write vector before command */ | |
1784 | if (reg == APIC_ICR) | |
1785 | apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); | |
1786 | return apic_reg_write(apic, reg, (u32)data); | |
1787 | } | |
1788 | ||
1789 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
1790 | { | |
1791 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1792 | u32 low, high = 0; | |
1793 | ||
c48f1496 | 1794 | if (!kvm_vcpu_has_lapic(vcpu)) |
10388a07 GN |
1795 | return 1; |
1796 | ||
1797 | if (apic_reg_read(apic, reg, 4, &low)) | |
1798 | return 1; | |
1799 | if (reg == APIC_ICR) | |
1800 | apic_reg_read(apic, APIC_ICR2, 4, &high); | |
1801 | ||
1802 | *data = (((u64)high) << 32) | low; | |
1803 | ||
1804 | return 0; | |
1805 | } | |
ae7a2a3f MT |
1806 | |
1807 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
1808 | { | |
1809 | u64 addr = data & ~KVM_MSR_ENABLED; | |
1810 | if (!IS_ALIGNED(addr, 4)) | |
1811 | return 1; | |
1812 | ||
1813 | vcpu->arch.pv_eoi.msr_val = data; | |
1814 | if (!pv_eoi_enabled(vcpu)) | |
1815 | return 0; | |
1816 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
1817 | addr); | |
1818 | } | |
c5cc421b | 1819 | |
66450a21 JK |
1820 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
1821 | { | |
1822 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1823 | unsigned int sipi_vector; | |
1824 | ||
1825 | if (!kvm_vcpu_has_lapic(vcpu)) | |
1826 | return; | |
1827 | ||
1828 | if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { | |
1829 | kvm_lapic_reset(vcpu); | |
1830 | kvm_vcpu_reset(vcpu); | |
1831 | if (kvm_vcpu_is_bsp(apic->vcpu)) | |
1832 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
1833 | else | |
1834 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
1835 | } | |
1836 | if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events) && | |
1837 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { | |
1838 | /* evaluate pending_events before reading the vector */ | |
1839 | smp_rmb(); | |
1840 | sipi_vector = apic->sipi_vector; | |
1841 | pr_debug("vcpu %d received sipi with vector # %x\n", | |
1842 | vcpu->vcpu_id, sipi_vector); | |
1843 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
1844 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
1845 | } | |
1846 | } | |
1847 | ||
c5cc421b GN |
1848 | void kvm_lapic_init(void) |
1849 | { | |
1850 | /* do not patch jump label more than once per second */ | |
1851 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 1852 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 1853 | } |