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kvm/x86: per-vcpu apicv deactivation support
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
3548a259
RK		 136/* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
3b5a5ffa
RK		 144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
1e08ec4a
GN		 158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
173beedc
NA		 171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
25995e5b 174 u32 ldr, aid;
1e08ec4a 175
df04d1d1
RK		 176 if (!kvm_apic_present(vcpu))
177 continue;
178
25995e5b 179 aid = kvm_apic_id(apic);
1e08ec4a 180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
1e08ec4a 181
25995e5b
RK		 182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
3548a259 184
3b5a5ffa
RK		 185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
3548a259
RK		 196 continue;
197
3b5a5ffa
RK		 198 apic_logical_id(new, ldr, &cid, &lid);
199
25995e5b 200 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
c7c9c56c 211
b053b2ae 212 kvm_make_scan_ioapic_request(kvm);
1e08ec4a
GN		 213}
214
1e1b6c26
NA		 215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
e462755c 217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 218
219 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
1e1b6c26
NA		 224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
1e08ec4a
GN		 231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
257b9a5f
RK		 243static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
244{
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
246
247 apic_set_reg(apic, APIC_ID, id << 24);
248 apic_set_reg(apic, APIC_LDR, ldr);
249 recalculate_apic_map(apic->vcpu->kvm);
250}
251
97222cc8
ED		 252static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
253{
c48f1496 254 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 255}
256
257static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
258{
c48f1496 259 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 260}
261
a3e06bbe
LJ		 262static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
263{
f30ebc31 264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 265}
266
97222cc8
ED		 267static inline int apic_lvtt_period(struct kvm_lapic *apic)
268{
f30ebc31 269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 270}
271
272static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
273{
f30ebc31 274 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 275}
276
cc6e462c
JK		 277static inline int apic_lvt_nmi_mode(u32 lvt_val)
278{
279 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
280}
281
fc61b800
GN		 282void kvm_apic_set_version(struct kvm_vcpu *vcpu)
283{
284 struct kvm_lapic *apic = vcpu->arch.apic;
285 struct kvm_cpuid_entry2 *feat;
286 u32 v = APIC_VERSION;
287
c48f1496 288 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 289 return;
290
291 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293 v |= APIC_LVR_DIRECTED_EOI;
294 apic_set_reg(apic, APIC_LVR, v);
295}
296
f1d24831 297static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 298 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 299 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
300 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
301 LINT_MASK, LINT_MASK, /* LVT0-1 */
302 LVT_MASK /* LVTERR */
303};
304
305static int find_highest_vector(void *bitmap)
306{
ecba9a52
TY		 307 int vec;
308 u32 *reg;
97222cc8 309
ecba9a52
TY		 310 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
313 if (*reg)
314 return fls(*reg) - 1 + vec;
315 }
97222cc8 316
ecba9a52 317 return -1;
97222cc8
ED		 318}
319
8680b94b
MT		 320static u8 count_vectors(void *bitmap)
321{
ecba9a52
TY		 322 int vec;
323 u32 *reg;
8680b94b 324 u8 count = 0;
ecba9a52
TY		 325
326 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327 reg = bitmap + REG_POS(vec);
328 count += hweight32(*reg);
329 }
330
8680b94b
MT		 331 return count;
332}
333
705699a1 334void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 335{
336 u32 i, pir_val;
a20ed54d
YZ		 337
338 for (i = 0; i <= 7; i++) {
339 pir_val = xchg(&pir[i], 0);
340 if (pir_val)
705699a1 341 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 342 }
343}
705699a1
WV		 344EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
345
346void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
347{
348 struct kvm_lapic *apic = vcpu->arch.apic;
349
350 __kvm_apic_update_irr(pir, apic->regs);
c77f3fab
RK		 351
352 kvm_make_request(KVM_REQ_EVENT, vcpu);
705699a1 353}
a20ed54d
YZ		 354EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
355
11f5cc05 356static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 357{
11f5cc05 358 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 359 /*
360 * irr_pending must be true if any interrupt is pending; set it after
361 * APIC_IRR to avoid race with apic_clear_irr
362 */
363 apic->irr_pending = true;
97222cc8
ED		 364}
365
33e4c686 366static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 367{
33e4c686 368 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 369}
370
371static inline int apic_find_highest_irr(struct kvm_lapic *apic)
372{
373 int result;
374
c7c9c56c
YZ		 375 /*
376 * Note that irr_pending is just a hint. It will be always
377 * true with virtual interrupt delivery enabled.
378 */
33e4c686
GN		 379 if (!apic->irr_pending)
380 return -1;
381
d62caabb
AS		 382 if (apic->vcpu->arch.apicv_active)
383 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 384 result = apic_search_irr(apic);
97222cc8
ED		 385 ASSERT(result == -1 || result >= 16);
386
387 return result;
388}
389
33e4c686
GN		 390static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
391{
56cc2406
WL		 392 struct kvm_vcpu *vcpu;
393
394 vcpu = apic->vcpu;
395
d62caabb 396 if (unlikely(vcpu->arch.apicv_active)) {
56cc2406 397 /* try to update RVI */
f210f757 398 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 399 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 400 } else {
401 apic->irr_pending = false;
402 apic_clear_vector(vec, apic->regs + APIC_IRR);
403 if (apic_search_irr(apic) != -1)
404 apic->irr_pending = true;
56cc2406 405 }
33e4c686
GN		 406}
407
8680b94b
MT		 408static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
409{
56cc2406
WL		 410 struct kvm_vcpu *vcpu;
411
412 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
413 return;
414
415 vcpu = apic->vcpu;
fc57ac2c 416
8680b94b 417 /*
56cc2406
WL		 418 * With APIC virtualization enabled, all caching is disabled
419 * because the processor can modify ISR under the hood. Instead
420 * just set SVI.
8680b94b 421 */
d62caabb 422 if (unlikely(vcpu->arch.apicv_active))
56cc2406
WL		 423 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
424 else {
425 ++apic->isr_count;
426 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
427 /*
428 * ISR (in service register) bit is set when injecting an interrupt.
429 * The highest vector is injected. Thus the latest bit set matches
430 * the highest bit in ISR.
431 */
432 apic->highest_isr_cache = vec;
433 }
8680b94b
MT		 434}
435
fc57ac2c
PB		 436static inline int apic_find_highest_isr(struct kvm_lapic *apic)
437{
438 int result;
439
440 /*
441 * Note that isr_count is always 1, and highest_isr_cache
442 * is always -1, with APIC virtualization enabled.
443 */
444 if (!apic->isr_count)
445 return -1;
446 if (likely(apic->highest_isr_cache != -1))
447 return apic->highest_isr_cache;
448
449 result = find_highest_vector(apic->regs + APIC_ISR);
450 ASSERT(result == -1 || result >= 16);
451
452 return result;
453}
454
8680b94b
MT		 455static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
456{
fc57ac2c
PB		 457 struct kvm_vcpu *vcpu;
458 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
459 return;
460
461 vcpu = apic->vcpu;
462
463 /*
464 * We do get here for APIC virtualization enabled if the guest
465 * uses the Hyper-V APIC enlightenment. In this case we may need
466 * to trigger a new interrupt delivery by writing the SVI field;
467 * on the other hand isr_count and highest_isr_cache are unused
468 * and must be left alone.
469 */
d62caabb 470 if (unlikely(vcpu->arch.apicv_active))
fc57ac2c
PB		 471 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
472 apic_find_highest_isr(apic));
473 else {
8680b94b 474 --apic->isr_count;
fc57ac2c
PB		 475 BUG_ON(apic->isr_count < 0);
476 apic->highest_isr_cache = -1;
477 }
8680b94b
MT		 478}
479
6e5d865c
YS		 480int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
481{
6e5d865c
YS		 482 int highest_irr;
483
33e4c686
GN		 484 /* This may race with setting of irr in __apic_accept_irq() and
485 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
486 * will cause vmexit immediately and the value will be recalculated
487 * on the next vmentry.
488 */
c48f1496 489 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 490 return 0;
54e9818f 491 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 492
493 return highest_irr;
494}
6e5d865c 495
6da7e3f6 496static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 497 int vector, int level, int trig_mode,
498 unsigned long *dest_map);
6da7e3f6 499
b4f2225c
YZ		 500int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
501 unsigned long *dest_map)
97222cc8 502{
ad312c7c 503 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 504
58c2dde1 505 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 506 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 507}
508
ae7a2a3f
MT		 509static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
510{
511
512 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
513 sizeof(val));
514}
515
516static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
517{
518
519 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
520 sizeof(*val));
521}
522
523static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
524{
525 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
526}
527
528static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
529{
530 u8 val;
531 if (pv_eoi_get_user(vcpu, &val) < 0)
532 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 533 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 534 return val & 0x1;
535}
536
537static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
538{
539 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
540 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 541 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 542 return;
543 }
544 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
545}
546
547static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
548{
549 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
550 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 551 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 552 return;
553 }
554 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
555}
556
97222cc8
ED		 557static void apic_update_ppr(struct kvm_lapic *apic)
558{
3842d135 559 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 560 int isr;
561
c48f1496
GN		 562 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
563 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 564 isr = apic_find_highest_isr(apic);
565 isrv = (isr != -1) ? isr : 0;
566
567 if ((tpr & 0xf0) >= (isrv & 0xf0))
568 ppr = tpr & 0xff;
569 else
570 ppr = isrv & 0xf0;
571
572 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
573 apic, ppr, isr, isrv);
574
3842d135
AK		 575 if (old_ppr != ppr) {
576 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 577 if (ppr < old_ppr)
578 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 579 }
97222cc8
ED		 580}
581
582static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
583{
584 apic_set_reg(apic, APIC_TASKPRI, tpr);
585 apic_update_ppr(apic);
586}
587
03d2249e 588static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 589{
03d2249e
RK		 590 if (apic_x2apic_mode(apic))
591 return mda == X2APIC_BROADCAST;
592
593 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 594}
595
03d2249e 596static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 597{
03d2249e
RK		 598 if (kvm_apic_broadcast(apic, mda))
599 return true;
600
601 if (apic_x2apic_mode(apic))
602 return mda == kvm_apic_id(apic);
603
604 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 605}
606
52c233a4 607static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 608{
0105d1a5
GN		 609 u32 logical_id;
610
394457a9 611 if (kvm_apic_broadcast(apic, mda))
9368b567 612 return true;
394457a9 613
9368b567 614 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 615
9368b567 616 if (apic_x2apic_mode(apic))
8a395363
RK		 617 return ((logical_id >> 16) == (mda >> 16))
618 && (logical_id & mda & 0xffff) != 0;
97222cc8 619
9368b567 620 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 621 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 622
c48f1496 623 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 624 case APIC_DFR_FLAT:
9368b567 625 return (logical_id & mda) != 0;
97222cc8 626 case APIC_DFR_CLUSTER:
9368b567
RK		 627 return ((logical_id >> 4) == (mda >> 4))
628 && (logical_id & mda & 0xf) != 0;
97222cc8 629 default:
7712de87 630 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 631 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 632 return false;
97222cc8 633 }
97222cc8
ED		 634}
635
03d2249e
RK		 636/* KVM APIC implementation has two quirks
637 * - dest always begins at 0 while xAPIC MDA has offset 24,
638 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
639 */
640static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
641 struct kvm_lapic *target)
642{
643 bool ipi = source != NULL;
644 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
645
646 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
647 return X2APIC_BROADCAST;
648
649 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
650}
651
52c233a4 652bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 653 int short_hand, unsigned int dest, int dest_mode)
97222cc8 654{
ad312c7c 655 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 656 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 657
658 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 659 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 660 target, source, dest, dest_mode, short_hand);
661
bd371396 662 ASSERT(target);
97222cc8
ED		 663 switch (short_hand) {
664 case APIC_DEST_NOSHORT:
3697f302 665 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 666 return kvm_apic_match_physical_addr(target, mda);
343f94fe 667 else
03d2249e 668 return kvm_apic_match_logical_addr(target, mda);
97222cc8 669 case APIC_DEST_SELF:
9368b567 670 return target == source;
97222cc8 671 case APIC_DEST_ALLINC:
9368b567 672 return true;
97222cc8 673 case APIC_DEST_ALLBUT:
9368b567 674 return target != source;
97222cc8 675 default:
7712de87
JK		 676 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
677 short_hand);
9368b567 678 return false;
97222cc8 679 }
97222cc8
ED		 680}
681
1e08ec4a 682bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 683 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 684{
685 struct kvm_apic_map *map;
686 unsigned long bitmap = 1;
687 struct kvm_lapic **dst;
688 int i;
bea15428 689 bool ret, x2apic_ipi;
1e08ec4a
GN		 690
691 *r = -1;
692
693 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 694 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 695 return true;
696 }
697
698 if (irq->shorthand)
699 return false;
700
bea15428 701 x2apic_ipi = src && apic_x2apic_mode(src);
9ea369b0
RK		 702 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
703 return false;
704
bea15428 705 ret = true;
1e08ec4a
GN		 706 rcu_read_lock();
707 map = rcu_dereference(kvm->arch.apic_map);
708
bea15428
PB		 709 if (!map) {
710 ret = false;
1e08ec4a 711 goto out;
bea15428 712 }
698f9755 713
3697f302 714 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 715 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
716 goto out;
717
718 dst = &map->phys_map[irq->dest_id];
1e08ec4a 719 } else {
3548a259
RK		 720 u16 cid;
721
722 if (!kvm_apic_logical_map_valid(map)) {
723 ret = false;
724 goto out;
725 }
726
3b5a5ffa 727 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
45c3094a
RK		 728
729 if (cid >= ARRAY_SIZE(map->logical_map))
730 goto out;
1e08ec4a 731
45c3094a 732 dst = map->logical_map[cid];
1e08ec4a 733
d1ebdbf9 734 if (kvm_lowest_prio_delivery(irq)) {
1e08ec4a
GN		 735 int l = -1;
736 for_each_set_bit(i, &bitmap, 16) {
737 if (!dst[i])
738 continue;
739 if (l < 0)
740 l = i;
741 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
742 l = i;
743 }
744
745 bitmap = (l >= 0) ? 1 << l : 0;
746 }
747 }
748
749 for_each_set_bit(i, &bitmap, 16) {
750 if (!dst[i])
751 continue;
752 if (*r < 0)
753 *r = 0;
b4f2225c 754 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 755 }
1e08ec4a
GN		 756out:
757 rcu_read_unlock();
758 return ret;
759}
760
8feb4a04
FW		 761bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
762 struct kvm_vcpu **dest_vcpu)
763{
764 struct kvm_apic_map *map;
765 bool ret = false;
766 struct kvm_lapic *dst = NULL;
767
768 if (irq->shorthand)
769 return false;
770
771 rcu_read_lock();
772 map = rcu_dereference(kvm->arch.apic_map);
773
774 if (!map)
775 goto out;
776
777 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
778 if (irq->dest_id == 0xFF)
779 goto out;
780
781 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
782 goto out;
783
784 dst = map->phys_map[irq->dest_id];
785 if (dst && kvm_apic_present(dst->vcpu))
786 *dest_vcpu = dst->vcpu;
787 else
788 goto out;
789 } else {
790 u16 cid;
791 unsigned long bitmap = 1;
792 int i, r = 0;
793
794 if (!kvm_apic_logical_map_valid(map))
795 goto out;
796
797 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
798
799 if (cid >= ARRAY_SIZE(map->logical_map))
800 goto out;
801
802 for_each_set_bit(i, &bitmap, 16) {
803 dst = map->logical_map[cid][i];
804 if (++r == 2)
805 goto out;
806 }
807
808 if (dst && kvm_apic_present(dst->vcpu))
809 *dest_vcpu = dst->vcpu;
810 else
811 goto out;
812 }
813
814 ret = true;
815out:
816 rcu_read_unlock();
817 return ret;
818}
819
97222cc8
ED		 820/*
821 * Add a pending IRQ into lapic.
822 * Return 1 if successfully added and 0 if discarded.
823 */
824static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 825 int vector, int level, int trig_mode,
826 unsigned long *dest_map)
97222cc8 827{
6da7e3f6 828 int result = 0;
c5ec1534 829 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 830
a183b638
PB		 831 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
832 trig_mode, vector);
97222cc8 833 switch (delivery_mode) {
97222cc8 834 case APIC_DM_LOWEST:
e1035715
GN		 835 vcpu->arch.apic_arb_prio++;
836 case APIC_DM_FIXED:
bdaffe1d
PB		 837 if (unlikely(trig_mode && !level))
838 break;
839
97222cc8
ED		 840 /* FIXME add logic for vcpu on reset */
841 if (unlikely(!apic_enabled(apic)))
842 break;
843
11f5cc05
JK		 844 result = 1;
845
b4f2225c
YZ		 846 if (dest_map)
847 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 848
bdaffe1d
PB		 849 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
850 if (trig_mode)
851 apic_set_vector(vector, apic->regs + APIC_TMR);
852 else
853 apic_clear_vector(vector, apic->regs + APIC_TMR);
854 }
855
d62caabb 856 if (vcpu->arch.apicv_active)
5a71785d 857 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 858 else {
859 apic_set_irr(vector, apic);
5a71785d
YZ		 860
861 kvm_make_request(KVM_REQ_EVENT, vcpu);
862 kvm_vcpu_kick(vcpu);
863 }
97222cc8
ED		 864 break;
865
866 case APIC_DM_REMRD:
24d2166b
R		 867 result = 1;
868 vcpu->arch.pv.pv_unhalted = 1;
869 kvm_make_request(KVM_REQ_EVENT, vcpu);
870 kvm_vcpu_kick(vcpu);
97222cc8
ED		 871 break;
872
873 case APIC_DM_SMI:
64d60670
PB		 874 result = 1;
875 kvm_make_request(KVM_REQ_SMI, vcpu);
876 kvm_vcpu_kick(vcpu);
97222cc8 877 break;
3419ffc8 878
97222cc8 879 case APIC_DM_NMI:
6da7e3f6 880 result = 1;
3419ffc8 881 kvm_inject_nmi(vcpu);
26df99c6 882 kvm_vcpu_kick(vcpu);
97222cc8
ED		 883 break;
884
885 case APIC_DM_INIT:
a52315e1 886 if (!trig_mode || level) {
6da7e3f6 887 result = 1;
66450a21
JK		 888 /* assumes that there are only KVM_APIC_INIT/SIPI */
889 apic->pending_events = (1UL << KVM_APIC_INIT);
890 /* make sure pending_events is visible before sending
891 * the request */
892 smp_wmb();
3842d135 893 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 894 kvm_vcpu_kick(vcpu);
895 } else {
1b10bf31
JK		 896 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
897 vcpu->vcpu_id);
c5ec1534 898 }
97222cc8
ED		 899 break;
900
901 case APIC_DM_STARTUP:
1b10bf31
JK		 902 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
903 vcpu->vcpu_id, vector);
66450a21
JK		 904 result = 1;
905 apic->sipi_vector = vector;
906 /* make sure sipi_vector is visible for the receiver */
907 smp_wmb();
908 set_bit(KVM_APIC_SIPI, &apic->pending_events);
909 kvm_make_request(KVM_REQ_EVENT, vcpu);
910 kvm_vcpu_kick(vcpu);
97222cc8
ED		 911 break;
912
23930f95
JK		 913 case APIC_DM_EXTINT:
914 /*
915 * Should only be called by kvm_apic_local_deliver() with LVT0,
916 * before NMI watchdog was enabled. Already handled by
917 * kvm_apic_accept_pic_intr().
918 */
919 break;
920
97222cc8
ED		 921 default:
922 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
923 delivery_mode);
924 break;
925 }
926 return result;
927}
928
e1035715 929int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 930{
e1035715 931 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 932}
933
3bb345f3
PB		 934static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
935{
6308630b 936 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
3bb345f3
PB		 937}
938
c7c9c56c
YZ		 939static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
940{
7543a635
SR		 941 int trigger_mode;
942
943 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
944 if (!kvm_ioapic_handles_vector(apic, vector))
945 return;
3bb345f3 946
7543a635
SR		 947 /* Request a KVM exit to inform the userspace IOAPIC. */
948 if (irqchip_split(apic->vcpu->kvm)) {
949 apic->vcpu->arch.pending_ioapic_eoi = vector;
950 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
951 return;
c7c9c56c 952 }
7543a635
SR		 953
954 if (apic_test_vector(vector, apic->regs + APIC_TMR))
955 trigger_mode = IOAPIC_LEVEL_TRIG;
956 else
957 trigger_mode = IOAPIC_EDGE_TRIG;
958
959 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 960}
961
ae7a2a3f 962static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 963{
964 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 965
966 trace_kvm_eoi(apic, vector);
967
97222cc8
ED		 968 /*
969 * Not every write EOI will has corresponding ISR,
970 * one example is when Kernel check timer on setup_IO_APIC
971 */
972 if (vector == -1)
ae7a2a3f 973 return vector;
97222cc8 974
8680b94b 975 apic_clear_isr(vector, apic);
97222cc8
ED		 976 apic_update_ppr(apic);
977
c7c9c56c 978 kvm_ioapic_send_eoi(apic, vector);
3842d135 979 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 980 return vector;
97222cc8
ED		 981}
982
c7c9c56c
YZ		 983/*
984 * this interface assumes a trap-like exit, which has already finished
985 * desired side effect including vISR and vPPR update.
986 */
987void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
988{
989 struct kvm_lapic *apic = vcpu->arch.apic;
990
991 trace_kvm_eoi(apic, vector);
992
993 kvm_ioapic_send_eoi(apic, vector);
994 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
995}
996EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
997
97222cc8
ED		 998static void apic_send_ipi(struct kvm_lapic *apic)
999{
c48f1496
GN		 1000 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
1001 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 1002 struct kvm_lapic_irq irq;
97222cc8 1003
58c2dde1
GN		 1004 irq.vector = icr_low & APIC_VECTOR_MASK;
1005 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1006 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 1007 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 1008 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1009 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 1010 irq.msi_redir_hint = false;
0105d1a5
GN		 1011 if (apic_x2apic_mode(apic))
1012 irq.dest_id = icr_high;
1013 else
1014 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 1015
1000ff8d
GN		 1016 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1017
97222cc8
ED		 1018 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1019 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 1020 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1021 "msi_redir_hint 0x%x\n",
9b5843dd 1022 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 1023 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 1024 irq.vector, irq.msi_redir_hint);
58c2dde1 1025
b4f2225c 1026 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 1027}
1028
1029static u32 apic_get_tmcct(struct kvm_lapic *apic)
1030{
b682b814
MT		 1031 ktime_t remaining;
1032 s64 ns;
9da8f4e8 1033 u32 tmcct;
97222cc8
ED		 1034
1035 ASSERT(apic != NULL);
1036
9da8f4e8 1037 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 1038 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
1039 apic->lapic_timer.period == 0)
9da8f4e8
KP		 1040 return 0;
1041
ace15464 1042 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 1043 if (ktime_to_ns(remaining) < 0)
1044 remaining = ktime_set(0, 0);
1045
d3c7b77d
MT		 1046 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1047 tmcct = div64_u64(ns,
1048 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 1049
1050 return tmcct;
1051}
1052
b209749f
AK		 1053static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1054{
1055 struct kvm_vcpu *vcpu = apic->vcpu;
1056 struct kvm_run *run = vcpu->run;
1057
a8eeb04a 1058 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 1059 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 1060 run->tpr_access.is_write = write;
1061}
1062
1063static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1064{
1065 if (apic->vcpu->arch.tpr_access_reporting)
1066 __report_tpr_access(apic, write);
1067}
1068
97222cc8
ED		 1069static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1070{
1071 u32 val = 0;
1072
1073 if (offset >= LAPIC_MMIO_LENGTH)
1074 return 0;
1075
1076 switch (offset) {
0105d1a5
GN		 1077 case APIC_ID:
1078 if (apic_x2apic_mode(apic))
1079 val = kvm_apic_id(apic);
1080 else
1081 val = kvm_apic_id(apic) << 24;
1082 break;
97222cc8 1083 case APIC_ARBPRI:
7712de87 1084 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 1085 break;
1086
1087 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1088 if (apic_lvtt_tscdeadline(apic))
1089 return 0;
1090
97222cc8
ED		 1091 val = apic_get_tmcct(apic);
1092 break;
4a4541a4
AK		 1093 case APIC_PROCPRI:
1094 apic_update_ppr(apic);
c48f1496 1095 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1096 break;
b209749f
AK		 1097 case APIC_TASKPRI:
1098 report_tpr_access(apic, false);
1099 /* fall thru */
97222cc8 1100 default:
c48f1496 1101 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1102 break;
1103 }
1104
1105 return val;
1106}
1107
d76685c4
GH		 1108static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1109{
1110 return container_of(dev, struct kvm_lapic, dev);
1111}
1112
0105d1a5
GN		 1113static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1114 void *data)
97222cc8 1115{
97222cc8
ED		 1116 unsigned char alignment = offset & 0xf;
1117 u32 result;
d5b0b5b1 1118 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1119 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1120
1121 if ((alignment + len) > 4) {
4088bb3c
GN		 1122 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1123 offset, len);
0105d1a5 1124 return 1;
97222cc8 1125 }
0105d1a5
GN		 1126
1127 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1128 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1129 offset);
0105d1a5
GN		 1130 return 1;
1131 }
1132
97222cc8
ED		 1133 result = __apic_read(apic, offset & ~0xf);
1134
229456fc
MT		 1135 trace_kvm_apic_read(offset, result);
1136
97222cc8
ED		 1137 switch (len) {
1138 case 1:
1139 case 2:
1140 case 4:
1141 memcpy(data, (char *)&result + alignment, len);
1142 break;
1143 default:
1144 printk(KERN_ERR "Local APIC read with len = %x, "
1145 "should be 1,2, or 4 instead\n", len);
1146 break;
1147 }
bda9020e 1148 return 0;
97222cc8
ED		 1149}
1150
0105d1a5
GN		 1151static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1152{
c48f1496 1153 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1154 addr >= apic->base_address &&
1155 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1156}
1157
e32edf4f 1158static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1159 gpa_t address, int len, void *data)
1160{
1161 struct kvm_lapic *apic = to_lapic(this);
1162 u32 offset = address - apic->base_address;
1163
1164 if (!apic_mmio_in_range(apic, address))
1165 return -EOPNOTSUPP;
1166
1167 apic_reg_read(apic, offset, len, data);
1168
1169 return 0;
1170}
1171
97222cc8
ED		 1172static void update_divide_count(struct kvm_lapic *apic)
1173{
1174 u32 tmp1, tmp2, tdcr;
1175
c48f1496 1176 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1177 tmp1 = tdcr & 0xf;
1178 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1179 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1180
1181 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1182 apic->divide_count);
97222cc8
ED		 1183}
1184
b6ac0695
RK		 1185static void apic_update_lvtt(struct kvm_lapic *apic)
1186{
1187 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1188 apic->lapic_timer.timer_mode_mask;
1189
1190 if (apic->lapic_timer.timer_mode != timer_mode) {
1191 apic->lapic_timer.timer_mode = timer_mode;
1192 hrtimer_cancel(&apic->lapic_timer.timer);
1193 }
1194}
1195
5d87db71
RK		 1196static void apic_timer_expired(struct kvm_lapic *apic)
1197{
1198 struct kvm_vcpu *vcpu = apic->vcpu;
1199 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1200 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1201
5d87db71
RK		 1202 if (atomic_read(&apic->lapic_timer.pending))
1203 return;
1204
1205 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1206 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1207
1208 if (waitqueue_active(q))
1209 wake_up_interruptible(q);
d0659d94
MT		 1210
1211 if (apic_lvtt_tscdeadline(apic))
1212 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1213}
1214
1215/*
1216 * On APICv, this test will cause a busy wait
1217 * during a higher-priority task.
1218 */
1219
1220static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1221{
1222 struct kvm_lapic *apic = vcpu->arch.apic;
1223 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1224
1225 if (kvm_apic_hw_enabled(apic)) {
1226 int vec = reg & APIC_VECTOR_MASK;
f9339860 1227 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1228
d62caabb 1229 if (vcpu->arch.apicv_active)
f9339860
MT		 1230 bitmap = apic->regs + APIC_IRR;
1231
1232 if (apic_test_vector(vec, bitmap))
1233 return true;
d0659d94
MT		 1234 }
1235 return false;
1236}
1237
1238void wait_lapic_expire(struct kvm_vcpu *vcpu)
1239{
1240 struct kvm_lapic *apic = vcpu->arch.apic;
1241 u64 guest_tsc, tsc_deadline;
1242
1243 if (!kvm_vcpu_has_lapic(vcpu))
1244 return;
1245
1246 if (apic->lapic_timer.expired_tscdeadline == 0)
1247 return;
1248
1249 if (!lapic_timer_int_injected(vcpu))
1250 return;
1251
1252 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1253 apic->lapic_timer.expired_tscdeadline = 0;
4ba76538 1254 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6c19b753 1255 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1256
1257 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1258 if (guest_tsc < tsc_deadline)
1259 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1260}
1261
97222cc8
ED		 1262static void start_apic_timer(struct kvm_lapic *apic)
1263{
a3e06bbe 1264 ktime_t now;
d0659d94 1265
d3c7b77d 1266 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1267
a3e06bbe 1268 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1269 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1270 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1271 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1272 * APIC_BUS_CYCLE_NS * apic->divide_count;
1273
1274 if (!apic->lapic_timer.period)
1275 return;
1276 /*
1277 * Do not allow the guest to program periodic timers with small
1278 * interval, since the hrtimers are not throttled by the host
1279 * scheduler.
1280 */
1281 if (apic_lvtt_period(apic)) {
1282 s64 min_period = min_timer_period_us * 1000LL;
1283
1284 if (apic->lapic_timer.period < min_period) {
1285 pr_info_ratelimited(
1286 "kvm: vcpu %i: requested %lld ns "
1287 "lapic timer period limited to %lld ns\n",
1288 apic->vcpu->vcpu_id,
1289 apic->lapic_timer.period, min_period);
1290 apic->lapic_timer.period = min_period;
1291 }
9bc5791d 1292 }
0b975a3c 1293
a3e06bbe
LJ		 1294 hrtimer_start(&apic->lapic_timer.timer,
1295 ktime_add_ns(now, apic->lapic_timer.period),
1296 HRTIMER_MODE_ABS);
97222cc8 1297
a3e06bbe 1298 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1299 PRIx64 ", "
1300 "timer initial count 0x%x, period %lldns, "
b8688d51 1301 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1302 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1303 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1304 apic->lapic_timer.period,
97222cc8 1305 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1306 apic->lapic_timer.period)));
a3e06bbe
LJ		 1307 } else if (apic_lvtt_tscdeadline(apic)) {
1308 /* lapic timer in tsc deadline mode */
1309 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1310 u64 ns = 0;
d0659d94 1311 ktime_t expire;
a3e06bbe 1312 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1313 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1314 unsigned long flags;
1315
1316 if (unlikely(!tscdeadline || !this_tsc_khz))
1317 return;
1318
1319 local_irq_save(flags);
1320
1321 now = apic->lapic_timer.timer.base->get_time();
4ba76538 1322 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
a3e06bbe
LJ		 1323 if (likely(tscdeadline > guest_tsc)) {
1324 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1325 do_div(ns, this_tsc_khz);
d0659d94
MT		 1326 expire = ktime_add_ns(now, ns);
1327 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1328 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1329 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1330 } else
1331 apic_timer_expired(apic);
a3e06bbe
LJ		 1332
1333 local_irq_restore(flags);
1334 }
97222cc8
ED		 1335}
1336
cc6e462c
JK		 1337static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1338{
59fd1323 1339 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1340
59fd1323
RK		 1341 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1342 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1343 if (lvt0_in_nmi_mode) {
cc6e462c
JK		 1344 apic_debug("Receive NMI setting on APIC_LVT0 "
1345 "for cpu %d\n", apic->vcpu->vcpu_id);
42720138 1346 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1347 } else
1348 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1349 }
cc6e462c
JK		 1350}
1351
0105d1a5 1352static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1353{
0105d1a5 1354 int ret = 0;
97222cc8 1355
0105d1a5 1356 trace_kvm_apic_write(reg, val);
97222cc8 1357
0105d1a5 1358 switch (reg) {
97222cc8 1359 case APIC_ID: /* Local APIC ID */
0105d1a5 1360 if (!apic_x2apic_mode(apic))
1e08ec4a 1361 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1362 else
1363 ret = 1;
97222cc8
ED		 1364 break;
1365
1366 case APIC_TASKPRI:
b209749f 1367 report_tpr_access(apic, true);
97222cc8
ED		 1368 apic_set_tpr(apic, val & 0xff);
1369 break;
1370
1371 case APIC_EOI:
1372 apic_set_eoi(apic);
1373 break;
1374
1375 case APIC_LDR:
0105d1a5 1376 if (!apic_x2apic_mode(apic))
1e08ec4a 1377 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1378 else
1379 ret = 1;
97222cc8
ED		 1380 break;
1381
1382 case APIC_DFR:
1e08ec4a 1383 if (!apic_x2apic_mode(apic)) {
0105d1a5 1384 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1385 recalculate_apic_map(apic->vcpu->kvm);
1386 } else
0105d1a5 1387 ret = 1;
97222cc8
ED		 1388 break;
1389
fc61b800
GN		 1390 case APIC_SPIV: {
1391 u32 mask = 0x3ff;
c48f1496 1392 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1393 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1394 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1395 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1396 int i;
1397 u32 lvt_val;
1398
1399 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1400 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1401 APIC_LVTT + 0x10 * i);
1402 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1403 lvt_val | APIC_LVT_MASKED);
1404 }
b6ac0695 1405 apic_update_lvtt(apic);
d3c7b77d 1406 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1407
1408 }
1409 break;
fc61b800 1410 }
97222cc8
ED		 1411 case APIC_ICR:
1412 /* No delay here, so we always clear the pending bit */
1413 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1414 apic_send_ipi(apic);
1415 break;
1416
1417 case APIC_ICR2:
0105d1a5
GN		 1418 if (!apic_x2apic_mode(apic))
1419 val &= 0xff000000;
1420 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1421 break;
1422
23930f95 1423 case APIC_LVT0:
cc6e462c 1424 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1425 case APIC_LVTTHMR:
1426 case APIC_LVTPC:
97222cc8
ED		 1427 case APIC_LVT1:
1428 case APIC_LVTERR:
1429 /* TODO: Check vector */
c48f1496 1430 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1431 val |= APIC_LVT_MASKED;
1432
0105d1a5
GN		 1433 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1434 apic_set_reg(apic, reg, val);
97222cc8
ED		 1435
1436 break;
1437
b6ac0695 1438 case APIC_LVTT:
c48f1496 1439 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1440 val |= APIC_LVT_MASKED;
1441 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1442 apic_set_reg(apic, APIC_LVTT, val);
b6ac0695 1443 apic_update_lvtt(apic);
a3e06bbe
LJ		 1444 break;
1445
97222cc8 1446 case APIC_TMICT:
a3e06bbe
LJ		 1447 if (apic_lvtt_tscdeadline(apic))
1448 break;
1449
d3c7b77d 1450 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1451 apic_set_reg(apic, APIC_TMICT, val);
1452 start_apic_timer(apic);
0105d1a5 1453 break;
97222cc8
ED		 1454
1455 case APIC_TDCR:
1456 if (val & 4)
7712de87 1457 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1458 apic_set_reg(apic, APIC_TDCR, val);
1459 update_divide_count(apic);
1460 break;
1461
0105d1a5
GN		 1462 case APIC_ESR:
1463 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1464 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1465 ret = 1;
1466 }
1467 break;
1468
1469 case APIC_SELF_IPI:
1470 if (apic_x2apic_mode(apic)) {
1471 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1472 } else
1473 ret = 1;
1474 break;
97222cc8 1475 default:
0105d1a5 1476 ret = 1;
97222cc8
ED		 1477 break;
1478 }
0105d1a5
GN		 1479 if (ret)
1480 apic_debug("Local APIC Write to read-only register %x\n", reg);
1481 return ret;
1482}
1483
e32edf4f 1484static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1485 gpa_t address, int len, const void *data)
1486{
1487 struct kvm_lapic *apic = to_lapic(this);
1488 unsigned int offset = address - apic->base_address;
1489 u32 val;
1490
1491 if (!apic_mmio_in_range(apic, address))
1492 return -EOPNOTSUPP;
1493
1494 /*
1495 * APIC register must be aligned on 128-bits boundary.
1496 * 32/64/128 bits registers must be accessed thru 32 bits.
1497 * Refer SDM 8.4.1
1498 */
1499 if (len != 4 || (offset & 0xf)) {
1500 /* Don't shout loud, $infamous_os would cause only noise. */
1501 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1502 return 0;
0105d1a5
GN		 1503 }
1504
1505 val = *(u32*)data;
1506
1507 /* too common printing */
1508 if (offset != APIC_EOI)
1509 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1510 "0x%x\n", __func__, offset, len, val);
1511
1512 apic_reg_write(apic, offset & 0xff0, val);
1513
bda9020e 1514 return 0;
97222cc8
ED		 1515}
1516
58fbbf26
KT		 1517void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1518{
c48f1496 1519 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1520 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1521}
1522EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1523
83d4c286
YZ		 1524/* emulate APIC access in a trap manner */
1525void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1526{
1527 u32 val = 0;
1528
1529 /* hw has done the conditional check and inst decode */
1530 offset &= 0xff0;
1531
1532 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1533
1534 /* TODO: optimize to just emulate side effect w/o one more write */
1535 apic_reg_write(vcpu->arch.apic, offset, val);
1536}
1537EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1538
d589444e 1539void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1540{
f8c1ea10
GN		 1541 struct kvm_lapic *apic = vcpu->arch.apic;
1542
ad312c7c 1543 if (!vcpu->arch.apic)
97222cc8
ED		 1544 return;
1545
f8c1ea10 1546 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1547
c5cc421b
GN		 1548 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1549 static_key_slow_dec_deferred(&apic_hw_disabled);
1550
e462755c 1551 if (!apic->sw_enabled)
f8c1ea10 1552 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1553
f8c1ea10
GN		 1554 if (apic->regs)
1555 free_page((unsigned long)apic->regs);
1556
1557 kfree(apic);
97222cc8
ED		 1558}
1559
1560/*
1561 *----------------------------------------------------------------------
1562 * LAPIC interface
1563 *----------------------------------------------------------------------
1564 */
1565
a3e06bbe
LJ		 1566u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1567{
1568 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1569
c48f1496 1570 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1571 apic_lvtt_period(apic))
a3e06bbe
LJ		 1572 return 0;
1573
1574 return apic->lapic_timer.tscdeadline;
1575}
1576
1577void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1578{
1579 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1580
c48f1496 1581 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1582 apic_lvtt_period(apic))
a3e06bbe
LJ		 1583 return;
1584
1585 hrtimer_cancel(&apic->lapic_timer.timer);
1586 apic->lapic_timer.tscdeadline = data;
1587 start_apic_timer(apic);
1588}
1589
97222cc8
ED		 1590void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1591{
ad312c7c 1592 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1593
c48f1496 1594 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1595 return;
54e9818f 1596
b93463aa 1597 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1598 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1599}
1600
1601u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1602{
97222cc8
ED		 1603 u64 tpr;
1604
c48f1496 1605 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1606 return 0;
54e9818f 1607
c48f1496 1608 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1609
1610 return (tpr & 0xf0) >> 4;
1611}
1612
1613void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1614{
8d14695f 1615 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1616 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1617
1618 if (!apic) {
1619 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1620 vcpu->arch.apic_base = value;
97222cc8
ED		 1621 return;
1622 }
c5af89b6 1623
e66d2ae7
JK		 1624 vcpu->arch.apic_base = value;
1625
c5cc421b 1626 /* update jump label if enable bit changes */
0dce7cd6 1627 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1628 if (value & MSR_IA32_APICBASE_ENABLE)
1629 static_key_slow_dec_deferred(&apic_hw_disabled);
1630 else
1631 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1632 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1633 }
1634
8d14695f
YZ		 1635 if ((old_value ^ value) & X2APIC_ENABLE) {
1636 if (value & X2APIC_ENABLE) {
257b9a5f 1637 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
8d14695f
YZ		 1638 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1639 } else
1640 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1641 }
8d14695f 1642
ad312c7c 1643 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1644 MSR_IA32_APICBASE_BASE;
1645
db324fe6
NA		 1646 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1647 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1648 pr_warn_once("APIC base relocation is unsupported by KVM");
1649
97222cc8
ED		 1650 /* with FSB delivery interrupt, we can restart APIC functionality */
1651 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1652 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1653
1654}
1655
d28bc9dd 1656void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8
ED		 1657{
1658 struct kvm_lapic *apic;
1659 int i;
1660
b8688d51 1661 apic_debug("%s\n", __func__);
97222cc8
ED		 1662
1663 ASSERT(vcpu);
ad312c7c 1664 apic = vcpu->arch.apic;
97222cc8
ED		 1665 ASSERT(apic != NULL);
1666
1667 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1668 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1669
d28bc9dd
NA		 1670 if (!init_event)
1671 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1672 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1673
1674 for (i = 0; i < APIC_LVT_NUM; i++)
1675 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 1676 apic_update_lvtt(apic);
0da029ed 1677 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
90de4a18
NA		 1678 apic_set_reg(apic, APIC_LVT0,
1679 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
59fd1323 1680 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
97222cc8
ED		 1681
1682 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1683 apic_set_spiv(apic, 0xff);
97222cc8 1684 apic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 1685 if (!apic_x2apic_mode(apic))
1686 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1687 apic_set_reg(apic, APIC_ESR, 0);
1688 apic_set_reg(apic, APIC_ICR, 0);
1689 apic_set_reg(apic, APIC_ICR2, 0);
1690 apic_set_reg(apic, APIC_TDCR, 0);
1691 apic_set_reg(apic, APIC_TMICT, 0);
1692 for (i = 0; i < 8; i++) {
1693 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1694 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1695 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1696 }
d62caabb
AS		 1697 apic->irr_pending = vcpu->arch.apicv_active;
1698 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
8680b94b 1699 apic->highest_isr_cache = -1;
b33ac88b 1700 update_divide_count(apic);
d3c7b77d 1701 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1702 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1703 kvm_lapic_set_base(vcpu,
1704 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1705 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1706 apic_update_ppr(apic);
1707
e1035715 1708 vcpu->arch.apic_arb_prio = 0;
41383771 1709 vcpu->arch.apic_attention = 0;
e1035715 1710
98eff52a 1711 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1712 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1713 vcpu, kvm_apic_id(apic),
ad312c7c 1714 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1715}
1716
97222cc8
ED		 1717/*
1718 *----------------------------------------------------------------------
1719 * timer interface
1720 *----------------------------------------------------------------------
1721 */
1b9778da 1722
2a6eac96 1723static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1724{
d3c7b77d 1725 return apic_lvtt_period(apic);
97222cc8
ED		 1726}
1727
3d80840d
MT		 1728int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1729{
54e9818f 1730 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1731
c48f1496 1732 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1733 apic_lvt_enabled(apic, APIC_LVTT))
1734 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1735
1736 return 0;
1737}
1738
89342082 1739int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1740{
c48f1496 1741 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1742 int vector, mode, trig_mode;
23930f95 1743
c48f1496 1744 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1745 vector = reg & APIC_VECTOR_MASK;
1746 mode = reg & APIC_MODE_MASK;
1747 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1748 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1749 NULL);
23930f95
JK		 1750 }
1751 return 0;
1752}
1b9778da 1753
8fdb2351 1754void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1755{
8fdb2351
JK		 1756 struct kvm_lapic *apic = vcpu->arch.apic;
1757
1758 if (apic)
1759 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1760}
1761
d76685c4
GH		 1762static const struct kvm_io_device_ops apic_mmio_ops = {
1763 .read = apic_mmio_read,
1764 .write = apic_mmio_write,
d76685c4
GH		 1765};
1766
e9d90d47
AK		 1767static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1768{
1769 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1770 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1771
5d87db71 1772 apic_timer_expired(apic);
e9d90d47 1773
2a6eac96 1774 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1775 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1776 return HRTIMER_RESTART;
1777 } else
1778 return HRTIMER_NORESTART;
1779}
1780
97222cc8
ED		 1781int kvm_create_lapic(struct kvm_vcpu *vcpu)
1782{
1783 struct kvm_lapic *apic;
1784
1785 ASSERT(vcpu != NULL);
1786 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1787
1788 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1789 if (!apic)
1790 goto nomem;
1791
ad312c7c 1792 vcpu->arch.apic = apic;
97222cc8 1793
afc20184
TY		 1794 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1795 if (!apic->regs) {
97222cc8
ED		 1796 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1797 vcpu->vcpu_id);
d589444e 1798 goto nomem_free_apic;
97222cc8 1799 }
97222cc8
ED		 1800 apic->vcpu = vcpu;
1801
d3c7b77d
MT		 1802 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1803 HRTIMER_MODE_ABS);
e9d90d47 1804 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1805
c5cc421b
GN		 1806 /*
1807 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1808 * thinking that APIC satet has changed.
1809 */
1810 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1811 kvm_lapic_set_base(vcpu,
1812 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1813
f8c1ea10 1814 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d28bc9dd 1815 kvm_lapic_reset(vcpu, false);
d76685c4 1816 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1817
1818 return 0;
d589444e
RR		 1819nomem_free_apic:
1820 kfree(apic);
97222cc8 1821nomem:
97222cc8
ED		 1822 return -ENOMEM;
1823}
97222cc8
ED		 1824
1825int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1826{
ad312c7c 1827 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1828 int highest_irr;
1829
c48f1496 1830 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1831 return -1;
1832
6e5d865c 1833 apic_update_ppr(apic);
97222cc8
ED		 1834 highest_irr = apic_find_highest_irr(apic);
1835 if ((highest_irr == -1) ||
c48f1496 1836 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1837 return -1;
1838 return highest_irr;
1839}
1840
40487c68
QH		 1841int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1842{
c48f1496 1843 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1844 int r = 0;
1845
c48f1496 1846 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1847 r = 1;
1848 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1849 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1850 r = 1;
40487c68
QH		 1851 return r;
1852}
1853
1b9778da
ED		 1854void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1855{
ad312c7c 1856 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1857
c48f1496 1858 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1859 return;
1860
1861 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1862 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1863 if (apic_lvtt_tscdeadline(apic))
1864 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1865 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1866 }
1867}
1868
97222cc8
ED		 1869int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1870{
1871 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1872 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1873
1874 if (vector == -1)
1875 return -1;
1876
56cc2406
WL		 1877 /*
1878 * We get here even with APIC virtualization enabled, if doing
1879 * nested virtualization and L1 runs with the "acknowledge interrupt
1880 * on exit" mode. Then we cannot inject the interrupt via RVI,
1881 * because the process would deliver it through the IDT.
1882 */
1883
8680b94b 1884 apic_set_isr(vector, apic);
97222cc8
ED		 1885 apic_update_ppr(apic);
1886 apic_clear_irr(vector, apic);
1887 return vector;
1888}
96ad2cc6 1889
64eb0620
GN		 1890void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1891 struct kvm_lapic_state *s)
96ad2cc6 1892{
ad312c7c 1893 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1894
5dbc8f3f 1895 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1896 /* set SPIV separately to get count of SW disabled APICs right */
1897 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1898 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1899 /* call kvm_apic_set_id() to put apic into apic_map */
1900 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1901 kvm_apic_set_version(vcpu);
1902
96ad2cc6 1903 apic_update_ppr(apic);
d3c7b77d 1904 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 1905 apic_update_lvtt(apic);
db138562 1906 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
96ad2cc6
ED		 1907 update_divide_count(apic);
1908 start_apic_timer(apic);
6e24a6ef 1909 apic->irr_pending = true;
d62caabb 1910 apic->isr_count = vcpu->arch.apicv_active ?
c7c9c56c 1911 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1912 apic->highest_isr_cache = -1;
d62caabb 1913 if (vcpu->arch.apicv_active) {
4114c27d
WW		 1914 kvm_x86_ops->hwapic_irr_update(vcpu,
1915 apic_find_highest_irr(apic));
b4eef9b3
TC		 1916 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1917 apic_find_highest_isr(apic));
d62caabb 1918 }
3842d135 1919 kvm_make_request(KVM_REQ_EVENT, vcpu);
49df6397
SR		 1920 if (ioapic_in_kernel(vcpu->kvm))
1921 kvm_rtc_eoi_tracking_restore_one(vcpu);
0669a510
RK		 1922
1923 vcpu->arch.apic_arb_prio = 0;
96ad2cc6 1924}
a3d7f85f 1925
2f52d58c 1926void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1927{
a3d7f85f
ED		 1928 struct hrtimer *timer;
1929
c48f1496 1930 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1931 return;
1932
54e9818f 1933 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1934 if (hrtimer_cancel(timer))
beb20d52 1935 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1936}
b93463aa 1937
ae7a2a3f
MT		 1938/*
1939 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1940 *
1941 * Detect whether guest triggered PV EOI since the
1942 * last entry. If yes, set EOI on guests's behalf.
1943 * Clear PV EOI in guest memory in any case.
1944 */
1945static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1946 struct kvm_lapic *apic)
1947{
1948 bool pending;
1949 int vector;
1950 /*
1951 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1952 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1953 *
1954 * KVM_APIC_PV_EOI_PENDING is unset:
1955 * -> host disabled PV EOI.
1956 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1957 * -> host enabled PV EOI, guest did not execute EOI yet.
1958 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1959 * -> host enabled PV EOI, guest executed EOI.
1960 */
1961 BUG_ON(!pv_eoi_enabled(vcpu));
1962 pending = pv_eoi_get_pending(vcpu);
1963 /*
1964 * Clear pending bit in any case: it will be set again on vmentry.
1965 * While this might not be ideal from performance point of view,
1966 * this makes sure pv eoi is only enabled when we know it's safe.
1967 */
1968 pv_eoi_clr_pending(vcpu);
1969 if (pending)
1970 return;
1971 vector = apic_set_eoi(apic);
1972 trace_kvm_pv_eoi(apic, vector);
1973}
1974
b93463aa
AK		 1975void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1976{
1977 u32 data;
b93463aa 1978
ae7a2a3f
MT		 1979 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1980 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1981
41383771 1982 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1983 return;
1984
603242a8
NK		 1985 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1986 sizeof(u32)))
1987 return;
b93463aa
AK		 1988
1989 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1990}
1991
ae7a2a3f
MT		 1992/*
1993 * apic_sync_pv_eoi_to_guest - called before vmentry
1994 *
1995 * Detect whether it's safe to enable PV EOI and
1996 * if yes do so.
1997 */
1998static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1999 struct kvm_lapic *apic)
2000{
2001 if (!pv_eoi_enabled(vcpu) ||
2002 /* IRR set or many bits in ISR: could be nested. */
2003 apic->irr_pending ||
2004 /* Cache not set: could be safe but we don't bother. */
2005 apic->highest_isr_cache == -1 ||
2006 /* Need EOI to update ioapic. */
3bb345f3 2007 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
ae7a2a3f
MT		 2008 /*
2009 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2010 * so we need not do anything here.
2011 */
2012 return;
2013 }
2014
2015 pv_eoi_set_pending(apic->vcpu);
2016}
2017
b93463aa
AK		 2018void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2019{
2020 u32 data, tpr;
2021 int max_irr, max_isr;
ae7a2a3f 2022 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 2023
ae7a2a3f
MT		 2024 apic_sync_pv_eoi_to_guest(vcpu, apic);
2025
41383771 2026 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2027 return;
2028
c48f1496 2029 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 2030 max_irr = apic_find_highest_irr(apic);
2031 if (max_irr < 0)
2032 max_irr = 0;
2033 max_isr = apic_find_highest_isr(apic);
2034 if (max_isr < 0)
2035 max_isr = 0;
2036 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2037
fda4e2e8
AH		 2038 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2039 sizeof(u32));
b93463aa
AK		 2040}
2041
fda4e2e8 2042int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 2043{
fda4e2e8
AH		 2044 if (vapic_addr) {
2045 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2046 &vcpu->arch.apic->vapic_cache,
2047 vapic_addr, sizeof(u32)))
2048 return -EINVAL;
41383771 2049 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 2050 } else {
41383771 2051 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 2052 }
2053
2054 vcpu->arch.apic->vapic_addr = vapic_addr;
2055 return 0;
b93463aa 2056}
0105d1a5
GN		 2057
2058int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2059{
2060 struct kvm_lapic *apic = vcpu->arch.apic;
2061 u32 reg = (msr - APIC_BASE_MSR) << 4;
2062
35754c98 2063 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2064 return 1;
2065
c69d3d9b
NA		 2066 if (reg == APIC_ICR2)
2067 return 1;
2068
0105d1a5 2069 /* if this is ICR write vector before command */
decdc283 2070 if (reg == APIC_ICR)
0105d1a5
GN		 2071 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2072 return apic_reg_write(apic, reg, (u32)data);
2073}
2074
2075int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2076{
2077 struct kvm_lapic *apic = vcpu->arch.apic;
2078 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2079
35754c98 2080 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2081 return 1;
2082
c69d3d9b
NA		 2083 if (reg == APIC_DFR || reg == APIC_ICR2) {
2084 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2085 reg);
2086 return 1;
2087 }
2088
0105d1a5
GN		 2089 if (apic_reg_read(apic, reg, 4, &low))
2090 return 1;
decdc283 2091 if (reg == APIC_ICR)
0105d1a5
GN		 2092 apic_reg_read(apic, APIC_ICR2, 4, &high);
2093
2094 *data = (((u64)high) << 32) | low;
2095
2096 return 0;
2097}
10388a07
GN		 2098
2099int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2100{
2101 struct kvm_lapic *apic = vcpu->arch.apic;
2102
c48f1496 2103 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2104 return 1;
2105
2106 /* if this is ICR write vector before command */
2107 if (reg == APIC_ICR)
2108 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2109 return apic_reg_write(apic, reg, (u32)data);
2110}
2111
2112int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2113{
2114 struct kvm_lapic *apic = vcpu->arch.apic;
2115 u32 low, high = 0;
2116
c48f1496 2117 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2118 return 1;
2119
2120 if (apic_reg_read(apic, reg, 4, &low))
2121 return 1;
2122 if (reg == APIC_ICR)
2123 apic_reg_read(apic, APIC_ICR2, 4, &high);
2124
2125 *data = (((u64)high) << 32) | low;
2126
2127 return 0;
2128}
ae7a2a3f
MT		 2129
2130int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2131{
2132 u64 addr = data & ~KVM_MSR_ENABLED;
2133 if (!IS_ALIGNED(addr, 4))
2134 return 1;
2135
2136 vcpu->arch.pv_eoi.msr_val = data;
2137 if (!pv_eoi_enabled(vcpu))
2138 return 0;
2139 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2140 addr, sizeof(u8));
ae7a2a3f 2141}
c5cc421b 2142
66450a21
JK		 2143void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2144{
2145 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2146 u8 sipi_vector;
299018f4 2147 unsigned long pe;
66450a21 2148
299018f4 2149 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2150 return;
2151
cd7764fe
PB		 2152 /*
2153 * INITs are latched while in SMM. Because an SMM CPU cannot
2154 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2155 * and delay processing of INIT until the next RSM.
2156 */
2157 if (is_smm(vcpu)) {
2158 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2159 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2160 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2161 return;
2162 }
299018f4 2163
cd7764fe 2164 pe = xchg(&apic->pending_events, 0);
299018f4 2165 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd
NA		 2166 kvm_lapic_reset(vcpu, true);
2167 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2168 if (kvm_vcpu_is_bsp(apic->vcpu))
2169 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2170 else
2171 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2172 }
299018f4 2173 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2174 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2175 /* evaluate pending_events before reading the vector */
2176 smp_rmb();
2177 sipi_vector = apic->sipi_vector;
98eff52a 2178 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2179 vcpu->vcpu_id, sipi_vector);
2180 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2181 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2182 }
2183}
2184
c5cc421b
GN		 2185void kvm_lapic_init(void)
2186{
2187 /* do not patch jump label more than once per second */
2188 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2189 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2190}
Linux kernel - Deliverables
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