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KVM: Add some helper functions for Posted-Interrupts
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
3548a259
RK		 136/* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
3b5a5ffa
RK		 144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
1e08ec4a
GN		 158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
173beedc
NA		 171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
25995e5b 174 u32 ldr, aid;
1e08ec4a 175
df04d1d1
RK		 176 if (!kvm_apic_present(vcpu))
177 continue;
178
25995e5b 179 aid = kvm_apic_id(apic);
1e08ec4a 180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
1e08ec4a 181
25995e5b
RK		 182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
3548a259 184
3b5a5ffa
RK		 185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
3548a259
RK		 196 continue;
197
3b5a5ffa
RK		 198 apic_logical_id(new, ldr, &cid, &lid);
199
25995e5b 200 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
c7c9c56c 211
b053b2ae 212 kvm_make_scan_ioapic_request(kvm);
1e08ec4a
GN		 213}
214
1e1b6c26
NA		 215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
e462755c 217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 218
219 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
1e1b6c26
NA		 224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
1e08ec4a
GN		 231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
257b9a5f
RK		 243static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
244{
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
246
247 apic_set_reg(apic, APIC_ID, id << 24);
248 apic_set_reg(apic, APIC_LDR, ldr);
249 recalculate_apic_map(apic->vcpu->kvm);
250}
251
97222cc8
ED		 252static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
253{
c48f1496 254 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 255}
256
257static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
258{
c48f1496 259 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 260}
261
a3e06bbe
LJ		 262static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
263{
f30ebc31 264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 265}
266
97222cc8
ED		 267static inline int apic_lvtt_period(struct kvm_lapic *apic)
268{
f30ebc31 269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 270}
271
272static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
273{
f30ebc31 274 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 275}
276
cc6e462c
JK		 277static inline int apic_lvt_nmi_mode(u32 lvt_val)
278{
279 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
280}
281
fc61b800
GN		 282void kvm_apic_set_version(struct kvm_vcpu *vcpu)
283{
284 struct kvm_lapic *apic = vcpu->arch.apic;
285 struct kvm_cpuid_entry2 *feat;
286 u32 v = APIC_VERSION;
287
c48f1496 288 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 289 return;
290
291 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293 v |= APIC_LVR_DIRECTED_EOI;
294 apic_set_reg(apic, APIC_LVR, v);
295}
296
f1d24831 297static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 298 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 299 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
300 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
301 LINT_MASK, LINT_MASK, /* LVT0-1 */
302 LVT_MASK /* LVTERR */
303};
304
305static int find_highest_vector(void *bitmap)
306{
ecba9a52
TY		 307 int vec;
308 u32 *reg;
97222cc8 309
ecba9a52
TY		 310 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
313 if (*reg)
314 return fls(*reg) - 1 + vec;
315 }
97222cc8 316
ecba9a52 317 return -1;
97222cc8
ED		 318}
319
8680b94b
MT		 320static u8 count_vectors(void *bitmap)
321{
ecba9a52
TY		 322 int vec;
323 u32 *reg;
8680b94b 324 u8 count = 0;
ecba9a52
TY		 325
326 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327 reg = bitmap + REG_POS(vec);
328 count += hweight32(*reg);
329 }
330
8680b94b
MT		 331 return count;
332}
333
705699a1 334void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 335{
336 u32 i, pir_val;
a20ed54d
YZ		 337
338 for (i = 0; i <= 7; i++) {
339 pir_val = xchg(&pir[i], 0);
340 if (pir_val)
705699a1 341 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 342 }
343}
705699a1
WV		 344EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
345
346void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
347{
348 struct kvm_lapic *apic = vcpu->arch.apic;
349
350 __kvm_apic_update_irr(pir, apic->regs);
351}
a20ed54d
YZ		 352EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
353
11f5cc05 354static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 355{
11f5cc05 356 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 357 /*
358 * irr_pending must be true if any interrupt is pending; set it after
359 * APIC_IRR to avoid race with apic_clear_irr
360 */
361 apic->irr_pending = true;
97222cc8
ED		 362}
363
33e4c686 364static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 365{
33e4c686 366 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 367}
368
369static inline int apic_find_highest_irr(struct kvm_lapic *apic)
370{
371 int result;
372
c7c9c56c
YZ		 373 /*
374 * Note that irr_pending is just a hint. It will be always
375 * true with virtual interrupt delivery enabled.
376 */
33e4c686
GN		 377 if (!apic->irr_pending)
378 return -1;
379
5a71785d 380 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 381 result = apic_search_irr(apic);
97222cc8
ED		 382 ASSERT(result == -1 || result >= 16);
383
384 return result;
385}
386
33e4c686
GN		 387static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
388{
56cc2406
WL		 389 struct kvm_vcpu *vcpu;
390
391 vcpu = apic->vcpu;
392
d50ab6c1 393 if (unlikely(kvm_vcpu_apic_vid_enabled(vcpu))) {
56cc2406 394 /* try to update RVI */
f210f757 395 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 396 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 397 } else {
398 apic->irr_pending = false;
399 apic_clear_vector(vec, apic->regs + APIC_IRR);
400 if (apic_search_irr(apic) != -1)
401 apic->irr_pending = true;
56cc2406 402 }
33e4c686
GN		 403}
404
8680b94b
MT		 405static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
406{
56cc2406
WL		 407 struct kvm_vcpu *vcpu;
408
409 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
410 return;
411
412 vcpu = apic->vcpu;
fc57ac2c 413
8680b94b 414 /*
56cc2406
WL		 415 * With APIC virtualization enabled, all caching is disabled
416 * because the processor can modify ISR under the hood. Instead
417 * just set SVI.
8680b94b 418 */
b4eef9b3 419 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 420 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
421 else {
422 ++apic->isr_count;
423 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
424 /*
425 * ISR (in service register) bit is set when injecting an interrupt.
426 * The highest vector is injected. Thus the latest bit set matches
427 * the highest bit in ISR.
428 */
429 apic->highest_isr_cache = vec;
430 }
8680b94b
MT		 431}
432
fc57ac2c
PB		 433static inline int apic_find_highest_isr(struct kvm_lapic *apic)
434{
435 int result;
436
437 /*
438 * Note that isr_count is always 1, and highest_isr_cache
439 * is always -1, with APIC virtualization enabled.
440 */
441 if (!apic->isr_count)
442 return -1;
443 if (likely(apic->highest_isr_cache != -1))
444 return apic->highest_isr_cache;
445
446 result = find_highest_vector(apic->regs + APIC_ISR);
447 ASSERT(result == -1 || result >= 16);
448
449 return result;
450}
451
8680b94b
MT		 452static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
453{
fc57ac2c
PB		 454 struct kvm_vcpu *vcpu;
455 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
456 return;
457
458 vcpu = apic->vcpu;
459
460 /*
461 * We do get here for APIC virtualization enabled if the guest
462 * uses the Hyper-V APIC enlightenment. In this case we may need
463 * to trigger a new interrupt delivery by writing the SVI field;
464 * on the other hand isr_count and highest_isr_cache are unused
465 * and must be left alone.
466 */
b4eef9b3 467 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 468 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
469 apic_find_highest_isr(apic));
470 else {
8680b94b 471 --apic->isr_count;
fc57ac2c
PB		 472 BUG_ON(apic->isr_count < 0);
473 apic->highest_isr_cache = -1;
474 }
8680b94b
MT		 475}
476
6e5d865c
YS		 477int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
478{
6e5d865c
YS		 479 int highest_irr;
480
33e4c686
GN		 481 /* This may race with setting of irr in __apic_accept_irq() and
482 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
483 * will cause vmexit immediately and the value will be recalculated
484 * on the next vmentry.
485 */
c48f1496 486 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 487 return 0;
54e9818f 488 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 489
490 return highest_irr;
491}
6e5d865c 492
6da7e3f6 493static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 494 int vector, int level, int trig_mode,
495 unsigned long *dest_map);
6da7e3f6 496
b4f2225c
YZ		 497int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
498 unsigned long *dest_map)
97222cc8 499{
ad312c7c 500 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 501
58c2dde1 502 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 503 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 504}
505
ae7a2a3f
MT		 506static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
507{
508
509 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
510 sizeof(val));
511}
512
513static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
514{
515
516 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
517 sizeof(*val));
518}
519
520static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
521{
522 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
523}
524
525static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
526{
527 u8 val;
528 if (pv_eoi_get_user(vcpu, &val) < 0)
529 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 530 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 531 return val & 0x1;
532}
533
534static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
535{
536 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
537 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 538 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 539 return;
540 }
541 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
542}
543
544static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
545{
546 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
547 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 548 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 549 return;
550 }
551 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
552}
553
97222cc8
ED		 554static void apic_update_ppr(struct kvm_lapic *apic)
555{
3842d135 556 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 557 int isr;
558
c48f1496
GN		 559 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
560 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 561 isr = apic_find_highest_isr(apic);
562 isrv = (isr != -1) ? isr : 0;
563
564 if ((tpr & 0xf0) >= (isrv & 0xf0))
565 ppr = tpr & 0xff;
566 else
567 ppr = isrv & 0xf0;
568
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic, ppr, isr, isrv);
571
3842d135
AK		 572 if (old_ppr != ppr) {
573 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 574 if (ppr < old_ppr)
575 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 576 }
97222cc8
ED		 577}
578
579static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
580{
581 apic_set_reg(apic, APIC_TASKPRI, tpr);
582 apic_update_ppr(apic);
583}
584
03d2249e 585static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 586{
03d2249e
RK		 587 if (apic_x2apic_mode(apic))
588 return mda == X2APIC_BROADCAST;
589
590 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 591}
592
03d2249e 593static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 594{
03d2249e
RK		 595 if (kvm_apic_broadcast(apic, mda))
596 return true;
597
598 if (apic_x2apic_mode(apic))
599 return mda == kvm_apic_id(apic);
600
601 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 602}
603
52c233a4 604static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 605{
0105d1a5
GN		 606 u32 logical_id;
607
394457a9 608 if (kvm_apic_broadcast(apic, mda))
9368b567 609 return true;
394457a9 610
9368b567 611 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 612
9368b567 613 if (apic_x2apic_mode(apic))
8a395363
RK		 614 return ((logical_id >> 16) == (mda >> 16))
615 && (logical_id & mda & 0xffff) != 0;
97222cc8 616
9368b567 617 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 618 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 619
c48f1496 620 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 621 case APIC_DFR_FLAT:
9368b567 622 return (logical_id & mda) != 0;
97222cc8 623 case APIC_DFR_CLUSTER:
9368b567
RK		 624 return ((logical_id >> 4) == (mda >> 4))
625 && (logical_id & mda & 0xf) != 0;
97222cc8 626 default:
7712de87 627 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 628 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 629 return false;
97222cc8 630 }
97222cc8
ED		 631}
632
03d2249e
RK		 633/* KVM APIC implementation has two quirks
634 * - dest always begins at 0 while xAPIC MDA has offset 24,
635 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
636 */
637static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
638 struct kvm_lapic *target)
639{
640 bool ipi = source != NULL;
641 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
642
643 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
644 return X2APIC_BROADCAST;
645
646 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
647}
648
52c233a4 649bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 650 int short_hand, unsigned int dest, int dest_mode)
97222cc8 651{
ad312c7c 652 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 653 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 654
655 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 656 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 657 target, source, dest, dest_mode, short_hand);
658
bd371396 659 ASSERT(target);
97222cc8
ED		 660 switch (short_hand) {
661 case APIC_DEST_NOSHORT:
3697f302 662 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 663 return kvm_apic_match_physical_addr(target, mda);
343f94fe 664 else
03d2249e 665 return kvm_apic_match_logical_addr(target, mda);
97222cc8 666 case APIC_DEST_SELF:
9368b567 667 return target == source;
97222cc8 668 case APIC_DEST_ALLINC:
9368b567 669 return true;
97222cc8 670 case APIC_DEST_ALLBUT:
9368b567 671 return target != source;
97222cc8 672 default:
7712de87
JK		 673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
674 short_hand);
9368b567 675 return false;
97222cc8 676 }
97222cc8
ED		 677}
678
1e08ec4a 679bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 680 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 681{
682 struct kvm_apic_map *map;
683 unsigned long bitmap = 1;
684 struct kvm_lapic **dst;
685 int i;
bea15428 686 bool ret, x2apic_ipi;
1e08ec4a
GN		 687
688 *r = -1;
689
690 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 691 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 692 return true;
693 }
694
695 if (irq->shorthand)
696 return false;
697
bea15428 698 x2apic_ipi = src && apic_x2apic_mode(src);
9ea369b0
RK		 699 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
700 return false;
701
bea15428 702 ret = true;
1e08ec4a
GN		 703 rcu_read_lock();
704 map = rcu_dereference(kvm->arch.apic_map);
705
bea15428
PB		 706 if (!map) {
707 ret = false;
1e08ec4a 708 goto out;
bea15428 709 }
698f9755 710
3697f302 711 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 712 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
713 goto out;
714
715 dst = &map->phys_map[irq->dest_id];
1e08ec4a 716 } else {
3548a259
RK		 717 u16 cid;
718
719 if (!kvm_apic_logical_map_valid(map)) {
720 ret = false;
721 goto out;
722 }
723
3b5a5ffa 724 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
45c3094a
RK		 725
726 if (cid >= ARRAY_SIZE(map->logical_map))
727 goto out;
1e08ec4a 728
45c3094a 729 dst = map->logical_map[cid];
1e08ec4a 730
d1ebdbf9 731 if (kvm_lowest_prio_delivery(irq)) {
1e08ec4a
GN		 732 int l = -1;
733 for_each_set_bit(i, &bitmap, 16) {
734 if (!dst[i])
735 continue;
736 if (l < 0)
737 l = i;
738 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
739 l = i;
740 }
741
742 bitmap = (l >= 0) ? 1 << l : 0;
743 }
744 }
745
746 for_each_set_bit(i, &bitmap, 16) {
747 if (!dst[i])
748 continue;
749 if (*r < 0)
750 *r = 0;
b4f2225c 751 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 752 }
1e08ec4a
GN		 753out:
754 rcu_read_unlock();
755 return ret;
756}
757
97222cc8
ED		 758/*
759 * Add a pending IRQ into lapic.
760 * Return 1 if successfully added and 0 if discarded.
761 */
762static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 763 int vector, int level, int trig_mode,
764 unsigned long *dest_map)
97222cc8 765{
6da7e3f6 766 int result = 0;
c5ec1534 767 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 768
a183b638
PB		 769 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
770 trig_mode, vector);
97222cc8 771 switch (delivery_mode) {
97222cc8 772 case APIC_DM_LOWEST:
e1035715
GN		 773 vcpu->arch.apic_arb_prio++;
774 case APIC_DM_FIXED:
bdaffe1d
PB		 775 if (unlikely(trig_mode && !level))
776 break;
777
97222cc8
ED		 778 /* FIXME add logic for vcpu on reset */
779 if (unlikely(!apic_enabled(apic)))
780 break;
781
11f5cc05
JK		 782 result = 1;
783
b4f2225c
YZ		 784 if (dest_map)
785 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 786
bdaffe1d
PB		 787 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
788 if (trig_mode)
789 apic_set_vector(vector, apic->regs + APIC_TMR);
790 else
791 apic_clear_vector(vector, apic->regs + APIC_TMR);
792 }
793
11f5cc05 794 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 795 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 796 else {
797 apic_set_irr(vector, apic);
5a71785d
YZ		 798
799 kvm_make_request(KVM_REQ_EVENT, vcpu);
800 kvm_vcpu_kick(vcpu);
801 }
97222cc8
ED		 802 break;
803
804 case APIC_DM_REMRD:
24d2166b
R		 805 result = 1;
806 vcpu->arch.pv.pv_unhalted = 1;
807 kvm_make_request(KVM_REQ_EVENT, vcpu);
808 kvm_vcpu_kick(vcpu);
97222cc8
ED		 809 break;
810
811 case APIC_DM_SMI:
64d60670
PB		 812 result = 1;
813 kvm_make_request(KVM_REQ_SMI, vcpu);
814 kvm_vcpu_kick(vcpu);
97222cc8 815 break;
3419ffc8 816
97222cc8 817 case APIC_DM_NMI:
6da7e3f6 818 result = 1;
3419ffc8 819 kvm_inject_nmi(vcpu);
26df99c6 820 kvm_vcpu_kick(vcpu);
97222cc8
ED		 821 break;
822
823 case APIC_DM_INIT:
a52315e1 824 if (!trig_mode || level) {
6da7e3f6 825 result = 1;
66450a21
JK		 826 /* assumes that there are only KVM_APIC_INIT/SIPI */
827 apic->pending_events = (1UL << KVM_APIC_INIT);
828 /* make sure pending_events is visible before sending
829 * the request */
830 smp_wmb();
3842d135 831 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 832 kvm_vcpu_kick(vcpu);
833 } else {
1b10bf31
JK		 834 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
835 vcpu->vcpu_id);
c5ec1534 836 }
97222cc8
ED		 837 break;
838
839 case APIC_DM_STARTUP:
1b10bf31
JK		 840 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
841 vcpu->vcpu_id, vector);
66450a21
JK		 842 result = 1;
843 apic->sipi_vector = vector;
844 /* make sure sipi_vector is visible for the receiver */
845 smp_wmb();
846 set_bit(KVM_APIC_SIPI, &apic->pending_events);
847 kvm_make_request(KVM_REQ_EVENT, vcpu);
848 kvm_vcpu_kick(vcpu);
97222cc8
ED		 849 break;
850
23930f95
JK		 851 case APIC_DM_EXTINT:
852 /*
853 * Should only be called by kvm_apic_local_deliver() with LVT0,
854 * before NMI watchdog was enabled. Already handled by
855 * kvm_apic_accept_pic_intr().
856 */
857 break;
858
97222cc8
ED		 859 default:
860 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
861 delivery_mode);
862 break;
863 }
864 return result;
865}
866
e1035715 867int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 868{
e1035715 869 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 870}
871
3bb345f3
PB		 872static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
873{
874 return test_bit(vector, (ulong *)apic->vcpu->arch.eoi_exit_bitmap);
875}
876
c7c9c56c
YZ		 877static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
878{
7543a635
SR		 879 int trigger_mode;
880
881 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
882 if (!kvm_ioapic_handles_vector(apic, vector))
883 return;
3bb345f3 884
7543a635
SR		 885 /* Request a KVM exit to inform the userspace IOAPIC. */
886 if (irqchip_split(apic->vcpu->kvm)) {
887 apic->vcpu->arch.pending_ioapic_eoi = vector;
888 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
889 return;
c7c9c56c 890 }
7543a635
SR		 891
892 if (apic_test_vector(vector, apic->regs + APIC_TMR))
893 trigger_mode = IOAPIC_LEVEL_TRIG;
894 else
895 trigger_mode = IOAPIC_EDGE_TRIG;
896
897 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 898}
899
ae7a2a3f 900static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 901{
902 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 903
904 trace_kvm_eoi(apic, vector);
905
97222cc8
ED		 906 /*
907 * Not every write EOI will has corresponding ISR,
908 * one example is when Kernel check timer on setup_IO_APIC
909 */
910 if (vector == -1)
ae7a2a3f 911 return vector;
97222cc8 912
8680b94b 913 apic_clear_isr(vector, apic);
97222cc8
ED		 914 apic_update_ppr(apic);
915
c7c9c56c 916 kvm_ioapic_send_eoi(apic, vector);
3842d135 917 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 918 return vector;
97222cc8
ED		 919}
920
c7c9c56c
YZ		 921/*
922 * this interface assumes a trap-like exit, which has already finished
923 * desired side effect including vISR and vPPR update.
924 */
925void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
926{
927 struct kvm_lapic *apic = vcpu->arch.apic;
928
929 trace_kvm_eoi(apic, vector);
930
931 kvm_ioapic_send_eoi(apic, vector);
932 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
933}
934EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
935
97222cc8
ED		 936static void apic_send_ipi(struct kvm_lapic *apic)
937{
c48f1496
GN		 938 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
939 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 940 struct kvm_lapic_irq irq;
97222cc8 941
58c2dde1
GN		 942 irq.vector = icr_low & APIC_VECTOR_MASK;
943 irq.delivery_mode = icr_low & APIC_MODE_MASK;
944 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 945 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 946 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
947 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 948 irq.msi_redir_hint = false;
0105d1a5
GN		 949 if (apic_x2apic_mode(apic))
950 irq.dest_id = icr_high;
951 else
952 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 953
1000ff8d
GN		 954 trace_kvm_apic_ipi(icr_low, irq.dest_id);
955
97222cc8
ED		 956 apic_debug("icr_high 0x%x, icr_low 0x%x, "
957 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 958 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
959 "msi_redir_hint 0x%x\n",
9b5843dd 960 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 961 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 962 irq.vector, irq.msi_redir_hint);
58c2dde1 963
b4f2225c 964 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 965}
966
967static u32 apic_get_tmcct(struct kvm_lapic *apic)
968{
b682b814
MT		 969 ktime_t remaining;
970 s64 ns;
9da8f4e8 971 u32 tmcct;
97222cc8
ED		 972
973 ASSERT(apic != NULL);
974
9da8f4e8 975 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 976 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
977 apic->lapic_timer.period == 0)
9da8f4e8
KP		 978 return 0;
979
ace15464 980 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 981 if (ktime_to_ns(remaining) < 0)
982 remaining = ktime_set(0, 0);
983
d3c7b77d
MT		 984 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
985 tmcct = div64_u64(ns,
986 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 987
988 return tmcct;
989}
990
b209749f
AK		 991static void __report_tpr_access(struct kvm_lapic *apic, bool write)
992{
993 struct kvm_vcpu *vcpu = apic->vcpu;
994 struct kvm_run *run = vcpu->run;
995
a8eeb04a 996 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 997 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 998 run->tpr_access.is_write = write;
999}
1000
1001static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1002{
1003 if (apic->vcpu->arch.tpr_access_reporting)
1004 __report_tpr_access(apic, write);
1005}
1006
97222cc8
ED		 1007static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1008{
1009 u32 val = 0;
1010
1011 if (offset >= LAPIC_MMIO_LENGTH)
1012 return 0;
1013
1014 switch (offset) {
0105d1a5
GN		 1015 case APIC_ID:
1016 if (apic_x2apic_mode(apic))
1017 val = kvm_apic_id(apic);
1018 else
1019 val = kvm_apic_id(apic) << 24;
1020 break;
97222cc8 1021 case APIC_ARBPRI:
7712de87 1022 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 1023 break;
1024
1025 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1026 if (apic_lvtt_tscdeadline(apic))
1027 return 0;
1028
97222cc8
ED		 1029 val = apic_get_tmcct(apic);
1030 break;
4a4541a4
AK		 1031 case APIC_PROCPRI:
1032 apic_update_ppr(apic);
c48f1496 1033 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1034 break;
b209749f
AK		 1035 case APIC_TASKPRI:
1036 report_tpr_access(apic, false);
1037 /* fall thru */
97222cc8 1038 default:
c48f1496 1039 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1040 break;
1041 }
1042
1043 return val;
1044}
1045
d76685c4
GH		 1046static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1047{
1048 return container_of(dev, struct kvm_lapic, dev);
1049}
1050
0105d1a5
GN		 1051static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1052 void *data)
97222cc8 1053{
97222cc8
ED		 1054 unsigned char alignment = offset & 0xf;
1055 u32 result;
d5b0b5b1 1056 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1057 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1058
1059 if ((alignment + len) > 4) {
4088bb3c
GN		 1060 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1061 offset, len);
0105d1a5 1062 return 1;
97222cc8 1063 }
0105d1a5
GN		 1064
1065 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1066 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1067 offset);
0105d1a5
GN		 1068 return 1;
1069 }
1070
97222cc8
ED		 1071 result = __apic_read(apic, offset & ~0xf);
1072
229456fc
MT		 1073 trace_kvm_apic_read(offset, result);
1074
97222cc8
ED		 1075 switch (len) {
1076 case 1:
1077 case 2:
1078 case 4:
1079 memcpy(data, (char *)&result + alignment, len);
1080 break;
1081 default:
1082 printk(KERN_ERR "Local APIC read with len = %x, "
1083 "should be 1,2, or 4 instead\n", len);
1084 break;
1085 }
bda9020e 1086 return 0;
97222cc8
ED		 1087}
1088
0105d1a5
GN		 1089static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1090{
c48f1496 1091 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1092 addr >= apic->base_address &&
1093 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1094}
1095
e32edf4f 1096static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1097 gpa_t address, int len, void *data)
1098{
1099 struct kvm_lapic *apic = to_lapic(this);
1100 u32 offset = address - apic->base_address;
1101
1102 if (!apic_mmio_in_range(apic, address))
1103 return -EOPNOTSUPP;
1104
1105 apic_reg_read(apic, offset, len, data);
1106
1107 return 0;
1108}
1109
97222cc8
ED		 1110static void update_divide_count(struct kvm_lapic *apic)
1111{
1112 u32 tmp1, tmp2, tdcr;
1113
c48f1496 1114 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1115 tmp1 = tdcr & 0xf;
1116 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1117 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1118
1119 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1120 apic->divide_count);
97222cc8
ED		 1121}
1122
b6ac0695
RK		 1123static void apic_update_lvtt(struct kvm_lapic *apic)
1124{
1125 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1126 apic->lapic_timer.timer_mode_mask;
1127
1128 if (apic->lapic_timer.timer_mode != timer_mode) {
1129 apic->lapic_timer.timer_mode = timer_mode;
1130 hrtimer_cancel(&apic->lapic_timer.timer);
1131 }
1132}
1133
5d87db71
RK		 1134static void apic_timer_expired(struct kvm_lapic *apic)
1135{
1136 struct kvm_vcpu *vcpu = apic->vcpu;
1137 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1138 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1139
5d87db71
RK		 1140 if (atomic_read(&apic->lapic_timer.pending))
1141 return;
1142
1143 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1144 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1145
1146 if (waitqueue_active(q))
1147 wake_up_interruptible(q);
d0659d94
MT		 1148
1149 if (apic_lvtt_tscdeadline(apic))
1150 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1151}
1152
1153/*
1154 * On APICv, this test will cause a busy wait
1155 * during a higher-priority task.
1156 */
1157
1158static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1159{
1160 struct kvm_lapic *apic = vcpu->arch.apic;
1161 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1162
1163 if (kvm_apic_hw_enabled(apic)) {
1164 int vec = reg & APIC_VECTOR_MASK;
f9339860 1165 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1166
f9339860
MT		 1167 if (kvm_x86_ops->deliver_posted_interrupt)
1168 bitmap = apic->regs + APIC_IRR;
1169
1170 if (apic_test_vector(vec, bitmap))
1171 return true;
d0659d94
MT		 1172 }
1173 return false;
1174}
1175
1176void wait_lapic_expire(struct kvm_vcpu *vcpu)
1177{
1178 struct kvm_lapic *apic = vcpu->arch.apic;
1179 u64 guest_tsc, tsc_deadline;
1180
1181 if (!kvm_vcpu_has_lapic(vcpu))
1182 return;
1183
1184 if (apic->lapic_timer.expired_tscdeadline == 0)
1185 return;
1186
1187 if (!lapic_timer_int_injected(vcpu))
1188 return;
1189
1190 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1191 apic->lapic_timer.expired_tscdeadline = 0;
4ea1636b 1192 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc());
6c19b753 1193 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1194
1195 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1196 if (guest_tsc < tsc_deadline)
1197 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1198}
1199
97222cc8
ED		 1200static void start_apic_timer(struct kvm_lapic *apic)
1201{
a3e06bbe 1202 ktime_t now;
d0659d94 1203
d3c7b77d 1204 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1205
a3e06bbe 1206 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1207 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1208 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1209 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1210 * APIC_BUS_CYCLE_NS * apic->divide_count;
1211
1212 if (!apic->lapic_timer.period)
1213 return;
1214 /*
1215 * Do not allow the guest to program periodic timers with small
1216 * interval, since the hrtimers are not throttled by the host
1217 * scheduler.
1218 */
1219 if (apic_lvtt_period(apic)) {
1220 s64 min_period = min_timer_period_us * 1000LL;
1221
1222 if (apic->lapic_timer.period < min_period) {
1223 pr_info_ratelimited(
1224 "kvm: vcpu %i: requested %lld ns "
1225 "lapic timer period limited to %lld ns\n",
1226 apic->vcpu->vcpu_id,
1227 apic->lapic_timer.period, min_period);
1228 apic->lapic_timer.period = min_period;
1229 }
9bc5791d 1230 }
0b975a3c 1231
a3e06bbe
LJ		 1232 hrtimer_start(&apic->lapic_timer.timer,
1233 ktime_add_ns(now, apic->lapic_timer.period),
1234 HRTIMER_MODE_ABS);
97222cc8 1235
a3e06bbe 1236 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1237 PRIx64 ", "
1238 "timer initial count 0x%x, period %lldns, "
b8688d51 1239 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1240 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1241 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1242 apic->lapic_timer.period,
97222cc8 1243 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1244 apic->lapic_timer.period)));
a3e06bbe
LJ		 1245 } else if (apic_lvtt_tscdeadline(apic)) {
1246 /* lapic timer in tsc deadline mode */
1247 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1248 u64 ns = 0;
d0659d94 1249 ktime_t expire;
a3e06bbe 1250 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1251 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1252 unsigned long flags;
1253
1254 if (unlikely(!tscdeadline || !this_tsc_khz))
1255 return;
1256
1257 local_irq_save(flags);
1258
1259 now = apic->lapic_timer.timer.base->get_time();
4ea1636b 1260 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, rdtsc());
a3e06bbe
LJ		 1261 if (likely(tscdeadline > guest_tsc)) {
1262 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1263 do_div(ns, this_tsc_khz);
d0659d94
MT		 1264 expire = ktime_add_ns(now, ns);
1265 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1266 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1267 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1268 } else
1269 apic_timer_expired(apic);
a3e06bbe
LJ		 1270
1271 local_irq_restore(flags);
1272 }
97222cc8
ED		 1273}
1274
cc6e462c
JK		 1275static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1276{
59fd1323 1277 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1278
59fd1323
RK		 1279 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1280 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1281 if (lvt0_in_nmi_mode) {
cc6e462c
JK		 1282 apic_debug("Receive NMI setting on APIC_LVT0 "
1283 "for cpu %d\n", apic->vcpu->vcpu_id);
42720138 1284 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1285 } else
1286 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1287 }
cc6e462c
JK		 1288}
1289
0105d1a5 1290static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1291{
0105d1a5 1292 int ret = 0;
97222cc8 1293
0105d1a5 1294 trace_kvm_apic_write(reg, val);
97222cc8 1295
0105d1a5 1296 switch (reg) {
97222cc8 1297 case APIC_ID: /* Local APIC ID */
0105d1a5 1298 if (!apic_x2apic_mode(apic))
1e08ec4a 1299 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1300 else
1301 ret = 1;
97222cc8
ED		 1302 break;
1303
1304 case APIC_TASKPRI:
b209749f 1305 report_tpr_access(apic, true);
97222cc8
ED		 1306 apic_set_tpr(apic, val & 0xff);
1307 break;
1308
1309 case APIC_EOI:
1310 apic_set_eoi(apic);
1311 break;
1312
1313 case APIC_LDR:
0105d1a5 1314 if (!apic_x2apic_mode(apic))
1e08ec4a 1315 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1316 else
1317 ret = 1;
97222cc8
ED		 1318 break;
1319
1320 case APIC_DFR:
1e08ec4a 1321 if (!apic_x2apic_mode(apic)) {
0105d1a5 1322 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1323 recalculate_apic_map(apic->vcpu->kvm);
1324 } else
0105d1a5 1325 ret = 1;
97222cc8
ED		 1326 break;
1327
fc61b800
GN		 1328 case APIC_SPIV: {
1329 u32 mask = 0x3ff;
c48f1496 1330 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1331 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1332 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1333 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1334 int i;
1335 u32 lvt_val;
1336
1337 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1338 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1339 APIC_LVTT + 0x10 * i);
1340 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1341 lvt_val | APIC_LVT_MASKED);
1342 }
b6ac0695 1343 apic_update_lvtt(apic);
d3c7b77d 1344 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1345
1346 }
1347 break;
fc61b800 1348 }
97222cc8
ED		 1349 case APIC_ICR:
1350 /* No delay here, so we always clear the pending bit */
1351 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1352 apic_send_ipi(apic);
1353 break;
1354
1355 case APIC_ICR2:
0105d1a5
GN		 1356 if (!apic_x2apic_mode(apic))
1357 val &= 0xff000000;
1358 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1359 break;
1360
23930f95 1361 case APIC_LVT0:
cc6e462c 1362 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1363 case APIC_LVTTHMR:
1364 case APIC_LVTPC:
97222cc8
ED		 1365 case APIC_LVT1:
1366 case APIC_LVTERR:
1367 /* TODO: Check vector */
c48f1496 1368 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1369 val |= APIC_LVT_MASKED;
1370
0105d1a5
GN		 1371 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1372 apic_set_reg(apic, reg, val);
97222cc8
ED		 1373
1374 break;
1375
b6ac0695 1376 case APIC_LVTT:
c48f1496 1377 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1378 val |= APIC_LVT_MASKED;
1379 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1380 apic_set_reg(apic, APIC_LVTT, val);
b6ac0695 1381 apic_update_lvtt(apic);
a3e06bbe
LJ		 1382 break;
1383
97222cc8 1384 case APIC_TMICT:
a3e06bbe
LJ		 1385 if (apic_lvtt_tscdeadline(apic))
1386 break;
1387
d3c7b77d 1388 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1389 apic_set_reg(apic, APIC_TMICT, val);
1390 start_apic_timer(apic);
0105d1a5 1391 break;
97222cc8
ED		 1392
1393 case APIC_TDCR:
1394 if (val & 4)
7712de87 1395 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1396 apic_set_reg(apic, APIC_TDCR, val);
1397 update_divide_count(apic);
1398 break;
1399
0105d1a5
GN		 1400 case APIC_ESR:
1401 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1402 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1403 ret = 1;
1404 }
1405 break;
1406
1407 case APIC_SELF_IPI:
1408 if (apic_x2apic_mode(apic)) {
1409 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1410 } else
1411 ret = 1;
1412 break;
97222cc8 1413 default:
0105d1a5 1414 ret = 1;
97222cc8
ED		 1415 break;
1416 }
0105d1a5
GN		 1417 if (ret)
1418 apic_debug("Local APIC Write to read-only register %x\n", reg);
1419 return ret;
1420}
1421
e32edf4f 1422static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1423 gpa_t address, int len, const void *data)
1424{
1425 struct kvm_lapic *apic = to_lapic(this);
1426 unsigned int offset = address - apic->base_address;
1427 u32 val;
1428
1429 if (!apic_mmio_in_range(apic, address))
1430 return -EOPNOTSUPP;
1431
1432 /*
1433 * APIC register must be aligned on 128-bits boundary.
1434 * 32/64/128 bits registers must be accessed thru 32 bits.
1435 * Refer SDM 8.4.1
1436 */
1437 if (len != 4 || (offset & 0xf)) {
1438 /* Don't shout loud, $infamous_os would cause only noise. */
1439 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1440 return 0;
0105d1a5
GN		 1441 }
1442
1443 val = *(u32*)data;
1444
1445 /* too common printing */
1446 if (offset != APIC_EOI)
1447 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1448 "0x%x\n", __func__, offset, len, val);
1449
1450 apic_reg_write(apic, offset & 0xff0, val);
1451
bda9020e 1452 return 0;
97222cc8
ED		 1453}
1454
58fbbf26
KT		 1455void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1456{
c48f1496 1457 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1458 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1459}
1460EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1461
83d4c286
YZ		 1462/* emulate APIC access in a trap manner */
1463void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1464{
1465 u32 val = 0;
1466
1467 /* hw has done the conditional check and inst decode */
1468 offset &= 0xff0;
1469
1470 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1471
1472 /* TODO: optimize to just emulate side effect w/o one more write */
1473 apic_reg_write(vcpu->arch.apic, offset, val);
1474}
1475EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1476
d589444e 1477void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1478{
f8c1ea10
GN		 1479 struct kvm_lapic *apic = vcpu->arch.apic;
1480
ad312c7c 1481 if (!vcpu->arch.apic)
97222cc8
ED		 1482 return;
1483
f8c1ea10 1484 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1485
c5cc421b
GN		 1486 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1487 static_key_slow_dec_deferred(&apic_hw_disabled);
1488
e462755c 1489 if (!apic->sw_enabled)
f8c1ea10 1490 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1491
f8c1ea10
GN		 1492 if (apic->regs)
1493 free_page((unsigned long)apic->regs);
1494
1495 kfree(apic);
97222cc8
ED		 1496}
1497
1498/*
1499 *----------------------------------------------------------------------
1500 * LAPIC interface
1501 *----------------------------------------------------------------------
1502 */
1503
a3e06bbe
LJ		 1504u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1505{
1506 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1507
c48f1496 1508 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1509 apic_lvtt_period(apic))
a3e06bbe
LJ		 1510 return 0;
1511
1512 return apic->lapic_timer.tscdeadline;
1513}
1514
1515void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1516{
1517 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1518
c48f1496 1519 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1520 apic_lvtt_period(apic))
a3e06bbe
LJ		 1521 return;
1522
1523 hrtimer_cancel(&apic->lapic_timer.timer);
1524 apic->lapic_timer.tscdeadline = data;
1525 start_apic_timer(apic);
1526}
1527
97222cc8
ED		 1528void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1529{
ad312c7c 1530 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1531
c48f1496 1532 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1533 return;
54e9818f 1534
b93463aa 1535 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1536 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1537}
1538
1539u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1540{
97222cc8
ED		 1541 u64 tpr;
1542
c48f1496 1543 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1544 return 0;
54e9818f 1545
c48f1496 1546 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1547
1548 return (tpr & 0xf0) >> 4;
1549}
1550
1551void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1552{
8d14695f 1553 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1554 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1555
1556 if (!apic) {
1557 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1558 vcpu->arch.apic_base = value;
97222cc8
ED		 1559 return;
1560 }
c5af89b6 1561
e66d2ae7
JK		 1562 vcpu->arch.apic_base = value;
1563
c5cc421b 1564 /* update jump label if enable bit changes */
0dce7cd6 1565 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1566 if (value & MSR_IA32_APICBASE_ENABLE)
1567 static_key_slow_dec_deferred(&apic_hw_disabled);
1568 else
1569 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1570 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1571 }
1572
8d14695f
YZ		 1573 if ((old_value ^ value) & X2APIC_ENABLE) {
1574 if (value & X2APIC_ENABLE) {
257b9a5f 1575 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
8d14695f
YZ		 1576 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1577 } else
1578 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1579 }
8d14695f 1580
ad312c7c 1581 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1582 MSR_IA32_APICBASE_BASE;
1583
db324fe6
NA		 1584 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1585 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1586 pr_warn_once("APIC base relocation is unsupported by KVM");
1587
97222cc8
ED		 1588 /* with FSB delivery interrupt, we can restart APIC functionality */
1589 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1590 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1591
1592}
1593
d28bc9dd 1594void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8
ED		 1595{
1596 struct kvm_lapic *apic;
1597 int i;
1598
b8688d51 1599 apic_debug("%s\n", __func__);
97222cc8
ED		 1600
1601 ASSERT(vcpu);
ad312c7c 1602 apic = vcpu->arch.apic;
97222cc8
ED		 1603 ASSERT(apic != NULL);
1604
1605 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1606 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1607
d28bc9dd
NA		 1608 if (!init_event)
1609 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1610 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1611
1612 for (i = 0; i < APIC_LVT_NUM; i++)
1613 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 1614 apic_update_lvtt(apic);
0da029ed 1615 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
90de4a18
NA		 1616 apic_set_reg(apic, APIC_LVT0,
1617 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
59fd1323 1618 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
97222cc8
ED		 1619
1620 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1621 apic_set_spiv(apic, 0xff);
97222cc8 1622 apic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 1623 if (!apic_x2apic_mode(apic))
1624 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1625 apic_set_reg(apic, APIC_ESR, 0);
1626 apic_set_reg(apic, APIC_ICR, 0);
1627 apic_set_reg(apic, APIC_ICR2, 0);
1628 apic_set_reg(apic, APIC_TDCR, 0);
1629 apic_set_reg(apic, APIC_TMICT, 0);
1630 for (i = 0; i < 8; i++) {
1631 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1632 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1633 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1634 }
d50ab6c1 1635 apic->irr_pending = kvm_vcpu_apic_vid_enabled(vcpu);
f563db4b 1636 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
8680b94b 1637 apic->highest_isr_cache = -1;
b33ac88b 1638 update_divide_count(apic);
d3c7b77d 1639 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1640 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1641 kvm_lapic_set_base(vcpu,
1642 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1643 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1644 apic_update_ppr(apic);
1645
e1035715 1646 vcpu->arch.apic_arb_prio = 0;
41383771 1647 vcpu->arch.apic_attention = 0;
e1035715 1648
98eff52a 1649 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1650 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1651 vcpu, kvm_apic_id(apic),
ad312c7c 1652 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1653}
1654
97222cc8
ED		 1655/*
1656 *----------------------------------------------------------------------
1657 * timer interface
1658 *----------------------------------------------------------------------
1659 */
1b9778da 1660
2a6eac96 1661static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1662{
d3c7b77d 1663 return apic_lvtt_period(apic);
97222cc8
ED		 1664}
1665
3d80840d
MT		 1666int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1667{
54e9818f 1668 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1669
c48f1496 1670 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1671 apic_lvt_enabled(apic, APIC_LVTT))
1672 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1673
1674 return 0;
1675}
1676
89342082 1677int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1678{
c48f1496 1679 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1680 int vector, mode, trig_mode;
23930f95 1681
c48f1496 1682 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1683 vector = reg & APIC_VECTOR_MASK;
1684 mode = reg & APIC_MODE_MASK;
1685 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1686 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1687 NULL);
23930f95
JK		 1688 }
1689 return 0;
1690}
1b9778da 1691
8fdb2351 1692void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1693{
8fdb2351
JK		 1694 struct kvm_lapic *apic = vcpu->arch.apic;
1695
1696 if (apic)
1697 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1698}
1699
d76685c4
GH		 1700static const struct kvm_io_device_ops apic_mmio_ops = {
1701 .read = apic_mmio_read,
1702 .write = apic_mmio_write,
d76685c4
GH		 1703};
1704
e9d90d47
AK		 1705static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1706{
1707 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1708 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1709
5d87db71 1710 apic_timer_expired(apic);
e9d90d47 1711
2a6eac96 1712 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1713 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1714 return HRTIMER_RESTART;
1715 } else
1716 return HRTIMER_NORESTART;
1717}
1718
97222cc8
ED		 1719int kvm_create_lapic(struct kvm_vcpu *vcpu)
1720{
1721 struct kvm_lapic *apic;
1722
1723 ASSERT(vcpu != NULL);
1724 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1725
1726 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1727 if (!apic)
1728 goto nomem;
1729
ad312c7c 1730 vcpu->arch.apic = apic;
97222cc8 1731
afc20184
TY		 1732 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1733 if (!apic->regs) {
97222cc8
ED		 1734 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1735 vcpu->vcpu_id);
d589444e 1736 goto nomem_free_apic;
97222cc8 1737 }
97222cc8
ED		 1738 apic->vcpu = vcpu;
1739
d3c7b77d
MT		 1740 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1741 HRTIMER_MODE_ABS);
e9d90d47 1742 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1743
c5cc421b
GN		 1744 /*
1745 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1746 * thinking that APIC satet has changed.
1747 */
1748 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1749 kvm_lapic_set_base(vcpu,
1750 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1751
f8c1ea10 1752 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d28bc9dd 1753 kvm_lapic_reset(vcpu, false);
d76685c4 1754 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1755
1756 return 0;
d589444e
RR		 1757nomem_free_apic:
1758 kfree(apic);
97222cc8 1759nomem:
97222cc8
ED		 1760 return -ENOMEM;
1761}
97222cc8
ED		 1762
1763int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1764{
ad312c7c 1765 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1766 int highest_irr;
1767
c48f1496 1768 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1769 return -1;
1770
6e5d865c 1771 apic_update_ppr(apic);
97222cc8
ED		 1772 highest_irr = apic_find_highest_irr(apic);
1773 if ((highest_irr == -1) ||
c48f1496 1774 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1775 return -1;
1776 return highest_irr;
1777}
1778
40487c68
QH		 1779int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1780{
c48f1496 1781 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1782 int r = 0;
1783
c48f1496 1784 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1785 r = 1;
1786 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1787 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1788 r = 1;
40487c68
QH		 1789 return r;
1790}
1791
1b9778da
ED		 1792void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1793{
ad312c7c 1794 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1795
c48f1496 1796 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1797 return;
1798
1799 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1800 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1801 if (apic_lvtt_tscdeadline(apic))
1802 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1803 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1804 }
1805}
1806
97222cc8
ED		 1807int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1808{
1809 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1810 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1811
1812 if (vector == -1)
1813 return -1;
1814
56cc2406
WL		 1815 /*
1816 * We get here even with APIC virtualization enabled, if doing
1817 * nested virtualization and L1 runs with the "acknowledge interrupt
1818 * on exit" mode. Then we cannot inject the interrupt via RVI,
1819 * because the process would deliver it through the IDT.
1820 */
1821
8680b94b 1822 apic_set_isr(vector, apic);
97222cc8
ED		 1823 apic_update_ppr(apic);
1824 apic_clear_irr(vector, apic);
1825 return vector;
1826}
96ad2cc6 1827
64eb0620
GN		 1828void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1829 struct kvm_lapic_state *s)
96ad2cc6 1830{
ad312c7c 1831 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1832
5dbc8f3f 1833 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1834 /* set SPIV separately to get count of SW disabled APICs right */
1835 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1836 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1837 /* call kvm_apic_set_id() to put apic into apic_map */
1838 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1839 kvm_apic_set_version(vcpu);
1840
96ad2cc6 1841 apic_update_ppr(apic);
d3c7b77d 1842 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 1843 apic_update_lvtt(apic);
db138562 1844 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
96ad2cc6
ED		 1845 update_divide_count(apic);
1846 start_apic_timer(apic);
6e24a6ef 1847 apic->irr_pending = true;
f563db4b 1848 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
c7c9c56c 1849 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1850 apic->highest_isr_cache = -1;
4114c27d
WW		 1851 if (kvm_x86_ops->hwapic_irr_update)
1852 kvm_x86_ops->hwapic_irr_update(vcpu,
1853 apic_find_highest_irr(apic));
b4eef9b3
TC		 1854 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1855 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1856 apic_find_highest_isr(apic));
3842d135 1857 kvm_make_request(KVM_REQ_EVENT, vcpu);
49df6397
SR		 1858 if (ioapic_in_kernel(vcpu->kvm))
1859 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1860}
a3d7f85f 1861
2f52d58c 1862void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1863{
a3d7f85f
ED		 1864 struct hrtimer *timer;
1865
c48f1496 1866 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1867 return;
1868
54e9818f 1869 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1870 if (hrtimer_cancel(timer))
beb20d52 1871 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1872}
b93463aa 1873
ae7a2a3f
MT		 1874/*
1875 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1876 *
1877 * Detect whether guest triggered PV EOI since the
1878 * last entry. If yes, set EOI on guests's behalf.
1879 * Clear PV EOI in guest memory in any case.
1880 */
1881static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1882 struct kvm_lapic *apic)
1883{
1884 bool pending;
1885 int vector;
1886 /*
1887 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1888 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1889 *
1890 * KVM_APIC_PV_EOI_PENDING is unset:
1891 * -> host disabled PV EOI.
1892 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1893 * -> host enabled PV EOI, guest did not execute EOI yet.
1894 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1895 * -> host enabled PV EOI, guest executed EOI.
1896 */
1897 BUG_ON(!pv_eoi_enabled(vcpu));
1898 pending = pv_eoi_get_pending(vcpu);
1899 /*
1900 * Clear pending bit in any case: it will be set again on vmentry.
1901 * While this might not be ideal from performance point of view,
1902 * this makes sure pv eoi is only enabled when we know it's safe.
1903 */
1904 pv_eoi_clr_pending(vcpu);
1905 if (pending)
1906 return;
1907 vector = apic_set_eoi(apic);
1908 trace_kvm_pv_eoi(apic, vector);
1909}
1910
b93463aa
AK		 1911void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1912{
1913 u32 data;
b93463aa 1914
ae7a2a3f
MT		 1915 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1916 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1917
41383771 1918 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1919 return;
1920
603242a8
NK		 1921 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1922 sizeof(u32)))
1923 return;
b93463aa
AK		 1924
1925 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1926}
1927
ae7a2a3f
MT		 1928/*
1929 * apic_sync_pv_eoi_to_guest - called before vmentry
1930 *
1931 * Detect whether it's safe to enable PV EOI and
1932 * if yes do so.
1933 */
1934static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1935 struct kvm_lapic *apic)
1936{
1937 if (!pv_eoi_enabled(vcpu) ||
1938 /* IRR set or many bits in ISR: could be nested. */
1939 apic->irr_pending ||
1940 /* Cache not set: could be safe but we don't bother. */
1941 apic->highest_isr_cache == -1 ||
1942 /* Need EOI to update ioapic. */
3bb345f3 1943 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
ae7a2a3f
MT		 1944 /*
1945 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1946 * so we need not do anything here.
1947 */
1948 return;
1949 }
1950
1951 pv_eoi_set_pending(apic->vcpu);
1952}
1953
b93463aa
AK		 1954void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1955{
1956 u32 data, tpr;
1957 int max_irr, max_isr;
ae7a2a3f 1958 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1959
ae7a2a3f
MT		 1960 apic_sync_pv_eoi_to_guest(vcpu, apic);
1961
41383771 1962 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1963 return;
1964
c48f1496 1965 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1966 max_irr = apic_find_highest_irr(apic);
1967 if (max_irr < 0)
1968 max_irr = 0;
1969 max_isr = apic_find_highest_isr(apic);
1970 if (max_isr < 0)
1971 max_isr = 0;
1972 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1973
fda4e2e8
AH		 1974 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1975 sizeof(u32));
b93463aa
AK		 1976}
1977
fda4e2e8 1978int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1979{
fda4e2e8
AH		 1980 if (vapic_addr) {
1981 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1982 &vcpu->arch.apic->vapic_cache,
1983 vapic_addr, sizeof(u32)))
1984 return -EINVAL;
41383771 1985 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1986 } else {
41383771 1987 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1988 }
1989
1990 vcpu->arch.apic->vapic_addr = vapic_addr;
1991 return 0;
b93463aa 1992}
0105d1a5
GN		 1993
1994int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1995{
1996 struct kvm_lapic *apic = vcpu->arch.apic;
1997 u32 reg = (msr - APIC_BASE_MSR) << 4;
1998
35754c98 1999 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2000 return 1;
2001
c69d3d9b
NA		 2002 if (reg == APIC_ICR2)
2003 return 1;
2004
0105d1a5 2005 /* if this is ICR write vector before command */
decdc283 2006 if (reg == APIC_ICR)
0105d1a5
GN		 2007 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2008 return apic_reg_write(apic, reg, (u32)data);
2009}
2010
2011int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2012{
2013 struct kvm_lapic *apic = vcpu->arch.apic;
2014 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2015
35754c98 2016 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2017 return 1;
2018
c69d3d9b
NA		 2019 if (reg == APIC_DFR || reg == APIC_ICR2) {
2020 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2021 reg);
2022 return 1;
2023 }
2024
0105d1a5
GN		 2025 if (apic_reg_read(apic, reg, 4, &low))
2026 return 1;
decdc283 2027 if (reg == APIC_ICR)
0105d1a5
GN		 2028 apic_reg_read(apic, APIC_ICR2, 4, &high);
2029
2030 *data = (((u64)high) << 32) | low;
2031
2032 return 0;
2033}
10388a07
GN		 2034
2035int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2036{
2037 struct kvm_lapic *apic = vcpu->arch.apic;
2038
c48f1496 2039 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2040 return 1;
2041
2042 /* if this is ICR write vector before command */
2043 if (reg == APIC_ICR)
2044 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2045 return apic_reg_write(apic, reg, (u32)data);
2046}
2047
2048int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2049{
2050 struct kvm_lapic *apic = vcpu->arch.apic;
2051 u32 low, high = 0;
2052
c48f1496 2053 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2054 return 1;
2055
2056 if (apic_reg_read(apic, reg, 4, &low))
2057 return 1;
2058 if (reg == APIC_ICR)
2059 apic_reg_read(apic, APIC_ICR2, 4, &high);
2060
2061 *data = (((u64)high) << 32) | low;
2062
2063 return 0;
2064}
ae7a2a3f
MT		 2065
2066int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2067{
2068 u64 addr = data & ~KVM_MSR_ENABLED;
2069 if (!IS_ALIGNED(addr, 4))
2070 return 1;
2071
2072 vcpu->arch.pv_eoi.msr_val = data;
2073 if (!pv_eoi_enabled(vcpu))
2074 return 0;
2075 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2076 addr, sizeof(u8));
ae7a2a3f 2077}
c5cc421b 2078
66450a21
JK		 2079void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2080{
2081 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2082 u8 sipi_vector;
299018f4 2083 unsigned long pe;
66450a21 2084
299018f4 2085 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2086 return;
2087
cd7764fe
PB		 2088 /*
2089 * INITs are latched while in SMM. Because an SMM CPU cannot
2090 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2091 * and delay processing of INIT until the next RSM.
2092 */
2093 if (is_smm(vcpu)) {
2094 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2095 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2096 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2097 return;
2098 }
299018f4 2099
cd7764fe 2100 pe = xchg(&apic->pending_events, 0);
299018f4 2101 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd
NA		 2102 kvm_lapic_reset(vcpu, true);
2103 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2104 if (kvm_vcpu_is_bsp(apic->vcpu))
2105 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2106 else
2107 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2108 }
299018f4 2109 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2110 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2111 /* evaluate pending_events before reading the vector */
2112 smp_rmb();
2113 sipi_vector = apic->sipi_vector;
98eff52a 2114 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2115 vcpu->vcpu_id, sipi_vector);
2116 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2117 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2118 }
2119}
2120
c5cc421b
GN		 2121void kvm_lapic_init(void)
2122{
2123 /* do not patch jump label more than once per second */
2124 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2125 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2126}
Linux kernel - Deliverables
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