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KVM: vmx: obey KVM_QUIRK_CD_NW_CLEARED
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
3548a259
RK		 136/* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
3b5a5ffa
RK		 144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
1e08ec4a
GN		 158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
173beedc
NA		 171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
25995e5b 174 u32 ldr, aid;
1e08ec4a 175
df04d1d1
RK		 176 if (!kvm_apic_present(vcpu))
177 continue;
178
25995e5b 179 aid = kvm_apic_id(apic);
1e08ec4a 180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
1e08ec4a 181
25995e5b
RK		 182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
3548a259 184
3b5a5ffa
RK		 185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
3548a259
RK		 196 continue;
197
3b5a5ffa
RK		 198 apic_logical_id(new, ldr, &cid, &lid);
199
25995e5b 200 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
c7c9c56c 211
3d81bc7e 212 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 213}
214
1e1b6c26
NA		 215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
e462755c 217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 218
219 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
1e1b6c26
NA		 224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
1e08ec4a
GN		 231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
257b9a5f
RK		 243static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
244{
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
246
247 apic_set_reg(apic, APIC_ID, id << 24);
248 apic_set_reg(apic, APIC_LDR, ldr);
249 recalculate_apic_map(apic->vcpu->kvm);
250}
251
97222cc8
ED		 252static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
253{
c48f1496 254 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 255}
256
257static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
258{
c48f1496 259 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 260}
261
a3e06bbe
LJ		 262static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
263{
f30ebc31 264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 265}
266
97222cc8
ED		 267static inline int apic_lvtt_period(struct kvm_lapic *apic)
268{
f30ebc31 269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 270}
271
272static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
273{
f30ebc31 274 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 275}
276
cc6e462c
JK		 277static inline int apic_lvt_nmi_mode(u32 lvt_val)
278{
279 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
280}
281
fc61b800
GN		 282void kvm_apic_set_version(struct kvm_vcpu *vcpu)
283{
284 struct kvm_lapic *apic = vcpu->arch.apic;
285 struct kvm_cpuid_entry2 *feat;
286 u32 v = APIC_VERSION;
287
c48f1496 288 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 289 return;
290
291 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293 v |= APIC_LVR_DIRECTED_EOI;
294 apic_set_reg(apic, APIC_LVR, v);
295}
296
f1d24831 297static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 298 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 299 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
300 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
301 LINT_MASK, LINT_MASK, /* LVT0-1 */
302 LVT_MASK /* LVTERR */
303};
304
305static int find_highest_vector(void *bitmap)
306{
ecba9a52
TY		 307 int vec;
308 u32 *reg;
97222cc8 309
ecba9a52
TY		 310 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
313 if (*reg)
314 return fls(*reg) - 1 + vec;
315 }
97222cc8 316
ecba9a52 317 return -1;
97222cc8
ED		 318}
319
8680b94b
MT		 320static u8 count_vectors(void *bitmap)
321{
ecba9a52
TY		 322 int vec;
323 u32 *reg;
8680b94b 324 u8 count = 0;
ecba9a52
TY		 325
326 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327 reg = bitmap + REG_POS(vec);
328 count += hweight32(*reg);
329 }
330
8680b94b
MT		 331 return count;
332}
333
705699a1 334void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 335{
336 u32 i, pir_val;
a20ed54d
YZ		 337
338 for (i = 0; i <= 7; i++) {
339 pir_val = xchg(&pir[i], 0);
340 if (pir_val)
705699a1 341 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 342 }
343}
705699a1
WV		 344EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
345
346void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
347{
348 struct kvm_lapic *apic = vcpu->arch.apic;
349
350 __kvm_apic_update_irr(pir, apic->regs);
351}
a20ed54d
YZ		 352EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
353
11f5cc05 354static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 355{
11f5cc05 356 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 357 /*
358 * irr_pending must be true if any interrupt is pending; set it after
359 * APIC_IRR to avoid race with apic_clear_irr
360 */
361 apic->irr_pending = true;
97222cc8
ED		 362}
363
33e4c686 364static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 365{
33e4c686 366 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 367}
368
369static inline int apic_find_highest_irr(struct kvm_lapic *apic)
370{
371 int result;
372
c7c9c56c
YZ		 373 /*
374 * Note that irr_pending is just a hint. It will be always
375 * true with virtual interrupt delivery enabled.
376 */
33e4c686
GN		 377 if (!apic->irr_pending)
378 return -1;
379
5a71785d 380 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 381 result = apic_search_irr(apic);
97222cc8
ED		 382 ASSERT(result == -1 || result >= 16);
383
384 return result;
385}
386
33e4c686
GN		 387static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
388{
56cc2406
WL		 389 struct kvm_vcpu *vcpu;
390
391 vcpu = apic->vcpu;
392
f210f757 393 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 394 /* try to update RVI */
f210f757 395 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 396 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 397 } else {
398 apic->irr_pending = false;
399 apic_clear_vector(vec, apic->regs + APIC_IRR);
400 if (apic_search_irr(apic) != -1)
401 apic->irr_pending = true;
56cc2406 402 }
33e4c686
GN		 403}
404
8680b94b
MT		 405static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
406{
56cc2406
WL		 407 struct kvm_vcpu *vcpu;
408
409 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
410 return;
411
412 vcpu = apic->vcpu;
fc57ac2c 413
8680b94b 414 /*
56cc2406
WL		 415 * With APIC virtualization enabled, all caching is disabled
416 * because the processor can modify ISR under the hood. Instead
417 * just set SVI.
8680b94b 418 */
b4eef9b3 419 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 420 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
421 else {
422 ++apic->isr_count;
423 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
424 /*
425 * ISR (in service register) bit is set when injecting an interrupt.
426 * The highest vector is injected. Thus the latest bit set matches
427 * the highest bit in ISR.
428 */
429 apic->highest_isr_cache = vec;
430 }
8680b94b
MT		 431}
432
fc57ac2c
PB		 433static inline int apic_find_highest_isr(struct kvm_lapic *apic)
434{
435 int result;
436
437 /*
438 * Note that isr_count is always 1, and highest_isr_cache
439 * is always -1, with APIC virtualization enabled.
440 */
441 if (!apic->isr_count)
442 return -1;
443 if (likely(apic->highest_isr_cache != -1))
444 return apic->highest_isr_cache;
445
446 result = find_highest_vector(apic->regs + APIC_ISR);
447 ASSERT(result == -1 || result >= 16);
448
449 return result;
450}
451
8680b94b
MT		 452static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
453{
fc57ac2c
PB		 454 struct kvm_vcpu *vcpu;
455 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
456 return;
457
458 vcpu = apic->vcpu;
459
460 /*
461 * We do get here for APIC virtualization enabled if the guest
462 * uses the Hyper-V APIC enlightenment. In this case we may need
463 * to trigger a new interrupt delivery by writing the SVI field;
464 * on the other hand isr_count and highest_isr_cache are unused
465 * and must be left alone.
466 */
b4eef9b3 467 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 468 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
469 apic_find_highest_isr(apic));
470 else {
8680b94b 471 --apic->isr_count;
fc57ac2c
PB		 472 BUG_ON(apic->isr_count < 0);
473 apic->highest_isr_cache = -1;
474 }
8680b94b
MT		 475}
476
6e5d865c
YS		 477int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
478{
6e5d865c
YS		 479 int highest_irr;
480
33e4c686
GN		 481 /* This may race with setting of irr in __apic_accept_irq() and
482 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
483 * will cause vmexit immediately and the value will be recalculated
484 * on the next vmentry.
485 */
c48f1496 486 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 487 return 0;
54e9818f 488 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 489
490 return highest_irr;
491}
6e5d865c 492
6da7e3f6 493static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 494 int vector, int level, int trig_mode,
495 unsigned long *dest_map);
6da7e3f6 496
b4f2225c
YZ		 497int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
498 unsigned long *dest_map)
97222cc8 499{
ad312c7c 500 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 501
58c2dde1 502 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 503 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 504}
505
ae7a2a3f
MT		 506static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
507{
508
509 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
510 sizeof(val));
511}
512
513static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
514{
515
516 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
517 sizeof(*val));
518}
519
520static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
521{
522 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
523}
524
525static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
526{
527 u8 val;
528 if (pv_eoi_get_user(vcpu, &val) < 0)
529 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 530 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 531 return val & 0x1;
532}
533
534static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
535{
536 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
537 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 538 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 539 return;
540 }
541 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
542}
543
544static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
545{
546 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
547 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 548 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 549 return;
550 }
551 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
552}
553
cf9e65b7
YZ		 554void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
555{
556 struct kvm_lapic *apic = vcpu->arch.apic;
557 int i;
558
559 for (i = 0; i < 8; i++)
560 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
561}
562
97222cc8
ED		 563static void apic_update_ppr(struct kvm_lapic *apic)
564{
3842d135 565 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 566 int isr;
567
c48f1496
GN		 568 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
569 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 570 isr = apic_find_highest_isr(apic);
571 isrv = (isr != -1) ? isr : 0;
572
573 if ((tpr & 0xf0) >= (isrv & 0xf0))
574 ppr = tpr & 0xff;
575 else
576 ppr = isrv & 0xf0;
577
578 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
579 apic, ppr, isr, isrv);
580
3842d135
AK		 581 if (old_ppr != ppr) {
582 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 583 if (ppr < old_ppr)
584 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 585 }
97222cc8
ED		 586}
587
588static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
589{
590 apic_set_reg(apic, APIC_TASKPRI, tpr);
591 apic_update_ppr(apic);
592}
593
03d2249e 594static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 595{
03d2249e
RK		 596 if (apic_x2apic_mode(apic))
597 return mda == X2APIC_BROADCAST;
598
599 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 600}
601
03d2249e 602static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 603{
03d2249e
RK		 604 if (kvm_apic_broadcast(apic, mda))
605 return true;
606
607 if (apic_x2apic_mode(apic))
608 return mda == kvm_apic_id(apic);
609
610 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 611}
612
52c233a4 613static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 614{
0105d1a5
GN		 615 u32 logical_id;
616
394457a9 617 if (kvm_apic_broadcast(apic, mda))
9368b567 618 return true;
394457a9 619
9368b567 620 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 621
9368b567 622 if (apic_x2apic_mode(apic))
8a395363
RK		 623 return ((logical_id >> 16) == (mda >> 16))
624 && (logical_id & mda & 0xffff) != 0;
97222cc8 625
9368b567 626 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 627 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 628
c48f1496 629 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 630 case APIC_DFR_FLAT:
9368b567 631 return (logical_id & mda) != 0;
97222cc8 632 case APIC_DFR_CLUSTER:
9368b567
RK		 633 return ((logical_id >> 4) == (mda >> 4))
634 && (logical_id & mda & 0xf) != 0;
97222cc8 635 default:
7712de87 636 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 637 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 638 return false;
97222cc8 639 }
97222cc8
ED		 640}
641
03d2249e
RK		 642/* KVM APIC implementation has two quirks
643 * - dest always begins at 0 while xAPIC MDA has offset 24,
644 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
645 */
646static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
647 struct kvm_lapic *target)
648{
649 bool ipi = source != NULL;
650 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
651
652 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
653 return X2APIC_BROADCAST;
654
655 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
656}
657
52c233a4 658bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 659 int short_hand, unsigned int dest, int dest_mode)
97222cc8 660{
ad312c7c 661 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 662 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 663
664 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 665 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 666 target, source, dest, dest_mode, short_hand);
667
bd371396 668 ASSERT(target);
97222cc8
ED		 669 switch (short_hand) {
670 case APIC_DEST_NOSHORT:
3697f302 671 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 672 return kvm_apic_match_physical_addr(target, mda);
343f94fe 673 else
03d2249e 674 return kvm_apic_match_logical_addr(target, mda);
97222cc8 675 case APIC_DEST_SELF:
9368b567 676 return target == source;
97222cc8 677 case APIC_DEST_ALLINC:
9368b567 678 return true;
97222cc8 679 case APIC_DEST_ALLBUT:
9368b567 680 return target != source;
97222cc8 681 default:
7712de87
JK		 682 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
683 short_hand);
9368b567 684 return false;
97222cc8 685 }
97222cc8
ED		 686}
687
1e08ec4a 688bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 689 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 690{
691 struct kvm_apic_map *map;
692 unsigned long bitmap = 1;
693 struct kvm_lapic **dst;
694 int i;
bea15428 695 bool ret, x2apic_ipi;
1e08ec4a
GN		 696
697 *r = -1;
698
699 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 700 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 701 return true;
702 }
703
704 if (irq->shorthand)
705 return false;
706
bea15428 707 x2apic_ipi = src && apic_x2apic_mode(src);
9ea369b0
RK		 708 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
709 return false;
710
bea15428 711 ret = true;
1e08ec4a
GN		 712 rcu_read_lock();
713 map = rcu_dereference(kvm->arch.apic_map);
714
bea15428
PB		 715 if (!map) {
716 ret = false;
1e08ec4a 717 goto out;
bea15428 718 }
698f9755 719
3697f302 720 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 721 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
722 goto out;
723
724 dst = &map->phys_map[irq->dest_id];
1e08ec4a 725 } else {
3548a259
RK		 726 u16 cid;
727
728 if (!kvm_apic_logical_map_valid(map)) {
729 ret = false;
730 goto out;
731 }
732
3b5a5ffa 733 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
45c3094a
RK		 734
735 if (cid >= ARRAY_SIZE(map->logical_map))
736 goto out;
1e08ec4a 737
45c3094a 738 dst = map->logical_map[cid];
1e08ec4a 739
d1ebdbf9 740 if (kvm_lowest_prio_delivery(irq)) {
1e08ec4a
GN		 741 int l = -1;
742 for_each_set_bit(i, &bitmap, 16) {
743 if (!dst[i])
744 continue;
745 if (l < 0)
746 l = i;
747 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
748 l = i;
749 }
750
751 bitmap = (l >= 0) ? 1 << l : 0;
752 }
753 }
754
755 for_each_set_bit(i, &bitmap, 16) {
756 if (!dst[i])
757 continue;
758 if (*r < 0)
759 *r = 0;
b4f2225c 760 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 761 }
1e08ec4a
GN		 762out:
763 rcu_read_unlock();
764 return ret;
765}
766
97222cc8
ED		 767/*
768 * Add a pending IRQ into lapic.
769 * Return 1 if successfully added and 0 if discarded.
770 */
771static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 772 int vector, int level, int trig_mode,
773 unsigned long *dest_map)
97222cc8 774{
6da7e3f6 775 int result = 0;
c5ec1534 776 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 777
a183b638
PB		 778 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
779 trig_mode, vector);
97222cc8 780 switch (delivery_mode) {
97222cc8 781 case APIC_DM_LOWEST:
e1035715
GN		 782 vcpu->arch.apic_arb_prio++;
783 case APIC_DM_FIXED:
97222cc8
ED		 784 /* FIXME add logic for vcpu on reset */
785 if (unlikely(!apic_enabled(apic)))
786 break;
787
11f5cc05
JK		 788 result = 1;
789
b4f2225c
YZ		 790 if (dest_map)
791 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 792
11f5cc05 793 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 794 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 795 else {
796 apic_set_irr(vector, apic);
5a71785d
YZ		 797
798 kvm_make_request(KVM_REQ_EVENT, vcpu);
799 kvm_vcpu_kick(vcpu);
800 }
97222cc8
ED		 801 break;
802
803 case APIC_DM_REMRD:
24d2166b
R		 804 result = 1;
805 vcpu->arch.pv.pv_unhalted = 1;
806 kvm_make_request(KVM_REQ_EVENT, vcpu);
807 kvm_vcpu_kick(vcpu);
97222cc8
ED		 808 break;
809
810 case APIC_DM_SMI:
64d60670
PB		 811 result = 1;
812 kvm_make_request(KVM_REQ_SMI, vcpu);
813 kvm_vcpu_kick(vcpu);
97222cc8 814 break;
3419ffc8 815
97222cc8 816 case APIC_DM_NMI:
6da7e3f6 817 result = 1;
3419ffc8 818 kvm_inject_nmi(vcpu);
26df99c6 819 kvm_vcpu_kick(vcpu);
97222cc8
ED		 820 break;
821
822 case APIC_DM_INIT:
a52315e1 823 if (!trig_mode || level) {
6da7e3f6 824 result = 1;
66450a21
JK		 825 /* assumes that there are only KVM_APIC_INIT/SIPI */
826 apic->pending_events = (1UL << KVM_APIC_INIT);
827 /* make sure pending_events is visible before sending
828 * the request */
829 smp_wmb();
3842d135 830 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 831 kvm_vcpu_kick(vcpu);
832 } else {
1b10bf31
JK		 833 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
834 vcpu->vcpu_id);
c5ec1534 835 }
97222cc8
ED		 836 break;
837
838 case APIC_DM_STARTUP:
1b10bf31
JK		 839 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
840 vcpu->vcpu_id, vector);
66450a21
JK		 841 result = 1;
842 apic->sipi_vector = vector;
843 /* make sure sipi_vector is visible for the receiver */
844 smp_wmb();
845 set_bit(KVM_APIC_SIPI, &apic->pending_events);
846 kvm_make_request(KVM_REQ_EVENT, vcpu);
847 kvm_vcpu_kick(vcpu);
97222cc8
ED		 848 break;
849
23930f95
JK		 850 case APIC_DM_EXTINT:
851 /*
852 * Should only be called by kvm_apic_local_deliver() with LVT0,
853 * before NMI watchdog was enabled. Already handled by
854 * kvm_apic_accept_pic_intr().
855 */
856 break;
857
97222cc8
ED		 858 default:
859 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
860 delivery_mode);
861 break;
862 }
863 return result;
864}
865
e1035715 866int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 867{
e1035715 868 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 869}
870
c7c9c56c
YZ		 871static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
872{
c806a6ad 873 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
c7c9c56c
YZ		 874 int trigger_mode;
875 if (apic_test_vector(vector, apic->regs + APIC_TMR))
876 trigger_mode = IOAPIC_LEVEL_TRIG;
877 else
878 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 879 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 880 }
881}
882
ae7a2a3f 883static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 884{
885 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 886
887 trace_kvm_eoi(apic, vector);
888
97222cc8
ED		 889 /*
890 * Not every write EOI will has corresponding ISR,
891 * one example is when Kernel check timer on setup_IO_APIC
892 */
893 if (vector == -1)
ae7a2a3f 894 return vector;
97222cc8 895
8680b94b 896 apic_clear_isr(vector, apic);
97222cc8
ED		 897 apic_update_ppr(apic);
898
c7c9c56c 899 kvm_ioapic_send_eoi(apic, vector);
3842d135 900 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 901 return vector;
97222cc8
ED		 902}
903
c7c9c56c
YZ		 904/*
905 * this interface assumes a trap-like exit, which has already finished
906 * desired side effect including vISR and vPPR update.
907 */
908void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
909{
910 struct kvm_lapic *apic = vcpu->arch.apic;
911
912 trace_kvm_eoi(apic, vector);
913
914 kvm_ioapic_send_eoi(apic, vector);
915 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
916}
917EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
918
97222cc8
ED		 919static void apic_send_ipi(struct kvm_lapic *apic)
920{
c48f1496
GN		 921 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
922 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 923 struct kvm_lapic_irq irq;
97222cc8 924
58c2dde1
GN		 925 irq.vector = icr_low & APIC_VECTOR_MASK;
926 irq.delivery_mode = icr_low & APIC_MODE_MASK;
927 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 928 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 929 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
930 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 931 irq.msi_redir_hint = false;
0105d1a5
GN		 932 if (apic_x2apic_mode(apic))
933 irq.dest_id = icr_high;
934 else
935 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 936
1000ff8d
GN		 937 trace_kvm_apic_ipi(icr_low, irq.dest_id);
938
97222cc8
ED		 939 apic_debug("icr_high 0x%x, icr_low 0x%x, "
940 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 941 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
942 "msi_redir_hint 0x%x\n",
9b5843dd 943 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 944 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 945 irq.vector, irq.msi_redir_hint);
58c2dde1 946
b4f2225c 947 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 948}
949
950static u32 apic_get_tmcct(struct kvm_lapic *apic)
951{
b682b814
MT		 952 ktime_t remaining;
953 s64 ns;
9da8f4e8 954 u32 tmcct;
97222cc8
ED		 955
956 ASSERT(apic != NULL);
957
9da8f4e8 958 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 959 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
960 apic->lapic_timer.period == 0)
9da8f4e8
KP		 961 return 0;
962
ace15464 963 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 964 if (ktime_to_ns(remaining) < 0)
965 remaining = ktime_set(0, 0);
966
d3c7b77d
MT		 967 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
968 tmcct = div64_u64(ns,
969 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 970
971 return tmcct;
972}
973
b209749f
AK		 974static void __report_tpr_access(struct kvm_lapic *apic, bool write)
975{
976 struct kvm_vcpu *vcpu = apic->vcpu;
977 struct kvm_run *run = vcpu->run;
978
a8eeb04a 979 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 980 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 981 run->tpr_access.is_write = write;
982}
983
984static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
985{
986 if (apic->vcpu->arch.tpr_access_reporting)
987 __report_tpr_access(apic, write);
988}
989
97222cc8
ED		 990static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
991{
992 u32 val = 0;
993
994 if (offset >= LAPIC_MMIO_LENGTH)
995 return 0;
996
997 switch (offset) {
0105d1a5
GN		 998 case APIC_ID:
999 if (apic_x2apic_mode(apic))
1000 val = kvm_apic_id(apic);
1001 else
1002 val = kvm_apic_id(apic) << 24;
1003 break;
97222cc8 1004 case APIC_ARBPRI:
7712de87 1005 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 1006 break;
1007
1008 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1009 if (apic_lvtt_tscdeadline(apic))
1010 return 0;
1011
97222cc8
ED		 1012 val = apic_get_tmcct(apic);
1013 break;
4a4541a4
AK		 1014 case APIC_PROCPRI:
1015 apic_update_ppr(apic);
c48f1496 1016 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1017 break;
b209749f
AK		 1018 case APIC_TASKPRI:
1019 report_tpr_access(apic, false);
1020 /* fall thru */
97222cc8 1021 default:
c48f1496 1022 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1023 break;
1024 }
1025
1026 return val;
1027}
1028
d76685c4
GH		 1029static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1030{
1031 return container_of(dev, struct kvm_lapic, dev);
1032}
1033
0105d1a5
GN		 1034static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1035 void *data)
97222cc8 1036{
97222cc8
ED		 1037 unsigned char alignment = offset & 0xf;
1038 u32 result;
d5b0b5b1 1039 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1040 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1041
1042 if ((alignment + len) > 4) {
4088bb3c
GN		 1043 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1044 offset, len);
0105d1a5 1045 return 1;
97222cc8 1046 }
0105d1a5
GN		 1047
1048 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1049 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1050 offset);
0105d1a5
GN		 1051 return 1;
1052 }
1053
97222cc8
ED		 1054 result = __apic_read(apic, offset & ~0xf);
1055
229456fc
MT		 1056 trace_kvm_apic_read(offset, result);
1057
97222cc8
ED		 1058 switch (len) {
1059 case 1:
1060 case 2:
1061 case 4:
1062 memcpy(data, (char *)&result + alignment, len);
1063 break;
1064 default:
1065 printk(KERN_ERR "Local APIC read with len = %x, "
1066 "should be 1,2, or 4 instead\n", len);
1067 break;
1068 }
bda9020e 1069 return 0;
97222cc8
ED		 1070}
1071
0105d1a5
GN		 1072static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1073{
c48f1496 1074 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1075 addr >= apic->base_address &&
1076 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1077}
1078
e32edf4f 1079static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1080 gpa_t address, int len, void *data)
1081{
1082 struct kvm_lapic *apic = to_lapic(this);
1083 u32 offset = address - apic->base_address;
1084
1085 if (!apic_mmio_in_range(apic, address))
1086 return -EOPNOTSUPP;
1087
1088 apic_reg_read(apic, offset, len, data);
1089
1090 return 0;
1091}
1092
97222cc8
ED		 1093static void update_divide_count(struct kvm_lapic *apic)
1094{
1095 u32 tmp1, tmp2, tdcr;
1096
c48f1496 1097 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1098 tmp1 = tdcr & 0xf;
1099 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1100 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1101
1102 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1103 apic->divide_count);
97222cc8
ED		 1104}
1105
b6ac0695
RK		 1106static void apic_update_lvtt(struct kvm_lapic *apic)
1107{
1108 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1109 apic->lapic_timer.timer_mode_mask;
1110
1111 if (apic->lapic_timer.timer_mode != timer_mode) {
1112 apic->lapic_timer.timer_mode = timer_mode;
1113 hrtimer_cancel(&apic->lapic_timer.timer);
1114 }
1115}
1116
5d87db71
RK		 1117static void apic_timer_expired(struct kvm_lapic *apic)
1118{
1119 struct kvm_vcpu *vcpu = apic->vcpu;
1120 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1121 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1122
5d87db71
RK		 1123 if (atomic_read(&apic->lapic_timer.pending))
1124 return;
1125
1126 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1127 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1128
1129 if (waitqueue_active(q))
1130 wake_up_interruptible(q);
d0659d94
MT		 1131
1132 if (apic_lvtt_tscdeadline(apic))
1133 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1134}
1135
1136/*
1137 * On APICv, this test will cause a busy wait
1138 * during a higher-priority task.
1139 */
1140
1141static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1142{
1143 struct kvm_lapic *apic = vcpu->arch.apic;
1144 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1145
1146 if (kvm_apic_hw_enabled(apic)) {
1147 int vec = reg & APIC_VECTOR_MASK;
f9339860 1148 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1149
f9339860
MT		 1150 if (kvm_x86_ops->deliver_posted_interrupt)
1151 bitmap = apic->regs + APIC_IRR;
1152
1153 if (apic_test_vector(vec, bitmap))
1154 return true;
d0659d94
MT		 1155 }
1156 return false;
1157}
1158
1159void wait_lapic_expire(struct kvm_vcpu *vcpu)
1160{
1161 struct kvm_lapic *apic = vcpu->arch.apic;
1162 u64 guest_tsc, tsc_deadline;
1163
1164 if (!kvm_vcpu_has_lapic(vcpu))
1165 return;
1166
1167 if (apic->lapic_timer.expired_tscdeadline == 0)
1168 return;
1169
1170 if (!lapic_timer_int_injected(vcpu))
1171 return;
1172
1173 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1174 apic->lapic_timer.expired_tscdeadline = 0;
1175 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
6c19b753 1176 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1177
1178 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1179 if (guest_tsc < tsc_deadline)
1180 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1181}
1182
97222cc8
ED		 1183static void start_apic_timer(struct kvm_lapic *apic)
1184{
a3e06bbe 1185 ktime_t now;
d0659d94 1186
d3c7b77d 1187 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1188
a3e06bbe 1189 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1190 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1191 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1192 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1193 * APIC_BUS_CYCLE_NS * apic->divide_count;
1194
1195 if (!apic->lapic_timer.period)
1196 return;
1197 /*
1198 * Do not allow the guest to program periodic timers with small
1199 * interval, since the hrtimers are not throttled by the host
1200 * scheduler.
1201 */
1202 if (apic_lvtt_period(apic)) {
1203 s64 min_period = min_timer_period_us * 1000LL;
1204
1205 if (apic->lapic_timer.period < min_period) {
1206 pr_info_ratelimited(
1207 "kvm: vcpu %i: requested %lld ns "
1208 "lapic timer period limited to %lld ns\n",
1209 apic->vcpu->vcpu_id,
1210 apic->lapic_timer.period, min_period);
1211 apic->lapic_timer.period = min_period;
1212 }
9bc5791d 1213 }
0b975a3c 1214
a3e06bbe
LJ		 1215 hrtimer_start(&apic->lapic_timer.timer,
1216 ktime_add_ns(now, apic->lapic_timer.period),
1217 HRTIMER_MODE_ABS);
97222cc8 1218
a3e06bbe 1219 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1220 PRIx64 ", "
1221 "timer initial count 0x%x, period %lldns, "
b8688d51 1222 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1223 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1224 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1225 apic->lapic_timer.period,
97222cc8 1226 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1227 apic->lapic_timer.period)));
a3e06bbe
LJ		 1228 } else if (apic_lvtt_tscdeadline(apic)) {
1229 /* lapic timer in tsc deadline mode */
1230 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1231 u64 ns = 0;
d0659d94 1232 ktime_t expire;
a3e06bbe 1233 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1234 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1235 unsigned long flags;
1236
1237 if (unlikely(!tscdeadline || !this_tsc_khz))
1238 return;
1239
1240 local_irq_save(flags);
1241
1242 now = apic->lapic_timer.timer.base->get_time();
886b470c 1243 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1244 if (likely(tscdeadline > guest_tsc)) {
1245 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1246 do_div(ns, this_tsc_khz);
d0659d94
MT		 1247 expire = ktime_add_ns(now, ns);
1248 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1249 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1250 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1251 } else
1252 apic_timer_expired(apic);
a3e06bbe
LJ		 1253
1254 local_irq_restore(flags);
1255 }
97222cc8
ED		 1256}
1257
cc6e462c
JK		 1258static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1259{
59fd1323 1260 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1261
59fd1323
RK		 1262 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1263 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1264 if (lvt0_in_nmi_mode) {
cc6e462c
JK		 1265 apic_debug("Receive NMI setting on APIC_LVT0 "
1266 "for cpu %d\n", apic->vcpu->vcpu_id);
42720138 1267 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1268 } else
1269 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1270 }
cc6e462c
JK		 1271}
1272
0105d1a5 1273static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1274{
0105d1a5 1275 int ret = 0;
97222cc8 1276
0105d1a5 1277 trace_kvm_apic_write(reg, val);
97222cc8 1278
0105d1a5 1279 switch (reg) {
97222cc8 1280 case APIC_ID: /* Local APIC ID */
0105d1a5 1281 if (!apic_x2apic_mode(apic))
1e08ec4a 1282 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1283 else
1284 ret = 1;
97222cc8
ED		 1285 break;
1286
1287 case APIC_TASKPRI:
b209749f 1288 report_tpr_access(apic, true);
97222cc8
ED		 1289 apic_set_tpr(apic, val & 0xff);
1290 break;
1291
1292 case APIC_EOI:
1293 apic_set_eoi(apic);
1294 break;
1295
1296 case APIC_LDR:
0105d1a5 1297 if (!apic_x2apic_mode(apic))
1e08ec4a 1298 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1299 else
1300 ret = 1;
97222cc8
ED		 1301 break;
1302
1303 case APIC_DFR:
1e08ec4a 1304 if (!apic_x2apic_mode(apic)) {
0105d1a5 1305 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1306 recalculate_apic_map(apic->vcpu->kvm);
1307 } else
0105d1a5 1308 ret = 1;
97222cc8
ED		 1309 break;
1310
fc61b800
GN		 1311 case APIC_SPIV: {
1312 u32 mask = 0x3ff;
c48f1496 1313 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1314 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1315 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1316 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1317 int i;
1318 u32 lvt_val;
1319
1320 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1321 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1322 APIC_LVTT + 0x10 * i);
1323 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1324 lvt_val | APIC_LVT_MASKED);
1325 }
b6ac0695 1326 apic_update_lvtt(apic);
d3c7b77d 1327 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1328
1329 }
1330 break;
fc61b800 1331 }
97222cc8
ED		 1332 case APIC_ICR:
1333 /* No delay here, so we always clear the pending bit */
1334 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1335 apic_send_ipi(apic);
1336 break;
1337
1338 case APIC_ICR2:
0105d1a5
GN		 1339 if (!apic_x2apic_mode(apic))
1340 val &= 0xff000000;
1341 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1342 break;
1343
23930f95 1344 case APIC_LVT0:
cc6e462c 1345 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1346 case APIC_LVTTHMR:
1347 case APIC_LVTPC:
97222cc8
ED		 1348 case APIC_LVT1:
1349 case APIC_LVTERR:
1350 /* TODO: Check vector */
c48f1496 1351 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1352 val |= APIC_LVT_MASKED;
1353
0105d1a5
GN		 1354 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1355 apic_set_reg(apic, reg, val);
97222cc8
ED		 1356
1357 break;
1358
b6ac0695 1359 case APIC_LVTT:
c48f1496 1360 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1361 val |= APIC_LVT_MASKED;
1362 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1363 apic_set_reg(apic, APIC_LVTT, val);
b6ac0695 1364 apic_update_lvtt(apic);
a3e06bbe
LJ		 1365 break;
1366
97222cc8 1367 case APIC_TMICT:
a3e06bbe
LJ		 1368 if (apic_lvtt_tscdeadline(apic))
1369 break;
1370
d3c7b77d 1371 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1372 apic_set_reg(apic, APIC_TMICT, val);
1373 start_apic_timer(apic);
0105d1a5 1374 break;
97222cc8
ED		 1375
1376 case APIC_TDCR:
1377 if (val & 4)
7712de87 1378 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1379 apic_set_reg(apic, APIC_TDCR, val);
1380 update_divide_count(apic);
1381 break;
1382
0105d1a5
GN		 1383 case APIC_ESR:
1384 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1385 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1386 ret = 1;
1387 }
1388 break;
1389
1390 case APIC_SELF_IPI:
1391 if (apic_x2apic_mode(apic)) {
1392 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1393 } else
1394 ret = 1;
1395 break;
97222cc8 1396 default:
0105d1a5 1397 ret = 1;
97222cc8
ED		 1398 break;
1399 }
0105d1a5
GN		 1400 if (ret)
1401 apic_debug("Local APIC Write to read-only register %x\n", reg);
1402 return ret;
1403}
1404
e32edf4f 1405static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1406 gpa_t address, int len, const void *data)
1407{
1408 struct kvm_lapic *apic = to_lapic(this);
1409 unsigned int offset = address - apic->base_address;
1410 u32 val;
1411
1412 if (!apic_mmio_in_range(apic, address))
1413 return -EOPNOTSUPP;
1414
1415 /*
1416 * APIC register must be aligned on 128-bits boundary.
1417 * 32/64/128 bits registers must be accessed thru 32 bits.
1418 * Refer SDM 8.4.1
1419 */
1420 if (len != 4 || (offset & 0xf)) {
1421 /* Don't shout loud, $infamous_os would cause only noise. */
1422 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1423 return 0;
0105d1a5
GN		 1424 }
1425
1426 val = *(u32*)data;
1427
1428 /* too common printing */
1429 if (offset != APIC_EOI)
1430 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1431 "0x%x\n", __func__, offset, len, val);
1432
1433 apic_reg_write(apic, offset & 0xff0, val);
1434
bda9020e 1435 return 0;
97222cc8
ED		 1436}
1437
58fbbf26
KT		 1438void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1439{
c48f1496 1440 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1441 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1442}
1443EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1444
83d4c286
YZ		 1445/* emulate APIC access in a trap manner */
1446void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1447{
1448 u32 val = 0;
1449
1450 /* hw has done the conditional check and inst decode */
1451 offset &= 0xff0;
1452
1453 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1454
1455 /* TODO: optimize to just emulate side effect w/o one more write */
1456 apic_reg_write(vcpu->arch.apic, offset, val);
1457}
1458EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1459
d589444e 1460void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1461{
f8c1ea10
GN		 1462 struct kvm_lapic *apic = vcpu->arch.apic;
1463
ad312c7c 1464 if (!vcpu->arch.apic)
97222cc8
ED		 1465 return;
1466
f8c1ea10 1467 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1468
c5cc421b
GN		 1469 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1470 static_key_slow_dec_deferred(&apic_hw_disabled);
1471
e462755c 1472 if (!apic->sw_enabled)
f8c1ea10 1473 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1474
f8c1ea10
GN		 1475 if (apic->regs)
1476 free_page((unsigned long)apic->regs);
1477
1478 kfree(apic);
97222cc8
ED		 1479}
1480
1481/*
1482 *----------------------------------------------------------------------
1483 * LAPIC interface
1484 *----------------------------------------------------------------------
1485 */
1486
a3e06bbe
LJ		 1487u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1488{
1489 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1490
c48f1496 1491 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1492 apic_lvtt_period(apic))
a3e06bbe
LJ		 1493 return 0;
1494
1495 return apic->lapic_timer.tscdeadline;
1496}
1497
1498void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1499{
1500 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1501
c48f1496 1502 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1503 apic_lvtt_period(apic))
a3e06bbe
LJ		 1504 return;
1505
1506 hrtimer_cancel(&apic->lapic_timer.timer);
1507 apic->lapic_timer.tscdeadline = data;
1508 start_apic_timer(apic);
1509}
1510
97222cc8
ED		 1511void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1512{
ad312c7c 1513 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1514
c48f1496 1515 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1516 return;
54e9818f 1517
b93463aa 1518 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1519 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1520}
1521
1522u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1523{
97222cc8
ED		 1524 u64 tpr;
1525
c48f1496 1526 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1527 return 0;
54e9818f 1528
c48f1496 1529 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1530
1531 return (tpr & 0xf0) >> 4;
1532}
1533
1534void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1535{
8d14695f 1536 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1537 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1538
1539 if (!apic) {
1540 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1541 vcpu->arch.apic_base = value;
97222cc8
ED		 1542 return;
1543 }
c5af89b6 1544
e66d2ae7
JK		 1545 vcpu->arch.apic_base = value;
1546
c5cc421b 1547 /* update jump label if enable bit changes */
0dce7cd6 1548 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1549 if (value & MSR_IA32_APICBASE_ENABLE)
1550 static_key_slow_dec_deferred(&apic_hw_disabled);
1551 else
1552 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1553 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1554 }
1555
8d14695f
YZ		 1556 if ((old_value ^ value) & X2APIC_ENABLE) {
1557 if (value & X2APIC_ENABLE) {
257b9a5f 1558 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
8d14695f
YZ		 1559 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1560 } else
1561 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1562 }
8d14695f 1563
ad312c7c 1564 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1565 MSR_IA32_APICBASE_BASE;
1566
db324fe6
NA		 1567 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1568 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1569 pr_warn_once("APIC base relocation is unsupported by KVM");
1570
97222cc8
ED		 1571 /* with FSB delivery interrupt, we can restart APIC functionality */
1572 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1573 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1574
1575}
1576
d28bc9dd 1577void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8
ED		 1578{
1579 struct kvm_lapic *apic;
1580 int i;
1581
b8688d51 1582 apic_debug("%s\n", __func__);
97222cc8
ED		 1583
1584 ASSERT(vcpu);
ad312c7c 1585 apic = vcpu->arch.apic;
97222cc8
ED		 1586 ASSERT(apic != NULL);
1587
1588 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1589 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1590
d28bc9dd
NA		 1591 if (!init_event)
1592 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1593 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1594
1595 for (i = 0; i < APIC_LVT_NUM; i++)
1596 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 1597 apic_update_lvtt(apic);
41dbc6bc 1598 if (kvm_check_has_quirk(vcpu->kvm, KVM_QUIRK_LINT0_REENABLED))
90de4a18
NA		 1599 apic_set_reg(apic, APIC_LVT0,
1600 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
59fd1323 1601 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
97222cc8
ED		 1602
1603 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1604 apic_set_spiv(apic, 0xff);
97222cc8 1605 apic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 1606 if (!apic_x2apic_mode(apic))
1607 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1608 apic_set_reg(apic, APIC_ESR, 0);
1609 apic_set_reg(apic, APIC_ICR, 0);
1610 apic_set_reg(apic, APIC_ICR2, 0);
1611 apic_set_reg(apic, APIC_TDCR, 0);
1612 apic_set_reg(apic, APIC_TMICT, 0);
1613 for (i = 0; i < 8; i++) {
1614 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1615 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1616 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1617 }
c7c9c56c 1618 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
f563db4b 1619 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
8680b94b 1620 apic->highest_isr_cache = -1;
b33ac88b 1621 update_divide_count(apic);
d3c7b77d 1622 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1623 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1624 kvm_lapic_set_base(vcpu,
1625 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1626 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1627 apic_update_ppr(apic);
1628
e1035715 1629 vcpu->arch.apic_arb_prio = 0;
41383771 1630 vcpu->arch.apic_attention = 0;
e1035715 1631
98eff52a 1632 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1633 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1634 vcpu, kvm_apic_id(apic),
ad312c7c 1635 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1636}
1637
97222cc8
ED		 1638/*
1639 *----------------------------------------------------------------------
1640 * timer interface
1641 *----------------------------------------------------------------------
1642 */
1b9778da 1643
2a6eac96 1644static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1645{
d3c7b77d 1646 return apic_lvtt_period(apic);
97222cc8
ED		 1647}
1648
3d80840d
MT		 1649int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1650{
54e9818f 1651 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1652
c48f1496 1653 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1654 apic_lvt_enabled(apic, APIC_LVTT))
1655 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1656
1657 return 0;
1658}
1659
89342082 1660int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1661{
c48f1496 1662 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1663 int vector, mode, trig_mode;
23930f95 1664
c48f1496 1665 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1666 vector = reg & APIC_VECTOR_MASK;
1667 mode = reg & APIC_MODE_MASK;
1668 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1669 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1670 NULL);
23930f95
JK		 1671 }
1672 return 0;
1673}
1b9778da 1674
8fdb2351 1675void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1676{
8fdb2351
JK		 1677 struct kvm_lapic *apic = vcpu->arch.apic;
1678
1679 if (apic)
1680 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1681}
1682
d76685c4
GH		 1683static const struct kvm_io_device_ops apic_mmio_ops = {
1684 .read = apic_mmio_read,
1685 .write = apic_mmio_write,
d76685c4
GH		 1686};
1687
e9d90d47
AK		 1688static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1689{
1690 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1691 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1692
5d87db71 1693 apic_timer_expired(apic);
e9d90d47 1694
2a6eac96 1695 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1696 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1697 return HRTIMER_RESTART;
1698 } else
1699 return HRTIMER_NORESTART;
1700}
1701
97222cc8
ED		 1702int kvm_create_lapic(struct kvm_vcpu *vcpu)
1703{
1704 struct kvm_lapic *apic;
1705
1706 ASSERT(vcpu != NULL);
1707 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1708
1709 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1710 if (!apic)
1711 goto nomem;
1712
ad312c7c 1713 vcpu->arch.apic = apic;
97222cc8 1714
afc20184
TY		 1715 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1716 if (!apic->regs) {
97222cc8
ED		 1717 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1718 vcpu->vcpu_id);
d589444e 1719 goto nomem_free_apic;
97222cc8 1720 }
97222cc8
ED		 1721 apic->vcpu = vcpu;
1722
d3c7b77d
MT		 1723 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1724 HRTIMER_MODE_ABS);
e9d90d47 1725 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1726
c5cc421b
GN		 1727 /*
1728 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1729 * thinking that APIC satet has changed.
1730 */
1731 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1732 kvm_lapic_set_base(vcpu,
1733 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1734
f8c1ea10 1735 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d28bc9dd 1736 kvm_lapic_reset(vcpu, false);
d76685c4 1737 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1738
1739 return 0;
d589444e
RR		 1740nomem_free_apic:
1741 kfree(apic);
97222cc8 1742nomem:
97222cc8
ED		 1743 return -ENOMEM;
1744}
97222cc8
ED		 1745
1746int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1747{
ad312c7c 1748 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1749 int highest_irr;
1750
c48f1496 1751 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1752 return -1;
1753
6e5d865c 1754 apic_update_ppr(apic);
97222cc8
ED		 1755 highest_irr = apic_find_highest_irr(apic);
1756 if ((highest_irr == -1) ||
c48f1496 1757 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1758 return -1;
1759 return highest_irr;
1760}
1761
40487c68
QH		 1762int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1763{
c48f1496 1764 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1765 int r = 0;
1766
c48f1496 1767 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1768 r = 1;
1769 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1770 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1771 r = 1;
40487c68
QH		 1772 return r;
1773}
1774
1b9778da
ED		 1775void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1776{
ad312c7c 1777 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1778
c48f1496 1779 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1780 return;
1781
1782 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1783 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1784 if (apic_lvtt_tscdeadline(apic))
1785 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1786 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1787 }
1788}
1789
97222cc8
ED		 1790int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1791{
1792 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1793 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1794
1795 if (vector == -1)
1796 return -1;
1797
56cc2406
WL		 1798 /*
1799 * We get here even with APIC virtualization enabled, if doing
1800 * nested virtualization and L1 runs with the "acknowledge interrupt
1801 * on exit" mode. Then we cannot inject the interrupt via RVI,
1802 * because the process would deliver it through the IDT.
1803 */
1804
8680b94b 1805 apic_set_isr(vector, apic);
97222cc8
ED		 1806 apic_update_ppr(apic);
1807 apic_clear_irr(vector, apic);
1808 return vector;
1809}
96ad2cc6 1810
64eb0620
GN		 1811void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1812 struct kvm_lapic_state *s)
96ad2cc6 1813{
ad312c7c 1814 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1815
5dbc8f3f 1816 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1817 /* set SPIV separately to get count of SW disabled APICs right */
1818 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1819 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1820 /* call kvm_apic_set_id() to put apic into apic_map */
1821 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1822 kvm_apic_set_version(vcpu);
1823
96ad2cc6 1824 apic_update_ppr(apic);
d3c7b77d 1825 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 1826 apic_update_lvtt(apic);
db138562 1827 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
96ad2cc6
ED		 1828 update_divide_count(apic);
1829 start_apic_timer(apic);
6e24a6ef 1830 apic->irr_pending = true;
f563db4b 1831 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
c7c9c56c 1832 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1833 apic->highest_isr_cache = -1;
4114c27d
WW		 1834 if (kvm_x86_ops->hwapic_irr_update)
1835 kvm_x86_ops->hwapic_irr_update(vcpu,
1836 apic_find_highest_irr(apic));
b4eef9b3
TC		 1837 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1838 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1839 apic_find_highest_isr(apic));
3842d135 1840 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1841 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1842}
a3d7f85f 1843
2f52d58c 1844void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1845{
a3d7f85f
ED		 1846 struct hrtimer *timer;
1847
c48f1496 1848 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1849 return;
1850
54e9818f 1851 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1852 if (hrtimer_cancel(timer))
beb20d52 1853 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1854}
b93463aa 1855
ae7a2a3f
MT		 1856/*
1857 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1858 *
1859 * Detect whether guest triggered PV EOI since the
1860 * last entry. If yes, set EOI on guests's behalf.
1861 * Clear PV EOI in guest memory in any case.
1862 */
1863static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1864 struct kvm_lapic *apic)
1865{
1866 bool pending;
1867 int vector;
1868 /*
1869 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1870 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1871 *
1872 * KVM_APIC_PV_EOI_PENDING is unset:
1873 * -> host disabled PV EOI.
1874 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1875 * -> host enabled PV EOI, guest did not execute EOI yet.
1876 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1877 * -> host enabled PV EOI, guest executed EOI.
1878 */
1879 BUG_ON(!pv_eoi_enabled(vcpu));
1880 pending = pv_eoi_get_pending(vcpu);
1881 /*
1882 * Clear pending bit in any case: it will be set again on vmentry.
1883 * While this might not be ideal from performance point of view,
1884 * this makes sure pv eoi is only enabled when we know it's safe.
1885 */
1886 pv_eoi_clr_pending(vcpu);
1887 if (pending)
1888 return;
1889 vector = apic_set_eoi(apic);
1890 trace_kvm_pv_eoi(apic, vector);
1891}
1892
b93463aa
AK		 1893void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1894{
1895 u32 data;
b93463aa 1896
ae7a2a3f
MT		 1897 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1898 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1899
41383771 1900 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1901 return;
1902
fda4e2e8
AH		 1903 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1904 sizeof(u32));
b93463aa
AK		 1905
1906 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1907}
1908
ae7a2a3f
MT		 1909/*
1910 * apic_sync_pv_eoi_to_guest - called before vmentry
1911 *
1912 * Detect whether it's safe to enable PV EOI and
1913 * if yes do so.
1914 */
1915static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1916 struct kvm_lapic *apic)
1917{
1918 if (!pv_eoi_enabled(vcpu) ||
1919 /* IRR set or many bits in ISR: could be nested. */
1920 apic->irr_pending ||
1921 /* Cache not set: could be safe but we don't bother. */
1922 apic->highest_isr_cache == -1 ||
1923 /* Need EOI to update ioapic. */
1924 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1925 /*
1926 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1927 * so we need not do anything here.
1928 */
1929 return;
1930 }
1931
1932 pv_eoi_set_pending(apic->vcpu);
1933}
1934
b93463aa
AK		 1935void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1936{
1937 u32 data, tpr;
1938 int max_irr, max_isr;
ae7a2a3f 1939 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1940
ae7a2a3f
MT		 1941 apic_sync_pv_eoi_to_guest(vcpu, apic);
1942
41383771 1943 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1944 return;
1945
c48f1496 1946 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1947 max_irr = apic_find_highest_irr(apic);
1948 if (max_irr < 0)
1949 max_irr = 0;
1950 max_isr = apic_find_highest_isr(apic);
1951 if (max_isr < 0)
1952 max_isr = 0;
1953 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1954
fda4e2e8
AH		 1955 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1956 sizeof(u32));
b93463aa
AK		 1957}
1958
fda4e2e8 1959int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1960{
fda4e2e8
AH		 1961 if (vapic_addr) {
1962 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1963 &vcpu->arch.apic->vapic_cache,
1964 vapic_addr, sizeof(u32)))
1965 return -EINVAL;
41383771 1966 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1967 } else {
41383771 1968 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1969 }
1970
1971 vcpu->arch.apic->vapic_addr = vapic_addr;
1972 return 0;
b93463aa 1973}
0105d1a5
GN		 1974
1975int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1976{
1977 struct kvm_lapic *apic = vcpu->arch.apic;
1978 u32 reg = (msr - APIC_BASE_MSR) << 4;
1979
1980 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1981 return 1;
1982
c69d3d9b
NA		 1983 if (reg == APIC_ICR2)
1984 return 1;
1985
0105d1a5 1986 /* if this is ICR write vector before command */
decdc283 1987 if (reg == APIC_ICR)
0105d1a5
GN		 1988 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1989 return apic_reg_write(apic, reg, (u32)data);
1990}
1991
1992int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1993{
1994 struct kvm_lapic *apic = vcpu->arch.apic;
1995 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1996
1997 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1998 return 1;
1999
c69d3d9b
NA		 2000 if (reg == APIC_DFR || reg == APIC_ICR2) {
2001 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2002 reg);
2003 return 1;
2004 }
2005
0105d1a5
GN		 2006 if (apic_reg_read(apic, reg, 4, &low))
2007 return 1;
decdc283 2008 if (reg == APIC_ICR)
0105d1a5
GN		 2009 apic_reg_read(apic, APIC_ICR2, 4, &high);
2010
2011 *data = (((u64)high) << 32) | low;
2012
2013 return 0;
2014}
10388a07
GN		 2015
2016int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2017{
2018 struct kvm_lapic *apic = vcpu->arch.apic;
2019
c48f1496 2020 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2021 return 1;
2022
2023 /* if this is ICR write vector before command */
2024 if (reg == APIC_ICR)
2025 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2026 return apic_reg_write(apic, reg, (u32)data);
2027}
2028
2029int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2030{
2031 struct kvm_lapic *apic = vcpu->arch.apic;
2032 u32 low, high = 0;
2033
c48f1496 2034 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2035 return 1;
2036
2037 if (apic_reg_read(apic, reg, 4, &low))
2038 return 1;
2039 if (reg == APIC_ICR)
2040 apic_reg_read(apic, APIC_ICR2, 4, &high);
2041
2042 *data = (((u64)high) << 32) | low;
2043
2044 return 0;
2045}
ae7a2a3f
MT		 2046
2047int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2048{
2049 u64 addr = data & ~KVM_MSR_ENABLED;
2050 if (!IS_ALIGNED(addr, 4))
2051 return 1;
2052
2053 vcpu->arch.pv_eoi.msr_val = data;
2054 if (!pv_eoi_enabled(vcpu))
2055 return 0;
2056 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2057 addr, sizeof(u8));
ae7a2a3f 2058}
c5cc421b 2059
66450a21
JK		 2060void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2061{
2062 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2063 u8 sipi_vector;
299018f4 2064 unsigned long pe;
66450a21 2065
299018f4 2066 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2067 return;
2068
cd7764fe
PB		 2069 /*
2070 * INITs are latched while in SMM. Because an SMM CPU cannot
2071 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2072 * and delay processing of INIT until the next RSM.
2073 */
2074 if (is_smm(vcpu)) {
2075 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2076 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2077 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2078 return;
2079 }
299018f4 2080
cd7764fe 2081 pe = xchg(&apic->pending_events, 0);
299018f4 2082 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd
NA		 2083 kvm_lapic_reset(vcpu, true);
2084 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2085 if (kvm_vcpu_is_bsp(apic->vcpu))
2086 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2087 else
2088 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2089 }
299018f4 2090 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2091 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2092 /* evaluate pending_events before reading the vector */
2093 smp_rmb();
2094 sipi_vector = apic->sipi_vector;
98eff52a 2095 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2096 vcpu->vcpu_id, sipi_vector);
2097 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2098 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2099 }
2100}
2101
c5cc421b
GN		 2102void kvm_lapic_init(void)
2103{
2104 /* do not patch jump label more than once per second */
2105 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2106 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2107}
Linux kernel - Deliverables
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