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82470196 ZX |
1 | #ifndef __KVM_X86_LAPIC_H |
2 | #define __KVM_X86_LAPIC_H | |
3 | ||
af669ac6 | 4 | #include <kvm/iodev.h> |
82470196 ZX |
5 | |
6 | #include <linux/kvm_host.h> | |
7 | ||
66450a21 JK |
8 | #define KVM_APIC_INIT 0 |
9 | #define KVM_APIC_SIPI 1 | |
1e6e2755 | 10 | #define KVM_APIC_LVT_NUM 6 |
66450a21 | 11 | |
18f40c53 SS |
12 | #define KVM_APIC_SHORT_MASK 0xc0000 |
13 | #define KVM_APIC_DEST_MASK 0x800 | |
14 | ||
e9d90d47 AK |
15 | struct kvm_timer { |
16 | struct hrtimer timer; | |
17 | s64 period; /* unit: ns */ | |
a323b409 | 18 | u32 timer_mode; |
e9d90d47 AK |
19 | u32 timer_mode_mask; |
20 | u64 tscdeadline; | |
d0659d94 | 21 | u64 expired_tscdeadline; |
e9d90d47 | 22 | atomic_t pending; /* accumulated triggered timers */ |
e9d90d47 AK |
23 | }; |
24 | ||
82470196 ZX |
25 | struct kvm_lapic { |
26 | unsigned long base_address; | |
27 | struct kvm_io_device dev; | |
d3c7b77d MT |
28 | struct kvm_timer lapic_timer; |
29 | u32 divide_count; | |
82470196 | 30 | struct kvm_vcpu *vcpu; |
e462755c | 31 | bool sw_enabled; |
33e4c686 | 32 | bool irr_pending; |
59fd1323 | 33 | bool lvt0_in_nmi_mode; |
8680b94b MT |
34 | /* Number of bits set in ISR. */ |
35 | s16 isr_count; | |
36 | /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ | |
37 | int highest_isr_cache; | |
5eadf916 MT |
38 | /** |
39 | * APIC register page. The layout matches the register layout seen by | |
40 | * the guest 1:1, because it is accessed by the vmx microcode. | |
41 | * Note: Only one register, the TPR, is used by the microcode. | |
42 | */ | |
82470196 | 43 | void *regs; |
b93463aa | 44 | gpa_t vapic_addr; |
fda4e2e8 | 45 | struct gfn_to_hva_cache vapic_cache; |
66450a21 JK |
46 | unsigned long pending_events; |
47 | unsigned int sipi_vector; | |
82470196 | 48 | }; |
9e4aabe2 JR |
49 | |
50 | struct dest_map; | |
51 | ||
82470196 ZX |
52 | int kvm_create_lapic(struct kvm_vcpu *vcpu); |
53 | void kvm_free_lapic(struct kvm_vcpu *vcpu); | |
54 | ||
55 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); | |
56 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); | |
57 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); | |
66450a21 | 58 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu); |
d28bc9dd | 59 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); |
82470196 ZX |
60 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); |
61 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); | |
58fbbf26 | 62 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); |
82470196 | 63 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); |
8b2cf73c | 64 | u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); |
fc61b800 | 65 | void kvm_apic_set_version(struct kvm_vcpu *vcpu); |
1e6e2755 SS |
66 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); |
67 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, | |
68 | void *data); | |
69 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, | |
70 | int short_hand, unsigned int dest, int dest_mode); | |
82470196 | 71 | |
705699a1 | 72 | void __kvm_apic_update_irr(u32 *pir, void *regs); |
a20ed54d | 73 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir); |
b4f2225c | 74 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 75 | struct dest_map *dest_map); |
89342082 | 76 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); |
82470196 | 77 | |
1e08ec4a | 78 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
9e4aabe2 | 79 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); |
1e08ec4a | 80 | |
82470196 | 81 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
58cb628d | 82 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); |
64eb0620 GN |
83 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
84 | struct kvm_lapic_state *s); | |
82470196 | 85 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); |
82470196 | 86 | |
a3e06bbe LJ |
87 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); |
88 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); | |
89 | ||
83d4c286 | 90 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); |
c7c9c56c | 91 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); |
83d4c286 | 92 | |
fda4e2e8 | 93 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); |
b93463aa AK |
94 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); |
95 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); | |
96 | ||
0105d1a5 GN |
97 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); |
98 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
10388a07 GN |
99 | |
100 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
101 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
102 | ||
103 | static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) | |
104 | { | |
e83d5887 | 105 | return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE; |
10388a07 | 106 | } |
ae7a2a3f MT |
107 | |
108 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data); | |
c5cc421b | 109 | void kvm_lapic_init(void); |
c48f1496 | 110 | |
1e6e2755 SS |
111 | #define VEC_POS(v) ((v) & (32 - 1)) |
112 | #define REG_POS(v) (((v) >> 5) << 4) | |
113 | ||
114 | static inline void kvm_lapic_set_vector(int vec, void *bitmap) | |
115 | { | |
116 | set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
117 | } | |
118 | ||
119 | static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) | |
120 | { | |
121 | kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); | |
122 | /* | |
123 | * irr_pending must be true if any interrupt is pending; set it after | |
124 | * APIC_IRR to avoid race with apic_clear_irr | |
125 | */ | |
126 | apic->irr_pending = true; | |
127 | } | |
128 | ||
dfb95954 | 129 | static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) |
c48f1496 | 130 | { |
dfb95954 | 131 | return *((u32 *) (apic->regs + reg_off)); |
c48f1496 GN |
132 | } |
133 | ||
1e6e2755 SS |
134 | static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) |
135 | { | |
136 | *((u32 *) (apic->regs + reg_off)) = val; | |
137 | } | |
138 | ||
c48f1496 GN |
139 | extern struct static_key kvm_no_apic_vcpu; |
140 | ||
bce87cce | 141 | static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) |
c48f1496 GN |
142 | { |
143 | if (static_key_false(&kvm_no_apic_vcpu)) | |
144 | return vcpu->arch.apic; | |
145 | return true; | |
146 | } | |
147 | ||
148 | extern struct static_key_deferred apic_hw_disabled; | |
149 | ||
150 | static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) | |
151 | { | |
152 | if (static_key_false(&apic_hw_disabled.key)) | |
153 | return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; | |
154 | return MSR_IA32_APICBASE_ENABLE; | |
155 | } | |
156 | ||
157 | extern struct static_key_deferred apic_sw_disabled; | |
158 | ||
f30ebc31 | 159 | static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) |
c48f1496 GN |
160 | { |
161 | if (static_key_false(&apic_sw_disabled.key)) | |
f30ebc31 RK |
162 | return apic->sw_enabled; |
163 | return true; | |
c48f1496 GN |
164 | } |
165 | ||
166 | static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) | |
167 | { | |
bce87cce | 168 | return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); |
c48f1496 GN |
169 | } |
170 | ||
171 | static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) | |
172 | { | |
173 | return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); | |
174 | } | |
175 | ||
8d14695f YZ |
176 | static inline int apic_x2apic_mode(struct kvm_lapic *apic) |
177 | { | |
178 | return apic->vcpu->arch.apic_base & X2APIC_ENABLE; | |
179 | } | |
180 | ||
d62caabb | 181 | static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) |
c7c9c56c | 182 | { |
d62caabb | 183 | return vcpu->arch.apic && vcpu->arch.apicv_active; |
c7c9c56c YZ |
184 | } |
185 | ||
66450a21 JK |
186 | static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) |
187 | { | |
bce87cce | 188 | return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; |
66450a21 JK |
189 | } |
190 | ||
d1ebdbf9 JS |
191 | static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) |
192 | { | |
193 | return (irq->delivery_mode == APIC_DM_LOWEST || | |
194 | irq->msi_redir_hint); | |
195 | } | |
196 | ||
f077825a PB |
197 | static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) |
198 | { | |
bce87cce | 199 | return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); |
f077825a PB |
200 | } |
201 | ||
5c919412 AS |
202 | static inline int kvm_apic_id(struct kvm_lapic *apic) |
203 | { | |
dfb95954 | 204 | return (kvm_lapic_get_reg(apic, APIC_ID) >> 24) & 0xff; |
5c919412 AS |
205 | } |
206 | ||
10606919 YZ |
207 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); |
208 | ||
d0659d94 MT |
209 | void wait_lapic_expire(struct kvm_vcpu *vcpu); |
210 | ||
8feb4a04 FW |
211 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
212 | struct kvm_vcpu **dest_vcpu); | |
52004014 FW |
213 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
214 | const unsigned long *bitmap, u32 bitmap_size); | |
82470196 | 215 | #endif |