Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
1d737c8a | 21 | #include "mmu.h" |
836a1b3c | 22 | #include "x86.h" |
6de4f3ad | 23 | #include "kvm_cache_regs.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
30 | #include <linux/module.h> | |
448353ca | 31 | #include <linux/swap.h> |
05da4558 | 32 | #include <linux/hugetlb.h> |
2f333bcb | 33 | #include <linux/compiler.h> |
bc6678a3 | 34 | #include <linux/srcu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bf998156 | 36 | #include <linux/uaccess.h> |
6aa8b732 | 37 | |
e495606d AK |
38 | #include <asm/page.h> |
39 | #include <asm/cmpxchg.h> | |
4e542370 | 40 | #include <asm/io.h> |
13673a90 | 41 | #include <asm/vmx.h> |
6aa8b732 | 42 | |
18552672 JR |
43 | /* |
44 | * When setting this variable to true it enables Two-Dimensional-Paging | |
45 | * where the hardware walks 2 page tables: | |
46 | * 1. the guest-virtual to guest-physical | |
47 | * 2. while doing 1. it walks guest-physical to host-physical | |
48 | * If the hardware supports that we don't need to do shadow paging. | |
49 | */ | |
2f333bcb | 50 | bool tdp_enabled = false; |
18552672 | 51 | |
8b1fe17c XG |
52 | enum { |
53 | AUDIT_PRE_PAGE_FAULT, | |
54 | AUDIT_POST_PAGE_FAULT, | |
55 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
56 | AUDIT_POST_PTE_WRITE, |
57 | AUDIT_PRE_SYNC, | |
58 | AUDIT_POST_SYNC | |
8b1fe17c | 59 | }; |
37a7d8b0 | 60 | |
8b1fe17c XG |
61 | char *audit_point_name[] = { |
62 | "pre page fault", | |
63 | "post page fault", | |
64 | "pre pte write", | |
6903074c XG |
65 | "post pte write", |
66 | "pre sync", | |
67 | "post sync" | |
8b1fe17c | 68 | }; |
37a7d8b0 | 69 | |
8b1fe17c | 70 | #undef MMU_DEBUG |
37a7d8b0 AK |
71 | |
72 | #ifdef MMU_DEBUG | |
73 | ||
74 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
75 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
76 | ||
77 | #else | |
78 | ||
79 | #define pgprintk(x...) do { } while (0) | |
80 | #define rmap_printk(x...) do { } while (0) | |
81 | ||
82 | #endif | |
83 | ||
8b1fe17c | 84 | #ifdef MMU_DEBUG |
6ada8cca AK |
85 | static int dbg = 0; |
86 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 87 | #endif |
6aa8b732 | 88 | |
582801a9 MT |
89 | static int oos_shadow = 1; |
90 | module_param(oos_shadow, bool, 0644); | |
91 | ||
d6c69ee9 YD |
92 | #ifndef MMU_DEBUG |
93 | #define ASSERT(x) do { } while (0) | |
94 | #else | |
6aa8b732 AK |
95 | #define ASSERT(x) \ |
96 | if (!(x)) { \ | |
97 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
98 | __FILE__, __LINE__, #x); \ | |
99 | } | |
d6c69ee9 | 100 | #endif |
6aa8b732 | 101 | |
957ed9ef XG |
102 | #define PTE_PREFETCH_NUM 8 |
103 | ||
6aa8b732 AK |
104 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
105 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
106 | ||
6aa8b732 AK |
107 | #define PT64_LEVEL_BITS 9 |
108 | ||
109 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 110 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
111 | |
112 | #define PT64_LEVEL_MASK(level) \ | |
113 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
114 | ||
115 | #define PT64_INDEX(address, level)\ | |
116 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
117 | ||
118 | ||
119 | #define PT32_LEVEL_BITS 10 | |
120 | ||
121 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 122 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
123 | |
124 | #define PT32_LEVEL_MASK(level) \ | |
125 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
126 | #define PT32_LVL_OFFSET_MASK(level) \ |
127 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
128 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
129 | |
130 | #define PT32_INDEX(address, level)\ | |
131 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
132 | ||
133 | ||
27aba766 | 134 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
135 | #define PT64_DIR_BASE_ADDR_MASK \ |
136 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
137 | #define PT64_LVL_ADDR_MASK(level) \ |
138 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
139 | * PT64_LEVEL_BITS))) - 1)) | |
140 | #define PT64_LVL_OFFSET_MASK(level) \ | |
141 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
142 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
143 | |
144 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
145 | #define PT32_DIR_BASE_ADDR_MASK \ | |
146 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
147 | #define PT32_LVL_ADDR_MASK(level) \ |
148 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
149 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 150 | |
79539cec AK |
151 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
152 | | PT64_NX_MASK) | |
6aa8b732 | 153 | |
cd4a4e53 AK |
154 | #define RMAP_EXT 4 |
155 | ||
fe135d2c AK |
156 | #define ACC_EXEC_MASK 1 |
157 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
158 | #define ACC_USER_MASK PT_USER_MASK | |
159 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
160 | ||
90bb6fc5 AK |
161 | #include <trace/events/kvm.h> |
162 | ||
07420171 AK |
163 | #define CREATE_TRACE_POINTS |
164 | #include "mmutrace.h" | |
165 | ||
1403283a IE |
166 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
167 | ||
135f8c2b AK |
168 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
169 | ||
cd4a4e53 | 170 | struct kvm_rmap_desc { |
d555c333 | 171 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
172 | struct kvm_rmap_desc *more; |
173 | }; | |
174 | ||
2d11123a AK |
175 | struct kvm_shadow_walk_iterator { |
176 | u64 addr; | |
177 | hpa_t shadow_addr; | |
178 | int level; | |
179 | u64 *sptep; | |
180 | unsigned index; | |
181 | }; | |
182 | ||
183 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
184 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
185 | shadow_walk_okay(&(_walker)); \ | |
186 | shadow_walk_next(&(_walker))) | |
187 | ||
1047df1f | 188 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 189 | |
b5a33a75 AK |
190 | static struct kmem_cache *pte_chain_cache; |
191 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 192 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 193 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 194 | |
c7addb90 AK |
195 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
196 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
197 | static u64 __read_mostly shadow_base_present_pte; |
198 | static u64 __read_mostly shadow_nx_mask; | |
199 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
200 | static u64 __read_mostly shadow_user_mask; | |
201 | static u64 __read_mostly shadow_accessed_mask; | |
202 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 203 | |
82725b20 DE |
204 | static inline u64 rsvd_bits(int s, int e) |
205 | { | |
206 | return ((1ULL << (e - s + 1)) - 1) << s; | |
207 | } | |
208 | ||
c7addb90 AK |
209 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
210 | { | |
211 | shadow_trap_nonpresent_pte = trap_pte; | |
212 | shadow_notrap_nonpresent_pte = notrap_pte; | |
213 | } | |
214 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
215 | ||
7b52345e SY |
216 | void kvm_mmu_set_base_ptes(u64 base_pte) |
217 | { | |
218 | shadow_base_present_pte = base_pte; | |
219 | } | |
220 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
221 | ||
222 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 223 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
224 | { |
225 | shadow_user_mask = user_mask; | |
226 | shadow_accessed_mask = accessed_mask; | |
227 | shadow_dirty_mask = dirty_mask; | |
228 | shadow_nx_mask = nx_mask; | |
229 | shadow_x_mask = x_mask; | |
230 | } | |
231 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
232 | ||
3dbe1415 | 233 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 234 | { |
4d4ec087 | 235 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
236 | } |
237 | ||
238 | static int is_cpuid_PSE36(void) | |
239 | { | |
240 | return 1; | |
241 | } | |
242 | ||
73b1087e AK |
243 | static int is_nx(struct kvm_vcpu *vcpu) |
244 | { | |
f6801dff | 245 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
246 | } |
247 | ||
c7addb90 AK |
248 | static int is_shadow_present_pte(u64 pte) |
249 | { | |
c7addb90 AK |
250 | return pte != shadow_trap_nonpresent_pte |
251 | && pte != shadow_notrap_nonpresent_pte; | |
252 | } | |
253 | ||
05da4558 MT |
254 | static int is_large_pte(u64 pte) |
255 | { | |
256 | return pte & PT_PAGE_SIZE_MASK; | |
257 | } | |
258 | ||
8dae4445 | 259 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
260 | { |
261 | return pte & PT_WRITABLE_MASK; | |
262 | } | |
263 | ||
43a3795a | 264 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 265 | { |
439e218a | 266 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
267 | } |
268 | ||
43a3795a | 269 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 270 | { |
4b1a80fa | 271 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
272 | } |
273 | ||
776e6633 MT |
274 | static int is_last_spte(u64 pte, int level) |
275 | { | |
276 | if (level == PT_PAGE_TABLE_LEVEL) | |
277 | return 1; | |
852e3c19 | 278 | if (is_large_pte(pte)) |
776e6633 MT |
279 | return 1; |
280 | return 0; | |
281 | } | |
282 | ||
35149e21 | 283 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 284 | { |
35149e21 | 285 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
286 | } |
287 | ||
da928521 AK |
288 | static gfn_t pse36_gfn_delta(u32 gpte) |
289 | { | |
290 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
291 | ||
292 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
293 | } | |
294 | ||
d555c333 | 295 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 296 | { |
7645e432 | 297 | set_64bit(sptep, spte); |
e663ee64 AK |
298 | } |
299 | ||
a9221dd5 AK |
300 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
301 | { | |
302 | #ifdef CONFIG_X86_64 | |
303 | return xchg(sptep, new_spte); | |
304 | #else | |
305 | u64 old_spte; | |
306 | ||
307 | do { | |
308 | old_spte = *sptep; | |
309 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
310 | ||
311 | return old_spte; | |
312 | #endif | |
313 | } | |
314 | ||
8672b721 XG |
315 | static bool spte_has_volatile_bits(u64 spte) |
316 | { | |
317 | if (!shadow_accessed_mask) | |
318 | return false; | |
319 | ||
320 | if (!is_shadow_present_pte(spte)) | |
321 | return false; | |
322 | ||
4132779b XG |
323 | if ((spte & shadow_accessed_mask) && |
324 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
325 | return false; |
326 | ||
327 | return true; | |
328 | } | |
329 | ||
4132779b XG |
330 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
331 | { | |
332 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
333 | } | |
334 | ||
b79b93f9 AK |
335 | static void update_spte(u64 *sptep, u64 new_spte) |
336 | { | |
4132779b XG |
337 | u64 mask, old_spte = *sptep; |
338 | ||
339 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 340 | |
4132779b XG |
341 | new_spte |= old_spte & shadow_dirty_mask; |
342 | ||
343 | mask = shadow_accessed_mask; | |
344 | if (is_writable_pte(old_spte)) | |
345 | mask |= shadow_dirty_mask; | |
346 | ||
347 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 348 | __set_spte(sptep, new_spte); |
4132779b | 349 | else |
b79b93f9 | 350 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
351 | |
352 | if (!shadow_accessed_mask) | |
353 | return; | |
354 | ||
355 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
356 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
357 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
358 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
359 | } |
360 | ||
e2dec939 | 361 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 362 | struct kmem_cache *base_cache, int min) |
714b93da AK |
363 | { |
364 | void *obj; | |
365 | ||
366 | if (cache->nobjs >= min) | |
e2dec939 | 367 | return 0; |
714b93da | 368 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 369 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 370 | if (!obj) |
e2dec939 | 371 | return -ENOMEM; |
714b93da AK |
372 | cache->objects[cache->nobjs++] = obj; |
373 | } | |
e2dec939 | 374 | return 0; |
714b93da AK |
375 | } |
376 | ||
e8ad9a70 XG |
377 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
378 | struct kmem_cache *cache) | |
714b93da AK |
379 | { |
380 | while (mc->nobjs) | |
e8ad9a70 | 381 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
382 | } |
383 | ||
c1158e63 | 384 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 385 | int min) |
c1158e63 AK |
386 | { |
387 | struct page *page; | |
388 | ||
389 | if (cache->nobjs >= min) | |
390 | return 0; | |
391 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 392 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
393 | if (!page) |
394 | return -ENOMEM; | |
c1158e63 AK |
395 | cache->objects[cache->nobjs++] = page_address(page); |
396 | } | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
401 | { | |
402 | while (mc->nobjs) | |
c4d198d5 | 403 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
404 | } |
405 | ||
2e3e5882 | 406 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 407 | { |
e2dec939 AK |
408 | int r; |
409 | ||
ad312c7c | 410 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 411 | pte_chain_cache, 4); |
e2dec939 AK |
412 | if (r) |
413 | goto out; | |
ad312c7c | 414 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
957ed9ef | 415 | rmap_desc_cache, 4 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
416 | if (r) |
417 | goto out; | |
ad312c7c | 418 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
419 | if (r) |
420 | goto out; | |
ad312c7c | 421 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 422 | mmu_page_header_cache, 4); |
e2dec939 AK |
423 | out: |
424 | return r; | |
714b93da AK |
425 | } |
426 | ||
427 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
428 | { | |
e8ad9a70 XG |
429 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
430 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 431 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
432 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
433 | mmu_page_header_cache); | |
714b93da AK |
434 | } |
435 | ||
436 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
437 | size_t size) | |
438 | { | |
439 | void *p; | |
440 | ||
441 | BUG_ON(!mc->nobjs); | |
442 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
443 | return p; |
444 | } | |
445 | ||
714b93da AK |
446 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
447 | { | |
ad312c7c | 448 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
449 | sizeof(struct kvm_pte_chain)); |
450 | } | |
451 | ||
90cb0529 | 452 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 453 | { |
e8ad9a70 | 454 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
455 | } |
456 | ||
457 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
458 | { | |
ad312c7c | 459 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
460 | sizeof(struct kvm_rmap_desc)); |
461 | } | |
462 | ||
90cb0529 | 463 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 464 | { |
e8ad9a70 | 465 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
466 | } |
467 | ||
2032a93d LJ |
468 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
469 | { | |
470 | if (!sp->role.direct) | |
471 | return sp->gfns[index]; | |
472 | ||
473 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
474 | } | |
475 | ||
476 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
477 | { | |
478 | if (sp->role.direct) | |
479 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
480 | else | |
481 | sp->gfns[index] = gfn; | |
482 | } | |
483 | ||
05da4558 MT |
484 | /* |
485 | * Return the pointer to the largepage write count for a given | |
486 | * gfn, handling slots that are not large page aligned. | |
487 | */ | |
d25797b2 JR |
488 | static int *slot_largepage_idx(gfn_t gfn, |
489 | struct kvm_memory_slot *slot, | |
490 | int level) | |
05da4558 MT |
491 | { |
492 | unsigned long idx; | |
493 | ||
82855413 JR |
494 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
495 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 496 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
497 | } |
498 | ||
499 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
500 | { | |
d25797b2 | 501 | struct kvm_memory_slot *slot; |
05da4558 | 502 | int *write_count; |
d25797b2 | 503 | int i; |
05da4558 | 504 | |
a1f4d395 | 505 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
506 | for (i = PT_DIRECTORY_LEVEL; |
507 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
508 | write_count = slot_largepage_idx(gfn, slot, i); | |
509 | *write_count += 1; | |
510 | } | |
05da4558 MT |
511 | } |
512 | ||
513 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
514 | { | |
d25797b2 | 515 | struct kvm_memory_slot *slot; |
05da4558 | 516 | int *write_count; |
d25797b2 | 517 | int i; |
05da4558 | 518 | |
a1f4d395 | 519 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
520 | for (i = PT_DIRECTORY_LEVEL; |
521 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
522 | write_count = slot_largepage_idx(gfn, slot, i); |
523 | *write_count -= 1; | |
524 | WARN_ON(*write_count < 0); | |
525 | } | |
05da4558 MT |
526 | } |
527 | ||
d25797b2 JR |
528 | static int has_wrprotected_page(struct kvm *kvm, |
529 | gfn_t gfn, | |
530 | int level) | |
05da4558 | 531 | { |
2843099f | 532 | struct kvm_memory_slot *slot; |
05da4558 MT |
533 | int *largepage_idx; |
534 | ||
a1f4d395 | 535 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 536 | if (slot) { |
d25797b2 | 537 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
538 | return *largepage_idx; |
539 | } | |
540 | ||
541 | return 1; | |
542 | } | |
543 | ||
d25797b2 | 544 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 545 | { |
8f0b1ab6 | 546 | unsigned long page_size; |
d25797b2 | 547 | int i, ret = 0; |
05da4558 | 548 | |
8f0b1ab6 | 549 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 550 | |
d25797b2 JR |
551 | for (i = PT_PAGE_TABLE_LEVEL; |
552 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
553 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
554 | ret = i; | |
555 | else | |
556 | break; | |
557 | } | |
558 | ||
4c2155ce | 559 | return ret; |
05da4558 MT |
560 | } |
561 | ||
d25797b2 | 562 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
563 | { |
564 | struct kvm_memory_slot *slot; | |
878403b7 | 565 | int host_level, level, max_level; |
05da4558 MT |
566 | |
567 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
568 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 569 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 570 | |
d25797b2 JR |
571 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
572 | ||
573 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
574 | return host_level; | |
575 | ||
878403b7 SY |
576 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
577 | kvm_x86_ops->get_lpage_level() : host_level; | |
578 | ||
579 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
580 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
581 | break; | |
d25797b2 JR |
582 | |
583 | return level - 1; | |
05da4558 MT |
584 | } |
585 | ||
290fc38d IE |
586 | /* |
587 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
588 | */ |
589 | ||
44ad9944 | 590 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
591 | { |
592 | struct kvm_memory_slot *slot; | |
05da4558 | 593 | unsigned long idx; |
290fc38d IE |
594 | |
595 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 596 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
597 | return &slot->rmap[gfn - slot->base_gfn]; |
598 | ||
82855413 JR |
599 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
600 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 601 | |
44ad9944 | 602 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
603 | } |
604 | ||
cd4a4e53 AK |
605 | /* |
606 | * Reverse mapping data structures: | |
607 | * | |
290fc38d IE |
608 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
609 | * that points to page_address(page). | |
cd4a4e53 | 610 | * |
290fc38d IE |
611 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
612 | * containing more mappings. | |
53a27b39 MT |
613 | * |
614 | * Returns the number of rmap entries before the spte was added or zero if | |
615 | * the spte was not added. | |
616 | * | |
cd4a4e53 | 617 | */ |
44ad9944 | 618 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 619 | { |
4db35314 | 620 | struct kvm_mmu_page *sp; |
cd4a4e53 | 621 | struct kvm_rmap_desc *desc; |
290fc38d | 622 | unsigned long *rmapp; |
53a27b39 | 623 | int i, count = 0; |
cd4a4e53 | 624 | |
43a3795a | 625 | if (!is_rmap_spte(*spte)) |
53a27b39 | 626 | return count; |
4db35314 | 627 | sp = page_header(__pa(spte)); |
2032a93d | 628 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 629 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 630 | if (!*rmapp) { |
cd4a4e53 | 631 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
632 | *rmapp = (unsigned long)spte; |
633 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 634 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 635 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
636 | desc->sptes[0] = (u64 *)*rmapp; |
637 | desc->sptes[1] = spte; | |
290fc38d | 638 | *rmapp = (unsigned long)desc | 1; |
cb16a7b3 | 639 | ++count; |
cd4a4e53 AK |
640 | } else { |
641 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 642 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 643 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 644 | desc = desc->more; |
53a27b39 MT |
645 | count += RMAP_EXT; |
646 | } | |
d555c333 | 647 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 648 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
649 | desc = desc->more; |
650 | } | |
d555c333 | 651 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 652 | ++count; |
d555c333 | 653 | desc->sptes[i] = spte; |
cd4a4e53 | 654 | } |
53a27b39 | 655 | return count; |
cd4a4e53 AK |
656 | } |
657 | ||
290fc38d | 658 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
659 | struct kvm_rmap_desc *desc, |
660 | int i, | |
661 | struct kvm_rmap_desc *prev_desc) | |
662 | { | |
663 | int j; | |
664 | ||
d555c333 | 665 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 666 | ; |
d555c333 AK |
667 | desc->sptes[i] = desc->sptes[j]; |
668 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
669 | if (j != 0) |
670 | return; | |
671 | if (!prev_desc && !desc->more) | |
d555c333 | 672 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
673 | else |
674 | if (prev_desc) | |
675 | prev_desc->more = desc->more; | |
676 | else | |
290fc38d | 677 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 678 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
679 | } |
680 | ||
290fc38d | 681 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 682 | { |
cd4a4e53 AK |
683 | struct kvm_rmap_desc *desc; |
684 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 685 | struct kvm_mmu_page *sp; |
2032a93d | 686 | gfn_t gfn; |
290fc38d | 687 | unsigned long *rmapp; |
cd4a4e53 AK |
688 | int i; |
689 | ||
4db35314 | 690 | sp = page_header(__pa(spte)); |
2032a93d LJ |
691 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
692 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 693 | if (!*rmapp) { |
19ada5c4 | 694 | printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 695 | BUG(); |
290fc38d | 696 | } else if (!(*rmapp & 1)) { |
19ada5c4 | 697 | rmap_printk("rmap_remove: %p 1->0\n", spte); |
290fc38d | 698 | if ((u64 *)*rmapp != spte) { |
19ada5c4 | 699 | printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
700 | BUG(); |
701 | } | |
290fc38d | 702 | *rmapp = 0; |
cd4a4e53 | 703 | } else { |
19ada5c4 | 704 | rmap_printk("rmap_remove: %p many->many\n", spte); |
290fc38d | 705 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
706 | prev_desc = NULL; |
707 | while (desc) { | |
d555c333 AK |
708 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
709 | if (desc->sptes[i] == spte) { | |
290fc38d | 710 | rmap_desc_remove_entry(rmapp, |
714b93da | 711 | desc, i, |
cd4a4e53 AK |
712 | prev_desc); |
713 | return; | |
714 | } | |
715 | prev_desc = desc; | |
716 | desc = desc->more; | |
717 | } | |
19ada5c4 | 718 | pr_err("rmap_remove: %p many->many\n", spte); |
cd4a4e53 AK |
719 | BUG(); |
720 | } | |
721 | } | |
722 | ||
eb45fda4 | 723 | static int set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 724 | { |
ce061867 | 725 | pfn_t pfn; |
9a3aad70 XG |
726 | u64 old_spte = *sptep; |
727 | ||
8672b721 | 728 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 729 | __set_spte(sptep, new_spte); |
8672b721 | 730 | else |
9a3aad70 | 731 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 732 | |
a9221dd5 | 733 | if (!is_rmap_spte(old_spte)) |
eb45fda4 | 734 | return 0; |
8672b721 | 735 | |
a9221dd5 | 736 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 737 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 738 | kvm_set_pfn_accessed(pfn); |
4132779b | 739 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 740 | kvm_set_pfn_dirty(pfn); |
eb45fda4 | 741 | return 1; |
e4b502ea XG |
742 | } |
743 | ||
744 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
745 | { | |
eb45fda4 MT |
746 | if (set_spte_track_bits(sptep, new_spte)) |
747 | rmap_remove(kvm, sptep); | |
be38d276 AK |
748 | } |
749 | ||
98348e95 | 750 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 751 | { |
374cbac0 | 752 | struct kvm_rmap_desc *desc; |
98348e95 IE |
753 | u64 *prev_spte; |
754 | int i; | |
755 | ||
756 | if (!*rmapp) | |
757 | return NULL; | |
758 | else if (!(*rmapp & 1)) { | |
759 | if (!spte) | |
760 | return (u64 *)*rmapp; | |
761 | return NULL; | |
762 | } | |
763 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
764 | prev_spte = NULL; |
765 | while (desc) { | |
d555c333 | 766 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 767 | if (prev_spte == spte) |
d555c333 AK |
768 | return desc->sptes[i]; |
769 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
770 | } |
771 | desc = desc->more; | |
772 | } | |
773 | return NULL; | |
774 | } | |
775 | ||
b1a36821 | 776 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 777 | { |
290fc38d | 778 | unsigned long *rmapp; |
374cbac0 | 779 | u64 *spte; |
44ad9944 | 780 | int i, write_protected = 0; |
374cbac0 | 781 | |
44ad9944 | 782 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 783 | |
98348e95 IE |
784 | spte = rmap_next(kvm, rmapp, NULL); |
785 | while (spte) { | |
374cbac0 | 786 | BUG_ON(!spte); |
374cbac0 | 787 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 788 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 789 | if (is_writable_pte(*spte)) { |
b79b93f9 | 790 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
791 | write_protected = 1; |
792 | } | |
9647c14c | 793 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 794 | } |
855149aa | 795 | |
05da4558 | 796 | /* check for huge page mappings */ |
44ad9944 JR |
797 | for (i = PT_DIRECTORY_LEVEL; |
798 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
799 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
800 | spte = rmap_next(kvm, rmapp, NULL); | |
801 | while (spte) { | |
802 | BUG_ON(!spte); | |
803 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
804 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
805 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 806 | if (is_writable_pte(*spte)) { |
be38d276 AK |
807 | drop_spte(kvm, spte, |
808 | shadow_trap_nonpresent_pte); | |
44ad9944 | 809 | --kvm->stat.lpages; |
44ad9944 JR |
810 | spte = NULL; |
811 | write_protected = 1; | |
812 | } | |
813 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 814 | } |
05da4558 MT |
815 | } |
816 | ||
b1a36821 | 817 | return write_protected; |
374cbac0 AK |
818 | } |
819 | ||
8a8365c5 FD |
820 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
821 | unsigned long data) | |
e930bffe AA |
822 | { |
823 | u64 *spte; | |
824 | int need_tlb_flush = 0; | |
825 | ||
826 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
827 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
828 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 829 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
830 | need_tlb_flush = 1; |
831 | } | |
832 | return need_tlb_flush; | |
833 | } | |
834 | ||
8a8365c5 FD |
835 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
836 | unsigned long data) | |
3da0dd43 IE |
837 | { |
838 | int need_flush = 0; | |
e4b502ea | 839 | u64 *spte, new_spte; |
3da0dd43 IE |
840 | pte_t *ptep = (pte_t *)data; |
841 | pfn_t new_pfn; | |
842 | ||
843 | WARN_ON(pte_huge(*ptep)); | |
844 | new_pfn = pte_pfn(*ptep); | |
845 | spte = rmap_next(kvm, rmapp, NULL); | |
846 | while (spte) { | |
847 | BUG_ON(!is_shadow_present_pte(*spte)); | |
848 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
849 | need_flush = 1; | |
850 | if (pte_write(*ptep)) { | |
be38d276 | 851 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
852 | spte = rmap_next(kvm, rmapp, NULL); |
853 | } else { | |
854 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
855 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
856 | ||
857 | new_spte &= ~PT_WRITABLE_MASK; | |
858 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 859 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 860 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
861 | spte = rmap_next(kvm, rmapp, spte); |
862 | } | |
863 | } | |
864 | if (need_flush) | |
865 | kvm_flush_remote_tlbs(kvm); | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
8a8365c5 FD |
870 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
871 | unsigned long data, | |
3da0dd43 | 872 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 873 | unsigned long data)) |
e930bffe | 874 | { |
852e3c19 | 875 | int i, j; |
90bb6fc5 | 876 | int ret; |
e930bffe | 877 | int retval = 0; |
bc6678a3 MT |
878 | struct kvm_memslots *slots; |
879 | ||
90d83dc3 | 880 | slots = kvm_memslots(kvm); |
e930bffe | 881 | |
46a26bf5 MT |
882 | for (i = 0; i < slots->nmemslots; i++) { |
883 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
884 | unsigned long start = memslot->userspace_addr; |
885 | unsigned long end; | |
886 | ||
e930bffe AA |
887 | end = start + (memslot->npages << PAGE_SHIFT); |
888 | if (hva >= start && hva < end) { | |
889 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 890 | |
90bb6fc5 | 891 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
892 | |
893 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
6e3e243c AA |
894 | unsigned long idx; |
895 | int sh; | |
896 | ||
897 | sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j); | |
898 | idx = ((memslot->base_gfn+gfn_offset) >> sh) - | |
899 | (memslot->base_gfn >> sh); | |
90bb6fc5 | 900 | ret |= handler(kvm, |
3da0dd43 IE |
901 | &memslot->lpage_info[j][idx].rmap_pde, |
902 | data); | |
852e3c19 | 903 | } |
90bb6fc5 AK |
904 | trace_kvm_age_page(hva, memslot, ret); |
905 | retval |= ret; | |
e930bffe AA |
906 | } |
907 | } | |
908 | ||
909 | return retval; | |
910 | } | |
911 | ||
912 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
913 | { | |
3da0dd43 IE |
914 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
915 | } | |
916 | ||
917 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
918 | { | |
8a8365c5 | 919 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
920 | } |
921 | ||
8a8365c5 FD |
922 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
923 | unsigned long data) | |
e930bffe AA |
924 | { |
925 | u64 *spte; | |
926 | int young = 0; | |
927 | ||
6316e1c8 RR |
928 | /* |
929 | * Emulate the accessed bit for EPT, by checking if this page has | |
930 | * an EPT mapping, and clearing it if it does. On the next access, | |
931 | * a new EPT mapping will be established. | |
932 | * This has some overhead, but not as much as the cost of swapping | |
933 | * out actively used pages or breaking up actively used hugepages. | |
934 | */ | |
534e38b4 | 935 | if (!shadow_accessed_mask) |
6316e1c8 | 936 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 937 | |
e930bffe AA |
938 | spte = rmap_next(kvm, rmapp, NULL); |
939 | while (spte) { | |
940 | int _young; | |
941 | u64 _spte = *spte; | |
942 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
943 | _young = _spte & PT_ACCESSED_MASK; | |
944 | if (_young) { | |
945 | young = 1; | |
946 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
947 | } | |
948 | spte = rmap_next(kvm, rmapp, spte); | |
949 | } | |
950 | return young; | |
951 | } | |
952 | ||
53a27b39 MT |
953 | #define RMAP_RECYCLE_THRESHOLD 1000 |
954 | ||
852e3c19 | 955 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
956 | { |
957 | unsigned long *rmapp; | |
852e3c19 JR |
958 | struct kvm_mmu_page *sp; |
959 | ||
960 | sp = page_header(__pa(spte)); | |
53a27b39 | 961 | |
852e3c19 | 962 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 963 | |
3da0dd43 | 964 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
965 | kvm_flush_remote_tlbs(vcpu->kvm); |
966 | } | |
967 | ||
e930bffe AA |
968 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
969 | { | |
3da0dd43 | 970 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
971 | } |
972 | ||
d6c69ee9 | 973 | #ifdef MMU_DEBUG |
47ad8e68 | 974 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 975 | { |
139bdb2d AK |
976 | u64 *pos; |
977 | u64 *end; | |
978 | ||
47ad8e68 | 979 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 980 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 981 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 982 | pos, *pos); |
6aa8b732 | 983 | return 0; |
139bdb2d | 984 | } |
6aa8b732 AK |
985 | return 1; |
986 | } | |
d6c69ee9 | 987 | #endif |
6aa8b732 | 988 | |
45221ab6 DH |
989 | /* |
990 | * This value is the sum of all of the kvm instances's | |
991 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
992 | * aggregate version in order to make the slab shrinker | |
993 | * faster | |
994 | */ | |
995 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
996 | { | |
997 | kvm->arch.n_used_mmu_pages += nr; | |
998 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
999 | } | |
1000 | ||
4db35314 | 1001 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 1002 | { |
4db35314 | 1003 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1004 | hlist_del(&sp->hash_link); |
4db35314 AK |
1005 | list_del(&sp->link); |
1006 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
1007 | if (!sp->role.direct) |
1008 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 1009 | kmem_cache_free(mmu_page_header_cache, sp); |
45221ab6 | 1010 | kvm_mod_used_mmu_pages(kvm, -1); |
260746c0 AK |
1011 | } |
1012 | ||
cea0f0e7 AK |
1013 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1014 | { | |
1ae0a13d | 1015 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1016 | } |
1017 | ||
25c0de2c | 1018 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 1019 | u64 *parent_pte, int direct) |
6aa8b732 | 1020 | { |
4db35314 | 1021 | struct kvm_mmu_page *sp; |
6aa8b732 | 1022 | |
ad312c7c ZX |
1023 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
1024 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
1025 | if (!direct) |
1026 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1027 | PAGE_SIZE); | |
4db35314 | 1028 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 1029 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 1030 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
1031 | sp->multimapped = 0; |
1032 | sp->parent_pte = parent_pte; | |
45221ab6 | 1033 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
4db35314 | 1034 | return sp; |
6aa8b732 AK |
1035 | } |
1036 | ||
714b93da | 1037 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1038 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
1039 | { |
1040 | struct kvm_pte_chain *pte_chain; | |
1041 | struct hlist_node *node; | |
1042 | int i; | |
1043 | ||
1044 | if (!parent_pte) | |
1045 | return; | |
4db35314 AK |
1046 | if (!sp->multimapped) { |
1047 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
1048 | |
1049 | if (!old) { | |
4db35314 | 1050 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
1051 | return; |
1052 | } | |
4db35314 | 1053 | sp->multimapped = 1; |
714b93da | 1054 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1055 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1056 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1057 | pte_chain->parent_ptes[0] = old; |
1058 | } | |
4db35314 | 1059 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1060 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1061 | continue; | |
1062 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1063 | if (!pte_chain->parent_ptes[i]) { | |
1064 | pte_chain->parent_ptes[i] = parent_pte; | |
1065 | return; | |
1066 | } | |
1067 | } | |
714b93da | 1068 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1069 | BUG_ON(!pte_chain); |
4db35314 | 1070 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1071 | pte_chain->parent_ptes[0] = parent_pte; |
1072 | } | |
1073 | ||
4db35314 | 1074 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1075 | u64 *parent_pte) |
1076 | { | |
1077 | struct kvm_pte_chain *pte_chain; | |
1078 | struct hlist_node *node; | |
1079 | int i; | |
1080 | ||
4db35314 AK |
1081 | if (!sp->multimapped) { |
1082 | BUG_ON(sp->parent_pte != parent_pte); | |
1083 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1084 | return; |
1085 | } | |
4db35314 | 1086 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1087 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1088 | if (!pte_chain->parent_ptes[i]) | |
1089 | break; | |
1090 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1091 | continue; | |
697fe2e2 AK |
1092 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1093 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1094 | pte_chain->parent_ptes[i] |
1095 | = pte_chain->parent_ptes[i + 1]; | |
1096 | ++i; | |
1097 | } | |
1098 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1099 | if (i == 0) { |
1100 | hlist_del(&pte_chain->link); | |
90cb0529 | 1101 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1102 | if (hlist_empty(&sp->parent_ptes)) { |
1103 | sp->multimapped = 0; | |
1104 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1105 | } |
1106 | } | |
cea0f0e7 AK |
1107 | return; |
1108 | } | |
1109 | BUG(); | |
1110 | } | |
1111 | ||
6b18493d | 1112 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1113 | { |
1114 | struct kvm_pte_chain *pte_chain; | |
1115 | struct hlist_node *node; | |
1116 | struct kvm_mmu_page *parent_sp; | |
1117 | int i; | |
1118 | ||
1119 | if (!sp->multimapped && sp->parent_pte) { | |
1120 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1121 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1122 | return; |
1123 | } | |
1047df1f | 1124 | |
ad8cfbe3 MT |
1125 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1126 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1127 | u64 *spte = pte_chain->parent_ptes[i]; |
1128 | ||
1129 | if (!spte) | |
ad8cfbe3 | 1130 | break; |
1047df1f XG |
1131 | parent_sp = page_header(__pa(spte)); |
1132 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1133 | } |
1134 | } | |
1135 | ||
1047df1f XG |
1136 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1137 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1138 | { |
1047df1f | 1139 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1140 | } |
1141 | ||
1047df1f | 1142 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1143 | { |
1047df1f | 1144 | unsigned int index; |
0074ff63 | 1145 | |
1047df1f XG |
1146 | index = spte - sp->spt; |
1147 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1148 | return; |
1047df1f | 1149 | if (sp->unsync_children++) |
0074ff63 | 1150 | return; |
1047df1f | 1151 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1152 | } |
1153 | ||
d761a501 AK |
1154 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1155 | struct kvm_mmu_page *sp) | |
1156 | { | |
1157 | int i; | |
1158 | ||
1159 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1160 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1161 | } | |
1162 | ||
e8bc217a | 1163 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
be71e061 | 1164 | struct kvm_mmu_page *sp, bool clear_unsync) |
e8bc217a MT |
1165 | { |
1166 | return 1; | |
1167 | } | |
1168 | ||
a7052897 MT |
1169 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1170 | { | |
1171 | } | |
1172 | ||
60c8aec6 MT |
1173 | #define KVM_PAGE_ARRAY_NR 16 |
1174 | ||
1175 | struct kvm_mmu_pages { | |
1176 | struct mmu_page_and_offset { | |
1177 | struct kvm_mmu_page *sp; | |
1178 | unsigned int idx; | |
1179 | } page[KVM_PAGE_ARRAY_NR]; | |
1180 | unsigned int nr; | |
1181 | }; | |
1182 | ||
0074ff63 MT |
1183 | #define for_each_unsync_children(bitmap, idx) \ |
1184 | for (idx = find_first_bit(bitmap, 512); \ | |
1185 | idx < 512; \ | |
1186 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1187 | ||
cded19f3 HE |
1188 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1189 | int idx) | |
4731d4c7 | 1190 | { |
60c8aec6 | 1191 | int i; |
4731d4c7 | 1192 | |
60c8aec6 MT |
1193 | if (sp->unsync) |
1194 | for (i=0; i < pvec->nr; i++) | |
1195 | if (pvec->page[i].sp == sp) | |
1196 | return 0; | |
1197 | ||
1198 | pvec->page[pvec->nr].sp = sp; | |
1199 | pvec->page[pvec->nr].idx = idx; | |
1200 | pvec->nr++; | |
1201 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1202 | } | |
1203 | ||
1204 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1205 | struct kvm_mmu_pages *pvec) | |
1206 | { | |
1207 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1208 | |
0074ff63 | 1209 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1210 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1211 | u64 ent = sp->spt[i]; |
1212 | ||
7a8f1a74 XG |
1213 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1214 | goto clear_child_bitmap; | |
1215 | ||
1216 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1217 | ||
1218 | if (child->unsync_children) { | |
1219 | if (mmu_pages_add(pvec, child, i)) | |
1220 | return -ENOSPC; | |
1221 | ||
1222 | ret = __mmu_unsync_walk(child, pvec); | |
1223 | if (!ret) | |
1224 | goto clear_child_bitmap; | |
1225 | else if (ret > 0) | |
1226 | nr_unsync_leaf += ret; | |
1227 | else | |
1228 | return ret; | |
1229 | } else if (child->unsync) { | |
1230 | nr_unsync_leaf++; | |
1231 | if (mmu_pages_add(pvec, child, i)) | |
1232 | return -ENOSPC; | |
1233 | } else | |
1234 | goto clear_child_bitmap; | |
1235 | ||
1236 | continue; | |
1237 | ||
1238 | clear_child_bitmap: | |
1239 | __clear_bit(i, sp->unsync_child_bitmap); | |
1240 | sp->unsync_children--; | |
1241 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1242 | } |
1243 | ||
4731d4c7 | 1244 | |
60c8aec6 MT |
1245 | return nr_unsync_leaf; |
1246 | } | |
1247 | ||
1248 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1249 | struct kvm_mmu_pages *pvec) | |
1250 | { | |
1251 | if (!sp->unsync_children) | |
1252 | return 0; | |
1253 | ||
1254 | mmu_pages_add(pvec, sp, 0); | |
1255 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1256 | } |
1257 | ||
4731d4c7 MT |
1258 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1259 | { | |
1260 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1261 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1262 | sp->unsync = 0; |
1263 | --kvm->stat.mmu_unsync; | |
1264 | } | |
1265 | ||
7775834a XG |
1266 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1267 | struct list_head *invalid_list); | |
1268 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1269 | struct list_head *invalid_list); | |
4731d4c7 | 1270 | |
f41d335a XG |
1271 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1272 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1273 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1274 | if ((sp)->gfn != (gfn)) {} else | |
1275 | ||
f41d335a XG |
1276 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1277 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1278 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1279 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1280 | (sp)->role.invalid) {} else | |
1281 | ||
f918b443 | 1282 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1283 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1284 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1285 | { |
5b7e0102 | 1286 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1287 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1288 | return 1; |
1289 | } | |
1290 | ||
f918b443 | 1291 | if (clear_unsync) |
1d9dc7e0 | 1292 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1293 | |
be71e061 | 1294 | if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) { |
d98ba053 | 1295 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1296 | return 1; |
1297 | } | |
1298 | ||
1299 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1300 | return 0; |
1301 | } | |
1302 | ||
1d9dc7e0 XG |
1303 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1304 | struct kvm_mmu_page *sp) | |
1305 | { | |
d98ba053 | 1306 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1307 | int ret; |
1308 | ||
d98ba053 | 1309 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1310 | if (ret) |
d98ba053 XG |
1311 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1312 | ||
1d9dc7e0 XG |
1313 | return ret; |
1314 | } | |
1315 | ||
d98ba053 XG |
1316 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1317 | struct list_head *invalid_list) | |
1d9dc7e0 | 1318 | { |
d98ba053 | 1319 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1320 | } |
1321 | ||
9f1a122f XG |
1322 | /* @gfn should be write-protected at the call site */ |
1323 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1324 | { | |
9f1a122f | 1325 | struct kvm_mmu_page *s; |
f41d335a | 1326 | struct hlist_node *node; |
d98ba053 | 1327 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1328 | bool flush = false; |
1329 | ||
f41d335a | 1330 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1331 | if (!s->unsync) |
9f1a122f XG |
1332 | continue; |
1333 | ||
1334 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
1335 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || | |
be71e061 | 1336 | (vcpu->arch.mmu.sync_page(vcpu, s, true))) { |
d98ba053 | 1337 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1338 | continue; |
1339 | } | |
1340 | kvm_unlink_unsync_page(vcpu->kvm, s); | |
1341 | flush = true; | |
1342 | } | |
1343 | ||
d98ba053 | 1344 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1345 | if (flush) |
1346 | kvm_mmu_flush_tlb(vcpu); | |
1347 | } | |
1348 | ||
60c8aec6 MT |
1349 | struct mmu_page_path { |
1350 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1351 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1352 | }; |
1353 | ||
60c8aec6 MT |
1354 | #define for_each_sp(pvec, sp, parents, i) \ |
1355 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1356 | sp = pvec.page[i].sp; \ | |
1357 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1358 | i = mmu_pages_next(&pvec, &parents, i)) | |
1359 | ||
cded19f3 HE |
1360 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1361 | struct mmu_page_path *parents, | |
1362 | int i) | |
60c8aec6 MT |
1363 | { |
1364 | int n; | |
1365 | ||
1366 | for (n = i+1; n < pvec->nr; n++) { | |
1367 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1368 | ||
1369 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1370 | parents->idx[0] = pvec->page[n].idx; | |
1371 | return n; | |
1372 | } | |
1373 | ||
1374 | parents->parent[sp->role.level-2] = sp; | |
1375 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1376 | } | |
1377 | ||
1378 | return n; | |
1379 | } | |
1380 | ||
cded19f3 | 1381 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1382 | { |
60c8aec6 MT |
1383 | struct kvm_mmu_page *sp; |
1384 | unsigned int level = 0; | |
1385 | ||
1386 | do { | |
1387 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1388 | |
60c8aec6 MT |
1389 | sp = parents->parent[level]; |
1390 | if (!sp) | |
1391 | return; | |
1392 | ||
1393 | --sp->unsync_children; | |
1394 | WARN_ON((int)sp->unsync_children < 0); | |
1395 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1396 | level++; | |
1397 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1398 | } |
1399 | ||
60c8aec6 MT |
1400 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1401 | struct mmu_page_path *parents, | |
1402 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1403 | { |
60c8aec6 MT |
1404 | parents->parent[parent->role.level-1] = NULL; |
1405 | pvec->nr = 0; | |
1406 | } | |
4731d4c7 | 1407 | |
60c8aec6 MT |
1408 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1409 | struct kvm_mmu_page *parent) | |
1410 | { | |
1411 | int i; | |
1412 | struct kvm_mmu_page *sp; | |
1413 | struct mmu_page_path parents; | |
1414 | struct kvm_mmu_pages pages; | |
d98ba053 | 1415 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1416 | |
1417 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1418 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1419 | int protected = 0; |
1420 | ||
1421 | for_each_sp(pages, sp, parents, i) | |
1422 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1423 | ||
1424 | if (protected) | |
1425 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1426 | ||
60c8aec6 | 1427 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1428 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1429 | mmu_pages_clear_parents(&parents); |
1430 | } | |
d98ba053 | 1431 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1432 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1433 | kvm_mmu_pages_init(parent, &parents, &pages); |
1434 | } | |
4731d4c7 MT |
1435 | } |
1436 | ||
cea0f0e7 AK |
1437 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1438 | gfn_t gfn, | |
1439 | gva_t gaddr, | |
1440 | unsigned level, | |
f6e2c02b | 1441 | int direct, |
41074d07 | 1442 | unsigned access, |
f7d9c7b7 | 1443 | u64 *parent_pte) |
cea0f0e7 AK |
1444 | { |
1445 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1446 | unsigned quadrant; |
9f1a122f | 1447 | struct kvm_mmu_page *sp; |
f41d335a | 1448 | struct hlist_node *node; |
9f1a122f | 1449 | bool need_sync = false; |
cea0f0e7 | 1450 | |
a770f6f2 | 1451 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1452 | role.level = level; |
f6e2c02b | 1453 | role.direct = direct; |
84b0c8c6 | 1454 | if (role.direct) |
5b7e0102 | 1455 | role.cr4_pae = 0; |
41074d07 | 1456 | role.access = access; |
c5a78f2b JR |
1457 | if (!vcpu->arch.mmu.direct_map |
1458 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1459 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1460 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1461 | role.quadrant = quadrant; | |
1462 | } | |
f41d335a | 1463 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1464 | if (!need_sync && sp->unsync) |
1465 | need_sync = true; | |
4731d4c7 | 1466 | |
7ae680eb XG |
1467 | if (sp->role.word != role.word) |
1468 | continue; | |
4731d4c7 | 1469 | |
7ae680eb XG |
1470 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1471 | break; | |
e02aa901 | 1472 | |
7ae680eb XG |
1473 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1474 | if (sp->unsync_children) { | |
a8eeb04a | 1475 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1476 | kvm_mmu_mark_parents_unsync(sp); |
1477 | } else if (sp->unsync) | |
1478 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1479 | |
7ae680eb XG |
1480 | trace_kvm_mmu_get_page(sp, false); |
1481 | return sp; | |
1482 | } | |
dfc5aa00 | 1483 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1484 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1485 | if (!sp) |
1486 | return sp; | |
4db35314 AK |
1487 | sp->gfn = gfn; |
1488 | sp->role = role; | |
7ae680eb XG |
1489 | hlist_add_head(&sp->hash_link, |
1490 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1491 | if (!direct) { |
b1a36821 MT |
1492 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1493 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1494 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1495 | kvm_sync_pages(vcpu, gfn); | |
1496 | ||
4731d4c7 MT |
1497 | account_shadowed(vcpu->kvm, gfn); |
1498 | } | |
131d8279 AK |
1499 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1500 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1501 | else | |
1502 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1503 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1504 | return sp; |
cea0f0e7 AK |
1505 | } |
1506 | ||
2d11123a AK |
1507 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1508 | struct kvm_vcpu *vcpu, u64 addr) | |
1509 | { | |
1510 | iterator->addr = addr; | |
1511 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1512 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1513 | |
1514 | if (iterator->level == PT64_ROOT_LEVEL && | |
1515 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1516 | !vcpu->arch.mmu.direct_map) | |
1517 | --iterator->level; | |
1518 | ||
2d11123a AK |
1519 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1520 | iterator->shadow_addr | |
1521 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1522 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1523 | --iterator->level; | |
1524 | if (!iterator->shadow_addr) | |
1525 | iterator->level = 0; | |
1526 | } | |
1527 | } | |
1528 | ||
1529 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1530 | { | |
1531 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1532 | return false; | |
4d88954d MT |
1533 | |
1534 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1535 | if (is_large_pte(*iterator->sptep)) | |
1536 | return false; | |
1537 | ||
2d11123a AK |
1538 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1539 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1540 | return true; | |
1541 | } | |
1542 | ||
1543 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1544 | { | |
1545 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1546 | --iterator->level; | |
1547 | } | |
1548 | ||
32ef26a3 AK |
1549 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1550 | { | |
1551 | u64 spte; | |
1552 | ||
1553 | spte = __pa(sp->spt) | |
1554 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1555 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1556 | __set_spte(sptep, spte); |
32ef26a3 AK |
1557 | } |
1558 | ||
a3aa51cf AK |
1559 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1560 | { | |
1561 | if (is_large_pte(*sptep)) { | |
1562 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1563 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1564 | } | |
1565 | } | |
1566 | ||
a357bd22 AK |
1567 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1568 | unsigned direct_access) | |
1569 | { | |
1570 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1571 | struct kvm_mmu_page *child; | |
1572 | ||
1573 | /* | |
1574 | * For the direct sp, if the guest pte's dirty bit | |
1575 | * changed form clean to dirty, it will corrupt the | |
1576 | * sp's access: allow writable in the read-only sp, | |
1577 | * so we should update the spte at this point to get | |
1578 | * a new sp with the correct access. | |
1579 | */ | |
1580 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1581 | if (child->role.access == direct_access) | |
1582 | return; | |
1583 | ||
1584 | mmu_page_remove_parent_pte(child, sptep); | |
1585 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1586 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1587 | } | |
1588 | } | |
1589 | ||
90cb0529 | 1590 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1591 | struct kvm_mmu_page *sp) |
a436036b | 1592 | { |
697fe2e2 AK |
1593 | unsigned i; |
1594 | u64 *pt; | |
1595 | u64 ent; | |
1596 | ||
4db35314 | 1597 | pt = sp->spt; |
697fe2e2 | 1598 | |
697fe2e2 AK |
1599 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1600 | ent = pt[i]; | |
1601 | ||
05da4558 | 1602 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1603 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1604 | ent &= PT64_BASE_ADDR_MASK; |
1605 | mmu_page_remove_parent_pte(page_header(ent), | |
1606 | &pt[i]); | |
1607 | } else { | |
776e6633 MT |
1608 | if (is_large_pte(ent)) |
1609 | --kvm->stat.lpages; | |
be38d276 AK |
1610 | drop_spte(kvm, &pt[i], |
1611 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1612 | } |
1613 | } | |
c7addb90 | 1614 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1615 | } |
a436036b AK |
1616 | } |
1617 | ||
4db35314 | 1618 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1619 | { |
4db35314 | 1620 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1621 | } |
1622 | ||
12b7d28f AK |
1623 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1624 | { | |
1625 | int i; | |
988a2cae | 1626 | struct kvm_vcpu *vcpu; |
12b7d28f | 1627 | |
988a2cae GN |
1628 | kvm_for_each_vcpu(i, vcpu, kvm) |
1629 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1630 | } |
1631 | ||
31aa2b44 | 1632 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1633 | { |
1634 | u64 *parent_pte; | |
1635 | ||
4db35314 AK |
1636 | while (sp->multimapped || sp->parent_pte) { |
1637 | if (!sp->multimapped) | |
1638 | parent_pte = sp->parent_pte; | |
a436036b AK |
1639 | else { |
1640 | struct kvm_pte_chain *chain; | |
1641 | ||
4db35314 | 1642 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1643 | struct kvm_pte_chain, link); |
1644 | parent_pte = chain->parent_ptes[0]; | |
1645 | } | |
697fe2e2 | 1646 | BUG_ON(!parent_pte); |
4db35314 | 1647 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1648 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1649 | } |
31aa2b44 AK |
1650 | } |
1651 | ||
60c8aec6 | 1652 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1653 | struct kvm_mmu_page *parent, |
1654 | struct list_head *invalid_list) | |
4731d4c7 | 1655 | { |
60c8aec6 MT |
1656 | int i, zapped = 0; |
1657 | struct mmu_page_path parents; | |
1658 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1659 | |
60c8aec6 | 1660 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1661 | return 0; |
60c8aec6 MT |
1662 | |
1663 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1664 | while (mmu_unsync_walk(parent, &pages)) { | |
1665 | struct kvm_mmu_page *sp; | |
1666 | ||
1667 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1668 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1669 | mmu_pages_clear_parents(&parents); |
77662e00 | 1670 | zapped++; |
60c8aec6 | 1671 | } |
60c8aec6 MT |
1672 | kvm_mmu_pages_init(parent, &parents, &pages); |
1673 | } | |
1674 | ||
1675 | return zapped; | |
4731d4c7 MT |
1676 | } |
1677 | ||
7775834a XG |
1678 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1679 | struct list_head *invalid_list) | |
31aa2b44 | 1680 | { |
4731d4c7 | 1681 | int ret; |
f691fe1d | 1682 | |
7775834a | 1683 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1684 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1685 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1686 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1687 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1688 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1689 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1690 | if (sp->unsync) |
1691 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1692 | if (!sp->root_count) { |
54a4f023 GJ |
1693 | /* Count self */ |
1694 | ret++; | |
7775834a | 1695 | list_move(&sp->link, invalid_list); |
2e53d63a | 1696 | } else { |
5b5c6a5a | 1697 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1698 | kvm_reload_remote_mmus(kvm); |
1699 | } | |
7775834a XG |
1700 | |
1701 | sp->role.invalid = 1; | |
12b7d28f | 1702 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1703 | return ret; |
a436036b AK |
1704 | } |
1705 | ||
7775834a XG |
1706 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1707 | struct list_head *invalid_list) | |
1708 | { | |
1709 | struct kvm_mmu_page *sp; | |
1710 | ||
1711 | if (list_empty(invalid_list)) | |
1712 | return; | |
1713 | ||
1714 | kvm_flush_remote_tlbs(kvm); | |
1715 | ||
1716 | do { | |
1717 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1718 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1719 | kvm_mmu_free_page(kvm, sp); | |
1720 | } while (!list_empty(invalid_list)); | |
1721 | ||
1722 | } | |
1723 | ||
82ce2c96 IE |
1724 | /* |
1725 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1726 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1727 | */ |
49d5ca26 | 1728 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1729 | { |
d98ba053 | 1730 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1731 | /* |
1732 | * If we set the number of mmu pages to be smaller be than the | |
1733 | * number of actived pages , we must to free some mmu pages before we | |
1734 | * change the value | |
1735 | */ | |
1736 | ||
49d5ca26 DH |
1737 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1738 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1739 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1740 | struct kvm_mmu_page *page; |
1741 | ||
f05e70ac | 1742 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1743 | struct kvm_mmu_page, link); |
80b63faf XF |
1744 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
1745 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
82ce2c96 | 1746 | } |
49d5ca26 | 1747 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1748 | } |
82ce2c96 | 1749 | |
49d5ca26 | 1750 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1751 | } |
1752 | ||
f67a46f4 | 1753 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1754 | { |
4db35314 | 1755 | struct kvm_mmu_page *sp; |
f41d335a | 1756 | struct hlist_node *node; |
d98ba053 | 1757 | LIST_HEAD(invalid_list); |
a436036b AK |
1758 | int r; |
1759 | ||
9ad17b10 | 1760 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1761 | r = 0; |
f41d335a XG |
1762 | |
1763 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1764 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1765 | sp->role.word); |
1766 | r = 1; | |
f41d335a | 1767 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1768 | } |
d98ba053 | 1769 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1770 | return r; |
cea0f0e7 AK |
1771 | } |
1772 | ||
f67a46f4 | 1773 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1774 | { |
4db35314 | 1775 | struct kvm_mmu_page *sp; |
f41d335a | 1776 | struct hlist_node *node; |
d98ba053 | 1777 | LIST_HEAD(invalid_list); |
97a0a01e | 1778 | |
f41d335a | 1779 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1780 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1781 | __func__, gfn, sp->role.word); |
f41d335a | 1782 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1783 | } |
d98ba053 | 1784 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1785 | } |
1786 | ||
38c335f1 | 1787 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1788 | { |
bc6678a3 | 1789 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1790 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1791 | |
291f26bc | 1792 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1793 | } |
1794 | ||
6844dec6 MT |
1795 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1796 | { | |
1797 | int i; | |
1798 | u64 *pt = sp->spt; | |
1799 | ||
1800 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1801 | return; | |
1802 | ||
1803 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1804 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1805 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1806 | } |
1807 | } | |
1808 | ||
74be52e3 SY |
1809 | /* |
1810 | * The function is based on mtrr_type_lookup() in | |
1811 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1812 | */ | |
1813 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1814 | u64 start, u64 end) | |
1815 | { | |
1816 | int i; | |
1817 | u64 base, mask; | |
1818 | u8 prev_match, curr_match; | |
1819 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1820 | ||
1821 | if (!mtrr_state->enabled) | |
1822 | return 0xFF; | |
1823 | ||
1824 | /* Make end inclusive end, instead of exclusive */ | |
1825 | end--; | |
1826 | ||
1827 | /* Look in fixed ranges. Just return the type as per start */ | |
1828 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1829 | int idx; | |
1830 | ||
1831 | if (start < 0x80000) { | |
1832 | idx = 0; | |
1833 | idx += (start >> 16); | |
1834 | return mtrr_state->fixed_ranges[idx]; | |
1835 | } else if (start < 0xC0000) { | |
1836 | idx = 1 * 8; | |
1837 | idx += ((start - 0x80000) >> 14); | |
1838 | return mtrr_state->fixed_ranges[idx]; | |
1839 | } else if (start < 0x1000000) { | |
1840 | idx = 3 * 8; | |
1841 | idx += ((start - 0xC0000) >> 12); | |
1842 | return mtrr_state->fixed_ranges[idx]; | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | /* | |
1847 | * Look in variable ranges | |
1848 | * Look of multiple ranges matching this address and pick type | |
1849 | * as per MTRR precedence | |
1850 | */ | |
1851 | if (!(mtrr_state->enabled & 2)) | |
1852 | return mtrr_state->def_type; | |
1853 | ||
1854 | prev_match = 0xFF; | |
1855 | for (i = 0; i < num_var_ranges; ++i) { | |
1856 | unsigned short start_state, end_state; | |
1857 | ||
1858 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1859 | continue; | |
1860 | ||
1861 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1862 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1863 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1864 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1865 | ||
1866 | start_state = ((start & mask) == (base & mask)); | |
1867 | end_state = ((end & mask) == (base & mask)); | |
1868 | if (start_state != end_state) | |
1869 | return 0xFE; | |
1870 | ||
1871 | if ((start & mask) != (base & mask)) | |
1872 | continue; | |
1873 | ||
1874 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1875 | if (prev_match == 0xFF) { | |
1876 | prev_match = curr_match; | |
1877 | continue; | |
1878 | } | |
1879 | ||
1880 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1881 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1882 | return MTRR_TYPE_UNCACHABLE; | |
1883 | ||
1884 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1885 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1886 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1887 | curr_match == MTRR_TYPE_WRBACK)) { | |
1888 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1889 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1890 | } | |
1891 | ||
1892 | if (prev_match != curr_match) | |
1893 | return MTRR_TYPE_UNCACHABLE; | |
1894 | } | |
1895 | ||
1896 | if (prev_match != 0xFF) | |
1897 | return prev_match; | |
1898 | ||
1899 | return mtrr_state->def_type; | |
1900 | } | |
1901 | ||
4b12f0de | 1902 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1903 | { |
1904 | u8 mtrr; | |
1905 | ||
1906 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1907 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1908 | if (mtrr == 0xfe || mtrr == 0xff) | |
1909 | mtrr = MTRR_TYPE_WRBACK; | |
1910 | return mtrr; | |
1911 | } | |
4b12f0de | 1912 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1913 | |
9cf5cf5a XG |
1914 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1915 | { | |
1916 | trace_kvm_mmu_unsync_page(sp); | |
1917 | ++vcpu->kvm->stat.mmu_unsync; | |
1918 | sp->unsync = 1; | |
1919 | ||
1920 | kvm_mmu_mark_parents_unsync(sp); | |
1921 | mmu_convert_notrap(sp); | |
1922 | } | |
1923 | ||
1924 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1925 | { |
4731d4c7 | 1926 | struct kvm_mmu_page *s; |
f41d335a | 1927 | struct hlist_node *node; |
9cf5cf5a | 1928 | |
f41d335a | 1929 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1930 | if (s->unsync) |
4731d4c7 | 1931 | continue; |
9cf5cf5a XG |
1932 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1933 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1934 | } |
4731d4c7 MT |
1935 | } |
1936 | ||
1937 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1938 | bool can_unsync) | |
1939 | { | |
9cf5cf5a | 1940 | struct kvm_mmu_page *s; |
f41d335a | 1941 | struct hlist_node *node; |
9cf5cf5a XG |
1942 | bool need_unsync = false; |
1943 | ||
f41d335a | 1944 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1945 | if (!can_unsync) |
1946 | return 1; | |
1947 | ||
9cf5cf5a | 1948 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1949 | return 1; |
9cf5cf5a XG |
1950 | |
1951 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1952 | if (!oos_shadow) |
9cf5cf5a XG |
1953 | return 1; |
1954 | need_unsync = true; | |
1955 | } | |
4731d4c7 | 1956 | } |
9cf5cf5a XG |
1957 | if (need_unsync) |
1958 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1959 | return 0; |
1960 | } | |
1961 | ||
d555c333 | 1962 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1963 | unsigned pte_access, int user_fault, |
852e3c19 | 1964 | int write_fault, int dirty, int level, |
c2d0ee46 | 1965 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1966 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1967 | { |
1968 | u64 spte; | |
1e73f9dd | 1969 | int ret = 0; |
64d4d521 | 1970 | |
1c4f1fd6 AK |
1971 | /* |
1972 | * We don't set the accessed bit, since we sometimes want to see | |
1973 | * whether the guest actually used the pte (in order to detect | |
1974 | * demand paging). | |
1975 | */ | |
4132779b | 1976 | spte = shadow_base_present_pte; |
947da538 | 1977 | if (!speculative) |
3201b5d9 | 1978 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1979 | if (!dirty) |
1980 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1981 | if (pte_access & ACC_EXEC_MASK) |
1982 | spte |= shadow_x_mask; | |
1983 | else | |
1984 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1985 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1986 | spte |= shadow_user_mask; |
852e3c19 | 1987 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1988 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 1989 | if (tdp_enabled) |
4b12f0de SY |
1990 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
1991 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1992 | |
1403283a IE |
1993 | if (reset_host_protection) |
1994 | spte |= SPTE_HOST_WRITEABLE; | |
1995 | ||
35149e21 | 1996 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1997 | |
1998 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
1999 | || (!vcpu->arch.mmu.direct_map && write_fault |
2000 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 2001 | |
852e3c19 JR |
2002 | if (level > PT_PAGE_TABLE_LEVEL && |
2003 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 2004 | ret = 1; |
be38d276 AK |
2005 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
2006 | goto done; | |
38187c83 MT |
2007 | } |
2008 | ||
1c4f1fd6 | 2009 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2010 | |
c5a78f2b JR |
2011 | if (!vcpu->arch.mmu.direct_map |
2012 | && !(pte_access & ACC_WRITE_MASK)) | |
69325a12 AK |
2013 | spte &= ~PT_USER_MASK; |
2014 | ||
ecc5589f MT |
2015 | /* |
2016 | * Optimization: for pte sync, if spte was writable the hash | |
2017 | * lookup is unnecessary (and expensive). Write protection | |
2018 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2019 | * Same reasoning can be applied to dirty page accounting. | |
2020 | */ | |
8dae4445 | 2021 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2022 | goto set_pte; |
2023 | ||
4731d4c7 | 2024 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2025 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2026 | __func__, gfn); |
1e73f9dd | 2027 | ret = 1; |
1c4f1fd6 | 2028 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2029 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2030 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2031 | } |
2032 | } | |
2033 | ||
1c4f1fd6 AK |
2034 | if (pte_access & ACC_WRITE_MASK) |
2035 | mark_page_dirty(vcpu->kvm, gfn); | |
2036 | ||
38187c83 | 2037 | set_pte: |
b79b93f9 | 2038 | update_spte(sptep, spte); |
be38d276 | 2039 | done: |
1e73f9dd MT |
2040 | return ret; |
2041 | } | |
2042 | ||
d555c333 | 2043 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
2044 | unsigned pt_access, unsigned pte_access, |
2045 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 2046 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
2047 | pfn_t pfn, bool speculative, |
2048 | bool reset_host_protection) | |
1e73f9dd MT |
2049 | { |
2050 | int was_rmapped = 0; | |
53a27b39 | 2051 | int rmap_count; |
1e73f9dd MT |
2052 | |
2053 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2054 | " user_fault %d gfn %llx\n", |
d555c333 | 2055 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2056 | write_fault, user_fault, gfn); |
2057 | ||
d555c333 | 2058 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2059 | /* |
2060 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2061 | * the parent of the now unreachable PTE. | |
2062 | */ | |
852e3c19 JR |
2063 | if (level > PT_PAGE_TABLE_LEVEL && |
2064 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2065 | struct kvm_mmu_page *child; |
d555c333 | 2066 | u64 pte = *sptep; |
1e73f9dd MT |
2067 | |
2068 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2069 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2070 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2071 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2072 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2073 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2074 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2075 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2076 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2077 | } else |
2078 | was_rmapped = 1; | |
1e73f9dd | 2079 | } |
852e3c19 | 2080 | |
d555c333 | 2081 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
2082 | dirty, level, gfn, pfn, speculative, true, |
2083 | reset_host_protection)) { | |
1e73f9dd MT |
2084 | if (write_fault) |
2085 | *ptwrite = 1; | |
5304efde | 2086 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2087 | } |
1e73f9dd | 2088 | |
d555c333 | 2089 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2090 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2091 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2092 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2093 | *sptep, sptep); | |
d555c333 | 2094 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2095 | ++vcpu->kvm->stat.lpages; |
2096 | ||
d555c333 | 2097 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2098 | if (!was_rmapped) { |
44ad9944 | 2099 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2100 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2101 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2102 | } |
9ed5520d | 2103 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2104 | if (speculative) { |
d555c333 | 2105 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2106 | vcpu->arch.last_pte_gfn = gfn; |
2107 | } | |
1c4f1fd6 AK |
2108 | } |
2109 | ||
6aa8b732 AK |
2110 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2111 | { | |
2112 | } | |
2113 | ||
957ed9ef XG |
2114 | static struct kvm_memory_slot * |
2115 | pte_prefetch_gfn_to_memslot(struct kvm_vcpu *vcpu, gfn_t gfn, bool no_dirty_log) | |
2116 | { | |
2117 | struct kvm_memory_slot *slot; | |
2118 | ||
2119 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
2120 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
2121 | (no_dirty_log && slot->dirty_bitmap)) | |
2122 | slot = NULL; | |
2123 | ||
2124 | return slot; | |
2125 | } | |
2126 | ||
2127 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2128 | bool no_dirty_log) | |
2129 | { | |
2130 | struct kvm_memory_slot *slot; | |
2131 | unsigned long hva; | |
2132 | ||
2133 | slot = pte_prefetch_gfn_to_memslot(vcpu, gfn, no_dirty_log); | |
2134 | if (!slot) { | |
2135 | get_page(bad_page); | |
2136 | return page_to_pfn(bad_page); | |
2137 | } | |
2138 | ||
2139 | hva = gfn_to_hva_memslot(slot, gfn); | |
2140 | ||
2141 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2142 | } | |
2143 | ||
2144 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2145 | struct kvm_mmu_page *sp, | |
2146 | u64 *start, u64 *end) | |
2147 | { | |
2148 | struct page *pages[PTE_PREFETCH_NUM]; | |
2149 | unsigned access = sp->role.access; | |
2150 | int i, ret; | |
2151 | gfn_t gfn; | |
2152 | ||
2153 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
2154 | if (!pte_prefetch_gfn_to_memslot(vcpu, gfn, access & ACC_WRITE_MASK)) | |
2155 | return -1; | |
2156 | ||
2157 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2158 | if (ret <= 0) | |
2159 | return -1; | |
2160 | ||
2161 | for (i = 0; i < ret; i++, gfn++, start++) | |
2162 | mmu_set_spte(vcpu, start, ACC_ALL, | |
2163 | access, 0, 0, 1, NULL, | |
2164 | sp->role.level, gfn, | |
2165 | page_to_pfn(pages[i]), true, true); | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2171 | struct kvm_mmu_page *sp, u64 *sptep) | |
2172 | { | |
2173 | u64 *spte, *start = NULL; | |
2174 | int i; | |
2175 | ||
2176 | WARN_ON(!sp->role.direct); | |
2177 | ||
2178 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2179 | spte = sp->spt + i; | |
2180 | ||
2181 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2182 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2183 | if (!start) | |
2184 | continue; | |
2185 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2186 | break; | |
2187 | start = NULL; | |
2188 | } else if (!start) | |
2189 | start = spte; | |
2190 | } | |
2191 | } | |
2192 | ||
2193 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2194 | { | |
2195 | struct kvm_mmu_page *sp; | |
2196 | ||
2197 | /* | |
2198 | * Since it's no accessed bit on EPT, it's no way to | |
2199 | * distinguish between actually accessed translations | |
2200 | * and prefetched, so disable pte prefetch if EPT is | |
2201 | * enabled. | |
2202 | */ | |
2203 | if (!shadow_accessed_mask) | |
2204 | return; | |
2205 | ||
2206 | sp = page_header(__pa(sptep)); | |
2207 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2208 | return; | |
2209 | ||
2210 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2211 | } | |
2212 | ||
9f652d21 | 2213 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 2214 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 2215 | { |
9f652d21 | 2216 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2217 | struct kvm_mmu_page *sp; |
9f652d21 | 2218 | int pt_write = 0; |
140754bc | 2219 | gfn_t pseudo_gfn; |
6aa8b732 | 2220 | |
9f652d21 | 2221 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2222 | if (iterator.level == level) { |
9f652d21 AK |
2223 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
2224 | 0, write, 1, &pt_write, | |
1403283a | 2225 | level, gfn, pfn, false, true); |
957ed9ef | 2226 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2227 | ++vcpu->stat.pf_fixed; |
2228 | break; | |
6aa8b732 AK |
2229 | } |
2230 | ||
9f652d21 | 2231 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2232 | u64 base_addr = iterator.addr; |
2233 | ||
2234 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2235 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2236 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2237 | iterator.level - 1, | |
2238 | 1, ACC_ALL, iterator.sptep); | |
2239 | if (!sp) { | |
2240 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2241 | kvm_release_pfn_clean(pfn); | |
2242 | return -ENOMEM; | |
2243 | } | |
140754bc | 2244 | |
d555c333 AK |
2245 | __set_spte(iterator.sptep, |
2246 | __pa(sp->spt) | |
2247 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
33f91edb XG |
2248 | | shadow_user_mask | shadow_x_mask |
2249 | | shadow_accessed_mask); | |
9f652d21 AK |
2250 | } |
2251 | } | |
2252 | return pt_write; | |
6aa8b732 AK |
2253 | } |
2254 | ||
77db5cbd | 2255 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2256 | { |
77db5cbd HY |
2257 | siginfo_t info; |
2258 | ||
2259 | info.si_signo = SIGBUS; | |
2260 | info.si_errno = 0; | |
2261 | info.si_code = BUS_MCEERR_AR; | |
2262 | info.si_addr = (void __user *)address; | |
2263 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2264 | |
77db5cbd | 2265 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2266 | } |
2267 | ||
2268 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2269 | { | |
2270 | kvm_release_pfn_clean(pfn); | |
2271 | if (is_hwpoison_pfn(pfn)) { | |
77db5cbd | 2272 | kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current); |
bf998156 | 2273 | return 0; |
edba23e5 GN |
2274 | } else if (is_fault_pfn(pfn)) |
2275 | return -EFAULT; | |
2276 | ||
bf998156 HY |
2277 | return 1; |
2278 | } | |
2279 | ||
10589a46 MT |
2280 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
2281 | { | |
2282 | int r; | |
852e3c19 | 2283 | int level; |
35149e21 | 2284 | pfn_t pfn; |
e930bffe | 2285 | unsigned long mmu_seq; |
aaee2c94 | 2286 | |
852e3c19 JR |
2287 | level = mapping_level(vcpu, gfn); |
2288 | ||
2289 | /* | |
2290 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2291 | * maximum. Therefore check if the level is larger than that. | |
2292 | */ | |
2293 | if (level > PT_DIRECTORY_LEVEL) | |
2294 | level = PT_DIRECTORY_LEVEL; | |
2295 | ||
2296 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2297 | |
e930bffe | 2298 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2299 | smp_rmb(); |
35149e21 | 2300 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 2301 | |
d196e343 | 2302 | /* mmio */ |
bf998156 HY |
2303 | if (is_error_pfn(pfn)) |
2304 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2305 | |
aaee2c94 | 2306 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2307 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2308 | goto out_unlock; | |
eb787d10 | 2309 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2310 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2311 | spin_unlock(&vcpu->kvm->mmu_lock); |
2312 | ||
aaee2c94 | 2313 | |
10589a46 | 2314 | return r; |
e930bffe AA |
2315 | |
2316 | out_unlock: | |
2317 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2318 | kvm_release_pfn_clean(pfn); | |
2319 | return 0; | |
10589a46 MT |
2320 | } |
2321 | ||
2322 | ||
17ac10ad AK |
2323 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2324 | { | |
2325 | int i; | |
4db35314 | 2326 | struct kvm_mmu_page *sp; |
d98ba053 | 2327 | LIST_HEAD(invalid_list); |
17ac10ad | 2328 | |
ad312c7c | 2329 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2330 | return; |
aaee2c94 | 2331 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2332 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2333 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2334 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2335 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2336 | |
4db35314 AK |
2337 | sp = page_header(root); |
2338 | --sp->root_count; | |
d98ba053 XG |
2339 | if (!sp->root_count && sp->role.invalid) { |
2340 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2341 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2342 | } | |
ad312c7c | 2343 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2344 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2345 | return; |
2346 | } | |
17ac10ad | 2347 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2348 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2349 | |
417726a3 | 2350 | if (root) { |
417726a3 | 2351 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2352 | sp = page_header(root); |
2353 | --sp->root_count; | |
2e53d63a | 2354 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2355 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2356 | &invalid_list); | |
417726a3 | 2357 | } |
ad312c7c | 2358 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2359 | } |
d98ba053 | 2360 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2361 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2362 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2363 | } |
2364 | ||
8986ecc0 MT |
2365 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2366 | { | |
2367 | int ret = 0; | |
2368 | ||
2369 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2370 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2371 | ret = 1; |
2372 | } | |
2373 | ||
2374 | return ret; | |
2375 | } | |
2376 | ||
651dd37a JR |
2377 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2378 | { | |
2379 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2380 | unsigned i; |
651dd37a JR |
2381 | |
2382 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2383 | spin_lock(&vcpu->kvm->mmu_lock); | |
2384 | kvm_mmu_free_some_pages(vcpu); | |
2385 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2386 | 1, ACC_ALL, NULL); | |
2387 | ++sp->root_count; | |
2388 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2389 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2390 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2391 | for (i = 0; i < 4; ++i) { | |
2392 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2393 | ||
2394 | ASSERT(!VALID_PAGE(root)); | |
2395 | spin_lock(&vcpu->kvm->mmu_lock); | |
2396 | kvm_mmu_free_some_pages(vcpu); | |
2397 | sp = kvm_mmu_get_page(vcpu, i << 30, i << 30, | |
2398 | PT32_ROOT_LEVEL, 1, ACC_ALL, | |
2399 | NULL); | |
2400 | root = __pa(sp->spt); | |
2401 | ++sp->root_count; | |
2402 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2403 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2404 | } |
6292757f | 2405 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2406 | } else |
2407 | BUG(); | |
2408 | ||
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2413 | { |
4db35314 | 2414 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2415 | u64 pdptr, pm_mask; |
2416 | gfn_t root_gfn; | |
2417 | int i; | |
3bb65a22 | 2418 | |
5777ed34 | 2419 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2420 | |
651dd37a JR |
2421 | if (mmu_check_root(vcpu, root_gfn)) |
2422 | return 1; | |
2423 | ||
2424 | /* | |
2425 | * Do we shadow a long mode page table? If so we need to | |
2426 | * write-protect the guests page table root. | |
2427 | */ | |
2428 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2429 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2430 | |
2431 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2432 | |
8facbbff | 2433 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2434 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2435 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2436 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2437 | root = __pa(sp->spt); |
2438 | ++sp->root_count; | |
8facbbff | 2439 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2440 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2441 | return 0; |
17ac10ad | 2442 | } |
f87f9288 | 2443 | |
651dd37a JR |
2444 | /* |
2445 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2446 | * or a PAE 3-level page table. In either case we need to be aware that |
2447 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2448 | */ |
81407ca5 JR |
2449 | pm_mask = PT_PRESENT_MASK; |
2450 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2451 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2452 | ||
17ac10ad | 2453 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2454 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2455 | |
2456 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2457 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2458 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2459 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2460 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2461 | continue; |
2462 | } | |
6de4f3ad | 2463 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2464 | if (mmu_check_root(vcpu, root_gfn)) |
2465 | return 1; | |
5a7388c2 | 2466 | } |
8facbbff | 2467 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2468 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2469 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2470 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2471 | ACC_ALL, NULL); |
4db35314 AK |
2472 | root = __pa(sp->spt); |
2473 | ++sp->root_count; | |
8facbbff AK |
2474 | spin_unlock(&vcpu->kvm->mmu_lock); |
2475 | ||
81407ca5 | 2476 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2477 | } |
6292757f | 2478 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2479 | |
2480 | /* | |
2481 | * If we shadow a 32 bit page table with a long mode page | |
2482 | * table we enter this path. | |
2483 | */ | |
2484 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2485 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2486 | /* | |
2487 | * The additional page necessary for this is only | |
2488 | * allocated on demand. | |
2489 | */ | |
2490 | ||
2491 | u64 *lm_root; | |
2492 | ||
2493 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2494 | if (lm_root == NULL) | |
2495 | return 1; | |
2496 | ||
2497 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2498 | ||
2499 | vcpu->arch.mmu.lm_root = lm_root; | |
2500 | } | |
2501 | ||
2502 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2503 | } | |
2504 | ||
8986ecc0 | 2505 | return 0; |
17ac10ad AK |
2506 | } |
2507 | ||
651dd37a JR |
2508 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2509 | { | |
2510 | if (vcpu->arch.mmu.direct_map) | |
2511 | return mmu_alloc_direct_roots(vcpu); | |
2512 | else | |
2513 | return mmu_alloc_shadow_roots(vcpu); | |
2514 | } | |
2515 | ||
0ba73cda MT |
2516 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2517 | { | |
2518 | int i; | |
2519 | struct kvm_mmu_page *sp; | |
2520 | ||
81407ca5 JR |
2521 | if (vcpu->arch.mmu.direct_map) |
2522 | return; | |
2523 | ||
0ba73cda MT |
2524 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2525 | return; | |
6903074c XG |
2526 | |
2527 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
81407ca5 | 2528 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2529 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2530 | sp = page_header(root); | |
2531 | mmu_sync_children(vcpu, sp); | |
2532 | return; | |
2533 | } | |
2534 | for (i = 0; i < 4; ++i) { | |
2535 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2536 | ||
8986ecc0 | 2537 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2538 | root &= PT64_BASE_ADDR_MASK; |
2539 | sp = page_header(root); | |
2540 | mmu_sync_children(vcpu, sp); | |
2541 | } | |
2542 | } | |
6903074c | 2543 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2544 | } |
2545 | ||
2546 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2547 | { | |
2548 | spin_lock(&vcpu->kvm->mmu_lock); | |
2549 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2550 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2551 | } |
2552 | ||
1871c602 GN |
2553 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2554 | u32 access, u32 *error) | |
6aa8b732 | 2555 | { |
1871c602 GN |
2556 | if (error) |
2557 | *error = 0; | |
6aa8b732 AK |
2558 | return vaddr; |
2559 | } | |
2560 | ||
6539e738 JR |
2561 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
2562 | u32 access, u32 *error) | |
2563 | { | |
2564 | if (error) | |
2565 | *error = 0; | |
2566 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); | |
2567 | } | |
2568 | ||
6aa8b732 | 2569 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
3f3e7124 | 2570 | u32 error_code) |
6aa8b732 | 2571 | { |
e833240f | 2572 | gfn_t gfn; |
e2dec939 | 2573 | int r; |
6aa8b732 | 2574 | |
b8688d51 | 2575 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2576 | r = mmu_topup_memory_caches(vcpu); |
2577 | if (r) | |
2578 | return r; | |
714b93da | 2579 | |
6aa8b732 | 2580 | ASSERT(vcpu); |
ad312c7c | 2581 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2582 | |
e833240f | 2583 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2584 | |
e833240f AK |
2585 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2586 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2587 | } |
2588 | ||
fb72d167 JR |
2589 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2590 | u32 error_code) | |
2591 | { | |
35149e21 | 2592 | pfn_t pfn; |
fb72d167 | 2593 | int r; |
852e3c19 | 2594 | int level; |
05da4558 | 2595 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2596 | unsigned long mmu_seq; |
fb72d167 JR |
2597 | |
2598 | ASSERT(vcpu); | |
2599 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2600 | ||
2601 | r = mmu_topup_memory_caches(vcpu); | |
2602 | if (r) | |
2603 | return r; | |
2604 | ||
852e3c19 JR |
2605 | level = mapping_level(vcpu, gfn); |
2606 | ||
2607 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2608 | ||
e930bffe | 2609 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2610 | smp_rmb(); |
35149e21 | 2611 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
bf998156 HY |
2612 | if (is_error_pfn(pfn)) |
2613 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2614 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2615 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2616 | goto out_unlock; | |
fb72d167 JR |
2617 | kvm_mmu_free_some_pages(vcpu); |
2618 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2619 | level, gfn, pfn); |
fb72d167 | 2620 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2621 | |
2622 | return r; | |
e930bffe AA |
2623 | |
2624 | out_unlock: | |
2625 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2626 | kvm_release_pfn_clean(pfn); | |
2627 | return 0; | |
fb72d167 JR |
2628 | } |
2629 | ||
6aa8b732 AK |
2630 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2631 | { | |
17ac10ad | 2632 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2633 | } |
2634 | ||
52fde8df JR |
2635 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2636 | struct kvm_mmu *context) | |
6aa8b732 | 2637 | { |
6aa8b732 AK |
2638 | context->new_cr3 = nonpaging_new_cr3; |
2639 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2640 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2641 | context->free = nonpaging_free; | |
c7addb90 | 2642 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2643 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2644 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2645 | context->root_level = 0; |
6aa8b732 | 2646 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2647 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2648 | context->direct_map = true; |
2d48a985 | 2649 | context->nx = false; |
6aa8b732 AK |
2650 | return 0; |
2651 | } | |
2652 | ||
d835dfec | 2653 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2654 | { |
1165f5fe | 2655 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2656 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2657 | } |
2658 | ||
2659 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2660 | { | |
b8688d51 | 2661 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2662 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2663 | } |
2664 | ||
5777ed34 JR |
2665 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2666 | { | |
2667 | return vcpu->arch.cr3; | |
2668 | } | |
2669 | ||
8df25a32 | 2670 | static void inject_page_fault(struct kvm_vcpu *vcpu) |
6aa8b732 | 2671 | { |
8df25a32 | 2672 | vcpu->arch.mmu.inject_page_fault(vcpu); |
6aa8b732 AK |
2673 | } |
2674 | ||
6aa8b732 AK |
2675 | static void paging_free(struct kvm_vcpu *vcpu) |
2676 | { | |
2677 | nonpaging_free(vcpu); | |
2678 | } | |
2679 | ||
3241f22d | 2680 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2681 | { |
2682 | int bit7; | |
2683 | ||
2684 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2685 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2686 | } |
2687 | ||
6aa8b732 AK |
2688 | #define PTTYPE 64 |
2689 | #include "paging_tmpl.h" | |
2690 | #undef PTTYPE | |
2691 | ||
2692 | #define PTTYPE 32 | |
2693 | #include "paging_tmpl.h" | |
2694 | #undef PTTYPE | |
2695 | ||
52fde8df JR |
2696 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2697 | struct kvm_mmu *context, | |
2698 | int level) | |
82725b20 | 2699 | { |
82725b20 DE |
2700 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2701 | u64 exb_bit_rsvd = 0; | |
2702 | ||
2d48a985 | 2703 | if (!context->nx) |
82725b20 DE |
2704 | exb_bit_rsvd = rsvd_bits(63, 63); |
2705 | switch (level) { | |
2706 | case PT32_ROOT_LEVEL: | |
2707 | /* no rsvd bits for 2 level 4K page table entries */ | |
2708 | context->rsvd_bits_mask[0][1] = 0; | |
2709 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2710 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2711 | ||
2712 | if (!is_pse(vcpu)) { | |
2713 | context->rsvd_bits_mask[1][1] = 0; | |
2714 | break; | |
2715 | } | |
2716 | ||
82725b20 DE |
2717 | if (is_cpuid_PSE36()) |
2718 | /* 36bits PSE 4MB page */ | |
2719 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2720 | else | |
2721 | /* 32 bits PSE 4MB page */ | |
2722 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2723 | break; |
2724 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2725 | context->rsvd_bits_mask[0][2] = |
2726 | rsvd_bits(maxphyaddr, 63) | | |
2727 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2728 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2729 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2730 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2731 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2732 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2733 | rsvd_bits(maxphyaddr, 62) | | |
2734 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2735 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2736 | break; |
2737 | case PT64_ROOT_LEVEL: | |
2738 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2739 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2740 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2741 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2742 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2743 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2744 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2745 | rsvd_bits(maxphyaddr, 51); | |
2746 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2747 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2748 | rsvd_bits(maxphyaddr, 51) | | |
2749 | rsvd_bits(13, 29); | |
82725b20 | 2750 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2751 | rsvd_bits(maxphyaddr, 51) | |
2752 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2753 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2754 | break; |
2755 | } | |
2756 | } | |
2757 | ||
52fde8df JR |
2758 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2759 | struct kvm_mmu *context, | |
2760 | int level) | |
6aa8b732 | 2761 | { |
2d48a985 JR |
2762 | context->nx = is_nx(vcpu); |
2763 | ||
52fde8df | 2764 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2765 | |
2766 | ASSERT(is_pae(vcpu)); | |
2767 | context->new_cr3 = paging_new_cr3; | |
2768 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2769 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2770 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2771 | context->sync_page = paging64_sync_page; |
a7052897 | 2772 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2773 | context->free = paging_free; |
17ac10ad AK |
2774 | context->root_level = level; |
2775 | context->shadow_root_level = level; | |
17c3ba9d | 2776 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2777 | context->direct_map = false; |
6aa8b732 AK |
2778 | return 0; |
2779 | } | |
2780 | ||
52fde8df JR |
2781 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2782 | struct kvm_mmu *context) | |
17ac10ad | 2783 | { |
52fde8df | 2784 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2785 | } |
2786 | ||
52fde8df JR |
2787 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2788 | struct kvm_mmu *context) | |
6aa8b732 | 2789 | { |
2d48a985 JR |
2790 | context->nx = false; |
2791 | ||
52fde8df | 2792 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2793 | |
2794 | context->new_cr3 = paging_new_cr3; | |
2795 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2796 | context->gva_to_gpa = paging32_gva_to_gpa; |
2797 | context->free = paging_free; | |
c7addb90 | 2798 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2799 | context->sync_page = paging32_sync_page; |
a7052897 | 2800 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2801 | context->root_level = PT32_ROOT_LEVEL; |
2802 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2803 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2804 | context->direct_map = false; |
6aa8b732 AK |
2805 | return 0; |
2806 | } | |
2807 | ||
52fde8df JR |
2808 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2809 | struct kvm_mmu *context) | |
6aa8b732 | 2810 | { |
52fde8df | 2811 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2812 | } |
2813 | ||
fb72d167 JR |
2814 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2815 | { | |
14dfe855 | 2816 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 JR |
2817 | |
2818 | context->new_cr3 = nonpaging_new_cr3; | |
2819 | context->page_fault = tdp_page_fault; | |
2820 | context->free = nonpaging_free; | |
2821 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2822 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2823 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2824 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 2825 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2826 | context->direct_map = true; |
1c97f0a0 | 2827 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 2828 | context->get_cr3 = get_cr3; |
cb659db8 | 2829 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 2830 | context->nx = is_nx(vcpu); |
fb72d167 JR |
2831 | |
2832 | if (!is_paging(vcpu)) { | |
2d48a985 | 2833 | context->nx = false; |
fb72d167 JR |
2834 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2835 | context->root_level = 0; | |
2836 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 2837 | context->nx = is_nx(vcpu); |
52fde8df | 2838 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
2839 | context->gva_to_gpa = paging64_gva_to_gpa; |
2840 | context->root_level = PT64_ROOT_LEVEL; | |
2841 | } else if (is_pae(vcpu)) { | |
2d48a985 | 2842 | context->nx = is_nx(vcpu); |
52fde8df | 2843 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2844 | context->gva_to_gpa = paging64_gva_to_gpa; |
2845 | context->root_level = PT32E_ROOT_LEVEL; | |
2846 | } else { | |
2d48a985 | 2847 | context->nx = false; |
52fde8df | 2848 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
2849 | context->gva_to_gpa = paging32_gva_to_gpa; |
2850 | context->root_level = PT32_ROOT_LEVEL; | |
2851 | } | |
2852 | ||
2853 | return 0; | |
2854 | } | |
2855 | ||
52fde8df | 2856 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 2857 | { |
a770f6f2 | 2858 | int r; |
6aa8b732 | 2859 | ASSERT(vcpu); |
ad312c7c | 2860 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2861 | |
2862 | if (!is_paging(vcpu)) | |
52fde8df | 2863 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 2864 | else if (is_long_mode(vcpu)) |
52fde8df | 2865 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 2866 | else if (is_pae(vcpu)) |
52fde8df | 2867 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 2868 | else |
52fde8df | 2869 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 2870 | |
5b7e0102 | 2871 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 2872 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
52fde8df JR |
2873 | |
2874 | return r; | |
2875 | } | |
2876 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
2877 | ||
2878 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
2879 | { | |
14dfe855 | 2880 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 2881 | |
14dfe855 JR |
2882 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
2883 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
2884 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
2885 | |
2886 | return r; | |
6aa8b732 AK |
2887 | } |
2888 | ||
02f59dc9 JR |
2889 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
2890 | { | |
2891 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
2892 | ||
2893 | g_context->get_cr3 = get_cr3; | |
2894 | g_context->inject_page_fault = kvm_inject_page_fault; | |
2895 | ||
2896 | /* | |
2897 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
2898 | * translation of l2_gpa to l1_gpa addresses is done using the | |
2899 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
2900 | * functions between mmu and nested_mmu are swapped. | |
2901 | */ | |
2902 | if (!is_paging(vcpu)) { | |
2d48a985 | 2903 | g_context->nx = false; |
02f59dc9 JR |
2904 | g_context->root_level = 0; |
2905 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
2906 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 2907 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
2908 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
2909 | g_context->root_level = PT64_ROOT_LEVEL; | |
2910 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
2911 | } else if (is_pae(vcpu)) { | |
2d48a985 | 2912 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
2913 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
2914 | g_context->root_level = PT32E_ROOT_LEVEL; | |
2915 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
2916 | } else { | |
2d48a985 | 2917 | g_context->nx = false; |
02f59dc9 JR |
2918 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
2919 | g_context->root_level = PT32_ROOT_LEVEL; | |
2920 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
2921 | } | |
2922 | ||
2923 | return 0; | |
2924 | } | |
2925 | ||
fb72d167 JR |
2926 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2927 | { | |
35149e21 AL |
2928 | vcpu->arch.update_pte.pfn = bad_pfn; |
2929 | ||
02f59dc9 JR |
2930 | if (mmu_is_nested(vcpu)) |
2931 | return init_kvm_nested_mmu(vcpu); | |
2932 | else if (tdp_enabled) | |
fb72d167 JR |
2933 | return init_kvm_tdp_mmu(vcpu); |
2934 | else | |
2935 | return init_kvm_softmmu(vcpu); | |
2936 | } | |
2937 | ||
6aa8b732 AK |
2938 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2939 | { | |
2940 | ASSERT(vcpu); | |
62ad0755 SY |
2941 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2942 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 2943 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
2944 | } |
2945 | ||
2946 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2947 | { |
2948 | destroy_kvm_mmu(vcpu); | |
2949 | return init_kvm_mmu(vcpu); | |
2950 | } | |
8668a3c4 | 2951 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2952 | |
2953 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2954 | { |
714b93da AK |
2955 | int r; |
2956 | ||
e2dec939 | 2957 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2958 | if (r) |
2959 | goto out; | |
8986ecc0 | 2960 | r = mmu_alloc_roots(vcpu); |
8facbbff | 2961 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 2962 | mmu_sync_roots(vcpu); |
aaee2c94 | 2963 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2964 | if (r) |
2965 | goto out; | |
3662cb1c | 2966 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 2967 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2968 | out: |
2969 | return r; | |
6aa8b732 | 2970 | } |
17c3ba9d AK |
2971 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2972 | ||
2973 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2974 | { | |
2975 | mmu_free_roots(vcpu); | |
2976 | } | |
4b16184c | 2977 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 2978 | |
09072daf | 2979 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2980 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2981 | u64 *spte) |
2982 | { | |
2983 | u64 pte; | |
2984 | struct kvm_mmu_page *child; | |
2985 | ||
2986 | pte = *spte; | |
c7addb90 | 2987 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2988 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 2989 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
2990 | else { |
2991 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2992 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2993 | } |
2994 | } | |
d555c333 | 2995 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2996 | if (is_large_pte(pte)) |
2997 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2998 | } |
2999 | ||
0028425f | 3000 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 3001 | struct kvm_mmu_page *sp, |
0028425f | 3002 | u64 *spte, |
489f1d65 | 3003 | const void *new) |
0028425f | 3004 | { |
30945387 | 3005 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3006 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3007 | return; | |
30945387 | 3008 | } |
0028425f | 3009 | |
3241f22d | 3010 | if (is_rsvd_bits_set(&vcpu->arch.mmu, *(u64 *)new, PT_PAGE_TABLE_LEVEL)) |
fa1de2bf XG |
3011 | return; |
3012 | ||
4cee5764 | 3013 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 3014 | if (!sp->role.cr4_pae) |
489f1d65 | 3015 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 3016 | else |
489f1d65 | 3017 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
3018 | } |
3019 | ||
79539cec AK |
3020 | static bool need_remote_flush(u64 old, u64 new) |
3021 | { | |
3022 | if (!is_shadow_present_pte(old)) | |
3023 | return false; | |
3024 | if (!is_shadow_present_pte(new)) | |
3025 | return true; | |
3026 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3027 | return true; | |
3028 | old ^= PT64_NX_MASK; | |
3029 | new ^= PT64_NX_MASK; | |
3030 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3031 | } | |
3032 | ||
0671a8e7 XG |
3033 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3034 | bool remote_flush, bool local_flush) | |
79539cec | 3035 | { |
0671a8e7 XG |
3036 | if (zap_page) |
3037 | return; | |
3038 | ||
3039 | if (remote_flush) | |
79539cec | 3040 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3041 | else if (local_flush) |
79539cec AK |
3042 | kvm_mmu_flush_tlb(vcpu); |
3043 | } | |
3044 | ||
12b7d28f AK |
3045 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3046 | { | |
ad312c7c | 3047 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3048 | |
7b52345e | 3049 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3050 | } |
3051 | ||
d7824fff | 3052 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 3053 | u64 gpte) |
d7824fff AK |
3054 | { |
3055 | gfn_t gfn; | |
35149e21 | 3056 | pfn_t pfn; |
d7824fff | 3057 | |
43a3795a | 3058 | if (!is_present_gpte(gpte)) |
d7824fff AK |
3059 | return; |
3060 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 3061 | |
e930bffe | 3062 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3063 | smp_rmb(); |
35149e21 | 3064 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 3065 | |
35149e21 AL |
3066 | if (is_error_pfn(pfn)) { |
3067 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
3068 | return; |
3069 | } | |
d7824fff | 3070 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 3071 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
3072 | } |
3073 | ||
1b7fcd32 AK |
3074 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3075 | { | |
3076 | u64 *spte = vcpu->arch.last_pte_updated; | |
3077 | ||
3078 | if (spte | |
3079 | && vcpu->arch.last_pte_gfn == gfn | |
3080 | && shadow_accessed_mask | |
3081 | && !(*spte & shadow_accessed_mask) | |
3082 | && is_shadow_present_pte(*spte)) | |
3083 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3084 | } | |
3085 | ||
09072daf | 3086 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3087 | const u8 *new, int bytes, |
3088 | bool guest_initiated) | |
da4a00f0 | 3089 | { |
9b7a0325 | 3090 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3091 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3092 | struct kvm_mmu_page *sp; |
f41d335a | 3093 | struct hlist_node *node; |
d98ba053 | 3094 | LIST_HEAD(invalid_list); |
489f1d65 | 3095 | u64 entry, gentry; |
9b7a0325 | 3096 | u64 *spte; |
9b7a0325 | 3097 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 3098 | unsigned pte_size; |
9b7a0325 | 3099 | unsigned page_offset; |
0e7bc4b9 | 3100 | unsigned misaligned; |
fce0657f | 3101 | unsigned quadrant; |
9b7a0325 | 3102 | int level; |
86a5ba02 | 3103 | int flooded = 0; |
ac1b714e | 3104 | int npte; |
489f1d65 | 3105 | int r; |
08e850c6 | 3106 | int invlpg_counter; |
0671a8e7 XG |
3107 | bool remote_flush, local_flush, zap_page; |
3108 | ||
3109 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 3110 | |
b8688d51 | 3111 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3112 | |
08e850c6 | 3113 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3114 | |
3115 | /* | |
3116 | * Assume that the pte write on a page table of the same type | |
3117 | * as the current vcpu paging mode. This is nearly always true | |
3118 | * (might be false while changing modes). Note it is verified later | |
3119 | * by update_pte(). | |
3120 | */ | |
08e850c6 | 3121 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3122 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3123 | if (is_pae(vcpu)) { |
3124 | gpa &= ~(gpa_t)7; | |
3125 | bytes = 8; | |
3126 | } | |
3127 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3128 | if (r) |
3129 | gentry = 0; | |
08e850c6 AK |
3130 | new = (const u8 *)&gentry; |
3131 | } | |
3132 | ||
3133 | switch (bytes) { | |
3134 | case 4: | |
3135 | gentry = *(const u32 *)new; | |
3136 | break; | |
3137 | case 8: | |
3138 | gentry = *(const u64 *)new; | |
3139 | break; | |
3140 | default: | |
3141 | gentry = 0; | |
3142 | break; | |
72016f3a AK |
3143 | } |
3144 | ||
3145 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 3146 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3147 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3148 | gentry = 0; | |
1b7fcd32 | 3149 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 3150 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3151 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3152 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 MT |
3153 | if (guest_initiated) { |
3154 | if (gfn == vcpu->arch.last_pt_write_gfn | |
3155 | && !last_updated_pte_accessed(vcpu)) { | |
3156 | ++vcpu->arch.last_pt_write_count; | |
3157 | if (vcpu->arch.last_pt_write_count >= 3) | |
3158 | flooded = 1; | |
3159 | } else { | |
3160 | vcpu->arch.last_pt_write_gfn = gfn; | |
3161 | vcpu->arch.last_pt_write_count = 1; | |
3162 | vcpu->arch.last_pte_updated = NULL; | |
3163 | } | |
86a5ba02 | 3164 | } |
3246af0e | 3165 | |
fa1de2bf | 3166 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3167 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3168 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3169 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3170 | misaligned |= bytes < 4; |
86a5ba02 | 3171 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3172 | /* |
3173 | * Misaligned accesses are too much trouble to fix | |
3174 | * up; also, they usually indicate a page is not used | |
3175 | * as a page table. | |
86a5ba02 AK |
3176 | * |
3177 | * If we're seeing too many writes to a page, | |
3178 | * it may no longer be a page table, or we may be | |
3179 | * forking, in which case it is better to unmap the | |
3180 | * page. | |
0e7bc4b9 AK |
3181 | */ |
3182 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3183 | gpa, bytes, sp->role.word); |
0671a8e7 | 3184 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3185 | &invalid_list); |
4cee5764 | 3186 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3187 | continue; |
3188 | } | |
9b7a0325 | 3189 | page_offset = offset; |
4db35314 | 3190 | level = sp->role.level; |
ac1b714e | 3191 | npte = 1; |
5b7e0102 | 3192 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3193 | page_offset <<= 1; /* 32->64 */ |
3194 | /* | |
3195 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3196 | * only 2MB. So we need to double the offset again | |
3197 | * and zap two pdes instead of one. | |
3198 | */ | |
3199 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3200 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3201 | page_offset <<= 1; |
3202 | npte = 2; | |
3203 | } | |
fce0657f | 3204 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3205 | page_offset &= ~PAGE_MASK; |
4db35314 | 3206 | if (quadrant != sp->role.quadrant) |
fce0657f | 3207 | continue; |
9b7a0325 | 3208 | } |
0671a8e7 | 3209 | local_flush = true; |
4db35314 | 3210 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3211 | while (npte--) { |
79539cec | 3212 | entry = *spte; |
4db35314 | 3213 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
3214 | if (gentry && |
3215 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3216 | & mask.word)) | |
72016f3a | 3217 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3218 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3219 | remote_flush = true; | |
ac1b714e | 3220 | ++spte; |
9b7a0325 | 3221 | } |
9b7a0325 | 3222 | } |
0671a8e7 | 3223 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3224 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3225 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3226 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
3227 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
3228 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
3229 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 3230 | } |
da4a00f0 AK |
3231 | } |
3232 | ||
a436036b AK |
3233 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3234 | { | |
10589a46 MT |
3235 | gpa_t gpa; |
3236 | int r; | |
a436036b | 3237 | |
c5a78f2b | 3238 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3239 | return 0; |
3240 | ||
1871c602 | 3241 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3242 | |
aaee2c94 | 3243 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3244 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3245 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3246 | return r; |
a436036b | 3247 | } |
577bdc49 | 3248 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3249 | |
22d95b12 | 3250 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3251 | { |
d98ba053 | 3252 | LIST_HEAD(invalid_list); |
103ad25a | 3253 | |
e0df7b9f | 3254 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3255 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3256 | struct kvm_mmu_page *sp; |
ebeace86 | 3257 | |
f05e70ac | 3258 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3259 | struct kvm_mmu_page, link); |
e0df7b9f | 3260 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
80b63faf | 3261 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4cee5764 | 3262 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
3263 | } |
3264 | } | |
ebeace86 | 3265 | |
3067714c AK |
3266 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
3267 | { | |
3268 | int r; | |
3269 | enum emulation_result er; | |
3270 | ||
ad312c7c | 3271 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
3272 | if (r < 0) |
3273 | goto out; | |
3274 | ||
3275 | if (!r) { | |
3276 | r = 1; | |
3277 | goto out; | |
3278 | } | |
3279 | ||
b733bfb5 AK |
3280 | r = mmu_topup_memory_caches(vcpu); |
3281 | if (r) | |
3282 | goto out; | |
3283 | ||
851ba692 | 3284 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
3285 | |
3286 | switch (er) { | |
3287 | case EMULATE_DONE: | |
3288 | return 1; | |
3289 | case EMULATE_DO_MMIO: | |
3290 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3291 | /* fall through */ |
3067714c | 3292 | case EMULATE_FAIL: |
3f5d18a9 | 3293 | return 0; |
3067714c AK |
3294 | default: |
3295 | BUG(); | |
3296 | } | |
3297 | out: | |
3067714c AK |
3298 | return r; |
3299 | } | |
3300 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3301 | ||
a7052897 MT |
3302 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3303 | { | |
a7052897 | 3304 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3305 | kvm_mmu_flush_tlb(vcpu); |
3306 | ++vcpu->stat.invlpg; | |
3307 | } | |
3308 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3309 | ||
18552672 JR |
3310 | void kvm_enable_tdp(void) |
3311 | { | |
3312 | tdp_enabled = true; | |
3313 | } | |
3314 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3315 | ||
5f4cb662 JR |
3316 | void kvm_disable_tdp(void) |
3317 | { | |
3318 | tdp_enabled = false; | |
3319 | } | |
3320 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3321 | ||
6aa8b732 AK |
3322 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3323 | { | |
ad312c7c | 3324 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3325 | if (vcpu->arch.mmu.lm_root != NULL) |
3326 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3327 | } |
3328 | ||
3329 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3330 | { | |
17ac10ad | 3331 | struct page *page; |
6aa8b732 AK |
3332 | int i; |
3333 | ||
3334 | ASSERT(vcpu); | |
3335 | ||
17ac10ad AK |
3336 | /* |
3337 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3338 | * Therefore we need to allocate shadow page tables in the first | |
3339 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3340 | */ | |
3341 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3342 | if (!page) | |
d7fa6ab2 WY |
3343 | return -ENOMEM; |
3344 | ||
ad312c7c | 3345 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3346 | for (i = 0; i < 4; ++i) |
ad312c7c | 3347 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3348 | |
6aa8b732 | 3349 | return 0; |
6aa8b732 AK |
3350 | } |
3351 | ||
8018c27b | 3352 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3353 | { |
6aa8b732 | 3354 | ASSERT(vcpu); |
ad312c7c | 3355 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3356 | |
8018c27b IM |
3357 | return alloc_mmu_pages(vcpu); |
3358 | } | |
6aa8b732 | 3359 | |
8018c27b IM |
3360 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3361 | { | |
3362 | ASSERT(vcpu); | |
ad312c7c | 3363 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3364 | |
8018c27b | 3365 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3366 | } |
3367 | ||
90cb0529 | 3368 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3369 | { |
4db35314 | 3370 | struct kvm_mmu_page *sp; |
6aa8b732 | 3371 | |
f05e70ac | 3372 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3373 | int i; |
3374 | u64 *pt; | |
3375 | ||
291f26bc | 3376 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3377 | continue; |
3378 | ||
4db35314 | 3379 | pt = sp->spt; |
6aa8b732 AK |
3380 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
3381 | /* avoid RMW */ | |
01c168ac | 3382 | if (is_writable_pte(pt[i])) |
6aa8b732 | 3383 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 3384 | } |
171d595d | 3385 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3386 | } |
37a7d8b0 | 3387 | |
90cb0529 | 3388 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3389 | { |
4db35314 | 3390 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3391 | LIST_HEAD(invalid_list); |
e0fa826f | 3392 | |
aaee2c94 | 3393 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3394 | restart: |
f05e70ac | 3395 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3396 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3397 | goto restart; |
3398 | ||
d98ba053 | 3399 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3400 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3401 | } |
3402 | ||
d98ba053 XG |
3403 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3404 | struct list_head *invalid_list) | |
3ee16c81 IE |
3405 | { |
3406 | struct kvm_mmu_page *page; | |
3407 | ||
3408 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3409 | struct kvm_mmu_page, link); | |
d98ba053 | 3410 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3411 | } |
3412 | ||
7f8275d0 | 3413 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3414 | { |
3415 | struct kvm *kvm; | |
3416 | struct kvm *kvm_freed = NULL; | |
45221ab6 DH |
3417 | |
3418 | if (nr_to_scan == 0) | |
3419 | goto out; | |
3ee16c81 IE |
3420 | |
3421 | spin_lock(&kvm_lock); | |
3422 | ||
3423 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3424 | int idx, freed_pages; |
d98ba053 | 3425 | LIST_HEAD(invalid_list); |
3ee16c81 | 3426 | |
f656ce01 | 3427 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3428 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3429 | if (!kvm_freed && nr_to_scan > 0 && |
3430 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3431 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3432 | &invalid_list); | |
3ee16c81 IE |
3433 | kvm_freed = kvm; |
3434 | } | |
3435 | nr_to_scan--; | |
3436 | ||
d98ba053 | 3437 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3438 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3439 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3440 | } |
3441 | if (kvm_freed) | |
3442 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3443 | ||
3444 | spin_unlock(&kvm_lock); | |
3445 | ||
45221ab6 DH |
3446 | out: |
3447 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3448 | } |
3449 | ||
3450 | static struct shrinker mmu_shrinker = { | |
3451 | .shrink = mmu_shrink, | |
3452 | .seeks = DEFAULT_SEEKS * 10, | |
3453 | }; | |
3454 | ||
2ddfd20e | 3455 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3456 | { |
3457 | if (pte_chain_cache) | |
3458 | kmem_cache_destroy(pte_chain_cache); | |
3459 | if (rmap_desc_cache) | |
3460 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3461 | if (mmu_page_header_cache) |
3462 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3463 | } |
3464 | ||
3ee16c81 IE |
3465 | void kvm_mmu_module_exit(void) |
3466 | { | |
3467 | mmu_destroy_caches(); | |
45bf21a8 | 3468 | percpu_counter_destroy(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
3469 | unregister_shrinker(&mmu_shrinker); |
3470 | } | |
3471 | ||
b5a33a75 AK |
3472 | int kvm_mmu_module_init(void) |
3473 | { | |
3474 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3475 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3476 | 0, 0, NULL); |
b5a33a75 AK |
3477 | if (!pte_chain_cache) |
3478 | goto nomem; | |
3479 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3480 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3481 | 0, 0, NULL); |
b5a33a75 AK |
3482 | if (!rmap_desc_cache) |
3483 | goto nomem; | |
3484 | ||
d3d25b04 AK |
3485 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3486 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3487 | 0, 0, NULL); |
d3d25b04 AK |
3488 | if (!mmu_page_header_cache) |
3489 | goto nomem; | |
3490 | ||
45bf21a8 WY |
3491 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3492 | goto nomem; | |
3493 | ||
3ee16c81 IE |
3494 | register_shrinker(&mmu_shrinker); |
3495 | ||
b5a33a75 AK |
3496 | return 0; |
3497 | ||
3498 | nomem: | |
3ee16c81 | 3499 | mmu_destroy_caches(); |
b5a33a75 AK |
3500 | return -ENOMEM; |
3501 | } | |
3502 | ||
3ad82a7e ZX |
3503 | /* |
3504 | * Caculate mmu pages needed for kvm. | |
3505 | */ | |
3506 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3507 | { | |
3508 | int i; | |
3509 | unsigned int nr_mmu_pages; | |
3510 | unsigned int nr_pages = 0; | |
bc6678a3 | 3511 | struct kvm_memslots *slots; |
3ad82a7e | 3512 | |
90d83dc3 LJ |
3513 | slots = kvm_memslots(kvm); |
3514 | ||
bc6678a3 MT |
3515 | for (i = 0; i < slots->nmemslots; i++) |
3516 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3517 | |
3518 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3519 | nr_mmu_pages = max(nr_mmu_pages, | |
3520 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3521 | ||
3522 | return nr_mmu_pages; | |
3523 | } | |
3524 | ||
2f333bcb MT |
3525 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3526 | unsigned len) | |
3527 | { | |
3528 | if (len > buffer->len) | |
3529 | return NULL; | |
3530 | return buffer->ptr; | |
3531 | } | |
3532 | ||
3533 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3534 | unsigned len) | |
3535 | { | |
3536 | void *ret; | |
3537 | ||
3538 | ret = pv_mmu_peek_buffer(buffer, len); | |
3539 | if (!ret) | |
3540 | return ret; | |
3541 | buffer->ptr += len; | |
3542 | buffer->len -= len; | |
3543 | buffer->processed += len; | |
3544 | return ret; | |
3545 | } | |
3546 | ||
3547 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3548 | gpa_t addr, gpa_t value) | |
3549 | { | |
3550 | int bytes = 8; | |
3551 | int r; | |
3552 | ||
3553 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3554 | bytes = 4; | |
3555 | ||
3556 | r = mmu_topup_memory_caches(vcpu); | |
3557 | if (r) | |
3558 | return r; | |
3559 | ||
3200f405 | 3560 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3561 | return -EFAULT; |
3562 | ||
3563 | return 1; | |
3564 | } | |
3565 | ||
3566 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3567 | { | |
2390218b | 3568 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3569 | return 1; |
3570 | } | |
3571 | ||
3572 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3573 | { | |
3574 | spin_lock(&vcpu->kvm->mmu_lock); | |
3575 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3576 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3577 | return 1; | |
3578 | } | |
3579 | ||
3580 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3581 | struct kvm_pv_mmu_op_buffer *buffer) | |
3582 | { | |
3583 | struct kvm_mmu_op_header *header; | |
3584 | ||
3585 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3586 | if (!header) | |
3587 | return 0; | |
3588 | switch (header->op) { | |
3589 | case KVM_MMU_OP_WRITE_PTE: { | |
3590 | struct kvm_mmu_op_write_pte *wpte; | |
3591 | ||
3592 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3593 | if (!wpte) | |
3594 | return 0; | |
3595 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3596 | wpte->pte_val); | |
3597 | } | |
3598 | case KVM_MMU_OP_FLUSH_TLB: { | |
3599 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3600 | ||
3601 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3602 | if (!ftlb) | |
3603 | return 0; | |
3604 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3605 | } | |
3606 | case KVM_MMU_OP_RELEASE_PT: { | |
3607 | struct kvm_mmu_op_release_pt *rpt; | |
3608 | ||
3609 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3610 | if (!rpt) | |
3611 | return 0; | |
3612 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3613 | } | |
3614 | default: return 0; | |
3615 | } | |
3616 | } | |
3617 | ||
3618 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3619 | gpa_t addr, unsigned long *ret) | |
3620 | { | |
3621 | int r; | |
6ad18fba | 3622 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3623 | |
6ad18fba DH |
3624 | buffer->ptr = buffer->buf; |
3625 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3626 | buffer->processed = 0; | |
2f333bcb | 3627 | |
6ad18fba | 3628 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3629 | if (r) |
3630 | goto out; | |
3631 | ||
6ad18fba DH |
3632 | while (buffer->len) { |
3633 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3634 | if (r < 0) |
3635 | goto out; | |
3636 | if (r == 0) | |
3637 | break; | |
3638 | } | |
3639 | ||
3640 | r = 1; | |
3641 | out: | |
6ad18fba | 3642 | *ret = buffer->processed; |
2f333bcb MT |
3643 | return r; |
3644 | } | |
3645 | ||
94d8b056 MT |
3646 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3647 | { | |
3648 | struct kvm_shadow_walk_iterator iterator; | |
3649 | int nr_sptes = 0; | |
3650 | ||
3651 | spin_lock(&vcpu->kvm->mmu_lock); | |
3652 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3653 | sptes[iterator.level-1] = *iterator.sptep; | |
3654 | nr_sptes++; | |
3655 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3656 | break; | |
3657 | } | |
3658 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3659 | ||
3660 | return nr_sptes; | |
3661 | } | |
3662 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3663 | ||
8b1fe17c | 3664 | #ifdef CONFIG_KVM_MMU_AUDIT |
2f4f3372 | 3665 | #include "mmu_audit.c" |
c42fffe3 XG |
3666 | #else |
3667 | static void mmu_audit_disable(void) { } | |
37a7d8b0 | 3668 | #endif |
c42fffe3 XG |
3669 | |
3670 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
3671 | { | |
3672 | ASSERT(vcpu); | |
3673 | ||
3674 | destroy_kvm_mmu(vcpu); | |
3675 | free_mmu_pages(vcpu); | |
3676 | mmu_free_memory_caches(vcpu); | |
3677 | mmu_audit_disable(); | |
3678 | } |