Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
af585b92 | 25 | #include "x86.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
6aa8b732 | 44 | |
18552672 JR |
45 | /* |
46 | * When setting this variable to true it enables Two-Dimensional-Paging | |
47 | * where the hardware walks 2 page tables: | |
48 | * 1. the guest-virtual to guest-physical | |
49 | * 2. while doing 1. it walks guest-physical to host-physical | |
50 | * If the hardware supports that we don't need to do shadow paging. | |
51 | */ | |
2f333bcb | 52 | bool tdp_enabled = false; |
18552672 | 53 | |
8b1fe17c XG |
54 | enum { |
55 | AUDIT_PRE_PAGE_FAULT, | |
56 | AUDIT_POST_PAGE_FAULT, | |
57 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
58 | AUDIT_POST_PTE_WRITE, |
59 | AUDIT_PRE_SYNC, | |
60 | AUDIT_POST_SYNC | |
8b1fe17c | 61 | }; |
37a7d8b0 | 62 | |
8b1fe17c XG |
63 | char *audit_point_name[] = { |
64 | "pre page fault", | |
65 | "post page fault", | |
66 | "pre pte write", | |
6903074c XG |
67 | "post pte write", |
68 | "pre sync", | |
69 | "post sync" | |
8b1fe17c | 70 | }; |
37a7d8b0 | 71 | |
8b1fe17c | 72 | #undef MMU_DEBUG |
37a7d8b0 AK |
73 | |
74 | #ifdef MMU_DEBUG | |
75 | ||
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
78 | ||
79 | #else | |
80 | ||
81 | #define pgprintk(x...) do { } while (0) | |
82 | #define rmap_printk(x...) do { } while (0) | |
83 | ||
84 | #endif | |
85 | ||
8b1fe17c | 86 | #ifdef MMU_DEBUG |
6ada8cca AK |
87 | static int dbg = 0; |
88 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 89 | #endif |
6aa8b732 | 90 | |
582801a9 MT |
91 | static int oos_shadow = 1; |
92 | module_param(oos_shadow, bool, 0644); | |
93 | ||
d6c69ee9 YD |
94 | #ifndef MMU_DEBUG |
95 | #define ASSERT(x) do { } while (0) | |
96 | #else | |
6aa8b732 AK |
97 | #define ASSERT(x) \ |
98 | if (!(x)) { \ | |
99 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
100 | __FILE__, __LINE__, #x); \ | |
101 | } | |
d6c69ee9 | 102 | #endif |
6aa8b732 | 103 | |
957ed9ef XG |
104 | #define PTE_PREFETCH_NUM 8 |
105 | ||
6aa8b732 AK |
106 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
107 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
108 | ||
6aa8b732 AK |
109 | #define PT64_LEVEL_BITS 9 |
110 | ||
111 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 112 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
113 | |
114 | #define PT64_LEVEL_MASK(level) \ | |
115 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
116 | ||
117 | #define PT64_INDEX(address, level)\ | |
118 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
119 | ||
120 | ||
121 | #define PT32_LEVEL_BITS 10 | |
122 | ||
123 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 124 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
125 | |
126 | #define PT32_LEVEL_MASK(level) \ | |
127 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
128 | #define PT32_LVL_OFFSET_MASK(level) \ |
129 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
130 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
131 | |
132 | #define PT32_INDEX(address, level)\ | |
133 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
134 | ||
135 | ||
27aba766 | 136 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
137 | #define PT64_DIR_BASE_ADDR_MASK \ |
138 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
139 | #define PT64_LVL_ADDR_MASK(level) \ |
140 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
141 | * PT64_LEVEL_BITS))) - 1)) | |
142 | #define PT64_LVL_OFFSET_MASK(level) \ | |
143 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
144 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
145 | |
146 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
147 | #define PT32_DIR_BASE_ADDR_MASK \ | |
148 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
149 | #define PT32_LVL_ADDR_MASK(level) \ |
150 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
151 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 152 | |
79539cec AK |
153 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
154 | | PT64_NX_MASK) | |
6aa8b732 | 155 | |
cd4a4e53 AK |
156 | #define RMAP_EXT 4 |
157 | ||
fe135d2c AK |
158 | #define ACC_EXEC_MASK 1 |
159 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
160 | #define ACC_USER_MASK PT_USER_MASK | |
161 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
162 | ||
90bb6fc5 AK |
163 | #include <trace/events/kvm.h> |
164 | ||
07420171 AK |
165 | #define CREATE_TRACE_POINTS |
166 | #include "mmutrace.h" | |
167 | ||
1403283a IE |
168 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
169 | ||
135f8c2b AK |
170 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
171 | ||
cd4a4e53 | 172 | struct kvm_rmap_desc { |
d555c333 | 173 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
174 | struct kvm_rmap_desc *more; |
175 | }; | |
176 | ||
2d11123a AK |
177 | struct kvm_shadow_walk_iterator { |
178 | u64 addr; | |
179 | hpa_t shadow_addr; | |
180 | int level; | |
181 | u64 *sptep; | |
182 | unsigned index; | |
183 | }; | |
184 | ||
185 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
186 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
187 | shadow_walk_okay(&(_walker)); \ | |
188 | shadow_walk_next(&(_walker))) | |
189 | ||
1047df1f | 190 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 191 | |
b5a33a75 AK |
192 | static struct kmem_cache *pte_chain_cache; |
193 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 194 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 195 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 196 | |
c7addb90 AK |
197 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
198 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
199 | static u64 __read_mostly shadow_nx_mask; |
200 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
201 | static u64 __read_mostly shadow_user_mask; | |
202 | static u64 __read_mostly shadow_accessed_mask; | |
203 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 204 | |
82725b20 DE |
205 | static inline u64 rsvd_bits(int s, int e) |
206 | { | |
207 | return ((1ULL << (e - s + 1)) - 1) << s; | |
208 | } | |
209 | ||
c7addb90 AK |
210 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
211 | { | |
212 | shadow_trap_nonpresent_pte = trap_pte; | |
213 | shadow_notrap_nonpresent_pte = notrap_pte; | |
214 | } | |
215 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
216 | ||
7b52345e | 217 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 218 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
219 | { |
220 | shadow_user_mask = user_mask; | |
221 | shadow_accessed_mask = accessed_mask; | |
222 | shadow_dirty_mask = dirty_mask; | |
223 | shadow_nx_mask = nx_mask; | |
224 | shadow_x_mask = x_mask; | |
225 | } | |
226 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
227 | ||
3dbe1415 | 228 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 229 | { |
4d4ec087 | 230 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
231 | } |
232 | ||
233 | static int is_cpuid_PSE36(void) | |
234 | { | |
235 | return 1; | |
236 | } | |
237 | ||
73b1087e AK |
238 | static int is_nx(struct kvm_vcpu *vcpu) |
239 | { | |
f6801dff | 240 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
241 | } |
242 | ||
c7addb90 AK |
243 | static int is_shadow_present_pte(u64 pte) |
244 | { | |
c7addb90 AK |
245 | return pte != shadow_trap_nonpresent_pte |
246 | && pte != shadow_notrap_nonpresent_pte; | |
247 | } | |
248 | ||
05da4558 MT |
249 | static int is_large_pte(u64 pte) |
250 | { | |
251 | return pte & PT_PAGE_SIZE_MASK; | |
252 | } | |
253 | ||
8dae4445 | 254 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
255 | { |
256 | return pte & PT_WRITABLE_MASK; | |
257 | } | |
258 | ||
43a3795a | 259 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 260 | { |
439e218a | 261 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
262 | } |
263 | ||
43a3795a | 264 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 265 | { |
4b1a80fa | 266 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
267 | } |
268 | ||
776e6633 MT |
269 | static int is_last_spte(u64 pte, int level) |
270 | { | |
271 | if (level == PT_PAGE_TABLE_LEVEL) | |
272 | return 1; | |
852e3c19 | 273 | if (is_large_pte(pte)) |
776e6633 MT |
274 | return 1; |
275 | return 0; | |
276 | } | |
277 | ||
35149e21 | 278 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 279 | { |
35149e21 | 280 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
281 | } |
282 | ||
da928521 AK |
283 | static gfn_t pse36_gfn_delta(u32 gpte) |
284 | { | |
285 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
286 | ||
287 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
288 | } | |
289 | ||
d555c333 | 290 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 291 | { |
7645e432 | 292 | set_64bit(sptep, spte); |
e663ee64 AK |
293 | } |
294 | ||
a9221dd5 AK |
295 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
296 | { | |
297 | #ifdef CONFIG_X86_64 | |
298 | return xchg(sptep, new_spte); | |
299 | #else | |
300 | u64 old_spte; | |
301 | ||
302 | do { | |
303 | old_spte = *sptep; | |
304 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
305 | ||
306 | return old_spte; | |
307 | #endif | |
308 | } | |
309 | ||
8672b721 XG |
310 | static bool spte_has_volatile_bits(u64 spte) |
311 | { | |
312 | if (!shadow_accessed_mask) | |
313 | return false; | |
314 | ||
315 | if (!is_shadow_present_pte(spte)) | |
316 | return false; | |
317 | ||
4132779b XG |
318 | if ((spte & shadow_accessed_mask) && |
319 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
320 | return false; |
321 | ||
322 | return true; | |
323 | } | |
324 | ||
4132779b XG |
325 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
326 | { | |
327 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
328 | } | |
329 | ||
b79b93f9 AK |
330 | static void update_spte(u64 *sptep, u64 new_spte) |
331 | { | |
4132779b XG |
332 | u64 mask, old_spte = *sptep; |
333 | ||
334 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 335 | |
4132779b XG |
336 | new_spte |= old_spte & shadow_dirty_mask; |
337 | ||
338 | mask = shadow_accessed_mask; | |
339 | if (is_writable_pte(old_spte)) | |
340 | mask |= shadow_dirty_mask; | |
341 | ||
342 | if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask) | |
b79b93f9 | 343 | __set_spte(sptep, new_spte); |
4132779b | 344 | else |
b79b93f9 | 345 | old_spte = __xchg_spte(sptep, new_spte); |
4132779b XG |
346 | |
347 | if (!shadow_accessed_mask) | |
348 | return; | |
349 | ||
350 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
351 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
352 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
353 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
b79b93f9 AK |
354 | } |
355 | ||
e2dec939 | 356 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 357 | struct kmem_cache *base_cache, int min) |
714b93da AK |
358 | { |
359 | void *obj; | |
360 | ||
361 | if (cache->nobjs >= min) | |
e2dec939 | 362 | return 0; |
714b93da | 363 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 364 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 365 | if (!obj) |
e2dec939 | 366 | return -ENOMEM; |
714b93da AK |
367 | cache->objects[cache->nobjs++] = obj; |
368 | } | |
e2dec939 | 369 | return 0; |
714b93da AK |
370 | } |
371 | ||
e8ad9a70 XG |
372 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
373 | struct kmem_cache *cache) | |
714b93da AK |
374 | { |
375 | while (mc->nobjs) | |
e8ad9a70 | 376 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
377 | } |
378 | ||
c1158e63 | 379 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 380 | int min) |
c1158e63 AK |
381 | { |
382 | struct page *page; | |
383 | ||
384 | if (cache->nobjs >= min) | |
385 | return 0; | |
386 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 387 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
388 | if (!page) |
389 | return -ENOMEM; | |
c1158e63 AK |
390 | cache->objects[cache->nobjs++] = page_address(page); |
391 | } | |
392 | return 0; | |
393 | } | |
394 | ||
395 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
396 | { | |
397 | while (mc->nobjs) | |
c4d198d5 | 398 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
399 | } |
400 | ||
2e3e5882 | 401 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 402 | { |
e2dec939 AK |
403 | int r; |
404 | ||
ad312c7c | 405 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 406 | pte_chain_cache, 4); |
e2dec939 AK |
407 | if (r) |
408 | goto out; | |
ad312c7c | 409 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
957ed9ef | 410 | rmap_desc_cache, 4 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
411 | if (r) |
412 | goto out; | |
ad312c7c | 413 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
414 | if (r) |
415 | goto out; | |
ad312c7c | 416 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 417 | mmu_page_header_cache, 4); |
e2dec939 AK |
418 | out: |
419 | return r; | |
714b93da AK |
420 | } |
421 | ||
422 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
423 | { | |
e8ad9a70 XG |
424 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
425 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 426 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
427 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
428 | mmu_page_header_cache); | |
714b93da AK |
429 | } |
430 | ||
431 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
432 | size_t size) | |
433 | { | |
434 | void *p; | |
435 | ||
436 | BUG_ON(!mc->nobjs); | |
437 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
438 | return p; |
439 | } | |
440 | ||
714b93da AK |
441 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
442 | { | |
ad312c7c | 443 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
444 | sizeof(struct kvm_pte_chain)); |
445 | } | |
446 | ||
90cb0529 | 447 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 448 | { |
e8ad9a70 | 449 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
450 | } |
451 | ||
452 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
453 | { | |
ad312c7c | 454 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
455 | sizeof(struct kvm_rmap_desc)); |
456 | } | |
457 | ||
90cb0529 | 458 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 459 | { |
e8ad9a70 | 460 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
461 | } |
462 | ||
2032a93d LJ |
463 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
464 | { | |
465 | if (!sp->role.direct) | |
466 | return sp->gfns[index]; | |
467 | ||
468 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
469 | } | |
470 | ||
471 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
472 | { | |
473 | if (sp->role.direct) | |
474 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
475 | else | |
476 | sp->gfns[index] = gfn; | |
477 | } | |
478 | ||
05da4558 MT |
479 | /* |
480 | * Return the pointer to the largepage write count for a given | |
481 | * gfn, handling slots that are not large page aligned. | |
482 | */ | |
d25797b2 JR |
483 | static int *slot_largepage_idx(gfn_t gfn, |
484 | struct kvm_memory_slot *slot, | |
485 | int level) | |
05da4558 MT |
486 | { |
487 | unsigned long idx; | |
488 | ||
82855413 JR |
489 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
490 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 491 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
492 | } |
493 | ||
494 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
495 | { | |
d25797b2 | 496 | struct kvm_memory_slot *slot; |
05da4558 | 497 | int *write_count; |
d25797b2 | 498 | int i; |
05da4558 | 499 | |
a1f4d395 | 500 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
501 | for (i = PT_DIRECTORY_LEVEL; |
502 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
503 | write_count = slot_largepage_idx(gfn, slot, i); | |
504 | *write_count += 1; | |
505 | } | |
05da4558 MT |
506 | } |
507 | ||
508 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
509 | { | |
d25797b2 | 510 | struct kvm_memory_slot *slot; |
05da4558 | 511 | int *write_count; |
d25797b2 | 512 | int i; |
05da4558 | 513 | |
a1f4d395 | 514 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
515 | for (i = PT_DIRECTORY_LEVEL; |
516 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
517 | write_count = slot_largepage_idx(gfn, slot, i); |
518 | *write_count -= 1; | |
519 | WARN_ON(*write_count < 0); | |
520 | } | |
05da4558 MT |
521 | } |
522 | ||
d25797b2 JR |
523 | static int has_wrprotected_page(struct kvm *kvm, |
524 | gfn_t gfn, | |
525 | int level) | |
05da4558 | 526 | { |
2843099f | 527 | struct kvm_memory_slot *slot; |
05da4558 MT |
528 | int *largepage_idx; |
529 | ||
a1f4d395 | 530 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 531 | if (slot) { |
d25797b2 | 532 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
533 | return *largepage_idx; |
534 | } | |
535 | ||
536 | return 1; | |
537 | } | |
538 | ||
d25797b2 | 539 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 540 | { |
8f0b1ab6 | 541 | unsigned long page_size; |
d25797b2 | 542 | int i, ret = 0; |
05da4558 | 543 | |
8f0b1ab6 | 544 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 545 | |
d25797b2 JR |
546 | for (i = PT_PAGE_TABLE_LEVEL; |
547 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
548 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
549 | ret = i; | |
550 | else | |
551 | break; | |
552 | } | |
553 | ||
4c2155ce | 554 | return ret; |
05da4558 MT |
555 | } |
556 | ||
d25797b2 | 557 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
558 | { |
559 | struct kvm_memory_slot *slot; | |
878403b7 | 560 | int host_level, level, max_level; |
05da4558 MT |
561 | |
562 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
563 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 564 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 565 | |
d25797b2 JR |
566 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
567 | ||
568 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
569 | return host_level; | |
570 | ||
878403b7 SY |
571 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
572 | kvm_x86_ops->get_lpage_level() : host_level; | |
573 | ||
574 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
575 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
576 | break; | |
d25797b2 JR |
577 | |
578 | return level - 1; | |
05da4558 MT |
579 | } |
580 | ||
290fc38d IE |
581 | /* |
582 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
583 | */ |
584 | ||
44ad9944 | 585 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
586 | { |
587 | struct kvm_memory_slot *slot; | |
05da4558 | 588 | unsigned long idx; |
290fc38d IE |
589 | |
590 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 591 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
592 | return &slot->rmap[gfn - slot->base_gfn]; |
593 | ||
82855413 JR |
594 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
595 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 596 | |
44ad9944 | 597 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
598 | } |
599 | ||
cd4a4e53 AK |
600 | /* |
601 | * Reverse mapping data structures: | |
602 | * | |
290fc38d IE |
603 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
604 | * that points to page_address(page). | |
cd4a4e53 | 605 | * |
290fc38d IE |
606 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
607 | * containing more mappings. | |
53a27b39 MT |
608 | * |
609 | * Returns the number of rmap entries before the spte was added or zero if | |
610 | * the spte was not added. | |
611 | * | |
cd4a4e53 | 612 | */ |
44ad9944 | 613 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 614 | { |
4db35314 | 615 | struct kvm_mmu_page *sp; |
cd4a4e53 | 616 | struct kvm_rmap_desc *desc; |
290fc38d | 617 | unsigned long *rmapp; |
53a27b39 | 618 | int i, count = 0; |
cd4a4e53 | 619 | |
43a3795a | 620 | if (!is_rmap_spte(*spte)) |
53a27b39 | 621 | return count; |
4db35314 | 622 | sp = page_header(__pa(spte)); |
2032a93d | 623 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 624 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 625 | if (!*rmapp) { |
cd4a4e53 | 626 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
627 | *rmapp = (unsigned long)spte; |
628 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 629 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 630 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
631 | desc->sptes[0] = (u64 *)*rmapp; |
632 | desc->sptes[1] = spte; | |
290fc38d | 633 | *rmapp = (unsigned long)desc | 1; |
cb16a7b3 | 634 | ++count; |
cd4a4e53 AK |
635 | } else { |
636 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 637 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 638 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 639 | desc = desc->more; |
53a27b39 MT |
640 | count += RMAP_EXT; |
641 | } | |
d555c333 | 642 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 643 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
644 | desc = desc->more; |
645 | } | |
d555c333 | 646 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 647 | ++count; |
d555c333 | 648 | desc->sptes[i] = spte; |
cd4a4e53 | 649 | } |
53a27b39 | 650 | return count; |
cd4a4e53 AK |
651 | } |
652 | ||
290fc38d | 653 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
654 | struct kvm_rmap_desc *desc, |
655 | int i, | |
656 | struct kvm_rmap_desc *prev_desc) | |
657 | { | |
658 | int j; | |
659 | ||
d555c333 | 660 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 661 | ; |
d555c333 AK |
662 | desc->sptes[i] = desc->sptes[j]; |
663 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
664 | if (j != 0) |
665 | return; | |
666 | if (!prev_desc && !desc->more) | |
d555c333 | 667 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
668 | else |
669 | if (prev_desc) | |
670 | prev_desc->more = desc->more; | |
671 | else | |
290fc38d | 672 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 673 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
674 | } |
675 | ||
290fc38d | 676 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 677 | { |
cd4a4e53 AK |
678 | struct kvm_rmap_desc *desc; |
679 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 680 | struct kvm_mmu_page *sp; |
2032a93d | 681 | gfn_t gfn; |
290fc38d | 682 | unsigned long *rmapp; |
cd4a4e53 AK |
683 | int i; |
684 | ||
4db35314 | 685 | sp = page_header(__pa(spte)); |
2032a93d LJ |
686 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
687 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 688 | if (!*rmapp) { |
19ada5c4 | 689 | printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 690 | BUG(); |
290fc38d | 691 | } else if (!(*rmapp & 1)) { |
19ada5c4 | 692 | rmap_printk("rmap_remove: %p 1->0\n", spte); |
290fc38d | 693 | if ((u64 *)*rmapp != spte) { |
19ada5c4 | 694 | printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
695 | BUG(); |
696 | } | |
290fc38d | 697 | *rmapp = 0; |
cd4a4e53 | 698 | } else { |
19ada5c4 | 699 | rmap_printk("rmap_remove: %p many->many\n", spte); |
290fc38d | 700 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
701 | prev_desc = NULL; |
702 | while (desc) { | |
d555c333 AK |
703 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
704 | if (desc->sptes[i] == spte) { | |
290fc38d | 705 | rmap_desc_remove_entry(rmapp, |
714b93da | 706 | desc, i, |
cd4a4e53 AK |
707 | prev_desc); |
708 | return; | |
709 | } | |
710 | prev_desc = desc; | |
711 | desc = desc->more; | |
712 | } | |
19ada5c4 | 713 | pr_err("rmap_remove: %p many->many\n", spte); |
cd4a4e53 AK |
714 | BUG(); |
715 | } | |
716 | } | |
717 | ||
eb45fda4 | 718 | static int set_spte_track_bits(u64 *sptep, u64 new_spte) |
be38d276 | 719 | { |
ce061867 | 720 | pfn_t pfn; |
9a3aad70 XG |
721 | u64 old_spte = *sptep; |
722 | ||
8672b721 | 723 | if (!spte_has_volatile_bits(old_spte)) |
9a3aad70 | 724 | __set_spte(sptep, new_spte); |
8672b721 | 725 | else |
9a3aad70 | 726 | old_spte = __xchg_spte(sptep, new_spte); |
ce061867 | 727 | |
a9221dd5 | 728 | if (!is_rmap_spte(old_spte)) |
eb45fda4 | 729 | return 0; |
8672b721 | 730 | |
a9221dd5 | 731 | pfn = spte_to_pfn(old_spte); |
daa3db69 | 732 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
ce061867 | 733 | kvm_set_pfn_accessed(pfn); |
4132779b | 734 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) |
ce061867 | 735 | kvm_set_pfn_dirty(pfn); |
eb45fda4 | 736 | return 1; |
e4b502ea XG |
737 | } |
738 | ||
739 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) | |
740 | { | |
eb45fda4 MT |
741 | if (set_spte_track_bits(sptep, new_spte)) |
742 | rmap_remove(kvm, sptep); | |
be38d276 AK |
743 | } |
744 | ||
98348e95 | 745 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 746 | { |
374cbac0 | 747 | struct kvm_rmap_desc *desc; |
98348e95 IE |
748 | u64 *prev_spte; |
749 | int i; | |
750 | ||
751 | if (!*rmapp) | |
752 | return NULL; | |
753 | else if (!(*rmapp & 1)) { | |
754 | if (!spte) | |
755 | return (u64 *)*rmapp; | |
756 | return NULL; | |
757 | } | |
758 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
759 | prev_spte = NULL; |
760 | while (desc) { | |
d555c333 | 761 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 762 | if (prev_spte == spte) |
d555c333 AK |
763 | return desc->sptes[i]; |
764 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
765 | } |
766 | desc = desc->more; | |
767 | } | |
768 | return NULL; | |
769 | } | |
770 | ||
b1a36821 | 771 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 772 | { |
290fc38d | 773 | unsigned long *rmapp; |
374cbac0 | 774 | u64 *spte; |
44ad9944 | 775 | int i, write_protected = 0; |
374cbac0 | 776 | |
44ad9944 | 777 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 778 | |
98348e95 IE |
779 | spte = rmap_next(kvm, rmapp, NULL); |
780 | while (spte) { | |
374cbac0 | 781 | BUG_ON(!spte); |
374cbac0 | 782 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 783 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 784 | if (is_writable_pte(*spte)) { |
b79b93f9 | 785 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
786 | write_protected = 1; |
787 | } | |
9647c14c | 788 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 789 | } |
855149aa | 790 | |
05da4558 | 791 | /* check for huge page mappings */ |
44ad9944 JR |
792 | for (i = PT_DIRECTORY_LEVEL; |
793 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
794 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
795 | spte = rmap_next(kvm, rmapp, NULL); | |
796 | while (spte) { | |
797 | BUG_ON(!spte); | |
798 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
799 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
800 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 801 | if (is_writable_pte(*spte)) { |
be38d276 AK |
802 | drop_spte(kvm, spte, |
803 | shadow_trap_nonpresent_pte); | |
44ad9944 | 804 | --kvm->stat.lpages; |
44ad9944 JR |
805 | spte = NULL; |
806 | write_protected = 1; | |
807 | } | |
808 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 809 | } |
05da4558 MT |
810 | } |
811 | ||
b1a36821 | 812 | return write_protected; |
374cbac0 AK |
813 | } |
814 | ||
8a8365c5 FD |
815 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
816 | unsigned long data) | |
e930bffe AA |
817 | { |
818 | u64 *spte; | |
819 | int need_tlb_flush = 0; | |
820 | ||
821 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
822 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
823 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 824 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
825 | need_tlb_flush = 1; |
826 | } | |
827 | return need_tlb_flush; | |
828 | } | |
829 | ||
8a8365c5 FD |
830 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
831 | unsigned long data) | |
3da0dd43 IE |
832 | { |
833 | int need_flush = 0; | |
e4b502ea | 834 | u64 *spte, new_spte; |
3da0dd43 IE |
835 | pte_t *ptep = (pte_t *)data; |
836 | pfn_t new_pfn; | |
837 | ||
838 | WARN_ON(pte_huge(*ptep)); | |
839 | new_pfn = pte_pfn(*ptep); | |
840 | spte = rmap_next(kvm, rmapp, NULL); | |
841 | while (spte) { | |
842 | BUG_ON(!is_shadow_present_pte(*spte)); | |
843 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
844 | need_flush = 1; | |
845 | if (pte_write(*ptep)) { | |
be38d276 | 846 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
847 | spte = rmap_next(kvm, rmapp, NULL); |
848 | } else { | |
849 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
850 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
851 | ||
852 | new_spte &= ~PT_WRITABLE_MASK; | |
853 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 854 | new_spte &= ~shadow_accessed_mask; |
e4b502ea | 855 | set_spte_track_bits(spte, new_spte); |
3da0dd43 IE |
856 | spte = rmap_next(kvm, rmapp, spte); |
857 | } | |
858 | } | |
859 | if (need_flush) | |
860 | kvm_flush_remote_tlbs(kvm); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
8a8365c5 FD |
865 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
866 | unsigned long data, | |
3da0dd43 | 867 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 868 | unsigned long data)) |
e930bffe | 869 | { |
852e3c19 | 870 | int i, j; |
90bb6fc5 | 871 | int ret; |
e930bffe | 872 | int retval = 0; |
bc6678a3 MT |
873 | struct kvm_memslots *slots; |
874 | ||
90d83dc3 | 875 | slots = kvm_memslots(kvm); |
e930bffe | 876 | |
46a26bf5 MT |
877 | for (i = 0; i < slots->nmemslots; i++) { |
878 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
879 | unsigned long start = memslot->userspace_addr; |
880 | unsigned long end; | |
881 | ||
e930bffe AA |
882 | end = start + (memslot->npages << PAGE_SHIFT); |
883 | if (hva >= start && hva < end) { | |
884 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 885 | |
90bb6fc5 | 886 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
887 | |
888 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
6e3e243c AA |
889 | unsigned long idx; |
890 | int sh; | |
891 | ||
892 | sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j); | |
893 | idx = ((memslot->base_gfn+gfn_offset) >> sh) - | |
894 | (memslot->base_gfn >> sh); | |
90bb6fc5 | 895 | ret |= handler(kvm, |
3da0dd43 IE |
896 | &memslot->lpage_info[j][idx].rmap_pde, |
897 | data); | |
852e3c19 | 898 | } |
90bb6fc5 AK |
899 | trace_kvm_age_page(hva, memslot, ret); |
900 | retval |= ret; | |
e930bffe AA |
901 | } |
902 | } | |
903 | ||
904 | return retval; | |
905 | } | |
906 | ||
907 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
908 | { | |
3da0dd43 IE |
909 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
910 | } | |
911 | ||
912 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
913 | { | |
8a8365c5 | 914 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
915 | } |
916 | ||
8a8365c5 FD |
917 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
918 | unsigned long data) | |
e930bffe AA |
919 | { |
920 | u64 *spte; | |
921 | int young = 0; | |
922 | ||
6316e1c8 RR |
923 | /* |
924 | * Emulate the accessed bit for EPT, by checking if this page has | |
925 | * an EPT mapping, and clearing it if it does. On the next access, | |
926 | * a new EPT mapping will be established. | |
927 | * This has some overhead, but not as much as the cost of swapping | |
928 | * out actively used pages or breaking up actively used hugepages. | |
929 | */ | |
534e38b4 | 930 | if (!shadow_accessed_mask) |
6316e1c8 | 931 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 932 | |
e930bffe AA |
933 | spte = rmap_next(kvm, rmapp, NULL); |
934 | while (spte) { | |
935 | int _young; | |
936 | u64 _spte = *spte; | |
937 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
938 | _young = _spte & PT_ACCESSED_MASK; | |
939 | if (_young) { | |
940 | young = 1; | |
941 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
942 | } | |
943 | spte = rmap_next(kvm, rmapp, spte); | |
944 | } | |
945 | return young; | |
946 | } | |
947 | ||
53a27b39 MT |
948 | #define RMAP_RECYCLE_THRESHOLD 1000 |
949 | ||
852e3c19 | 950 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
951 | { |
952 | unsigned long *rmapp; | |
852e3c19 JR |
953 | struct kvm_mmu_page *sp; |
954 | ||
955 | sp = page_header(__pa(spte)); | |
53a27b39 | 956 | |
852e3c19 | 957 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 958 | |
3da0dd43 | 959 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
960 | kvm_flush_remote_tlbs(vcpu->kvm); |
961 | } | |
962 | ||
e930bffe AA |
963 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
964 | { | |
3da0dd43 | 965 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
966 | } |
967 | ||
d6c69ee9 | 968 | #ifdef MMU_DEBUG |
47ad8e68 | 969 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 970 | { |
139bdb2d AK |
971 | u64 *pos; |
972 | u64 *end; | |
973 | ||
47ad8e68 | 974 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 975 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 976 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 977 | pos, *pos); |
6aa8b732 | 978 | return 0; |
139bdb2d | 979 | } |
6aa8b732 AK |
980 | return 1; |
981 | } | |
d6c69ee9 | 982 | #endif |
6aa8b732 | 983 | |
45221ab6 DH |
984 | /* |
985 | * This value is the sum of all of the kvm instances's | |
986 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
987 | * aggregate version in order to make the slab shrinker | |
988 | * faster | |
989 | */ | |
990 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
991 | { | |
992 | kvm->arch.n_used_mmu_pages += nr; | |
993 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
994 | } | |
995 | ||
4db35314 | 996 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 997 | { |
4db35314 | 998 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 999 | hlist_del(&sp->hash_link); |
4db35314 AK |
1000 | list_del(&sp->link); |
1001 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
1002 | if (!sp->role.direct) |
1003 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 1004 | kmem_cache_free(mmu_page_header_cache, sp); |
45221ab6 | 1005 | kvm_mod_used_mmu_pages(kvm, -1); |
260746c0 AK |
1006 | } |
1007 | ||
cea0f0e7 AK |
1008 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1009 | { | |
1ae0a13d | 1010 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1011 | } |
1012 | ||
25c0de2c | 1013 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 1014 | u64 *parent_pte, int direct) |
6aa8b732 | 1015 | { |
4db35314 | 1016 | struct kvm_mmu_page *sp; |
6aa8b732 | 1017 | |
ad312c7c ZX |
1018 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
1019 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
1020 | if (!direct) |
1021 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
1022 | PAGE_SIZE); | |
4db35314 | 1023 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 1024 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 1025 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
1026 | sp->multimapped = 0; |
1027 | sp->parent_pte = parent_pte; | |
45221ab6 | 1028 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
4db35314 | 1029 | return sp; |
6aa8b732 AK |
1030 | } |
1031 | ||
714b93da | 1032 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1033 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
1034 | { |
1035 | struct kvm_pte_chain *pte_chain; | |
1036 | struct hlist_node *node; | |
1037 | int i; | |
1038 | ||
1039 | if (!parent_pte) | |
1040 | return; | |
4db35314 AK |
1041 | if (!sp->multimapped) { |
1042 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
1043 | |
1044 | if (!old) { | |
4db35314 | 1045 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
1046 | return; |
1047 | } | |
4db35314 | 1048 | sp->multimapped = 1; |
714b93da | 1049 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
1050 | INIT_HLIST_HEAD(&sp->parent_ptes); |
1051 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1052 | pte_chain->parent_ptes[0] = old; |
1053 | } | |
4db35314 | 1054 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1055 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1056 | continue; | |
1057 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1058 | if (!pte_chain->parent_ptes[i]) { | |
1059 | pte_chain->parent_ptes[i] = parent_pte; | |
1060 | return; | |
1061 | } | |
1062 | } | |
714b93da | 1063 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1064 | BUG_ON(!pte_chain); |
4db35314 | 1065 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1066 | pte_chain->parent_ptes[0] = parent_pte; |
1067 | } | |
1068 | ||
4db35314 | 1069 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1070 | u64 *parent_pte) |
1071 | { | |
1072 | struct kvm_pte_chain *pte_chain; | |
1073 | struct hlist_node *node; | |
1074 | int i; | |
1075 | ||
4db35314 AK |
1076 | if (!sp->multimapped) { |
1077 | BUG_ON(sp->parent_pte != parent_pte); | |
1078 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1079 | return; |
1080 | } | |
4db35314 | 1081 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1082 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1083 | if (!pte_chain->parent_ptes[i]) | |
1084 | break; | |
1085 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1086 | continue; | |
697fe2e2 AK |
1087 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1088 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1089 | pte_chain->parent_ptes[i] |
1090 | = pte_chain->parent_ptes[i + 1]; | |
1091 | ++i; | |
1092 | } | |
1093 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1094 | if (i == 0) { |
1095 | hlist_del(&pte_chain->link); | |
90cb0529 | 1096 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1097 | if (hlist_empty(&sp->parent_ptes)) { |
1098 | sp->multimapped = 0; | |
1099 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1100 | } |
1101 | } | |
cea0f0e7 AK |
1102 | return; |
1103 | } | |
1104 | BUG(); | |
1105 | } | |
1106 | ||
6b18493d | 1107 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1108 | { |
1109 | struct kvm_pte_chain *pte_chain; | |
1110 | struct hlist_node *node; | |
1111 | struct kvm_mmu_page *parent_sp; | |
1112 | int i; | |
1113 | ||
1114 | if (!sp->multimapped && sp->parent_pte) { | |
1115 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1116 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1117 | return; |
1118 | } | |
1047df1f | 1119 | |
ad8cfbe3 MT |
1120 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1121 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1122 | u64 *spte = pte_chain->parent_ptes[i]; |
1123 | ||
1124 | if (!spte) | |
ad8cfbe3 | 1125 | break; |
1047df1f XG |
1126 | parent_sp = page_header(__pa(spte)); |
1127 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1128 | } |
1129 | } | |
1130 | ||
1047df1f XG |
1131 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1132 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1133 | { |
1047df1f | 1134 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1135 | } |
1136 | ||
1047df1f | 1137 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1138 | { |
1047df1f | 1139 | unsigned int index; |
0074ff63 | 1140 | |
1047df1f XG |
1141 | index = spte - sp->spt; |
1142 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1143 | return; |
1047df1f | 1144 | if (sp->unsync_children++) |
0074ff63 | 1145 | return; |
1047df1f | 1146 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1147 | } |
1148 | ||
d761a501 AK |
1149 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1150 | struct kvm_mmu_page *sp) | |
1151 | { | |
1152 | int i; | |
1153 | ||
1154 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1155 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1156 | } | |
1157 | ||
e8bc217a | 1158 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1159 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1160 | { |
1161 | return 1; | |
1162 | } | |
1163 | ||
a7052897 MT |
1164 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1165 | { | |
1166 | } | |
1167 | ||
60c8aec6 MT |
1168 | #define KVM_PAGE_ARRAY_NR 16 |
1169 | ||
1170 | struct kvm_mmu_pages { | |
1171 | struct mmu_page_and_offset { | |
1172 | struct kvm_mmu_page *sp; | |
1173 | unsigned int idx; | |
1174 | } page[KVM_PAGE_ARRAY_NR]; | |
1175 | unsigned int nr; | |
1176 | }; | |
1177 | ||
0074ff63 MT |
1178 | #define for_each_unsync_children(bitmap, idx) \ |
1179 | for (idx = find_first_bit(bitmap, 512); \ | |
1180 | idx < 512; \ | |
1181 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1182 | ||
cded19f3 HE |
1183 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1184 | int idx) | |
4731d4c7 | 1185 | { |
60c8aec6 | 1186 | int i; |
4731d4c7 | 1187 | |
60c8aec6 MT |
1188 | if (sp->unsync) |
1189 | for (i=0; i < pvec->nr; i++) | |
1190 | if (pvec->page[i].sp == sp) | |
1191 | return 0; | |
1192 | ||
1193 | pvec->page[pvec->nr].sp = sp; | |
1194 | pvec->page[pvec->nr].idx = idx; | |
1195 | pvec->nr++; | |
1196 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1197 | } | |
1198 | ||
1199 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1200 | struct kvm_mmu_pages *pvec) | |
1201 | { | |
1202 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1203 | |
0074ff63 | 1204 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1205 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1206 | u64 ent = sp->spt[i]; |
1207 | ||
7a8f1a74 XG |
1208 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1209 | goto clear_child_bitmap; | |
1210 | ||
1211 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1212 | ||
1213 | if (child->unsync_children) { | |
1214 | if (mmu_pages_add(pvec, child, i)) | |
1215 | return -ENOSPC; | |
1216 | ||
1217 | ret = __mmu_unsync_walk(child, pvec); | |
1218 | if (!ret) | |
1219 | goto clear_child_bitmap; | |
1220 | else if (ret > 0) | |
1221 | nr_unsync_leaf += ret; | |
1222 | else | |
1223 | return ret; | |
1224 | } else if (child->unsync) { | |
1225 | nr_unsync_leaf++; | |
1226 | if (mmu_pages_add(pvec, child, i)) | |
1227 | return -ENOSPC; | |
1228 | } else | |
1229 | goto clear_child_bitmap; | |
1230 | ||
1231 | continue; | |
1232 | ||
1233 | clear_child_bitmap: | |
1234 | __clear_bit(i, sp->unsync_child_bitmap); | |
1235 | sp->unsync_children--; | |
1236 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1237 | } |
1238 | ||
4731d4c7 | 1239 | |
60c8aec6 MT |
1240 | return nr_unsync_leaf; |
1241 | } | |
1242 | ||
1243 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1244 | struct kvm_mmu_pages *pvec) | |
1245 | { | |
1246 | if (!sp->unsync_children) | |
1247 | return 0; | |
1248 | ||
1249 | mmu_pages_add(pvec, sp, 0); | |
1250 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1251 | } |
1252 | ||
4731d4c7 MT |
1253 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1254 | { | |
1255 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1256 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1257 | sp->unsync = 0; |
1258 | --kvm->stat.mmu_unsync; | |
1259 | } | |
1260 | ||
7775834a XG |
1261 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1262 | struct list_head *invalid_list); | |
1263 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1264 | struct list_head *invalid_list); | |
4731d4c7 | 1265 | |
f41d335a XG |
1266 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1267 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1268 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1269 | if ((sp)->gfn != (gfn)) {} else | |
1270 | ||
f41d335a XG |
1271 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1272 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1273 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1274 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1275 | (sp)->role.invalid) {} else | |
1276 | ||
f918b443 | 1277 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1278 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1279 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1280 | { |
5b7e0102 | 1281 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1282 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1283 | return 1; |
1284 | } | |
1285 | ||
f918b443 | 1286 | if (clear_unsync) |
1d9dc7e0 | 1287 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1288 | |
a4a8e6f7 | 1289 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1290 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1291 | return 1; |
1292 | } | |
1293 | ||
1294 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1295 | return 0; |
1296 | } | |
1297 | ||
1d9dc7e0 XG |
1298 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1299 | struct kvm_mmu_page *sp) | |
1300 | { | |
d98ba053 | 1301 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1302 | int ret; |
1303 | ||
d98ba053 | 1304 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1305 | if (ret) |
d98ba053 XG |
1306 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1307 | ||
1d9dc7e0 XG |
1308 | return ret; |
1309 | } | |
1310 | ||
d98ba053 XG |
1311 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1312 | struct list_head *invalid_list) | |
1d9dc7e0 | 1313 | { |
d98ba053 | 1314 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1315 | } |
1316 | ||
9f1a122f XG |
1317 | /* @gfn should be write-protected at the call site */ |
1318 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1319 | { | |
9f1a122f | 1320 | struct kvm_mmu_page *s; |
f41d335a | 1321 | struct hlist_node *node; |
d98ba053 | 1322 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1323 | bool flush = false; |
1324 | ||
f41d335a | 1325 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1326 | if (!s->unsync) |
9f1a122f XG |
1327 | continue; |
1328 | ||
1329 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1330 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1331 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1332 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1333 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1334 | continue; |
1335 | } | |
9f1a122f XG |
1336 | flush = true; |
1337 | } | |
1338 | ||
d98ba053 | 1339 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1340 | if (flush) |
1341 | kvm_mmu_flush_tlb(vcpu); | |
1342 | } | |
1343 | ||
60c8aec6 MT |
1344 | struct mmu_page_path { |
1345 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1346 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1347 | }; |
1348 | ||
60c8aec6 MT |
1349 | #define for_each_sp(pvec, sp, parents, i) \ |
1350 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1351 | sp = pvec.page[i].sp; \ | |
1352 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1353 | i = mmu_pages_next(&pvec, &parents, i)) | |
1354 | ||
cded19f3 HE |
1355 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1356 | struct mmu_page_path *parents, | |
1357 | int i) | |
60c8aec6 MT |
1358 | { |
1359 | int n; | |
1360 | ||
1361 | for (n = i+1; n < pvec->nr; n++) { | |
1362 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1363 | ||
1364 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1365 | parents->idx[0] = pvec->page[n].idx; | |
1366 | return n; | |
1367 | } | |
1368 | ||
1369 | parents->parent[sp->role.level-2] = sp; | |
1370 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1371 | } | |
1372 | ||
1373 | return n; | |
1374 | } | |
1375 | ||
cded19f3 | 1376 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1377 | { |
60c8aec6 MT |
1378 | struct kvm_mmu_page *sp; |
1379 | unsigned int level = 0; | |
1380 | ||
1381 | do { | |
1382 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1383 | |
60c8aec6 MT |
1384 | sp = parents->parent[level]; |
1385 | if (!sp) | |
1386 | return; | |
1387 | ||
1388 | --sp->unsync_children; | |
1389 | WARN_ON((int)sp->unsync_children < 0); | |
1390 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1391 | level++; | |
1392 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1393 | } |
1394 | ||
60c8aec6 MT |
1395 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1396 | struct mmu_page_path *parents, | |
1397 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1398 | { |
60c8aec6 MT |
1399 | parents->parent[parent->role.level-1] = NULL; |
1400 | pvec->nr = 0; | |
1401 | } | |
4731d4c7 | 1402 | |
60c8aec6 MT |
1403 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1404 | struct kvm_mmu_page *parent) | |
1405 | { | |
1406 | int i; | |
1407 | struct kvm_mmu_page *sp; | |
1408 | struct mmu_page_path parents; | |
1409 | struct kvm_mmu_pages pages; | |
d98ba053 | 1410 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1411 | |
1412 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1413 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1414 | int protected = 0; |
1415 | ||
1416 | for_each_sp(pages, sp, parents, i) | |
1417 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1418 | ||
1419 | if (protected) | |
1420 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1421 | ||
60c8aec6 | 1422 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1423 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1424 | mmu_pages_clear_parents(&parents); |
1425 | } | |
d98ba053 | 1426 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1427 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1428 | kvm_mmu_pages_init(parent, &parents, &pages); |
1429 | } | |
4731d4c7 MT |
1430 | } |
1431 | ||
cea0f0e7 AK |
1432 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1433 | gfn_t gfn, | |
1434 | gva_t gaddr, | |
1435 | unsigned level, | |
f6e2c02b | 1436 | int direct, |
41074d07 | 1437 | unsigned access, |
f7d9c7b7 | 1438 | u64 *parent_pte) |
cea0f0e7 AK |
1439 | { |
1440 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1441 | unsigned quadrant; |
9f1a122f | 1442 | struct kvm_mmu_page *sp; |
f41d335a | 1443 | struct hlist_node *node; |
9f1a122f | 1444 | bool need_sync = false; |
cea0f0e7 | 1445 | |
a770f6f2 | 1446 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1447 | role.level = level; |
f6e2c02b | 1448 | role.direct = direct; |
84b0c8c6 | 1449 | if (role.direct) |
5b7e0102 | 1450 | role.cr4_pae = 0; |
41074d07 | 1451 | role.access = access; |
c5a78f2b JR |
1452 | if (!vcpu->arch.mmu.direct_map |
1453 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1454 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1455 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1456 | role.quadrant = quadrant; | |
1457 | } | |
f41d335a | 1458 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1459 | if (!need_sync && sp->unsync) |
1460 | need_sync = true; | |
4731d4c7 | 1461 | |
7ae680eb XG |
1462 | if (sp->role.word != role.word) |
1463 | continue; | |
4731d4c7 | 1464 | |
7ae680eb XG |
1465 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1466 | break; | |
e02aa901 | 1467 | |
7ae680eb XG |
1468 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1469 | if (sp->unsync_children) { | |
a8eeb04a | 1470 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1471 | kvm_mmu_mark_parents_unsync(sp); |
1472 | } else if (sp->unsync) | |
1473 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1474 | |
7ae680eb XG |
1475 | trace_kvm_mmu_get_page(sp, false); |
1476 | return sp; | |
1477 | } | |
dfc5aa00 | 1478 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1479 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1480 | if (!sp) |
1481 | return sp; | |
4db35314 AK |
1482 | sp->gfn = gfn; |
1483 | sp->role = role; | |
7ae680eb XG |
1484 | hlist_add_head(&sp->hash_link, |
1485 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1486 | if (!direct) { |
b1a36821 MT |
1487 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1488 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1489 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1490 | kvm_sync_pages(vcpu, gfn); | |
1491 | ||
4731d4c7 MT |
1492 | account_shadowed(vcpu->kvm, gfn); |
1493 | } | |
131d8279 AK |
1494 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1495 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1496 | else | |
1497 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1498 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1499 | return sp; |
cea0f0e7 AK |
1500 | } |
1501 | ||
2d11123a AK |
1502 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1503 | struct kvm_vcpu *vcpu, u64 addr) | |
1504 | { | |
1505 | iterator->addr = addr; | |
1506 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1507 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1508 | |
1509 | if (iterator->level == PT64_ROOT_LEVEL && | |
1510 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1511 | !vcpu->arch.mmu.direct_map) | |
1512 | --iterator->level; | |
1513 | ||
2d11123a AK |
1514 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1515 | iterator->shadow_addr | |
1516 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1517 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1518 | --iterator->level; | |
1519 | if (!iterator->shadow_addr) | |
1520 | iterator->level = 0; | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1525 | { | |
1526 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1527 | return false; | |
4d88954d MT |
1528 | |
1529 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1530 | if (is_large_pte(*iterator->sptep)) | |
1531 | return false; | |
1532 | ||
2d11123a AK |
1533 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1534 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1535 | return true; | |
1536 | } | |
1537 | ||
1538 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1539 | { | |
1540 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1541 | --iterator->level; | |
1542 | } | |
1543 | ||
32ef26a3 AK |
1544 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1545 | { | |
1546 | u64 spte; | |
1547 | ||
1548 | spte = __pa(sp->spt) | |
1549 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1550 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
121eee97 | 1551 | __set_spte(sptep, spte); |
32ef26a3 AK |
1552 | } |
1553 | ||
a3aa51cf AK |
1554 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) |
1555 | { | |
1556 | if (is_large_pte(*sptep)) { | |
1557 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); | |
1558 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1559 | } | |
1560 | } | |
1561 | ||
a357bd22 AK |
1562 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1563 | unsigned direct_access) | |
1564 | { | |
1565 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1566 | struct kvm_mmu_page *child; | |
1567 | ||
1568 | /* | |
1569 | * For the direct sp, if the guest pte's dirty bit | |
1570 | * changed form clean to dirty, it will corrupt the | |
1571 | * sp's access: allow writable in the read-only sp, | |
1572 | * so we should update the spte at this point to get | |
1573 | * a new sp with the correct access. | |
1574 | */ | |
1575 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1576 | if (child->role.access == direct_access) | |
1577 | return; | |
1578 | ||
1579 | mmu_page_remove_parent_pte(child, sptep); | |
1580 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
1581 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1582 | } | |
1583 | } | |
1584 | ||
90cb0529 | 1585 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1586 | struct kvm_mmu_page *sp) |
a436036b | 1587 | { |
697fe2e2 AK |
1588 | unsigned i; |
1589 | u64 *pt; | |
1590 | u64 ent; | |
1591 | ||
4db35314 | 1592 | pt = sp->spt; |
697fe2e2 | 1593 | |
697fe2e2 AK |
1594 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1595 | ent = pt[i]; | |
1596 | ||
05da4558 | 1597 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1598 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1599 | ent &= PT64_BASE_ADDR_MASK; |
1600 | mmu_page_remove_parent_pte(page_header(ent), | |
1601 | &pt[i]); | |
1602 | } else { | |
776e6633 MT |
1603 | if (is_large_pte(ent)) |
1604 | --kvm->stat.lpages; | |
be38d276 AK |
1605 | drop_spte(kvm, &pt[i], |
1606 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1607 | } |
1608 | } | |
c7addb90 | 1609 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1610 | } |
a436036b AK |
1611 | } |
1612 | ||
4db35314 | 1613 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1614 | { |
4db35314 | 1615 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1616 | } |
1617 | ||
12b7d28f AK |
1618 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1619 | { | |
1620 | int i; | |
988a2cae | 1621 | struct kvm_vcpu *vcpu; |
12b7d28f | 1622 | |
988a2cae GN |
1623 | kvm_for_each_vcpu(i, vcpu, kvm) |
1624 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1625 | } |
1626 | ||
31aa2b44 | 1627 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1628 | { |
1629 | u64 *parent_pte; | |
1630 | ||
4db35314 AK |
1631 | while (sp->multimapped || sp->parent_pte) { |
1632 | if (!sp->multimapped) | |
1633 | parent_pte = sp->parent_pte; | |
a436036b AK |
1634 | else { |
1635 | struct kvm_pte_chain *chain; | |
1636 | ||
4db35314 | 1637 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1638 | struct kvm_pte_chain, link); |
1639 | parent_pte = chain->parent_ptes[0]; | |
1640 | } | |
697fe2e2 | 1641 | BUG_ON(!parent_pte); |
4db35314 | 1642 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1643 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1644 | } |
31aa2b44 AK |
1645 | } |
1646 | ||
60c8aec6 | 1647 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1648 | struct kvm_mmu_page *parent, |
1649 | struct list_head *invalid_list) | |
4731d4c7 | 1650 | { |
60c8aec6 MT |
1651 | int i, zapped = 0; |
1652 | struct mmu_page_path parents; | |
1653 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1654 | |
60c8aec6 | 1655 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1656 | return 0; |
60c8aec6 MT |
1657 | |
1658 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1659 | while (mmu_unsync_walk(parent, &pages)) { | |
1660 | struct kvm_mmu_page *sp; | |
1661 | ||
1662 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1663 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1664 | mmu_pages_clear_parents(&parents); |
77662e00 | 1665 | zapped++; |
60c8aec6 | 1666 | } |
60c8aec6 MT |
1667 | kvm_mmu_pages_init(parent, &parents, &pages); |
1668 | } | |
1669 | ||
1670 | return zapped; | |
4731d4c7 MT |
1671 | } |
1672 | ||
7775834a XG |
1673 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1674 | struct list_head *invalid_list) | |
31aa2b44 | 1675 | { |
4731d4c7 | 1676 | int ret; |
f691fe1d | 1677 | |
7775834a | 1678 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1679 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1680 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1681 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1682 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1683 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1684 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1685 | if (sp->unsync) |
1686 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1687 | if (!sp->root_count) { |
54a4f023 GJ |
1688 | /* Count self */ |
1689 | ret++; | |
7775834a | 1690 | list_move(&sp->link, invalid_list); |
2e53d63a | 1691 | } else { |
5b5c6a5a | 1692 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1693 | kvm_reload_remote_mmus(kvm); |
1694 | } | |
7775834a XG |
1695 | |
1696 | sp->role.invalid = 1; | |
12b7d28f | 1697 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1698 | return ret; |
a436036b AK |
1699 | } |
1700 | ||
7775834a XG |
1701 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1702 | struct list_head *invalid_list) | |
1703 | { | |
1704 | struct kvm_mmu_page *sp; | |
1705 | ||
1706 | if (list_empty(invalid_list)) | |
1707 | return; | |
1708 | ||
1709 | kvm_flush_remote_tlbs(kvm); | |
1710 | ||
1711 | do { | |
1712 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1713 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1714 | kvm_mmu_free_page(kvm, sp); | |
1715 | } while (!list_empty(invalid_list)); | |
1716 | ||
1717 | } | |
1718 | ||
82ce2c96 IE |
1719 | /* |
1720 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 1721 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 1722 | */ |
49d5ca26 | 1723 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 1724 | { |
d98ba053 | 1725 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
1726 | /* |
1727 | * If we set the number of mmu pages to be smaller be than the | |
1728 | * number of actived pages , we must to free some mmu pages before we | |
1729 | * change the value | |
1730 | */ | |
1731 | ||
49d5ca26 DH |
1732 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
1733 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 1734 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
1735 | struct kvm_mmu_page *page; |
1736 | ||
f05e70ac | 1737 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1738 | struct kvm_mmu_page, link); |
80b63faf XF |
1739 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
1740 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
82ce2c96 | 1741 | } |
49d5ca26 | 1742 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 1743 | } |
82ce2c96 | 1744 | |
49d5ca26 | 1745 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
1746 | } |
1747 | ||
f67a46f4 | 1748 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1749 | { |
4db35314 | 1750 | struct kvm_mmu_page *sp; |
f41d335a | 1751 | struct hlist_node *node; |
d98ba053 | 1752 | LIST_HEAD(invalid_list); |
a436036b AK |
1753 | int r; |
1754 | ||
9ad17b10 | 1755 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 1756 | r = 0; |
f41d335a XG |
1757 | |
1758 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
9ad17b10 | 1759 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
1760 | sp->role.word); |
1761 | r = 1; | |
f41d335a | 1762 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1763 | } |
d98ba053 | 1764 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1765 | return r; |
cea0f0e7 AK |
1766 | } |
1767 | ||
f67a46f4 | 1768 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1769 | { |
4db35314 | 1770 | struct kvm_mmu_page *sp; |
f41d335a | 1771 | struct hlist_node *node; |
d98ba053 | 1772 | LIST_HEAD(invalid_list); |
97a0a01e | 1773 | |
f41d335a | 1774 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 1775 | pgprintk("%s: zap %llx %x\n", |
7ae680eb | 1776 | __func__, gfn, sp->role.word); |
f41d335a | 1777 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1778 | } |
d98ba053 | 1779 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1780 | } |
1781 | ||
38c335f1 | 1782 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1783 | { |
bc6678a3 | 1784 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1785 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1786 | |
291f26bc | 1787 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1788 | } |
1789 | ||
6844dec6 MT |
1790 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1791 | { | |
1792 | int i; | |
1793 | u64 *pt = sp->spt; | |
1794 | ||
1795 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1796 | return; | |
1797 | ||
1798 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1799 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1800 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1801 | } |
1802 | } | |
1803 | ||
74be52e3 SY |
1804 | /* |
1805 | * The function is based on mtrr_type_lookup() in | |
1806 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1807 | */ | |
1808 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1809 | u64 start, u64 end) | |
1810 | { | |
1811 | int i; | |
1812 | u64 base, mask; | |
1813 | u8 prev_match, curr_match; | |
1814 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1815 | ||
1816 | if (!mtrr_state->enabled) | |
1817 | return 0xFF; | |
1818 | ||
1819 | /* Make end inclusive end, instead of exclusive */ | |
1820 | end--; | |
1821 | ||
1822 | /* Look in fixed ranges. Just return the type as per start */ | |
1823 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1824 | int idx; | |
1825 | ||
1826 | if (start < 0x80000) { | |
1827 | idx = 0; | |
1828 | idx += (start >> 16); | |
1829 | return mtrr_state->fixed_ranges[idx]; | |
1830 | } else if (start < 0xC0000) { | |
1831 | idx = 1 * 8; | |
1832 | idx += ((start - 0x80000) >> 14); | |
1833 | return mtrr_state->fixed_ranges[idx]; | |
1834 | } else if (start < 0x1000000) { | |
1835 | idx = 3 * 8; | |
1836 | idx += ((start - 0xC0000) >> 12); | |
1837 | return mtrr_state->fixed_ranges[idx]; | |
1838 | } | |
1839 | } | |
1840 | ||
1841 | /* | |
1842 | * Look in variable ranges | |
1843 | * Look of multiple ranges matching this address and pick type | |
1844 | * as per MTRR precedence | |
1845 | */ | |
1846 | if (!(mtrr_state->enabled & 2)) | |
1847 | return mtrr_state->def_type; | |
1848 | ||
1849 | prev_match = 0xFF; | |
1850 | for (i = 0; i < num_var_ranges; ++i) { | |
1851 | unsigned short start_state, end_state; | |
1852 | ||
1853 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1854 | continue; | |
1855 | ||
1856 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1857 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1858 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1859 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1860 | ||
1861 | start_state = ((start & mask) == (base & mask)); | |
1862 | end_state = ((end & mask) == (base & mask)); | |
1863 | if (start_state != end_state) | |
1864 | return 0xFE; | |
1865 | ||
1866 | if ((start & mask) != (base & mask)) | |
1867 | continue; | |
1868 | ||
1869 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1870 | if (prev_match == 0xFF) { | |
1871 | prev_match = curr_match; | |
1872 | continue; | |
1873 | } | |
1874 | ||
1875 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1876 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1877 | return MTRR_TYPE_UNCACHABLE; | |
1878 | ||
1879 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1880 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1881 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1882 | curr_match == MTRR_TYPE_WRBACK)) { | |
1883 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1884 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1885 | } | |
1886 | ||
1887 | if (prev_match != curr_match) | |
1888 | return MTRR_TYPE_UNCACHABLE; | |
1889 | } | |
1890 | ||
1891 | if (prev_match != 0xFF) | |
1892 | return prev_match; | |
1893 | ||
1894 | return mtrr_state->def_type; | |
1895 | } | |
1896 | ||
4b12f0de | 1897 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1898 | { |
1899 | u8 mtrr; | |
1900 | ||
1901 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1902 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1903 | if (mtrr == 0xfe || mtrr == 0xff) | |
1904 | mtrr = MTRR_TYPE_WRBACK; | |
1905 | return mtrr; | |
1906 | } | |
4b12f0de | 1907 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1908 | |
9cf5cf5a XG |
1909 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1910 | { | |
1911 | trace_kvm_mmu_unsync_page(sp); | |
1912 | ++vcpu->kvm->stat.mmu_unsync; | |
1913 | sp->unsync = 1; | |
1914 | ||
1915 | kvm_mmu_mark_parents_unsync(sp); | |
1916 | mmu_convert_notrap(sp); | |
1917 | } | |
1918 | ||
1919 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1920 | { |
4731d4c7 | 1921 | struct kvm_mmu_page *s; |
f41d335a | 1922 | struct hlist_node *node; |
9cf5cf5a | 1923 | |
f41d335a | 1924 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1925 | if (s->unsync) |
4731d4c7 | 1926 | continue; |
9cf5cf5a XG |
1927 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1928 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1929 | } |
4731d4c7 MT |
1930 | } |
1931 | ||
1932 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1933 | bool can_unsync) | |
1934 | { | |
9cf5cf5a | 1935 | struct kvm_mmu_page *s; |
f41d335a | 1936 | struct hlist_node *node; |
9cf5cf5a XG |
1937 | bool need_unsync = false; |
1938 | ||
f41d335a | 1939 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1940 | if (!can_unsync) |
1941 | return 1; | |
1942 | ||
9cf5cf5a | 1943 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1944 | return 1; |
9cf5cf5a XG |
1945 | |
1946 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1947 | if (!oos_shadow) |
9cf5cf5a XG |
1948 | return 1; |
1949 | need_unsync = true; | |
1950 | } | |
4731d4c7 | 1951 | } |
9cf5cf5a XG |
1952 | if (need_unsync) |
1953 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1954 | return 0; |
1955 | } | |
1956 | ||
d555c333 | 1957 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1958 | unsigned pte_access, int user_fault, |
852e3c19 | 1959 | int write_fault, int dirty, int level, |
c2d0ee46 | 1960 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 1961 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 1962 | { |
b330aa0c | 1963 | u64 spte, entry = *sptep; |
1e73f9dd | 1964 | int ret = 0; |
64d4d521 | 1965 | |
1c4f1fd6 AK |
1966 | /* |
1967 | * We don't set the accessed bit, since we sometimes want to see | |
1968 | * whether the guest actually used the pte (in order to detect | |
1969 | * demand paging). | |
1970 | */ | |
982c2565 | 1971 | spte = PT_PRESENT_MASK; |
947da538 | 1972 | if (!speculative) |
3201b5d9 | 1973 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1974 | if (!dirty) |
1975 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1976 | if (pte_access & ACC_EXEC_MASK) |
1977 | spte |= shadow_x_mask; | |
1978 | else | |
1979 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1980 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1981 | spte |= shadow_user_mask; |
852e3c19 | 1982 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1983 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 1984 | if (tdp_enabled) |
4b12f0de SY |
1985 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
1986 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1987 | |
9bdbba13 | 1988 | if (host_writable) |
1403283a IE |
1989 | spte |= SPTE_HOST_WRITEABLE; |
1990 | ||
35149e21 | 1991 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1992 | |
1993 | if ((pte_access & ACC_WRITE_MASK) | |
c5a78f2b JR |
1994 | || (!vcpu->arch.mmu.direct_map && write_fault |
1995 | && !is_write_protection(vcpu) && !user_fault)) { | |
1c4f1fd6 | 1996 | |
852e3c19 JR |
1997 | if (level > PT_PAGE_TABLE_LEVEL && |
1998 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1999 | ret = 1; |
be38d276 AK |
2000 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
2001 | goto done; | |
38187c83 MT |
2002 | } |
2003 | ||
1c4f1fd6 | 2004 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 2005 | |
c5a78f2b JR |
2006 | if (!vcpu->arch.mmu.direct_map |
2007 | && !(pte_access & ACC_WRITE_MASK)) | |
69325a12 AK |
2008 | spte &= ~PT_USER_MASK; |
2009 | ||
ecc5589f MT |
2010 | /* |
2011 | * Optimization: for pte sync, if spte was writable the hash | |
2012 | * lookup is unnecessary (and expensive). Write protection | |
2013 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2014 | * Same reasoning can be applied to dirty page accounting. | |
2015 | */ | |
8dae4445 | 2016 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2017 | goto set_pte; |
2018 | ||
4731d4c7 | 2019 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2020 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2021 | __func__, gfn); |
1e73f9dd | 2022 | ret = 1; |
1c4f1fd6 | 2023 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 2024 | if (is_writable_pte(spte)) |
1c4f1fd6 | 2025 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
2026 | } |
2027 | } | |
2028 | ||
1c4f1fd6 AK |
2029 | if (pte_access & ACC_WRITE_MASK) |
2030 | mark_page_dirty(vcpu->kvm, gfn); | |
2031 | ||
38187c83 | 2032 | set_pte: |
b79b93f9 | 2033 | update_spte(sptep, spte); |
b330aa0c XG |
2034 | /* |
2035 | * If we overwrite a writable spte with a read-only one we | |
2036 | * should flush remote TLBs. Otherwise rmap_write_protect | |
2037 | * will find a read-only spte, even though the writable spte | |
2038 | * might be cached on a CPU's TLB. | |
2039 | */ | |
2040 | if (is_writable_pte(entry) && !is_writable_pte(*sptep)) | |
2041 | kvm_flush_remote_tlbs(vcpu->kvm); | |
be38d276 | 2042 | done: |
1e73f9dd MT |
2043 | return ret; |
2044 | } | |
2045 | ||
d555c333 | 2046 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
2047 | unsigned pt_access, unsigned pte_access, |
2048 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 2049 | int *ptwrite, int level, gfn_t gfn, |
1403283a | 2050 | pfn_t pfn, bool speculative, |
9bdbba13 | 2051 | bool host_writable) |
1e73f9dd MT |
2052 | { |
2053 | int was_rmapped = 0; | |
53a27b39 | 2054 | int rmap_count; |
1e73f9dd MT |
2055 | |
2056 | pgprintk("%s: spte %llx access %x write_fault %d" | |
9ad17b10 | 2057 | " user_fault %d gfn %llx\n", |
d555c333 | 2058 | __func__, *sptep, pt_access, |
1e73f9dd MT |
2059 | write_fault, user_fault, gfn); |
2060 | ||
d555c333 | 2061 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2062 | /* |
2063 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2064 | * the parent of the now unreachable PTE. | |
2065 | */ | |
852e3c19 JR |
2066 | if (level > PT_PAGE_TABLE_LEVEL && |
2067 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2068 | struct kvm_mmu_page *child; |
d555c333 | 2069 | u64 pte = *sptep; |
1e73f9dd MT |
2070 | |
2071 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 2072 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
2073 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
2074 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 2075 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2076 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2077 | spte_to_pfn(*sptep), pfn); |
be38d276 | 2078 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 2079 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2080 | } else |
2081 | was_rmapped = 1; | |
1e73f9dd | 2082 | } |
852e3c19 | 2083 | |
d555c333 | 2084 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a | 2085 | dirty, level, gfn, pfn, speculative, true, |
9bdbba13 | 2086 | host_writable)) { |
1e73f9dd MT |
2087 | if (write_fault) |
2088 | *ptwrite = 1; | |
5304efde | 2089 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2090 | } |
1e73f9dd | 2091 | |
d555c333 | 2092 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2093 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2094 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2095 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2096 | *sptep, sptep); | |
d555c333 | 2097 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2098 | ++vcpu->kvm->stat.lpages; |
2099 | ||
d555c333 | 2100 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2101 | if (!was_rmapped) { |
44ad9944 | 2102 | rmap_count = rmap_add(vcpu, sptep, gfn); |
53a27b39 | 2103 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2104 | rmap_recycle(vcpu, sptep, gfn); |
1c4f1fd6 | 2105 | } |
9ed5520d | 2106 | kvm_release_pfn_clean(pfn); |
1b7fcd32 | 2107 | if (speculative) { |
d555c333 | 2108 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2109 | vcpu->arch.last_pte_gfn = gfn; |
2110 | } | |
1c4f1fd6 AK |
2111 | } |
2112 | ||
6aa8b732 AK |
2113 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2114 | { | |
2115 | } | |
2116 | ||
957ed9ef XG |
2117 | static struct kvm_memory_slot * |
2118 | pte_prefetch_gfn_to_memslot(struct kvm_vcpu *vcpu, gfn_t gfn, bool no_dirty_log) | |
2119 | { | |
2120 | struct kvm_memory_slot *slot; | |
2121 | ||
2122 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
2123 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
2124 | (no_dirty_log && slot->dirty_bitmap)) | |
2125 | slot = NULL; | |
2126 | ||
2127 | return slot; | |
2128 | } | |
2129 | ||
2130 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2131 | bool no_dirty_log) | |
2132 | { | |
2133 | struct kvm_memory_slot *slot; | |
2134 | unsigned long hva; | |
2135 | ||
2136 | slot = pte_prefetch_gfn_to_memslot(vcpu, gfn, no_dirty_log); | |
2137 | if (!slot) { | |
2138 | get_page(bad_page); | |
2139 | return page_to_pfn(bad_page); | |
2140 | } | |
2141 | ||
2142 | hva = gfn_to_hva_memslot(slot, gfn); | |
2143 | ||
2144 | return hva_to_pfn_atomic(vcpu->kvm, hva); | |
2145 | } | |
2146 | ||
2147 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2148 | struct kvm_mmu_page *sp, | |
2149 | u64 *start, u64 *end) | |
2150 | { | |
2151 | struct page *pages[PTE_PREFETCH_NUM]; | |
2152 | unsigned access = sp->role.access; | |
2153 | int i, ret; | |
2154 | gfn_t gfn; | |
2155 | ||
2156 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
2157 | if (!pte_prefetch_gfn_to_memslot(vcpu, gfn, access & ACC_WRITE_MASK)) | |
2158 | return -1; | |
2159 | ||
2160 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2161 | if (ret <= 0) | |
2162 | return -1; | |
2163 | ||
2164 | for (i = 0; i < ret; i++, gfn++, start++) | |
2165 | mmu_set_spte(vcpu, start, ACC_ALL, | |
2166 | access, 0, 0, 1, NULL, | |
2167 | sp->role.level, gfn, | |
2168 | page_to_pfn(pages[i]), true, true); | |
2169 | ||
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2174 | struct kvm_mmu_page *sp, u64 *sptep) | |
2175 | { | |
2176 | u64 *spte, *start = NULL; | |
2177 | int i; | |
2178 | ||
2179 | WARN_ON(!sp->role.direct); | |
2180 | ||
2181 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2182 | spte = sp->spt + i; | |
2183 | ||
2184 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
2185 | if (*spte != shadow_trap_nonpresent_pte || spte == sptep) { | |
2186 | if (!start) | |
2187 | continue; | |
2188 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2189 | break; | |
2190 | start = NULL; | |
2191 | } else if (!start) | |
2192 | start = spte; | |
2193 | } | |
2194 | } | |
2195 | ||
2196 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2197 | { | |
2198 | struct kvm_mmu_page *sp; | |
2199 | ||
2200 | /* | |
2201 | * Since it's no accessed bit on EPT, it's no way to | |
2202 | * distinguish between actually accessed translations | |
2203 | * and prefetched, so disable pte prefetch if EPT is | |
2204 | * enabled. | |
2205 | */ | |
2206 | if (!shadow_accessed_mask) | |
2207 | return; | |
2208 | ||
2209 | sp = page_header(__pa(sptep)); | |
2210 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2211 | return; | |
2212 | ||
2213 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2214 | } | |
2215 | ||
9f652d21 | 2216 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2217 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2218 | bool prefault) | |
140754bc | 2219 | { |
9f652d21 | 2220 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2221 | struct kvm_mmu_page *sp; |
9f652d21 | 2222 | int pt_write = 0; |
140754bc | 2223 | gfn_t pseudo_gfn; |
6aa8b732 | 2224 | |
9f652d21 | 2225 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2226 | if (iterator.level == level) { |
612819c3 MT |
2227 | unsigned pte_access = ACC_ALL; |
2228 | ||
2229 | if (!map_writable) | |
2230 | pte_access &= ~ACC_WRITE_MASK; | |
2231 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, | |
9f652d21 | 2232 | 0, write, 1, &pt_write, |
2ec4739d | 2233 | level, gfn, pfn, prefault, map_writable); |
957ed9ef | 2234 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2235 | ++vcpu->stat.pf_fixed; |
2236 | break; | |
6aa8b732 AK |
2237 | } |
2238 | ||
9f652d21 | 2239 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2240 | u64 base_addr = iterator.addr; |
2241 | ||
2242 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2243 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2244 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2245 | iterator.level - 1, | |
2246 | 1, ACC_ALL, iterator.sptep); | |
2247 | if (!sp) { | |
2248 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2249 | kvm_release_pfn_clean(pfn); | |
2250 | return -ENOMEM; | |
2251 | } | |
140754bc | 2252 | |
d555c333 AK |
2253 | __set_spte(iterator.sptep, |
2254 | __pa(sp->spt) | |
2255 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
33f91edb XG |
2256 | | shadow_user_mask | shadow_x_mask |
2257 | | shadow_accessed_mask); | |
9f652d21 AK |
2258 | } |
2259 | } | |
2260 | return pt_write; | |
6aa8b732 AK |
2261 | } |
2262 | ||
77db5cbd | 2263 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2264 | { |
77db5cbd HY |
2265 | siginfo_t info; |
2266 | ||
2267 | info.si_signo = SIGBUS; | |
2268 | info.si_errno = 0; | |
2269 | info.si_code = BUS_MCEERR_AR; | |
2270 | info.si_addr = (void __user *)address; | |
2271 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2272 | |
77db5cbd | 2273 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2274 | } |
2275 | ||
2276 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2277 | { | |
2278 | kvm_release_pfn_clean(pfn); | |
2279 | if (is_hwpoison_pfn(pfn)) { | |
77db5cbd | 2280 | kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current); |
bf998156 | 2281 | return 0; |
edba23e5 GN |
2282 | } else if (is_fault_pfn(pfn)) |
2283 | return -EFAULT; | |
2284 | ||
bf998156 HY |
2285 | return 1; |
2286 | } | |
2287 | ||
78b2c54a | 2288 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2289 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2290 | ||
2291 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn, | |
78b2c54a | 2292 | bool prefault) |
10589a46 MT |
2293 | { |
2294 | int r; | |
852e3c19 | 2295 | int level; |
35149e21 | 2296 | pfn_t pfn; |
e930bffe | 2297 | unsigned long mmu_seq; |
612819c3 | 2298 | bool map_writable; |
aaee2c94 | 2299 | |
852e3c19 JR |
2300 | level = mapping_level(vcpu, gfn); |
2301 | ||
2302 | /* | |
2303 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2304 | * maximum. Therefore check if the level is larger than that. | |
2305 | */ | |
2306 | if (level > PT_DIRECTORY_LEVEL) | |
2307 | level = PT_DIRECTORY_LEVEL; | |
2308 | ||
2309 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2310 | |
e930bffe | 2311 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2312 | smp_rmb(); |
060c2abe | 2313 | |
78b2c54a | 2314 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2315 | return 0; |
aaee2c94 | 2316 | |
d196e343 | 2317 | /* mmio */ |
bf998156 HY |
2318 | if (is_error_pfn(pfn)) |
2319 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2320 | |
aaee2c94 | 2321 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2322 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2323 | goto out_unlock; | |
eb787d10 | 2324 | kvm_mmu_free_some_pages(vcpu); |
2ec4739d XG |
2325 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2326 | prefault); | |
aaee2c94 MT |
2327 | spin_unlock(&vcpu->kvm->mmu_lock); |
2328 | ||
aaee2c94 | 2329 | |
10589a46 | 2330 | return r; |
e930bffe AA |
2331 | |
2332 | out_unlock: | |
2333 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2334 | kvm_release_pfn_clean(pfn); | |
2335 | return 0; | |
10589a46 MT |
2336 | } |
2337 | ||
2338 | ||
17ac10ad AK |
2339 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2340 | { | |
2341 | int i; | |
4db35314 | 2342 | struct kvm_mmu_page *sp; |
d98ba053 | 2343 | LIST_HEAD(invalid_list); |
17ac10ad | 2344 | |
ad312c7c | 2345 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2346 | return; |
aaee2c94 | 2347 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2348 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2349 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2350 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2351 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2352 | |
4db35314 AK |
2353 | sp = page_header(root); |
2354 | --sp->root_count; | |
d98ba053 XG |
2355 | if (!sp->root_count && sp->role.invalid) { |
2356 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2357 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2358 | } | |
ad312c7c | 2359 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2360 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2361 | return; |
2362 | } | |
17ac10ad | 2363 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2364 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2365 | |
417726a3 | 2366 | if (root) { |
417726a3 | 2367 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2368 | sp = page_header(root); |
2369 | --sp->root_count; | |
2e53d63a | 2370 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2371 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2372 | &invalid_list); | |
417726a3 | 2373 | } |
ad312c7c | 2374 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2375 | } |
d98ba053 | 2376 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2377 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2378 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2379 | } |
2380 | ||
8986ecc0 MT |
2381 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2382 | { | |
2383 | int ret = 0; | |
2384 | ||
2385 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2386 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2387 | ret = 1; |
2388 | } | |
2389 | ||
2390 | return ret; | |
2391 | } | |
2392 | ||
651dd37a JR |
2393 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2394 | { | |
2395 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2396 | unsigned i; |
651dd37a JR |
2397 | |
2398 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2399 | spin_lock(&vcpu->kvm->mmu_lock); | |
2400 | kvm_mmu_free_some_pages(vcpu); | |
2401 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2402 | 1, ACC_ALL, NULL); | |
2403 | ++sp->root_count; | |
2404 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2405 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2406 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2407 | for (i = 0; i < 4; ++i) { | |
2408 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2409 | ||
2410 | ASSERT(!VALID_PAGE(root)); | |
2411 | spin_lock(&vcpu->kvm->mmu_lock); | |
2412 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2413 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2414 | i << 30, | |
651dd37a JR |
2415 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2416 | NULL); | |
2417 | root = __pa(sp->spt); | |
2418 | ++sp->root_count; | |
2419 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2420 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2421 | } |
6292757f | 2422 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2423 | } else |
2424 | BUG(); | |
2425 | ||
2426 | return 0; | |
2427 | } | |
2428 | ||
2429 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2430 | { |
4db35314 | 2431 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2432 | u64 pdptr, pm_mask; |
2433 | gfn_t root_gfn; | |
2434 | int i; | |
3bb65a22 | 2435 | |
5777ed34 | 2436 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2437 | |
651dd37a JR |
2438 | if (mmu_check_root(vcpu, root_gfn)) |
2439 | return 1; | |
2440 | ||
2441 | /* | |
2442 | * Do we shadow a long mode page table? If so we need to | |
2443 | * write-protect the guests page table root. | |
2444 | */ | |
2445 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2446 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2447 | |
2448 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2449 | |
8facbbff | 2450 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2451 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2452 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2453 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2454 | root = __pa(sp->spt); |
2455 | ++sp->root_count; | |
8facbbff | 2456 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2457 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2458 | return 0; |
17ac10ad | 2459 | } |
f87f9288 | 2460 | |
651dd37a JR |
2461 | /* |
2462 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
2463 | * or a PAE 3-level page table. In either case we need to be aware that |
2464 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 2465 | */ |
81407ca5 JR |
2466 | pm_mask = PT_PRESENT_MASK; |
2467 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
2468 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
2469 | ||
17ac10ad | 2470 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2471 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2472 | |
2473 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2474 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
d41d1895 | 2475 | pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i); |
43a3795a | 2476 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2477 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2478 | continue; |
2479 | } | |
6de4f3ad | 2480 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
2481 | if (mmu_check_root(vcpu, root_gfn)) |
2482 | return 1; | |
5a7388c2 | 2483 | } |
8facbbff | 2484 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2485 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2486 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 2487 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 2488 | ACC_ALL, NULL); |
4db35314 AK |
2489 | root = __pa(sp->spt); |
2490 | ++sp->root_count; | |
8facbbff AK |
2491 | spin_unlock(&vcpu->kvm->mmu_lock); |
2492 | ||
81407ca5 | 2493 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 2494 | } |
6292757f | 2495 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
2496 | |
2497 | /* | |
2498 | * If we shadow a 32 bit page table with a long mode page | |
2499 | * table we enter this path. | |
2500 | */ | |
2501 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2502 | if (vcpu->arch.mmu.lm_root == NULL) { | |
2503 | /* | |
2504 | * The additional page necessary for this is only | |
2505 | * allocated on demand. | |
2506 | */ | |
2507 | ||
2508 | u64 *lm_root; | |
2509 | ||
2510 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
2511 | if (lm_root == NULL) | |
2512 | return 1; | |
2513 | ||
2514 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
2515 | ||
2516 | vcpu->arch.mmu.lm_root = lm_root; | |
2517 | } | |
2518 | ||
2519 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
2520 | } | |
2521 | ||
8986ecc0 | 2522 | return 0; |
17ac10ad AK |
2523 | } |
2524 | ||
651dd37a JR |
2525 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
2526 | { | |
2527 | if (vcpu->arch.mmu.direct_map) | |
2528 | return mmu_alloc_direct_roots(vcpu); | |
2529 | else | |
2530 | return mmu_alloc_shadow_roots(vcpu); | |
2531 | } | |
2532 | ||
0ba73cda MT |
2533 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2534 | { | |
2535 | int i; | |
2536 | struct kvm_mmu_page *sp; | |
2537 | ||
81407ca5 JR |
2538 | if (vcpu->arch.mmu.direct_map) |
2539 | return; | |
2540 | ||
0ba73cda MT |
2541 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2542 | return; | |
6903074c XG |
2543 | |
2544 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
81407ca5 | 2545 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
2546 | hpa_t root = vcpu->arch.mmu.root_hpa; |
2547 | sp = page_header(root); | |
2548 | mmu_sync_children(vcpu, sp); | |
5054c0de | 2549 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2550 | return; |
2551 | } | |
2552 | for (i = 0; i < 4; ++i) { | |
2553 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2554 | ||
8986ecc0 | 2555 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2556 | root &= PT64_BASE_ADDR_MASK; |
2557 | sp = page_header(root); | |
2558 | mmu_sync_children(vcpu, sp); | |
2559 | } | |
2560 | } | |
6903074c | 2561 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
2562 | } |
2563 | ||
2564 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2565 | { | |
2566 | spin_lock(&vcpu->kvm->mmu_lock); | |
2567 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2568 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2569 | } |
2570 | ||
1871c602 | 2571 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 2572 | u32 access, struct x86_exception *exception) |
6aa8b732 | 2573 | { |
ab9ae313 AK |
2574 | if (exception) |
2575 | exception->error_code = 0; | |
6aa8b732 AK |
2576 | return vaddr; |
2577 | } | |
2578 | ||
6539e738 | 2579 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
2580 | u32 access, |
2581 | struct x86_exception *exception) | |
6539e738 | 2582 | { |
ab9ae313 AK |
2583 | if (exception) |
2584 | exception->error_code = 0; | |
6539e738 JR |
2585 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
2586 | } | |
2587 | ||
6aa8b732 | 2588 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 2589 | u32 error_code, bool prefault) |
6aa8b732 | 2590 | { |
e833240f | 2591 | gfn_t gfn; |
e2dec939 | 2592 | int r; |
6aa8b732 | 2593 | |
b8688d51 | 2594 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2595 | r = mmu_topup_memory_caches(vcpu); |
2596 | if (r) | |
2597 | return r; | |
714b93da | 2598 | |
6aa8b732 | 2599 | ASSERT(vcpu); |
ad312c7c | 2600 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2601 | |
e833240f | 2602 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2603 | |
e833240f | 2604 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
78b2c54a | 2605 | error_code & PFERR_WRITE_MASK, gfn, prefault); |
6aa8b732 AK |
2606 | } |
2607 | ||
7e1fbeac | 2608 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
2609 | { |
2610 | struct kvm_arch_async_pf arch; | |
fb67e14f | 2611 | |
7c90705b | 2612 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 2613 | arch.gfn = gfn; |
c4806acd | 2614 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 2615 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
2616 | |
2617 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
2618 | } | |
2619 | ||
2620 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
2621 | { | |
2622 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
2623 | kvm_event_needs_reinjection(vcpu))) | |
2624 | return false; | |
2625 | ||
2626 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
2627 | } | |
2628 | ||
78b2c54a | 2629 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 2630 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
2631 | { |
2632 | bool async; | |
2633 | ||
612819c3 | 2634 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
2635 | |
2636 | if (!async) | |
2637 | return false; /* *pfn has correct page already */ | |
2638 | ||
2639 | put_page(pfn_to_page(*pfn)); | |
2640 | ||
78b2c54a | 2641 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 2642 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
2643 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
2644 | trace_kvm_async_pf_doublefault(gva, gfn); | |
2645 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2646 | return true; | |
2647 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
2648 | return true; | |
2649 | } | |
2650 | ||
612819c3 | 2651 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
2652 | |
2653 | return false; | |
2654 | } | |
2655 | ||
56028d08 | 2656 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 2657 | bool prefault) |
fb72d167 | 2658 | { |
35149e21 | 2659 | pfn_t pfn; |
fb72d167 | 2660 | int r; |
852e3c19 | 2661 | int level; |
05da4558 | 2662 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2663 | unsigned long mmu_seq; |
612819c3 MT |
2664 | int write = error_code & PFERR_WRITE_MASK; |
2665 | bool map_writable; | |
fb72d167 JR |
2666 | |
2667 | ASSERT(vcpu); | |
2668 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2669 | ||
2670 | r = mmu_topup_memory_caches(vcpu); | |
2671 | if (r) | |
2672 | return r; | |
2673 | ||
852e3c19 JR |
2674 | level = mapping_level(vcpu, gfn); |
2675 | ||
2676 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2677 | ||
e930bffe | 2678 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2679 | smp_rmb(); |
af585b92 | 2680 | |
78b2c54a | 2681 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
2682 | return 0; |
2683 | ||
2684 | /* mmio */ | |
bf998156 HY |
2685 | if (is_error_pfn(pfn)) |
2686 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2687 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2688 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2689 | goto out_unlock; | |
fb72d167 | 2690 | kvm_mmu_free_some_pages(vcpu); |
612819c3 | 2691 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 2692 | level, gfn, pfn, prefault); |
fb72d167 | 2693 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2694 | |
2695 | return r; | |
e930bffe AA |
2696 | |
2697 | out_unlock: | |
2698 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2699 | kvm_release_pfn_clean(pfn); | |
2700 | return 0; | |
fb72d167 JR |
2701 | } |
2702 | ||
6aa8b732 AK |
2703 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2704 | { | |
17ac10ad | 2705 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2706 | } |
2707 | ||
52fde8df JR |
2708 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
2709 | struct kvm_mmu *context) | |
6aa8b732 | 2710 | { |
6aa8b732 AK |
2711 | context->new_cr3 = nonpaging_new_cr3; |
2712 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2713 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2714 | context->free = nonpaging_free; | |
c7addb90 | 2715 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2716 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2717 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2718 | context->root_level = 0; |
6aa8b732 | 2719 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2720 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2721 | context->direct_map = true; |
2d48a985 | 2722 | context->nx = false; |
6aa8b732 AK |
2723 | return 0; |
2724 | } | |
2725 | ||
d835dfec | 2726 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2727 | { |
1165f5fe | 2728 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2729 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2730 | } |
2731 | ||
2732 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2733 | { | |
b8688d51 | 2734 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2735 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2736 | } |
2737 | ||
5777ed34 JR |
2738 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
2739 | { | |
2740 | return vcpu->arch.cr3; | |
2741 | } | |
2742 | ||
6389ee94 AK |
2743 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2744 | struct x86_exception *fault) | |
6aa8b732 | 2745 | { |
6389ee94 | 2746 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
2747 | } |
2748 | ||
6aa8b732 AK |
2749 | static void paging_free(struct kvm_vcpu *vcpu) |
2750 | { | |
2751 | nonpaging_free(vcpu); | |
2752 | } | |
2753 | ||
3241f22d | 2754 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
82725b20 DE |
2755 | { |
2756 | int bit7; | |
2757 | ||
2758 | bit7 = (gpte >> 7) & 1; | |
3241f22d | 2759 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; |
82725b20 DE |
2760 | } |
2761 | ||
6aa8b732 AK |
2762 | #define PTTYPE 64 |
2763 | #include "paging_tmpl.h" | |
2764 | #undef PTTYPE | |
2765 | ||
2766 | #define PTTYPE 32 | |
2767 | #include "paging_tmpl.h" | |
2768 | #undef PTTYPE | |
2769 | ||
52fde8df JR |
2770 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
2771 | struct kvm_mmu *context, | |
2772 | int level) | |
82725b20 | 2773 | { |
82725b20 DE |
2774 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
2775 | u64 exb_bit_rsvd = 0; | |
2776 | ||
2d48a985 | 2777 | if (!context->nx) |
82725b20 DE |
2778 | exb_bit_rsvd = rsvd_bits(63, 63); |
2779 | switch (level) { | |
2780 | case PT32_ROOT_LEVEL: | |
2781 | /* no rsvd bits for 2 level 4K page table entries */ | |
2782 | context->rsvd_bits_mask[0][1] = 0; | |
2783 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2784 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2785 | ||
2786 | if (!is_pse(vcpu)) { | |
2787 | context->rsvd_bits_mask[1][1] = 0; | |
2788 | break; | |
2789 | } | |
2790 | ||
82725b20 DE |
2791 | if (is_cpuid_PSE36()) |
2792 | /* 36bits PSE 4MB page */ | |
2793 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2794 | else | |
2795 | /* 32 bits PSE 4MB page */ | |
2796 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2797 | break; |
2798 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2799 | context->rsvd_bits_mask[0][2] = |
2800 | rsvd_bits(maxphyaddr, 63) | | |
2801 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2802 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2803 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2804 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2805 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2806 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2807 | rsvd_bits(maxphyaddr, 62) | | |
2808 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2809 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2810 | break; |
2811 | case PT64_ROOT_LEVEL: | |
2812 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2813 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2814 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2815 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2816 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2817 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2818 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2819 | rsvd_bits(maxphyaddr, 51); | |
2820 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2821 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2822 | rsvd_bits(maxphyaddr, 51) | | |
2823 | rsvd_bits(13, 29); | |
82725b20 | 2824 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2825 | rsvd_bits(maxphyaddr, 51) | |
2826 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2827 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2828 | break; |
2829 | } | |
2830 | } | |
2831 | ||
52fde8df JR |
2832 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
2833 | struct kvm_mmu *context, | |
2834 | int level) | |
6aa8b732 | 2835 | { |
2d48a985 JR |
2836 | context->nx = is_nx(vcpu); |
2837 | ||
52fde8df | 2838 | reset_rsvds_bits_mask(vcpu, context, level); |
6aa8b732 AK |
2839 | |
2840 | ASSERT(is_pae(vcpu)); | |
2841 | context->new_cr3 = paging_new_cr3; | |
2842 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2843 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2844 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2845 | context->sync_page = paging64_sync_page; |
a7052897 | 2846 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2847 | context->free = paging_free; |
17ac10ad AK |
2848 | context->root_level = level; |
2849 | context->shadow_root_level = level; | |
17c3ba9d | 2850 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2851 | context->direct_map = false; |
6aa8b732 AK |
2852 | return 0; |
2853 | } | |
2854 | ||
52fde8df JR |
2855 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
2856 | struct kvm_mmu *context) | |
17ac10ad | 2857 | { |
52fde8df | 2858 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
2859 | } |
2860 | ||
52fde8df JR |
2861 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
2862 | struct kvm_mmu *context) | |
6aa8b732 | 2863 | { |
2d48a985 JR |
2864 | context->nx = false; |
2865 | ||
52fde8df | 2866 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2867 | |
2868 | context->new_cr3 = paging_new_cr3; | |
2869 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2870 | context->gva_to_gpa = paging32_gva_to_gpa; |
2871 | context->free = paging_free; | |
c7addb90 | 2872 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2873 | context->sync_page = paging32_sync_page; |
a7052897 | 2874 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2875 | context->root_level = PT32_ROOT_LEVEL; |
2876 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2877 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2878 | context->direct_map = false; |
6aa8b732 AK |
2879 | return 0; |
2880 | } | |
2881 | ||
52fde8df JR |
2882 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
2883 | struct kvm_mmu *context) | |
6aa8b732 | 2884 | { |
52fde8df | 2885 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2886 | } |
2887 | ||
fb72d167 JR |
2888 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2889 | { | |
14dfe855 | 2890 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 JR |
2891 | |
2892 | context->new_cr3 = nonpaging_new_cr3; | |
2893 | context->page_fault = tdp_page_fault; | |
2894 | context->free = nonpaging_free; | |
2895 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2896 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2897 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2898 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 2899 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 2900 | context->direct_map = true; |
1c97f0a0 | 2901 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 2902 | context->get_cr3 = get_cr3; |
cb659db8 | 2903 | context->inject_page_fault = kvm_inject_page_fault; |
2d48a985 | 2904 | context->nx = is_nx(vcpu); |
fb72d167 JR |
2905 | |
2906 | if (!is_paging(vcpu)) { | |
2d48a985 | 2907 | context->nx = false; |
fb72d167 JR |
2908 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2909 | context->root_level = 0; | |
2910 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 2911 | context->nx = is_nx(vcpu); |
52fde8df | 2912 | reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL); |
fb72d167 JR |
2913 | context->gva_to_gpa = paging64_gva_to_gpa; |
2914 | context->root_level = PT64_ROOT_LEVEL; | |
2915 | } else if (is_pae(vcpu)) { | |
2d48a985 | 2916 | context->nx = is_nx(vcpu); |
52fde8df | 2917 | reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2918 | context->gva_to_gpa = paging64_gva_to_gpa; |
2919 | context->root_level = PT32E_ROOT_LEVEL; | |
2920 | } else { | |
2d48a985 | 2921 | context->nx = false; |
52fde8df | 2922 | reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL); |
fb72d167 JR |
2923 | context->gva_to_gpa = paging32_gva_to_gpa; |
2924 | context->root_level = PT32_ROOT_LEVEL; | |
2925 | } | |
2926 | ||
2927 | return 0; | |
2928 | } | |
2929 | ||
52fde8df | 2930 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 2931 | { |
a770f6f2 | 2932 | int r; |
6aa8b732 | 2933 | ASSERT(vcpu); |
ad312c7c | 2934 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2935 | |
2936 | if (!is_paging(vcpu)) | |
52fde8df | 2937 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 2938 | else if (is_long_mode(vcpu)) |
52fde8df | 2939 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 2940 | else if (is_pae(vcpu)) |
52fde8df | 2941 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 2942 | else |
52fde8df | 2943 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 2944 | |
5b7e0102 | 2945 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 2946 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
52fde8df JR |
2947 | |
2948 | return r; | |
2949 | } | |
2950 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
2951 | ||
2952 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
2953 | { | |
14dfe855 | 2954 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 2955 | |
14dfe855 JR |
2956 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
2957 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
2958 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
a770f6f2 AK |
2959 | |
2960 | return r; | |
6aa8b732 AK |
2961 | } |
2962 | ||
02f59dc9 JR |
2963 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
2964 | { | |
2965 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
2966 | ||
2967 | g_context->get_cr3 = get_cr3; | |
2968 | g_context->inject_page_fault = kvm_inject_page_fault; | |
2969 | ||
2970 | /* | |
2971 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
2972 | * translation of l2_gpa to l1_gpa addresses is done using the | |
2973 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
2974 | * functions between mmu and nested_mmu are swapped. | |
2975 | */ | |
2976 | if (!is_paging(vcpu)) { | |
2d48a985 | 2977 | g_context->nx = false; |
02f59dc9 JR |
2978 | g_context->root_level = 0; |
2979 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
2980 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 2981 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
2982 | reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL); |
2983 | g_context->root_level = PT64_ROOT_LEVEL; | |
2984 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
2985 | } else if (is_pae(vcpu)) { | |
2d48a985 | 2986 | g_context->nx = is_nx(vcpu); |
02f59dc9 JR |
2987 | reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL); |
2988 | g_context->root_level = PT32E_ROOT_LEVEL; | |
2989 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; | |
2990 | } else { | |
2d48a985 | 2991 | g_context->nx = false; |
02f59dc9 JR |
2992 | reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL); |
2993 | g_context->root_level = PT32_ROOT_LEVEL; | |
2994 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; | |
2995 | } | |
2996 | ||
2997 | return 0; | |
2998 | } | |
2999 | ||
fb72d167 JR |
3000 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3001 | { | |
35149e21 AL |
3002 | vcpu->arch.update_pte.pfn = bad_pfn; |
3003 | ||
02f59dc9 JR |
3004 | if (mmu_is_nested(vcpu)) |
3005 | return init_kvm_nested_mmu(vcpu); | |
3006 | else if (tdp_enabled) | |
fb72d167 JR |
3007 | return init_kvm_tdp_mmu(vcpu); |
3008 | else | |
3009 | return init_kvm_softmmu(vcpu); | |
3010 | } | |
3011 | ||
6aa8b732 AK |
3012 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3013 | { | |
3014 | ASSERT(vcpu); | |
62ad0755 SY |
3015 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3016 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3017 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3018 | } |
3019 | ||
3020 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3021 | { |
3022 | destroy_kvm_mmu(vcpu); | |
3023 | return init_kvm_mmu(vcpu); | |
3024 | } | |
8668a3c4 | 3025 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3026 | |
3027 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3028 | { |
714b93da AK |
3029 | int r; |
3030 | ||
e2dec939 | 3031 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3032 | if (r) |
3033 | goto out; | |
8986ecc0 | 3034 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3035 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3036 | mmu_sync_roots(vcpu); |
aaee2c94 | 3037 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3038 | if (r) |
3039 | goto out; | |
3662cb1c | 3040 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3041 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3042 | out: |
3043 | return r; | |
6aa8b732 | 3044 | } |
17c3ba9d AK |
3045 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3046 | ||
3047 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3048 | { | |
3049 | mmu_free_roots(vcpu); | |
3050 | } | |
4b16184c | 3051 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3052 | |
09072daf | 3053 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 3054 | struct kvm_mmu_page *sp, |
ac1b714e AK |
3055 | u64 *spte) |
3056 | { | |
3057 | u64 pte; | |
3058 | struct kvm_mmu_page *child; | |
3059 | ||
3060 | pte = *spte; | |
c7addb90 | 3061 | if (is_shadow_present_pte(pte)) { |
776e6633 | 3062 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 3063 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
3064 | else { |
3065 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 3066 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
3067 | } |
3068 | } | |
d555c333 | 3069 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
3070 | if (is_large_pte(pte)) |
3071 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
3072 | } |
3073 | ||
0028425f | 3074 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 3075 | struct kvm_mmu_page *sp, |
0028425f | 3076 | u64 *spte, |
489f1d65 | 3077 | const void *new) |
0028425f | 3078 | { |
30945387 | 3079 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3080 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3081 | return; | |
30945387 | 3082 | } |
0028425f | 3083 | |
4cee5764 | 3084 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 3085 | if (!sp->role.cr4_pae) |
489f1d65 | 3086 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 3087 | else |
489f1d65 | 3088 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
3089 | } |
3090 | ||
79539cec AK |
3091 | static bool need_remote_flush(u64 old, u64 new) |
3092 | { | |
3093 | if (!is_shadow_present_pte(old)) | |
3094 | return false; | |
3095 | if (!is_shadow_present_pte(new)) | |
3096 | return true; | |
3097 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3098 | return true; | |
3099 | old ^= PT64_NX_MASK; | |
3100 | new ^= PT64_NX_MASK; | |
3101 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3102 | } | |
3103 | ||
0671a8e7 XG |
3104 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3105 | bool remote_flush, bool local_flush) | |
79539cec | 3106 | { |
0671a8e7 XG |
3107 | if (zap_page) |
3108 | return; | |
3109 | ||
3110 | if (remote_flush) | |
79539cec | 3111 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3112 | else if (local_flush) |
79539cec AK |
3113 | kvm_mmu_flush_tlb(vcpu); |
3114 | } | |
3115 | ||
12b7d28f AK |
3116 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
3117 | { | |
ad312c7c | 3118 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 3119 | |
7b52345e | 3120 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
3121 | } |
3122 | ||
d7824fff | 3123 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 3124 | u64 gpte) |
d7824fff AK |
3125 | { |
3126 | gfn_t gfn; | |
35149e21 | 3127 | pfn_t pfn; |
d7824fff | 3128 | |
43a3795a | 3129 | if (!is_present_gpte(gpte)) |
d7824fff AK |
3130 | return; |
3131 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 3132 | |
e930bffe | 3133 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3134 | smp_rmb(); |
35149e21 | 3135 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 3136 | |
35149e21 AL |
3137 | if (is_error_pfn(pfn)) { |
3138 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
3139 | return; |
3140 | } | |
d7824fff | 3141 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 3142 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
3143 | } |
3144 | ||
1b7fcd32 AK |
3145 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
3146 | { | |
3147 | u64 *spte = vcpu->arch.last_pte_updated; | |
3148 | ||
3149 | if (spte | |
3150 | && vcpu->arch.last_pte_gfn == gfn | |
3151 | && shadow_accessed_mask | |
3152 | && !(*spte & shadow_accessed_mask) | |
3153 | && is_shadow_present_pte(*spte)) | |
3154 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
3155 | } | |
3156 | ||
09072daf | 3157 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
3158 | const u8 *new, int bytes, |
3159 | bool guest_initiated) | |
da4a00f0 | 3160 | { |
9b7a0325 | 3161 | gfn_t gfn = gpa >> PAGE_SHIFT; |
fa1de2bf | 3162 | union kvm_mmu_page_role mask = { .word = 0 }; |
4db35314 | 3163 | struct kvm_mmu_page *sp; |
f41d335a | 3164 | struct hlist_node *node; |
d98ba053 | 3165 | LIST_HEAD(invalid_list); |
489f1d65 | 3166 | u64 entry, gentry; |
9b7a0325 | 3167 | u64 *spte; |
9b7a0325 | 3168 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 3169 | unsigned pte_size; |
9b7a0325 | 3170 | unsigned page_offset; |
0e7bc4b9 | 3171 | unsigned misaligned; |
fce0657f | 3172 | unsigned quadrant; |
9b7a0325 | 3173 | int level; |
86a5ba02 | 3174 | int flooded = 0; |
ac1b714e | 3175 | int npte; |
489f1d65 | 3176 | int r; |
08e850c6 | 3177 | int invlpg_counter; |
0671a8e7 XG |
3178 | bool remote_flush, local_flush, zap_page; |
3179 | ||
3180 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 3181 | |
b8688d51 | 3182 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 3183 | |
08e850c6 | 3184 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
3185 | |
3186 | /* | |
3187 | * Assume that the pte write on a page table of the same type | |
3188 | * as the current vcpu paging mode. This is nearly always true | |
3189 | * (might be false while changing modes). Note it is verified later | |
3190 | * by update_pte(). | |
3191 | */ | |
08e850c6 | 3192 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 3193 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
3194 | if (is_pae(vcpu)) { |
3195 | gpa &= ~(gpa_t)7; | |
3196 | bytes = 8; | |
3197 | } | |
3198 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
3199 | if (r) |
3200 | gentry = 0; | |
08e850c6 AK |
3201 | new = (const u8 *)&gentry; |
3202 | } | |
3203 | ||
3204 | switch (bytes) { | |
3205 | case 4: | |
3206 | gentry = *(const u32 *)new; | |
3207 | break; | |
3208 | case 8: | |
3209 | gentry = *(const u64 *)new; | |
3210 | break; | |
3211 | default: | |
3212 | gentry = 0; | |
3213 | break; | |
72016f3a AK |
3214 | } |
3215 | ||
3216 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 3217 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
3218 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
3219 | gentry = 0; | |
1b7fcd32 | 3220 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 3221 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 3222 | ++vcpu->kvm->stat.mmu_pte_write; |
8b1fe17c | 3223 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
ad218f85 MT |
3224 | if (guest_initiated) { |
3225 | if (gfn == vcpu->arch.last_pt_write_gfn | |
3226 | && !last_updated_pte_accessed(vcpu)) { | |
3227 | ++vcpu->arch.last_pt_write_count; | |
3228 | if (vcpu->arch.last_pt_write_count >= 3) | |
3229 | flooded = 1; | |
3230 | } else { | |
3231 | vcpu->arch.last_pt_write_gfn = gfn; | |
3232 | vcpu->arch.last_pt_write_count = 1; | |
3233 | vcpu->arch.last_pte_updated = NULL; | |
3234 | } | |
86a5ba02 | 3235 | } |
3246af0e | 3236 | |
fa1de2bf | 3237 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3238 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 3239 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 3240 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 3241 | misaligned |= bytes < 4; |
86a5ba02 | 3242 | if (misaligned || flooded) { |
0e7bc4b9 AK |
3243 | /* |
3244 | * Misaligned accesses are too much trouble to fix | |
3245 | * up; also, they usually indicate a page is not used | |
3246 | * as a page table. | |
86a5ba02 AK |
3247 | * |
3248 | * If we're seeing too many writes to a page, | |
3249 | * it may no longer be a page table, or we may be | |
3250 | * forking, in which case it is better to unmap the | |
3251 | * page. | |
0e7bc4b9 AK |
3252 | */ |
3253 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 3254 | gpa, bytes, sp->role.word); |
0671a8e7 | 3255 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3256 | &invalid_list); |
4cee5764 | 3257 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3258 | continue; |
3259 | } | |
9b7a0325 | 3260 | page_offset = offset; |
4db35314 | 3261 | level = sp->role.level; |
ac1b714e | 3262 | npte = 1; |
5b7e0102 | 3263 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
3264 | page_offset <<= 1; /* 32->64 */ |
3265 | /* | |
3266 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3267 | * only 2MB. So we need to double the offset again | |
3268 | * and zap two pdes instead of one. | |
3269 | */ | |
3270 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 3271 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
3272 | page_offset <<= 1; |
3273 | npte = 2; | |
3274 | } | |
fce0657f | 3275 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 3276 | page_offset &= ~PAGE_MASK; |
4db35314 | 3277 | if (quadrant != sp->role.quadrant) |
fce0657f | 3278 | continue; |
9b7a0325 | 3279 | } |
0671a8e7 | 3280 | local_flush = true; |
4db35314 | 3281 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 3282 | while (npte--) { |
79539cec | 3283 | entry = *spte; |
4db35314 | 3284 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
fa1de2bf XG |
3285 | if (gentry && |
3286 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
3287 | & mask.word)) | |
72016f3a | 3288 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
3289 | if (!remote_flush && need_remote_flush(entry, *spte)) |
3290 | remote_flush = true; | |
ac1b714e | 3291 | ++spte; |
9b7a0325 | 3292 | } |
9b7a0325 | 3293 | } |
0671a8e7 | 3294 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 3295 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
8b1fe17c | 3296 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 3297 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
3298 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
3299 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
3300 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 3301 | } |
da4a00f0 AK |
3302 | } |
3303 | ||
a436036b AK |
3304 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
3305 | { | |
10589a46 MT |
3306 | gpa_t gpa; |
3307 | int r; | |
a436036b | 3308 | |
c5a78f2b | 3309 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
3310 | return 0; |
3311 | ||
1871c602 | 3312 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 3313 | |
aaee2c94 | 3314 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 3315 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 3316 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 3317 | return r; |
a436036b | 3318 | } |
577bdc49 | 3319 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 3320 | |
22d95b12 | 3321 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 3322 | { |
d98ba053 | 3323 | LIST_HEAD(invalid_list); |
103ad25a | 3324 | |
e0df7b9f | 3325 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 3326 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 3327 | struct kvm_mmu_page *sp; |
ebeace86 | 3328 | |
f05e70ac | 3329 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 3330 | struct kvm_mmu_page, link); |
e0df7b9f | 3331 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
80b63faf | 3332 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4cee5764 | 3333 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 AK |
3334 | } |
3335 | } | |
ebeace86 | 3336 | |
3067714c AK |
3337 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
3338 | { | |
3339 | int r; | |
3340 | enum emulation_result er; | |
3341 | ||
56028d08 | 3342 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
3343 | if (r < 0) |
3344 | goto out; | |
3345 | ||
3346 | if (!r) { | |
3347 | r = 1; | |
3348 | goto out; | |
3349 | } | |
3350 | ||
b733bfb5 AK |
3351 | r = mmu_topup_memory_caches(vcpu); |
3352 | if (r) | |
3353 | goto out; | |
3354 | ||
851ba692 | 3355 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
3356 | |
3357 | switch (er) { | |
3358 | case EMULATE_DONE: | |
3359 | return 1; | |
3360 | case EMULATE_DO_MMIO: | |
3361 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 3362 | /* fall through */ |
3067714c | 3363 | case EMULATE_FAIL: |
3f5d18a9 | 3364 | return 0; |
3067714c AK |
3365 | default: |
3366 | BUG(); | |
3367 | } | |
3368 | out: | |
3067714c AK |
3369 | return r; |
3370 | } | |
3371 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
3372 | ||
a7052897 MT |
3373 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
3374 | { | |
a7052897 | 3375 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
3376 | kvm_mmu_flush_tlb(vcpu); |
3377 | ++vcpu->stat.invlpg; | |
3378 | } | |
3379 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
3380 | ||
18552672 JR |
3381 | void kvm_enable_tdp(void) |
3382 | { | |
3383 | tdp_enabled = true; | |
3384 | } | |
3385 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
3386 | ||
5f4cb662 JR |
3387 | void kvm_disable_tdp(void) |
3388 | { | |
3389 | tdp_enabled = false; | |
3390 | } | |
3391 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
3392 | ||
6aa8b732 AK |
3393 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
3394 | { | |
ad312c7c | 3395 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3396 | if (vcpu->arch.mmu.lm_root != NULL) |
3397 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
3398 | } |
3399 | ||
3400 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
3401 | { | |
17ac10ad | 3402 | struct page *page; |
6aa8b732 AK |
3403 | int i; |
3404 | ||
3405 | ASSERT(vcpu); | |
3406 | ||
17ac10ad AK |
3407 | /* |
3408 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
3409 | * Therefore we need to allocate shadow page tables in the first | |
3410 | * 4GB of memory, which happens to fit the DMA32 zone. | |
3411 | */ | |
3412 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
3413 | if (!page) | |
d7fa6ab2 WY |
3414 | return -ENOMEM; |
3415 | ||
ad312c7c | 3416 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 3417 | for (i = 0; i < 4; ++i) |
ad312c7c | 3418 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3419 | |
6aa8b732 | 3420 | return 0; |
6aa8b732 AK |
3421 | } |
3422 | ||
8018c27b | 3423 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 3424 | { |
6aa8b732 | 3425 | ASSERT(vcpu); |
ad312c7c | 3426 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3427 | |
8018c27b IM |
3428 | return alloc_mmu_pages(vcpu); |
3429 | } | |
6aa8b732 | 3430 | |
8018c27b IM |
3431 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3432 | { | |
3433 | ASSERT(vcpu); | |
ad312c7c | 3434 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3435 | |
8018c27b | 3436 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3437 | } |
3438 | ||
90cb0529 | 3439 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3440 | { |
4db35314 | 3441 | struct kvm_mmu_page *sp; |
6aa8b732 | 3442 | |
f05e70ac | 3443 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3444 | int i; |
3445 | u64 *pt; | |
3446 | ||
291f26bc | 3447 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3448 | continue; |
3449 | ||
4db35314 | 3450 | pt = sp->spt; |
6aa8b732 AK |
3451 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
3452 | /* avoid RMW */ | |
01c168ac | 3453 | if (is_writable_pte(pt[i])) |
700e1b12 | 3454 | update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK); |
6aa8b732 | 3455 | } |
171d595d | 3456 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3457 | } |
37a7d8b0 | 3458 | |
90cb0529 | 3459 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3460 | { |
4db35314 | 3461 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3462 | LIST_HEAD(invalid_list); |
e0fa826f | 3463 | |
aaee2c94 | 3464 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3465 | restart: |
f05e70ac | 3466 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3467 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3468 | goto restart; |
3469 | ||
d98ba053 | 3470 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3471 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3472 | } |
3473 | ||
d98ba053 XG |
3474 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3475 | struct list_head *invalid_list) | |
3ee16c81 IE |
3476 | { |
3477 | struct kvm_mmu_page *page; | |
3478 | ||
3479 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3480 | struct kvm_mmu_page, link); | |
d98ba053 | 3481 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3482 | } |
3483 | ||
7f8275d0 | 3484 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3485 | { |
3486 | struct kvm *kvm; | |
3487 | struct kvm *kvm_freed = NULL; | |
45221ab6 DH |
3488 | |
3489 | if (nr_to_scan == 0) | |
3490 | goto out; | |
3ee16c81 IE |
3491 | |
3492 | spin_lock(&kvm_lock); | |
3493 | ||
3494 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
45221ab6 | 3495 | int idx, freed_pages; |
d98ba053 | 3496 | LIST_HEAD(invalid_list); |
3ee16c81 | 3497 | |
f656ce01 | 3498 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 3499 | spin_lock(&kvm->mmu_lock); |
45221ab6 DH |
3500 | if (!kvm_freed && nr_to_scan > 0 && |
3501 | kvm->arch.n_used_mmu_pages > 0) { | |
d98ba053 XG |
3502 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3503 | &invalid_list); | |
3ee16c81 IE |
3504 | kvm_freed = kvm; |
3505 | } | |
3506 | nr_to_scan--; | |
3507 | ||
d98ba053 | 3508 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3509 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3510 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3511 | } |
3512 | if (kvm_freed) | |
3513 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3514 | ||
3515 | spin_unlock(&kvm_lock); | |
3516 | ||
45221ab6 DH |
3517 | out: |
3518 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
3519 | } |
3520 | ||
3521 | static struct shrinker mmu_shrinker = { | |
3522 | .shrink = mmu_shrink, | |
3523 | .seeks = DEFAULT_SEEKS * 10, | |
3524 | }; | |
3525 | ||
2ddfd20e | 3526 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3527 | { |
3528 | if (pte_chain_cache) | |
3529 | kmem_cache_destroy(pte_chain_cache); | |
3530 | if (rmap_desc_cache) | |
3531 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3532 | if (mmu_page_header_cache) |
3533 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3534 | } |
3535 | ||
3ee16c81 IE |
3536 | void kvm_mmu_module_exit(void) |
3537 | { | |
3538 | mmu_destroy_caches(); | |
45bf21a8 | 3539 | percpu_counter_destroy(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
3540 | unregister_shrinker(&mmu_shrinker); |
3541 | } | |
3542 | ||
b5a33a75 AK |
3543 | int kvm_mmu_module_init(void) |
3544 | { | |
3545 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3546 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3547 | 0, 0, NULL); |
b5a33a75 AK |
3548 | if (!pte_chain_cache) |
3549 | goto nomem; | |
3550 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3551 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3552 | 0, 0, NULL); |
b5a33a75 AK |
3553 | if (!rmap_desc_cache) |
3554 | goto nomem; | |
3555 | ||
d3d25b04 AK |
3556 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3557 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3558 | 0, 0, NULL); |
d3d25b04 AK |
3559 | if (!mmu_page_header_cache) |
3560 | goto nomem; | |
3561 | ||
45bf21a8 WY |
3562 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
3563 | goto nomem; | |
3564 | ||
3ee16c81 IE |
3565 | register_shrinker(&mmu_shrinker); |
3566 | ||
b5a33a75 AK |
3567 | return 0; |
3568 | ||
3569 | nomem: | |
3ee16c81 | 3570 | mmu_destroy_caches(); |
b5a33a75 AK |
3571 | return -ENOMEM; |
3572 | } | |
3573 | ||
3ad82a7e ZX |
3574 | /* |
3575 | * Caculate mmu pages needed for kvm. | |
3576 | */ | |
3577 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3578 | { | |
3579 | int i; | |
3580 | unsigned int nr_mmu_pages; | |
3581 | unsigned int nr_pages = 0; | |
bc6678a3 | 3582 | struct kvm_memslots *slots; |
3ad82a7e | 3583 | |
90d83dc3 LJ |
3584 | slots = kvm_memslots(kvm); |
3585 | ||
bc6678a3 MT |
3586 | for (i = 0; i < slots->nmemslots; i++) |
3587 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3588 | |
3589 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3590 | nr_mmu_pages = max(nr_mmu_pages, | |
3591 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3592 | ||
3593 | return nr_mmu_pages; | |
3594 | } | |
3595 | ||
2f333bcb MT |
3596 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3597 | unsigned len) | |
3598 | { | |
3599 | if (len > buffer->len) | |
3600 | return NULL; | |
3601 | return buffer->ptr; | |
3602 | } | |
3603 | ||
3604 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3605 | unsigned len) | |
3606 | { | |
3607 | void *ret; | |
3608 | ||
3609 | ret = pv_mmu_peek_buffer(buffer, len); | |
3610 | if (!ret) | |
3611 | return ret; | |
3612 | buffer->ptr += len; | |
3613 | buffer->len -= len; | |
3614 | buffer->processed += len; | |
3615 | return ret; | |
3616 | } | |
3617 | ||
3618 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3619 | gpa_t addr, gpa_t value) | |
3620 | { | |
3621 | int bytes = 8; | |
3622 | int r; | |
3623 | ||
3624 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3625 | bytes = 4; | |
3626 | ||
3627 | r = mmu_topup_memory_caches(vcpu); | |
3628 | if (r) | |
3629 | return r; | |
3630 | ||
3200f405 | 3631 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3632 | return -EFAULT; |
3633 | ||
3634 | return 1; | |
3635 | } | |
3636 | ||
3637 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3638 | { | |
2390218b | 3639 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3640 | return 1; |
3641 | } | |
3642 | ||
3643 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3644 | { | |
3645 | spin_lock(&vcpu->kvm->mmu_lock); | |
3646 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3647 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3648 | return 1; | |
3649 | } | |
3650 | ||
3651 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3652 | struct kvm_pv_mmu_op_buffer *buffer) | |
3653 | { | |
3654 | struct kvm_mmu_op_header *header; | |
3655 | ||
3656 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3657 | if (!header) | |
3658 | return 0; | |
3659 | switch (header->op) { | |
3660 | case KVM_MMU_OP_WRITE_PTE: { | |
3661 | struct kvm_mmu_op_write_pte *wpte; | |
3662 | ||
3663 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3664 | if (!wpte) | |
3665 | return 0; | |
3666 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3667 | wpte->pte_val); | |
3668 | } | |
3669 | case KVM_MMU_OP_FLUSH_TLB: { | |
3670 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3671 | ||
3672 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3673 | if (!ftlb) | |
3674 | return 0; | |
3675 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3676 | } | |
3677 | case KVM_MMU_OP_RELEASE_PT: { | |
3678 | struct kvm_mmu_op_release_pt *rpt; | |
3679 | ||
3680 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3681 | if (!rpt) | |
3682 | return 0; | |
3683 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3684 | } | |
3685 | default: return 0; | |
3686 | } | |
3687 | } | |
3688 | ||
3689 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3690 | gpa_t addr, unsigned long *ret) | |
3691 | { | |
3692 | int r; | |
6ad18fba | 3693 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3694 | |
6ad18fba DH |
3695 | buffer->ptr = buffer->buf; |
3696 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3697 | buffer->processed = 0; | |
2f333bcb | 3698 | |
6ad18fba | 3699 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3700 | if (r) |
3701 | goto out; | |
3702 | ||
6ad18fba DH |
3703 | while (buffer->len) { |
3704 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3705 | if (r < 0) |
3706 | goto out; | |
3707 | if (r == 0) | |
3708 | break; | |
3709 | } | |
3710 | ||
3711 | r = 1; | |
3712 | out: | |
6ad18fba | 3713 | *ret = buffer->processed; |
2f333bcb MT |
3714 | return r; |
3715 | } | |
3716 | ||
94d8b056 MT |
3717 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3718 | { | |
3719 | struct kvm_shadow_walk_iterator iterator; | |
3720 | int nr_sptes = 0; | |
3721 | ||
3722 | spin_lock(&vcpu->kvm->mmu_lock); | |
3723 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3724 | sptes[iterator.level-1] = *iterator.sptep; | |
3725 | nr_sptes++; | |
3726 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3727 | break; | |
3728 | } | |
3729 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3730 | ||
3731 | return nr_sptes; | |
3732 | } | |
3733 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3734 | ||
8b1fe17c | 3735 | #ifdef CONFIG_KVM_MMU_AUDIT |
2f4f3372 | 3736 | #include "mmu_audit.c" |
c42fffe3 XG |
3737 | #else |
3738 | static void mmu_audit_disable(void) { } | |
37a7d8b0 | 3739 | #endif |
c42fffe3 XG |
3740 | |
3741 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
3742 | { | |
3743 | ASSERT(vcpu); | |
3744 | ||
3745 | destroy_kvm_mmu(vcpu); | |
3746 | free_mmu_pages(vcpu); | |
3747 | mmu_free_memory_caches(vcpu); | |
3748 | mmu_audit_disable(); | |
3749 | } |