Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
1d737c8a | 21 | #include "mmu.h" |
836a1b3c | 22 | #include "x86.h" |
6de4f3ad | 23 | #include "kvm_cache_regs.h" |
e495606d | 24 | |
edf88417 | 25 | #include <linux/kvm_host.h> |
6aa8b732 AK |
26 | #include <linux/types.h> |
27 | #include <linux/string.h> | |
6aa8b732 AK |
28 | #include <linux/mm.h> |
29 | #include <linux/highmem.h> | |
30 | #include <linux/module.h> | |
448353ca | 31 | #include <linux/swap.h> |
05da4558 | 32 | #include <linux/hugetlb.h> |
2f333bcb | 33 | #include <linux/compiler.h> |
bc6678a3 | 34 | #include <linux/srcu.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bf998156 | 36 | #include <linux/uaccess.h> |
6aa8b732 | 37 | |
e495606d AK |
38 | #include <asm/page.h> |
39 | #include <asm/cmpxchg.h> | |
4e542370 | 40 | #include <asm/io.h> |
13673a90 | 41 | #include <asm/vmx.h> |
6aa8b732 | 42 | |
18552672 JR |
43 | /* |
44 | * When setting this variable to true it enables Two-Dimensional-Paging | |
45 | * where the hardware walks 2 page tables: | |
46 | * 1. the guest-virtual to guest-physical | |
47 | * 2. while doing 1. it walks guest-physical to host-physical | |
48 | * If the hardware supports that we don't need to do shadow paging. | |
49 | */ | |
2f333bcb | 50 | bool tdp_enabled = false; |
18552672 | 51 | |
37a7d8b0 AK |
52 | #undef MMU_DEBUG |
53 | ||
54 | #undef AUDIT | |
55 | ||
56 | #ifdef AUDIT | |
57 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg); | |
58 | #else | |
59 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {} | |
60 | #endif | |
61 | ||
62 | #ifdef MMU_DEBUG | |
63 | ||
64 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
65 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
66 | ||
67 | #else | |
68 | ||
69 | #define pgprintk(x...) do { } while (0) | |
70 | #define rmap_printk(x...) do { } while (0) | |
71 | ||
72 | #endif | |
73 | ||
74 | #if defined(MMU_DEBUG) || defined(AUDIT) | |
6ada8cca AK |
75 | static int dbg = 0; |
76 | module_param(dbg, bool, 0644); | |
37a7d8b0 | 77 | #endif |
6aa8b732 | 78 | |
582801a9 MT |
79 | static int oos_shadow = 1; |
80 | module_param(oos_shadow, bool, 0644); | |
81 | ||
d6c69ee9 YD |
82 | #ifndef MMU_DEBUG |
83 | #define ASSERT(x) do { } while (0) | |
84 | #else | |
6aa8b732 AK |
85 | #define ASSERT(x) \ |
86 | if (!(x)) { \ | |
87 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
88 | __FILE__, __LINE__, #x); \ | |
89 | } | |
d6c69ee9 | 90 | #endif |
6aa8b732 | 91 | |
6aa8b732 AK |
92 | #define PT_FIRST_AVAIL_BITS_SHIFT 9 |
93 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 | |
94 | ||
6aa8b732 AK |
95 | #define PT64_LEVEL_BITS 9 |
96 | ||
97 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 98 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 AK |
99 | |
100 | #define PT64_LEVEL_MASK(level) \ | |
101 | (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level)) | |
102 | ||
103 | #define PT64_INDEX(address, level)\ | |
104 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
105 | ||
106 | ||
107 | #define PT32_LEVEL_BITS 10 | |
108 | ||
109 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 110 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 AK |
111 | |
112 | #define PT32_LEVEL_MASK(level) \ | |
113 | (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level)) | |
e04da980 JR |
114 | #define PT32_LVL_OFFSET_MASK(level) \ |
115 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
116 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
117 | |
118 | #define PT32_INDEX(address, level)\ | |
119 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
120 | ||
121 | ||
27aba766 | 122 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
123 | #define PT64_DIR_BASE_ADDR_MASK \ |
124 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
125 | #define PT64_LVL_ADDR_MASK(level) \ |
126 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
127 | * PT64_LEVEL_BITS))) - 1)) | |
128 | #define PT64_LVL_OFFSET_MASK(level) \ | |
129 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
130 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
131 | |
132 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
133 | #define PT32_DIR_BASE_ADDR_MASK \ | |
134 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
135 | #define PT32_LVL_ADDR_MASK(level) \ |
136 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
137 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 138 | |
79539cec AK |
139 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
140 | | PT64_NX_MASK) | |
6aa8b732 | 141 | |
cd4a4e53 AK |
142 | #define RMAP_EXT 4 |
143 | ||
fe135d2c AK |
144 | #define ACC_EXEC_MASK 1 |
145 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
146 | #define ACC_USER_MASK PT_USER_MASK | |
147 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
148 | ||
90bb6fc5 AK |
149 | #include <trace/events/kvm.h> |
150 | ||
07420171 AK |
151 | #define CREATE_TRACE_POINTS |
152 | #include "mmutrace.h" | |
153 | ||
1403283a IE |
154 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
155 | ||
135f8c2b AK |
156 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
157 | ||
cd4a4e53 | 158 | struct kvm_rmap_desc { |
d555c333 | 159 | u64 *sptes[RMAP_EXT]; |
cd4a4e53 AK |
160 | struct kvm_rmap_desc *more; |
161 | }; | |
162 | ||
2d11123a AK |
163 | struct kvm_shadow_walk_iterator { |
164 | u64 addr; | |
165 | hpa_t shadow_addr; | |
166 | int level; | |
167 | u64 *sptep; | |
168 | unsigned index; | |
169 | }; | |
170 | ||
171 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
172 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
173 | shadow_walk_okay(&(_walker)); \ | |
174 | shadow_walk_next(&(_walker))) | |
175 | ||
1047df1f | 176 | typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte); |
ad8cfbe3 | 177 | |
b5a33a75 AK |
178 | static struct kmem_cache *pte_chain_cache; |
179 | static struct kmem_cache *rmap_desc_cache; | |
d3d25b04 | 180 | static struct kmem_cache *mmu_page_header_cache; |
b5a33a75 | 181 | |
c7addb90 AK |
182 | static u64 __read_mostly shadow_trap_nonpresent_pte; |
183 | static u64 __read_mostly shadow_notrap_nonpresent_pte; | |
7b52345e SY |
184 | static u64 __read_mostly shadow_base_present_pte; |
185 | static u64 __read_mostly shadow_nx_mask; | |
186 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
187 | static u64 __read_mostly shadow_user_mask; | |
188 | static u64 __read_mostly shadow_accessed_mask; | |
189 | static u64 __read_mostly shadow_dirty_mask; | |
c7addb90 | 190 | |
82725b20 DE |
191 | static inline u64 rsvd_bits(int s, int e) |
192 | { | |
193 | return ((1ULL << (e - s + 1)) - 1) << s; | |
194 | } | |
195 | ||
c7addb90 AK |
196 | void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte) |
197 | { | |
198 | shadow_trap_nonpresent_pte = trap_pte; | |
199 | shadow_notrap_nonpresent_pte = notrap_pte; | |
200 | } | |
201 | EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes); | |
202 | ||
7b52345e SY |
203 | void kvm_mmu_set_base_ptes(u64 base_pte) |
204 | { | |
205 | shadow_base_present_pte = base_pte; | |
206 | } | |
207 | EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes); | |
208 | ||
209 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, | |
4b12f0de | 210 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
211 | { |
212 | shadow_user_mask = user_mask; | |
213 | shadow_accessed_mask = accessed_mask; | |
214 | shadow_dirty_mask = dirty_mask; | |
215 | shadow_nx_mask = nx_mask; | |
216 | shadow_x_mask = x_mask; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
219 | ||
3dbe1415 | 220 | static bool is_write_protection(struct kvm_vcpu *vcpu) |
6aa8b732 | 221 | { |
4d4ec087 | 222 | return kvm_read_cr0_bits(vcpu, X86_CR0_WP); |
6aa8b732 AK |
223 | } |
224 | ||
225 | static int is_cpuid_PSE36(void) | |
226 | { | |
227 | return 1; | |
228 | } | |
229 | ||
73b1087e AK |
230 | static int is_nx(struct kvm_vcpu *vcpu) |
231 | { | |
f6801dff | 232 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
233 | } |
234 | ||
c7addb90 AK |
235 | static int is_shadow_present_pte(u64 pte) |
236 | { | |
c7addb90 AK |
237 | return pte != shadow_trap_nonpresent_pte |
238 | && pte != shadow_notrap_nonpresent_pte; | |
239 | } | |
240 | ||
05da4558 MT |
241 | static int is_large_pte(u64 pte) |
242 | { | |
243 | return pte & PT_PAGE_SIZE_MASK; | |
244 | } | |
245 | ||
8dae4445 | 246 | static int is_writable_pte(unsigned long pte) |
6aa8b732 AK |
247 | { |
248 | return pte & PT_WRITABLE_MASK; | |
249 | } | |
250 | ||
43a3795a | 251 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 252 | { |
439e218a | 253 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
254 | } |
255 | ||
43a3795a | 256 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 257 | { |
4b1a80fa | 258 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
259 | } |
260 | ||
776e6633 MT |
261 | static int is_last_spte(u64 pte, int level) |
262 | { | |
263 | if (level == PT_PAGE_TABLE_LEVEL) | |
264 | return 1; | |
852e3c19 | 265 | if (is_large_pte(pte)) |
776e6633 MT |
266 | return 1; |
267 | return 0; | |
268 | } | |
269 | ||
35149e21 | 270 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 271 | { |
35149e21 | 272 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
273 | } |
274 | ||
da928521 AK |
275 | static gfn_t pse36_gfn_delta(u32 gpte) |
276 | { | |
277 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
278 | ||
279 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
280 | } | |
281 | ||
d555c333 | 282 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 AK |
283 | { |
284 | #ifdef CONFIG_X86_64 | |
285 | set_64bit((unsigned long *)sptep, spte); | |
286 | #else | |
287 | set_64bit((unsigned long long *)sptep, spte); | |
288 | #endif | |
289 | } | |
290 | ||
a9221dd5 AK |
291 | static u64 __xchg_spte(u64 *sptep, u64 new_spte) |
292 | { | |
293 | #ifdef CONFIG_X86_64 | |
294 | return xchg(sptep, new_spte); | |
295 | #else | |
296 | u64 old_spte; | |
297 | ||
298 | do { | |
299 | old_spte = *sptep; | |
300 | } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte); | |
301 | ||
302 | return old_spte; | |
303 | #endif | |
304 | } | |
305 | ||
b79b93f9 AK |
306 | static void update_spte(u64 *sptep, u64 new_spte) |
307 | { | |
308 | u64 old_spte; | |
309 | ||
310 | if (!shadow_accessed_mask || (new_spte & shadow_accessed_mask)) { | |
311 | __set_spte(sptep, new_spte); | |
312 | } else { | |
313 | old_spte = __xchg_spte(sptep, new_spte); | |
314 | if (old_spte & shadow_accessed_mask) | |
315 | mark_page_accessed(pfn_to_page(spte_to_pfn(old_spte))); | |
316 | } | |
317 | } | |
318 | ||
e2dec939 | 319 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 320 | struct kmem_cache *base_cache, int min) |
714b93da AK |
321 | { |
322 | void *obj; | |
323 | ||
324 | if (cache->nobjs >= min) | |
e2dec939 | 325 | return 0; |
714b93da | 326 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 327 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 328 | if (!obj) |
e2dec939 | 329 | return -ENOMEM; |
714b93da AK |
330 | cache->objects[cache->nobjs++] = obj; |
331 | } | |
e2dec939 | 332 | return 0; |
714b93da AK |
333 | } |
334 | ||
e8ad9a70 XG |
335 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
336 | struct kmem_cache *cache) | |
714b93da AK |
337 | { |
338 | while (mc->nobjs) | |
e8ad9a70 | 339 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
340 | } |
341 | ||
c1158e63 | 342 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 343 | int min) |
c1158e63 AK |
344 | { |
345 | struct page *page; | |
346 | ||
347 | if (cache->nobjs >= min) | |
348 | return 0; | |
349 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
2e3e5882 | 350 | page = alloc_page(GFP_KERNEL); |
c1158e63 AK |
351 | if (!page) |
352 | return -ENOMEM; | |
c1158e63 AK |
353 | cache->objects[cache->nobjs++] = page_address(page); |
354 | } | |
355 | return 0; | |
356 | } | |
357 | ||
358 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
359 | { | |
360 | while (mc->nobjs) | |
c4d198d5 | 361 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
362 | } |
363 | ||
2e3e5882 | 364 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 365 | { |
e2dec939 AK |
366 | int r; |
367 | ||
ad312c7c | 368 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache, |
2e3e5882 | 369 | pte_chain_cache, 4); |
e2dec939 AK |
370 | if (r) |
371 | goto out; | |
ad312c7c | 372 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, |
c41ef344 | 373 | rmap_desc_cache, 4); |
d3d25b04 AK |
374 | if (r) |
375 | goto out; | |
ad312c7c | 376 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
377 | if (r) |
378 | goto out; | |
ad312c7c | 379 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 380 | mmu_page_header_cache, 4); |
e2dec939 AK |
381 | out: |
382 | return r; | |
714b93da AK |
383 | } |
384 | ||
385 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
386 | { | |
e8ad9a70 XG |
387 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache); |
388 | mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache); | |
ad312c7c | 389 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
390 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
391 | mmu_page_header_cache); | |
714b93da AK |
392 | } |
393 | ||
394 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc, | |
395 | size_t size) | |
396 | { | |
397 | void *p; | |
398 | ||
399 | BUG_ON(!mc->nobjs); | |
400 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
401 | return p; |
402 | } | |
403 | ||
714b93da AK |
404 | static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu) |
405 | { | |
ad312c7c | 406 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache, |
714b93da AK |
407 | sizeof(struct kvm_pte_chain)); |
408 | } | |
409 | ||
90cb0529 | 410 | static void mmu_free_pte_chain(struct kvm_pte_chain *pc) |
714b93da | 411 | { |
e8ad9a70 | 412 | kmem_cache_free(pte_chain_cache, pc); |
714b93da AK |
413 | } |
414 | ||
415 | static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu) | |
416 | { | |
ad312c7c | 417 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache, |
714b93da AK |
418 | sizeof(struct kvm_rmap_desc)); |
419 | } | |
420 | ||
90cb0529 | 421 | static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd) |
714b93da | 422 | { |
e8ad9a70 | 423 | kmem_cache_free(rmap_desc_cache, rd); |
714b93da AK |
424 | } |
425 | ||
2032a93d LJ |
426 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
427 | { | |
428 | if (!sp->role.direct) | |
429 | return sp->gfns[index]; | |
430 | ||
431 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
432 | } | |
433 | ||
434 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
435 | { | |
436 | if (sp->role.direct) | |
437 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
438 | else | |
439 | sp->gfns[index] = gfn; | |
440 | } | |
441 | ||
05da4558 MT |
442 | /* |
443 | * Return the pointer to the largepage write count for a given | |
444 | * gfn, handling slots that are not large page aligned. | |
445 | */ | |
d25797b2 JR |
446 | static int *slot_largepage_idx(gfn_t gfn, |
447 | struct kvm_memory_slot *slot, | |
448 | int level) | |
05da4558 MT |
449 | { |
450 | unsigned long idx; | |
451 | ||
82855413 JR |
452 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
453 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
d25797b2 | 454 | return &slot->lpage_info[level - 2][idx].write_count; |
05da4558 MT |
455 | } |
456 | ||
457 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
458 | { | |
d25797b2 | 459 | struct kvm_memory_slot *slot; |
05da4558 | 460 | int *write_count; |
d25797b2 | 461 | int i; |
05da4558 | 462 | |
a1f4d395 | 463 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
464 | for (i = PT_DIRECTORY_LEVEL; |
465 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
466 | write_count = slot_largepage_idx(gfn, slot, i); | |
467 | *write_count += 1; | |
468 | } | |
05da4558 MT |
469 | } |
470 | ||
471 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
472 | { | |
d25797b2 | 473 | struct kvm_memory_slot *slot; |
05da4558 | 474 | int *write_count; |
d25797b2 | 475 | int i; |
05da4558 | 476 | |
a1f4d395 | 477 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
478 | for (i = PT_DIRECTORY_LEVEL; |
479 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d25797b2 JR |
480 | write_count = slot_largepage_idx(gfn, slot, i); |
481 | *write_count -= 1; | |
482 | WARN_ON(*write_count < 0); | |
483 | } | |
05da4558 MT |
484 | } |
485 | ||
d25797b2 JR |
486 | static int has_wrprotected_page(struct kvm *kvm, |
487 | gfn_t gfn, | |
488 | int level) | |
05da4558 | 489 | { |
2843099f | 490 | struct kvm_memory_slot *slot; |
05da4558 MT |
491 | int *largepage_idx; |
492 | ||
a1f4d395 | 493 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 494 | if (slot) { |
d25797b2 | 495 | largepage_idx = slot_largepage_idx(gfn, slot, level); |
05da4558 MT |
496 | return *largepage_idx; |
497 | } | |
498 | ||
499 | return 1; | |
500 | } | |
501 | ||
d25797b2 | 502 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 503 | { |
8f0b1ab6 | 504 | unsigned long page_size; |
d25797b2 | 505 | int i, ret = 0; |
05da4558 | 506 | |
8f0b1ab6 | 507 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 508 | |
d25797b2 JR |
509 | for (i = PT_PAGE_TABLE_LEVEL; |
510 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
511 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
512 | ret = i; | |
513 | else | |
514 | break; | |
515 | } | |
516 | ||
4c2155ce | 517 | return ret; |
05da4558 MT |
518 | } |
519 | ||
d25797b2 | 520 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) |
05da4558 MT |
521 | { |
522 | struct kvm_memory_slot *slot; | |
878403b7 | 523 | int host_level, level, max_level; |
05da4558 MT |
524 | |
525 | slot = gfn_to_memslot(vcpu->kvm, large_gfn); | |
526 | if (slot && slot->dirty_bitmap) | |
d25797b2 | 527 | return PT_PAGE_TABLE_LEVEL; |
05da4558 | 528 | |
d25797b2 JR |
529 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
530 | ||
531 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
532 | return host_level; | |
533 | ||
878403b7 SY |
534 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
535 | kvm_x86_ops->get_lpage_level() : host_level; | |
536 | ||
537 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
538 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
539 | break; | |
d25797b2 JR |
540 | |
541 | return level - 1; | |
05da4558 MT |
542 | } |
543 | ||
290fc38d IE |
544 | /* |
545 | * Take gfn and return the reverse mapping to it. | |
290fc38d IE |
546 | */ |
547 | ||
44ad9944 | 548 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) |
290fc38d IE |
549 | { |
550 | struct kvm_memory_slot *slot; | |
05da4558 | 551 | unsigned long idx; |
290fc38d IE |
552 | |
553 | slot = gfn_to_memslot(kvm, gfn); | |
44ad9944 | 554 | if (likely(level == PT_PAGE_TABLE_LEVEL)) |
05da4558 MT |
555 | return &slot->rmap[gfn - slot->base_gfn]; |
556 | ||
82855413 JR |
557 | idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - |
558 | (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
05da4558 | 559 | |
44ad9944 | 560 | return &slot->lpage_info[level - 2][idx].rmap_pde; |
290fc38d IE |
561 | } |
562 | ||
cd4a4e53 AK |
563 | /* |
564 | * Reverse mapping data structures: | |
565 | * | |
290fc38d IE |
566 | * If rmapp bit zero is zero, then rmapp point to the shadw page table entry |
567 | * that points to page_address(page). | |
cd4a4e53 | 568 | * |
290fc38d IE |
569 | * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc |
570 | * containing more mappings. | |
53a27b39 MT |
571 | * |
572 | * Returns the number of rmap entries before the spte was added or zero if | |
573 | * the spte was not added. | |
574 | * | |
cd4a4e53 | 575 | */ |
44ad9944 | 576 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
cd4a4e53 | 577 | { |
4db35314 | 578 | struct kvm_mmu_page *sp; |
cd4a4e53 | 579 | struct kvm_rmap_desc *desc; |
290fc38d | 580 | unsigned long *rmapp; |
53a27b39 | 581 | int i, count = 0; |
cd4a4e53 | 582 | |
43a3795a | 583 | if (!is_rmap_spte(*spte)) |
53a27b39 | 584 | return count; |
4db35314 | 585 | sp = page_header(__pa(spte)); |
2032a93d | 586 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); |
44ad9944 | 587 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
290fc38d | 588 | if (!*rmapp) { |
cd4a4e53 | 589 | rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte); |
290fc38d IE |
590 | *rmapp = (unsigned long)spte; |
591 | } else if (!(*rmapp & 1)) { | |
cd4a4e53 | 592 | rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte); |
714b93da | 593 | desc = mmu_alloc_rmap_desc(vcpu); |
d555c333 AK |
594 | desc->sptes[0] = (u64 *)*rmapp; |
595 | desc->sptes[1] = spte; | |
290fc38d | 596 | *rmapp = (unsigned long)desc | 1; |
cd4a4e53 AK |
597 | } else { |
598 | rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte); | |
290fc38d | 599 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
d555c333 | 600 | while (desc->sptes[RMAP_EXT-1] && desc->more) { |
cd4a4e53 | 601 | desc = desc->more; |
53a27b39 MT |
602 | count += RMAP_EXT; |
603 | } | |
d555c333 | 604 | if (desc->sptes[RMAP_EXT-1]) { |
714b93da | 605 | desc->more = mmu_alloc_rmap_desc(vcpu); |
cd4a4e53 AK |
606 | desc = desc->more; |
607 | } | |
d555c333 | 608 | for (i = 0; desc->sptes[i]; ++i) |
cd4a4e53 | 609 | ; |
d555c333 | 610 | desc->sptes[i] = spte; |
cd4a4e53 | 611 | } |
53a27b39 | 612 | return count; |
cd4a4e53 AK |
613 | } |
614 | ||
290fc38d | 615 | static void rmap_desc_remove_entry(unsigned long *rmapp, |
cd4a4e53 AK |
616 | struct kvm_rmap_desc *desc, |
617 | int i, | |
618 | struct kvm_rmap_desc *prev_desc) | |
619 | { | |
620 | int j; | |
621 | ||
d555c333 | 622 | for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 623 | ; |
d555c333 AK |
624 | desc->sptes[i] = desc->sptes[j]; |
625 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
626 | if (j != 0) |
627 | return; | |
628 | if (!prev_desc && !desc->more) | |
d555c333 | 629 | *rmapp = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
630 | else |
631 | if (prev_desc) | |
632 | prev_desc->more = desc->more; | |
633 | else | |
290fc38d | 634 | *rmapp = (unsigned long)desc->more | 1; |
90cb0529 | 635 | mmu_free_rmap_desc(desc); |
cd4a4e53 AK |
636 | } |
637 | ||
290fc38d | 638 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
cd4a4e53 | 639 | { |
cd4a4e53 AK |
640 | struct kvm_rmap_desc *desc; |
641 | struct kvm_rmap_desc *prev_desc; | |
4db35314 | 642 | struct kvm_mmu_page *sp; |
2032a93d | 643 | gfn_t gfn; |
290fc38d | 644 | unsigned long *rmapp; |
cd4a4e53 AK |
645 | int i; |
646 | ||
4db35314 | 647 | sp = page_header(__pa(spte)); |
2032a93d LJ |
648 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); |
649 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
290fc38d | 650 | if (!*rmapp) { |
cd4a4e53 AK |
651 | printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte); |
652 | BUG(); | |
290fc38d | 653 | } else if (!(*rmapp & 1)) { |
cd4a4e53 | 654 | rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte); |
290fc38d | 655 | if ((u64 *)*rmapp != spte) { |
cd4a4e53 AK |
656 | printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n", |
657 | spte, *spte); | |
658 | BUG(); | |
659 | } | |
290fc38d | 660 | *rmapp = 0; |
cd4a4e53 AK |
661 | } else { |
662 | rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte); | |
290fc38d | 663 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
cd4a4e53 AK |
664 | prev_desc = NULL; |
665 | while (desc) { | |
d555c333 AK |
666 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) |
667 | if (desc->sptes[i] == spte) { | |
290fc38d | 668 | rmap_desc_remove_entry(rmapp, |
714b93da | 669 | desc, i, |
cd4a4e53 AK |
670 | prev_desc); |
671 | return; | |
672 | } | |
673 | prev_desc = desc; | |
674 | desc = desc->more; | |
675 | } | |
186a3e52 | 676 | pr_err("rmap_remove: %p %llx many->many\n", spte, *spte); |
cd4a4e53 AK |
677 | BUG(); |
678 | } | |
679 | } | |
680 | ||
be38d276 AK |
681 | static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte) |
682 | { | |
ce061867 | 683 | pfn_t pfn; |
a9221dd5 | 684 | u64 old_spte; |
ce061867 | 685 | |
a9221dd5 AK |
686 | old_spte = __xchg_spte(sptep, new_spte); |
687 | if (!is_rmap_spte(old_spte)) | |
ce061867 | 688 | return; |
a9221dd5 AK |
689 | pfn = spte_to_pfn(old_spte); |
690 | if (old_spte & shadow_accessed_mask) | |
ce061867 | 691 | kvm_set_pfn_accessed(pfn); |
a9221dd5 | 692 | if (is_writable_pte(old_spte)) |
ce061867 | 693 | kvm_set_pfn_dirty(pfn); |
be38d276 | 694 | rmap_remove(kvm, sptep); |
be38d276 AK |
695 | } |
696 | ||
98348e95 | 697 | static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte) |
374cbac0 | 698 | { |
374cbac0 | 699 | struct kvm_rmap_desc *desc; |
98348e95 IE |
700 | u64 *prev_spte; |
701 | int i; | |
702 | ||
703 | if (!*rmapp) | |
704 | return NULL; | |
705 | else if (!(*rmapp & 1)) { | |
706 | if (!spte) | |
707 | return (u64 *)*rmapp; | |
708 | return NULL; | |
709 | } | |
710 | desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul); | |
98348e95 IE |
711 | prev_spte = NULL; |
712 | while (desc) { | |
d555c333 | 713 | for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) { |
98348e95 | 714 | if (prev_spte == spte) |
d555c333 AK |
715 | return desc->sptes[i]; |
716 | prev_spte = desc->sptes[i]; | |
98348e95 IE |
717 | } |
718 | desc = desc->more; | |
719 | } | |
720 | return NULL; | |
721 | } | |
722 | ||
b1a36821 | 723 | static int rmap_write_protect(struct kvm *kvm, u64 gfn) |
98348e95 | 724 | { |
290fc38d | 725 | unsigned long *rmapp; |
374cbac0 | 726 | u64 *spte; |
44ad9944 | 727 | int i, write_protected = 0; |
374cbac0 | 728 | |
44ad9944 | 729 | rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL); |
374cbac0 | 730 | |
98348e95 IE |
731 | spte = rmap_next(kvm, rmapp, NULL); |
732 | while (spte) { | |
374cbac0 | 733 | BUG_ON(!spte); |
374cbac0 | 734 | BUG_ON(!(*spte & PT_PRESENT_MASK)); |
374cbac0 | 735 | rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte); |
8dae4445 | 736 | if (is_writable_pte(*spte)) { |
b79b93f9 | 737 | update_spte(spte, *spte & ~PT_WRITABLE_MASK); |
caa5b8a5 ED |
738 | write_protected = 1; |
739 | } | |
9647c14c | 740 | spte = rmap_next(kvm, rmapp, spte); |
374cbac0 | 741 | } |
855149aa | 742 | if (write_protected) { |
35149e21 | 743 | pfn_t pfn; |
855149aa IE |
744 | |
745 | spte = rmap_next(kvm, rmapp, NULL); | |
35149e21 AL |
746 | pfn = spte_to_pfn(*spte); |
747 | kvm_set_pfn_dirty(pfn); | |
855149aa IE |
748 | } |
749 | ||
05da4558 | 750 | /* check for huge page mappings */ |
44ad9944 JR |
751 | for (i = PT_DIRECTORY_LEVEL; |
752 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
753 | rmapp = gfn_to_rmap(kvm, gfn, i); | |
754 | spte = rmap_next(kvm, rmapp, NULL); | |
755 | while (spte) { | |
756 | BUG_ON(!spte); | |
757 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
758 | BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)); | |
759 | pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn); | |
8dae4445 | 760 | if (is_writable_pte(*spte)) { |
be38d276 AK |
761 | drop_spte(kvm, spte, |
762 | shadow_trap_nonpresent_pte); | |
44ad9944 | 763 | --kvm->stat.lpages; |
44ad9944 JR |
764 | spte = NULL; |
765 | write_protected = 1; | |
766 | } | |
767 | spte = rmap_next(kvm, rmapp, spte); | |
05da4558 | 768 | } |
05da4558 MT |
769 | } |
770 | ||
b1a36821 | 771 | return write_protected; |
374cbac0 AK |
772 | } |
773 | ||
8a8365c5 FD |
774 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
775 | unsigned long data) | |
e930bffe AA |
776 | { |
777 | u64 *spte; | |
778 | int need_tlb_flush = 0; | |
779 | ||
780 | while ((spte = rmap_next(kvm, rmapp, NULL))) { | |
781 | BUG_ON(!(*spte & PT_PRESENT_MASK)); | |
782 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte); | |
be38d276 | 783 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
e930bffe AA |
784 | need_tlb_flush = 1; |
785 | } | |
786 | return need_tlb_flush; | |
787 | } | |
788 | ||
8a8365c5 FD |
789 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
790 | unsigned long data) | |
3da0dd43 IE |
791 | { |
792 | int need_flush = 0; | |
b79b93f9 | 793 | u64 *spte, new_spte, old_spte; |
3da0dd43 IE |
794 | pte_t *ptep = (pte_t *)data; |
795 | pfn_t new_pfn; | |
796 | ||
797 | WARN_ON(pte_huge(*ptep)); | |
798 | new_pfn = pte_pfn(*ptep); | |
799 | spte = rmap_next(kvm, rmapp, NULL); | |
800 | while (spte) { | |
801 | BUG_ON(!is_shadow_present_pte(*spte)); | |
802 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte); | |
803 | need_flush = 1; | |
804 | if (pte_write(*ptep)) { | |
be38d276 | 805 | drop_spte(kvm, spte, shadow_trap_nonpresent_pte); |
3da0dd43 IE |
806 | spte = rmap_next(kvm, rmapp, NULL); |
807 | } else { | |
808 | new_spte = *spte &~ (PT64_BASE_ADDR_MASK); | |
809 | new_spte |= (u64)new_pfn << PAGE_SHIFT; | |
810 | ||
811 | new_spte &= ~PT_WRITABLE_MASK; | |
812 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 813 | new_spte &= ~shadow_accessed_mask; |
8dae4445 | 814 | if (is_writable_pte(*spte)) |
3da0dd43 | 815 | kvm_set_pfn_dirty(spte_to_pfn(*spte)); |
b79b93f9 AK |
816 | old_spte = __xchg_spte(spte, new_spte); |
817 | if (is_shadow_present_pte(old_spte) | |
818 | && (old_spte & shadow_accessed_mask)) | |
819 | mark_page_accessed(pfn_to_page(spte_to_pfn(old_spte))); | |
3da0dd43 IE |
820 | spte = rmap_next(kvm, rmapp, spte); |
821 | } | |
822 | } | |
823 | if (need_flush) | |
824 | kvm_flush_remote_tlbs(kvm); | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
8a8365c5 FD |
829 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
830 | unsigned long data, | |
3da0dd43 | 831 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, |
8a8365c5 | 832 | unsigned long data)) |
e930bffe | 833 | { |
852e3c19 | 834 | int i, j; |
90bb6fc5 | 835 | int ret; |
e930bffe | 836 | int retval = 0; |
bc6678a3 MT |
837 | struct kvm_memslots *slots; |
838 | ||
90d83dc3 | 839 | slots = kvm_memslots(kvm); |
e930bffe | 840 | |
46a26bf5 MT |
841 | for (i = 0; i < slots->nmemslots; i++) { |
842 | struct kvm_memory_slot *memslot = &slots->memslots[i]; | |
e930bffe AA |
843 | unsigned long start = memslot->userspace_addr; |
844 | unsigned long end; | |
845 | ||
e930bffe AA |
846 | end = start + (memslot->npages << PAGE_SHIFT); |
847 | if (hva >= start && hva < end) { | |
848 | gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT; | |
852e3c19 | 849 | |
90bb6fc5 | 850 | ret = handler(kvm, &memslot->rmap[gfn_offset], data); |
852e3c19 JR |
851 | |
852 | for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) { | |
853 | int idx = gfn_offset; | |
854 | idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j); | |
90bb6fc5 | 855 | ret |= handler(kvm, |
3da0dd43 IE |
856 | &memslot->lpage_info[j][idx].rmap_pde, |
857 | data); | |
852e3c19 | 858 | } |
90bb6fc5 AK |
859 | trace_kvm_age_page(hva, memslot, ret); |
860 | retval |= ret; | |
e930bffe AA |
861 | } |
862 | } | |
863 | ||
864 | return retval; | |
865 | } | |
866 | ||
867 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
868 | { | |
3da0dd43 IE |
869 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
870 | } | |
871 | ||
872 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) | |
873 | { | |
8a8365c5 | 874 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
875 | } |
876 | ||
8a8365c5 FD |
877 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
878 | unsigned long data) | |
e930bffe AA |
879 | { |
880 | u64 *spte; | |
881 | int young = 0; | |
882 | ||
6316e1c8 RR |
883 | /* |
884 | * Emulate the accessed bit for EPT, by checking if this page has | |
885 | * an EPT mapping, and clearing it if it does. On the next access, | |
886 | * a new EPT mapping will be established. | |
887 | * This has some overhead, but not as much as the cost of swapping | |
888 | * out actively used pages or breaking up actively used hugepages. | |
889 | */ | |
534e38b4 | 890 | if (!shadow_accessed_mask) |
6316e1c8 | 891 | return kvm_unmap_rmapp(kvm, rmapp, data); |
534e38b4 | 892 | |
e930bffe AA |
893 | spte = rmap_next(kvm, rmapp, NULL); |
894 | while (spte) { | |
895 | int _young; | |
896 | u64 _spte = *spte; | |
897 | BUG_ON(!(_spte & PT_PRESENT_MASK)); | |
898 | _young = _spte & PT_ACCESSED_MASK; | |
899 | if (_young) { | |
900 | young = 1; | |
901 | clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
902 | } | |
903 | spte = rmap_next(kvm, rmapp, spte); | |
904 | } | |
905 | return young; | |
906 | } | |
907 | ||
53a27b39 MT |
908 | #define RMAP_RECYCLE_THRESHOLD 1000 |
909 | ||
852e3c19 | 910 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
911 | { |
912 | unsigned long *rmapp; | |
852e3c19 JR |
913 | struct kvm_mmu_page *sp; |
914 | ||
915 | sp = page_header(__pa(spte)); | |
53a27b39 | 916 | |
852e3c19 | 917 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 918 | |
3da0dd43 | 919 | kvm_unmap_rmapp(vcpu->kvm, rmapp, 0); |
53a27b39 MT |
920 | kvm_flush_remote_tlbs(vcpu->kvm); |
921 | } | |
922 | ||
e930bffe AA |
923 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
924 | { | |
3da0dd43 | 925 | return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp); |
e930bffe AA |
926 | } |
927 | ||
d6c69ee9 | 928 | #ifdef MMU_DEBUG |
47ad8e68 | 929 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 930 | { |
139bdb2d AK |
931 | u64 *pos; |
932 | u64 *end; | |
933 | ||
47ad8e68 | 934 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 935 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 936 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 937 | pos, *pos); |
6aa8b732 | 938 | return 0; |
139bdb2d | 939 | } |
6aa8b732 AK |
940 | return 1; |
941 | } | |
d6c69ee9 | 942 | #endif |
6aa8b732 | 943 | |
4db35314 | 944 | static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
260746c0 | 945 | { |
4db35314 | 946 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 947 | hlist_del(&sp->hash_link); |
4db35314 AK |
948 | list_del(&sp->link); |
949 | __free_page(virt_to_page(sp->spt)); | |
2032a93d LJ |
950 | if (!sp->role.direct) |
951 | __free_page(virt_to_page(sp->gfns)); | |
e8ad9a70 | 952 | kmem_cache_free(mmu_page_header_cache, sp); |
f05e70ac | 953 | ++kvm->arch.n_free_mmu_pages; |
260746c0 AK |
954 | } |
955 | ||
cea0f0e7 AK |
956 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
957 | { | |
1ae0a13d | 958 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
959 | } |
960 | ||
25c0de2c | 961 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
2032a93d | 962 | u64 *parent_pte, int direct) |
6aa8b732 | 963 | { |
4db35314 | 964 | struct kvm_mmu_page *sp; |
6aa8b732 | 965 | |
ad312c7c ZX |
966 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp); |
967 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE); | |
2032a93d LJ |
968 | if (!direct) |
969 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, | |
970 | PAGE_SIZE); | |
4db35314 | 971 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
f05e70ac | 972 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
291f26bc | 973 | bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); |
4db35314 AK |
974 | sp->multimapped = 0; |
975 | sp->parent_pte = parent_pte; | |
f05e70ac | 976 | --vcpu->kvm->arch.n_free_mmu_pages; |
4db35314 | 977 | return sp; |
6aa8b732 AK |
978 | } |
979 | ||
714b93da | 980 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 981 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 AK |
982 | { |
983 | struct kvm_pte_chain *pte_chain; | |
984 | struct hlist_node *node; | |
985 | int i; | |
986 | ||
987 | if (!parent_pte) | |
988 | return; | |
4db35314 AK |
989 | if (!sp->multimapped) { |
990 | u64 *old = sp->parent_pte; | |
cea0f0e7 AK |
991 | |
992 | if (!old) { | |
4db35314 | 993 | sp->parent_pte = parent_pte; |
cea0f0e7 AK |
994 | return; |
995 | } | |
4db35314 | 996 | sp->multimapped = 1; |
714b93da | 997 | pte_chain = mmu_alloc_pte_chain(vcpu); |
4db35314 AK |
998 | INIT_HLIST_HEAD(&sp->parent_ptes); |
999 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); | |
cea0f0e7 AK |
1000 | pte_chain->parent_ptes[0] = old; |
1001 | } | |
4db35314 | 1002 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) { |
cea0f0e7 AK |
1003 | if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1]) |
1004 | continue; | |
1005 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) | |
1006 | if (!pte_chain->parent_ptes[i]) { | |
1007 | pte_chain->parent_ptes[i] = parent_pte; | |
1008 | return; | |
1009 | } | |
1010 | } | |
714b93da | 1011 | pte_chain = mmu_alloc_pte_chain(vcpu); |
cea0f0e7 | 1012 | BUG_ON(!pte_chain); |
4db35314 | 1013 | hlist_add_head(&pte_chain->link, &sp->parent_ptes); |
cea0f0e7 AK |
1014 | pte_chain->parent_ptes[0] = parent_pte; |
1015 | } | |
1016 | ||
4db35314 | 1017 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1018 | u64 *parent_pte) |
1019 | { | |
1020 | struct kvm_pte_chain *pte_chain; | |
1021 | struct hlist_node *node; | |
1022 | int i; | |
1023 | ||
4db35314 AK |
1024 | if (!sp->multimapped) { |
1025 | BUG_ON(sp->parent_pte != parent_pte); | |
1026 | sp->parent_pte = NULL; | |
cea0f0e7 AK |
1027 | return; |
1028 | } | |
4db35314 | 1029 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
cea0f0e7 AK |
1030 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { |
1031 | if (!pte_chain->parent_ptes[i]) | |
1032 | break; | |
1033 | if (pte_chain->parent_ptes[i] != parent_pte) | |
1034 | continue; | |
697fe2e2 AK |
1035 | while (i + 1 < NR_PTE_CHAIN_ENTRIES |
1036 | && pte_chain->parent_ptes[i + 1]) { | |
cea0f0e7 AK |
1037 | pte_chain->parent_ptes[i] |
1038 | = pte_chain->parent_ptes[i + 1]; | |
1039 | ++i; | |
1040 | } | |
1041 | pte_chain->parent_ptes[i] = NULL; | |
697fe2e2 AK |
1042 | if (i == 0) { |
1043 | hlist_del(&pte_chain->link); | |
90cb0529 | 1044 | mmu_free_pte_chain(pte_chain); |
4db35314 AK |
1045 | if (hlist_empty(&sp->parent_ptes)) { |
1046 | sp->multimapped = 0; | |
1047 | sp->parent_pte = NULL; | |
697fe2e2 AK |
1048 | } |
1049 | } | |
cea0f0e7 AK |
1050 | return; |
1051 | } | |
1052 | BUG(); | |
1053 | } | |
1054 | ||
6b18493d | 1055 | static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn) |
ad8cfbe3 MT |
1056 | { |
1057 | struct kvm_pte_chain *pte_chain; | |
1058 | struct hlist_node *node; | |
1059 | struct kvm_mmu_page *parent_sp; | |
1060 | int i; | |
1061 | ||
1062 | if (!sp->multimapped && sp->parent_pte) { | |
1063 | parent_sp = page_header(__pa(sp->parent_pte)); | |
1047df1f | 1064 | fn(parent_sp, sp->parent_pte); |
ad8cfbe3 MT |
1065 | return; |
1066 | } | |
1047df1f | 1067 | |
ad8cfbe3 MT |
1068 | hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) |
1069 | for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) { | |
1047df1f XG |
1070 | u64 *spte = pte_chain->parent_ptes[i]; |
1071 | ||
1072 | if (!spte) | |
ad8cfbe3 | 1073 | break; |
1047df1f XG |
1074 | parent_sp = page_header(__pa(spte)); |
1075 | fn(parent_sp, spte); | |
ad8cfbe3 MT |
1076 | } |
1077 | } | |
1078 | ||
1047df1f XG |
1079 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte); |
1080 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) | |
0074ff63 | 1081 | { |
1047df1f | 1082 | mmu_parent_walk(sp, mark_unsync); |
0074ff63 MT |
1083 | } |
1084 | ||
1047df1f | 1085 | static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte) |
0074ff63 | 1086 | { |
1047df1f | 1087 | unsigned int index; |
0074ff63 | 1088 | |
1047df1f XG |
1089 | index = spte - sp->spt; |
1090 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1091 | return; |
1047df1f | 1092 | if (sp->unsync_children++) |
0074ff63 | 1093 | return; |
1047df1f | 1094 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1095 | } |
1096 | ||
d761a501 AK |
1097 | static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu, |
1098 | struct kvm_mmu_page *sp) | |
1099 | { | |
1100 | int i; | |
1101 | ||
1102 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1103 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
1104 | } | |
1105 | ||
e8bc217a | 1106 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
be71e061 | 1107 | struct kvm_mmu_page *sp, bool clear_unsync) |
e8bc217a MT |
1108 | { |
1109 | return 1; | |
1110 | } | |
1111 | ||
a7052897 MT |
1112 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1113 | { | |
1114 | } | |
1115 | ||
60c8aec6 MT |
1116 | #define KVM_PAGE_ARRAY_NR 16 |
1117 | ||
1118 | struct kvm_mmu_pages { | |
1119 | struct mmu_page_and_offset { | |
1120 | struct kvm_mmu_page *sp; | |
1121 | unsigned int idx; | |
1122 | } page[KVM_PAGE_ARRAY_NR]; | |
1123 | unsigned int nr; | |
1124 | }; | |
1125 | ||
0074ff63 MT |
1126 | #define for_each_unsync_children(bitmap, idx) \ |
1127 | for (idx = find_first_bit(bitmap, 512); \ | |
1128 | idx < 512; \ | |
1129 | idx = find_next_bit(bitmap, 512, idx+1)) | |
1130 | ||
cded19f3 HE |
1131 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1132 | int idx) | |
4731d4c7 | 1133 | { |
60c8aec6 | 1134 | int i; |
4731d4c7 | 1135 | |
60c8aec6 MT |
1136 | if (sp->unsync) |
1137 | for (i=0; i < pvec->nr; i++) | |
1138 | if (pvec->page[i].sp == sp) | |
1139 | return 0; | |
1140 | ||
1141 | pvec->page[pvec->nr].sp = sp; | |
1142 | pvec->page[pvec->nr].idx = idx; | |
1143 | pvec->nr++; | |
1144 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1145 | } | |
1146 | ||
1147 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1148 | struct kvm_mmu_pages *pvec) | |
1149 | { | |
1150 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1151 | |
0074ff63 | 1152 | for_each_unsync_children(sp->unsync_child_bitmap, i) { |
7a8f1a74 | 1153 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1154 | u64 ent = sp->spt[i]; |
1155 | ||
7a8f1a74 XG |
1156 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1157 | goto clear_child_bitmap; | |
1158 | ||
1159 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1160 | ||
1161 | if (child->unsync_children) { | |
1162 | if (mmu_pages_add(pvec, child, i)) | |
1163 | return -ENOSPC; | |
1164 | ||
1165 | ret = __mmu_unsync_walk(child, pvec); | |
1166 | if (!ret) | |
1167 | goto clear_child_bitmap; | |
1168 | else if (ret > 0) | |
1169 | nr_unsync_leaf += ret; | |
1170 | else | |
1171 | return ret; | |
1172 | } else if (child->unsync) { | |
1173 | nr_unsync_leaf++; | |
1174 | if (mmu_pages_add(pvec, child, i)) | |
1175 | return -ENOSPC; | |
1176 | } else | |
1177 | goto clear_child_bitmap; | |
1178 | ||
1179 | continue; | |
1180 | ||
1181 | clear_child_bitmap: | |
1182 | __clear_bit(i, sp->unsync_child_bitmap); | |
1183 | sp->unsync_children--; | |
1184 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1185 | } |
1186 | ||
4731d4c7 | 1187 | |
60c8aec6 MT |
1188 | return nr_unsync_leaf; |
1189 | } | |
1190 | ||
1191 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1192 | struct kvm_mmu_pages *pvec) | |
1193 | { | |
1194 | if (!sp->unsync_children) | |
1195 | return 0; | |
1196 | ||
1197 | mmu_pages_add(pvec, sp, 0); | |
1198 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1199 | } |
1200 | ||
4731d4c7 MT |
1201 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1202 | { | |
1203 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1204 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1205 | sp->unsync = 0; |
1206 | --kvm->stat.mmu_unsync; | |
1207 | } | |
1208 | ||
7775834a XG |
1209 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1210 | struct list_head *invalid_list); | |
1211 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1212 | struct list_head *invalid_list); | |
4731d4c7 | 1213 | |
f41d335a XG |
1214 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1215 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1216 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1217 | if ((sp)->gfn != (gfn)) {} else | |
1218 | ||
f41d335a XG |
1219 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1220 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1221 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1222 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1223 | (sp)->role.invalid) {} else | |
1224 | ||
f918b443 | 1225 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1226 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1227 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1228 | { |
5b7e0102 | 1229 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1230 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1231 | return 1; |
1232 | } | |
1233 | ||
f918b443 | 1234 | if (clear_unsync) |
1d9dc7e0 | 1235 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1236 | |
be71e061 | 1237 | if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) { |
d98ba053 | 1238 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1239 | return 1; |
1240 | } | |
1241 | ||
1242 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1243 | return 0; |
1244 | } | |
1245 | ||
1d9dc7e0 XG |
1246 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1247 | struct kvm_mmu_page *sp) | |
1248 | { | |
d98ba053 | 1249 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1250 | int ret; |
1251 | ||
d98ba053 | 1252 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1253 | if (ret) |
d98ba053 XG |
1254 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1255 | ||
1d9dc7e0 XG |
1256 | return ret; |
1257 | } | |
1258 | ||
d98ba053 XG |
1259 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1260 | struct list_head *invalid_list) | |
1d9dc7e0 | 1261 | { |
d98ba053 | 1262 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1263 | } |
1264 | ||
9f1a122f XG |
1265 | /* @gfn should be write-protected at the call site */ |
1266 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1267 | { | |
9f1a122f | 1268 | struct kvm_mmu_page *s; |
f41d335a | 1269 | struct hlist_node *node; |
d98ba053 | 1270 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1271 | bool flush = false; |
1272 | ||
f41d335a | 1273 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1274 | if (!s->unsync) |
9f1a122f XG |
1275 | continue; |
1276 | ||
1277 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
1278 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || | |
be71e061 | 1279 | (vcpu->arch.mmu.sync_page(vcpu, s, true))) { |
d98ba053 | 1280 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1281 | continue; |
1282 | } | |
1283 | kvm_unlink_unsync_page(vcpu->kvm, s); | |
1284 | flush = true; | |
1285 | } | |
1286 | ||
d98ba053 | 1287 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1288 | if (flush) |
1289 | kvm_mmu_flush_tlb(vcpu); | |
1290 | } | |
1291 | ||
60c8aec6 MT |
1292 | struct mmu_page_path { |
1293 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1294 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1295 | }; |
1296 | ||
60c8aec6 MT |
1297 | #define for_each_sp(pvec, sp, parents, i) \ |
1298 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1299 | sp = pvec.page[i].sp; \ | |
1300 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1301 | i = mmu_pages_next(&pvec, &parents, i)) | |
1302 | ||
cded19f3 HE |
1303 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1304 | struct mmu_page_path *parents, | |
1305 | int i) | |
60c8aec6 MT |
1306 | { |
1307 | int n; | |
1308 | ||
1309 | for (n = i+1; n < pvec->nr; n++) { | |
1310 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1311 | ||
1312 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1313 | parents->idx[0] = pvec->page[n].idx; | |
1314 | return n; | |
1315 | } | |
1316 | ||
1317 | parents->parent[sp->role.level-2] = sp; | |
1318 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1319 | } | |
1320 | ||
1321 | return n; | |
1322 | } | |
1323 | ||
cded19f3 | 1324 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1325 | { |
60c8aec6 MT |
1326 | struct kvm_mmu_page *sp; |
1327 | unsigned int level = 0; | |
1328 | ||
1329 | do { | |
1330 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1331 | |
60c8aec6 MT |
1332 | sp = parents->parent[level]; |
1333 | if (!sp) | |
1334 | return; | |
1335 | ||
1336 | --sp->unsync_children; | |
1337 | WARN_ON((int)sp->unsync_children < 0); | |
1338 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1339 | level++; | |
1340 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1341 | } |
1342 | ||
60c8aec6 MT |
1343 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1344 | struct mmu_page_path *parents, | |
1345 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1346 | { |
60c8aec6 MT |
1347 | parents->parent[parent->role.level-1] = NULL; |
1348 | pvec->nr = 0; | |
1349 | } | |
4731d4c7 | 1350 | |
60c8aec6 MT |
1351 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1352 | struct kvm_mmu_page *parent) | |
1353 | { | |
1354 | int i; | |
1355 | struct kvm_mmu_page *sp; | |
1356 | struct mmu_page_path parents; | |
1357 | struct kvm_mmu_pages pages; | |
d98ba053 | 1358 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1359 | |
1360 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1361 | while (mmu_unsync_walk(parent, &pages)) { | |
b1a36821 MT |
1362 | int protected = 0; |
1363 | ||
1364 | for_each_sp(pages, sp, parents, i) | |
1365 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1366 | ||
1367 | if (protected) | |
1368 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1369 | ||
60c8aec6 | 1370 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1371 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1372 | mmu_pages_clear_parents(&parents); |
1373 | } | |
d98ba053 | 1374 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1375 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1376 | kvm_mmu_pages_init(parent, &parents, &pages); |
1377 | } | |
4731d4c7 MT |
1378 | } |
1379 | ||
cea0f0e7 AK |
1380 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1381 | gfn_t gfn, | |
1382 | gva_t gaddr, | |
1383 | unsigned level, | |
f6e2c02b | 1384 | int direct, |
41074d07 | 1385 | unsigned access, |
f7d9c7b7 | 1386 | u64 *parent_pte) |
cea0f0e7 AK |
1387 | { |
1388 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1389 | unsigned quadrant; |
9f1a122f | 1390 | struct kvm_mmu_page *sp; |
f41d335a | 1391 | struct hlist_node *node; |
9f1a122f | 1392 | bool need_sync = false; |
cea0f0e7 | 1393 | |
a770f6f2 | 1394 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1395 | role.level = level; |
f6e2c02b | 1396 | role.direct = direct; |
84b0c8c6 | 1397 | if (role.direct) |
5b7e0102 | 1398 | role.cr4_pae = 0; |
41074d07 | 1399 | role.access = access; |
b66d8000 | 1400 | if (!tdp_enabled && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { |
cea0f0e7 AK |
1401 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1402 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1403 | role.quadrant = quadrant; | |
1404 | } | |
f41d335a | 1405 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1406 | if (!need_sync && sp->unsync) |
1407 | need_sync = true; | |
4731d4c7 | 1408 | |
7ae680eb XG |
1409 | if (sp->role.word != role.word) |
1410 | continue; | |
4731d4c7 | 1411 | |
7ae680eb XG |
1412 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1413 | break; | |
e02aa901 | 1414 | |
7ae680eb XG |
1415 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1416 | if (sp->unsync_children) { | |
a8eeb04a | 1417 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1418 | kvm_mmu_mark_parents_unsync(sp); |
1419 | } else if (sp->unsync) | |
1420 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1421 | |
7ae680eb XG |
1422 | trace_kvm_mmu_get_page(sp, false); |
1423 | return sp; | |
1424 | } | |
dfc5aa00 | 1425 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1426 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1427 | if (!sp) |
1428 | return sp; | |
4db35314 AK |
1429 | sp->gfn = gfn; |
1430 | sp->role = role; | |
7ae680eb XG |
1431 | hlist_add_head(&sp->hash_link, |
1432 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1433 | if (!direct) { |
b1a36821 MT |
1434 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1435 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1436 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1437 | kvm_sync_pages(vcpu, gfn); | |
1438 | ||
4731d4c7 MT |
1439 | account_shadowed(vcpu->kvm, gfn); |
1440 | } | |
131d8279 AK |
1441 | if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte) |
1442 | vcpu->arch.mmu.prefetch_page(vcpu, sp); | |
1443 | else | |
1444 | nonpaging_prefetch_page(vcpu, sp); | |
f691fe1d | 1445 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1446 | return sp; |
cea0f0e7 AK |
1447 | } |
1448 | ||
2d11123a AK |
1449 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1450 | struct kvm_vcpu *vcpu, u64 addr) | |
1451 | { | |
1452 | iterator->addr = addr; | |
1453 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1454 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
1455 | if (iterator->level == PT32E_ROOT_LEVEL) { | |
1456 | iterator->shadow_addr | |
1457 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1458 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1459 | --iterator->level; | |
1460 | if (!iterator->shadow_addr) | |
1461 | iterator->level = 0; | |
1462 | } | |
1463 | } | |
1464 | ||
1465 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1466 | { | |
1467 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1468 | return false; | |
4d88954d MT |
1469 | |
1470 | if (iterator->level == PT_PAGE_TABLE_LEVEL) | |
1471 | if (is_large_pte(*iterator->sptep)) | |
1472 | return false; | |
1473 | ||
2d11123a AK |
1474 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1475 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1476 | return true; | |
1477 | } | |
1478 | ||
1479 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) | |
1480 | { | |
1481 | iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK; | |
1482 | --iterator->level; | |
1483 | } | |
1484 | ||
90cb0529 | 1485 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 1486 | struct kvm_mmu_page *sp) |
a436036b | 1487 | { |
697fe2e2 AK |
1488 | unsigned i; |
1489 | u64 *pt; | |
1490 | u64 ent; | |
1491 | ||
4db35314 | 1492 | pt = sp->spt; |
697fe2e2 | 1493 | |
697fe2e2 AK |
1494 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { |
1495 | ent = pt[i]; | |
1496 | ||
05da4558 | 1497 | if (is_shadow_present_pte(ent)) { |
776e6633 | 1498 | if (!is_last_spte(ent, sp->role.level)) { |
05da4558 MT |
1499 | ent &= PT64_BASE_ADDR_MASK; |
1500 | mmu_page_remove_parent_pte(page_header(ent), | |
1501 | &pt[i]); | |
1502 | } else { | |
776e6633 MT |
1503 | if (is_large_pte(ent)) |
1504 | --kvm->stat.lpages; | |
be38d276 AK |
1505 | drop_spte(kvm, &pt[i], |
1506 | shadow_trap_nonpresent_pte); | |
05da4558 MT |
1507 | } |
1508 | } | |
c7addb90 | 1509 | pt[i] = shadow_trap_nonpresent_pte; |
697fe2e2 | 1510 | } |
a436036b AK |
1511 | } |
1512 | ||
4db35314 | 1513 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1514 | { |
4db35314 | 1515 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
1516 | } |
1517 | ||
12b7d28f AK |
1518 | static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm) |
1519 | { | |
1520 | int i; | |
988a2cae | 1521 | struct kvm_vcpu *vcpu; |
12b7d28f | 1522 | |
988a2cae GN |
1523 | kvm_for_each_vcpu(i, vcpu, kvm) |
1524 | vcpu->arch.last_pte_updated = NULL; | |
12b7d28f AK |
1525 | } |
1526 | ||
31aa2b44 | 1527 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b AK |
1528 | { |
1529 | u64 *parent_pte; | |
1530 | ||
4db35314 AK |
1531 | while (sp->multimapped || sp->parent_pte) { |
1532 | if (!sp->multimapped) | |
1533 | parent_pte = sp->parent_pte; | |
a436036b AK |
1534 | else { |
1535 | struct kvm_pte_chain *chain; | |
1536 | ||
4db35314 | 1537 | chain = container_of(sp->parent_ptes.first, |
a436036b AK |
1538 | struct kvm_pte_chain, link); |
1539 | parent_pte = chain->parent_ptes[0]; | |
1540 | } | |
697fe2e2 | 1541 | BUG_ON(!parent_pte); |
4db35314 | 1542 | kvm_mmu_put_page(sp, parent_pte); |
d555c333 | 1543 | __set_spte(parent_pte, shadow_trap_nonpresent_pte); |
a436036b | 1544 | } |
31aa2b44 AK |
1545 | } |
1546 | ||
60c8aec6 | 1547 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
1548 | struct kvm_mmu_page *parent, |
1549 | struct list_head *invalid_list) | |
4731d4c7 | 1550 | { |
60c8aec6 MT |
1551 | int i, zapped = 0; |
1552 | struct mmu_page_path parents; | |
1553 | struct kvm_mmu_pages pages; | |
4731d4c7 | 1554 | |
60c8aec6 | 1555 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1556 | return 0; |
60c8aec6 MT |
1557 | |
1558 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1559 | while (mmu_unsync_walk(parent, &pages)) { | |
1560 | struct kvm_mmu_page *sp; | |
1561 | ||
1562 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 1563 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 1564 | mmu_pages_clear_parents(&parents); |
77662e00 | 1565 | zapped++; |
60c8aec6 | 1566 | } |
60c8aec6 MT |
1567 | kvm_mmu_pages_init(parent, &parents, &pages); |
1568 | } | |
1569 | ||
1570 | return zapped; | |
4731d4c7 MT |
1571 | } |
1572 | ||
7775834a XG |
1573 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1574 | struct list_head *invalid_list) | |
31aa2b44 | 1575 | { |
4731d4c7 | 1576 | int ret; |
f691fe1d | 1577 | |
7775834a | 1578 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 1579 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 1580 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 1581 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 1582 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 1583 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 1584 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
1585 | if (sp->unsync) |
1586 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 1587 | if (!sp->root_count) { |
54a4f023 GJ |
1588 | /* Count self */ |
1589 | ret++; | |
7775834a | 1590 | list_move(&sp->link, invalid_list); |
2e53d63a | 1591 | } else { |
5b5c6a5a | 1592 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
1593 | kvm_reload_remote_mmus(kvm); |
1594 | } | |
7775834a XG |
1595 | |
1596 | sp->role.invalid = 1; | |
12b7d28f | 1597 | kvm_mmu_reset_last_pte_updated(kvm); |
4731d4c7 | 1598 | return ret; |
a436036b AK |
1599 | } |
1600 | ||
7775834a XG |
1601 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
1602 | struct list_head *invalid_list) | |
1603 | { | |
1604 | struct kvm_mmu_page *sp; | |
1605 | ||
1606 | if (list_empty(invalid_list)) | |
1607 | return; | |
1608 | ||
1609 | kvm_flush_remote_tlbs(kvm); | |
1610 | ||
1611 | do { | |
1612 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
1613 | WARN_ON(!sp->role.invalid || sp->root_count); | |
1614 | kvm_mmu_free_page(kvm, sp); | |
1615 | } while (!list_empty(invalid_list)); | |
1616 | ||
1617 | } | |
1618 | ||
82ce2c96 IE |
1619 | /* |
1620 | * Changing the number of mmu pages allocated to the vm | |
1621 | * Note: if kvm_nr_mmu_pages is too small, you will get dead lock | |
1622 | */ | |
1623 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages) | |
1624 | { | |
025dbbf3 | 1625 | int used_pages; |
d98ba053 | 1626 | LIST_HEAD(invalid_list); |
025dbbf3 MT |
1627 | |
1628 | used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages; | |
1629 | used_pages = max(0, used_pages); | |
1630 | ||
82ce2c96 IE |
1631 | /* |
1632 | * If we set the number of mmu pages to be smaller be than the | |
1633 | * number of actived pages , we must to free some mmu pages before we | |
1634 | * change the value | |
1635 | */ | |
1636 | ||
025dbbf3 | 1637 | if (used_pages > kvm_nr_mmu_pages) { |
77662e00 XG |
1638 | while (used_pages > kvm_nr_mmu_pages && |
1639 | !list_empty(&kvm->arch.active_mmu_pages)) { | |
82ce2c96 IE |
1640 | struct kvm_mmu_page *page; |
1641 | ||
f05e70ac | 1642 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 1643 | struct kvm_mmu_page, link); |
d98ba053 XG |
1644 | used_pages -= kvm_mmu_prepare_zap_page(kvm, page, |
1645 | &invalid_list); | |
82ce2c96 | 1646 | } |
d98ba053 | 1647 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
77662e00 | 1648 | kvm_nr_mmu_pages = used_pages; |
f05e70ac | 1649 | kvm->arch.n_free_mmu_pages = 0; |
82ce2c96 IE |
1650 | } |
1651 | else | |
f05e70ac ZX |
1652 | kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages |
1653 | - kvm->arch.n_alloc_mmu_pages; | |
82ce2c96 | 1654 | |
f05e70ac | 1655 | kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages; |
82ce2c96 IE |
1656 | } |
1657 | ||
f67a46f4 | 1658 | static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 1659 | { |
4db35314 | 1660 | struct kvm_mmu_page *sp; |
f41d335a | 1661 | struct hlist_node *node; |
d98ba053 | 1662 | LIST_HEAD(invalid_list); |
a436036b AK |
1663 | int r; |
1664 | ||
b8688d51 | 1665 | pgprintk("%s: looking for gfn %lx\n", __func__, gfn); |
a436036b | 1666 | r = 0; |
f41d335a XG |
1667 | |
1668 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { | |
7ae680eb XG |
1669 | pgprintk("%s: gfn %lx role %x\n", __func__, gfn, |
1670 | sp->role.word); | |
1671 | r = 1; | |
f41d335a | 1672 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 1673 | } |
d98ba053 | 1674 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
a436036b | 1675 | return r; |
cea0f0e7 AK |
1676 | } |
1677 | ||
f67a46f4 | 1678 | static void mmu_unshadow(struct kvm *kvm, gfn_t gfn) |
97a0a01e | 1679 | { |
4db35314 | 1680 | struct kvm_mmu_page *sp; |
f41d335a | 1681 | struct hlist_node *node; |
d98ba053 | 1682 | LIST_HEAD(invalid_list); |
97a0a01e | 1683 | |
f41d335a | 1684 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
7ae680eb XG |
1685 | pgprintk("%s: zap %lx %x\n", |
1686 | __func__, gfn, sp->role.word); | |
f41d335a | 1687 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
97a0a01e | 1688 | } |
d98ba053 | 1689 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
97a0a01e AK |
1690 | } |
1691 | ||
38c335f1 | 1692 | static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) |
6aa8b732 | 1693 | { |
bc6678a3 | 1694 | int slot = memslot_id(kvm, gfn); |
4db35314 | 1695 | struct kvm_mmu_page *sp = page_header(__pa(pte)); |
6aa8b732 | 1696 | |
291f26bc | 1697 | __set_bit(slot, sp->slot_bitmap); |
6aa8b732 AK |
1698 | } |
1699 | ||
6844dec6 MT |
1700 | static void mmu_convert_notrap(struct kvm_mmu_page *sp) |
1701 | { | |
1702 | int i; | |
1703 | u64 *pt = sp->spt; | |
1704 | ||
1705 | if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte) | |
1706 | return; | |
1707 | ||
1708 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
1709 | if (pt[i] == shadow_notrap_nonpresent_pte) | |
d555c333 | 1710 | __set_spte(&pt[i], shadow_trap_nonpresent_pte); |
6844dec6 MT |
1711 | } |
1712 | } | |
1713 | ||
74be52e3 SY |
1714 | /* |
1715 | * The function is based on mtrr_type_lookup() in | |
1716 | * arch/x86/kernel/cpu/mtrr/generic.c | |
1717 | */ | |
1718 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
1719 | u64 start, u64 end) | |
1720 | { | |
1721 | int i; | |
1722 | u64 base, mask; | |
1723 | u8 prev_match, curr_match; | |
1724 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
1725 | ||
1726 | if (!mtrr_state->enabled) | |
1727 | return 0xFF; | |
1728 | ||
1729 | /* Make end inclusive end, instead of exclusive */ | |
1730 | end--; | |
1731 | ||
1732 | /* Look in fixed ranges. Just return the type as per start */ | |
1733 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
1734 | int idx; | |
1735 | ||
1736 | if (start < 0x80000) { | |
1737 | idx = 0; | |
1738 | idx += (start >> 16); | |
1739 | return mtrr_state->fixed_ranges[idx]; | |
1740 | } else if (start < 0xC0000) { | |
1741 | idx = 1 * 8; | |
1742 | idx += ((start - 0x80000) >> 14); | |
1743 | return mtrr_state->fixed_ranges[idx]; | |
1744 | } else if (start < 0x1000000) { | |
1745 | idx = 3 * 8; | |
1746 | idx += ((start - 0xC0000) >> 12); | |
1747 | return mtrr_state->fixed_ranges[idx]; | |
1748 | } | |
1749 | } | |
1750 | ||
1751 | /* | |
1752 | * Look in variable ranges | |
1753 | * Look of multiple ranges matching this address and pick type | |
1754 | * as per MTRR precedence | |
1755 | */ | |
1756 | if (!(mtrr_state->enabled & 2)) | |
1757 | return mtrr_state->def_type; | |
1758 | ||
1759 | prev_match = 0xFF; | |
1760 | for (i = 0; i < num_var_ranges; ++i) { | |
1761 | unsigned short start_state, end_state; | |
1762 | ||
1763 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
1764 | continue; | |
1765 | ||
1766 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
1767 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
1768 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
1769 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
1770 | ||
1771 | start_state = ((start & mask) == (base & mask)); | |
1772 | end_state = ((end & mask) == (base & mask)); | |
1773 | if (start_state != end_state) | |
1774 | return 0xFE; | |
1775 | ||
1776 | if ((start & mask) != (base & mask)) | |
1777 | continue; | |
1778 | ||
1779 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
1780 | if (prev_match == 0xFF) { | |
1781 | prev_match = curr_match; | |
1782 | continue; | |
1783 | } | |
1784 | ||
1785 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
1786 | curr_match == MTRR_TYPE_UNCACHABLE) | |
1787 | return MTRR_TYPE_UNCACHABLE; | |
1788 | ||
1789 | if ((prev_match == MTRR_TYPE_WRBACK && | |
1790 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
1791 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
1792 | curr_match == MTRR_TYPE_WRBACK)) { | |
1793 | prev_match = MTRR_TYPE_WRTHROUGH; | |
1794 | curr_match = MTRR_TYPE_WRTHROUGH; | |
1795 | } | |
1796 | ||
1797 | if (prev_match != curr_match) | |
1798 | return MTRR_TYPE_UNCACHABLE; | |
1799 | } | |
1800 | ||
1801 | if (prev_match != 0xFF) | |
1802 | return prev_match; | |
1803 | ||
1804 | return mtrr_state->def_type; | |
1805 | } | |
1806 | ||
4b12f0de | 1807 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
1808 | { |
1809 | u8 mtrr; | |
1810 | ||
1811 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
1812 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
1813 | if (mtrr == 0xfe || mtrr == 0xff) | |
1814 | mtrr = MTRR_TYPE_WRBACK; | |
1815 | return mtrr; | |
1816 | } | |
4b12f0de | 1817 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 1818 | |
9cf5cf5a XG |
1819 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
1820 | { | |
1821 | trace_kvm_mmu_unsync_page(sp); | |
1822 | ++vcpu->kvm->stat.mmu_unsync; | |
1823 | sp->unsync = 1; | |
1824 | ||
1825 | kvm_mmu_mark_parents_unsync(sp); | |
1826 | mmu_convert_notrap(sp); | |
1827 | } | |
1828 | ||
1829 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 1830 | { |
4731d4c7 | 1831 | struct kvm_mmu_page *s; |
f41d335a | 1832 | struct hlist_node *node; |
9cf5cf5a | 1833 | |
f41d335a | 1834 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1835 | if (s->unsync) |
4731d4c7 | 1836 | continue; |
9cf5cf5a XG |
1837 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
1838 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 1839 | } |
4731d4c7 MT |
1840 | } |
1841 | ||
1842 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1843 | bool can_unsync) | |
1844 | { | |
9cf5cf5a | 1845 | struct kvm_mmu_page *s; |
f41d335a | 1846 | struct hlist_node *node; |
9cf5cf5a XG |
1847 | bool need_unsync = false; |
1848 | ||
f41d335a | 1849 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
1850 | if (!can_unsync) |
1851 | return 1; | |
1852 | ||
9cf5cf5a | 1853 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 1854 | return 1; |
9cf5cf5a XG |
1855 | |
1856 | if (!need_unsync && !s->unsync) { | |
36a2e677 | 1857 | if (!oos_shadow) |
9cf5cf5a XG |
1858 | return 1; |
1859 | need_unsync = true; | |
1860 | } | |
4731d4c7 | 1861 | } |
9cf5cf5a XG |
1862 | if (need_unsync) |
1863 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
1864 | return 0; |
1865 | } | |
1866 | ||
d555c333 | 1867 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 1868 | unsigned pte_access, int user_fault, |
852e3c19 | 1869 | int write_fault, int dirty, int level, |
c2d0ee46 | 1870 | gfn_t gfn, pfn_t pfn, bool speculative, |
1403283a | 1871 | bool can_unsync, bool reset_host_protection) |
1c4f1fd6 AK |
1872 | { |
1873 | u64 spte; | |
1e73f9dd | 1874 | int ret = 0; |
64d4d521 | 1875 | |
1c4f1fd6 AK |
1876 | /* |
1877 | * We don't set the accessed bit, since we sometimes want to see | |
1878 | * whether the guest actually used the pte (in order to detect | |
1879 | * demand paging). | |
1880 | */ | |
7b52345e | 1881 | spte = shadow_base_present_pte | shadow_dirty_mask; |
947da538 | 1882 | if (!speculative) |
3201b5d9 | 1883 | spte |= shadow_accessed_mask; |
1c4f1fd6 AK |
1884 | if (!dirty) |
1885 | pte_access &= ~ACC_WRITE_MASK; | |
7b52345e SY |
1886 | if (pte_access & ACC_EXEC_MASK) |
1887 | spte |= shadow_x_mask; | |
1888 | else | |
1889 | spte |= shadow_nx_mask; | |
1c4f1fd6 | 1890 | if (pte_access & ACC_USER_MASK) |
7b52345e | 1891 | spte |= shadow_user_mask; |
852e3c19 | 1892 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 1893 | spte |= PT_PAGE_SIZE_MASK; |
4b12f0de SY |
1894 | if (tdp_enabled) |
1895 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, | |
1896 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 1897 | |
1403283a IE |
1898 | if (reset_host_protection) |
1899 | spte |= SPTE_HOST_WRITEABLE; | |
1900 | ||
35149e21 | 1901 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 AK |
1902 | |
1903 | if ((pte_access & ACC_WRITE_MASK) | |
8184dd38 AK |
1904 | || (!tdp_enabled && write_fault && !is_write_protection(vcpu) |
1905 | && !user_fault)) { | |
1c4f1fd6 | 1906 | |
852e3c19 JR |
1907 | if (level > PT_PAGE_TABLE_LEVEL && |
1908 | has_wrprotected_page(vcpu->kvm, gfn, level)) { | |
38187c83 | 1909 | ret = 1; |
be38d276 AK |
1910 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
1911 | goto done; | |
38187c83 MT |
1912 | } |
1913 | ||
1c4f1fd6 | 1914 | spte |= PT_WRITABLE_MASK; |
1c4f1fd6 | 1915 | |
69325a12 AK |
1916 | if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK)) |
1917 | spte &= ~PT_USER_MASK; | |
1918 | ||
ecc5589f MT |
1919 | /* |
1920 | * Optimization: for pte sync, if spte was writable the hash | |
1921 | * lookup is unnecessary (and expensive). Write protection | |
1922 | * is responsibility of mmu_get_page / kvm_sync_page. | |
1923 | * Same reasoning can be applied to dirty page accounting. | |
1924 | */ | |
8dae4445 | 1925 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
1926 | goto set_pte; |
1927 | ||
4731d4c7 | 1928 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
1c4f1fd6 | 1929 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
b8688d51 | 1930 | __func__, gfn); |
1e73f9dd | 1931 | ret = 1; |
1c4f1fd6 | 1932 | pte_access &= ~ACC_WRITE_MASK; |
8dae4445 | 1933 | if (is_writable_pte(spte)) |
1c4f1fd6 | 1934 | spte &= ~PT_WRITABLE_MASK; |
1c4f1fd6 AK |
1935 | } |
1936 | } | |
1937 | ||
1c4f1fd6 AK |
1938 | if (pte_access & ACC_WRITE_MASK) |
1939 | mark_page_dirty(vcpu->kvm, gfn); | |
1940 | ||
38187c83 | 1941 | set_pte: |
b79b93f9 | 1942 | update_spte(sptep, spte); |
be38d276 | 1943 | done: |
1e73f9dd MT |
1944 | return ret; |
1945 | } | |
1946 | ||
d555c333 | 1947 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd MT |
1948 | unsigned pt_access, unsigned pte_access, |
1949 | int user_fault, int write_fault, int dirty, | |
852e3c19 | 1950 | int *ptwrite, int level, gfn_t gfn, |
1403283a IE |
1951 | pfn_t pfn, bool speculative, |
1952 | bool reset_host_protection) | |
1e73f9dd MT |
1953 | { |
1954 | int was_rmapped = 0; | |
8dae4445 | 1955 | int was_writable = is_writable_pte(*sptep); |
53a27b39 | 1956 | int rmap_count; |
1e73f9dd MT |
1957 | |
1958 | pgprintk("%s: spte %llx access %x write_fault %d" | |
1959 | " user_fault %d gfn %lx\n", | |
d555c333 | 1960 | __func__, *sptep, pt_access, |
1e73f9dd MT |
1961 | write_fault, user_fault, gfn); |
1962 | ||
d555c333 | 1963 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
1964 | /* |
1965 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
1966 | * the parent of the now unreachable PTE. | |
1967 | */ | |
852e3c19 JR |
1968 | if (level > PT_PAGE_TABLE_LEVEL && |
1969 | !is_large_pte(*sptep)) { | |
1e73f9dd | 1970 | struct kvm_mmu_page *child; |
d555c333 | 1971 | u64 pte = *sptep; |
1e73f9dd MT |
1972 | |
1973 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
d555c333 | 1974 | mmu_page_remove_parent_pte(child, sptep); |
3be2264b MT |
1975 | __set_spte(sptep, shadow_trap_nonpresent_pte); |
1976 | kvm_flush_remote_tlbs(vcpu->kvm); | |
d555c333 | 1977 | } else if (pfn != spte_to_pfn(*sptep)) { |
1e73f9dd | 1978 | pgprintk("hfn old %lx new %lx\n", |
d555c333 | 1979 | spte_to_pfn(*sptep), pfn); |
be38d276 | 1980 | drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte); |
91546356 | 1981 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
1982 | } else |
1983 | was_rmapped = 1; | |
1e73f9dd | 1984 | } |
852e3c19 | 1985 | |
d555c333 | 1986 | if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault, |
1403283a IE |
1987 | dirty, level, gfn, pfn, speculative, true, |
1988 | reset_host_protection)) { | |
1e73f9dd MT |
1989 | if (write_fault) |
1990 | *ptwrite = 1; | |
5304efde | 1991 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 1992 | } |
1e73f9dd | 1993 | |
d555c333 | 1994 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
1e73f9dd | 1995 | pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n", |
d555c333 | 1996 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
1997 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
1998 | *sptep, sptep); | |
d555c333 | 1999 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2000 | ++vcpu->kvm->stat.lpages; |
2001 | ||
d555c333 | 2002 | page_header_update_slot(vcpu->kvm, sptep, gfn); |
1c4f1fd6 | 2003 | if (!was_rmapped) { |
44ad9944 | 2004 | rmap_count = rmap_add(vcpu, sptep, gfn); |
acb66dd0 | 2005 | kvm_release_pfn_clean(pfn); |
53a27b39 | 2006 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) |
852e3c19 | 2007 | rmap_recycle(vcpu, sptep, gfn); |
75e68e60 | 2008 | } else { |
8dae4445 | 2009 | if (was_writable) |
35149e21 | 2010 | kvm_release_pfn_dirty(pfn); |
75e68e60 | 2011 | else |
35149e21 | 2012 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 | 2013 | } |
1b7fcd32 | 2014 | if (speculative) { |
d555c333 | 2015 | vcpu->arch.last_pte_updated = sptep; |
1b7fcd32 AK |
2016 | vcpu->arch.last_pte_gfn = gfn; |
2017 | } | |
1c4f1fd6 AK |
2018 | } |
2019 | ||
6aa8b732 AK |
2020 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2021 | { | |
2022 | } | |
2023 | ||
9f652d21 | 2024 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
852e3c19 | 2025 | int level, gfn_t gfn, pfn_t pfn) |
140754bc | 2026 | { |
9f652d21 | 2027 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2028 | struct kvm_mmu_page *sp; |
9f652d21 | 2029 | int pt_write = 0; |
140754bc | 2030 | gfn_t pseudo_gfn; |
6aa8b732 | 2031 | |
9f652d21 | 2032 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2033 | if (iterator.level == level) { |
9f652d21 AK |
2034 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL, |
2035 | 0, write, 1, &pt_write, | |
1403283a | 2036 | level, gfn, pfn, false, true); |
9f652d21 AK |
2037 | ++vcpu->stat.pf_fixed; |
2038 | break; | |
6aa8b732 AK |
2039 | } |
2040 | ||
9f652d21 | 2041 | if (*iterator.sptep == shadow_trap_nonpresent_pte) { |
c9fa0b3b LJ |
2042 | u64 base_addr = iterator.addr; |
2043 | ||
2044 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2045 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2046 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2047 | iterator.level - 1, | |
2048 | 1, ACC_ALL, iterator.sptep); | |
2049 | if (!sp) { | |
2050 | pgprintk("nonpaging_map: ENOMEM\n"); | |
2051 | kvm_release_pfn_clean(pfn); | |
2052 | return -ENOMEM; | |
2053 | } | |
140754bc | 2054 | |
d555c333 AK |
2055 | __set_spte(iterator.sptep, |
2056 | __pa(sp->spt) | |
2057 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2058 | | shadow_user_mask | shadow_x_mask); | |
9f652d21 AK |
2059 | } |
2060 | } | |
2061 | return pt_write; | |
6aa8b732 AK |
2062 | } |
2063 | ||
bf998156 HY |
2064 | static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn) |
2065 | { | |
2066 | char buf[1]; | |
2067 | void __user *hva; | |
2068 | int r; | |
2069 | ||
2070 | /* Touch the page, so send SIGBUS */ | |
2071 | hva = (void __user *)gfn_to_hva(kvm, gfn); | |
2072 | r = copy_from_user(buf, hva, 1); | |
2073 | } | |
2074 | ||
2075 | static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn) | |
2076 | { | |
2077 | kvm_release_pfn_clean(pfn); | |
2078 | if (is_hwpoison_pfn(pfn)) { | |
2079 | kvm_send_hwpoison_signal(kvm, gfn); | |
2080 | return 0; | |
edba23e5 GN |
2081 | } else if (is_fault_pfn(pfn)) |
2082 | return -EFAULT; | |
2083 | ||
bf998156 HY |
2084 | return 1; |
2085 | } | |
2086 | ||
10589a46 MT |
2087 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) |
2088 | { | |
2089 | int r; | |
852e3c19 | 2090 | int level; |
35149e21 | 2091 | pfn_t pfn; |
e930bffe | 2092 | unsigned long mmu_seq; |
aaee2c94 | 2093 | |
852e3c19 JR |
2094 | level = mapping_level(vcpu, gfn); |
2095 | ||
2096 | /* | |
2097 | * This path builds a PAE pagetable - so we can map 2mb pages at | |
2098 | * maximum. Therefore check if the level is larger than that. | |
2099 | */ | |
2100 | if (level > PT_DIRECTORY_LEVEL) | |
2101 | level = PT_DIRECTORY_LEVEL; | |
2102 | ||
2103 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 2104 | |
e930bffe | 2105 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2106 | smp_rmb(); |
35149e21 | 2107 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
aaee2c94 | 2108 | |
d196e343 | 2109 | /* mmio */ |
bf998156 HY |
2110 | if (is_error_pfn(pfn)) |
2111 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
d196e343 | 2112 | |
aaee2c94 | 2113 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2114 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2115 | goto out_unlock; | |
eb787d10 | 2116 | kvm_mmu_free_some_pages(vcpu); |
852e3c19 | 2117 | r = __direct_map(vcpu, v, write, level, gfn, pfn); |
aaee2c94 MT |
2118 | spin_unlock(&vcpu->kvm->mmu_lock); |
2119 | ||
aaee2c94 | 2120 | |
10589a46 | 2121 | return r; |
e930bffe AA |
2122 | |
2123 | out_unlock: | |
2124 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2125 | kvm_release_pfn_clean(pfn); | |
2126 | return 0; | |
10589a46 MT |
2127 | } |
2128 | ||
2129 | ||
17ac10ad AK |
2130 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2131 | { | |
2132 | int i; | |
4db35314 | 2133 | struct kvm_mmu_page *sp; |
d98ba053 | 2134 | LIST_HEAD(invalid_list); |
17ac10ad | 2135 | |
ad312c7c | 2136 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2137 | return; |
aaee2c94 | 2138 | spin_lock(&vcpu->kvm->mmu_lock); |
ad312c7c ZX |
2139 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2140 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad | 2141 | |
4db35314 AK |
2142 | sp = page_header(root); |
2143 | --sp->root_count; | |
d98ba053 XG |
2144 | if (!sp->root_count && sp->role.invalid) { |
2145 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2146 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2147 | } | |
ad312c7c | 2148 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2149 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2150 | return; |
2151 | } | |
17ac10ad | 2152 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2153 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2154 | |
417726a3 | 2155 | if (root) { |
417726a3 | 2156 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2157 | sp = page_header(root); |
2158 | --sp->root_count; | |
2e53d63a | 2159 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2160 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2161 | &invalid_list); | |
417726a3 | 2162 | } |
ad312c7c | 2163 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2164 | } |
d98ba053 | 2165 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2166 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2167 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2168 | } |
2169 | ||
8986ecc0 MT |
2170 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2171 | { | |
2172 | int ret = 0; | |
2173 | ||
2174 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2175 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2176 | ret = 1; |
2177 | } | |
2178 | ||
2179 | return ret; | |
2180 | } | |
2181 | ||
2182 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) | |
17ac10ad AK |
2183 | { |
2184 | int i; | |
cea0f0e7 | 2185 | gfn_t root_gfn; |
4db35314 | 2186 | struct kvm_mmu_page *sp; |
f6e2c02b | 2187 | int direct = 0; |
6de4f3ad | 2188 | u64 pdptr; |
3bb65a22 | 2189 | |
ad312c7c | 2190 | root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT; |
17ac10ad | 2191 | |
ad312c7c ZX |
2192 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { |
2193 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
17ac10ad AK |
2194 | |
2195 | ASSERT(!VALID_PAGE(root)); | |
8986ecc0 MT |
2196 | if (mmu_check_root(vcpu, root_gfn)) |
2197 | return 1; | |
5a7388c2 EN |
2198 | if (tdp_enabled) { |
2199 | direct = 1; | |
2200 | root_gfn = 0; | |
2201 | } | |
8facbbff | 2202 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2203 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2204 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
f6e2c02b | 2205 | PT64_ROOT_LEVEL, direct, |
fb72d167 | 2206 | ACC_ALL, NULL); |
4db35314 AK |
2207 | root = __pa(sp->spt); |
2208 | ++sp->root_count; | |
8facbbff | 2209 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2210 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2211 | return 0; |
17ac10ad | 2212 | } |
f6e2c02b | 2213 | direct = !is_paging(vcpu); |
17ac10ad | 2214 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2215 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
2216 | |
2217 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 2218 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
6de4f3ad | 2219 | pdptr = kvm_pdptr_read(vcpu, i); |
43a3795a | 2220 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 2221 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
2222 | continue; |
2223 | } | |
6de4f3ad | 2224 | root_gfn = pdptr >> PAGE_SHIFT; |
ad312c7c | 2225 | } else if (vcpu->arch.mmu.root_level == 0) |
cea0f0e7 | 2226 | root_gfn = 0; |
8986ecc0 MT |
2227 | if (mmu_check_root(vcpu, root_gfn)) |
2228 | return 1; | |
5a7388c2 EN |
2229 | if (tdp_enabled) { |
2230 | direct = 1; | |
2231 | root_gfn = i << 30; | |
2232 | } | |
8facbbff | 2233 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2234 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 2235 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
f6e2c02b | 2236 | PT32_ROOT_LEVEL, direct, |
f7d9c7b7 | 2237 | ACC_ALL, NULL); |
4db35314 AK |
2238 | root = __pa(sp->spt); |
2239 | ++sp->root_count; | |
8facbbff AK |
2240 | spin_unlock(&vcpu->kvm->mmu_lock); |
2241 | ||
ad312c7c | 2242 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; |
17ac10ad | 2243 | } |
ad312c7c | 2244 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
8986ecc0 | 2245 | return 0; |
17ac10ad AK |
2246 | } |
2247 | ||
0ba73cda MT |
2248 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
2249 | { | |
2250 | int i; | |
2251 | struct kvm_mmu_page *sp; | |
2252 | ||
2253 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2254 | return; | |
2255 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2256 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
2257 | sp = page_header(root); | |
2258 | mmu_sync_children(vcpu, sp); | |
2259 | return; | |
2260 | } | |
2261 | for (i = 0; i < 4; ++i) { | |
2262 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2263 | ||
8986ecc0 | 2264 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
2265 | root &= PT64_BASE_ADDR_MASK; |
2266 | sp = page_header(root); | |
2267 | mmu_sync_children(vcpu, sp); | |
2268 | } | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
2273 | { | |
2274 | spin_lock(&vcpu->kvm->mmu_lock); | |
2275 | mmu_sync_roots(vcpu); | |
6cffe8ca | 2276 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
2277 | } |
2278 | ||
1871c602 GN |
2279 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
2280 | u32 access, u32 *error) | |
6aa8b732 | 2281 | { |
1871c602 GN |
2282 | if (error) |
2283 | *error = 0; | |
6aa8b732 AK |
2284 | return vaddr; |
2285 | } | |
2286 | ||
2287 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, | |
3f3e7124 | 2288 | u32 error_code) |
6aa8b732 | 2289 | { |
e833240f | 2290 | gfn_t gfn; |
e2dec939 | 2291 | int r; |
6aa8b732 | 2292 | |
b8688d51 | 2293 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
e2dec939 AK |
2294 | r = mmu_topup_memory_caches(vcpu); |
2295 | if (r) | |
2296 | return r; | |
714b93da | 2297 | |
6aa8b732 | 2298 | ASSERT(vcpu); |
ad312c7c | 2299 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2300 | |
e833240f | 2301 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 2302 | |
e833240f AK |
2303 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
2304 | error_code & PFERR_WRITE_MASK, gfn); | |
6aa8b732 AK |
2305 | } |
2306 | ||
fb72d167 JR |
2307 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, |
2308 | u32 error_code) | |
2309 | { | |
35149e21 | 2310 | pfn_t pfn; |
fb72d167 | 2311 | int r; |
852e3c19 | 2312 | int level; |
05da4558 | 2313 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 2314 | unsigned long mmu_seq; |
fb72d167 JR |
2315 | |
2316 | ASSERT(vcpu); | |
2317 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
2318 | ||
2319 | r = mmu_topup_memory_caches(vcpu); | |
2320 | if (r) | |
2321 | return r; | |
2322 | ||
852e3c19 JR |
2323 | level = mapping_level(vcpu, gfn); |
2324 | ||
2325 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
2326 | ||
e930bffe | 2327 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2328 | smp_rmb(); |
35149e21 | 2329 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
bf998156 HY |
2330 | if (is_error_pfn(pfn)) |
2331 | return kvm_handle_bad_page(vcpu->kvm, gfn, pfn); | |
fb72d167 | 2332 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
2333 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
2334 | goto out_unlock; | |
fb72d167 JR |
2335 | kvm_mmu_free_some_pages(vcpu); |
2336 | r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK, | |
852e3c19 | 2337 | level, gfn, pfn); |
fb72d167 | 2338 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
2339 | |
2340 | return r; | |
e930bffe AA |
2341 | |
2342 | out_unlock: | |
2343 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2344 | kvm_release_pfn_clean(pfn); | |
2345 | return 0; | |
fb72d167 JR |
2346 | } |
2347 | ||
6aa8b732 AK |
2348 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
2349 | { | |
17ac10ad | 2350 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2351 | } |
2352 | ||
2353 | static int nonpaging_init_context(struct kvm_vcpu *vcpu) | |
2354 | { | |
ad312c7c | 2355 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2356 | |
2357 | context->new_cr3 = nonpaging_new_cr3; | |
2358 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
2359 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
2360 | context->free = nonpaging_free; | |
c7addb90 | 2361 | context->prefetch_page = nonpaging_prefetch_page; |
e8bc217a | 2362 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2363 | context->invlpg = nonpaging_invlpg; |
cea0f0e7 | 2364 | context->root_level = 0; |
6aa8b732 | 2365 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 2366 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2367 | return 0; |
2368 | } | |
2369 | ||
d835dfec | 2370 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 2371 | { |
1165f5fe | 2372 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 2373 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
2374 | } |
2375 | ||
2376 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
2377 | { | |
b8688d51 | 2378 | pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3); |
cea0f0e7 | 2379 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2380 | } |
2381 | ||
6aa8b732 AK |
2382 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
2383 | u64 addr, | |
2384 | u32 err_code) | |
2385 | { | |
c3c91fee | 2386 | kvm_inject_page_fault(vcpu, addr, err_code); |
6aa8b732 AK |
2387 | } |
2388 | ||
6aa8b732 AK |
2389 | static void paging_free(struct kvm_vcpu *vcpu) |
2390 | { | |
2391 | nonpaging_free(vcpu); | |
2392 | } | |
2393 | ||
82725b20 DE |
2394 | static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level) |
2395 | { | |
2396 | int bit7; | |
2397 | ||
2398 | bit7 = (gpte >> 7) & 1; | |
2399 | return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0; | |
2400 | } | |
2401 | ||
6aa8b732 AK |
2402 | #define PTTYPE 64 |
2403 | #include "paging_tmpl.h" | |
2404 | #undef PTTYPE | |
2405 | ||
2406 | #define PTTYPE 32 | |
2407 | #include "paging_tmpl.h" | |
2408 | #undef PTTYPE | |
2409 | ||
82725b20 DE |
2410 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level) |
2411 | { | |
2412 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2413 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
2414 | u64 exb_bit_rsvd = 0; | |
2415 | ||
2416 | if (!is_nx(vcpu)) | |
2417 | exb_bit_rsvd = rsvd_bits(63, 63); | |
2418 | switch (level) { | |
2419 | case PT32_ROOT_LEVEL: | |
2420 | /* no rsvd bits for 2 level 4K page table entries */ | |
2421 | context->rsvd_bits_mask[0][1] = 0; | |
2422 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
2423 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
2424 | ||
2425 | if (!is_pse(vcpu)) { | |
2426 | context->rsvd_bits_mask[1][1] = 0; | |
2427 | break; | |
2428 | } | |
2429 | ||
82725b20 DE |
2430 | if (is_cpuid_PSE36()) |
2431 | /* 36bits PSE 4MB page */ | |
2432 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
2433 | else | |
2434 | /* 32 bits PSE 4MB page */ | |
2435 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
2436 | break; |
2437 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
2438 | context->rsvd_bits_mask[0][2] = |
2439 | rsvd_bits(maxphyaddr, 63) | | |
2440 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 2441 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 2442 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
2443 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2444 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
2445 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
2446 | rsvd_bits(maxphyaddr, 62) | | |
2447 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2448 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2449 | break; |
2450 | case PT64_ROOT_LEVEL: | |
2451 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
2452 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2453 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
2454 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
2455 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 2456 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
2457 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
2458 | rsvd_bits(maxphyaddr, 51); | |
2459 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
2460 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
2461 | rsvd_bits(maxphyaddr, 51) | | |
2462 | rsvd_bits(13, 29); | |
82725b20 | 2463 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
2464 | rsvd_bits(maxphyaddr, 51) | |
2465 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 2466 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
2467 | break; |
2468 | } | |
2469 | } | |
2470 | ||
17ac10ad | 2471 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level) |
6aa8b732 | 2472 | { |
ad312c7c | 2473 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 AK |
2474 | |
2475 | ASSERT(is_pae(vcpu)); | |
2476 | context->new_cr3 = paging_new_cr3; | |
2477 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 2478 | context->gva_to_gpa = paging64_gva_to_gpa; |
c7addb90 | 2479 | context->prefetch_page = paging64_prefetch_page; |
e8bc217a | 2480 | context->sync_page = paging64_sync_page; |
a7052897 | 2481 | context->invlpg = paging64_invlpg; |
6aa8b732 | 2482 | context->free = paging_free; |
17ac10ad AK |
2483 | context->root_level = level; |
2484 | context->shadow_root_level = level; | |
17c3ba9d | 2485 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2486 | return 0; |
2487 | } | |
2488 | ||
17ac10ad AK |
2489 | static int paging64_init_context(struct kvm_vcpu *vcpu) |
2490 | { | |
82725b20 | 2491 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
17ac10ad AK |
2492 | return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL); |
2493 | } | |
2494 | ||
6aa8b732 AK |
2495 | static int paging32_init_context(struct kvm_vcpu *vcpu) |
2496 | { | |
ad312c7c | 2497 | struct kvm_mmu *context = &vcpu->arch.mmu; |
6aa8b732 | 2498 | |
82725b20 | 2499 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
6aa8b732 AK |
2500 | context->new_cr3 = paging_new_cr3; |
2501 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
2502 | context->gva_to_gpa = paging32_gva_to_gpa; |
2503 | context->free = paging_free; | |
c7addb90 | 2504 | context->prefetch_page = paging32_prefetch_page; |
e8bc217a | 2505 | context->sync_page = paging32_sync_page; |
a7052897 | 2506 | context->invlpg = paging32_invlpg; |
6aa8b732 AK |
2507 | context->root_level = PT32_ROOT_LEVEL; |
2508 | context->shadow_root_level = PT32E_ROOT_LEVEL; | |
17c3ba9d | 2509 | context->root_hpa = INVALID_PAGE; |
6aa8b732 AK |
2510 | return 0; |
2511 | } | |
2512 | ||
2513 | static int paging32E_init_context(struct kvm_vcpu *vcpu) | |
2514 | { | |
82725b20 | 2515 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
17ac10ad | 2516 | return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
2517 | } |
2518 | ||
fb72d167 JR |
2519 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
2520 | { | |
2521 | struct kvm_mmu *context = &vcpu->arch.mmu; | |
2522 | ||
2523 | context->new_cr3 = nonpaging_new_cr3; | |
2524 | context->page_fault = tdp_page_fault; | |
2525 | context->free = nonpaging_free; | |
2526 | context->prefetch_page = nonpaging_prefetch_page; | |
e8bc217a | 2527 | context->sync_page = nonpaging_sync_page; |
a7052897 | 2528 | context->invlpg = nonpaging_invlpg; |
67253af5 | 2529 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 JR |
2530 | context->root_hpa = INVALID_PAGE; |
2531 | ||
2532 | if (!is_paging(vcpu)) { | |
2533 | context->gva_to_gpa = nonpaging_gva_to_gpa; | |
2534 | context->root_level = 0; | |
2535 | } else if (is_long_mode(vcpu)) { | |
82725b20 | 2536 | reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL); |
fb72d167 JR |
2537 | context->gva_to_gpa = paging64_gva_to_gpa; |
2538 | context->root_level = PT64_ROOT_LEVEL; | |
2539 | } else if (is_pae(vcpu)) { | |
82725b20 | 2540 | reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL); |
fb72d167 JR |
2541 | context->gva_to_gpa = paging64_gva_to_gpa; |
2542 | context->root_level = PT32E_ROOT_LEVEL; | |
2543 | } else { | |
82725b20 | 2544 | reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL); |
fb72d167 JR |
2545 | context->gva_to_gpa = paging32_gva_to_gpa; |
2546 | context->root_level = PT32_ROOT_LEVEL; | |
2547 | } | |
2548 | ||
2549 | return 0; | |
2550 | } | |
2551 | ||
2552 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2553 | { |
a770f6f2 AK |
2554 | int r; |
2555 | ||
6aa8b732 | 2556 | ASSERT(vcpu); |
ad312c7c | 2557 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
2558 | |
2559 | if (!is_paging(vcpu)) | |
a770f6f2 | 2560 | r = nonpaging_init_context(vcpu); |
a9058ecd | 2561 | else if (is_long_mode(vcpu)) |
a770f6f2 | 2562 | r = paging64_init_context(vcpu); |
6aa8b732 | 2563 | else if (is_pae(vcpu)) |
a770f6f2 | 2564 | r = paging32E_init_context(vcpu); |
6aa8b732 | 2565 | else |
a770f6f2 AK |
2566 | r = paging32_init_context(vcpu); |
2567 | ||
5b7e0102 | 2568 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
3dbe1415 | 2569 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
a770f6f2 AK |
2570 | |
2571 | return r; | |
6aa8b732 AK |
2572 | } |
2573 | ||
fb72d167 JR |
2574 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
2575 | { | |
35149e21 AL |
2576 | vcpu->arch.update_pte.pfn = bad_pfn; |
2577 | ||
fb72d167 JR |
2578 | if (tdp_enabled) |
2579 | return init_kvm_tdp_mmu(vcpu); | |
2580 | else | |
2581 | return init_kvm_softmmu(vcpu); | |
2582 | } | |
2583 | ||
6aa8b732 AK |
2584 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
2585 | { | |
2586 | ASSERT(vcpu); | |
62ad0755 SY |
2587 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2588 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 2589 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
2590 | } |
2591 | ||
2592 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
2593 | { |
2594 | destroy_kvm_mmu(vcpu); | |
2595 | return init_kvm_mmu(vcpu); | |
2596 | } | |
8668a3c4 | 2597 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
2598 | |
2599 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 2600 | { |
714b93da AK |
2601 | int r; |
2602 | ||
e2dec939 | 2603 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
2604 | if (r) |
2605 | goto out; | |
8986ecc0 | 2606 | r = mmu_alloc_roots(vcpu); |
8facbbff | 2607 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 2608 | mmu_sync_roots(vcpu); |
aaee2c94 | 2609 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
2610 | if (r) |
2611 | goto out; | |
3662cb1c | 2612 | /* set_cr3() should ensure TLB has been flushed */ |
ad312c7c | 2613 | kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
2614 | out: |
2615 | return r; | |
6aa8b732 | 2616 | } |
17c3ba9d AK |
2617 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
2618 | ||
2619 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
2620 | { | |
2621 | mmu_free_roots(vcpu); | |
2622 | } | |
6aa8b732 | 2623 | |
09072daf | 2624 | static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2625 | struct kvm_mmu_page *sp, |
ac1b714e AK |
2626 | u64 *spte) |
2627 | { | |
2628 | u64 pte; | |
2629 | struct kvm_mmu_page *child; | |
2630 | ||
2631 | pte = *spte; | |
c7addb90 | 2632 | if (is_shadow_present_pte(pte)) { |
776e6633 | 2633 | if (is_last_spte(pte, sp->role.level)) |
be38d276 | 2634 | drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte); |
ac1b714e AK |
2635 | else { |
2636 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
90cb0529 | 2637 | mmu_page_remove_parent_pte(child, spte); |
ac1b714e AK |
2638 | } |
2639 | } | |
d555c333 | 2640 | __set_spte(spte, shadow_trap_nonpresent_pte); |
05da4558 MT |
2641 | if (is_large_pte(pte)) |
2642 | --vcpu->kvm->stat.lpages; | |
ac1b714e AK |
2643 | } |
2644 | ||
0028425f | 2645 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2646 | struct kvm_mmu_page *sp, |
0028425f | 2647 | u64 *spte, |
489f1d65 | 2648 | const void *new) |
0028425f | 2649 | { |
30945387 | 2650 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
2651 | ++vcpu->kvm->stat.mmu_pde_zapped; |
2652 | return; | |
30945387 | 2653 | } |
0028425f | 2654 | |
4cee5764 | 2655 | ++vcpu->kvm->stat.mmu_pte_updated; |
5b7e0102 | 2656 | if (!sp->role.cr4_pae) |
489f1d65 | 2657 | paging32_update_pte(vcpu, sp, spte, new); |
0028425f | 2658 | else |
489f1d65 | 2659 | paging64_update_pte(vcpu, sp, spte, new); |
0028425f AK |
2660 | } |
2661 | ||
79539cec AK |
2662 | static bool need_remote_flush(u64 old, u64 new) |
2663 | { | |
2664 | if (!is_shadow_present_pte(old)) | |
2665 | return false; | |
2666 | if (!is_shadow_present_pte(new)) | |
2667 | return true; | |
2668 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
2669 | return true; | |
2670 | old ^= PT64_NX_MASK; | |
2671 | new ^= PT64_NX_MASK; | |
2672 | return (old & ~new & PT64_PERM_MASK) != 0; | |
2673 | } | |
2674 | ||
0671a8e7 XG |
2675 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
2676 | bool remote_flush, bool local_flush) | |
79539cec | 2677 | { |
0671a8e7 XG |
2678 | if (zap_page) |
2679 | return; | |
2680 | ||
2681 | if (remote_flush) | |
79539cec | 2682 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 2683 | else if (local_flush) |
79539cec AK |
2684 | kvm_mmu_flush_tlb(vcpu); |
2685 | } | |
2686 | ||
12b7d28f AK |
2687 | static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu) |
2688 | { | |
ad312c7c | 2689 | u64 *spte = vcpu->arch.last_pte_updated; |
12b7d28f | 2690 | |
7b52345e | 2691 | return !!(spte && (*spte & shadow_accessed_mask)); |
12b7d28f AK |
2692 | } |
2693 | ||
d7824fff | 2694 | static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
72016f3a | 2695 | u64 gpte) |
d7824fff AK |
2696 | { |
2697 | gfn_t gfn; | |
35149e21 | 2698 | pfn_t pfn; |
d7824fff | 2699 | |
43a3795a | 2700 | if (!is_present_gpte(gpte)) |
d7824fff AK |
2701 | return; |
2702 | gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; | |
72dc67a6 | 2703 | |
e930bffe | 2704 | vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2705 | smp_rmb(); |
35149e21 | 2706 | pfn = gfn_to_pfn(vcpu->kvm, gfn); |
72dc67a6 | 2707 | |
35149e21 AL |
2708 | if (is_error_pfn(pfn)) { |
2709 | kvm_release_pfn_clean(pfn); | |
d196e343 AK |
2710 | return; |
2711 | } | |
d7824fff | 2712 | vcpu->arch.update_pte.gfn = gfn; |
35149e21 | 2713 | vcpu->arch.update_pte.pfn = pfn; |
d7824fff AK |
2714 | } |
2715 | ||
1b7fcd32 AK |
2716 | static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn) |
2717 | { | |
2718 | u64 *spte = vcpu->arch.last_pte_updated; | |
2719 | ||
2720 | if (spte | |
2721 | && vcpu->arch.last_pte_gfn == gfn | |
2722 | && shadow_accessed_mask | |
2723 | && !(*spte & shadow_accessed_mask) | |
2724 | && is_shadow_present_pte(*spte)) | |
2725 | set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte); | |
2726 | } | |
2727 | ||
09072daf | 2728 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
ad218f85 MT |
2729 | const u8 *new, int bytes, |
2730 | bool guest_initiated) | |
da4a00f0 | 2731 | { |
9b7a0325 | 2732 | gfn_t gfn = gpa >> PAGE_SHIFT; |
4db35314 | 2733 | struct kvm_mmu_page *sp; |
f41d335a | 2734 | struct hlist_node *node; |
d98ba053 | 2735 | LIST_HEAD(invalid_list); |
489f1d65 | 2736 | u64 entry, gentry; |
9b7a0325 | 2737 | u64 *spte; |
9b7a0325 | 2738 | unsigned offset = offset_in_page(gpa); |
0e7bc4b9 | 2739 | unsigned pte_size; |
9b7a0325 | 2740 | unsigned page_offset; |
0e7bc4b9 | 2741 | unsigned misaligned; |
fce0657f | 2742 | unsigned quadrant; |
9b7a0325 | 2743 | int level; |
86a5ba02 | 2744 | int flooded = 0; |
ac1b714e | 2745 | int npte; |
489f1d65 | 2746 | int r; |
08e850c6 | 2747 | int invlpg_counter; |
0671a8e7 XG |
2748 | bool remote_flush, local_flush, zap_page; |
2749 | ||
2750 | zap_page = remote_flush = local_flush = false; | |
9b7a0325 | 2751 | |
b8688d51 | 2752 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); |
72016f3a | 2753 | |
08e850c6 | 2754 | invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter); |
72016f3a AK |
2755 | |
2756 | /* | |
2757 | * Assume that the pte write on a page table of the same type | |
2758 | * as the current vcpu paging mode. This is nearly always true | |
2759 | * (might be false while changing modes). Note it is verified later | |
2760 | * by update_pte(). | |
2761 | */ | |
08e850c6 | 2762 | if ((is_pae(vcpu) && bytes == 4) || !new) { |
72016f3a | 2763 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
08e850c6 AK |
2764 | if (is_pae(vcpu)) { |
2765 | gpa &= ~(gpa_t)7; | |
2766 | bytes = 8; | |
2767 | } | |
2768 | r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8)); | |
72016f3a AK |
2769 | if (r) |
2770 | gentry = 0; | |
08e850c6 AK |
2771 | new = (const u8 *)&gentry; |
2772 | } | |
2773 | ||
2774 | switch (bytes) { | |
2775 | case 4: | |
2776 | gentry = *(const u32 *)new; | |
2777 | break; | |
2778 | case 8: | |
2779 | gentry = *(const u64 *)new; | |
2780 | break; | |
2781 | default: | |
2782 | gentry = 0; | |
2783 | break; | |
72016f3a AK |
2784 | } |
2785 | ||
2786 | mmu_guess_page_from_pte_write(vcpu, gpa, gentry); | |
aaee2c94 | 2787 | spin_lock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
2788 | if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter) |
2789 | gentry = 0; | |
1b7fcd32 | 2790 | kvm_mmu_access_page(vcpu, gfn); |
eb787d10 | 2791 | kvm_mmu_free_some_pages(vcpu); |
4cee5764 | 2792 | ++vcpu->kvm->stat.mmu_pte_write; |
c7addb90 | 2793 | kvm_mmu_audit(vcpu, "pre pte write"); |
ad218f85 MT |
2794 | if (guest_initiated) { |
2795 | if (gfn == vcpu->arch.last_pt_write_gfn | |
2796 | && !last_updated_pte_accessed(vcpu)) { | |
2797 | ++vcpu->arch.last_pt_write_count; | |
2798 | if (vcpu->arch.last_pt_write_count >= 3) | |
2799 | flooded = 1; | |
2800 | } else { | |
2801 | vcpu->arch.last_pt_write_gfn = gfn; | |
2802 | vcpu->arch.last_pt_write_count = 1; | |
2803 | vcpu->arch.last_pte_updated = NULL; | |
2804 | } | |
86a5ba02 | 2805 | } |
3246af0e | 2806 | |
f41d335a | 2807 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
5b7e0102 | 2808 | pte_size = sp->role.cr4_pae ? 8 : 4; |
0e7bc4b9 | 2809 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
e925c5ba | 2810 | misaligned |= bytes < 4; |
86a5ba02 | 2811 | if (misaligned || flooded) { |
0e7bc4b9 AK |
2812 | /* |
2813 | * Misaligned accesses are too much trouble to fix | |
2814 | * up; also, they usually indicate a page is not used | |
2815 | * as a page table. | |
86a5ba02 AK |
2816 | * |
2817 | * If we're seeing too many writes to a page, | |
2818 | * it may no longer be a page table, or we may be | |
2819 | * forking, in which case it is better to unmap the | |
2820 | * page. | |
0e7bc4b9 AK |
2821 | */ |
2822 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4db35314 | 2823 | gpa, bytes, sp->role.word); |
0671a8e7 | 2824 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 2825 | &invalid_list); |
4cee5764 | 2826 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
2827 | continue; |
2828 | } | |
9b7a0325 | 2829 | page_offset = offset; |
4db35314 | 2830 | level = sp->role.level; |
ac1b714e | 2831 | npte = 1; |
5b7e0102 | 2832 | if (!sp->role.cr4_pae) { |
ac1b714e AK |
2833 | page_offset <<= 1; /* 32->64 */ |
2834 | /* | |
2835 | * A 32-bit pde maps 4MB while the shadow pdes map | |
2836 | * only 2MB. So we need to double the offset again | |
2837 | * and zap two pdes instead of one. | |
2838 | */ | |
2839 | if (level == PT32_ROOT_LEVEL) { | |
6b8d0f9b | 2840 | page_offset &= ~7; /* kill rounding error */ |
ac1b714e AK |
2841 | page_offset <<= 1; |
2842 | npte = 2; | |
2843 | } | |
fce0657f | 2844 | quadrant = page_offset >> PAGE_SHIFT; |
9b7a0325 | 2845 | page_offset &= ~PAGE_MASK; |
4db35314 | 2846 | if (quadrant != sp->role.quadrant) |
fce0657f | 2847 | continue; |
9b7a0325 | 2848 | } |
0671a8e7 | 2849 | local_flush = true; |
4db35314 | 2850 | spte = &sp->spt[page_offset / sizeof(*spte)]; |
ac1b714e | 2851 | while (npte--) { |
79539cec | 2852 | entry = *spte; |
4db35314 | 2853 | mmu_pte_write_zap_pte(vcpu, sp, spte); |
72016f3a AK |
2854 | if (gentry) |
2855 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); | |
0671a8e7 XG |
2856 | if (!remote_flush && need_remote_flush(entry, *spte)) |
2857 | remote_flush = true; | |
ac1b714e | 2858 | ++spte; |
9b7a0325 | 2859 | } |
9b7a0325 | 2860 | } |
0671a8e7 | 2861 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 2862 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
c7addb90 | 2863 | kvm_mmu_audit(vcpu, "post pte write"); |
aaee2c94 | 2864 | spin_unlock(&vcpu->kvm->mmu_lock); |
35149e21 AL |
2865 | if (!is_error_pfn(vcpu->arch.update_pte.pfn)) { |
2866 | kvm_release_pfn_clean(vcpu->arch.update_pte.pfn); | |
2867 | vcpu->arch.update_pte.pfn = bad_pfn; | |
d7824fff | 2868 | } |
da4a00f0 AK |
2869 | } |
2870 | ||
a436036b AK |
2871 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
2872 | { | |
10589a46 MT |
2873 | gpa_t gpa; |
2874 | int r; | |
a436036b | 2875 | |
60f24784 AK |
2876 | if (tdp_enabled) |
2877 | return 0; | |
2878 | ||
1871c602 | 2879 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 2880 | |
aaee2c94 | 2881 | spin_lock(&vcpu->kvm->mmu_lock); |
10589a46 | 2882 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
aaee2c94 | 2883 | spin_unlock(&vcpu->kvm->mmu_lock); |
10589a46 | 2884 | return r; |
a436036b | 2885 | } |
577bdc49 | 2886 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 2887 | |
22d95b12 | 2888 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 2889 | { |
103ad25a | 2890 | int free_pages; |
d98ba053 | 2891 | LIST_HEAD(invalid_list); |
103ad25a XG |
2892 | |
2893 | free_pages = vcpu->kvm->arch.n_free_mmu_pages; | |
2894 | while (free_pages < KVM_REFILL_PAGES && | |
3b80fffe | 2895 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 2896 | struct kvm_mmu_page *sp; |
ebeace86 | 2897 | |
f05e70ac | 2898 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 2899 | struct kvm_mmu_page, link); |
d98ba053 XG |
2900 | free_pages += kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2901 | &invalid_list); | |
4cee5764 | 2902 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 2903 | } |
d98ba053 | 2904 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 2905 | } |
ebeace86 | 2906 | |
3067714c AK |
2907 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code) |
2908 | { | |
2909 | int r; | |
2910 | enum emulation_result er; | |
2911 | ||
ad312c7c | 2912 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code); |
3067714c AK |
2913 | if (r < 0) |
2914 | goto out; | |
2915 | ||
2916 | if (!r) { | |
2917 | r = 1; | |
2918 | goto out; | |
2919 | } | |
2920 | ||
b733bfb5 AK |
2921 | r = mmu_topup_memory_caches(vcpu); |
2922 | if (r) | |
2923 | goto out; | |
2924 | ||
851ba692 | 2925 | er = emulate_instruction(vcpu, cr2, error_code, 0); |
3067714c AK |
2926 | |
2927 | switch (er) { | |
2928 | case EMULATE_DONE: | |
2929 | return 1; | |
2930 | case EMULATE_DO_MMIO: | |
2931 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 2932 | /* fall through */ |
3067714c | 2933 | case EMULATE_FAIL: |
3f5d18a9 | 2934 | return 0; |
3067714c AK |
2935 | default: |
2936 | BUG(); | |
2937 | } | |
2938 | out: | |
3067714c AK |
2939 | return r; |
2940 | } | |
2941 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
2942 | ||
a7052897 MT |
2943 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
2944 | { | |
a7052897 | 2945 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
2946 | kvm_mmu_flush_tlb(vcpu); |
2947 | ++vcpu->stat.invlpg; | |
2948 | } | |
2949 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
2950 | ||
18552672 JR |
2951 | void kvm_enable_tdp(void) |
2952 | { | |
2953 | tdp_enabled = true; | |
2954 | } | |
2955 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
2956 | ||
5f4cb662 JR |
2957 | void kvm_disable_tdp(void) |
2958 | { | |
2959 | tdp_enabled = false; | |
2960 | } | |
2961 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
2962 | ||
6aa8b732 AK |
2963 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
2964 | { | |
ad312c7c | 2965 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
6aa8b732 AK |
2966 | } |
2967 | ||
2968 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
2969 | { | |
17ac10ad | 2970 | struct page *page; |
6aa8b732 AK |
2971 | int i; |
2972 | ||
2973 | ASSERT(vcpu); | |
2974 | ||
17ac10ad AK |
2975 | /* |
2976 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
2977 | * Therefore we need to allocate shadow page tables in the first | |
2978 | * 4GB of memory, which happens to fit the DMA32 zone. | |
2979 | */ | |
2980 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
2981 | if (!page) | |
d7fa6ab2 WY |
2982 | return -ENOMEM; |
2983 | ||
ad312c7c | 2984 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 2985 | for (i = 0; i < 4; ++i) |
ad312c7c | 2986 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2987 | |
6aa8b732 | 2988 | return 0; |
6aa8b732 AK |
2989 | } |
2990 | ||
8018c27b | 2991 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 2992 | { |
6aa8b732 | 2993 | ASSERT(vcpu); |
ad312c7c | 2994 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 2995 | |
8018c27b IM |
2996 | return alloc_mmu_pages(vcpu); |
2997 | } | |
6aa8b732 | 2998 | |
8018c27b IM |
2999 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
3000 | { | |
3001 | ASSERT(vcpu); | |
ad312c7c | 3002 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 3003 | |
8018c27b | 3004 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
3005 | } |
3006 | ||
3007 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) | |
3008 | { | |
3009 | ASSERT(vcpu); | |
3010 | ||
3011 | destroy_kvm_mmu(vcpu); | |
3012 | free_mmu_pages(vcpu); | |
714b93da | 3013 | mmu_free_memory_caches(vcpu); |
6aa8b732 AK |
3014 | } |
3015 | ||
90cb0529 | 3016 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 3017 | { |
4db35314 | 3018 | struct kvm_mmu_page *sp; |
6aa8b732 | 3019 | |
f05e70ac | 3020 | list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) { |
6aa8b732 AK |
3021 | int i; |
3022 | u64 *pt; | |
3023 | ||
291f26bc | 3024 | if (!test_bit(slot, sp->slot_bitmap)) |
6aa8b732 AK |
3025 | continue; |
3026 | ||
4db35314 | 3027 | pt = sp->spt; |
6aa8b732 AK |
3028 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
3029 | /* avoid RMW */ | |
01c168ac | 3030 | if (is_writable_pte(pt[i])) |
6aa8b732 | 3031 | pt[i] &= ~PT_WRITABLE_MASK; |
6aa8b732 | 3032 | } |
171d595d | 3033 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 3034 | } |
37a7d8b0 | 3035 | |
90cb0529 | 3036 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 3037 | { |
4db35314 | 3038 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 3039 | LIST_HEAD(invalid_list); |
e0fa826f | 3040 | |
aaee2c94 | 3041 | spin_lock(&kvm->mmu_lock); |
3246af0e | 3042 | restart: |
f05e70ac | 3043 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 3044 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
3045 | goto restart; |
3046 | ||
d98ba053 | 3047 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 3048 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
3049 | } |
3050 | ||
d98ba053 XG |
3051 | static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
3052 | struct list_head *invalid_list) | |
3ee16c81 IE |
3053 | { |
3054 | struct kvm_mmu_page *page; | |
3055 | ||
3056 | page = container_of(kvm->arch.active_mmu_pages.prev, | |
3057 | struct kvm_mmu_page, link); | |
d98ba053 | 3058 | return kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
3059 | } |
3060 | ||
7f8275d0 | 3061 | static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
3ee16c81 IE |
3062 | { |
3063 | struct kvm *kvm; | |
3064 | struct kvm *kvm_freed = NULL; | |
3065 | int cache_count = 0; | |
3066 | ||
3067 | spin_lock(&kvm_lock); | |
3068 | ||
3069 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
d35b8dd9 | 3070 | int npages, idx, freed_pages; |
d98ba053 | 3071 | LIST_HEAD(invalid_list); |
3ee16c81 | 3072 | |
f656ce01 | 3073 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 IE |
3074 | spin_lock(&kvm->mmu_lock); |
3075 | npages = kvm->arch.n_alloc_mmu_pages - | |
3076 | kvm->arch.n_free_mmu_pages; | |
3077 | cache_count += npages; | |
3078 | if (!kvm_freed && nr_to_scan > 0 && npages > 0) { | |
d98ba053 XG |
3079 | freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm, |
3080 | &invalid_list); | |
d35b8dd9 | 3081 | cache_count -= freed_pages; |
3ee16c81 IE |
3082 | kvm_freed = kvm; |
3083 | } | |
3084 | nr_to_scan--; | |
3085 | ||
d98ba053 | 3086 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
3ee16c81 | 3087 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 3088 | srcu_read_unlock(&kvm->srcu, idx); |
3ee16c81 IE |
3089 | } |
3090 | if (kvm_freed) | |
3091 | list_move_tail(&kvm_freed->vm_list, &vm_list); | |
3092 | ||
3093 | spin_unlock(&kvm_lock); | |
3094 | ||
3095 | return cache_count; | |
3096 | } | |
3097 | ||
3098 | static struct shrinker mmu_shrinker = { | |
3099 | .shrink = mmu_shrink, | |
3100 | .seeks = DEFAULT_SEEKS * 10, | |
3101 | }; | |
3102 | ||
2ddfd20e | 3103 | static void mmu_destroy_caches(void) |
b5a33a75 AK |
3104 | { |
3105 | if (pte_chain_cache) | |
3106 | kmem_cache_destroy(pte_chain_cache); | |
3107 | if (rmap_desc_cache) | |
3108 | kmem_cache_destroy(rmap_desc_cache); | |
d3d25b04 AK |
3109 | if (mmu_page_header_cache) |
3110 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
3111 | } |
3112 | ||
3ee16c81 IE |
3113 | void kvm_mmu_module_exit(void) |
3114 | { | |
3115 | mmu_destroy_caches(); | |
3116 | unregister_shrinker(&mmu_shrinker); | |
3117 | } | |
3118 | ||
b5a33a75 AK |
3119 | int kvm_mmu_module_init(void) |
3120 | { | |
3121 | pte_chain_cache = kmem_cache_create("kvm_pte_chain", | |
3122 | sizeof(struct kvm_pte_chain), | |
20c2df83 | 3123 | 0, 0, NULL); |
b5a33a75 AK |
3124 | if (!pte_chain_cache) |
3125 | goto nomem; | |
3126 | rmap_desc_cache = kmem_cache_create("kvm_rmap_desc", | |
3127 | sizeof(struct kvm_rmap_desc), | |
20c2df83 | 3128 | 0, 0, NULL); |
b5a33a75 AK |
3129 | if (!rmap_desc_cache) |
3130 | goto nomem; | |
3131 | ||
d3d25b04 AK |
3132 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
3133 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 3134 | 0, 0, NULL); |
d3d25b04 AK |
3135 | if (!mmu_page_header_cache) |
3136 | goto nomem; | |
3137 | ||
3ee16c81 IE |
3138 | register_shrinker(&mmu_shrinker); |
3139 | ||
b5a33a75 AK |
3140 | return 0; |
3141 | ||
3142 | nomem: | |
3ee16c81 | 3143 | mmu_destroy_caches(); |
b5a33a75 AK |
3144 | return -ENOMEM; |
3145 | } | |
3146 | ||
3ad82a7e ZX |
3147 | /* |
3148 | * Caculate mmu pages needed for kvm. | |
3149 | */ | |
3150 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
3151 | { | |
3152 | int i; | |
3153 | unsigned int nr_mmu_pages; | |
3154 | unsigned int nr_pages = 0; | |
bc6678a3 | 3155 | struct kvm_memslots *slots; |
3ad82a7e | 3156 | |
90d83dc3 LJ |
3157 | slots = kvm_memslots(kvm); |
3158 | ||
bc6678a3 MT |
3159 | for (i = 0; i < slots->nmemslots; i++) |
3160 | nr_pages += slots->memslots[i].npages; | |
3ad82a7e ZX |
3161 | |
3162 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
3163 | nr_mmu_pages = max(nr_mmu_pages, | |
3164 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
3165 | ||
3166 | return nr_mmu_pages; | |
3167 | } | |
3168 | ||
2f333bcb MT |
3169 | static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer, |
3170 | unsigned len) | |
3171 | { | |
3172 | if (len > buffer->len) | |
3173 | return NULL; | |
3174 | return buffer->ptr; | |
3175 | } | |
3176 | ||
3177 | static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer, | |
3178 | unsigned len) | |
3179 | { | |
3180 | void *ret; | |
3181 | ||
3182 | ret = pv_mmu_peek_buffer(buffer, len); | |
3183 | if (!ret) | |
3184 | return ret; | |
3185 | buffer->ptr += len; | |
3186 | buffer->len -= len; | |
3187 | buffer->processed += len; | |
3188 | return ret; | |
3189 | } | |
3190 | ||
3191 | static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu, | |
3192 | gpa_t addr, gpa_t value) | |
3193 | { | |
3194 | int bytes = 8; | |
3195 | int r; | |
3196 | ||
3197 | if (!is_long_mode(vcpu) && !is_pae(vcpu)) | |
3198 | bytes = 4; | |
3199 | ||
3200 | r = mmu_topup_memory_caches(vcpu); | |
3201 | if (r) | |
3202 | return r; | |
3203 | ||
3200f405 | 3204 | if (!emulator_write_phys(vcpu, addr, &value, bytes)) |
2f333bcb MT |
3205 | return -EFAULT; |
3206 | ||
3207 | return 1; | |
3208 | } | |
3209 | ||
3210 | static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu) | |
3211 | { | |
2390218b | 3212 | (void)kvm_set_cr3(vcpu, vcpu->arch.cr3); |
2f333bcb MT |
3213 | return 1; |
3214 | } | |
3215 | ||
3216 | static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr) | |
3217 | { | |
3218 | spin_lock(&vcpu->kvm->mmu_lock); | |
3219 | mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT); | |
3220 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3221 | return 1; | |
3222 | } | |
3223 | ||
3224 | static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu, | |
3225 | struct kvm_pv_mmu_op_buffer *buffer) | |
3226 | { | |
3227 | struct kvm_mmu_op_header *header; | |
3228 | ||
3229 | header = pv_mmu_peek_buffer(buffer, sizeof *header); | |
3230 | if (!header) | |
3231 | return 0; | |
3232 | switch (header->op) { | |
3233 | case KVM_MMU_OP_WRITE_PTE: { | |
3234 | struct kvm_mmu_op_write_pte *wpte; | |
3235 | ||
3236 | wpte = pv_mmu_read_buffer(buffer, sizeof *wpte); | |
3237 | if (!wpte) | |
3238 | return 0; | |
3239 | return kvm_pv_mmu_write(vcpu, wpte->pte_phys, | |
3240 | wpte->pte_val); | |
3241 | } | |
3242 | case KVM_MMU_OP_FLUSH_TLB: { | |
3243 | struct kvm_mmu_op_flush_tlb *ftlb; | |
3244 | ||
3245 | ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb); | |
3246 | if (!ftlb) | |
3247 | return 0; | |
3248 | return kvm_pv_mmu_flush_tlb(vcpu); | |
3249 | } | |
3250 | case KVM_MMU_OP_RELEASE_PT: { | |
3251 | struct kvm_mmu_op_release_pt *rpt; | |
3252 | ||
3253 | rpt = pv_mmu_read_buffer(buffer, sizeof *rpt); | |
3254 | if (!rpt) | |
3255 | return 0; | |
3256 | return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys); | |
3257 | } | |
3258 | default: return 0; | |
3259 | } | |
3260 | } | |
3261 | ||
3262 | int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes, | |
3263 | gpa_t addr, unsigned long *ret) | |
3264 | { | |
3265 | int r; | |
6ad18fba | 3266 | struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer; |
2f333bcb | 3267 | |
6ad18fba DH |
3268 | buffer->ptr = buffer->buf; |
3269 | buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf); | |
3270 | buffer->processed = 0; | |
2f333bcb | 3271 | |
6ad18fba | 3272 | r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len); |
2f333bcb MT |
3273 | if (r) |
3274 | goto out; | |
3275 | ||
6ad18fba DH |
3276 | while (buffer->len) { |
3277 | r = kvm_pv_mmu_op_one(vcpu, buffer); | |
2f333bcb MT |
3278 | if (r < 0) |
3279 | goto out; | |
3280 | if (r == 0) | |
3281 | break; | |
3282 | } | |
3283 | ||
3284 | r = 1; | |
3285 | out: | |
6ad18fba | 3286 | *ret = buffer->processed; |
2f333bcb MT |
3287 | return r; |
3288 | } | |
3289 | ||
94d8b056 MT |
3290 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
3291 | { | |
3292 | struct kvm_shadow_walk_iterator iterator; | |
3293 | int nr_sptes = 0; | |
3294 | ||
3295 | spin_lock(&vcpu->kvm->mmu_lock); | |
3296 | for_each_shadow_entry(vcpu, addr, iterator) { | |
3297 | sptes[iterator.level-1] = *iterator.sptep; | |
3298 | nr_sptes++; | |
3299 | if (!is_shadow_present_pte(*iterator.sptep)) | |
3300 | break; | |
3301 | } | |
3302 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3303 | ||
3304 | return nr_sptes; | |
3305 | } | |
3306 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
3307 | ||
37a7d8b0 AK |
3308 | #ifdef AUDIT |
3309 | ||
3310 | static const char *audit_msg; | |
3311 | ||
3312 | static gva_t canonicalize(gva_t gva) | |
3313 | { | |
3314 | #ifdef CONFIG_X86_64 | |
3315 | gva = (long long)(gva << 16) >> 16; | |
3316 | #endif | |
3317 | return gva; | |
3318 | } | |
3319 | ||
08a3732b | 3320 | |
805d32de | 3321 | typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep); |
08a3732b MT |
3322 | |
3323 | static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp, | |
3324 | inspect_spte_fn fn) | |
3325 | { | |
3326 | int i; | |
3327 | ||
3328 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3329 | u64 ent = sp->spt[i]; | |
3330 | ||
3331 | if (is_shadow_present_pte(ent)) { | |
2920d728 | 3332 | if (!is_last_spte(ent, sp->role.level)) { |
08a3732b MT |
3333 | struct kvm_mmu_page *child; |
3334 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
3335 | __mmu_spte_walk(kvm, child, fn); | |
2920d728 | 3336 | } else |
805d32de | 3337 | fn(kvm, &sp->spt[i]); |
08a3732b MT |
3338 | } |
3339 | } | |
3340 | } | |
3341 | ||
3342 | static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn) | |
3343 | { | |
3344 | int i; | |
3345 | struct kvm_mmu_page *sp; | |
3346 | ||
3347 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3348 | return; | |
3349 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3350 | hpa_t root = vcpu->arch.mmu.root_hpa; | |
3351 | sp = page_header(root); | |
3352 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3353 | return; | |
3354 | } | |
3355 | for (i = 0; i < 4; ++i) { | |
3356 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3357 | ||
3358 | if (root && VALID_PAGE(root)) { | |
3359 | root &= PT64_BASE_ADDR_MASK; | |
3360 | sp = page_header(root); | |
3361 | __mmu_spte_walk(vcpu->kvm, sp, fn); | |
3362 | } | |
3363 | } | |
3364 | return; | |
3365 | } | |
3366 | ||
37a7d8b0 AK |
3367 | static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte, |
3368 | gva_t va, int level) | |
3369 | { | |
3370 | u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK); | |
3371 | int i; | |
3372 | gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1)); | |
3373 | ||
3374 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) { | |
3375 | u64 ent = pt[i]; | |
3376 | ||
c7addb90 | 3377 | if (ent == shadow_trap_nonpresent_pte) |
37a7d8b0 AK |
3378 | continue; |
3379 | ||
3380 | va = canonicalize(va); | |
2920d728 MT |
3381 | if (is_shadow_present_pte(ent) && !is_last_spte(ent, level)) |
3382 | audit_mappings_page(vcpu, ent, va, level - 1); | |
3383 | else { | |
1871c602 | 3384 | gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL); |
34382539 JK |
3385 | gfn_t gfn = gpa >> PAGE_SHIFT; |
3386 | pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn); | |
3387 | hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT; | |
37a7d8b0 | 3388 | |
2aaf65e8 MT |
3389 | if (is_error_pfn(pfn)) { |
3390 | kvm_release_pfn_clean(pfn); | |
3391 | continue; | |
3392 | } | |
3393 | ||
c7addb90 | 3394 | if (is_shadow_present_pte(ent) |
37a7d8b0 | 3395 | && (ent & PT64_BASE_ADDR_MASK) != hpa) |
c7addb90 AK |
3396 | printk(KERN_ERR "xx audit error: (%s) levels %d" |
3397 | " gva %lx gpa %llx hpa %llx ent %llx %d\n", | |
ad312c7c | 3398 | audit_msg, vcpu->arch.mmu.root_level, |
d77c26fc MD |
3399 | va, gpa, hpa, ent, |
3400 | is_shadow_present_pte(ent)); | |
c7addb90 AK |
3401 | else if (ent == shadow_notrap_nonpresent_pte |
3402 | && !is_error_hpa(hpa)) | |
3403 | printk(KERN_ERR "audit: (%s) notrap shadow," | |
3404 | " valid guest gva %lx\n", audit_msg, va); | |
35149e21 | 3405 | kvm_release_pfn_clean(pfn); |
c7addb90 | 3406 | |
37a7d8b0 AK |
3407 | } |
3408 | } | |
3409 | } | |
3410 | ||
3411 | static void audit_mappings(struct kvm_vcpu *vcpu) | |
3412 | { | |
1ea252af | 3413 | unsigned i; |
37a7d8b0 | 3414 | |
ad312c7c ZX |
3415 | if (vcpu->arch.mmu.root_level == 4) |
3416 | audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4); | |
37a7d8b0 AK |
3417 | else |
3418 | for (i = 0; i < 4; ++i) | |
ad312c7c | 3419 | if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK) |
37a7d8b0 | 3420 | audit_mappings_page(vcpu, |
ad312c7c | 3421 | vcpu->arch.mmu.pae_root[i], |
37a7d8b0 AK |
3422 | i << 30, |
3423 | 2); | |
3424 | } | |
3425 | ||
3426 | static int count_rmaps(struct kvm_vcpu *vcpu) | |
3427 | { | |
805d32de XG |
3428 | struct kvm *kvm = vcpu->kvm; |
3429 | struct kvm_memslots *slots; | |
37a7d8b0 | 3430 | int nmaps = 0; |
bc6678a3 | 3431 | int i, j, k, idx; |
37a7d8b0 | 3432 | |
bc6678a3 | 3433 | idx = srcu_read_lock(&kvm->srcu); |
90d83dc3 | 3434 | slots = kvm_memslots(kvm); |
37a7d8b0 | 3435 | for (i = 0; i < KVM_MEMORY_SLOTS; ++i) { |
bc6678a3 | 3436 | struct kvm_memory_slot *m = &slots->memslots[i]; |
37a7d8b0 AK |
3437 | struct kvm_rmap_desc *d; |
3438 | ||
3439 | for (j = 0; j < m->npages; ++j) { | |
290fc38d | 3440 | unsigned long *rmapp = &m->rmap[j]; |
37a7d8b0 | 3441 | |
290fc38d | 3442 | if (!*rmapp) |
37a7d8b0 | 3443 | continue; |
290fc38d | 3444 | if (!(*rmapp & 1)) { |
37a7d8b0 AK |
3445 | ++nmaps; |
3446 | continue; | |
3447 | } | |
290fc38d | 3448 | d = (struct kvm_rmap_desc *)(*rmapp & ~1ul); |
37a7d8b0 AK |
3449 | while (d) { |
3450 | for (k = 0; k < RMAP_EXT; ++k) | |
d555c333 | 3451 | if (d->sptes[k]) |
37a7d8b0 AK |
3452 | ++nmaps; |
3453 | else | |
3454 | break; | |
3455 | d = d->more; | |
3456 | } | |
3457 | } | |
3458 | } | |
bc6678a3 | 3459 | srcu_read_unlock(&kvm->srcu, idx); |
37a7d8b0 AK |
3460 | return nmaps; |
3461 | } | |
3462 | ||
805d32de | 3463 | void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep) |
08a3732b MT |
3464 | { |
3465 | unsigned long *rmapp; | |
3466 | struct kvm_mmu_page *rev_sp; | |
3467 | gfn_t gfn; | |
3468 | ||
01c168ac | 3469 | if (is_writable_pte(*sptep)) { |
08a3732b | 3470 | rev_sp = page_header(__pa(sptep)); |
2032a93d | 3471 | gfn = kvm_mmu_page_get_gfn(rev_sp, sptep - rev_sp->spt); |
08a3732b MT |
3472 | |
3473 | if (!gfn_to_memslot(kvm, gfn)) { | |
3474 | if (!printk_ratelimit()) | |
3475 | return; | |
3476 | printk(KERN_ERR "%s: no memslot for gfn %ld\n", | |
3477 | audit_msg, gfn); | |
3478 | printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n", | |
805d32de | 3479 | audit_msg, (long int)(sptep - rev_sp->spt), |
08a3732b MT |
3480 | rev_sp->gfn); |
3481 | dump_stack(); | |
3482 | return; | |
3483 | } | |
3484 | ||
2032a93d | 3485 | rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level); |
08a3732b MT |
3486 | if (!*rmapp) { |
3487 | if (!printk_ratelimit()) | |
3488 | return; | |
3489 | printk(KERN_ERR "%s: no rmap for writable spte %llx\n", | |
3490 | audit_msg, *sptep); | |
3491 | dump_stack(); | |
3492 | } | |
3493 | } | |
3494 | ||
3495 | } | |
3496 | ||
3497 | void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu) | |
3498 | { | |
3499 | mmu_spte_walk(vcpu, inspect_spte_has_rmap); | |
3500 | } | |
3501 | ||
3502 | static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu) | |
37a7d8b0 | 3503 | { |
4db35314 | 3504 | struct kvm_mmu_page *sp; |
37a7d8b0 AK |
3505 | int i; |
3506 | ||
f05e70ac | 3507 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
4db35314 | 3508 | u64 *pt = sp->spt; |
37a7d8b0 | 3509 | |
4db35314 | 3510 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) |
37a7d8b0 AK |
3511 | continue; |
3512 | ||
3513 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) { | |
3514 | u64 ent = pt[i]; | |
3515 | ||
3516 | if (!(ent & PT_PRESENT_MASK)) | |
3517 | continue; | |
01c168ac | 3518 | if (!is_writable_pte(ent)) |
37a7d8b0 | 3519 | continue; |
805d32de | 3520 | inspect_spte_has_rmap(vcpu->kvm, &pt[i]); |
37a7d8b0 AK |
3521 | } |
3522 | } | |
08a3732b | 3523 | return; |
37a7d8b0 AK |
3524 | } |
3525 | ||
3526 | static void audit_rmap(struct kvm_vcpu *vcpu) | |
3527 | { | |
08a3732b MT |
3528 | check_writable_mappings_rmap(vcpu); |
3529 | count_rmaps(vcpu); | |
37a7d8b0 AK |
3530 | } |
3531 | ||
3532 | static void audit_write_protection(struct kvm_vcpu *vcpu) | |
3533 | { | |
4db35314 | 3534 | struct kvm_mmu_page *sp; |
290fc38d IE |
3535 | struct kvm_memory_slot *slot; |
3536 | unsigned long *rmapp; | |
e58b0f9e | 3537 | u64 *spte; |
290fc38d | 3538 | gfn_t gfn; |
37a7d8b0 | 3539 | |
f05e70ac | 3540 | list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) { |
f6e2c02b | 3541 | if (sp->role.direct) |
37a7d8b0 | 3542 | continue; |
e58b0f9e MT |
3543 | if (sp->unsync) |
3544 | continue; | |
37a7d8b0 | 3545 | |
a1f4d395 | 3546 | slot = gfn_to_memslot(vcpu->kvm, sp->gfn); |
290fc38d | 3547 | rmapp = &slot->rmap[gfn - slot->base_gfn]; |
e58b0f9e MT |
3548 | |
3549 | spte = rmap_next(vcpu->kvm, rmapp, NULL); | |
3550 | while (spte) { | |
01c168ac | 3551 | if (is_writable_pte(*spte)) |
e58b0f9e MT |
3552 | printk(KERN_ERR "%s: (%s) shadow page has " |
3553 | "writable mappings: gfn %lx role %x\n", | |
b8688d51 | 3554 | __func__, audit_msg, sp->gfn, |
4db35314 | 3555 | sp->role.word); |
e58b0f9e MT |
3556 | spte = rmap_next(vcpu->kvm, rmapp, spte); |
3557 | } | |
37a7d8b0 AK |
3558 | } |
3559 | } | |
3560 | ||
3561 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) | |
3562 | { | |
3563 | int olddbg = dbg; | |
3564 | ||
3565 | dbg = 0; | |
3566 | audit_msg = msg; | |
3567 | audit_rmap(vcpu); | |
3568 | audit_write_protection(vcpu); | |
2aaf65e8 MT |
3569 | if (strcmp("pre pte write", audit_msg) != 0) |
3570 | audit_mappings(vcpu); | |
08a3732b | 3571 | audit_writable_sptes_have_rmaps(vcpu); |
37a7d8b0 AK |
3572 | dbg = olddbg; |
3573 | } | |
3574 | ||
3575 | #endif |