Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
00763e41 | 93 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
53c07b18 XG |
156 | struct pte_list_desc { |
157 | u64 *sptes[PTE_LIST_EXT]; | |
158 | struct pte_list_desc *more; | |
cd4a4e53 AK |
159 | }; |
160 | ||
2d11123a AK |
161 | struct kvm_shadow_walk_iterator { |
162 | u64 addr; | |
163 | hpa_t shadow_addr; | |
2d11123a | 164 | u64 *sptep; |
dd3bfd59 | 165 | int level; |
2d11123a AK |
166 | unsigned index; |
167 | }; | |
168 | ||
169 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
170 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
171 | shadow_walk_okay(&(_walker)); \ | |
172 | shadow_walk_next(&(_walker))) | |
173 | ||
c2a2ac2b XG |
174 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)) && \ | |
177 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
178 | __shadow_walk_next(&(_walker), spte)) | |
179 | ||
53c07b18 | 180 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 181 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 182 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 183 | |
7b52345e SY |
184 | static u64 __read_mostly shadow_nx_mask; |
185 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
186 | static u64 __read_mostly shadow_user_mask; | |
187 | static u64 __read_mostly shadow_accessed_mask; | |
188 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
189 | static u64 __read_mostly shadow_mmio_mask; |
190 | ||
191 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 192 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
193 | |
194 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
195 | { | |
196 | shadow_mmio_mask = mmio_mask; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
199 | ||
200 | static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access) | |
201 | { | |
95b0430d TY |
202 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); |
203 | ||
ce88decf XG |
204 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
205 | ||
95b0430d | 206 | sp->mmio_cached = true; |
4f022648 | 207 | trace_mark_mmio_spte(sptep, gfn, access); |
ce88decf XG |
208 | mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT); |
209 | } | |
210 | ||
211 | static bool is_mmio_spte(u64 spte) | |
212 | { | |
213 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
214 | } | |
215 | ||
216 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
217 | { | |
218 | return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT; | |
219 | } | |
220 | ||
221 | static unsigned get_mmio_spte_access(u64 spte) | |
222 | { | |
223 | return (spte & ~shadow_mmio_mask) & ~PAGE_MASK; | |
224 | } | |
225 | ||
226 | static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access) | |
227 | { | |
228 | if (unlikely(is_noslot_pfn(pfn))) { | |
229 | mark_mmio_spte(sptep, gfn, access); | |
230 | return true; | |
231 | } | |
232 | ||
233 | return false; | |
234 | } | |
c7addb90 | 235 | |
82725b20 DE |
236 | static inline u64 rsvd_bits(int s, int e) |
237 | { | |
238 | return ((1ULL << (e - s + 1)) - 1) << s; | |
239 | } | |
240 | ||
7b52345e | 241 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 242 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
243 | { |
244 | shadow_user_mask = user_mask; | |
245 | shadow_accessed_mask = accessed_mask; | |
246 | shadow_dirty_mask = dirty_mask; | |
247 | shadow_nx_mask = nx_mask; | |
248 | shadow_x_mask = x_mask; | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
251 | ||
6aa8b732 AK |
252 | static int is_cpuid_PSE36(void) |
253 | { | |
254 | return 1; | |
255 | } | |
256 | ||
73b1087e AK |
257 | static int is_nx(struct kvm_vcpu *vcpu) |
258 | { | |
f6801dff | 259 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
260 | } |
261 | ||
c7addb90 AK |
262 | static int is_shadow_present_pte(u64 pte) |
263 | { | |
ce88decf | 264 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
265 | } |
266 | ||
05da4558 MT |
267 | static int is_large_pte(u64 pte) |
268 | { | |
269 | return pte & PT_PAGE_SIZE_MASK; | |
270 | } | |
271 | ||
43a3795a | 272 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 273 | { |
439e218a | 274 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
275 | } |
276 | ||
43a3795a | 277 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 278 | { |
4b1a80fa | 279 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
280 | } |
281 | ||
776e6633 MT |
282 | static int is_last_spte(u64 pte, int level) |
283 | { | |
284 | if (level == PT_PAGE_TABLE_LEVEL) | |
285 | return 1; | |
852e3c19 | 286 | if (is_large_pte(pte)) |
776e6633 MT |
287 | return 1; |
288 | return 0; | |
289 | } | |
290 | ||
35149e21 | 291 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 292 | { |
35149e21 | 293 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
294 | } |
295 | ||
da928521 AK |
296 | static gfn_t pse36_gfn_delta(u32 gpte) |
297 | { | |
298 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
299 | ||
300 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
301 | } | |
302 | ||
603e0651 | 303 | #ifdef CONFIG_X86_64 |
d555c333 | 304 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 305 | { |
603e0651 | 306 | *sptep = spte; |
e663ee64 AK |
307 | } |
308 | ||
603e0651 | 309 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 310 | { |
603e0651 XG |
311 | *sptep = spte; |
312 | } | |
313 | ||
314 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
315 | { | |
316 | return xchg(sptep, spte); | |
317 | } | |
c2a2ac2b XG |
318 | |
319 | static u64 __get_spte_lockless(u64 *sptep) | |
320 | { | |
321 | return ACCESS_ONCE(*sptep); | |
322 | } | |
ce88decf XG |
323 | |
324 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
325 | { | |
326 | /* It is valid if the spte is zapped. */ | |
327 | return spte == 0ull; | |
328 | } | |
a9221dd5 | 329 | #else |
603e0651 XG |
330 | union split_spte { |
331 | struct { | |
332 | u32 spte_low; | |
333 | u32 spte_high; | |
334 | }; | |
335 | u64 spte; | |
336 | }; | |
a9221dd5 | 337 | |
c2a2ac2b XG |
338 | static void count_spte_clear(u64 *sptep, u64 spte) |
339 | { | |
340 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
341 | ||
342 | if (is_shadow_present_pte(spte)) | |
343 | return; | |
344 | ||
345 | /* Ensure the spte is completely set before we increase the count */ | |
346 | smp_wmb(); | |
347 | sp->clear_spte_count++; | |
348 | } | |
349 | ||
603e0651 XG |
350 | static void __set_spte(u64 *sptep, u64 spte) |
351 | { | |
352 | union split_spte *ssptep, sspte; | |
a9221dd5 | 353 | |
603e0651 XG |
354 | ssptep = (union split_spte *)sptep; |
355 | sspte = (union split_spte)spte; | |
356 | ||
357 | ssptep->spte_high = sspte.spte_high; | |
358 | ||
359 | /* | |
360 | * If we map the spte from nonpresent to present, We should store | |
361 | * the high bits firstly, then set present bit, so cpu can not | |
362 | * fetch this spte while we are setting the spte. | |
363 | */ | |
364 | smp_wmb(); | |
365 | ||
366 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
367 | } |
368 | ||
603e0651 XG |
369 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
370 | { | |
371 | union split_spte *ssptep, sspte; | |
372 | ||
373 | ssptep = (union split_spte *)sptep; | |
374 | sspte = (union split_spte)spte; | |
375 | ||
376 | ssptep->spte_low = sspte.spte_low; | |
377 | ||
378 | /* | |
379 | * If we map the spte from present to nonpresent, we should clear | |
380 | * present bit firstly to avoid vcpu fetch the old high bits. | |
381 | */ | |
382 | smp_wmb(); | |
383 | ||
384 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 385 | count_spte_clear(sptep, spte); |
603e0651 XG |
386 | } |
387 | ||
388 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
389 | { | |
390 | union split_spte *ssptep, sspte, orig; | |
391 | ||
392 | ssptep = (union split_spte *)sptep; | |
393 | sspte = (union split_spte)spte; | |
394 | ||
395 | /* xchg acts as a barrier before the setting of the high bits */ | |
396 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
397 | orig.spte_high = ssptep->spte_high; |
398 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 399 | count_spte_clear(sptep, spte); |
603e0651 XG |
400 | |
401 | return orig.spte; | |
402 | } | |
c2a2ac2b XG |
403 | |
404 | /* | |
405 | * The idea using the light way get the spte on x86_32 guest is from | |
406 | * gup_get_pte(arch/x86/mm/gup.c). | |
407 | * The difference is we can not catch the spte tlb flush if we leave | |
408 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
409 | * is cleared. | |
410 | */ | |
411 | static u64 __get_spte_lockless(u64 *sptep) | |
412 | { | |
413 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
414 | union split_spte spte, *orig = (union split_spte *)sptep; | |
415 | int count; | |
416 | ||
417 | retry: | |
418 | count = sp->clear_spte_count; | |
419 | smp_rmb(); | |
420 | ||
421 | spte.spte_low = orig->spte_low; | |
422 | smp_rmb(); | |
423 | ||
424 | spte.spte_high = orig->spte_high; | |
425 | smp_rmb(); | |
426 | ||
427 | if (unlikely(spte.spte_low != orig->spte_low || | |
428 | count != sp->clear_spte_count)) | |
429 | goto retry; | |
430 | ||
431 | return spte.spte; | |
432 | } | |
ce88decf XG |
433 | |
434 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
435 | { | |
436 | union split_spte sspte = (union split_spte)spte; | |
437 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
438 | ||
439 | /* It is valid if the spte is zapped. */ | |
440 | if (spte == 0ull) | |
441 | return true; | |
442 | ||
443 | /* It is valid if the spte is being zapped. */ | |
444 | if (sspte.spte_low == 0ull && | |
445 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
446 | return true; | |
447 | ||
448 | return false; | |
449 | } | |
603e0651 XG |
450 | #endif |
451 | ||
c7ba5b48 XG |
452 | static bool spte_is_locklessly_modifiable(u64 spte) |
453 | { | |
feb3eb70 GN |
454 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
455 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
456 | } |
457 | ||
8672b721 XG |
458 | static bool spte_has_volatile_bits(u64 spte) |
459 | { | |
c7ba5b48 XG |
460 | /* |
461 | * Always atomicly update spte if it can be updated | |
462 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
463 | * also, it can help us to get a stable is_writable_pte() | |
464 | * to ensure tlb flush is not missed. | |
465 | */ | |
466 | if (spte_is_locklessly_modifiable(spte)) | |
467 | return true; | |
468 | ||
8672b721 XG |
469 | if (!shadow_accessed_mask) |
470 | return false; | |
471 | ||
472 | if (!is_shadow_present_pte(spte)) | |
473 | return false; | |
474 | ||
4132779b XG |
475 | if ((spte & shadow_accessed_mask) && |
476 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
477 | return false; |
478 | ||
479 | return true; | |
480 | } | |
481 | ||
4132779b XG |
482 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
483 | { | |
484 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
485 | } | |
486 | ||
1df9f2dc XG |
487 | /* Rules for using mmu_spte_set: |
488 | * Set the sptep from nonpresent to present. | |
489 | * Note: the sptep being assigned *must* be either not present | |
490 | * or in a state where the hardware will not attempt to update | |
491 | * the spte. | |
492 | */ | |
493 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
494 | { | |
495 | WARN_ON(is_shadow_present_pte(*sptep)); | |
496 | __set_spte(sptep, new_spte); | |
497 | } | |
498 | ||
499 | /* Rules for using mmu_spte_update: | |
500 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
501 | * |
502 | * Whenever we overwrite a writable spte with a read-only one we | |
503 | * should flush remote TLBs. Otherwise rmap_write_protect | |
504 | * will find a read-only spte, even though the writable spte | |
505 | * might be cached on a CPU's TLB, the return value indicates this | |
506 | * case. | |
1df9f2dc | 507 | */ |
6e7d0354 | 508 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 509 | { |
c7ba5b48 | 510 | u64 old_spte = *sptep; |
6e7d0354 | 511 | bool ret = false; |
4132779b XG |
512 | |
513 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 514 | |
6e7d0354 XG |
515 | if (!is_shadow_present_pte(old_spte)) { |
516 | mmu_spte_set(sptep, new_spte); | |
517 | return ret; | |
518 | } | |
4132779b | 519 | |
c7ba5b48 | 520 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 521 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 522 | else |
603e0651 | 523 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 524 | |
c7ba5b48 XG |
525 | /* |
526 | * For the spte updated out of mmu-lock is safe, since | |
527 | * we always atomicly update it, see the comments in | |
528 | * spte_has_volatile_bits(). | |
529 | */ | |
6e7d0354 XG |
530 | if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) |
531 | ret = true; | |
532 | ||
4132779b | 533 | if (!shadow_accessed_mask) |
6e7d0354 | 534 | return ret; |
4132779b XG |
535 | |
536 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
537 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
538 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
539 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
540 | |
541 | return ret; | |
b79b93f9 AK |
542 | } |
543 | ||
1df9f2dc XG |
544 | /* |
545 | * Rules for using mmu_spte_clear_track_bits: | |
546 | * It sets the sptep from present to nonpresent, and track the | |
547 | * state bits, it is used to clear the last level sptep. | |
548 | */ | |
549 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
550 | { | |
551 | pfn_t pfn; | |
552 | u64 old_spte = *sptep; | |
553 | ||
554 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 555 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 556 | else |
603e0651 | 557 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
558 | |
559 | if (!is_rmap_spte(old_spte)) | |
560 | return 0; | |
561 | ||
562 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
563 | |
564 | /* | |
565 | * KVM does not hold the refcount of the page used by | |
566 | * kvm mmu, before reclaiming the page, we should | |
567 | * unmap it from mmu first. | |
568 | */ | |
569 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
570 | ||
1df9f2dc XG |
571 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
572 | kvm_set_pfn_accessed(pfn); | |
573 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
574 | kvm_set_pfn_dirty(pfn); | |
575 | return 1; | |
576 | } | |
577 | ||
578 | /* | |
579 | * Rules for using mmu_spte_clear_no_track: | |
580 | * Directly clear spte without caring the state bits of sptep, | |
581 | * it is used to set the upper level spte. | |
582 | */ | |
583 | static void mmu_spte_clear_no_track(u64 *sptep) | |
584 | { | |
603e0651 | 585 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
586 | } |
587 | ||
c2a2ac2b XG |
588 | static u64 mmu_spte_get_lockless(u64 *sptep) |
589 | { | |
590 | return __get_spte_lockless(sptep); | |
591 | } | |
592 | ||
593 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
594 | { | |
c142786c AK |
595 | /* |
596 | * Prevent page table teardown by making any free-er wait during | |
597 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
598 | */ | |
599 | local_irq_disable(); | |
600 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
601 | /* | |
602 | * Make sure a following spte read is not reordered ahead of the write | |
603 | * to vcpu->mode. | |
604 | */ | |
605 | smp_mb(); | |
c2a2ac2b XG |
606 | } |
607 | ||
608 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
609 | { | |
c142786c AK |
610 | /* |
611 | * Make sure the write to vcpu->mode is not reordered in front of | |
612 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
613 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
614 | */ | |
615 | smp_mb(); | |
616 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
617 | local_irq_enable(); | |
c2a2ac2b XG |
618 | } |
619 | ||
e2dec939 | 620 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 621 | struct kmem_cache *base_cache, int min) |
714b93da AK |
622 | { |
623 | void *obj; | |
624 | ||
625 | if (cache->nobjs >= min) | |
e2dec939 | 626 | return 0; |
714b93da | 627 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 628 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 629 | if (!obj) |
e2dec939 | 630 | return -ENOMEM; |
714b93da AK |
631 | cache->objects[cache->nobjs++] = obj; |
632 | } | |
e2dec939 | 633 | return 0; |
714b93da AK |
634 | } |
635 | ||
f759e2b4 XG |
636 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
637 | { | |
638 | return cache->nobjs; | |
639 | } | |
640 | ||
e8ad9a70 XG |
641 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
642 | struct kmem_cache *cache) | |
714b93da AK |
643 | { |
644 | while (mc->nobjs) | |
e8ad9a70 | 645 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
646 | } |
647 | ||
c1158e63 | 648 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 649 | int min) |
c1158e63 | 650 | { |
842f22ed | 651 | void *page; |
c1158e63 AK |
652 | |
653 | if (cache->nobjs >= min) | |
654 | return 0; | |
655 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 656 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
657 | if (!page) |
658 | return -ENOMEM; | |
842f22ed | 659 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
660 | } |
661 | return 0; | |
662 | } | |
663 | ||
664 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
665 | { | |
666 | while (mc->nobjs) | |
c4d198d5 | 667 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
668 | } |
669 | ||
2e3e5882 | 670 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 671 | { |
e2dec939 AK |
672 | int r; |
673 | ||
53c07b18 | 674 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 675 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
676 | if (r) |
677 | goto out; | |
ad312c7c | 678 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
679 | if (r) |
680 | goto out; | |
ad312c7c | 681 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 682 | mmu_page_header_cache, 4); |
e2dec939 AK |
683 | out: |
684 | return r; | |
714b93da AK |
685 | } |
686 | ||
687 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
688 | { | |
53c07b18 XG |
689 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
690 | pte_list_desc_cache); | |
ad312c7c | 691 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
692 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
693 | mmu_page_header_cache); | |
714b93da AK |
694 | } |
695 | ||
80feb89a | 696 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
697 | { |
698 | void *p; | |
699 | ||
700 | BUG_ON(!mc->nobjs); | |
701 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
702 | return p; |
703 | } | |
704 | ||
53c07b18 | 705 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 706 | { |
80feb89a | 707 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
708 | } |
709 | ||
53c07b18 | 710 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 711 | { |
53c07b18 | 712 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
713 | } |
714 | ||
2032a93d LJ |
715 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
716 | { | |
717 | if (!sp->role.direct) | |
718 | return sp->gfns[index]; | |
719 | ||
720 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
721 | } | |
722 | ||
723 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
724 | { | |
725 | if (sp->role.direct) | |
726 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
727 | else | |
728 | sp->gfns[index] = gfn; | |
729 | } | |
730 | ||
05da4558 | 731 | /* |
d4dbf470 TY |
732 | * Return the pointer to the large page information for a given gfn, |
733 | * handling slots that are not large page aligned. | |
05da4558 | 734 | */ |
d4dbf470 TY |
735 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
736 | struct kvm_memory_slot *slot, | |
737 | int level) | |
05da4558 MT |
738 | { |
739 | unsigned long idx; | |
740 | ||
fb03cb6f | 741 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 742 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
743 | } |
744 | ||
745 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
746 | { | |
d25797b2 | 747 | struct kvm_memory_slot *slot; |
d4dbf470 | 748 | struct kvm_lpage_info *linfo; |
d25797b2 | 749 | int i; |
05da4558 | 750 | |
a1f4d395 | 751 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
752 | for (i = PT_DIRECTORY_LEVEL; |
753 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
754 | linfo = lpage_info_slot(gfn, slot, i); |
755 | linfo->write_count += 1; | |
d25797b2 | 756 | } |
332b207d | 757 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
758 | } |
759 | ||
760 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
761 | { | |
d25797b2 | 762 | struct kvm_memory_slot *slot; |
d4dbf470 | 763 | struct kvm_lpage_info *linfo; |
d25797b2 | 764 | int i; |
05da4558 | 765 | |
a1f4d395 | 766 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
767 | for (i = PT_DIRECTORY_LEVEL; |
768 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
769 | linfo = lpage_info_slot(gfn, slot, i); |
770 | linfo->write_count -= 1; | |
771 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 772 | } |
332b207d | 773 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
774 | } |
775 | ||
d25797b2 JR |
776 | static int has_wrprotected_page(struct kvm *kvm, |
777 | gfn_t gfn, | |
778 | int level) | |
05da4558 | 779 | { |
2843099f | 780 | struct kvm_memory_slot *slot; |
d4dbf470 | 781 | struct kvm_lpage_info *linfo; |
05da4558 | 782 | |
a1f4d395 | 783 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 784 | if (slot) { |
d4dbf470 TY |
785 | linfo = lpage_info_slot(gfn, slot, level); |
786 | return linfo->write_count; | |
05da4558 MT |
787 | } |
788 | ||
789 | return 1; | |
790 | } | |
791 | ||
d25797b2 | 792 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 793 | { |
8f0b1ab6 | 794 | unsigned long page_size; |
d25797b2 | 795 | int i, ret = 0; |
05da4558 | 796 | |
8f0b1ab6 | 797 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 798 | |
d25797b2 JR |
799 | for (i = PT_PAGE_TABLE_LEVEL; |
800 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
801 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
802 | ret = i; | |
803 | else | |
804 | break; | |
805 | } | |
806 | ||
4c2155ce | 807 | return ret; |
05da4558 MT |
808 | } |
809 | ||
5d163b1c XG |
810 | static struct kvm_memory_slot * |
811 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
812 | bool no_dirty_log) | |
05da4558 MT |
813 | { |
814 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
815 | |
816 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
817 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
818 | (no_dirty_log && slot->dirty_bitmap)) | |
819 | slot = NULL; | |
820 | ||
821 | return slot; | |
822 | } | |
823 | ||
824 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
825 | { | |
a0a8eaba | 826 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
827 | } |
828 | ||
829 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
830 | { | |
831 | int host_level, level, max_level; | |
05da4558 | 832 | |
d25797b2 JR |
833 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
834 | ||
835 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
836 | return host_level; | |
837 | ||
55dd98c3 | 838 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
839 | |
840 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
841 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
842 | break; | |
d25797b2 JR |
843 | |
844 | return level - 1; | |
05da4558 MT |
845 | } |
846 | ||
290fc38d | 847 | /* |
53c07b18 | 848 | * Pte mapping structures: |
cd4a4e53 | 849 | * |
53c07b18 | 850 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 851 | * |
53c07b18 XG |
852 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
853 | * pte_list_desc containing more mappings. | |
53a27b39 | 854 | * |
53c07b18 | 855 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
856 | * the spte was not added. |
857 | * | |
cd4a4e53 | 858 | */ |
53c07b18 XG |
859 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
860 | unsigned long *pte_list) | |
cd4a4e53 | 861 | { |
53c07b18 | 862 | struct pte_list_desc *desc; |
53a27b39 | 863 | int i, count = 0; |
cd4a4e53 | 864 | |
53c07b18 XG |
865 | if (!*pte_list) { |
866 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
867 | *pte_list = (unsigned long)spte; | |
868 | } else if (!(*pte_list & 1)) { | |
869 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
870 | desc = mmu_alloc_pte_list_desc(vcpu); | |
871 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 872 | desc->sptes[1] = spte; |
53c07b18 | 873 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 874 | ++count; |
cd4a4e53 | 875 | } else { |
53c07b18 XG |
876 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
877 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
878 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 879 | desc = desc->more; |
53c07b18 | 880 | count += PTE_LIST_EXT; |
53a27b39 | 881 | } |
53c07b18 XG |
882 | if (desc->sptes[PTE_LIST_EXT-1]) { |
883 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
884 | desc = desc->more; |
885 | } | |
d555c333 | 886 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 887 | ++count; |
d555c333 | 888 | desc->sptes[i] = spte; |
cd4a4e53 | 889 | } |
53a27b39 | 890 | return count; |
cd4a4e53 AK |
891 | } |
892 | ||
53c07b18 XG |
893 | static void |
894 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
895 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
896 | { |
897 | int j; | |
898 | ||
53c07b18 | 899 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 900 | ; |
d555c333 AK |
901 | desc->sptes[i] = desc->sptes[j]; |
902 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
903 | if (j != 0) |
904 | return; | |
905 | if (!prev_desc && !desc->more) | |
53c07b18 | 906 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
907 | else |
908 | if (prev_desc) | |
909 | prev_desc->more = desc->more; | |
910 | else | |
53c07b18 XG |
911 | *pte_list = (unsigned long)desc->more | 1; |
912 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
913 | } |
914 | ||
53c07b18 | 915 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 916 | { |
53c07b18 XG |
917 | struct pte_list_desc *desc; |
918 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
919 | int i; |
920 | ||
53c07b18 XG |
921 | if (!*pte_list) { |
922 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 923 | BUG(); |
53c07b18 XG |
924 | } else if (!(*pte_list & 1)) { |
925 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
926 | if ((u64 *)*pte_list != spte) { | |
927 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
928 | BUG(); |
929 | } | |
53c07b18 | 930 | *pte_list = 0; |
cd4a4e53 | 931 | } else { |
53c07b18 XG |
932 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
933 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
934 | prev_desc = NULL; |
935 | while (desc) { | |
53c07b18 | 936 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 937 | if (desc->sptes[i] == spte) { |
53c07b18 | 938 | pte_list_desc_remove_entry(pte_list, |
714b93da | 939 | desc, i, |
cd4a4e53 AK |
940 | prev_desc); |
941 | return; | |
942 | } | |
943 | prev_desc = desc; | |
944 | desc = desc->more; | |
945 | } | |
53c07b18 | 946 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
947 | BUG(); |
948 | } | |
949 | } | |
950 | ||
67052b35 XG |
951 | typedef void (*pte_list_walk_fn) (u64 *spte); |
952 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
953 | { | |
954 | struct pte_list_desc *desc; | |
955 | int i; | |
956 | ||
957 | if (!*pte_list) | |
958 | return; | |
959 | ||
960 | if (!(*pte_list & 1)) | |
961 | return fn((u64 *)*pte_list); | |
962 | ||
963 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
964 | while (desc) { | |
965 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
966 | fn(desc->sptes[i]); | |
967 | desc = desc->more; | |
968 | } | |
969 | } | |
970 | ||
9373e2c0 | 971 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 972 | struct kvm_memory_slot *slot) |
53c07b18 | 973 | { |
77d11309 | 974 | unsigned long idx; |
53c07b18 | 975 | |
77d11309 | 976 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 977 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
978 | } |
979 | ||
9b9b1492 TY |
980 | /* |
981 | * Take gfn and return the reverse mapping to it. | |
982 | */ | |
983 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
984 | { | |
985 | struct kvm_memory_slot *slot; | |
986 | ||
987 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 988 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
989 | } |
990 | ||
f759e2b4 XG |
991 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
992 | { | |
993 | struct kvm_mmu_memory_cache *cache; | |
994 | ||
995 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
996 | return mmu_memory_cache_free_objects(cache); | |
997 | } | |
998 | ||
53c07b18 XG |
999 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1000 | { | |
1001 | struct kvm_mmu_page *sp; | |
1002 | unsigned long *rmapp; | |
1003 | ||
53c07b18 XG |
1004 | sp = page_header(__pa(spte)); |
1005 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1006 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1007 | return pte_list_add(vcpu, spte, rmapp); | |
1008 | } | |
1009 | ||
53c07b18 XG |
1010 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1011 | { | |
1012 | struct kvm_mmu_page *sp; | |
1013 | gfn_t gfn; | |
1014 | unsigned long *rmapp; | |
1015 | ||
1016 | sp = page_header(__pa(spte)); | |
1017 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1018 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1019 | pte_list_remove(spte, rmapp); | |
1020 | } | |
1021 | ||
1e3f42f0 TY |
1022 | /* |
1023 | * Used by the following functions to iterate through the sptes linked by a | |
1024 | * rmap. All fields are private and not assumed to be used outside. | |
1025 | */ | |
1026 | struct rmap_iterator { | |
1027 | /* private fields */ | |
1028 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1029 | int pos; /* index of the sptep */ | |
1030 | }; | |
1031 | ||
1032 | /* | |
1033 | * Iteration must be started by this function. This should also be used after | |
1034 | * removing/dropping sptes from the rmap link because in such cases the | |
1035 | * information in the itererator may not be valid. | |
1036 | * | |
1037 | * Returns sptep if found, NULL otherwise. | |
1038 | */ | |
1039 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1040 | { | |
1041 | if (!rmap) | |
1042 | return NULL; | |
1043 | ||
1044 | if (!(rmap & 1)) { | |
1045 | iter->desc = NULL; | |
1046 | return (u64 *)rmap; | |
1047 | } | |
1048 | ||
1049 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1050 | iter->pos = 0; | |
1051 | return iter->desc->sptes[iter->pos]; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1056 | * | |
1057 | * Returns sptep if found, NULL otherwise. | |
1058 | */ | |
1059 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1060 | { | |
1061 | if (iter->desc) { | |
1062 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1063 | u64 *sptep; | |
1064 | ||
1065 | ++iter->pos; | |
1066 | sptep = iter->desc->sptes[iter->pos]; | |
1067 | if (sptep) | |
1068 | return sptep; | |
1069 | } | |
1070 | ||
1071 | iter->desc = iter->desc->more; | |
1072 | ||
1073 | if (iter->desc) { | |
1074 | iter->pos = 0; | |
1075 | /* desc->sptes[0] cannot be NULL */ | |
1076 | return iter->desc->sptes[iter->pos]; | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | return NULL; | |
1081 | } | |
1082 | ||
c3707958 | 1083 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1084 | { |
1df9f2dc | 1085 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1086 | rmap_remove(kvm, sptep); |
be38d276 AK |
1087 | } |
1088 | ||
8e22f955 XG |
1089 | |
1090 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1091 | { | |
1092 | if (is_large_pte(*sptep)) { | |
1093 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1094 | PT_PAGE_TABLE_LEVEL); | |
1095 | drop_spte(kvm, sptep); | |
1096 | --kvm->stat.lpages; | |
1097 | return true; | |
1098 | } | |
1099 | ||
1100 | return false; | |
1101 | } | |
1102 | ||
1103 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1104 | { | |
1105 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1106 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1107 | } | |
1108 | ||
1109 | /* | |
49fde340 | 1110 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
6b73a960 MT |
1111 | * spte writ-protection is caused by protecting shadow page table. |
1112 | * @flush indicates whether tlb need be flushed. | |
49fde340 XG |
1113 | * |
1114 | * Note: write protection is difference between drity logging and spte | |
1115 | * protection: | |
1116 | * - for dirty logging, the spte can be set to writable at anytime if | |
1117 | * its dirty bitmap is properly set. | |
1118 | * - for spte protection, the spte can be writable only after unsync-ing | |
1119 | * shadow page. | |
8e22f955 | 1120 | * |
6b73a960 | 1121 | * Return true if the spte is dropped. |
8e22f955 | 1122 | */ |
6b73a960 MT |
1123 | static bool |
1124 | spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) | |
d13bc5b5 XG |
1125 | { |
1126 | u64 spte = *sptep; | |
1127 | ||
49fde340 XG |
1128 | if (!is_writable_pte(spte) && |
1129 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1130 | return false; |
1131 | ||
1132 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1133 | ||
6b73a960 MT |
1134 | if (__drop_large_spte(kvm, sptep)) { |
1135 | *flush |= true; | |
1136 | return true; | |
1137 | } | |
1138 | ||
49fde340 XG |
1139 | if (pt_protect) |
1140 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1141 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1142 | |
6b73a960 MT |
1143 | *flush |= mmu_spte_update(sptep, spte); |
1144 | return false; | |
d13bc5b5 XG |
1145 | } |
1146 | ||
49fde340 | 1147 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1148 | bool pt_protect) |
98348e95 | 1149 | { |
1e3f42f0 TY |
1150 | u64 *sptep; |
1151 | struct rmap_iterator iter; | |
d13bc5b5 | 1152 | bool flush = false; |
374cbac0 | 1153 | |
1e3f42f0 TY |
1154 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1155 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
6b73a960 MT |
1156 | if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { |
1157 | sptep = rmap_get_first(*rmapp, &iter); | |
1158 | continue; | |
1159 | } | |
a0ed4607 | 1160 | |
d13bc5b5 | 1161 | sptep = rmap_get_next(&iter); |
374cbac0 | 1162 | } |
855149aa | 1163 | |
d13bc5b5 | 1164 | return flush; |
a0ed4607 TY |
1165 | } |
1166 | ||
5dc99b23 TY |
1167 | /** |
1168 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1169 | * @kvm: kvm instance | |
1170 | * @slot: slot to protect | |
1171 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1172 | * @mask: indicates which pages we should protect | |
1173 | * | |
1174 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1175 | * logging we do not have any such mappings. | |
1176 | */ | |
1177 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1178 | struct kvm_memory_slot *slot, | |
1179 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1180 | { |
1181 | unsigned long *rmapp; | |
a0ed4607 | 1182 | |
5dc99b23 | 1183 | while (mask) { |
65fbe37c TY |
1184 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1185 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1186 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1187 | |
5dc99b23 TY |
1188 | /* clear the first set bit */ |
1189 | mask &= mask - 1; | |
1190 | } | |
374cbac0 AK |
1191 | } |
1192 | ||
2f84569f | 1193 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1194 | { |
1195 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1196 | unsigned long *rmapp; |
1197 | int i; | |
2f84569f | 1198 | bool write_protected = false; |
95d4c16c TY |
1199 | |
1200 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1201 | |
1202 | for (i = PT_PAGE_TABLE_LEVEL; | |
1203 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1204 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1205 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1206 | } |
1207 | ||
1208 | return write_protected; | |
95d4c16c TY |
1209 | } |
1210 | ||
8a8365c5 | 1211 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1212 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1213 | { |
1e3f42f0 TY |
1214 | u64 *sptep; |
1215 | struct rmap_iterator iter; | |
e930bffe AA |
1216 | int need_tlb_flush = 0; |
1217 | ||
1e3f42f0 TY |
1218 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1219 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1220 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1221 | ||
1222 | drop_spte(kvm, sptep); | |
e930bffe AA |
1223 | need_tlb_flush = 1; |
1224 | } | |
1e3f42f0 | 1225 | |
e930bffe AA |
1226 | return need_tlb_flush; |
1227 | } | |
1228 | ||
8a8365c5 | 1229 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1230 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1231 | { |
1e3f42f0 TY |
1232 | u64 *sptep; |
1233 | struct rmap_iterator iter; | |
3da0dd43 | 1234 | int need_flush = 0; |
1e3f42f0 | 1235 | u64 new_spte; |
3da0dd43 IE |
1236 | pte_t *ptep = (pte_t *)data; |
1237 | pfn_t new_pfn; | |
1238 | ||
1239 | WARN_ON(pte_huge(*ptep)); | |
1240 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1241 | |
1242 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1243 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1244 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1245 | ||
3da0dd43 | 1246 | need_flush = 1; |
1e3f42f0 | 1247 | |
3da0dd43 | 1248 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1249 | drop_spte(kvm, sptep); |
1250 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1251 | } else { |
1e3f42f0 | 1252 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1253 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1254 | ||
1255 | new_spte &= ~PT_WRITABLE_MASK; | |
1256 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1257 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1258 | |
1259 | mmu_spte_clear_track_bits(sptep); | |
1260 | mmu_spte_set(sptep, new_spte); | |
1261 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1262 | } |
1263 | } | |
1e3f42f0 | 1264 | |
3da0dd43 IE |
1265 | if (need_flush) |
1266 | kvm_flush_remote_tlbs(kvm); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
84504ef3 TY |
1271 | static int kvm_handle_hva_range(struct kvm *kvm, |
1272 | unsigned long start, | |
1273 | unsigned long end, | |
1274 | unsigned long data, | |
1275 | int (*handler)(struct kvm *kvm, | |
1276 | unsigned long *rmapp, | |
048212d0 | 1277 | struct kvm_memory_slot *slot, |
84504ef3 | 1278 | unsigned long data)) |
e930bffe | 1279 | { |
be6ba0f0 | 1280 | int j; |
f395302e | 1281 | int ret = 0; |
bc6678a3 | 1282 | struct kvm_memslots *slots; |
be6ba0f0 | 1283 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1284 | |
90d83dc3 | 1285 | slots = kvm_memslots(kvm); |
e930bffe | 1286 | |
be6ba0f0 | 1287 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1288 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1289 | gfn_t gfn_start, gfn_end; |
e930bffe | 1290 | |
84504ef3 TY |
1291 | hva_start = max(start, memslot->userspace_addr); |
1292 | hva_end = min(end, memslot->userspace_addr + | |
1293 | (memslot->npages << PAGE_SHIFT)); | |
1294 | if (hva_start >= hva_end) | |
1295 | continue; | |
1296 | /* | |
1297 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1298 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1299 | */ |
bcd3ef58 | 1300 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1301 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1302 | |
bcd3ef58 TY |
1303 | for (j = PT_PAGE_TABLE_LEVEL; |
1304 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1305 | unsigned long idx, idx_end; | |
1306 | unsigned long *rmapp; | |
d4dbf470 | 1307 | |
bcd3ef58 TY |
1308 | /* |
1309 | * {idx(page_j) | page_j intersects with | |
1310 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1311 | */ | |
1312 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1313 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1314 | |
bcd3ef58 | 1315 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1316 | |
bcd3ef58 TY |
1317 | for (; idx <= idx_end; ++idx) |
1318 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1319 | } |
1320 | } | |
1321 | ||
f395302e | 1322 | return ret; |
e930bffe AA |
1323 | } |
1324 | ||
84504ef3 TY |
1325 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1326 | unsigned long data, | |
1327 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1328 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1329 | unsigned long data)) |
1330 | { | |
1331 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1332 | } |
1333 | ||
1334 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1335 | { | |
3da0dd43 IE |
1336 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1337 | } | |
1338 | ||
b3ae2096 TY |
1339 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1340 | { | |
1341 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1342 | } | |
1343 | ||
3da0dd43 IE |
1344 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1345 | { | |
8a8365c5 | 1346 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1347 | } |
1348 | ||
8a8365c5 | 1349 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1350 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1351 | { |
1e3f42f0 | 1352 | u64 *sptep; |
79f702a6 | 1353 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1354 | int young = 0; |
1355 | ||
6316e1c8 | 1356 | /* |
3f6d8c8a XH |
1357 | * In case of absence of EPT Access and Dirty Bits supports, |
1358 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1359 | * an EPT mapping, and clearing it if it does. On the next access, |
1360 | * a new EPT mapping will be established. | |
1361 | * This has some overhead, but not as much as the cost of swapping | |
1362 | * out actively used pages or breaking up actively used hugepages. | |
1363 | */ | |
f395302e TY |
1364 | if (!shadow_accessed_mask) { |
1365 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1366 | goto out; | |
1367 | } | |
534e38b4 | 1368 | |
1e3f42f0 TY |
1369 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1370 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1371 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1372 | |
3f6d8c8a | 1373 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1374 | young = 1; |
3f6d8c8a XH |
1375 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1376 | (unsigned long *)sptep); | |
e930bffe | 1377 | } |
e930bffe | 1378 | } |
f395302e TY |
1379 | out: |
1380 | /* @data has hva passed to kvm_age_hva(). */ | |
1381 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1382 | return young; |
1383 | } | |
1384 | ||
8ee53820 | 1385 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1386 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1387 | { |
1e3f42f0 TY |
1388 | u64 *sptep; |
1389 | struct rmap_iterator iter; | |
8ee53820 AA |
1390 | int young = 0; |
1391 | ||
1392 | /* | |
1393 | * If there's no access bit in the secondary pte set by the | |
1394 | * hardware it's up to gup-fast/gup to set the access bit in | |
1395 | * the primary pte or in the page structure. | |
1396 | */ | |
1397 | if (!shadow_accessed_mask) | |
1398 | goto out; | |
1399 | ||
1e3f42f0 TY |
1400 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1401 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1402 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1403 | |
3f6d8c8a | 1404 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1405 | young = 1; |
1406 | break; | |
1407 | } | |
8ee53820 AA |
1408 | } |
1409 | out: | |
1410 | return young; | |
1411 | } | |
1412 | ||
53a27b39 MT |
1413 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1414 | ||
852e3c19 | 1415 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1416 | { |
1417 | unsigned long *rmapp; | |
852e3c19 JR |
1418 | struct kvm_mmu_page *sp; |
1419 | ||
1420 | sp = page_header(__pa(spte)); | |
53a27b39 | 1421 | |
852e3c19 | 1422 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1423 | |
048212d0 | 1424 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1425 | kvm_flush_remote_tlbs(vcpu->kvm); |
1426 | } | |
1427 | ||
e930bffe AA |
1428 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1429 | { | |
f395302e | 1430 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1431 | } |
1432 | ||
8ee53820 AA |
1433 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1434 | { | |
1435 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1436 | } | |
1437 | ||
d6c69ee9 | 1438 | #ifdef MMU_DEBUG |
47ad8e68 | 1439 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1440 | { |
139bdb2d AK |
1441 | u64 *pos; |
1442 | u64 *end; | |
1443 | ||
47ad8e68 | 1444 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1445 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1446 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1447 | pos, *pos); |
6aa8b732 | 1448 | return 0; |
139bdb2d | 1449 | } |
6aa8b732 AK |
1450 | return 1; |
1451 | } | |
d6c69ee9 | 1452 | #endif |
6aa8b732 | 1453 | |
45221ab6 DH |
1454 | /* |
1455 | * This value is the sum of all of the kvm instances's | |
1456 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1457 | * aggregate version in order to make the slab shrinker | |
1458 | * faster | |
1459 | */ | |
1460 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1461 | { | |
1462 | kvm->arch.n_used_mmu_pages += nr; | |
1463 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1464 | } | |
1465 | ||
834be0d8 | 1466 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1467 | { |
4db35314 | 1468 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1469 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1470 | list_del(&sp->link); |
1471 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1472 | if (!sp->role.direct) |
1473 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1474 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1475 | } |
1476 | ||
cea0f0e7 AK |
1477 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1478 | { | |
1ae0a13d | 1479 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1480 | } |
1481 | ||
714b93da | 1482 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1483 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1484 | { |
cea0f0e7 AK |
1485 | if (!parent_pte) |
1486 | return; | |
cea0f0e7 | 1487 | |
67052b35 | 1488 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1489 | } |
1490 | ||
4db35314 | 1491 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1492 | u64 *parent_pte) |
1493 | { | |
67052b35 | 1494 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1495 | } |
1496 | ||
bcdd9a93 XG |
1497 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1498 | u64 *parent_pte) | |
1499 | { | |
1500 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1501 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1502 | } |
1503 | ||
67052b35 XG |
1504 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1505 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1506 | { |
67052b35 | 1507 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1508 | |
80feb89a TY |
1509 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1510 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1511 | if (!direct) |
80feb89a | 1512 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1513 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1514 | |
1515 | /* | |
1516 | * The active_mmu_pages list is the FIFO list, do not move the | |
1517 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1518 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1519 | */ | |
67052b35 | 1520 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1521 | sp->parent_ptes = 0; |
1522 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1523 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1524 | return sp; | |
ad8cfbe3 MT |
1525 | } |
1526 | ||
67052b35 | 1527 | static void mark_unsync(u64 *spte); |
1047df1f | 1528 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1529 | { |
67052b35 | 1530 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1531 | } |
1532 | ||
67052b35 | 1533 | static void mark_unsync(u64 *spte) |
0074ff63 | 1534 | { |
67052b35 | 1535 | struct kvm_mmu_page *sp; |
1047df1f | 1536 | unsigned int index; |
0074ff63 | 1537 | |
67052b35 | 1538 | sp = page_header(__pa(spte)); |
1047df1f XG |
1539 | index = spte - sp->spt; |
1540 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1541 | return; |
1047df1f | 1542 | if (sp->unsync_children++) |
0074ff63 | 1543 | return; |
1047df1f | 1544 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1545 | } |
1546 | ||
e8bc217a | 1547 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1548 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1549 | { |
1550 | return 1; | |
1551 | } | |
1552 | ||
a7052897 MT |
1553 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1554 | { | |
1555 | } | |
1556 | ||
0f53b5b1 XG |
1557 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1558 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1559 | const void *pte) |
0f53b5b1 XG |
1560 | { |
1561 | WARN_ON(1); | |
1562 | } | |
1563 | ||
60c8aec6 MT |
1564 | #define KVM_PAGE_ARRAY_NR 16 |
1565 | ||
1566 | struct kvm_mmu_pages { | |
1567 | struct mmu_page_and_offset { | |
1568 | struct kvm_mmu_page *sp; | |
1569 | unsigned int idx; | |
1570 | } page[KVM_PAGE_ARRAY_NR]; | |
1571 | unsigned int nr; | |
1572 | }; | |
1573 | ||
cded19f3 HE |
1574 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1575 | int idx) | |
4731d4c7 | 1576 | { |
60c8aec6 | 1577 | int i; |
4731d4c7 | 1578 | |
60c8aec6 MT |
1579 | if (sp->unsync) |
1580 | for (i=0; i < pvec->nr; i++) | |
1581 | if (pvec->page[i].sp == sp) | |
1582 | return 0; | |
1583 | ||
1584 | pvec->page[pvec->nr].sp = sp; | |
1585 | pvec->page[pvec->nr].idx = idx; | |
1586 | pvec->nr++; | |
1587 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1588 | } | |
1589 | ||
1590 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1591 | struct kvm_mmu_pages *pvec) | |
1592 | { | |
1593 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1594 | |
37178b8b | 1595 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1596 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1597 | u64 ent = sp->spt[i]; |
1598 | ||
7a8f1a74 XG |
1599 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1600 | goto clear_child_bitmap; | |
1601 | ||
1602 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1603 | ||
1604 | if (child->unsync_children) { | |
1605 | if (mmu_pages_add(pvec, child, i)) | |
1606 | return -ENOSPC; | |
1607 | ||
1608 | ret = __mmu_unsync_walk(child, pvec); | |
1609 | if (!ret) | |
1610 | goto clear_child_bitmap; | |
1611 | else if (ret > 0) | |
1612 | nr_unsync_leaf += ret; | |
1613 | else | |
1614 | return ret; | |
1615 | } else if (child->unsync) { | |
1616 | nr_unsync_leaf++; | |
1617 | if (mmu_pages_add(pvec, child, i)) | |
1618 | return -ENOSPC; | |
1619 | } else | |
1620 | goto clear_child_bitmap; | |
1621 | ||
1622 | continue; | |
1623 | ||
1624 | clear_child_bitmap: | |
1625 | __clear_bit(i, sp->unsync_child_bitmap); | |
1626 | sp->unsync_children--; | |
1627 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1628 | } |
1629 | ||
4731d4c7 | 1630 | |
60c8aec6 MT |
1631 | return nr_unsync_leaf; |
1632 | } | |
1633 | ||
1634 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1635 | struct kvm_mmu_pages *pvec) | |
1636 | { | |
1637 | if (!sp->unsync_children) | |
1638 | return 0; | |
1639 | ||
1640 | mmu_pages_add(pvec, sp, 0); | |
1641 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1642 | } |
1643 | ||
4731d4c7 MT |
1644 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1645 | { | |
1646 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1647 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1648 | sp->unsync = 0; |
1649 | --kvm->stat.mmu_unsync; | |
1650 | } | |
1651 | ||
7775834a XG |
1652 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1653 | struct list_head *invalid_list); | |
1654 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1655 | struct list_head *invalid_list); | |
4731d4c7 | 1656 | |
f34d251d XG |
1657 | /* |
1658 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1659 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1660 | * since it has been deleted from active_mmu_pages but still can be found | |
1661 | * at hast list. | |
1662 | * | |
1663 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1664 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1665 | * all the obsolete pages. | |
1666 | */ | |
1044b030 TY |
1667 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1668 | hlist_for_each_entry(_sp, \ | |
1669 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1670 | if ((_sp)->gfn != (_gfn)) {} else | |
1671 | ||
1672 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1673 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1674 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1675 | |
f918b443 | 1676 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1677 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1678 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1679 | { |
5b7e0102 | 1680 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1681 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1682 | return 1; |
1683 | } | |
1684 | ||
f918b443 | 1685 | if (clear_unsync) |
1d9dc7e0 | 1686 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1687 | |
a4a8e6f7 | 1688 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1689 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1690 | return 1; |
1691 | } | |
1692 | ||
1693 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1694 | return 0; |
1695 | } | |
1696 | ||
1d9dc7e0 XG |
1697 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1698 | struct kvm_mmu_page *sp) | |
1699 | { | |
d98ba053 | 1700 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1701 | int ret; |
1702 | ||
d98ba053 | 1703 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1704 | if (ret) |
d98ba053 XG |
1705 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1706 | ||
1d9dc7e0 XG |
1707 | return ret; |
1708 | } | |
1709 | ||
e37fa785 XG |
1710 | #ifdef CONFIG_KVM_MMU_AUDIT |
1711 | #include "mmu_audit.c" | |
1712 | #else | |
1713 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1714 | static void mmu_audit_disable(void) { } | |
1715 | #endif | |
1716 | ||
d98ba053 XG |
1717 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1718 | struct list_head *invalid_list) | |
1d9dc7e0 | 1719 | { |
d98ba053 | 1720 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1721 | } |
1722 | ||
9f1a122f XG |
1723 | /* @gfn should be write-protected at the call site */ |
1724 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1725 | { | |
9f1a122f | 1726 | struct kvm_mmu_page *s; |
d98ba053 | 1727 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1728 | bool flush = false; |
1729 | ||
b67bfe0d | 1730 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1731 | if (!s->unsync) |
9f1a122f XG |
1732 | continue; |
1733 | ||
1734 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1735 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1736 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1737 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1738 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1739 | continue; |
1740 | } | |
9f1a122f XG |
1741 | flush = true; |
1742 | } | |
1743 | ||
d98ba053 | 1744 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1745 | if (flush) |
1746 | kvm_mmu_flush_tlb(vcpu); | |
1747 | } | |
1748 | ||
60c8aec6 MT |
1749 | struct mmu_page_path { |
1750 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1751 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1752 | }; |
1753 | ||
60c8aec6 MT |
1754 | #define for_each_sp(pvec, sp, parents, i) \ |
1755 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1756 | sp = pvec.page[i].sp; \ | |
1757 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1758 | i = mmu_pages_next(&pvec, &parents, i)) | |
1759 | ||
cded19f3 HE |
1760 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1761 | struct mmu_page_path *parents, | |
1762 | int i) | |
60c8aec6 MT |
1763 | { |
1764 | int n; | |
1765 | ||
1766 | for (n = i+1; n < pvec->nr; n++) { | |
1767 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1768 | ||
1769 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1770 | parents->idx[0] = pvec->page[n].idx; | |
1771 | return n; | |
1772 | } | |
1773 | ||
1774 | parents->parent[sp->role.level-2] = sp; | |
1775 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1776 | } | |
1777 | ||
1778 | return n; | |
1779 | } | |
1780 | ||
cded19f3 | 1781 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1782 | { |
60c8aec6 MT |
1783 | struct kvm_mmu_page *sp; |
1784 | unsigned int level = 0; | |
1785 | ||
1786 | do { | |
1787 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1788 | |
60c8aec6 MT |
1789 | sp = parents->parent[level]; |
1790 | if (!sp) | |
1791 | return; | |
1792 | ||
1793 | --sp->unsync_children; | |
1794 | WARN_ON((int)sp->unsync_children < 0); | |
1795 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1796 | level++; | |
1797 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1798 | } |
1799 | ||
60c8aec6 MT |
1800 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1801 | struct mmu_page_path *parents, | |
1802 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1803 | { |
60c8aec6 MT |
1804 | parents->parent[parent->role.level-1] = NULL; |
1805 | pvec->nr = 0; | |
1806 | } | |
4731d4c7 | 1807 | |
60c8aec6 MT |
1808 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1809 | struct kvm_mmu_page *parent) | |
1810 | { | |
1811 | int i; | |
1812 | struct kvm_mmu_page *sp; | |
1813 | struct mmu_page_path parents; | |
1814 | struct kvm_mmu_pages pages; | |
d98ba053 | 1815 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1816 | |
1817 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1818 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1819 | bool protected = false; |
b1a36821 MT |
1820 | |
1821 | for_each_sp(pages, sp, parents, i) | |
1822 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1823 | ||
1824 | if (protected) | |
1825 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1826 | ||
60c8aec6 | 1827 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1828 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1829 | mmu_pages_clear_parents(&parents); |
1830 | } | |
d98ba053 | 1831 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1832 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1833 | kvm_mmu_pages_init(parent, &parents, &pages); |
1834 | } | |
4731d4c7 MT |
1835 | } |
1836 | ||
c3707958 XG |
1837 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1838 | { | |
1839 | int i; | |
1840 | ||
1841 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1842 | sp->spt[i] = 0ull; | |
1843 | } | |
1844 | ||
a30f47cb XG |
1845 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1846 | { | |
1847 | sp->write_flooding_count = 0; | |
1848 | } | |
1849 | ||
1850 | static void clear_sp_write_flooding_count(u64 *spte) | |
1851 | { | |
1852 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1853 | ||
1854 | __clear_sp_write_flooding_count(sp); | |
1855 | } | |
1856 | ||
5304b8d3 XG |
1857 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
1858 | { | |
1859 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
1860 | } | |
1861 | ||
cea0f0e7 AK |
1862 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1863 | gfn_t gfn, | |
1864 | gva_t gaddr, | |
1865 | unsigned level, | |
f6e2c02b | 1866 | int direct, |
41074d07 | 1867 | unsigned access, |
f7d9c7b7 | 1868 | u64 *parent_pte) |
cea0f0e7 AK |
1869 | { |
1870 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1871 | unsigned quadrant; |
9f1a122f | 1872 | struct kvm_mmu_page *sp; |
9f1a122f | 1873 | bool need_sync = false; |
cea0f0e7 | 1874 | |
a770f6f2 | 1875 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1876 | role.level = level; |
f6e2c02b | 1877 | role.direct = direct; |
84b0c8c6 | 1878 | if (role.direct) |
5b7e0102 | 1879 | role.cr4_pae = 0; |
41074d07 | 1880 | role.access = access; |
c5a78f2b JR |
1881 | if (!vcpu->arch.mmu.direct_map |
1882 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1883 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1884 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1885 | role.quadrant = quadrant; | |
1886 | } | |
b67bfe0d | 1887 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
1888 | if (is_obsolete_sp(vcpu->kvm, sp)) |
1889 | continue; | |
1890 | ||
7ae680eb XG |
1891 | if (!need_sync && sp->unsync) |
1892 | need_sync = true; | |
4731d4c7 | 1893 | |
7ae680eb XG |
1894 | if (sp->role.word != role.word) |
1895 | continue; | |
4731d4c7 | 1896 | |
7ae680eb XG |
1897 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1898 | break; | |
e02aa901 | 1899 | |
7ae680eb XG |
1900 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1901 | if (sp->unsync_children) { | |
a8eeb04a | 1902 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1903 | kvm_mmu_mark_parents_unsync(sp); |
1904 | } else if (sp->unsync) | |
1905 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1906 | |
a30f47cb | 1907 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1908 | trace_kvm_mmu_get_page(sp, false); |
1909 | return sp; | |
1910 | } | |
dfc5aa00 | 1911 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1912 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1913 | if (!sp) |
1914 | return sp; | |
4db35314 AK |
1915 | sp->gfn = gfn; |
1916 | sp->role = role; | |
7ae680eb XG |
1917 | hlist_add_head(&sp->hash_link, |
1918 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1919 | if (!direct) { |
b1a36821 MT |
1920 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1921 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1922 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1923 | kvm_sync_pages(vcpu, gfn); | |
1924 | ||
4731d4c7 MT |
1925 | account_shadowed(vcpu->kvm, gfn); |
1926 | } | |
5304b8d3 | 1927 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
c3707958 | 1928 | init_shadow_page_table(sp); |
f691fe1d | 1929 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1930 | return sp; |
cea0f0e7 AK |
1931 | } |
1932 | ||
2d11123a AK |
1933 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1934 | struct kvm_vcpu *vcpu, u64 addr) | |
1935 | { | |
1936 | iterator->addr = addr; | |
1937 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1938 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1939 | |
1940 | if (iterator->level == PT64_ROOT_LEVEL && | |
1941 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1942 | !vcpu->arch.mmu.direct_map) | |
1943 | --iterator->level; | |
1944 | ||
2d11123a AK |
1945 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1946 | iterator->shadow_addr | |
1947 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1948 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1949 | --iterator->level; | |
1950 | if (!iterator->shadow_addr) | |
1951 | iterator->level = 0; | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1956 | { | |
1957 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1958 | return false; | |
4d88954d | 1959 | |
2d11123a AK |
1960 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1961 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1962 | return true; | |
1963 | } | |
1964 | ||
c2a2ac2b XG |
1965 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1966 | u64 spte) | |
2d11123a | 1967 | { |
c2a2ac2b | 1968 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1969 | iterator->level = 0; |
1970 | return; | |
1971 | } | |
1972 | ||
c2a2ac2b | 1973 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1974 | --iterator->level; |
1975 | } | |
1976 | ||
c2a2ac2b XG |
1977 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1978 | { | |
1979 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1980 | } | |
1981 | ||
32ef26a3 AK |
1982 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1983 | { | |
1984 | u64 spte; | |
1985 | ||
24db2734 XG |
1986 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
1987 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; | |
1988 | ||
1df9f2dc | 1989 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1990 | } |
1991 | ||
a357bd22 AK |
1992 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1993 | unsigned direct_access) | |
1994 | { | |
1995 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1996 | struct kvm_mmu_page *child; | |
1997 | ||
1998 | /* | |
1999 | * For the direct sp, if the guest pte's dirty bit | |
2000 | * changed form clean to dirty, it will corrupt the | |
2001 | * sp's access: allow writable in the read-only sp, | |
2002 | * so we should update the spte at this point to get | |
2003 | * a new sp with the correct access. | |
2004 | */ | |
2005 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2006 | if (child->role.access == direct_access) | |
2007 | return; | |
2008 | ||
bcdd9a93 | 2009 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2010 | kvm_flush_remote_tlbs(vcpu->kvm); |
2011 | } | |
2012 | } | |
2013 | ||
505aef8f | 2014 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2015 | u64 *spte) |
2016 | { | |
2017 | u64 pte; | |
2018 | struct kvm_mmu_page *child; | |
2019 | ||
2020 | pte = *spte; | |
2021 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2022 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2023 | drop_spte(kvm, spte); |
505aef8f XG |
2024 | if (is_large_pte(pte)) |
2025 | --kvm->stat.lpages; | |
2026 | } else { | |
38e3b2b2 | 2027 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2028 | drop_parent_pte(child, spte); |
38e3b2b2 | 2029 | } |
505aef8f XG |
2030 | return true; |
2031 | } | |
2032 | ||
2033 | if (is_mmio_spte(pte)) | |
ce88decf | 2034 | mmu_spte_clear_no_track(spte); |
c3707958 | 2035 | |
505aef8f | 2036 | return false; |
38e3b2b2 XG |
2037 | } |
2038 | ||
90cb0529 | 2039 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2040 | struct kvm_mmu_page *sp) |
a436036b | 2041 | { |
697fe2e2 | 2042 | unsigned i; |
697fe2e2 | 2043 | |
38e3b2b2 XG |
2044 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2045 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2046 | } |
2047 | ||
4db35314 | 2048 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2049 | { |
4db35314 | 2050 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2051 | } |
2052 | ||
31aa2b44 | 2053 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2054 | { |
1e3f42f0 TY |
2055 | u64 *sptep; |
2056 | struct rmap_iterator iter; | |
a436036b | 2057 | |
1e3f42f0 TY |
2058 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2059 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2060 | } |
2061 | ||
60c8aec6 | 2062 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2063 | struct kvm_mmu_page *parent, |
2064 | struct list_head *invalid_list) | |
4731d4c7 | 2065 | { |
60c8aec6 MT |
2066 | int i, zapped = 0; |
2067 | struct mmu_page_path parents; | |
2068 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2069 | |
60c8aec6 | 2070 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2071 | return 0; |
60c8aec6 MT |
2072 | |
2073 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2074 | while (mmu_unsync_walk(parent, &pages)) { | |
2075 | struct kvm_mmu_page *sp; | |
2076 | ||
2077 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2078 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2079 | mmu_pages_clear_parents(&parents); |
77662e00 | 2080 | zapped++; |
60c8aec6 | 2081 | } |
60c8aec6 MT |
2082 | kvm_mmu_pages_init(parent, &parents, &pages); |
2083 | } | |
2084 | ||
2085 | return zapped; | |
4731d4c7 MT |
2086 | } |
2087 | ||
7775834a XG |
2088 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2089 | struct list_head *invalid_list) | |
31aa2b44 | 2090 | { |
4731d4c7 | 2091 | int ret; |
f691fe1d | 2092 | |
7775834a | 2093 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2094 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2095 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2096 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2097 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2098 | |
f6e2c02b | 2099 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2100 | unaccount_shadowed(kvm, sp->gfn); |
5304b8d3 | 2101 | |
4731d4c7 MT |
2102 | if (sp->unsync) |
2103 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2104 | if (!sp->root_count) { |
54a4f023 GJ |
2105 | /* Count self */ |
2106 | ret++; | |
7775834a | 2107 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2108 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2109 | } else { |
5b5c6a5a | 2110 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2111 | |
2112 | /* | |
2113 | * The obsolete pages can not be used on any vcpus. | |
2114 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2115 | */ | |
2116 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2117 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2118 | } |
7775834a XG |
2119 | |
2120 | sp->role.invalid = 1; | |
4731d4c7 | 2121 | return ret; |
a436036b AK |
2122 | } |
2123 | ||
7775834a XG |
2124 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2125 | struct list_head *invalid_list) | |
2126 | { | |
945315b9 | 2127 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2128 | |
2129 | if (list_empty(invalid_list)) | |
2130 | return; | |
2131 | ||
c142786c AK |
2132 | /* |
2133 | * wmb: make sure everyone sees our modifications to the page tables | |
2134 | * rmb: make sure we see changes to vcpu->mode | |
2135 | */ | |
2136 | smp_mb(); | |
4f022648 | 2137 | |
c142786c AK |
2138 | /* |
2139 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2140 | * page table walks. | |
2141 | */ | |
2142 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2143 | |
945315b9 | 2144 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2145 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2146 | kvm_mmu_free_page(sp); |
945315b9 | 2147 | } |
7775834a XG |
2148 | } |
2149 | ||
5da59607 TY |
2150 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2151 | struct list_head *invalid_list) | |
2152 | { | |
2153 | struct kvm_mmu_page *sp; | |
2154 | ||
2155 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2156 | return false; | |
2157 | ||
2158 | sp = list_entry(kvm->arch.active_mmu_pages.prev, | |
2159 | struct kvm_mmu_page, link); | |
2160 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
2161 | ||
2162 | return true; | |
2163 | } | |
2164 | ||
82ce2c96 IE |
2165 | /* |
2166 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2167 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2168 | */ |
49d5ca26 | 2169 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2170 | { |
d98ba053 | 2171 | LIST_HEAD(invalid_list); |
82ce2c96 | 2172 | |
b34cb590 TY |
2173 | spin_lock(&kvm->mmu_lock); |
2174 | ||
49d5ca26 | 2175 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2176 | /* Need to free some mmu pages to achieve the goal. */ |
2177 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2178 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2179 | break; | |
82ce2c96 | 2180 | |
aa6bd187 | 2181 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2182 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2183 | } |
82ce2c96 | 2184 | |
49d5ca26 | 2185 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2186 | |
2187 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2188 | } |
2189 | ||
1cb3f3ae | 2190 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2191 | { |
4db35314 | 2192 | struct kvm_mmu_page *sp; |
d98ba053 | 2193 | LIST_HEAD(invalid_list); |
a436036b AK |
2194 | int r; |
2195 | ||
9ad17b10 | 2196 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2197 | r = 0; |
1cb3f3ae | 2198 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2199 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2200 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2201 | sp->role.word); |
2202 | r = 1; | |
f41d335a | 2203 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2204 | } |
d98ba053 | 2205 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2206 | spin_unlock(&kvm->mmu_lock); |
2207 | ||
a436036b | 2208 | return r; |
cea0f0e7 | 2209 | } |
1cb3f3ae | 2210 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2211 | |
74be52e3 SY |
2212 | /* |
2213 | * The function is based on mtrr_type_lookup() in | |
2214 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2215 | */ | |
2216 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2217 | u64 start, u64 end) | |
2218 | { | |
2219 | int i; | |
2220 | u64 base, mask; | |
2221 | u8 prev_match, curr_match; | |
2222 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2223 | ||
2224 | if (!mtrr_state->enabled) | |
2225 | return 0xFF; | |
2226 | ||
2227 | /* Make end inclusive end, instead of exclusive */ | |
2228 | end--; | |
2229 | ||
2230 | /* Look in fixed ranges. Just return the type as per start */ | |
2231 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2232 | int idx; | |
2233 | ||
2234 | if (start < 0x80000) { | |
2235 | idx = 0; | |
2236 | idx += (start >> 16); | |
2237 | return mtrr_state->fixed_ranges[idx]; | |
2238 | } else if (start < 0xC0000) { | |
2239 | idx = 1 * 8; | |
2240 | idx += ((start - 0x80000) >> 14); | |
2241 | return mtrr_state->fixed_ranges[idx]; | |
2242 | } else if (start < 0x1000000) { | |
2243 | idx = 3 * 8; | |
2244 | idx += ((start - 0xC0000) >> 12); | |
2245 | return mtrr_state->fixed_ranges[idx]; | |
2246 | } | |
2247 | } | |
2248 | ||
2249 | /* | |
2250 | * Look in variable ranges | |
2251 | * Look of multiple ranges matching this address and pick type | |
2252 | * as per MTRR precedence | |
2253 | */ | |
2254 | if (!(mtrr_state->enabled & 2)) | |
2255 | return mtrr_state->def_type; | |
2256 | ||
2257 | prev_match = 0xFF; | |
2258 | for (i = 0; i < num_var_ranges; ++i) { | |
2259 | unsigned short start_state, end_state; | |
2260 | ||
2261 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2262 | continue; | |
2263 | ||
2264 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2265 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2266 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2267 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2268 | ||
2269 | start_state = ((start & mask) == (base & mask)); | |
2270 | end_state = ((end & mask) == (base & mask)); | |
2271 | if (start_state != end_state) | |
2272 | return 0xFE; | |
2273 | ||
2274 | if ((start & mask) != (base & mask)) | |
2275 | continue; | |
2276 | ||
2277 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2278 | if (prev_match == 0xFF) { | |
2279 | prev_match = curr_match; | |
2280 | continue; | |
2281 | } | |
2282 | ||
2283 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2284 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2285 | return MTRR_TYPE_UNCACHABLE; | |
2286 | ||
2287 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2288 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2289 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2290 | curr_match == MTRR_TYPE_WRBACK)) { | |
2291 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2292 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2293 | } | |
2294 | ||
2295 | if (prev_match != curr_match) | |
2296 | return MTRR_TYPE_UNCACHABLE; | |
2297 | } | |
2298 | ||
2299 | if (prev_match != 0xFF) | |
2300 | return prev_match; | |
2301 | ||
2302 | return mtrr_state->def_type; | |
2303 | } | |
2304 | ||
4b12f0de | 2305 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2306 | { |
2307 | u8 mtrr; | |
2308 | ||
2309 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2310 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2311 | if (mtrr == 0xfe || mtrr == 0xff) | |
2312 | mtrr = MTRR_TYPE_WRBACK; | |
2313 | return mtrr; | |
2314 | } | |
4b12f0de | 2315 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2316 | |
9cf5cf5a XG |
2317 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2318 | { | |
2319 | trace_kvm_mmu_unsync_page(sp); | |
2320 | ++vcpu->kvm->stat.mmu_unsync; | |
2321 | sp->unsync = 1; | |
2322 | ||
2323 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2324 | } |
2325 | ||
2326 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2327 | { |
4731d4c7 | 2328 | struct kvm_mmu_page *s; |
9cf5cf5a | 2329 | |
b67bfe0d | 2330 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2331 | if (s->unsync) |
4731d4c7 | 2332 | continue; |
9cf5cf5a XG |
2333 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2334 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2335 | } |
4731d4c7 MT |
2336 | } |
2337 | ||
2338 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2339 | bool can_unsync) | |
2340 | { | |
9cf5cf5a | 2341 | struct kvm_mmu_page *s; |
9cf5cf5a XG |
2342 | bool need_unsync = false; |
2343 | ||
b67bfe0d | 2344 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
36a2e677 XG |
2345 | if (!can_unsync) |
2346 | return 1; | |
2347 | ||
9cf5cf5a | 2348 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2349 | return 1; |
9cf5cf5a | 2350 | |
9bb4f6b1 | 2351 | if (!s->unsync) |
9cf5cf5a | 2352 | need_unsync = true; |
4731d4c7 | 2353 | } |
9cf5cf5a XG |
2354 | if (need_unsync) |
2355 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2356 | return 0; |
2357 | } | |
2358 | ||
d555c333 | 2359 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2360 | unsigned pte_access, int level, |
c2d0ee46 | 2361 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2362 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2363 | { |
6e7d0354 | 2364 | u64 spte; |
1e73f9dd | 2365 | int ret = 0; |
64d4d521 | 2366 | |
ce88decf XG |
2367 | if (set_mmio_spte(sptep, gfn, pfn, pte_access)) |
2368 | return 0; | |
2369 | ||
982c2565 | 2370 | spte = PT_PRESENT_MASK; |
947da538 | 2371 | if (!speculative) |
3201b5d9 | 2372 | spte |= shadow_accessed_mask; |
640d9b0d | 2373 | |
7b52345e SY |
2374 | if (pte_access & ACC_EXEC_MASK) |
2375 | spte |= shadow_x_mask; | |
2376 | else | |
2377 | spte |= shadow_nx_mask; | |
49fde340 | 2378 | |
1c4f1fd6 | 2379 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2380 | spte |= shadow_user_mask; |
49fde340 | 2381 | |
852e3c19 | 2382 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2383 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2384 | if (tdp_enabled) |
4b12f0de SY |
2385 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2386 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2387 | |
9bdbba13 | 2388 | if (host_writable) |
1403283a | 2389 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2390 | else |
2391 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2392 | |
35149e21 | 2393 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2394 | |
c2288505 | 2395 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2396 | |
c2193463 | 2397 | /* |
7751babd XG |
2398 | * Other vcpu creates new sp in the window between |
2399 | * mapping_level() and acquiring mmu-lock. We can | |
2400 | * allow guest to retry the access, the mapping can | |
2401 | * be fixed if guest refault. | |
c2193463 | 2402 | */ |
852e3c19 | 2403 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2404 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2405 | goto done; |
38187c83 | 2406 | |
49fde340 | 2407 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2408 | |
ecc5589f MT |
2409 | /* |
2410 | * Optimization: for pte sync, if spte was writable the hash | |
2411 | * lookup is unnecessary (and expensive). Write protection | |
2412 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2413 | * Same reasoning can be applied to dirty page accounting. | |
2414 | */ | |
8dae4445 | 2415 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2416 | goto set_pte; |
2417 | ||
4731d4c7 | 2418 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2419 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2420 | __func__, gfn); |
1e73f9dd | 2421 | ret = 1; |
1c4f1fd6 | 2422 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2423 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2424 | } |
2425 | } | |
2426 | ||
1c4f1fd6 AK |
2427 | if (pte_access & ACC_WRITE_MASK) |
2428 | mark_page_dirty(vcpu->kvm, gfn); | |
2429 | ||
38187c83 | 2430 | set_pte: |
6e7d0354 | 2431 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2432 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2433 | done: |
1e73f9dd MT |
2434 | return ret; |
2435 | } | |
2436 | ||
d555c333 | 2437 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
f7616203 XG |
2438 | unsigned pte_access, int write_fault, int *emulate, |
2439 | int level, gfn_t gfn, pfn_t pfn, bool speculative, | |
2440 | bool host_writable) | |
1e73f9dd MT |
2441 | { |
2442 | int was_rmapped = 0; | |
53a27b39 | 2443 | int rmap_count; |
1e73f9dd | 2444 | |
f7616203 XG |
2445 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2446 | *sptep, write_fault, gfn); | |
1e73f9dd | 2447 | |
d555c333 | 2448 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2449 | /* |
2450 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2451 | * the parent of the now unreachable PTE. | |
2452 | */ | |
852e3c19 JR |
2453 | if (level > PT_PAGE_TABLE_LEVEL && |
2454 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2455 | struct kvm_mmu_page *child; |
d555c333 | 2456 | u64 pte = *sptep; |
1e73f9dd MT |
2457 | |
2458 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2459 | drop_parent_pte(child, sptep); |
3be2264b | 2460 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2461 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2462 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2463 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2464 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2465 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2466 | } else |
2467 | was_rmapped = 1; | |
1e73f9dd | 2468 | } |
852e3c19 | 2469 | |
c2288505 XG |
2470 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2471 | true, host_writable)) { | |
1e73f9dd | 2472 | if (write_fault) |
b90a0e6c | 2473 | *emulate = 1; |
5304efde | 2474 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2475 | } |
1e73f9dd | 2476 | |
ce88decf XG |
2477 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2478 | *emulate = 1; | |
2479 | ||
d555c333 | 2480 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2481 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2482 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2483 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2484 | *sptep, sptep); | |
d555c333 | 2485 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2486 | ++vcpu->kvm->stat.lpages; |
2487 | ||
ffb61bb3 | 2488 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2489 | if (!was_rmapped) { |
2490 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2491 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2492 | rmap_recycle(vcpu, sptep, gfn); | |
2493 | } | |
1c4f1fd6 | 2494 | } |
cb9aaa30 | 2495 | |
f3ac1a4b | 2496 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2497 | } |
2498 | ||
6aa8b732 AK |
2499 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2500 | { | |
e676505a | 2501 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2502 | } |
2503 | ||
a052b42b XG |
2504 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
2505 | { | |
2506 | int bit7; | |
2507 | ||
2508 | bit7 = (gpte >> 7) & 1; | |
2509 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
2510 | } | |
2511 | ||
957ed9ef XG |
2512 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2513 | bool no_dirty_log) | |
2514 | { | |
2515 | struct kvm_memory_slot *slot; | |
957ed9ef | 2516 | |
5d163b1c | 2517 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2518 | if (!slot) |
6c8ee57b | 2519 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2520 | |
037d92dc | 2521 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2522 | } |
2523 | ||
a052b42b XG |
2524 | static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu, |
2525 | struct kvm_mmu_page *sp, u64 *spte, | |
2526 | u64 gpte) | |
2527 | { | |
2528 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
2529 | goto no_present; | |
2530 | ||
2531 | if (!is_present_gpte(gpte)) | |
2532 | goto no_present; | |
2533 | ||
2534 | if (!(gpte & PT_ACCESSED_MASK)) | |
2535 | goto no_present; | |
2536 | ||
2537 | return false; | |
2538 | ||
2539 | no_present: | |
2540 | drop_spte(vcpu->kvm, spte); | |
2541 | return true; | |
2542 | } | |
2543 | ||
957ed9ef XG |
2544 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, |
2545 | struct kvm_mmu_page *sp, | |
2546 | u64 *start, u64 *end) | |
2547 | { | |
2548 | struct page *pages[PTE_PREFETCH_NUM]; | |
2549 | unsigned access = sp->role.access; | |
2550 | int i, ret; | |
2551 | gfn_t gfn; | |
2552 | ||
2553 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2554 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2555 | return -1; |
2556 | ||
2557 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2558 | if (ret <= 0) | |
2559 | return -1; | |
2560 | ||
2561 | for (i = 0; i < ret; i++, gfn++, start++) | |
f7616203 | 2562 | mmu_set_spte(vcpu, start, access, 0, NULL, |
c2288505 XG |
2563 | sp->role.level, gfn, page_to_pfn(pages[i]), |
2564 | true, true); | |
957ed9ef XG |
2565 | |
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2570 | struct kvm_mmu_page *sp, u64 *sptep) | |
2571 | { | |
2572 | u64 *spte, *start = NULL; | |
2573 | int i; | |
2574 | ||
2575 | WARN_ON(!sp->role.direct); | |
2576 | ||
2577 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2578 | spte = sp->spt + i; | |
2579 | ||
2580 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2581 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2582 | if (!start) |
2583 | continue; | |
2584 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2585 | break; | |
2586 | start = NULL; | |
2587 | } else if (!start) | |
2588 | start = spte; | |
2589 | } | |
2590 | } | |
2591 | ||
2592 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2593 | { | |
2594 | struct kvm_mmu_page *sp; | |
2595 | ||
2596 | /* | |
2597 | * Since it's no accessed bit on EPT, it's no way to | |
2598 | * distinguish between actually accessed translations | |
2599 | * and prefetched, so disable pte prefetch if EPT is | |
2600 | * enabled. | |
2601 | */ | |
2602 | if (!shadow_accessed_mask) | |
2603 | return; | |
2604 | ||
2605 | sp = page_header(__pa(sptep)); | |
2606 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2607 | return; | |
2608 | ||
2609 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2610 | } | |
2611 | ||
9f652d21 | 2612 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2613 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2614 | bool prefault) | |
140754bc | 2615 | { |
9f652d21 | 2616 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2617 | struct kvm_mmu_page *sp; |
b90a0e6c | 2618 | int emulate = 0; |
140754bc | 2619 | gfn_t pseudo_gfn; |
6aa8b732 | 2620 | |
9f652d21 | 2621 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2622 | if (iterator.level == level) { |
f7616203 | 2623 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
c2288505 XG |
2624 | write, &emulate, level, gfn, pfn, |
2625 | prefault, map_writable); | |
957ed9ef | 2626 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2627 | ++vcpu->stat.pf_fixed; |
2628 | break; | |
6aa8b732 AK |
2629 | } |
2630 | ||
c3707958 | 2631 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2632 | u64 base_addr = iterator.addr; |
2633 | ||
2634 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2635 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2636 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2637 | iterator.level - 1, | |
2638 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2639 | |
24db2734 | 2640 | link_shadow_page(iterator.sptep, sp); |
9f652d21 AK |
2641 | } |
2642 | } | |
b90a0e6c | 2643 | return emulate; |
6aa8b732 AK |
2644 | } |
2645 | ||
77db5cbd | 2646 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2647 | { |
77db5cbd HY |
2648 | siginfo_t info; |
2649 | ||
2650 | info.si_signo = SIGBUS; | |
2651 | info.si_errno = 0; | |
2652 | info.si_code = BUS_MCEERR_AR; | |
2653 | info.si_addr = (void __user *)address; | |
2654 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2655 | |
77db5cbd | 2656 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2657 | } |
2658 | ||
d7c55201 | 2659 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2660 | { |
4d8b81ab XG |
2661 | /* |
2662 | * Do not cache the mmio info caused by writing the readonly gfn | |
2663 | * into the spte otherwise read access on readonly gfn also can | |
2664 | * caused mmio page fault and treat it as mmio access. | |
2665 | * Return 1 to tell kvm to emulate it. | |
2666 | */ | |
2667 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2668 | return 1; | |
2669 | ||
e6c1502b | 2670 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2671 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2672 | return 0; |
d7c55201 | 2673 | } |
edba23e5 | 2674 | |
d7c55201 | 2675 | return -EFAULT; |
bf998156 HY |
2676 | } |
2677 | ||
936a5fe6 AA |
2678 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2679 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2680 | { | |
2681 | pfn_t pfn = *pfnp; | |
2682 | gfn_t gfn = *gfnp; | |
2683 | int level = *levelp; | |
2684 | ||
2685 | /* | |
2686 | * Check if it's a transparent hugepage. If this would be an | |
2687 | * hugetlbfs page, level wouldn't be set to | |
2688 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2689 | * here. | |
2690 | */ | |
81c52c56 | 2691 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2692 | level == PT_PAGE_TABLE_LEVEL && |
2693 | PageTransCompound(pfn_to_page(pfn)) && | |
2694 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2695 | unsigned long mask; | |
2696 | /* | |
2697 | * mmu_notifier_retry was successful and we hold the | |
2698 | * mmu_lock here, so the pmd can't become splitting | |
2699 | * from under us, and in turn | |
2700 | * __split_huge_page_refcount() can't run from under | |
2701 | * us and we can safely transfer the refcount from | |
2702 | * PG_tail to PG_head as we switch the pfn to tail to | |
2703 | * head. | |
2704 | */ | |
2705 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2706 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2707 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2708 | if (pfn & mask) { | |
2709 | gfn &= ~mask; | |
2710 | *gfnp = gfn; | |
2711 | kvm_release_pfn_clean(pfn); | |
2712 | pfn &= ~mask; | |
c3586667 | 2713 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2714 | *pfnp = pfn; |
2715 | } | |
2716 | } | |
2717 | } | |
2718 | ||
d7c55201 XG |
2719 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2720 | pfn_t pfn, unsigned access, int *ret_val) | |
2721 | { | |
2722 | bool ret = true; | |
2723 | ||
2724 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2725 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2726 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2727 | goto exit; | |
2728 | } | |
2729 | ||
ce88decf | 2730 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2731 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2732 | |
2733 | ret = false; | |
2734 | exit: | |
2735 | return ret; | |
2736 | } | |
2737 | ||
c7ba5b48 XG |
2738 | static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code) |
2739 | { | |
2740 | /* | |
2741 | * #PF can be fast only if the shadow page table is present and it | |
2742 | * is caused by write-protect, that means we just need change the | |
2743 | * W bit of the spte which can be done out of mmu-lock. | |
2744 | */ | |
2745 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2746 | !(error_code & PFERR_WRITE_MASK)) | |
2747 | return false; | |
2748 | ||
2749 | return true; | |
2750 | } | |
2751 | ||
2752 | static bool | |
2753 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) | |
2754 | { | |
2755 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
2756 | gfn_t gfn; | |
2757 | ||
2758 | WARN_ON(!sp->role.direct); | |
2759 | ||
2760 | /* | |
2761 | * The gfn of direct spte is stable since it is calculated | |
2762 | * by sp->gfn. | |
2763 | */ | |
2764 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2765 | ||
2766 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2767 | mark_page_dirty(vcpu->kvm, gfn); | |
2768 | ||
2769 | return true; | |
2770 | } | |
2771 | ||
2772 | /* | |
2773 | * Return value: | |
2774 | * - true: let the vcpu to access on the same address again. | |
2775 | * - false: let the real page fault path to fix it. | |
2776 | */ | |
2777 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2778 | u32 error_code) | |
2779 | { | |
2780 | struct kvm_shadow_walk_iterator iterator; | |
2781 | bool ret = false; | |
2782 | u64 spte = 0ull; | |
2783 | ||
2784 | if (!page_fault_can_be_fast(vcpu, error_code)) | |
2785 | return false; | |
2786 | ||
2787 | walk_shadow_page_lockless_begin(vcpu); | |
2788 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2789 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2790 | break; | |
2791 | ||
2792 | /* | |
2793 | * If the mapping has been changed, let the vcpu fault on the | |
2794 | * same address again. | |
2795 | */ | |
2796 | if (!is_rmap_spte(spte)) { | |
2797 | ret = true; | |
2798 | goto exit; | |
2799 | } | |
2800 | ||
2801 | if (!is_last_spte(spte, level)) | |
2802 | goto exit; | |
2803 | ||
2804 | /* | |
2805 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2806 | * | |
2807 | * Need not check the access of upper level table entries since | |
2808 | * they are always ACC_ALL. | |
2809 | */ | |
2810 | if (is_writable_pte(spte)) { | |
2811 | ret = true; | |
2812 | goto exit; | |
2813 | } | |
2814 | ||
2815 | /* | |
2816 | * Currently, to simplify the code, only the spte write-protected | |
2817 | * by dirty-log can be fast fixed. | |
2818 | */ | |
2819 | if (!spte_is_locklessly_modifiable(spte)) | |
2820 | goto exit; | |
2821 | ||
2822 | /* | |
2823 | * Currently, fast page fault only works for direct mapping since | |
2824 | * the gfn is not stable for indirect shadow page. | |
2825 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2826 | */ | |
2827 | ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); | |
2828 | exit: | |
a72faf25 XG |
2829 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2830 | spte, ret); | |
c7ba5b48 XG |
2831 | walk_shadow_page_lockless_end(vcpu); |
2832 | ||
2833 | return ret; | |
2834 | } | |
2835 | ||
78b2c54a | 2836 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe | 2837 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 2838 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 2839 | |
c7ba5b48 XG |
2840 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2841 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2842 | { |
2843 | int r; | |
852e3c19 | 2844 | int level; |
936a5fe6 | 2845 | int force_pt_level; |
35149e21 | 2846 | pfn_t pfn; |
e930bffe | 2847 | unsigned long mmu_seq; |
c7ba5b48 | 2848 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2849 | |
936a5fe6 AA |
2850 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2851 | if (likely(!force_pt_level)) { | |
2852 | level = mapping_level(vcpu, gfn); | |
2853 | /* | |
2854 | * This path builds a PAE pagetable - so we can map | |
2855 | * 2mb pages at maximum. Therefore check if the level | |
2856 | * is larger than that. | |
2857 | */ | |
2858 | if (level > PT_DIRECTORY_LEVEL) | |
2859 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2860 | |
936a5fe6 AA |
2861 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2862 | } else | |
2863 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2864 | |
c7ba5b48 XG |
2865 | if (fast_page_fault(vcpu, v, level, error_code)) |
2866 | return 0; | |
2867 | ||
e930bffe | 2868 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2869 | smp_rmb(); |
060c2abe | 2870 | |
78b2c54a | 2871 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2872 | return 0; |
aaee2c94 | 2873 | |
d7c55201 XG |
2874 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2875 | return r; | |
d196e343 | 2876 | |
aaee2c94 | 2877 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2878 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2879 | goto out_unlock; |
450e0b41 | 2880 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
2881 | if (likely(!force_pt_level)) |
2882 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2883 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2884 | prefault); | |
aaee2c94 MT |
2885 | spin_unlock(&vcpu->kvm->mmu_lock); |
2886 | ||
aaee2c94 | 2887 | |
10589a46 | 2888 | return r; |
e930bffe AA |
2889 | |
2890 | out_unlock: | |
2891 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2892 | kvm_release_pfn_clean(pfn); | |
2893 | return 0; | |
10589a46 MT |
2894 | } |
2895 | ||
2896 | ||
17ac10ad AK |
2897 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2898 | { | |
2899 | int i; | |
4db35314 | 2900 | struct kvm_mmu_page *sp; |
d98ba053 | 2901 | LIST_HEAD(invalid_list); |
17ac10ad | 2902 | |
ad312c7c | 2903 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2904 | return; |
35af577a | 2905 | |
81407ca5 JR |
2906 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2907 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2908 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2909 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2910 | |
35af577a | 2911 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
2912 | sp = page_header(root); |
2913 | --sp->root_count; | |
d98ba053 XG |
2914 | if (!sp->root_count && sp->role.invalid) { |
2915 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2916 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2917 | } | |
aaee2c94 | 2918 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 2919 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2920 | return; |
2921 | } | |
35af577a GN |
2922 | |
2923 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 2924 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2925 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2926 | |
417726a3 | 2927 | if (root) { |
417726a3 | 2928 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2929 | sp = page_header(root); |
2930 | --sp->root_count; | |
2e53d63a | 2931 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2932 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2933 | &invalid_list); | |
417726a3 | 2934 | } |
ad312c7c | 2935 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2936 | } |
d98ba053 | 2937 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2938 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2939 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2940 | } |
2941 | ||
8986ecc0 MT |
2942 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2943 | { | |
2944 | int ret = 0; | |
2945 | ||
2946 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2947 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2948 | ret = 1; |
2949 | } | |
2950 | ||
2951 | return ret; | |
2952 | } | |
2953 | ||
651dd37a JR |
2954 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2955 | { | |
2956 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2957 | unsigned i; |
651dd37a JR |
2958 | |
2959 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2960 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 2961 | make_mmu_pages_available(vcpu); |
651dd37a JR |
2962 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, |
2963 | 1, ACC_ALL, NULL); | |
2964 | ++sp->root_count; | |
2965 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2966 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2967 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2968 | for (i = 0; i < 4; ++i) { | |
2969 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2970 | ||
2971 | ASSERT(!VALID_PAGE(root)); | |
2972 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 2973 | make_mmu_pages_available(vcpu); |
649497d1 AK |
2974 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2975 | i << 30, | |
651dd37a JR |
2976 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2977 | NULL); | |
2978 | root = __pa(sp->spt); | |
2979 | ++sp->root_count; | |
2980 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2981 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2982 | } |
6292757f | 2983 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2984 | } else |
2985 | BUG(); | |
2986 | ||
2987 | return 0; | |
2988 | } | |
2989 | ||
2990 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2991 | { |
4db35314 | 2992 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2993 | u64 pdptr, pm_mask; |
2994 | gfn_t root_gfn; | |
2995 | int i; | |
3bb65a22 | 2996 | |
5777ed34 | 2997 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2998 | |
651dd37a JR |
2999 | if (mmu_check_root(vcpu, root_gfn)) |
3000 | return 1; | |
3001 | ||
3002 | /* | |
3003 | * Do we shadow a long mode page table? If so we need to | |
3004 | * write-protect the guests page table root. | |
3005 | */ | |
3006 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3007 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
3008 | |
3009 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 3010 | |
8facbbff | 3011 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3012 | make_mmu_pages_available(vcpu); |
651dd37a JR |
3013 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
3014 | 0, ACC_ALL, NULL); | |
4db35314 AK |
3015 | root = __pa(sp->spt); |
3016 | ++sp->root_count; | |
8facbbff | 3017 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3018 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3019 | return 0; |
17ac10ad | 3020 | } |
f87f9288 | 3021 | |
651dd37a JR |
3022 | /* |
3023 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3024 | * or a PAE 3-level page table. In either case we need to be aware that |
3025 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3026 | */ |
81407ca5 JR |
3027 | pm_mask = PT_PRESENT_MASK; |
3028 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3029 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3030 | ||
17ac10ad | 3031 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3032 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
3033 | |
3034 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 3035 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3036 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3037 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3038 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3039 | continue; |
3040 | } | |
6de4f3ad | 3041 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3042 | if (mmu_check_root(vcpu, root_gfn)) |
3043 | return 1; | |
5a7388c2 | 3044 | } |
8facbbff | 3045 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3046 | make_mmu_pages_available(vcpu); |
4db35314 | 3047 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3048 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3049 | ACC_ALL, NULL); |
4db35314 AK |
3050 | root = __pa(sp->spt); |
3051 | ++sp->root_count; | |
8facbbff AK |
3052 | spin_unlock(&vcpu->kvm->mmu_lock); |
3053 | ||
81407ca5 | 3054 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3055 | } |
6292757f | 3056 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3057 | |
3058 | /* | |
3059 | * If we shadow a 32 bit page table with a long mode page | |
3060 | * table we enter this path. | |
3061 | */ | |
3062 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3063 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3064 | /* | |
3065 | * The additional page necessary for this is only | |
3066 | * allocated on demand. | |
3067 | */ | |
3068 | ||
3069 | u64 *lm_root; | |
3070 | ||
3071 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3072 | if (lm_root == NULL) | |
3073 | return 1; | |
3074 | ||
3075 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3076 | ||
3077 | vcpu->arch.mmu.lm_root = lm_root; | |
3078 | } | |
3079 | ||
3080 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3081 | } | |
3082 | ||
8986ecc0 | 3083 | return 0; |
17ac10ad AK |
3084 | } |
3085 | ||
651dd37a JR |
3086 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3087 | { | |
3088 | if (vcpu->arch.mmu.direct_map) | |
3089 | return mmu_alloc_direct_roots(vcpu); | |
3090 | else | |
3091 | return mmu_alloc_shadow_roots(vcpu); | |
3092 | } | |
3093 | ||
0ba73cda MT |
3094 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3095 | { | |
3096 | int i; | |
3097 | struct kvm_mmu_page *sp; | |
3098 | ||
81407ca5 JR |
3099 | if (vcpu->arch.mmu.direct_map) |
3100 | return; | |
3101 | ||
0ba73cda MT |
3102 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3103 | return; | |
6903074c | 3104 | |
bebb106a | 3105 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 3106 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3107 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3108 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3109 | sp = page_header(root); | |
3110 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3111 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3112 | return; |
3113 | } | |
3114 | for (i = 0; i < 4; ++i) { | |
3115 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3116 | ||
8986ecc0 | 3117 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3118 | root &= PT64_BASE_ADDR_MASK; |
3119 | sp = page_header(root); | |
3120 | mmu_sync_children(vcpu, sp); | |
3121 | } | |
3122 | } | |
0375f7fa | 3123 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3124 | } |
3125 | ||
3126 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3127 | { | |
3128 | spin_lock(&vcpu->kvm->mmu_lock); | |
3129 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3130 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3131 | } |
3132 | ||
1871c602 | 3133 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3134 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3135 | { |
ab9ae313 AK |
3136 | if (exception) |
3137 | exception->error_code = 0; | |
6aa8b732 AK |
3138 | return vaddr; |
3139 | } | |
3140 | ||
6539e738 | 3141 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3142 | u32 access, |
3143 | struct x86_exception *exception) | |
6539e738 | 3144 | { |
ab9ae313 AK |
3145 | if (exception) |
3146 | exception->error_code = 0; | |
6539e738 JR |
3147 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
3148 | } | |
3149 | ||
ce88decf XG |
3150 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3151 | { | |
3152 | if (direct) | |
3153 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3154 | ||
3155 | return vcpu_match_mmio_gva(vcpu, addr); | |
3156 | } | |
3157 | ||
3158 | ||
3159 | /* | |
3160 | * On direct hosts, the last spte is only allows two states | |
3161 | * for mmio page fault: | |
3162 | * - It is the mmio spte | |
3163 | * - It is zapped or it is being zapped. | |
3164 | * | |
3165 | * This function completely checks the spte when the last spte | |
3166 | * is not the mmio spte. | |
3167 | */ | |
3168 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3169 | { | |
3170 | return __check_direct_spte_mmio_pf(spte); | |
3171 | } | |
3172 | ||
3173 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3174 | { | |
3175 | struct kvm_shadow_walk_iterator iterator; | |
3176 | u64 spte = 0ull; | |
3177 | ||
3178 | walk_shadow_page_lockless_begin(vcpu); | |
3179 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3180 | if (!is_shadow_present_pte(spte)) | |
3181 | break; | |
3182 | walk_shadow_page_lockless_end(vcpu); | |
3183 | ||
3184 | return spte; | |
3185 | } | |
3186 | ||
3187 | /* | |
3188 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
3189 | * directly, return 0 to let CPU fault again on the address, -1 is | |
3190 | * returned if bug is detected. | |
3191 | */ | |
3192 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
3193 | { | |
3194 | u64 spte; | |
3195 | ||
3196 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
3197 | return 1; | |
3198 | ||
3199 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3200 | ||
3201 | if (is_mmio_spte(spte)) { | |
3202 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3203 | unsigned access = get_mmio_spte_access(spte); | |
3204 | ||
3205 | if (direct) | |
3206 | addr = 0; | |
4f022648 XG |
3207 | |
3208 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
3209 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
3210 | return 1; | |
3211 | } | |
3212 | ||
3213 | /* | |
3214 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3215 | * it's a BUG if the gfn is not a mmio page. | |
3216 | */ | |
3217 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
3218 | return -1; | |
3219 | ||
3220 | /* | |
3221 | * If the page table is zapped by other cpus, let CPU fault again on | |
3222 | * the address. | |
3223 | */ | |
3224 | return 0; | |
3225 | } | |
3226 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3227 | ||
3228 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3229 | u32 error_code, bool direct) | |
3230 | { | |
3231 | int ret; | |
3232 | ||
3233 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
3234 | WARN_ON(ret < 0); | |
3235 | return ret; | |
3236 | } | |
3237 | ||
6aa8b732 | 3238 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3239 | u32 error_code, bool prefault) |
6aa8b732 | 3240 | { |
e833240f | 3241 | gfn_t gfn; |
e2dec939 | 3242 | int r; |
6aa8b732 | 3243 | |
b8688d51 | 3244 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3245 | |
3246 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3247 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3248 | ||
e2dec939 AK |
3249 | r = mmu_topup_memory_caches(vcpu); |
3250 | if (r) | |
3251 | return r; | |
714b93da | 3252 | |
6aa8b732 | 3253 | ASSERT(vcpu); |
ad312c7c | 3254 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3255 | |
e833240f | 3256 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3257 | |
e833240f | 3258 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3259 | error_code, gfn, prefault); |
6aa8b732 AK |
3260 | } |
3261 | ||
7e1fbeac | 3262 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3263 | { |
3264 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3265 | |
7c90705b | 3266 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3267 | arch.gfn = gfn; |
c4806acd | 3268 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3269 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3270 | |
3271 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3272 | } | |
3273 | ||
3274 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3275 | { | |
3276 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3277 | kvm_event_needs_reinjection(vcpu))) | |
3278 | return false; | |
3279 | ||
3280 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3281 | } | |
3282 | ||
78b2c54a | 3283 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3284 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3285 | { |
3286 | bool async; | |
3287 | ||
612819c3 | 3288 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3289 | |
3290 | if (!async) | |
3291 | return false; /* *pfn has correct page already */ | |
3292 | ||
78b2c54a | 3293 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3294 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3295 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3296 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3297 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3298 | return true; | |
3299 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3300 | return true; | |
3301 | } | |
3302 | ||
612819c3 | 3303 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3304 | |
3305 | return false; | |
3306 | } | |
3307 | ||
56028d08 | 3308 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3309 | bool prefault) |
fb72d167 | 3310 | { |
35149e21 | 3311 | pfn_t pfn; |
fb72d167 | 3312 | int r; |
852e3c19 | 3313 | int level; |
936a5fe6 | 3314 | int force_pt_level; |
05da4558 | 3315 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3316 | unsigned long mmu_seq; |
612819c3 MT |
3317 | int write = error_code & PFERR_WRITE_MASK; |
3318 | bool map_writable; | |
fb72d167 JR |
3319 | |
3320 | ASSERT(vcpu); | |
3321 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3322 | ||
ce88decf XG |
3323 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3324 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3325 | ||
fb72d167 JR |
3326 | r = mmu_topup_memory_caches(vcpu); |
3327 | if (r) | |
3328 | return r; | |
3329 | ||
936a5fe6 AA |
3330 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3331 | if (likely(!force_pt_level)) { | |
3332 | level = mapping_level(vcpu, gfn); | |
3333 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3334 | } else | |
3335 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3336 | |
c7ba5b48 XG |
3337 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3338 | return 0; | |
3339 | ||
e930bffe | 3340 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3341 | smp_rmb(); |
af585b92 | 3342 | |
78b2c54a | 3343 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3344 | return 0; |
3345 | ||
d7c55201 XG |
3346 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3347 | return r; | |
3348 | ||
fb72d167 | 3349 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3350 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3351 | goto out_unlock; |
450e0b41 | 3352 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3353 | if (likely(!force_pt_level)) |
3354 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3355 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3356 | level, gfn, pfn, prefault); |
fb72d167 | 3357 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3358 | |
3359 | return r; | |
e930bffe AA |
3360 | |
3361 | out_unlock: | |
3362 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3363 | kvm_release_pfn_clean(pfn); | |
3364 | return 0; | |
fb72d167 JR |
3365 | } |
3366 | ||
6aa8b732 AK |
3367 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3368 | { | |
17ac10ad | 3369 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3370 | } |
3371 | ||
52fde8df JR |
3372 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3373 | struct kvm_mmu *context) | |
6aa8b732 | 3374 | { |
6aa8b732 AK |
3375 | context->new_cr3 = nonpaging_new_cr3; |
3376 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3377 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3378 | context->free = nonpaging_free; | |
e8bc217a | 3379 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3380 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3381 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3382 | context->root_level = 0; |
6aa8b732 | 3383 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3384 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3385 | context->direct_map = true; |
2d48a985 | 3386 | context->nx = false; |
6aa8b732 AK |
3387 | return 0; |
3388 | } | |
3389 | ||
d835dfec | 3390 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3391 | { |
1165f5fe | 3392 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3393 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3394 | } |
3395 | ||
3396 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3397 | { | |
9f8fe504 | 3398 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3399 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3400 | } |
3401 | ||
5777ed34 JR |
3402 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3403 | { | |
9f8fe504 | 3404 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3405 | } |
3406 | ||
6389ee94 AK |
3407 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3408 | struct x86_exception *fault) | |
6aa8b732 | 3409 | { |
6389ee94 | 3410 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3411 | } |
3412 | ||
6aa8b732 AK |
3413 | static void paging_free(struct kvm_vcpu *vcpu) |
3414 | { | |
3415 | nonpaging_free(vcpu); | |
3416 | } | |
3417 | ||
8ea667f2 AK |
3418 | static inline void protect_clean_gpte(unsigned *access, unsigned gpte) |
3419 | { | |
3420 | unsigned mask; | |
3421 | ||
3422 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); | |
3423 | ||
3424 | mask = (unsigned)~ACC_WRITE_MASK; | |
3425 | /* Allow write access to dirty gptes */ | |
3426 | mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK; | |
3427 | *access &= mask; | |
3428 | } | |
3429 | ||
ce88decf XG |
3430 | static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access, |
3431 | int *nr_present) | |
3432 | { | |
3433 | if (unlikely(is_mmio_spte(*sptep))) { | |
3434 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3435 | mmu_spte_clear_no_track(sptep); | |
3436 | return true; | |
3437 | } | |
3438 | ||
3439 | (*nr_present)++; | |
3440 | mark_mmio_spte(sptep, gfn, access); | |
3441 | return true; | |
3442 | } | |
3443 | ||
3444 | return false; | |
3445 | } | |
3446 | ||
3d34adec AK |
3447 | static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte) |
3448 | { | |
3449 | unsigned access; | |
3450 | ||
3451 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
3452 | access &= ~(gpte >> PT64_NX_SHIFT); | |
3453 | ||
3454 | return access; | |
3455 | } | |
3456 | ||
6fd01b71 AK |
3457 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3458 | { | |
3459 | unsigned index; | |
3460 | ||
3461 | index = level - 1; | |
3462 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3463 | return mmu->last_pte_bitmap & (1 << index); | |
3464 | } | |
3465 | ||
6aa8b732 AK |
3466 | #define PTTYPE 64 |
3467 | #include "paging_tmpl.h" | |
3468 | #undef PTTYPE | |
3469 | ||
3470 | #define PTTYPE 32 | |
3471 | #include "paging_tmpl.h" | |
3472 | #undef PTTYPE | |
3473 | ||
52fde8df | 3474 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3475 | struct kvm_mmu *context) |
82725b20 | 3476 | { |
82725b20 DE |
3477 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3478 | u64 exb_bit_rsvd = 0; | |
3479 | ||
2d48a985 | 3480 | if (!context->nx) |
82725b20 | 3481 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3482 | switch (context->root_level) { |
82725b20 DE |
3483 | case PT32_ROOT_LEVEL: |
3484 | /* no rsvd bits for 2 level 4K page table entries */ | |
3485 | context->rsvd_bits_mask[0][1] = 0; | |
3486 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3487 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3488 | ||
3489 | if (!is_pse(vcpu)) { | |
3490 | context->rsvd_bits_mask[1][1] = 0; | |
3491 | break; | |
3492 | } | |
3493 | ||
82725b20 DE |
3494 | if (is_cpuid_PSE36()) |
3495 | /* 36bits PSE 4MB page */ | |
3496 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3497 | else | |
3498 | /* 32 bits PSE 4MB page */ | |
3499 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3500 | break; |
3501 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3502 | context->rsvd_bits_mask[0][2] = |
3503 | rsvd_bits(maxphyaddr, 63) | | |
3504 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3505 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3506 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3507 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3508 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3509 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3510 | rsvd_bits(maxphyaddr, 62) | | |
3511 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3512 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3513 | break; |
3514 | case PT64_ROOT_LEVEL: | |
3515 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3516 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3517 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3518 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3519 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3520 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3521 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3522 | rsvd_bits(maxphyaddr, 51); | |
3523 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3524 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3525 | rsvd_bits(maxphyaddr, 51) | | |
3526 | rsvd_bits(13, 29); | |
82725b20 | 3527 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3528 | rsvd_bits(maxphyaddr, 51) | |
3529 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3530 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3531 | break; |
3532 | } | |
3533 | } | |
3534 | ||
97d64b78 AK |
3535 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3536 | { | |
3537 | unsigned bit, byte, pfec; | |
3538 | u8 map; | |
3539 | bool fault, x, w, u, wf, uf, ff, smep; | |
3540 | ||
3541 | smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); | |
3542 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { | |
3543 | pfec = byte << 1; | |
3544 | map = 0; | |
3545 | wf = pfec & PFERR_WRITE_MASK; | |
3546 | uf = pfec & PFERR_USER_MASK; | |
3547 | ff = pfec & PFERR_FETCH_MASK; | |
3548 | for (bit = 0; bit < 8; ++bit) { | |
3549 | x = bit & ACC_EXEC_MASK; | |
3550 | w = bit & ACC_WRITE_MASK; | |
3551 | u = bit & ACC_USER_MASK; | |
3552 | ||
3553 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3554 | x |= !mmu->nx; | |
3555 | /* Allow supervisor writes if !cr0.wp */ | |
3556 | w |= !is_write_protection(vcpu) && !uf; | |
3557 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
3558 | x &= !(smep && u && !uf); | |
3559 | ||
3560 | fault = (ff && !x) || (uf && !u) || (wf && !w); | |
3561 | map |= fault << bit; | |
3562 | } | |
3563 | mmu->permissions[byte] = map; | |
3564 | } | |
3565 | } | |
3566 | ||
6fd01b71 AK |
3567 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3568 | { | |
3569 | u8 map; | |
3570 | unsigned level, root_level = mmu->root_level; | |
3571 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3572 | ||
3573 | if (root_level == PT32E_ROOT_LEVEL) | |
3574 | --root_level; | |
3575 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3576 | map = 1 | (1 << ps_set_index); | |
3577 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3578 | if (level <= PT_PDPE_LEVEL | |
3579 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3580 | map |= 1 << (ps_set_index | (level - 1)); | |
3581 | } | |
3582 | mmu->last_pte_bitmap = map; | |
3583 | } | |
3584 | ||
52fde8df JR |
3585 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3586 | struct kvm_mmu *context, | |
3587 | int level) | |
6aa8b732 | 3588 | { |
2d48a985 | 3589 | context->nx = is_nx(vcpu); |
4d6931c3 | 3590 | context->root_level = level; |
2d48a985 | 3591 | |
4d6931c3 | 3592 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3593 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3594 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3595 | |
3596 | ASSERT(is_pae(vcpu)); | |
3597 | context->new_cr3 = paging_new_cr3; | |
3598 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3599 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3600 | context->sync_page = paging64_sync_page; |
a7052897 | 3601 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3602 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3603 | context->free = paging_free; |
17ac10ad | 3604 | context->shadow_root_level = level; |
17c3ba9d | 3605 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3606 | context->direct_map = false; |
6aa8b732 AK |
3607 | return 0; |
3608 | } | |
3609 | ||
52fde8df JR |
3610 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3611 | struct kvm_mmu *context) | |
17ac10ad | 3612 | { |
52fde8df | 3613 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3614 | } |
3615 | ||
52fde8df JR |
3616 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3617 | struct kvm_mmu *context) | |
6aa8b732 | 3618 | { |
2d48a985 | 3619 | context->nx = false; |
4d6931c3 | 3620 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3621 | |
4d6931c3 | 3622 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3623 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3624 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3625 | |
3626 | context->new_cr3 = paging_new_cr3; | |
3627 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3628 | context->gva_to_gpa = paging32_gva_to_gpa; |
3629 | context->free = paging_free; | |
e8bc217a | 3630 | context->sync_page = paging32_sync_page; |
a7052897 | 3631 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3632 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3633 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3634 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3635 | context->direct_map = false; |
6aa8b732 AK |
3636 | return 0; |
3637 | } | |
3638 | ||
52fde8df JR |
3639 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3640 | struct kvm_mmu *context) | |
6aa8b732 | 3641 | { |
52fde8df | 3642 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3643 | } |
3644 | ||
fb72d167 JR |
3645 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3646 | { | |
14dfe855 | 3647 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3648 | |
c445f8ef | 3649 | context->base_role.word = 0; |
fb72d167 JR |
3650 | context->new_cr3 = nonpaging_new_cr3; |
3651 | context->page_fault = tdp_page_fault; | |
3652 | context->free = nonpaging_free; | |
e8bc217a | 3653 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3654 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3655 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3656 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3657 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3658 | context->direct_map = true; |
1c97f0a0 | 3659 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3660 | context->get_cr3 = get_cr3; |
e4e517b4 | 3661 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3662 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3663 | |
3664 | if (!is_paging(vcpu)) { | |
2d48a985 | 3665 | context->nx = false; |
fb72d167 JR |
3666 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3667 | context->root_level = 0; | |
3668 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3669 | context->nx = is_nx(vcpu); |
fb72d167 | 3670 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3671 | reset_rsvds_bits_mask(vcpu, context); |
3672 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3673 | } else if (is_pae(vcpu)) { |
2d48a985 | 3674 | context->nx = is_nx(vcpu); |
fb72d167 | 3675 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3676 | reset_rsvds_bits_mask(vcpu, context); |
3677 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3678 | } else { |
2d48a985 | 3679 | context->nx = false; |
fb72d167 | 3680 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3681 | reset_rsvds_bits_mask(vcpu, context); |
3682 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3683 | } |
3684 | ||
97d64b78 | 3685 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3686 | update_last_pte_bitmap(vcpu, context); |
97d64b78 | 3687 | |
fb72d167 JR |
3688 | return 0; |
3689 | } | |
3690 | ||
52fde8df | 3691 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3692 | { |
a770f6f2 | 3693 | int r; |
411c588d | 3694 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3695 | ASSERT(vcpu); |
ad312c7c | 3696 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3697 | |
3698 | if (!is_paging(vcpu)) | |
52fde8df | 3699 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3700 | else if (is_long_mode(vcpu)) |
52fde8df | 3701 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3702 | else if (is_pae(vcpu)) |
52fde8df | 3703 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3704 | else |
52fde8df | 3705 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3706 | |
2c9afa52 | 3707 | vcpu->arch.mmu.base_role.nxe = is_nx(vcpu); |
5b7e0102 | 3708 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3709 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3710 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3711 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3712 | |
3713 | return r; | |
3714 | } | |
3715 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3716 | ||
3717 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3718 | { | |
14dfe855 | 3719 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3720 | |
14dfe855 JR |
3721 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3722 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3723 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3724 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3725 | |
3726 | return r; | |
6aa8b732 AK |
3727 | } |
3728 | ||
02f59dc9 JR |
3729 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3730 | { | |
3731 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3732 | ||
3733 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3734 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3735 | g_context->inject_page_fault = kvm_inject_page_fault; |
3736 | ||
3737 | /* | |
3738 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3739 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3740 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3741 | * functions between mmu and nested_mmu are swapped. | |
3742 | */ | |
3743 | if (!is_paging(vcpu)) { | |
2d48a985 | 3744 | g_context->nx = false; |
02f59dc9 JR |
3745 | g_context->root_level = 0; |
3746 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3747 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3748 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3749 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3750 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3751 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3752 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3753 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3754 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3755 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3756 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3757 | } else { | |
2d48a985 | 3758 | g_context->nx = false; |
02f59dc9 | 3759 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3760 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3761 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3762 | } | |
3763 | ||
97d64b78 | 3764 | update_permission_bitmask(vcpu, g_context); |
6fd01b71 | 3765 | update_last_pte_bitmap(vcpu, g_context); |
97d64b78 | 3766 | |
02f59dc9 JR |
3767 | return 0; |
3768 | } | |
3769 | ||
fb72d167 JR |
3770 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3771 | { | |
02f59dc9 JR |
3772 | if (mmu_is_nested(vcpu)) |
3773 | return init_kvm_nested_mmu(vcpu); | |
3774 | else if (tdp_enabled) | |
fb72d167 JR |
3775 | return init_kvm_tdp_mmu(vcpu); |
3776 | else | |
3777 | return init_kvm_softmmu(vcpu); | |
3778 | } | |
3779 | ||
6aa8b732 AK |
3780 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3781 | { | |
3782 | ASSERT(vcpu); | |
62ad0755 SY |
3783 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3784 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3785 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3786 | } |
3787 | ||
3788 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3789 | { |
3790 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3791 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3792 | } |
8668a3c4 | 3793 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3794 | |
3795 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3796 | { |
714b93da AK |
3797 | int r; |
3798 | ||
e2dec939 | 3799 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3800 | if (r) |
3801 | goto out; | |
8986ecc0 | 3802 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 3803 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
3804 | if (r) |
3805 | goto out; | |
3662cb1c | 3806 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3807 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3808 | out: |
3809 | return r; | |
6aa8b732 | 3810 | } |
17c3ba9d AK |
3811 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3812 | ||
3813 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3814 | { | |
3815 | mmu_free_roots(vcpu); | |
3816 | } | |
4b16184c | 3817 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3818 | |
0028425f | 3819 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3820 | struct kvm_mmu_page *sp, u64 *spte, |
3821 | const void *new) | |
0028425f | 3822 | { |
30945387 | 3823 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3824 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3825 | return; | |
30945387 | 3826 | } |
0028425f | 3827 | |
4cee5764 | 3828 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3829 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3830 | } |
3831 | ||
79539cec AK |
3832 | static bool need_remote_flush(u64 old, u64 new) |
3833 | { | |
3834 | if (!is_shadow_present_pte(old)) | |
3835 | return false; | |
3836 | if (!is_shadow_present_pte(new)) | |
3837 | return true; | |
3838 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3839 | return true; | |
3840 | old ^= PT64_NX_MASK; | |
3841 | new ^= PT64_NX_MASK; | |
3842 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3843 | } | |
3844 | ||
0671a8e7 XG |
3845 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3846 | bool remote_flush, bool local_flush) | |
79539cec | 3847 | { |
0671a8e7 XG |
3848 | if (zap_page) |
3849 | return; | |
3850 | ||
3851 | if (remote_flush) | |
79539cec | 3852 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3853 | else if (local_flush) |
79539cec AK |
3854 | kvm_mmu_flush_tlb(vcpu); |
3855 | } | |
3856 | ||
889e5cbc XG |
3857 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3858 | const u8 *new, int *bytes) | |
da4a00f0 | 3859 | { |
889e5cbc XG |
3860 | u64 gentry; |
3861 | int r; | |
72016f3a | 3862 | |
72016f3a AK |
3863 | /* |
3864 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3865 | * as the current vcpu paging mode since we update the sptes only |
3866 | * when they have the same mode. | |
72016f3a | 3867 | */ |
889e5cbc | 3868 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3869 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3870 | *gpa &= ~(gpa_t)7; |
3871 | *bytes = 8; | |
116eb3d3 | 3872 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8); |
72016f3a AK |
3873 | if (r) |
3874 | gentry = 0; | |
08e850c6 AK |
3875 | new = (const u8 *)&gentry; |
3876 | } | |
3877 | ||
889e5cbc | 3878 | switch (*bytes) { |
08e850c6 AK |
3879 | case 4: |
3880 | gentry = *(const u32 *)new; | |
3881 | break; | |
3882 | case 8: | |
3883 | gentry = *(const u64 *)new; | |
3884 | break; | |
3885 | default: | |
3886 | gentry = 0; | |
3887 | break; | |
72016f3a AK |
3888 | } |
3889 | ||
889e5cbc XG |
3890 | return gentry; |
3891 | } | |
3892 | ||
3893 | /* | |
3894 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3895 | * or we may be forking, in which case it is better to unmap the page. | |
3896 | */ | |
a138fe75 | 3897 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3898 | { |
a30f47cb XG |
3899 | /* |
3900 | * Skip write-flooding detected for the sp whose level is 1, because | |
3901 | * it can become unsync, then the guest page is not write-protected. | |
3902 | */ | |
f71fa31f | 3903 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3904 | return false; |
3246af0e | 3905 | |
a30f47cb | 3906 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3907 | } |
3908 | ||
3909 | /* | |
3910 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3911 | * indicate a page is not used as a page table. | |
3912 | */ | |
3913 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3914 | int bytes) | |
3915 | { | |
3916 | unsigned offset, pte_size, misaligned; | |
3917 | ||
3918 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3919 | gpa, bytes, sp->role.word); | |
3920 | ||
3921 | offset = offset_in_page(gpa); | |
3922 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3923 | |
3924 | /* | |
3925 | * Sometimes, the OS only writes the last one bytes to update status | |
3926 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3927 | */ | |
3928 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3929 | return false; | |
3930 | ||
889e5cbc XG |
3931 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3932 | misaligned |= bytes < 4; | |
3933 | ||
3934 | return misaligned; | |
3935 | } | |
3936 | ||
3937 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3938 | { | |
3939 | unsigned page_offset, quadrant; | |
3940 | u64 *spte; | |
3941 | int level; | |
3942 | ||
3943 | page_offset = offset_in_page(gpa); | |
3944 | level = sp->role.level; | |
3945 | *nspte = 1; | |
3946 | if (!sp->role.cr4_pae) { | |
3947 | page_offset <<= 1; /* 32->64 */ | |
3948 | /* | |
3949 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3950 | * only 2MB. So we need to double the offset again | |
3951 | * and zap two pdes instead of one. | |
3952 | */ | |
3953 | if (level == PT32_ROOT_LEVEL) { | |
3954 | page_offset &= ~7; /* kill rounding error */ | |
3955 | page_offset <<= 1; | |
3956 | *nspte = 2; | |
3957 | } | |
3958 | quadrant = page_offset >> PAGE_SHIFT; | |
3959 | page_offset &= ~PAGE_MASK; | |
3960 | if (quadrant != sp->role.quadrant) | |
3961 | return NULL; | |
3962 | } | |
3963 | ||
3964 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
3965 | return spte; | |
3966 | } | |
3967 | ||
3968 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3969 | const u8 *new, int bytes) | |
3970 | { | |
3971 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3972 | union kvm_mmu_page_role mask = { .word = 0 }; | |
3973 | struct kvm_mmu_page *sp; | |
889e5cbc XG |
3974 | LIST_HEAD(invalid_list); |
3975 | u64 entry, gentry, *spte; | |
3976 | int npte; | |
a30f47cb | 3977 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
3978 | |
3979 | /* | |
3980 | * If we don't have indirect shadow pages, it means no page is | |
3981 | * write-protected, so we can exit simply. | |
3982 | */ | |
3983 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3984 | return; | |
3985 | ||
3986 | zap_page = remote_flush = local_flush = false; | |
3987 | ||
3988 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
3989 | ||
3990 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
3991 | ||
3992 | /* | |
3993 | * No need to care whether allocation memory is successful | |
3994 | * or not since pte prefetch is skiped if it does not have | |
3995 | * enough objects in the cache. | |
3996 | */ | |
3997 | mmu_topup_memory_caches(vcpu); | |
3998 | ||
3999 | spin_lock(&vcpu->kvm->mmu_lock); | |
4000 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4001 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4002 | |
fa1de2bf | 4003 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
b67bfe0d | 4004 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4005 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4006 | detect_write_flooding(sp)) { |
0671a8e7 | 4007 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 4008 | &invalid_list); |
4cee5764 | 4009 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4010 | continue; |
4011 | } | |
889e5cbc XG |
4012 | |
4013 | spte = get_written_sptes(sp, gpa, &npte); | |
4014 | if (!spte) | |
4015 | continue; | |
4016 | ||
0671a8e7 | 4017 | local_flush = true; |
ac1b714e | 4018 | while (npte--) { |
79539cec | 4019 | entry = *spte; |
38e3b2b2 | 4020 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4021 | if (gentry && |
4022 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4023 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4024 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4025 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4026 | remote_flush = true; |
ac1b714e | 4027 | ++spte; |
9b7a0325 | 4028 | } |
9b7a0325 | 4029 | } |
0671a8e7 | 4030 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4031 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4032 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4033 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4034 | } |
4035 | ||
a436036b AK |
4036 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4037 | { | |
10589a46 MT |
4038 | gpa_t gpa; |
4039 | int r; | |
a436036b | 4040 | |
c5a78f2b | 4041 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4042 | return 0; |
4043 | ||
1871c602 | 4044 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4045 | |
10589a46 | 4046 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4047 | |
10589a46 | 4048 | return r; |
a436036b | 4049 | } |
577bdc49 | 4050 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4051 | |
81f4f76b | 4052 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4053 | { |
d98ba053 | 4054 | LIST_HEAD(invalid_list); |
103ad25a | 4055 | |
81f4f76b TY |
4056 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4057 | return; | |
4058 | ||
5da59607 TY |
4059 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4060 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4061 | break; | |
ebeace86 | 4062 | |
4cee5764 | 4063 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4064 | } |
aa6bd187 | 4065 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4066 | } |
ebeace86 | 4067 | |
1cb3f3ae XG |
4068 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4069 | { | |
4070 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4071 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4072 | ||
4073 | return vcpu_match_mmio_gva(vcpu, addr); | |
4074 | } | |
4075 | ||
dc25e89e AP |
4076 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4077 | void *insn, int insn_len) | |
3067714c | 4078 | { |
1cb3f3ae | 4079 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4080 | enum emulation_result er; |
4081 | ||
56028d08 | 4082 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4083 | if (r < 0) |
4084 | goto out; | |
4085 | ||
4086 | if (!r) { | |
4087 | r = 1; | |
4088 | goto out; | |
4089 | } | |
4090 | ||
1cb3f3ae XG |
4091 | if (is_mmio_page_fault(vcpu, cr2)) |
4092 | emulation_type = 0; | |
4093 | ||
4094 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4095 | |
4096 | switch (er) { | |
4097 | case EMULATE_DONE: | |
4098 | return 1; | |
4099 | case EMULATE_DO_MMIO: | |
4100 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 4101 | /* fall through */ |
3067714c | 4102 | case EMULATE_FAIL: |
3f5d18a9 | 4103 | return 0; |
3067714c AK |
4104 | default: |
4105 | BUG(); | |
4106 | } | |
4107 | out: | |
3067714c AK |
4108 | return r; |
4109 | } | |
4110 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4111 | ||
a7052897 MT |
4112 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4113 | { | |
a7052897 | 4114 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4115 | kvm_mmu_flush_tlb(vcpu); |
4116 | ++vcpu->stat.invlpg; | |
4117 | } | |
4118 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4119 | ||
18552672 JR |
4120 | void kvm_enable_tdp(void) |
4121 | { | |
4122 | tdp_enabled = true; | |
4123 | } | |
4124 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4125 | ||
5f4cb662 JR |
4126 | void kvm_disable_tdp(void) |
4127 | { | |
4128 | tdp_enabled = false; | |
4129 | } | |
4130 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4131 | ||
6aa8b732 AK |
4132 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4133 | { | |
ad312c7c | 4134 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4135 | if (vcpu->arch.mmu.lm_root != NULL) |
4136 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4137 | } |
4138 | ||
4139 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4140 | { | |
17ac10ad | 4141 | struct page *page; |
6aa8b732 AK |
4142 | int i; |
4143 | ||
4144 | ASSERT(vcpu); | |
4145 | ||
17ac10ad AK |
4146 | /* |
4147 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4148 | * Therefore we need to allocate shadow page tables in the first | |
4149 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4150 | */ | |
4151 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4152 | if (!page) | |
d7fa6ab2 WY |
4153 | return -ENOMEM; |
4154 | ||
ad312c7c | 4155 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4156 | for (i = 0; i < 4; ++i) |
ad312c7c | 4157 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4158 | |
6aa8b732 | 4159 | return 0; |
6aa8b732 AK |
4160 | } |
4161 | ||
8018c27b | 4162 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4163 | { |
6aa8b732 | 4164 | ASSERT(vcpu); |
e459e322 XG |
4165 | |
4166 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4167 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4168 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4169 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4170 | |
8018c27b IM |
4171 | return alloc_mmu_pages(vcpu); |
4172 | } | |
6aa8b732 | 4173 | |
8018c27b IM |
4174 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
4175 | { | |
4176 | ASSERT(vcpu); | |
ad312c7c | 4177 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4178 | |
8018c27b | 4179 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
4180 | } |
4181 | ||
90cb0529 | 4182 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4183 | { |
b99db1d3 TY |
4184 | struct kvm_memory_slot *memslot; |
4185 | gfn_t last_gfn; | |
4186 | int i; | |
6aa8b732 | 4187 | |
b99db1d3 TY |
4188 | memslot = id_to_memslot(kvm->memslots, slot); |
4189 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4190 | |
9d1beefb TY |
4191 | spin_lock(&kvm->mmu_lock); |
4192 | ||
b99db1d3 TY |
4193 | for (i = PT_PAGE_TABLE_LEVEL; |
4194 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4195 | unsigned long *rmapp; | |
4196 | unsigned long last_index, index; | |
6aa8b732 | 4197 | |
b99db1d3 TY |
4198 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4199 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4200 | |
b99db1d3 TY |
4201 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4202 | if (*rmapp) | |
4203 | __rmap_write_protect(kvm, rmapp, false); | |
6b81b05e TY |
4204 | |
4205 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4206 | kvm_flush_remote_tlbs(kvm); | |
4207 | cond_resched_lock(&kvm->mmu_lock); | |
4208 | } | |
8234b22e | 4209 | } |
6aa8b732 | 4210 | } |
b99db1d3 | 4211 | |
171d595d | 4212 | kvm_flush_remote_tlbs(kvm); |
9d1beefb | 4213 | spin_unlock(&kvm->mmu_lock); |
6aa8b732 | 4214 | } |
37a7d8b0 | 4215 | |
e7d11c7a | 4216 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4217 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4218 | { | |
4219 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4220 | int batch = 0; |
5304b8d3 XG |
4221 | |
4222 | restart: | |
4223 | list_for_each_entry_safe_reverse(sp, node, | |
4224 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4225 | int ret; |
4226 | ||
5304b8d3 XG |
4227 | /* |
4228 | * No obsolete page exists before new created page since | |
4229 | * active_mmu_pages is the FIFO list. | |
4230 | */ | |
4231 | if (!is_obsolete_sp(kvm, sp)) | |
4232 | break; | |
4233 | ||
4234 | /* | |
5304b8d3 XG |
4235 | * Since we are reversely walking the list and the invalid |
4236 | * list will be moved to the head, skip the invalid page | |
4237 | * can help us to avoid the infinity list walking. | |
4238 | */ | |
4239 | if (sp->role.invalid) | |
4240 | continue; | |
4241 | ||
f34d251d XG |
4242 | /* |
4243 | * Need not flush tlb since we only zap the sp with invalid | |
4244 | * generation number. | |
4245 | */ | |
e7d11c7a | 4246 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4247 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4248 | batch = 0; |
5304b8d3 XG |
4249 | goto restart; |
4250 | } | |
4251 | ||
365c8868 XG |
4252 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4253 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4254 | batch += ret; |
4255 | ||
4256 | if (ret) | |
5304b8d3 XG |
4257 | goto restart; |
4258 | } | |
4259 | ||
f34d251d XG |
4260 | /* |
4261 | * Should flush tlb before free page tables since lockless-walking | |
4262 | * may use the pages. | |
4263 | */ | |
365c8868 | 4264 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4265 | } |
4266 | ||
4267 | /* | |
4268 | * Fast invalidate all shadow pages and use lock-break technique | |
4269 | * to zap obsolete pages. | |
4270 | * | |
4271 | * It's required when memslot is being deleted or VM is being | |
4272 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4273 | * not use any resource of the being-deleted slot or all slots | |
4274 | * after calling the function. | |
4275 | */ | |
4276 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4277 | { | |
4278 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4279 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4280 | kvm->arch.mmu_valid_gen++; |
4281 | ||
f34d251d XG |
4282 | /* |
4283 | * Notify all vcpus to reload its shadow page table | |
4284 | * and flush TLB. Then all vcpus will switch to new | |
4285 | * shadow page table with the new mmu_valid_gen. | |
4286 | * | |
4287 | * Note: we should do this under the protection of | |
4288 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4289 | * but miss tlb flush. | |
4290 | */ | |
4291 | kvm_reload_remote_mmus(kvm); | |
4292 | ||
5304b8d3 XG |
4293 | kvm_zap_obsolete_pages(kvm); |
4294 | spin_unlock(&kvm->mmu_lock); | |
4295 | } | |
4296 | ||
982b3394 TY |
4297 | void kvm_mmu_zap_mmio_sptes(struct kvm *kvm) |
4298 | { | |
4299 | struct kvm_mmu_page *sp, *node; | |
4300 | LIST_HEAD(invalid_list); | |
4301 | ||
4302 | spin_lock(&kvm->mmu_lock); | |
4303 | restart: | |
4304 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) { | |
4305 | if (!sp->mmio_cached) | |
4306 | continue; | |
4307 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) | |
4308 | goto restart; | |
4309 | } | |
4310 | ||
4311 | kvm_mmu_commit_zap_page(kvm, &invalid_list); | |
4312 | spin_unlock(&kvm->mmu_lock); | |
4313 | } | |
4314 | ||
365c8868 XG |
4315 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4316 | { | |
4317 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4318 | } | |
4319 | ||
1495f230 | 4320 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
4321 | { |
4322 | struct kvm *kvm; | |
1495f230 | 4323 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
4324 | |
4325 | if (nr_to_scan == 0) | |
4326 | goto out; | |
3ee16c81 | 4327 | |
e935b837 | 4328 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
4329 | |
4330 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4331 | int idx; |
d98ba053 | 4332 | LIST_HEAD(invalid_list); |
3ee16c81 | 4333 | |
35f2d16b TY |
4334 | /* |
4335 | * Never scan more than sc->nr_to_scan VM instances. | |
4336 | * Will not hit this condition practically since we do not try | |
4337 | * to shrink more than one VM and it is very unlikely to see | |
4338 | * !n_used_mmu_pages so many times. | |
4339 | */ | |
4340 | if (!nr_to_scan--) | |
4341 | break; | |
19526396 GN |
4342 | /* |
4343 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4344 | * here. We may skip a VM instance errorneosly, but we do not | |
4345 | * want to shrink a VM that only started to populate its MMU | |
4346 | * anyway. | |
4347 | */ | |
365c8868 XG |
4348 | if (!kvm->arch.n_used_mmu_pages && |
4349 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4350 | continue; |
19526396 | 4351 | |
f656ce01 | 4352 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4353 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4354 | |
365c8868 XG |
4355 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4356 | kvm_mmu_commit_zap_page(kvm, | |
4357 | &kvm->arch.zapped_obsolete_pages); | |
4358 | goto unlock; | |
4359 | } | |
4360 | ||
5da59607 | 4361 | prepare_zap_oldest_mmu_page(kvm, &invalid_list); |
d98ba053 | 4362 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4363 | |
365c8868 | 4364 | unlock: |
3ee16c81 | 4365 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4366 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 GN |
4367 | |
4368 | list_move_tail(&kvm->vm_list, &vm_list); | |
4369 | break; | |
3ee16c81 | 4370 | } |
3ee16c81 | 4371 | |
e935b837 | 4372 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 4373 | |
45221ab6 DH |
4374 | out: |
4375 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
4376 | } |
4377 | ||
4378 | static struct shrinker mmu_shrinker = { | |
4379 | .shrink = mmu_shrink, | |
4380 | .seeks = DEFAULT_SEEKS * 10, | |
4381 | }; | |
4382 | ||
2ddfd20e | 4383 | static void mmu_destroy_caches(void) |
b5a33a75 | 4384 | { |
53c07b18 XG |
4385 | if (pte_list_desc_cache) |
4386 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4387 | if (mmu_page_header_cache) |
4388 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4389 | } |
4390 | ||
4391 | int kvm_mmu_module_init(void) | |
4392 | { | |
53c07b18 XG |
4393 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4394 | sizeof(struct pte_list_desc), | |
20c2df83 | 4395 | 0, 0, NULL); |
53c07b18 | 4396 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4397 | goto nomem; |
4398 | ||
d3d25b04 AK |
4399 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4400 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4401 | 0, 0, NULL); |
d3d25b04 AK |
4402 | if (!mmu_page_header_cache) |
4403 | goto nomem; | |
4404 | ||
45bf21a8 WY |
4405 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4406 | goto nomem; | |
4407 | ||
3ee16c81 IE |
4408 | register_shrinker(&mmu_shrinker); |
4409 | ||
b5a33a75 AK |
4410 | return 0; |
4411 | ||
4412 | nomem: | |
3ee16c81 | 4413 | mmu_destroy_caches(); |
b5a33a75 AK |
4414 | return -ENOMEM; |
4415 | } | |
4416 | ||
3ad82a7e ZX |
4417 | /* |
4418 | * Caculate mmu pages needed for kvm. | |
4419 | */ | |
4420 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4421 | { | |
3ad82a7e ZX |
4422 | unsigned int nr_mmu_pages; |
4423 | unsigned int nr_pages = 0; | |
bc6678a3 | 4424 | struct kvm_memslots *slots; |
be6ba0f0 | 4425 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4426 | |
90d83dc3 LJ |
4427 | slots = kvm_memslots(kvm); |
4428 | ||
be6ba0f0 XG |
4429 | kvm_for_each_memslot(memslot, slots) |
4430 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4431 | |
4432 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4433 | nr_mmu_pages = max(nr_mmu_pages, | |
4434 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4435 | ||
4436 | return nr_mmu_pages; | |
4437 | } | |
4438 | ||
94d8b056 MT |
4439 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4440 | { | |
4441 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4442 | u64 spte; |
94d8b056 MT |
4443 | int nr_sptes = 0; |
4444 | ||
c2a2ac2b XG |
4445 | walk_shadow_page_lockless_begin(vcpu); |
4446 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4447 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4448 | nr_sptes++; |
c2a2ac2b | 4449 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4450 | break; |
4451 | } | |
c2a2ac2b | 4452 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4453 | |
4454 | return nr_sptes; | |
4455 | } | |
4456 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4457 | ||
c42fffe3 XG |
4458 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4459 | { | |
4460 | ASSERT(vcpu); | |
4461 | ||
4462 | destroy_kvm_mmu(vcpu); | |
4463 | free_mmu_pages(vcpu); | |
4464 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4465 | } |
4466 | ||
b034cf01 XG |
4467 | void kvm_mmu_module_exit(void) |
4468 | { | |
4469 | mmu_destroy_caches(); | |
4470 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4471 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4472 | mmu_audit_disable(); |
4473 | } |