Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
e495606d | 25 | |
edf88417 | 26 | #include <linux/kvm_host.h> |
6aa8b732 AK |
27 | #include <linux/types.h> |
28 | #include <linux/string.h> | |
6aa8b732 AK |
29 | #include <linux/mm.h> |
30 | #include <linux/highmem.h> | |
31 | #include <linux/module.h> | |
448353ca | 32 | #include <linux/swap.h> |
05da4558 | 33 | #include <linux/hugetlb.h> |
2f333bcb | 34 | #include <linux/compiler.h> |
bc6678a3 | 35 | #include <linux/srcu.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bf998156 | 37 | #include <linux/uaccess.h> |
6aa8b732 | 38 | |
e495606d AK |
39 | #include <asm/page.h> |
40 | #include <asm/cmpxchg.h> | |
4e542370 | 41 | #include <asm/io.h> |
13673a90 | 42 | #include <asm/vmx.h> |
6aa8b732 | 43 | |
18552672 JR |
44 | /* |
45 | * When setting this variable to true it enables Two-Dimensional-Paging | |
46 | * where the hardware walks 2 page tables: | |
47 | * 1. the guest-virtual to guest-physical | |
48 | * 2. while doing 1. it walks guest-physical to host-physical | |
49 | * If the hardware supports that we don't need to do shadow paging. | |
50 | */ | |
2f333bcb | 51 | bool tdp_enabled = false; |
18552672 | 52 | |
8b1fe17c XG |
53 | enum { |
54 | AUDIT_PRE_PAGE_FAULT, | |
55 | AUDIT_POST_PAGE_FAULT, | |
56 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
57 | AUDIT_POST_PTE_WRITE, |
58 | AUDIT_PRE_SYNC, | |
59 | AUDIT_POST_SYNC | |
8b1fe17c | 60 | }; |
37a7d8b0 | 61 | |
8b1fe17c | 62 | #undef MMU_DEBUG |
37a7d8b0 AK |
63 | |
64 | #ifdef MMU_DEBUG | |
65 | ||
66 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
67 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
68 | ||
69 | #else | |
70 | ||
71 | #define pgprintk(x...) do { } while (0) | |
72 | #define rmap_printk(x...) do { } while (0) | |
73 | ||
74 | #endif | |
75 | ||
8b1fe17c | 76 | #ifdef MMU_DEBUG |
476bc001 | 77 | static bool dbg = 0; |
6ada8cca | 78 | module_param(dbg, bool, 0644); |
37a7d8b0 | 79 | #endif |
6aa8b732 | 80 | |
d6c69ee9 YD |
81 | #ifndef MMU_DEBUG |
82 | #define ASSERT(x) do { } while (0) | |
83 | #else | |
6aa8b732 AK |
84 | #define ASSERT(x) \ |
85 | if (!(x)) { \ | |
86 | printk(KERN_WARNING "assertion failed %s:%d: %s\n", \ | |
87 | __FILE__, __LINE__, #x); \ | |
88 | } | |
d6c69ee9 | 89 | #endif |
6aa8b732 | 90 | |
957ed9ef XG |
91 | #define PTE_PREFETCH_NUM 8 |
92 | ||
00763e41 | 93 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
94 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
95 | ||
6aa8b732 AK |
96 | #define PT64_LEVEL_BITS 9 |
97 | ||
98 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 99 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 100 | |
6aa8b732 AK |
101 | #define PT64_INDEX(address, level)\ |
102 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
103 | ||
104 | ||
105 | #define PT32_LEVEL_BITS 10 | |
106 | ||
107 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 108 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 109 | |
e04da980 JR |
110 | #define PT32_LVL_OFFSET_MASK(level) \ |
111 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
112 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
113 | |
114 | #define PT32_INDEX(address, level)\ | |
115 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
116 | ||
117 | ||
27aba766 | 118 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
119 | #define PT64_DIR_BASE_ADDR_MASK \ |
120 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
121 | #define PT64_LVL_ADDR_MASK(level) \ |
122 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
123 | * PT64_LEVEL_BITS))) - 1)) | |
124 | #define PT64_LVL_OFFSET_MASK(level) \ | |
125 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
126 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
127 | |
128 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
129 | #define PT32_DIR_BASE_ADDR_MASK \ | |
130 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
131 | #define PT32_LVL_ADDR_MASK(level) \ |
132 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
133 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 134 | |
79539cec AK |
135 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \ |
136 | | PT64_NX_MASK) | |
6aa8b732 | 137 | |
fe135d2c AK |
138 | #define ACC_EXEC_MASK 1 |
139 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
140 | #define ACC_USER_MASK PT_USER_MASK | |
141 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
53c07b18 XG |
156 | struct pte_list_desc { |
157 | u64 *sptes[PTE_LIST_EXT]; | |
158 | struct pte_list_desc *more; | |
cd4a4e53 AK |
159 | }; |
160 | ||
2d11123a AK |
161 | struct kvm_shadow_walk_iterator { |
162 | u64 addr; | |
163 | hpa_t shadow_addr; | |
2d11123a | 164 | u64 *sptep; |
dd3bfd59 | 165 | int level; |
2d11123a AK |
166 | unsigned index; |
167 | }; | |
168 | ||
169 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
170 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
171 | shadow_walk_okay(&(_walker)); \ | |
172 | shadow_walk_next(&(_walker))) | |
173 | ||
c2a2ac2b XG |
174 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
175 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
176 | shadow_walk_okay(&(_walker)) && \ | |
177 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
178 | __shadow_walk_next(&(_walker), spte)) | |
179 | ||
53c07b18 | 180 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 181 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 182 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 183 | |
7b52345e SY |
184 | static u64 __read_mostly shadow_nx_mask; |
185 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
186 | static u64 __read_mostly shadow_user_mask; | |
187 | static u64 __read_mostly shadow_accessed_mask; | |
188 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
189 | static u64 __read_mostly shadow_mmio_mask; |
190 | ||
191 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 192 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
193 | |
194 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
195 | { | |
196 | shadow_mmio_mask = mmio_mask; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
199 | ||
200 | static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access) | |
201 | { | |
202 | access &= ACC_WRITE_MASK | ACC_USER_MASK; | |
203 | ||
4f022648 | 204 | trace_mark_mmio_spte(sptep, gfn, access); |
ce88decf XG |
205 | mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT); |
206 | } | |
207 | ||
208 | static bool is_mmio_spte(u64 spte) | |
209 | { | |
210 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
211 | } | |
212 | ||
213 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
214 | { | |
215 | return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT; | |
216 | } | |
217 | ||
218 | static unsigned get_mmio_spte_access(u64 spte) | |
219 | { | |
220 | return (spte & ~shadow_mmio_mask) & ~PAGE_MASK; | |
221 | } | |
222 | ||
223 | static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access) | |
224 | { | |
225 | if (unlikely(is_noslot_pfn(pfn))) { | |
226 | mark_mmio_spte(sptep, gfn, access); | |
227 | return true; | |
228 | } | |
229 | ||
230 | return false; | |
231 | } | |
c7addb90 | 232 | |
82725b20 DE |
233 | static inline u64 rsvd_bits(int s, int e) |
234 | { | |
235 | return ((1ULL << (e - s + 1)) - 1) << s; | |
236 | } | |
237 | ||
7b52345e | 238 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 239 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
240 | { |
241 | shadow_user_mask = user_mask; | |
242 | shadow_accessed_mask = accessed_mask; | |
243 | shadow_dirty_mask = dirty_mask; | |
244 | shadow_nx_mask = nx_mask; | |
245 | shadow_x_mask = x_mask; | |
246 | } | |
247 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
248 | ||
6aa8b732 AK |
249 | static int is_cpuid_PSE36(void) |
250 | { | |
251 | return 1; | |
252 | } | |
253 | ||
73b1087e AK |
254 | static int is_nx(struct kvm_vcpu *vcpu) |
255 | { | |
f6801dff | 256 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
257 | } |
258 | ||
c7addb90 AK |
259 | static int is_shadow_present_pte(u64 pte) |
260 | { | |
ce88decf | 261 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
262 | } |
263 | ||
05da4558 MT |
264 | static int is_large_pte(u64 pte) |
265 | { | |
266 | return pte & PT_PAGE_SIZE_MASK; | |
267 | } | |
268 | ||
43a3795a | 269 | static int is_dirty_gpte(unsigned long pte) |
e3c5e7ec | 270 | { |
439e218a | 271 | return pte & PT_DIRTY_MASK; |
e3c5e7ec AK |
272 | } |
273 | ||
43a3795a | 274 | static int is_rmap_spte(u64 pte) |
cd4a4e53 | 275 | { |
4b1a80fa | 276 | return is_shadow_present_pte(pte); |
cd4a4e53 AK |
277 | } |
278 | ||
776e6633 MT |
279 | static int is_last_spte(u64 pte, int level) |
280 | { | |
281 | if (level == PT_PAGE_TABLE_LEVEL) | |
282 | return 1; | |
852e3c19 | 283 | if (is_large_pte(pte)) |
776e6633 MT |
284 | return 1; |
285 | return 0; | |
286 | } | |
287 | ||
35149e21 | 288 | static pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 289 | { |
35149e21 | 290 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
291 | } |
292 | ||
da928521 AK |
293 | static gfn_t pse36_gfn_delta(u32 gpte) |
294 | { | |
295 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
296 | ||
297 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
298 | } | |
299 | ||
603e0651 | 300 | #ifdef CONFIG_X86_64 |
d555c333 | 301 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 302 | { |
603e0651 | 303 | *sptep = spte; |
e663ee64 AK |
304 | } |
305 | ||
603e0651 | 306 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 307 | { |
603e0651 XG |
308 | *sptep = spte; |
309 | } | |
310 | ||
311 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
312 | { | |
313 | return xchg(sptep, spte); | |
314 | } | |
c2a2ac2b XG |
315 | |
316 | static u64 __get_spte_lockless(u64 *sptep) | |
317 | { | |
318 | return ACCESS_ONCE(*sptep); | |
319 | } | |
ce88decf XG |
320 | |
321 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
322 | { | |
323 | /* It is valid if the spte is zapped. */ | |
324 | return spte == 0ull; | |
325 | } | |
a9221dd5 | 326 | #else |
603e0651 XG |
327 | union split_spte { |
328 | struct { | |
329 | u32 spte_low; | |
330 | u32 spte_high; | |
331 | }; | |
332 | u64 spte; | |
333 | }; | |
a9221dd5 | 334 | |
c2a2ac2b XG |
335 | static void count_spte_clear(u64 *sptep, u64 spte) |
336 | { | |
337 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
338 | ||
339 | if (is_shadow_present_pte(spte)) | |
340 | return; | |
341 | ||
342 | /* Ensure the spte is completely set before we increase the count */ | |
343 | smp_wmb(); | |
344 | sp->clear_spte_count++; | |
345 | } | |
346 | ||
603e0651 XG |
347 | static void __set_spte(u64 *sptep, u64 spte) |
348 | { | |
349 | union split_spte *ssptep, sspte; | |
a9221dd5 | 350 | |
603e0651 XG |
351 | ssptep = (union split_spte *)sptep; |
352 | sspte = (union split_spte)spte; | |
353 | ||
354 | ssptep->spte_high = sspte.spte_high; | |
355 | ||
356 | /* | |
357 | * If we map the spte from nonpresent to present, We should store | |
358 | * the high bits firstly, then set present bit, so cpu can not | |
359 | * fetch this spte while we are setting the spte. | |
360 | */ | |
361 | smp_wmb(); | |
362 | ||
363 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
364 | } |
365 | ||
603e0651 XG |
366 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
367 | { | |
368 | union split_spte *ssptep, sspte; | |
369 | ||
370 | ssptep = (union split_spte *)sptep; | |
371 | sspte = (union split_spte)spte; | |
372 | ||
373 | ssptep->spte_low = sspte.spte_low; | |
374 | ||
375 | /* | |
376 | * If we map the spte from present to nonpresent, we should clear | |
377 | * present bit firstly to avoid vcpu fetch the old high bits. | |
378 | */ | |
379 | smp_wmb(); | |
380 | ||
381 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 382 | count_spte_clear(sptep, spte); |
603e0651 XG |
383 | } |
384 | ||
385 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
386 | { | |
387 | union split_spte *ssptep, sspte, orig; | |
388 | ||
389 | ssptep = (union split_spte *)sptep; | |
390 | sspte = (union split_spte)spte; | |
391 | ||
392 | /* xchg acts as a barrier before the setting of the high bits */ | |
393 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
394 | orig.spte_high = ssptep->spte_high; |
395 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 396 | count_spte_clear(sptep, spte); |
603e0651 XG |
397 | |
398 | return orig.spte; | |
399 | } | |
c2a2ac2b XG |
400 | |
401 | /* | |
402 | * The idea using the light way get the spte on x86_32 guest is from | |
403 | * gup_get_pte(arch/x86/mm/gup.c). | |
404 | * The difference is we can not catch the spte tlb flush if we leave | |
405 | * guest mode, so we emulate it by increase clear_spte_count when spte | |
406 | * is cleared. | |
407 | */ | |
408 | static u64 __get_spte_lockless(u64 *sptep) | |
409 | { | |
410 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
411 | union split_spte spte, *orig = (union split_spte *)sptep; | |
412 | int count; | |
413 | ||
414 | retry: | |
415 | count = sp->clear_spte_count; | |
416 | smp_rmb(); | |
417 | ||
418 | spte.spte_low = orig->spte_low; | |
419 | smp_rmb(); | |
420 | ||
421 | spte.spte_high = orig->spte_high; | |
422 | smp_rmb(); | |
423 | ||
424 | if (unlikely(spte.spte_low != orig->spte_low || | |
425 | count != sp->clear_spte_count)) | |
426 | goto retry; | |
427 | ||
428 | return spte.spte; | |
429 | } | |
ce88decf XG |
430 | |
431 | static bool __check_direct_spte_mmio_pf(u64 spte) | |
432 | { | |
433 | union split_spte sspte = (union split_spte)spte; | |
434 | u32 high_mmio_mask = shadow_mmio_mask >> 32; | |
435 | ||
436 | /* It is valid if the spte is zapped. */ | |
437 | if (spte == 0ull) | |
438 | return true; | |
439 | ||
440 | /* It is valid if the spte is being zapped. */ | |
441 | if (sspte.spte_low == 0ull && | |
442 | (sspte.spte_high & high_mmio_mask) == high_mmio_mask) | |
443 | return true; | |
444 | ||
445 | return false; | |
446 | } | |
603e0651 XG |
447 | #endif |
448 | ||
c7ba5b48 XG |
449 | static bool spte_is_locklessly_modifiable(u64 spte) |
450 | { | |
451 | return !(~spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)); | |
452 | } | |
453 | ||
8672b721 XG |
454 | static bool spte_has_volatile_bits(u64 spte) |
455 | { | |
c7ba5b48 XG |
456 | /* |
457 | * Always atomicly update spte if it can be updated | |
458 | * out of mmu-lock, it can ensure dirty bit is not lost, | |
459 | * also, it can help us to get a stable is_writable_pte() | |
460 | * to ensure tlb flush is not missed. | |
461 | */ | |
462 | if (spte_is_locklessly_modifiable(spte)) | |
463 | return true; | |
464 | ||
8672b721 XG |
465 | if (!shadow_accessed_mask) |
466 | return false; | |
467 | ||
468 | if (!is_shadow_present_pte(spte)) | |
469 | return false; | |
470 | ||
4132779b XG |
471 | if ((spte & shadow_accessed_mask) && |
472 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
473 | return false; |
474 | ||
475 | return true; | |
476 | } | |
477 | ||
4132779b XG |
478 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
479 | { | |
480 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
481 | } | |
482 | ||
1df9f2dc XG |
483 | /* Rules for using mmu_spte_set: |
484 | * Set the sptep from nonpresent to present. | |
485 | * Note: the sptep being assigned *must* be either not present | |
486 | * or in a state where the hardware will not attempt to update | |
487 | * the spte. | |
488 | */ | |
489 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
490 | { | |
491 | WARN_ON(is_shadow_present_pte(*sptep)); | |
492 | __set_spte(sptep, new_spte); | |
493 | } | |
494 | ||
495 | /* Rules for using mmu_spte_update: | |
496 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
497 | * |
498 | * Whenever we overwrite a writable spte with a read-only one we | |
499 | * should flush remote TLBs. Otherwise rmap_write_protect | |
500 | * will find a read-only spte, even though the writable spte | |
501 | * might be cached on a CPU's TLB, the return value indicates this | |
502 | * case. | |
1df9f2dc | 503 | */ |
6e7d0354 | 504 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 505 | { |
c7ba5b48 | 506 | u64 old_spte = *sptep; |
6e7d0354 | 507 | bool ret = false; |
4132779b XG |
508 | |
509 | WARN_ON(!is_rmap_spte(new_spte)); | |
b79b93f9 | 510 | |
6e7d0354 XG |
511 | if (!is_shadow_present_pte(old_spte)) { |
512 | mmu_spte_set(sptep, new_spte); | |
513 | return ret; | |
514 | } | |
4132779b | 515 | |
c7ba5b48 | 516 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 517 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 518 | else |
603e0651 | 519 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 520 | |
c7ba5b48 XG |
521 | /* |
522 | * For the spte updated out of mmu-lock is safe, since | |
523 | * we always atomicly update it, see the comments in | |
524 | * spte_has_volatile_bits(). | |
525 | */ | |
6e7d0354 XG |
526 | if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) |
527 | ret = true; | |
528 | ||
4132779b | 529 | if (!shadow_accessed_mask) |
6e7d0354 | 530 | return ret; |
4132779b XG |
531 | |
532 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) | |
533 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
534 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
535 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
536 | |
537 | return ret; | |
b79b93f9 AK |
538 | } |
539 | ||
1df9f2dc XG |
540 | /* |
541 | * Rules for using mmu_spte_clear_track_bits: | |
542 | * It sets the sptep from present to nonpresent, and track the | |
543 | * state bits, it is used to clear the last level sptep. | |
544 | */ | |
545 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
546 | { | |
547 | pfn_t pfn; | |
548 | u64 old_spte = *sptep; | |
549 | ||
550 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 551 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 552 | else |
603e0651 | 553 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc XG |
554 | |
555 | if (!is_rmap_spte(old_spte)) | |
556 | return 0; | |
557 | ||
558 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
559 | |
560 | /* | |
561 | * KVM does not hold the refcount of the page used by | |
562 | * kvm mmu, before reclaiming the page, we should | |
563 | * unmap it from mmu first. | |
564 | */ | |
565 | WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn))); | |
566 | ||
1df9f2dc XG |
567 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
568 | kvm_set_pfn_accessed(pfn); | |
569 | if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask)) | |
570 | kvm_set_pfn_dirty(pfn); | |
571 | return 1; | |
572 | } | |
573 | ||
574 | /* | |
575 | * Rules for using mmu_spte_clear_no_track: | |
576 | * Directly clear spte without caring the state bits of sptep, | |
577 | * it is used to set the upper level spte. | |
578 | */ | |
579 | static void mmu_spte_clear_no_track(u64 *sptep) | |
580 | { | |
603e0651 | 581 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
582 | } |
583 | ||
c2a2ac2b XG |
584 | static u64 mmu_spte_get_lockless(u64 *sptep) |
585 | { | |
586 | return __get_spte_lockless(sptep); | |
587 | } | |
588 | ||
589 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
590 | { | |
c142786c AK |
591 | /* |
592 | * Prevent page table teardown by making any free-er wait during | |
593 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
594 | */ | |
595 | local_irq_disable(); | |
596 | vcpu->mode = READING_SHADOW_PAGE_TABLES; | |
597 | /* | |
598 | * Make sure a following spte read is not reordered ahead of the write | |
599 | * to vcpu->mode. | |
600 | */ | |
601 | smp_mb(); | |
c2a2ac2b XG |
602 | } |
603 | ||
604 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
605 | { | |
c142786c AK |
606 | /* |
607 | * Make sure the write to vcpu->mode is not reordered in front of | |
608 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
609 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
610 | */ | |
611 | smp_mb(); | |
612 | vcpu->mode = OUTSIDE_GUEST_MODE; | |
613 | local_irq_enable(); | |
c2a2ac2b XG |
614 | } |
615 | ||
e2dec939 | 616 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 617 | struct kmem_cache *base_cache, int min) |
714b93da AK |
618 | { |
619 | void *obj; | |
620 | ||
621 | if (cache->nobjs >= min) | |
e2dec939 | 622 | return 0; |
714b93da | 623 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 624 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 625 | if (!obj) |
e2dec939 | 626 | return -ENOMEM; |
714b93da AK |
627 | cache->objects[cache->nobjs++] = obj; |
628 | } | |
e2dec939 | 629 | return 0; |
714b93da AK |
630 | } |
631 | ||
f759e2b4 XG |
632 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
633 | { | |
634 | return cache->nobjs; | |
635 | } | |
636 | ||
e8ad9a70 XG |
637 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
638 | struct kmem_cache *cache) | |
714b93da AK |
639 | { |
640 | while (mc->nobjs) | |
e8ad9a70 | 641 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
642 | } |
643 | ||
c1158e63 | 644 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 645 | int min) |
c1158e63 | 646 | { |
842f22ed | 647 | void *page; |
c1158e63 AK |
648 | |
649 | if (cache->nobjs >= min) | |
650 | return 0; | |
651 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 652 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
653 | if (!page) |
654 | return -ENOMEM; | |
842f22ed | 655 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
656 | } |
657 | return 0; | |
658 | } | |
659 | ||
660 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
661 | { | |
662 | while (mc->nobjs) | |
c4d198d5 | 663 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
664 | } |
665 | ||
2e3e5882 | 666 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 667 | { |
e2dec939 AK |
668 | int r; |
669 | ||
53c07b18 | 670 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 671 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
672 | if (r) |
673 | goto out; | |
ad312c7c | 674 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
675 | if (r) |
676 | goto out; | |
ad312c7c | 677 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 678 | mmu_page_header_cache, 4); |
e2dec939 AK |
679 | out: |
680 | return r; | |
714b93da AK |
681 | } |
682 | ||
683 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
684 | { | |
53c07b18 XG |
685 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
686 | pte_list_desc_cache); | |
ad312c7c | 687 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
688 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
689 | mmu_page_header_cache); | |
714b93da AK |
690 | } |
691 | ||
80feb89a | 692 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
693 | { |
694 | void *p; | |
695 | ||
696 | BUG_ON(!mc->nobjs); | |
697 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
698 | return p; |
699 | } | |
700 | ||
53c07b18 | 701 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 702 | { |
80feb89a | 703 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
704 | } |
705 | ||
53c07b18 | 706 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 707 | { |
53c07b18 | 708 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
709 | } |
710 | ||
2032a93d LJ |
711 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
712 | { | |
713 | if (!sp->role.direct) | |
714 | return sp->gfns[index]; | |
715 | ||
716 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
717 | } | |
718 | ||
719 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
720 | { | |
721 | if (sp->role.direct) | |
722 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
723 | else | |
724 | sp->gfns[index] = gfn; | |
725 | } | |
726 | ||
05da4558 | 727 | /* |
d4dbf470 TY |
728 | * Return the pointer to the large page information for a given gfn, |
729 | * handling slots that are not large page aligned. | |
05da4558 | 730 | */ |
d4dbf470 TY |
731 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
732 | struct kvm_memory_slot *slot, | |
733 | int level) | |
05da4558 MT |
734 | { |
735 | unsigned long idx; | |
736 | ||
fb03cb6f | 737 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 738 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
739 | } |
740 | ||
741 | static void account_shadowed(struct kvm *kvm, gfn_t gfn) | |
742 | { | |
d25797b2 | 743 | struct kvm_memory_slot *slot; |
d4dbf470 | 744 | struct kvm_lpage_info *linfo; |
d25797b2 | 745 | int i; |
05da4558 | 746 | |
a1f4d395 | 747 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
748 | for (i = PT_DIRECTORY_LEVEL; |
749 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
750 | linfo = lpage_info_slot(gfn, slot, i); |
751 | linfo->write_count += 1; | |
d25797b2 | 752 | } |
332b207d | 753 | kvm->arch.indirect_shadow_pages++; |
05da4558 MT |
754 | } |
755 | ||
756 | static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn) | |
757 | { | |
d25797b2 | 758 | struct kvm_memory_slot *slot; |
d4dbf470 | 759 | struct kvm_lpage_info *linfo; |
d25797b2 | 760 | int i; |
05da4558 | 761 | |
a1f4d395 | 762 | slot = gfn_to_memslot(kvm, gfn); |
d25797b2 JR |
763 | for (i = PT_DIRECTORY_LEVEL; |
764 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
d4dbf470 TY |
765 | linfo = lpage_info_slot(gfn, slot, i); |
766 | linfo->write_count -= 1; | |
767 | WARN_ON(linfo->write_count < 0); | |
d25797b2 | 768 | } |
332b207d | 769 | kvm->arch.indirect_shadow_pages--; |
05da4558 MT |
770 | } |
771 | ||
d25797b2 JR |
772 | static int has_wrprotected_page(struct kvm *kvm, |
773 | gfn_t gfn, | |
774 | int level) | |
05da4558 | 775 | { |
2843099f | 776 | struct kvm_memory_slot *slot; |
d4dbf470 | 777 | struct kvm_lpage_info *linfo; |
05da4558 | 778 | |
a1f4d395 | 779 | slot = gfn_to_memslot(kvm, gfn); |
05da4558 | 780 | if (slot) { |
d4dbf470 TY |
781 | linfo = lpage_info_slot(gfn, slot, level); |
782 | return linfo->write_count; | |
05da4558 MT |
783 | } |
784 | ||
785 | return 1; | |
786 | } | |
787 | ||
d25797b2 | 788 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 789 | { |
8f0b1ab6 | 790 | unsigned long page_size; |
d25797b2 | 791 | int i, ret = 0; |
05da4558 | 792 | |
8f0b1ab6 | 793 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 794 | |
d25797b2 JR |
795 | for (i = PT_PAGE_TABLE_LEVEL; |
796 | i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) { | |
797 | if (page_size >= KVM_HPAGE_SIZE(i)) | |
798 | ret = i; | |
799 | else | |
800 | break; | |
801 | } | |
802 | ||
4c2155ce | 803 | return ret; |
05da4558 MT |
804 | } |
805 | ||
5d163b1c XG |
806 | static struct kvm_memory_slot * |
807 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
808 | bool no_dirty_log) | |
05da4558 MT |
809 | { |
810 | struct kvm_memory_slot *slot; | |
5d163b1c XG |
811 | |
812 | slot = gfn_to_memslot(vcpu->kvm, gfn); | |
813 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID || | |
814 | (no_dirty_log && slot->dirty_bitmap)) | |
815 | slot = NULL; | |
816 | ||
817 | return slot; | |
818 | } | |
819 | ||
820 | static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
821 | { | |
a0a8eaba | 822 | return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true); |
936a5fe6 AA |
823 | } |
824 | ||
825 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn) | |
826 | { | |
827 | int host_level, level, max_level; | |
05da4558 | 828 | |
d25797b2 JR |
829 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
830 | ||
831 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
832 | return host_level; | |
833 | ||
878403b7 SY |
834 | max_level = kvm_x86_ops->get_lpage_level() < host_level ? |
835 | kvm_x86_ops->get_lpage_level() : host_level; | |
836 | ||
837 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
d25797b2 JR |
838 | if (has_wrprotected_page(vcpu->kvm, large_gfn, level)) |
839 | break; | |
d25797b2 JR |
840 | |
841 | return level - 1; | |
05da4558 MT |
842 | } |
843 | ||
290fc38d | 844 | /* |
53c07b18 | 845 | * Pte mapping structures: |
cd4a4e53 | 846 | * |
53c07b18 | 847 | * If pte_list bit zero is zero, then pte_list point to the spte. |
cd4a4e53 | 848 | * |
53c07b18 XG |
849 | * If pte_list bit zero is one, (then pte_list & ~1) points to a struct |
850 | * pte_list_desc containing more mappings. | |
53a27b39 | 851 | * |
53c07b18 | 852 | * Returns the number of pte entries before the spte was added or zero if |
53a27b39 MT |
853 | * the spte was not added. |
854 | * | |
cd4a4e53 | 855 | */ |
53c07b18 XG |
856 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
857 | unsigned long *pte_list) | |
cd4a4e53 | 858 | { |
53c07b18 | 859 | struct pte_list_desc *desc; |
53a27b39 | 860 | int i, count = 0; |
cd4a4e53 | 861 | |
53c07b18 XG |
862 | if (!*pte_list) { |
863 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); | |
864 | *pte_list = (unsigned long)spte; | |
865 | } else if (!(*pte_list & 1)) { | |
866 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); | |
867 | desc = mmu_alloc_pte_list_desc(vcpu); | |
868 | desc->sptes[0] = (u64 *)*pte_list; | |
d555c333 | 869 | desc->sptes[1] = spte; |
53c07b18 | 870 | *pte_list = (unsigned long)desc | 1; |
cb16a7b3 | 871 | ++count; |
cd4a4e53 | 872 | } else { |
53c07b18 XG |
873 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
874 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
875 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { | |
cd4a4e53 | 876 | desc = desc->more; |
53c07b18 | 877 | count += PTE_LIST_EXT; |
53a27b39 | 878 | } |
53c07b18 XG |
879 | if (desc->sptes[PTE_LIST_EXT-1]) { |
880 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
881 | desc = desc->more; |
882 | } | |
d555c333 | 883 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 884 | ++count; |
d555c333 | 885 | desc->sptes[i] = spte; |
cd4a4e53 | 886 | } |
53a27b39 | 887 | return count; |
cd4a4e53 AK |
888 | } |
889 | ||
53c07b18 XG |
890 | static void |
891 | pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc, | |
892 | int i, struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
893 | { |
894 | int j; | |
895 | ||
53c07b18 | 896 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 897 | ; |
d555c333 AK |
898 | desc->sptes[i] = desc->sptes[j]; |
899 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
900 | if (j != 0) |
901 | return; | |
902 | if (!prev_desc && !desc->more) | |
53c07b18 | 903 | *pte_list = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
904 | else |
905 | if (prev_desc) | |
906 | prev_desc->more = desc->more; | |
907 | else | |
53c07b18 XG |
908 | *pte_list = (unsigned long)desc->more | 1; |
909 | mmu_free_pte_list_desc(desc); | |
cd4a4e53 AK |
910 | } |
911 | ||
53c07b18 | 912 | static void pte_list_remove(u64 *spte, unsigned long *pte_list) |
cd4a4e53 | 913 | { |
53c07b18 XG |
914 | struct pte_list_desc *desc; |
915 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
916 | int i; |
917 | ||
53c07b18 XG |
918 | if (!*pte_list) { |
919 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); | |
cd4a4e53 | 920 | BUG(); |
53c07b18 XG |
921 | } else if (!(*pte_list & 1)) { |
922 | rmap_printk("pte_list_remove: %p 1->0\n", spte); | |
923 | if ((u64 *)*pte_list != spte) { | |
924 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); | |
cd4a4e53 AK |
925 | BUG(); |
926 | } | |
53c07b18 | 927 | *pte_list = 0; |
cd4a4e53 | 928 | } else { |
53c07b18 XG |
929 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
930 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
cd4a4e53 AK |
931 | prev_desc = NULL; |
932 | while (desc) { | |
53c07b18 | 933 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) |
d555c333 | 934 | if (desc->sptes[i] == spte) { |
53c07b18 | 935 | pte_list_desc_remove_entry(pte_list, |
714b93da | 936 | desc, i, |
cd4a4e53 AK |
937 | prev_desc); |
938 | return; | |
939 | } | |
940 | prev_desc = desc; | |
941 | desc = desc->more; | |
942 | } | |
53c07b18 | 943 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
944 | BUG(); |
945 | } | |
946 | } | |
947 | ||
67052b35 XG |
948 | typedef void (*pte_list_walk_fn) (u64 *spte); |
949 | static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn) | |
950 | { | |
951 | struct pte_list_desc *desc; | |
952 | int i; | |
953 | ||
954 | if (!*pte_list) | |
955 | return; | |
956 | ||
957 | if (!(*pte_list & 1)) | |
958 | return fn((u64 *)*pte_list); | |
959 | ||
960 | desc = (struct pte_list_desc *)(*pte_list & ~1ul); | |
961 | while (desc) { | |
962 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) | |
963 | fn(desc->sptes[i]); | |
964 | desc = desc->more; | |
965 | } | |
966 | } | |
967 | ||
9373e2c0 | 968 | static unsigned long *__gfn_to_rmap(gfn_t gfn, int level, |
9b9b1492 | 969 | struct kvm_memory_slot *slot) |
53c07b18 | 970 | { |
77d11309 | 971 | unsigned long idx; |
53c07b18 | 972 | |
77d11309 | 973 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 974 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
975 | } |
976 | ||
9b9b1492 TY |
977 | /* |
978 | * Take gfn and return the reverse mapping to it. | |
979 | */ | |
980 | static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level) | |
981 | { | |
982 | struct kvm_memory_slot *slot; | |
983 | ||
984 | slot = gfn_to_memslot(kvm, gfn); | |
9373e2c0 | 985 | return __gfn_to_rmap(gfn, level, slot); |
9b9b1492 TY |
986 | } |
987 | ||
f759e2b4 XG |
988 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
989 | { | |
990 | struct kvm_mmu_memory_cache *cache; | |
991 | ||
992 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
993 | return mmu_memory_cache_free_objects(cache); | |
994 | } | |
995 | ||
53c07b18 XG |
996 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
997 | { | |
998 | struct kvm_mmu_page *sp; | |
999 | unsigned long *rmapp; | |
1000 | ||
53c07b18 XG |
1001 | sp = page_header(__pa(spte)); |
1002 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
1003 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); | |
1004 | return pte_list_add(vcpu, spte, rmapp); | |
1005 | } | |
1006 | ||
53c07b18 XG |
1007 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1008 | { | |
1009 | struct kvm_mmu_page *sp; | |
1010 | gfn_t gfn; | |
1011 | unsigned long *rmapp; | |
1012 | ||
1013 | sp = page_header(__pa(spte)); | |
1014 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
1015 | rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); | |
1016 | pte_list_remove(spte, rmapp); | |
1017 | } | |
1018 | ||
1e3f42f0 TY |
1019 | /* |
1020 | * Used by the following functions to iterate through the sptes linked by a | |
1021 | * rmap. All fields are private and not assumed to be used outside. | |
1022 | */ | |
1023 | struct rmap_iterator { | |
1024 | /* private fields */ | |
1025 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1026 | int pos; /* index of the sptep */ | |
1027 | }; | |
1028 | ||
1029 | /* | |
1030 | * Iteration must be started by this function. This should also be used after | |
1031 | * removing/dropping sptes from the rmap link because in such cases the | |
1032 | * information in the itererator may not be valid. | |
1033 | * | |
1034 | * Returns sptep if found, NULL otherwise. | |
1035 | */ | |
1036 | static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter) | |
1037 | { | |
1038 | if (!rmap) | |
1039 | return NULL; | |
1040 | ||
1041 | if (!(rmap & 1)) { | |
1042 | iter->desc = NULL; | |
1043 | return (u64 *)rmap; | |
1044 | } | |
1045 | ||
1046 | iter->desc = (struct pte_list_desc *)(rmap & ~1ul); | |
1047 | iter->pos = 0; | |
1048 | return iter->desc->sptes[iter->pos]; | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1053 | * | |
1054 | * Returns sptep if found, NULL otherwise. | |
1055 | */ | |
1056 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1057 | { | |
1058 | if (iter->desc) { | |
1059 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1060 | u64 *sptep; | |
1061 | ||
1062 | ++iter->pos; | |
1063 | sptep = iter->desc->sptes[iter->pos]; | |
1064 | if (sptep) | |
1065 | return sptep; | |
1066 | } | |
1067 | ||
1068 | iter->desc = iter->desc->more; | |
1069 | ||
1070 | if (iter->desc) { | |
1071 | iter->pos = 0; | |
1072 | /* desc->sptes[0] cannot be NULL */ | |
1073 | return iter->desc->sptes[iter->pos]; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | return NULL; | |
1078 | } | |
1079 | ||
c3707958 | 1080 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1081 | { |
1df9f2dc | 1082 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1083 | rmap_remove(kvm, sptep); |
be38d276 AK |
1084 | } |
1085 | ||
8e22f955 XG |
1086 | |
1087 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1088 | { | |
1089 | if (is_large_pte(*sptep)) { | |
1090 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1091 | PT_PAGE_TABLE_LEVEL); | |
1092 | drop_spte(kvm, sptep); | |
1093 | --kvm->stat.lpages; | |
1094 | return true; | |
1095 | } | |
1096 | ||
1097 | return false; | |
1098 | } | |
1099 | ||
1100 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1101 | { | |
1102 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1103 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1104 | } | |
1105 | ||
1106 | /* | |
49fde340 XG |
1107 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
1108 | * spte writ-protection is caused by protecting shadow page table. | |
1109 | * @flush indicates whether tlb need be flushed. | |
1110 | * | |
1111 | * Note: write protection is difference between drity logging and spte | |
1112 | * protection: | |
1113 | * - for dirty logging, the spte can be set to writable at anytime if | |
1114 | * its dirty bitmap is properly set. | |
1115 | * - for spte protection, the spte can be writable only after unsync-ing | |
1116 | * shadow page. | |
8e22f955 XG |
1117 | * |
1118 | * Return true if the spte is dropped. | |
1119 | */ | |
49fde340 XG |
1120 | static bool |
1121 | spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) | |
d13bc5b5 XG |
1122 | { |
1123 | u64 spte = *sptep; | |
1124 | ||
49fde340 XG |
1125 | if (!is_writable_pte(spte) && |
1126 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1127 | return false; |
1128 | ||
1129 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1130 | ||
49fde340 XG |
1131 | if (__drop_large_spte(kvm, sptep)) { |
1132 | *flush |= true; | |
d13bc5b5 | 1133 | return true; |
49fde340 | 1134 | } |
d13bc5b5 | 1135 | |
49fde340 XG |
1136 | if (pt_protect) |
1137 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1138 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 XG |
1139 | |
1140 | *flush |= mmu_spte_update(sptep, spte); | |
d13bc5b5 XG |
1141 | return false; |
1142 | } | |
1143 | ||
49fde340 | 1144 | static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, |
245c3912 | 1145 | bool pt_protect) |
98348e95 | 1146 | { |
1e3f42f0 TY |
1147 | u64 *sptep; |
1148 | struct rmap_iterator iter; | |
d13bc5b5 | 1149 | bool flush = false; |
374cbac0 | 1150 | |
1e3f42f0 TY |
1151 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { |
1152 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
49fde340 | 1153 | if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { |
1e3f42f0 | 1154 | sptep = rmap_get_first(*rmapp, &iter); |
d13bc5b5 | 1155 | continue; |
caa5b8a5 | 1156 | } |
a0ed4607 | 1157 | |
d13bc5b5 | 1158 | sptep = rmap_get_next(&iter); |
374cbac0 | 1159 | } |
855149aa | 1160 | |
d13bc5b5 | 1161 | return flush; |
a0ed4607 TY |
1162 | } |
1163 | ||
5dc99b23 TY |
1164 | /** |
1165 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages | |
1166 | * @kvm: kvm instance | |
1167 | * @slot: slot to protect | |
1168 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1169 | * @mask: indicates which pages we should protect | |
1170 | * | |
1171 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1172 | * logging we do not have any such mappings. | |
1173 | */ | |
1174 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, | |
1175 | struct kvm_memory_slot *slot, | |
1176 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 TY |
1177 | { |
1178 | unsigned long *rmapp; | |
a0ed4607 | 1179 | |
5dc99b23 | 1180 | while (mask) { |
65fbe37c TY |
1181 | rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1182 | PT_PAGE_TABLE_LEVEL, slot); | |
245c3912 | 1183 | __rmap_write_protect(kvm, rmapp, false); |
05da4558 | 1184 | |
5dc99b23 TY |
1185 | /* clear the first set bit */ |
1186 | mask &= mask - 1; | |
1187 | } | |
374cbac0 AK |
1188 | } |
1189 | ||
2f84569f | 1190 | static bool rmap_write_protect(struct kvm *kvm, u64 gfn) |
95d4c16c TY |
1191 | { |
1192 | struct kvm_memory_slot *slot; | |
5dc99b23 TY |
1193 | unsigned long *rmapp; |
1194 | int i; | |
2f84569f | 1195 | bool write_protected = false; |
95d4c16c TY |
1196 | |
1197 | slot = gfn_to_memslot(kvm, gfn); | |
5dc99b23 TY |
1198 | |
1199 | for (i = PT_PAGE_TABLE_LEVEL; | |
1200 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
1201 | rmapp = __gfn_to_rmap(gfn, i, slot); | |
245c3912 | 1202 | write_protected |= __rmap_write_protect(kvm, rmapp, true); |
5dc99b23 TY |
1203 | } |
1204 | ||
1205 | return write_protected; | |
95d4c16c TY |
1206 | } |
1207 | ||
8a8365c5 | 1208 | static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1209 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1210 | { |
1e3f42f0 TY |
1211 | u64 *sptep; |
1212 | struct rmap_iterator iter; | |
e930bffe AA |
1213 | int need_tlb_flush = 0; |
1214 | ||
1e3f42f0 TY |
1215 | while ((sptep = rmap_get_first(*rmapp, &iter))) { |
1216 | BUG_ON(!(*sptep & PT_PRESENT_MASK)); | |
1217 | rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep); | |
1218 | ||
1219 | drop_spte(kvm, sptep); | |
e930bffe AA |
1220 | need_tlb_flush = 1; |
1221 | } | |
1e3f42f0 | 1222 | |
e930bffe AA |
1223 | return need_tlb_flush; |
1224 | } | |
1225 | ||
8a8365c5 | 1226 | static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1227 | struct kvm_memory_slot *slot, unsigned long data) |
3da0dd43 | 1228 | { |
1e3f42f0 TY |
1229 | u64 *sptep; |
1230 | struct rmap_iterator iter; | |
3da0dd43 | 1231 | int need_flush = 0; |
1e3f42f0 | 1232 | u64 new_spte; |
3da0dd43 IE |
1233 | pte_t *ptep = (pte_t *)data; |
1234 | pfn_t new_pfn; | |
1235 | ||
1236 | WARN_ON(pte_huge(*ptep)); | |
1237 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 TY |
1238 | |
1239 | for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { | |
1240 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1241 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep); | |
1242 | ||
3da0dd43 | 1243 | need_flush = 1; |
1e3f42f0 | 1244 | |
3da0dd43 | 1245 | if (pte_write(*ptep)) { |
1e3f42f0 TY |
1246 | drop_spte(kvm, sptep); |
1247 | sptep = rmap_get_first(*rmapp, &iter); | |
3da0dd43 | 1248 | } else { |
1e3f42f0 | 1249 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1250 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1251 | ||
1252 | new_spte &= ~PT_WRITABLE_MASK; | |
1253 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1254 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1255 | |
1256 | mmu_spte_clear_track_bits(sptep); | |
1257 | mmu_spte_set(sptep, new_spte); | |
1258 | sptep = rmap_get_next(&iter); | |
3da0dd43 IE |
1259 | } |
1260 | } | |
1e3f42f0 | 1261 | |
3da0dd43 IE |
1262 | if (need_flush) |
1263 | kvm_flush_remote_tlbs(kvm); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
84504ef3 TY |
1268 | static int kvm_handle_hva_range(struct kvm *kvm, |
1269 | unsigned long start, | |
1270 | unsigned long end, | |
1271 | unsigned long data, | |
1272 | int (*handler)(struct kvm *kvm, | |
1273 | unsigned long *rmapp, | |
048212d0 | 1274 | struct kvm_memory_slot *slot, |
84504ef3 | 1275 | unsigned long data)) |
e930bffe | 1276 | { |
be6ba0f0 | 1277 | int j; |
f395302e | 1278 | int ret = 0; |
bc6678a3 | 1279 | struct kvm_memslots *slots; |
be6ba0f0 | 1280 | struct kvm_memory_slot *memslot; |
bc6678a3 | 1281 | |
90d83dc3 | 1282 | slots = kvm_memslots(kvm); |
e930bffe | 1283 | |
be6ba0f0 | 1284 | kvm_for_each_memslot(memslot, slots) { |
84504ef3 | 1285 | unsigned long hva_start, hva_end; |
bcd3ef58 | 1286 | gfn_t gfn_start, gfn_end; |
e930bffe | 1287 | |
84504ef3 TY |
1288 | hva_start = max(start, memslot->userspace_addr); |
1289 | hva_end = min(end, memslot->userspace_addr + | |
1290 | (memslot->npages << PAGE_SHIFT)); | |
1291 | if (hva_start >= hva_end) | |
1292 | continue; | |
1293 | /* | |
1294 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
bcd3ef58 | 1295 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. |
84504ef3 | 1296 | */ |
bcd3ef58 | 1297 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); |
84504ef3 | 1298 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); |
852e3c19 | 1299 | |
bcd3ef58 TY |
1300 | for (j = PT_PAGE_TABLE_LEVEL; |
1301 | j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) { | |
1302 | unsigned long idx, idx_end; | |
1303 | unsigned long *rmapp; | |
d4dbf470 | 1304 | |
bcd3ef58 TY |
1305 | /* |
1306 | * {idx(page_j) | page_j intersects with | |
1307 | * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}. | |
1308 | */ | |
1309 | idx = gfn_to_index(gfn_start, memslot->base_gfn, j); | |
1310 | idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j); | |
852e3c19 | 1311 | |
bcd3ef58 | 1312 | rmapp = __gfn_to_rmap(gfn_start, j, memslot); |
d4dbf470 | 1313 | |
bcd3ef58 TY |
1314 | for (; idx <= idx_end; ++idx) |
1315 | ret |= handler(kvm, rmapp++, memslot, data); | |
e930bffe AA |
1316 | } |
1317 | } | |
1318 | ||
f395302e | 1319 | return ret; |
e930bffe AA |
1320 | } |
1321 | ||
84504ef3 TY |
1322 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1323 | unsigned long data, | |
1324 | int (*handler)(struct kvm *kvm, unsigned long *rmapp, | |
048212d0 | 1325 | struct kvm_memory_slot *slot, |
84504ef3 TY |
1326 | unsigned long data)) |
1327 | { | |
1328 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1329 | } |
1330 | ||
1331 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1332 | { | |
3da0dd43 IE |
1333 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1334 | } | |
1335 | ||
b3ae2096 TY |
1336 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1337 | { | |
1338 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1339 | } | |
1340 | ||
3da0dd43 IE |
1341 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1342 | { | |
8a8365c5 | 1343 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1344 | } |
1345 | ||
8a8365c5 | 1346 | static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1347 | struct kvm_memory_slot *slot, unsigned long data) |
e930bffe | 1348 | { |
1e3f42f0 | 1349 | u64 *sptep; |
79f702a6 | 1350 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1351 | int young = 0; |
1352 | ||
6316e1c8 | 1353 | /* |
3f6d8c8a XH |
1354 | * In case of absence of EPT Access and Dirty Bits supports, |
1355 | * emulate the accessed bit for EPT, by checking if this page has | |
6316e1c8 RR |
1356 | * an EPT mapping, and clearing it if it does. On the next access, |
1357 | * a new EPT mapping will be established. | |
1358 | * This has some overhead, but not as much as the cost of swapping | |
1359 | * out actively used pages or breaking up actively used hugepages. | |
1360 | */ | |
f395302e TY |
1361 | if (!shadow_accessed_mask) { |
1362 | young = kvm_unmap_rmapp(kvm, rmapp, slot, data); | |
1363 | goto out; | |
1364 | } | |
534e38b4 | 1365 | |
1e3f42f0 TY |
1366 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1367 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1368 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1369 | |
3f6d8c8a | 1370 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1371 | young = 1; |
3f6d8c8a XH |
1372 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1373 | (unsigned long *)sptep); | |
e930bffe | 1374 | } |
e930bffe | 1375 | } |
f395302e TY |
1376 | out: |
1377 | /* @data has hva passed to kvm_age_hva(). */ | |
1378 | trace_kvm_age_page(data, slot, young); | |
e930bffe AA |
1379 | return young; |
1380 | } | |
1381 | ||
8ee53820 | 1382 | static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp, |
048212d0 | 1383 | struct kvm_memory_slot *slot, unsigned long data) |
8ee53820 | 1384 | { |
1e3f42f0 TY |
1385 | u64 *sptep; |
1386 | struct rmap_iterator iter; | |
8ee53820 AA |
1387 | int young = 0; |
1388 | ||
1389 | /* | |
1390 | * If there's no access bit in the secondary pte set by the | |
1391 | * hardware it's up to gup-fast/gup to set the access bit in | |
1392 | * the primary pte or in the page structure. | |
1393 | */ | |
1394 | if (!shadow_accessed_mask) | |
1395 | goto out; | |
1396 | ||
1e3f42f0 TY |
1397 | for (sptep = rmap_get_first(*rmapp, &iter); sptep; |
1398 | sptep = rmap_get_next(&iter)) { | |
3f6d8c8a | 1399 | BUG_ON(!is_shadow_present_pte(*sptep)); |
1e3f42f0 | 1400 | |
3f6d8c8a | 1401 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1402 | young = 1; |
1403 | break; | |
1404 | } | |
8ee53820 AA |
1405 | } |
1406 | out: | |
1407 | return young; | |
1408 | } | |
1409 | ||
53a27b39 MT |
1410 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1411 | ||
852e3c19 | 1412 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 MT |
1413 | { |
1414 | unsigned long *rmapp; | |
852e3c19 JR |
1415 | struct kvm_mmu_page *sp; |
1416 | ||
1417 | sp = page_header(__pa(spte)); | |
53a27b39 | 1418 | |
852e3c19 | 1419 | rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); |
53a27b39 | 1420 | |
048212d0 | 1421 | kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0); |
53a27b39 MT |
1422 | kvm_flush_remote_tlbs(vcpu->kvm); |
1423 | } | |
1424 | ||
e930bffe AA |
1425 | int kvm_age_hva(struct kvm *kvm, unsigned long hva) |
1426 | { | |
f395302e | 1427 | return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp); |
e930bffe AA |
1428 | } |
1429 | ||
8ee53820 AA |
1430 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1431 | { | |
1432 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1433 | } | |
1434 | ||
d6c69ee9 | 1435 | #ifdef MMU_DEBUG |
47ad8e68 | 1436 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1437 | { |
139bdb2d AK |
1438 | u64 *pos; |
1439 | u64 *end; | |
1440 | ||
47ad8e68 | 1441 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1442 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1443 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1444 | pos, *pos); |
6aa8b732 | 1445 | return 0; |
139bdb2d | 1446 | } |
6aa8b732 AK |
1447 | return 1; |
1448 | } | |
d6c69ee9 | 1449 | #endif |
6aa8b732 | 1450 | |
45221ab6 DH |
1451 | /* |
1452 | * This value is the sum of all of the kvm instances's | |
1453 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1454 | * aggregate version in order to make the slab shrinker | |
1455 | * faster | |
1456 | */ | |
1457 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1458 | { | |
1459 | kvm->arch.n_used_mmu_pages += nr; | |
1460 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1461 | } | |
1462 | ||
bd4c86ea XG |
1463 | /* |
1464 | * Remove the sp from shadow page cache, after call it, | |
1465 | * we can not find this sp from the cache, and the shadow | |
1466 | * page table is still valid. | |
1467 | * It should be under the protection of mmu lock. | |
1468 | */ | |
1469 | static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp) | |
260746c0 | 1470 | { |
4db35314 | 1471 | ASSERT(is_empty_shadow_page(sp->spt)); |
7775834a | 1472 | hlist_del(&sp->hash_link); |
2032a93d | 1473 | if (!sp->role.direct) |
842f22ed | 1474 | free_page((unsigned long)sp->gfns); |
bd4c86ea XG |
1475 | } |
1476 | ||
1477 | /* | |
1478 | * Free the shadow page table and the sp, we can do it | |
1479 | * out of the protection of mmu lock. | |
1480 | */ | |
1481 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) | |
1482 | { | |
1483 | list_del(&sp->link); | |
1484 | free_page((unsigned long)sp->spt); | |
e8ad9a70 | 1485 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1486 | } |
1487 | ||
cea0f0e7 AK |
1488 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1489 | { | |
1ae0a13d | 1490 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1491 | } |
1492 | ||
714b93da | 1493 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1494 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1495 | { |
cea0f0e7 AK |
1496 | if (!parent_pte) |
1497 | return; | |
cea0f0e7 | 1498 | |
67052b35 | 1499 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1500 | } |
1501 | ||
4db35314 | 1502 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1503 | u64 *parent_pte) |
1504 | { | |
67052b35 | 1505 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1506 | } |
1507 | ||
bcdd9a93 XG |
1508 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1509 | u64 *parent_pte) | |
1510 | { | |
1511 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1512 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1513 | } |
1514 | ||
67052b35 XG |
1515 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, |
1516 | u64 *parent_pte, int direct) | |
ad8cfbe3 | 1517 | { |
67052b35 | 1518 | struct kvm_mmu_page *sp; |
80feb89a TY |
1519 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1520 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1521 | if (!direct) |
80feb89a | 1522 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 XG |
1523 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
1524 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); | |
67052b35 XG |
1525 | sp->parent_ptes = 0; |
1526 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); | |
1527 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); | |
1528 | return sp; | |
ad8cfbe3 MT |
1529 | } |
1530 | ||
67052b35 | 1531 | static void mark_unsync(u64 *spte); |
1047df1f | 1532 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1533 | { |
67052b35 | 1534 | pte_list_walk(&sp->parent_ptes, mark_unsync); |
0074ff63 MT |
1535 | } |
1536 | ||
67052b35 | 1537 | static void mark_unsync(u64 *spte) |
0074ff63 | 1538 | { |
67052b35 | 1539 | struct kvm_mmu_page *sp; |
1047df1f | 1540 | unsigned int index; |
0074ff63 | 1541 | |
67052b35 | 1542 | sp = page_header(__pa(spte)); |
1047df1f XG |
1543 | index = spte - sp->spt; |
1544 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1545 | return; |
1047df1f | 1546 | if (sp->unsync_children++) |
0074ff63 | 1547 | return; |
1047df1f | 1548 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1549 | } |
1550 | ||
e8bc217a | 1551 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1552 | struct kvm_mmu_page *sp) |
e8bc217a MT |
1553 | { |
1554 | return 1; | |
1555 | } | |
1556 | ||
a7052897 MT |
1557 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1558 | { | |
1559 | } | |
1560 | ||
0f53b5b1 XG |
1561 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1562 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1563 | const void *pte) |
0f53b5b1 XG |
1564 | { |
1565 | WARN_ON(1); | |
1566 | } | |
1567 | ||
60c8aec6 MT |
1568 | #define KVM_PAGE_ARRAY_NR 16 |
1569 | ||
1570 | struct kvm_mmu_pages { | |
1571 | struct mmu_page_and_offset { | |
1572 | struct kvm_mmu_page *sp; | |
1573 | unsigned int idx; | |
1574 | } page[KVM_PAGE_ARRAY_NR]; | |
1575 | unsigned int nr; | |
1576 | }; | |
1577 | ||
cded19f3 HE |
1578 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1579 | int idx) | |
4731d4c7 | 1580 | { |
60c8aec6 | 1581 | int i; |
4731d4c7 | 1582 | |
60c8aec6 MT |
1583 | if (sp->unsync) |
1584 | for (i=0; i < pvec->nr; i++) | |
1585 | if (pvec->page[i].sp == sp) | |
1586 | return 0; | |
1587 | ||
1588 | pvec->page[pvec->nr].sp = sp; | |
1589 | pvec->page[pvec->nr].idx = idx; | |
1590 | pvec->nr++; | |
1591 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1592 | } | |
1593 | ||
1594 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1595 | struct kvm_mmu_pages *pvec) | |
1596 | { | |
1597 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1598 | |
37178b8b | 1599 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1600 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1601 | u64 ent = sp->spt[i]; |
1602 | ||
7a8f1a74 XG |
1603 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) |
1604 | goto clear_child_bitmap; | |
1605 | ||
1606 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1607 | ||
1608 | if (child->unsync_children) { | |
1609 | if (mmu_pages_add(pvec, child, i)) | |
1610 | return -ENOSPC; | |
1611 | ||
1612 | ret = __mmu_unsync_walk(child, pvec); | |
1613 | if (!ret) | |
1614 | goto clear_child_bitmap; | |
1615 | else if (ret > 0) | |
1616 | nr_unsync_leaf += ret; | |
1617 | else | |
1618 | return ret; | |
1619 | } else if (child->unsync) { | |
1620 | nr_unsync_leaf++; | |
1621 | if (mmu_pages_add(pvec, child, i)) | |
1622 | return -ENOSPC; | |
1623 | } else | |
1624 | goto clear_child_bitmap; | |
1625 | ||
1626 | continue; | |
1627 | ||
1628 | clear_child_bitmap: | |
1629 | __clear_bit(i, sp->unsync_child_bitmap); | |
1630 | sp->unsync_children--; | |
1631 | WARN_ON((int)sp->unsync_children < 0); | |
4731d4c7 MT |
1632 | } |
1633 | ||
4731d4c7 | 1634 | |
60c8aec6 MT |
1635 | return nr_unsync_leaf; |
1636 | } | |
1637 | ||
1638 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, | |
1639 | struct kvm_mmu_pages *pvec) | |
1640 | { | |
1641 | if (!sp->unsync_children) | |
1642 | return 0; | |
1643 | ||
1644 | mmu_pages_add(pvec, sp, 0); | |
1645 | return __mmu_unsync_walk(sp, pvec); | |
4731d4c7 MT |
1646 | } |
1647 | ||
4731d4c7 MT |
1648 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1649 | { | |
1650 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1651 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1652 | sp->unsync = 0; |
1653 | --kvm->stat.mmu_unsync; | |
1654 | } | |
1655 | ||
7775834a XG |
1656 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1657 | struct list_head *invalid_list); | |
1658 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1659 | struct list_head *invalid_list); | |
4731d4c7 | 1660 | |
f41d335a XG |
1661 | #define for_each_gfn_sp(kvm, sp, gfn, pos) \ |
1662 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1663 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1664 | if ((sp)->gfn != (gfn)) {} else | |
1665 | ||
f41d335a XG |
1666 | #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \ |
1667 | hlist_for_each_entry(sp, pos, \ | |
7ae680eb XG |
1668 | &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \ |
1669 | if ((sp)->gfn != (gfn) || (sp)->role.direct || \ | |
1670 | (sp)->role.invalid) {} else | |
1671 | ||
f918b443 | 1672 | /* @sp->gfn should be write-protected at the call site */ |
1d9dc7e0 | 1673 | static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1674 | struct list_head *invalid_list, bool clear_unsync) |
4731d4c7 | 1675 | { |
5b7e0102 | 1676 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1677 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1678 | return 1; |
1679 | } | |
1680 | ||
f918b443 | 1681 | if (clear_unsync) |
1d9dc7e0 | 1682 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1d9dc7e0 | 1683 | |
a4a8e6f7 | 1684 | if (vcpu->arch.mmu.sync_page(vcpu, sp)) { |
d98ba053 | 1685 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
4731d4c7 MT |
1686 | return 1; |
1687 | } | |
1688 | ||
1689 | kvm_mmu_flush_tlb(vcpu); | |
4731d4c7 MT |
1690 | return 0; |
1691 | } | |
1692 | ||
1d9dc7e0 XG |
1693 | static int kvm_sync_page_transient(struct kvm_vcpu *vcpu, |
1694 | struct kvm_mmu_page *sp) | |
1695 | { | |
d98ba053 | 1696 | LIST_HEAD(invalid_list); |
1d9dc7e0 XG |
1697 | int ret; |
1698 | ||
d98ba053 | 1699 | ret = __kvm_sync_page(vcpu, sp, &invalid_list, false); |
be71e061 | 1700 | if (ret) |
d98ba053 XG |
1701 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
1702 | ||
1d9dc7e0 XG |
1703 | return ret; |
1704 | } | |
1705 | ||
e37fa785 XG |
1706 | #ifdef CONFIG_KVM_MMU_AUDIT |
1707 | #include "mmu_audit.c" | |
1708 | #else | |
1709 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1710 | static void mmu_audit_disable(void) { } | |
1711 | #endif | |
1712 | ||
d98ba053 XG |
1713 | static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1714 | struct list_head *invalid_list) | |
1d9dc7e0 | 1715 | { |
d98ba053 | 1716 | return __kvm_sync_page(vcpu, sp, invalid_list, true); |
1d9dc7e0 XG |
1717 | } |
1718 | ||
9f1a122f XG |
1719 | /* @gfn should be write-protected at the call site */ |
1720 | static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
1721 | { | |
9f1a122f | 1722 | struct kvm_mmu_page *s; |
f41d335a | 1723 | struct hlist_node *node; |
d98ba053 | 1724 | LIST_HEAD(invalid_list); |
9f1a122f XG |
1725 | bool flush = false; |
1726 | ||
f41d335a | 1727 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 1728 | if (!s->unsync) |
9f1a122f XG |
1729 | continue; |
1730 | ||
1731 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
a4a8e6f7 | 1732 | kvm_unlink_unsync_page(vcpu->kvm, s); |
9f1a122f | 1733 | if ((s->role.cr4_pae != !!is_pae(vcpu)) || |
a4a8e6f7 | 1734 | (vcpu->arch.mmu.sync_page(vcpu, s))) { |
d98ba053 | 1735 | kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list); |
9f1a122f XG |
1736 | continue; |
1737 | } | |
9f1a122f XG |
1738 | flush = true; |
1739 | } | |
1740 | ||
d98ba053 | 1741 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
9f1a122f XG |
1742 | if (flush) |
1743 | kvm_mmu_flush_tlb(vcpu); | |
1744 | } | |
1745 | ||
60c8aec6 MT |
1746 | struct mmu_page_path { |
1747 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1]; | |
1748 | unsigned int idx[PT64_ROOT_LEVEL-1]; | |
4731d4c7 MT |
1749 | }; |
1750 | ||
60c8aec6 MT |
1751 | #define for_each_sp(pvec, sp, parents, i) \ |
1752 | for (i = mmu_pages_next(&pvec, &parents, -1), \ | |
1753 | sp = pvec.page[i].sp; \ | |
1754 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ | |
1755 | i = mmu_pages_next(&pvec, &parents, i)) | |
1756 | ||
cded19f3 HE |
1757 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
1758 | struct mmu_page_path *parents, | |
1759 | int i) | |
60c8aec6 MT |
1760 | { |
1761 | int n; | |
1762 | ||
1763 | for (n = i+1; n < pvec->nr; n++) { | |
1764 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
1765 | ||
1766 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) { | |
1767 | parents->idx[0] = pvec->page[n].idx; | |
1768 | return n; | |
1769 | } | |
1770 | ||
1771 | parents->parent[sp->role.level-2] = sp; | |
1772 | parents->idx[sp->role.level-1] = pvec->page[n].idx; | |
1773 | } | |
1774 | ||
1775 | return n; | |
1776 | } | |
1777 | ||
cded19f3 | 1778 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 1779 | { |
60c8aec6 MT |
1780 | struct kvm_mmu_page *sp; |
1781 | unsigned int level = 0; | |
1782 | ||
1783 | do { | |
1784 | unsigned int idx = parents->idx[level]; | |
4731d4c7 | 1785 | |
60c8aec6 MT |
1786 | sp = parents->parent[level]; |
1787 | if (!sp) | |
1788 | return; | |
1789 | ||
1790 | --sp->unsync_children; | |
1791 | WARN_ON((int)sp->unsync_children < 0); | |
1792 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1793 | level++; | |
1794 | } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children); | |
4731d4c7 MT |
1795 | } |
1796 | ||
60c8aec6 MT |
1797 | static void kvm_mmu_pages_init(struct kvm_mmu_page *parent, |
1798 | struct mmu_page_path *parents, | |
1799 | struct kvm_mmu_pages *pvec) | |
4731d4c7 | 1800 | { |
60c8aec6 MT |
1801 | parents->parent[parent->role.level-1] = NULL; |
1802 | pvec->nr = 0; | |
1803 | } | |
4731d4c7 | 1804 | |
60c8aec6 MT |
1805 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
1806 | struct kvm_mmu_page *parent) | |
1807 | { | |
1808 | int i; | |
1809 | struct kvm_mmu_page *sp; | |
1810 | struct mmu_page_path parents; | |
1811 | struct kvm_mmu_pages pages; | |
d98ba053 | 1812 | LIST_HEAD(invalid_list); |
60c8aec6 MT |
1813 | |
1814 | kvm_mmu_pages_init(parent, &parents, &pages); | |
1815 | while (mmu_unsync_walk(parent, &pages)) { | |
2f84569f | 1816 | bool protected = false; |
b1a36821 MT |
1817 | |
1818 | for_each_sp(pages, sp, parents, i) | |
1819 | protected |= rmap_write_protect(vcpu->kvm, sp->gfn); | |
1820 | ||
1821 | if (protected) | |
1822 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1823 | ||
60c8aec6 | 1824 | for_each_sp(pages, sp, parents, i) { |
d98ba053 | 1825 | kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
1826 | mmu_pages_clear_parents(&parents); |
1827 | } | |
d98ba053 | 1828 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
4731d4c7 | 1829 | cond_resched_lock(&vcpu->kvm->mmu_lock); |
60c8aec6 MT |
1830 | kvm_mmu_pages_init(parent, &parents, &pages); |
1831 | } | |
4731d4c7 MT |
1832 | } |
1833 | ||
c3707958 XG |
1834 | static void init_shadow_page_table(struct kvm_mmu_page *sp) |
1835 | { | |
1836 | int i; | |
1837 | ||
1838 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
1839 | sp->spt[i] = 0ull; | |
1840 | } | |
1841 | ||
a30f47cb XG |
1842 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
1843 | { | |
1844 | sp->write_flooding_count = 0; | |
1845 | } | |
1846 | ||
1847 | static void clear_sp_write_flooding_count(u64 *spte) | |
1848 | { | |
1849 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
1850 | ||
1851 | __clear_sp_write_flooding_count(sp); | |
1852 | } | |
1853 | ||
cea0f0e7 AK |
1854 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
1855 | gfn_t gfn, | |
1856 | gva_t gaddr, | |
1857 | unsigned level, | |
f6e2c02b | 1858 | int direct, |
41074d07 | 1859 | unsigned access, |
f7d9c7b7 | 1860 | u64 *parent_pte) |
cea0f0e7 AK |
1861 | { |
1862 | union kvm_mmu_page_role role; | |
cea0f0e7 | 1863 | unsigned quadrant; |
9f1a122f | 1864 | struct kvm_mmu_page *sp; |
f41d335a | 1865 | struct hlist_node *node; |
9f1a122f | 1866 | bool need_sync = false; |
cea0f0e7 | 1867 | |
a770f6f2 | 1868 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 1869 | role.level = level; |
f6e2c02b | 1870 | role.direct = direct; |
84b0c8c6 | 1871 | if (role.direct) |
5b7e0102 | 1872 | role.cr4_pae = 0; |
41074d07 | 1873 | role.access = access; |
c5a78f2b JR |
1874 | if (!vcpu->arch.mmu.direct_map |
1875 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
1876 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
1877 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
1878 | role.quadrant = quadrant; | |
1879 | } | |
f41d335a | 1880 | for_each_gfn_sp(vcpu->kvm, sp, gfn, node) { |
7ae680eb XG |
1881 | if (!need_sync && sp->unsync) |
1882 | need_sync = true; | |
4731d4c7 | 1883 | |
7ae680eb XG |
1884 | if (sp->role.word != role.word) |
1885 | continue; | |
4731d4c7 | 1886 | |
7ae680eb XG |
1887 | if (sp->unsync && kvm_sync_page_transient(vcpu, sp)) |
1888 | break; | |
e02aa901 | 1889 | |
7ae680eb XG |
1890 | mmu_page_add_parent_pte(vcpu, sp, parent_pte); |
1891 | if (sp->unsync_children) { | |
a8eeb04a | 1892 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
7ae680eb XG |
1893 | kvm_mmu_mark_parents_unsync(sp); |
1894 | } else if (sp->unsync) | |
1895 | kvm_mmu_mark_parents_unsync(sp); | |
e02aa901 | 1896 | |
a30f47cb | 1897 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
1898 | trace_kvm_mmu_get_page(sp, false); |
1899 | return sp; | |
1900 | } | |
dfc5aa00 | 1901 | ++vcpu->kvm->stat.mmu_cache_miss; |
2032a93d | 1902 | sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct); |
4db35314 AK |
1903 | if (!sp) |
1904 | return sp; | |
4db35314 AK |
1905 | sp->gfn = gfn; |
1906 | sp->role = role; | |
7ae680eb XG |
1907 | hlist_add_head(&sp->hash_link, |
1908 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 1909 | if (!direct) { |
b1a36821 MT |
1910 | if (rmap_write_protect(vcpu->kvm, gfn)) |
1911 | kvm_flush_remote_tlbs(vcpu->kvm); | |
9f1a122f XG |
1912 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
1913 | kvm_sync_pages(vcpu, gfn); | |
1914 | ||
4731d4c7 MT |
1915 | account_shadowed(vcpu->kvm, gfn); |
1916 | } | |
c3707958 | 1917 | init_shadow_page_table(sp); |
f691fe1d | 1918 | trace_kvm_mmu_get_page(sp, true); |
4db35314 | 1919 | return sp; |
cea0f0e7 AK |
1920 | } |
1921 | ||
2d11123a AK |
1922 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
1923 | struct kvm_vcpu *vcpu, u64 addr) | |
1924 | { | |
1925 | iterator->addr = addr; | |
1926 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
1927 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
1928 | |
1929 | if (iterator->level == PT64_ROOT_LEVEL && | |
1930 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
1931 | !vcpu->arch.mmu.direct_map) | |
1932 | --iterator->level; | |
1933 | ||
2d11123a AK |
1934 | if (iterator->level == PT32E_ROOT_LEVEL) { |
1935 | iterator->shadow_addr | |
1936 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
1937 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
1938 | --iterator->level; | |
1939 | if (!iterator->shadow_addr) | |
1940 | iterator->level = 0; | |
1941 | } | |
1942 | } | |
1943 | ||
1944 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
1945 | { | |
1946 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
1947 | return false; | |
4d88954d | 1948 | |
2d11123a AK |
1949 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
1950 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
1951 | return true; | |
1952 | } | |
1953 | ||
c2a2ac2b XG |
1954 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
1955 | u64 spte) | |
2d11123a | 1956 | { |
c2a2ac2b | 1957 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
1958 | iterator->level = 0; |
1959 | return; | |
1960 | } | |
1961 | ||
c2a2ac2b | 1962 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
1963 | --iterator->level; |
1964 | } | |
1965 | ||
c2a2ac2b XG |
1966 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
1967 | { | |
1968 | return __shadow_walk_next(iterator, *iterator->sptep); | |
1969 | } | |
1970 | ||
32ef26a3 AK |
1971 | static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp) |
1972 | { | |
1973 | u64 spte; | |
1974 | ||
1975 | spte = __pa(sp->spt) | |
1976 | | PT_PRESENT_MASK | PT_ACCESSED_MASK | |
1977 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
1df9f2dc | 1978 | mmu_spte_set(sptep, spte); |
32ef26a3 AK |
1979 | } |
1980 | ||
a357bd22 AK |
1981 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1982 | unsigned direct_access) | |
1983 | { | |
1984 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
1985 | struct kvm_mmu_page *child; | |
1986 | ||
1987 | /* | |
1988 | * For the direct sp, if the guest pte's dirty bit | |
1989 | * changed form clean to dirty, it will corrupt the | |
1990 | * sp's access: allow writable in the read-only sp, | |
1991 | * so we should update the spte at this point to get | |
1992 | * a new sp with the correct access. | |
1993 | */ | |
1994 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
1995 | if (child->role.access == direct_access) | |
1996 | return; | |
1997 | ||
bcdd9a93 | 1998 | drop_parent_pte(child, sptep); |
a357bd22 AK |
1999 | kvm_flush_remote_tlbs(vcpu->kvm); |
2000 | } | |
2001 | } | |
2002 | ||
505aef8f | 2003 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2004 | u64 *spte) |
2005 | { | |
2006 | u64 pte; | |
2007 | struct kvm_mmu_page *child; | |
2008 | ||
2009 | pte = *spte; | |
2010 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2011 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2012 | drop_spte(kvm, spte); |
505aef8f XG |
2013 | if (is_large_pte(pte)) |
2014 | --kvm->stat.lpages; | |
2015 | } else { | |
38e3b2b2 | 2016 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2017 | drop_parent_pte(child, spte); |
38e3b2b2 | 2018 | } |
505aef8f XG |
2019 | return true; |
2020 | } | |
2021 | ||
2022 | if (is_mmio_spte(pte)) | |
ce88decf | 2023 | mmu_spte_clear_no_track(spte); |
c3707958 | 2024 | |
505aef8f | 2025 | return false; |
38e3b2b2 XG |
2026 | } |
2027 | ||
90cb0529 | 2028 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2029 | struct kvm_mmu_page *sp) |
a436036b | 2030 | { |
697fe2e2 | 2031 | unsigned i; |
697fe2e2 | 2032 | |
38e3b2b2 XG |
2033 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2034 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2035 | } |
2036 | ||
4db35314 | 2037 | static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2038 | { |
4db35314 | 2039 | mmu_page_remove_parent_pte(sp, parent_pte); |
a436036b AK |
2040 | } |
2041 | ||
31aa2b44 | 2042 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2043 | { |
1e3f42f0 TY |
2044 | u64 *sptep; |
2045 | struct rmap_iterator iter; | |
a436036b | 2046 | |
1e3f42f0 TY |
2047 | while ((sptep = rmap_get_first(sp->parent_ptes, &iter))) |
2048 | drop_parent_pte(sp, sptep); | |
31aa2b44 AK |
2049 | } |
2050 | ||
60c8aec6 | 2051 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2052 | struct kvm_mmu_page *parent, |
2053 | struct list_head *invalid_list) | |
4731d4c7 | 2054 | { |
60c8aec6 MT |
2055 | int i, zapped = 0; |
2056 | struct mmu_page_path parents; | |
2057 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2058 | |
60c8aec6 | 2059 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2060 | return 0; |
60c8aec6 MT |
2061 | |
2062 | kvm_mmu_pages_init(parent, &parents, &pages); | |
2063 | while (mmu_unsync_walk(parent, &pages)) { | |
2064 | struct kvm_mmu_page *sp; | |
2065 | ||
2066 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2067 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2068 | mmu_pages_clear_parents(&parents); |
77662e00 | 2069 | zapped++; |
60c8aec6 | 2070 | } |
60c8aec6 MT |
2071 | kvm_mmu_pages_init(parent, &parents, &pages); |
2072 | } | |
2073 | ||
2074 | return zapped; | |
4731d4c7 MT |
2075 | } |
2076 | ||
7775834a XG |
2077 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2078 | struct list_head *invalid_list) | |
31aa2b44 | 2079 | { |
4731d4c7 | 2080 | int ret; |
f691fe1d | 2081 | |
7775834a | 2082 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2083 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2084 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2085 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2086 | kvm_mmu_unlink_parents(kvm, sp); |
f6e2c02b | 2087 | if (!sp->role.invalid && !sp->role.direct) |
5b5c6a5a | 2088 | unaccount_shadowed(kvm, sp->gfn); |
4731d4c7 MT |
2089 | if (sp->unsync) |
2090 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2091 | if (!sp->root_count) { |
54a4f023 GJ |
2092 | /* Count self */ |
2093 | ret++; | |
7775834a | 2094 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2095 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2096 | } else { |
5b5c6a5a | 2097 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
2e53d63a MT |
2098 | kvm_reload_remote_mmus(kvm); |
2099 | } | |
7775834a XG |
2100 | |
2101 | sp->role.invalid = 1; | |
4731d4c7 | 2102 | return ret; |
a436036b AK |
2103 | } |
2104 | ||
7775834a XG |
2105 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2106 | struct list_head *invalid_list) | |
2107 | { | |
2108 | struct kvm_mmu_page *sp; | |
2109 | ||
2110 | if (list_empty(invalid_list)) | |
2111 | return; | |
2112 | ||
c142786c AK |
2113 | /* |
2114 | * wmb: make sure everyone sees our modifications to the page tables | |
2115 | * rmb: make sure we see changes to vcpu->mode | |
2116 | */ | |
2117 | smp_mb(); | |
4f022648 | 2118 | |
c142786c AK |
2119 | /* |
2120 | * Wait for all vcpus to exit guest mode and/or lockless shadow | |
2121 | * page table walks. | |
2122 | */ | |
2123 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2124 | |
7775834a XG |
2125 | do { |
2126 | sp = list_first_entry(invalid_list, struct kvm_mmu_page, link); | |
2127 | WARN_ON(!sp->role.invalid || sp->root_count); | |
bd4c86ea | 2128 | kvm_mmu_isolate_page(sp); |
aa6bd187 | 2129 | kvm_mmu_free_page(sp); |
7775834a | 2130 | } while (!list_empty(invalid_list)); |
7775834a XG |
2131 | } |
2132 | ||
82ce2c96 IE |
2133 | /* |
2134 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2135 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2136 | */ |
49d5ca26 | 2137 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2138 | { |
d98ba053 | 2139 | LIST_HEAD(invalid_list); |
82ce2c96 IE |
2140 | /* |
2141 | * If we set the number of mmu pages to be smaller be than the | |
2142 | * number of actived pages , we must to free some mmu pages before we | |
2143 | * change the value | |
2144 | */ | |
2145 | ||
49d5ca26 DH |
2146 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
2147 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages && | |
77662e00 | 2148 | !list_empty(&kvm->arch.active_mmu_pages)) { |
82ce2c96 IE |
2149 | struct kvm_mmu_page *page; |
2150 | ||
f05e70ac | 2151 | page = container_of(kvm->arch.active_mmu_pages.prev, |
82ce2c96 | 2152 | struct kvm_mmu_page, link); |
80b63faf | 2153 | kvm_mmu_prepare_zap_page(kvm, page, &invalid_list); |
82ce2c96 | 2154 | } |
aa6bd187 | 2155 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2156 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2157 | } |
82ce2c96 | 2158 | |
49d5ca26 | 2159 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
82ce2c96 IE |
2160 | } |
2161 | ||
1cb3f3ae | 2162 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2163 | { |
4db35314 | 2164 | struct kvm_mmu_page *sp; |
f41d335a | 2165 | struct hlist_node *node; |
d98ba053 | 2166 | LIST_HEAD(invalid_list); |
a436036b AK |
2167 | int r; |
2168 | ||
9ad17b10 | 2169 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2170 | r = 0; |
1cb3f3ae | 2171 | spin_lock(&kvm->mmu_lock); |
f41d335a | 2172 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) { |
9ad17b10 | 2173 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2174 | sp->role.word); |
2175 | r = 1; | |
f41d335a | 2176 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2177 | } |
d98ba053 | 2178 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2179 | spin_unlock(&kvm->mmu_lock); |
2180 | ||
a436036b | 2181 | return r; |
cea0f0e7 | 2182 | } |
1cb3f3ae | 2183 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2184 | |
74be52e3 SY |
2185 | /* |
2186 | * The function is based on mtrr_type_lookup() in | |
2187 | * arch/x86/kernel/cpu/mtrr/generic.c | |
2188 | */ | |
2189 | static int get_mtrr_type(struct mtrr_state_type *mtrr_state, | |
2190 | u64 start, u64 end) | |
2191 | { | |
2192 | int i; | |
2193 | u64 base, mask; | |
2194 | u8 prev_match, curr_match; | |
2195 | int num_var_ranges = KVM_NR_VAR_MTRR; | |
2196 | ||
2197 | if (!mtrr_state->enabled) | |
2198 | return 0xFF; | |
2199 | ||
2200 | /* Make end inclusive end, instead of exclusive */ | |
2201 | end--; | |
2202 | ||
2203 | /* Look in fixed ranges. Just return the type as per start */ | |
2204 | if (mtrr_state->have_fixed && (start < 0x100000)) { | |
2205 | int idx; | |
2206 | ||
2207 | if (start < 0x80000) { | |
2208 | idx = 0; | |
2209 | idx += (start >> 16); | |
2210 | return mtrr_state->fixed_ranges[idx]; | |
2211 | } else if (start < 0xC0000) { | |
2212 | idx = 1 * 8; | |
2213 | idx += ((start - 0x80000) >> 14); | |
2214 | return mtrr_state->fixed_ranges[idx]; | |
2215 | } else if (start < 0x1000000) { | |
2216 | idx = 3 * 8; | |
2217 | idx += ((start - 0xC0000) >> 12); | |
2218 | return mtrr_state->fixed_ranges[idx]; | |
2219 | } | |
2220 | } | |
2221 | ||
2222 | /* | |
2223 | * Look in variable ranges | |
2224 | * Look of multiple ranges matching this address and pick type | |
2225 | * as per MTRR precedence | |
2226 | */ | |
2227 | if (!(mtrr_state->enabled & 2)) | |
2228 | return mtrr_state->def_type; | |
2229 | ||
2230 | prev_match = 0xFF; | |
2231 | for (i = 0; i < num_var_ranges; ++i) { | |
2232 | unsigned short start_state, end_state; | |
2233 | ||
2234 | if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11))) | |
2235 | continue; | |
2236 | ||
2237 | base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) + | |
2238 | (mtrr_state->var_ranges[i].base_lo & PAGE_MASK); | |
2239 | mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) + | |
2240 | (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK); | |
2241 | ||
2242 | start_state = ((start & mask) == (base & mask)); | |
2243 | end_state = ((end & mask) == (base & mask)); | |
2244 | if (start_state != end_state) | |
2245 | return 0xFE; | |
2246 | ||
2247 | if ((start & mask) != (base & mask)) | |
2248 | continue; | |
2249 | ||
2250 | curr_match = mtrr_state->var_ranges[i].base_lo & 0xff; | |
2251 | if (prev_match == 0xFF) { | |
2252 | prev_match = curr_match; | |
2253 | continue; | |
2254 | } | |
2255 | ||
2256 | if (prev_match == MTRR_TYPE_UNCACHABLE || | |
2257 | curr_match == MTRR_TYPE_UNCACHABLE) | |
2258 | return MTRR_TYPE_UNCACHABLE; | |
2259 | ||
2260 | if ((prev_match == MTRR_TYPE_WRBACK && | |
2261 | curr_match == MTRR_TYPE_WRTHROUGH) || | |
2262 | (prev_match == MTRR_TYPE_WRTHROUGH && | |
2263 | curr_match == MTRR_TYPE_WRBACK)) { | |
2264 | prev_match = MTRR_TYPE_WRTHROUGH; | |
2265 | curr_match = MTRR_TYPE_WRTHROUGH; | |
2266 | } | |
2267 | ||
2268 | if (prev_match != curr_match) | |
2269 | return MTRR_TYPE_UNCACHABLE; | |
2270 | } | |
2271 | ||
2272 | if (prev_match != 0xFF) | |
2273 | return prev_match; | |
2274 | ||
2275 | return mtrr_state->def_type; | |
2276 | } | |
2277 | ||
4b12f0de | 2278 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn) |
74be52e3 SY |
2279 | { |
2280 | u8 mtrr; | |
2281 | ||
2282 | mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT, | |
2283 | (gfn << PAGE_SHIFT) + PAGE_SIZE); | |
2284 | if (mtrr == 0xfe || mtrr == 0xff) | |
2285 | mtrr = MTRR_TYPE_WRBACK; | |
2286 | return mtrr; | |
2287 | } | |
4b12f0de | 2288 | EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type); |
74be52e3 | 2289 | |
9cf5cf5a XG |
2290 | static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
2291 | { | |
2292 | trace_kvm_mmu_unsync_page(sp); | |
2293 | ++vcpu->kvm->stat.mmu_unsync; | |
2294 | sp->unsync = 1; | |
2295 | ||
2296 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2297 | } |
2298 | ||
2299 | static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn) | |
4731d4c7 | 2300 | { |
4731d4c7 | 2301 | struct kvm_mmu_page *s; |
f41d335a | 2302 | struct hlist_node *node; |
9cf5cf5a | 2303 | |
f41d335a | 2304 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
7ae680eb | 2305 | if (s->unsync) |
4731d4c7 | 2306 | continue; |
9cf5cf5a XG |
2307 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); |
2308 | __kvm_unsync_page(vcpu, s); | |
4731d4c7 | 2309 | } |
4731d4c7 MT |
2310 | } |
2311 | ||
2312 | static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, | |
2313 | bool can_unsync) | |
2314 | { | |
9cf5cf5a | 2315 | struct kvm_mmu_page *s; |
f41d335a | 2316 | struct hlist_node *node; |
9cf5cf5a XG |
2317 | bool need_unsync = false; |
2318 | ||
f41d335a | 2319 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) { |
36a2e677 XG |
2320 | if (!can_unsync) |
2321 | return 1; | |
2322 | ||
9cf5cf5a | 2323 | if (s->role.level != PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2324 | return 1; |
9cf5cf5a XG |
2325 | |
2326 | if (!need_unsync && !s->unsync) { | |
9cf5cf5a XG |
2327 | need_unsync = true; |
2328 | } | |
4731d4c7 | 2329 | } |
9cf5cf5a XG |
2330 | if (need_unsync) |
2331 | kvm_unsync_pages(vcpu, gfn); | |
4731d4c7 MT |
2332 | return 0; |
2333 | } | |
2334 | ||
d555c333 | 2335 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2336 | unsigned pte_access, int level, |
c2d0ee46 | 2337 | gfn_t gfn, pfn_t pfn, bool speculative, |
9bdbba13 | 2338 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2339 | { |
6e7d0354 | 2340 | u64 spte; |
1e73f9dd | 2341 | int ret = 0; |
64d4d521 | 2342 | |
ce88decf XG |
2343 | if (set_mmio_spte(sptep, gfn, pfn, pte_access)) |
2344 | return 0; | |
2345 | ||
982c2565 | 2346 | spte = PT_PRESENT_MASK; |
947da538 | 2347 | if (!speculative) |
3201b5d9 | 2348 | spte |= shadow_accessed_mask; |
640d9b0d | 2349 | |
7b52345e SY |
2350 | if (pte_access & ACC_EXEC_MASK) |
2351 | spte |= shadow_x_mask; | |
2352 | else | |
2353 | spte |= shadow_nx_mask; | |
49fde340 | 2354 | |
1c4f1fd6 | 2355 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2356 | spte |= shadow_user_mask; |
49fde340 | 2357 | |
852e3c19 | 2358 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2359 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2360 | if (tdp_enabled) |
4b12f0de SY |
2361 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
2362 | kvm_is_mmio_pfn(pfn)); | |
1c4f1fd6 | 2363 | |
9bdbba13 | 2364 | if (host_writable) |
1403283a | 2365 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2366 | else |
2367 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2368 | |
35149e21 | 2369 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2370 | |
c2288505 | 2371 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2372 | |
c2193463 | 2373 | /* |
7751babd XG |
2374 | * Other vcpu creates new sp in the window between |
2375 | * mapping_level() and acquiring mmu-lock. We can | |
2376 | * allow guest to retry the access, the mapping can | |
2377 | * be fixed if guest refault. | |
c2193463 | 2378 | */ |
852e3c19 | 2379 | if (level > PT_PAGE_TABLE_LEVEL && |
c2193463 | 2380 | has_wrprotected_page(vcpu->kvm, gfn, level)) |
be38d276 | 2381 | goto done; |
38187c83 | 2382 | |
49fde340 | 2383 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2384 | |
ecc5589f MT |
2385 | /* |
2386 | * Optimization: for pte sync, if spte was writable the hash | |
2387 | * lookup is unnecessary (and expensive). Write protection | |
2388 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2389 | * Same reasoning can be applied to dirty page accounting. | |
2390 | */ | |
8dae4445 | 2391 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2392 | goto set_pte; |
2393 | ||
4731d4c7 | 2394 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2395 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2396 | __func__, gfn); |
1e73f9dd | 2397 | ret = 1; |
1c4f1fd6 | 2398 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2399 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2400 | } |
2401 | } | |
2402 | ||
1c4f1fd6 AK |
2403 | if (pte_access & ACC_WRITE_MASK) |
2404 | mark_page_dirty(vcpu->kvm, gfn); | |
2405 | ||
38187c83 | 2406 | set_pte: |
6e7d0354 | 2407 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2408 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2409 | done: |
1e73f9dd MT |
2410 | return ret; |
2411 | } | |
2412 | ||
d555c333 | 2413 | static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
1e73f9dd | 2414 | unsigned pt_access, unsigned pte_access, |
c2288505 XG |
2415 | int write_fault, int *emulate, int level, gfn_t gfn, |
2416 | pfn_t pfn, bool speculative, bool host_writable) | |
1e73f9dd MT |
2417 | { |
2418 | int was_rmapped = 0; | |
53a27b39 | 2419 | int rmap_count; |
1e73f9dd | 2420 | |
c2288505 | 2421 | pgprintk("%s: spte %llx access %x write_fault %d gfn %llx\n", |
d555c333 | 2422 | __func__, *sptep, pt_access, |
c2288505 | 2423 | write_fault, gfn); |
1e73f9dd | 2424 | |
d555c333 | 2425 | if (is_rmap_spte(*sptep)) { |
1e73f9dd MT |
2426 | /* |
2427 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2428 | * the parent of the now unreachable PTE. | |
2429 | */ | |
852e3c19 JR |
2430 | if (level > PT_PAGE_TABLE_LEVEL && |
2431 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2432 | struct kvm_mmu_page *child; |
d555c333 | 2433 | u64 pte = *sptep; |
1e73f9dd MT |
2434 | |
2435 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2436 | drop_parent_pte(child, sptep); |
3be2264b | 2437 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2438 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2439 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2440 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2441 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2442 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2443 | } else |
2444 | was_rmapped = 1; | |
1e73f9dd | 2445 | } |
852e3c19 | 2446 | |
c2288505 XG |
2447 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2448 | true, host_writable)) { | |
1e73f9dd | 2449 | if (write_fault) |
b90a0e6c | 2450 | *emulate = 1; |
5304efde | 2451 | kvm_mmu_flush_tlb(vcpu); |
a378b4e6 | 2452 | } |
1e73f9dd | 2453 | |
ce88decf XG |
2454 | if (unlikely(is_mmio_spte(*sptep) && emulate)) |
2455 | *emulate = 1; | |
2456 | ||
d555c333 | 2457 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2458 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2459 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2460 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2461 | *sptep, sptep); | |
d555c333 | 2462 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2463 | ++vcpu->kvm->stat.lpages; |
2464 | ||
ffb61bb3 | 2465 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2466 | if (!was_rmapped) { |
2467 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2468 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2469 | rmap_recycle(vcpu, sptep, gfn); | |
2470 | } | |
1c4f1fd6 | 2471 | } |
cb9aaa30 | 2472 | |
f3ac1a4b | 2473 | kvm_release_pfn_clean(pfn); |
1c4f1fd6 AK |
2474 | } |
2475 | ||
6aa8b732 AK |
2476 | static void nonpaging_new_cr3(struct kvm_vcpu *vcpu) |
2477 | { | |
e676505a | 2478 | mmu_free_roots(vcpu); |
6aa8b732 AK |
2479 | } |
2480 | ||
a052b42b XG |
2481 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) |
2482 | { | |
2483 | int bit7; | |
2484 | ||
2485 | bit7 = (gpte >> 7) & 1; | |
2486 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0; | |
2487 | } | |
2488 | ||
957ed9ef XG |
2489 | static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
2490 | bool no_dirty_log) | |
2491 | { | |
2492 | struct kvm_memory_slot *slot; | |
957ed9ef | 2493 | |
5d163b1c | 2494 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2495 | if (!slot) |
6c8ee57b | 2496 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2497 | |
037d92dc | 2498 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2499 | } |
2500 | ||
a052b42b XG |
2501 | static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu, |
2502 | struct kvm_mmu_page *sp, u64 *spte, | |
2503 | u64 gpte) | |
2504 | { | |
2505 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
2506 | goto no_present; | |
2507 | ||
2508 | if (!is_present_gpte(gpte)) | |
2509 | goto no_present; | |
2510 | ||
2511 | if (!(gpte & PT_ACCESSED_MASK)) | |
2512 | goto no_present; | |
2513 | ||
2514 | return false; | |
2515 | ||
2516 | no_present: | |
2517 | drop_spte(vcpu->kvm, spte); | |
2518 | return true; | |
2519 | } | |
2520 | ||
957ed9ef XG |
2521 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, |
2522 | struct kvm_mmu_page *sp, | |
2523 | u64 *start, u64 *end) | |
2524 | { | |
2525 | struct page *pages[PTE_PREFETCH_NUM]; | |
2526 | unsigned access = sp->role.access; | |
2527 | int i, ret; | |
2528 | gfn_t gfn; | |
2529 | ||
2530 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
5d163b1c | 2531 | if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK)) |
957ed9ef XG |
2532 | return -1; |
2533 | ||
2534 | ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start); | |
2535 | if (ret <= 0) | |
2536 | return -1; | |
2537 | ||
2538 | for (i = 0; i < ret; i++, gfn++, start++) | |
c2288505 XG |
2539 | mmu_set_spte(vcpu, start, ACC_ALL, access, 0, NULL, |
2540 | sp->role.level, gfn, page_to_pfn(pages[i]), | |
2541 | true, true); | |
957ed9ef XG |
2542 | |
2543 | return 0; | |
2544 | } | |
2545 | ||
2546 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2547 | struct kvm_mmu_page *sp, u64 *sptep) | |
2548 | { | |
2549 | u64 *spte, *start = NULL; | |
2550 | int i; | |
2551 | ||
2552 | WARN_ON(!sp->role.direct); | |
2553 | ||
2554 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2555 | spte = sp->spt + i; | |
2556 | ||
2557 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2558 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2559 | if (!start) |
2560 | continue; | |
2561 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2562 | break; | |
2563 | start = NULL; | |
2564 | } else if (!start) | |
2565 | start = spte; | |
2566 | } | |
2567 | } | |
2568 | ||
2569 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2570 | { | |
2571 | struct kvm_mmu_page *sp; | |
2572 | ||
2573 | /* | |
2574 | * Since it's no accessed bit on EPT, it's no way to | |
2575 | * distinguish between actually accessed translations | |
2576 | * and prefetched, so disable pte prefetch if EPT is | |
2577 | * enabled. | |
2578 | */ | |
2579 | if (!shadow_accessed_mask) | |
2580 | return; | |
2581 | ||
2582 | sp = page_header(__pa(sptep)); | |
2583 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2584 | return; | |
2585 | ||
2586 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2587 | } | |
2588 | ||
9f652d21 | 2589 | static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write, |
2ec4739d XG |
2590 | int map_writable, int level, gfn_t gfn, pfn_t pfn, |
2591 | bool prefault) | |
140754bc | 2592 | { |
9f652d21 | 2593 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2594 | struct kvm_mmu_page *sp; |
b90a0e6c | 2595 | int emulate = 0; |
140754bc | 2596 | gfn_t pseudo_gfn; |
6aa8b732 | 2597 | |
9f652d21 | 2598 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2599 | if (iterator.level == level) { |
612819c3 MT |
2600 | unsigned pte_access = ACC_ALL; |
2601 | ||
612819c3 | 2602 | mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access, |
c2288505 XG |
2603 | write, &emulate, level, gfn, pfn, |
2604 | prefault, map_writable); | |
957ed9ef | 2605 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2606 | ++vcpu->stat.pf_fixed; |
2607 | break; | |
6aa8b732 AK |
2608 | } |
2609 | ||
c3707958 | 2610 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2611 | u64 base_addr = iterator.addr; |
2612 | ||
2613 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2614 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 AK |
2615 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
2616 | iterator.level - 1, | |
2617 | 1, ACC_ALL, iterator.sptep); | |
140754bc | 2618 | |
1df9f2dc XG |
2619 | mmu_spte_set(iterator.sptep, |
2620 | __pa(sp->spt) | |
2621 | | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
2622 | | shadow_user_mask | shadow_x_mask | |
2623 | | shadow_accessed_mask); | |
9f652d21 AK |
2624 | } |
2625 | } | |
b90a0e6c | 2626 | return emulate; |
6aa8b732 AK |
2627 | } |
2628 | ||
77db5cbd | 2629 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2630 | { |
77db5cbd HY |
2631 | siginfo_t info; |
2632 | ||
2633 | info.si_signo = SIGBUS; | |
2634 | info.si_errno = 0; | |
2635 | info.si_code = BUS_MCEERR_AR; | |
2636 | info.si_addr = (void __user *)address; | |
2637 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2638 | |
77db5cbd | 2639 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2640 | } |
2641 | ||
d7c55201 | 2642 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn) |
bf998156 | 2643 | { |
4d8b81ab XG |
2644 | /* |
2645 | * Do not cache the mmio info caused by writing the readonly gfn | |
2646 | * into the spte otherwise read access on readonly gfn also can | |
2647 | * caused mmio page fault and treat it as mmio access. | |
2648 | * Return 1 to tell kvm to emulate it. | |
2649 | */ | |
2650 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2651 | return 1; | |
2652 | ||
e6c1502b | 2653 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
bebb106a | 2654 | kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current); |
bf998156 | 2655 | return 0; |
d7c55201 | 2656 | } |
edba23e5 | 2657 | |
d7c55201 | 2658 | return -EFAULT; |
bf998156 HY |
2659 | } |
2660 | ||
936a5fe6 AA |
2661 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
2662 | gfn_t *gfnp, pfn_t *pfnp, int *levelp) | |
2663 | { | |
2664 | pfn_t pfn = *pfnp; | |
2665 | gfn_t gfn = *gfnp; | |
2666 | int level = *levelp; | |
2667 | ||
2668 | /* | |
2669 | * Check if it's a transparent hugepage. If this would be an | |
2670 | * hugetlbfs page, level wouldn't be set to | |
2671 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2672 | * here. | |
2673 | */ | |
81c52c56 | 2674 | if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) && |
936a5fe6 AA |
2675 | level == PT_PAGE_TABLE_LEVEL && |
2676 | PageTransCompound(pfn_to_page(pfn)) && | |
2677 | !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) { | |
2678 | unsigned long mask; | |
2679 | /* | |
2680 | * mmu_notifier_retry was successful and we hold the | |
2681 | * mmu_lock here, so the pmd can't become splitting | |
2682 | * from under us, and in turn | |
2683 | * __split_huge_page_refcount() can't run from under | |
2684 | * us and we can safely transfer the refcount from | |
2685 | * PG_tail to PG_head as we switch the pfn to tail to | |
2686 | * head. | |
2687 | */ | |
2688 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2689 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2690 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2691 | if (pfn & mask) { | |
2692 | gfn &= ~mask; | |
2693 | *gfnp = gfn; | |
2694 | kvm_release_pfn_clean(pfn); | |
2695 | pfn &= ~mask; | |
c3586667 | 2696 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2697 | *pfnp = pfn; |
2698 | } | |
2699 | } | |
2700 | } | |
2701 | ||
d7c55201 XG |
2702 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
2703 | pfn_t pfn, unsigned access, int *ret_val) | |
2704 | { | |
2705 | bool ret = true; | |
2706 | ||
2707 | /* The pfn is invalid, report the error! */ | |
81c52c56 | 2708 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 XG |
2709 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
2710 | goto exit; | |
2711 | } | |
2712 | ||
ce88decf | 2713 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2714 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 XG |
2715 | |
2716 | ret = false; | |
2717 | exit: | |
2718 | return ret; | |
2719 | } | |
2720 | ||
c7ba5b48 XG |
2721 | static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code) |
2722 | { | |
2723 | /* | |
2724 | * #PF can be fast only if the shadow page table is present and it | |
2725 | * is caused by write-protect, that means we just need change the | |
2726 | * W bit of the spte which can be done out of mmu-lock. | |
2727 | */ | |
2728 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2729 | !(error_code & PFERR_WRITE_MASK)) | |
2730 | return false; | |
2731 | ||
2732 | return true; | |
2733 | } | |
2734 | ||
2735 | static bool | |
2736 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) | |
2737 | { | |
2738 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
2739 | gfn_t gfn; | |
2740 | ||
2741 | WARN_ON(!sp->role.direct); | |
2742 | ||
2743 | /* | |
2744 | * The gfn of direct spte is stable since it is calculated | |
2745 | * by sp->gfn. | |
2746 | */ | |
2747 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2748 | ||
2749 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) | |
2750 | mark_page_dirty(vcpu->kvm, gfn); | |
2751 | ||
2752 | return true; | |
2753 | } | |
2754 | ||
2755 | /* | |
2756 | * Return value: | |
2757 | * - true: let the vcpu to access on the same address again. | |
2758 | * - false: let the real page fault path to fix it. | |
2759 | */ | |
2760 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2761 | u32 error_code) | |
2762 | { | |
2763 | struct kvm_shadow_walk_iterator iterator; | |
2764 | bool ret = false; | |
2765 | u64 spte = 0ull; | |
2766 | ||
2767 | if (!page_fault_can_be_fast(vcpu, error_code)) | |
2768 | return false; | |
2769 | ||
2770 | walk_shadow_page_lockless_begin(vcpu); | |
2771 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2772 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2773 | break; | |
2774 | ||
2775 | /* | |
2776 | * If the mapping has been changed, let the vcpu fault on the | |
2777 | * same address again. | |
2778 | */ | |
2779 | if (!is_rmap_spte(spte)) { | |
2780 | ret = true; | |
2781 | goto exit; | |
2782 | } | |
2783 | ||
2784 | if (!is_last_spte(spte, level)) | |
2785 | goto exit; | |
2786 | ||
2787 | /* | |
2788 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2789 | * | |
2790 | * Need not check the access of upper level table entries since | |
2791 | * they are always ACC_ALL. | |
2792 | */ | |
2793 | if (is_writable_pte(spte)) { | |
2794 | ret = true; | |
2795 | goto exit; | |
2796 | } | |
2797 | ||
2798 | /* | |
2799 | * Currently, to simplify the code, only the spte write-protected | |
2800 | * by dirty-log can be fast fixed. | |
2801 | */ | |
2802 | if (!spte_is_locklessly_modifiable(spte)) | |
2803 | goto exit; | |
2804 | ||
2805 | /* | |
2806 | * Currently, fast page fault only works for direct mapping since | |
2807 | * the gfn is not stable for indirect shadow page. | |
2808 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2809 | */ | |
2810 | ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); | |
2811 | exit: | |
a72faf25 XG |
2812 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2813 | spte, ret); | |
c7ba5b48 XG |
2814 | walk_shadow_page_lockless_end(vcpu); |
2815 | ||
2816 | return ret; | |
2817 | } | |
2818 | ||
78b2c54a | 2819 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
060c2abe XG |
2820 | gva_t gva, pfn_t *pfn, bool write, bool *writable); |
2821 | ||
c7ba5b48 XG |
2822 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
2823 | gfn_t gfn, bool prefault) | |
10589a46 MT |
2824 | { |
2825 | int r; | |
852e3c19 | 2826 | int level; |
936a5fe6 | 2827 | int force_pt_level; |
35149e21 | 2828 | pfn_t pfn; |
e930bffe | 2829 | unsigned long mmu_seq; |
c7ba5b48 | 2830 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 2831 | |
936a5fe6 AA |
2832 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
2833 | if (likely(!force_pt_level)) { | |
2834 | level = mapping_level(vcpu, gfn); | |
2835 | /* | |
2836 | * This path builds a PAE pagetable - so we can map | |
2837 | * 2mb pages at maximum. Therefore check if the level | |
2838 | * is larger than that. | |
2839 | */ | |
2840 | if (level > PT_DIRECTORY_LEVEL) | |
2841 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 2842 | |
936a5fe6 AA |
2843 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
2844 | } else | |
2845 | level = PT_PAGE_TABLE_LEVEL; | |
05da4558 | 2846 | |
c7ba5b48 XG |
2847 | if (fast_page_fault(vcpu, v, level, error_code)) |
2848 | return 0; | |
2849 | ||
e930bffe | 2850 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 2851 | smp_rmb(); |
060c2abe | 2852 | |
78b2c54a | 2853 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 2854 | return 0; |
aaee2c94 | 2855 | |
d7c55201 XG |
2856 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
2857 | return r; | |
d196e343 | 2858 | |
aaee2c94 | 2859 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 2860 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 2861 | goto out_unlock; |
eb787d10 | 2862 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
2863 | if (likely(!force_pt_level)) |
2864 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
2ec4739d XG |
2865 | r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn, |
2866 | prefault); | |
aaee2c94 MT |
2867 | spin_unlock(&vcpu->kvm->mmu_lock); |
2868 | ||
aaee2c94 | 2869 | |
10589a46 | 2870 | return r; |
e930bffe AA |
2871 | |
2872 | out_unlock: | |
2873 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2874 | kvm_release_pfn_clean(pfn); | |
2875 | return 0; | |
10589a46 MT |
2876 | } |
2877 | ||
2878 | ||
17ac10ad AK |
2879 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
2880 | { | |
2881 | int i; | |
4db35314 | 2882 | struct kvm_mmu_page *sp; |
d98ba053 | 2883 | LIST_HEAD(invalid_list); |
17ac10ad | 2884 | |
ad312c7c | 2885 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 2886 | return; |
aaee2c94 | 2887 | spin_lock(&vcpu->kvm->mmu_lock); |
81407ca5 JR |
2888 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
2889 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
2890 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 2891 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 2892 | |
4db35314 AK |
2893 | sp = page_header(root); |
2894 | --sp->root_count; | |
d98ba053 XG |
2895 | if (!sp->root_count && sp->role.invalid) { |
2896 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
2897 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
2898 | } | |
ad312c7c | 2899 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
aaee2c94 | 2900 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad AK |
2901 | return; |
2902 | } | |
17ac10ad | 2903 | for (i = 0; i < 4; ++i) { |
ad312c7c | 2904 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 2905 | |
417726a3 | 2906 | if (root) { |
417726a3 | 2907 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
2908 | sp = page_header(root); |
2909 | --sp->root_count; | |
2e53d63a | 2910 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
2911 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
2912 | &invalid_list); | |
417726a3 | 2913 | } |
ad312c7c | 2914 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 2915 | } |
d98ba053 | 2916 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 2917 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2918 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
2919 | } |
2920 | ||
8986ecc0 MT |
2921 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
2922 | { | |
2923 | int ret = 0; | |
2924 | ||
2925 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 2926 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
2927 | ret = 1; |
2928 | } | |
2929 | ||
2930 | return ret; | |
2931 | } | |
2932 | ||
651dd37a JR |
2933 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
2934 | { | |
2935 | struct kvm_mmu_page *sp; | |
7ebaf15e | 2936 | unsigned i; |
651dd37a JR |
2937 | |
2938 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
2939 | spin_lock(&vcpu->kvm->mmu_lock); | |
2940 | kvm_mmu_free_some_pages(vcpu); | |
2941 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, | |
2942 | 1, ACC_ALL, NULL); | |
2943 | ++sp->root_count; | |
2944 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2945 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
2946 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
2947 | for (i = 0; i < 4; ++i) { | |
2948 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
2949 | ||
2950 | ASSERT(!VALID_PAGE(root)); | |
2951 | spin_lock(&vcpu->kvm->mmu_lock); | |
2952 | kvm_mmu_free_some_pages(vcpu); | |
649497d1 AK |
2953 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
2954 | i << 30, | |
651dd37a JR |
2955 | PT32_ROOT_LEVEL, 1, ACC_ALL, |
2956 | NULL); | |
2957 | root = __pa(sp->spt); | |
2958 | ++sp->root_count; | |
2959 | spin_unlock(&vcpu->kvm->mmu_lock); | |
2960 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 2961 | } |
6292757f | 2962 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
2963 | } else |
2964 | BUG(); | |
2965 | ||
2966 | return 0; | |
2967 | } | |
2968 | ||
2969 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 2970 | { |
4db35314 | 2971 | struct kvm_mmu_page *sp; |
81407ca5 JR |
2972 | u64 pdptr, pm_mask; |
2973 | gfn_t root_gfn; | |
2974 | int i; | |
3bb65a22 | 2975 | |
5777ed34 | 2976 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 2977 | |
651dd37a JR |
2978 | if (mmu_check_root(vcpu, root_gfn)) |
2979 | return 1; | |
2980 | ||
2981 | /* | |
2982 | * Do we shadow a long mode page table? If so we need to | |
2983 | * write-protect the guests page table root. | |
2984 | */ | |
2985 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 2986 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad AK |
2987 | |
2988 | ASSERT(!VALID_PAGE(root)); | |
651dd37a | 2989 | |
8facbbff | 2990 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 2991 | kvm_mmu_free_some_pages(vcpu); |
651dd37a JR |
2992 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
2993 | 0, ACC_ALL, NULL); | |
4db35314 AK |
2994 | root = __pa(sp->spt); |
2995 | ++sp->root_count; | |
8facbbff | 2996 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 2997 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 2998 | return 0; |
17ac10ad | 2999 | } |
f87f9288 | 3000 | |
651dd37a JR |
3001 | /* |
3002 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3003 | * or a PAE 3-level page table. In either case we need to be aware that |
3004 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3005 | */ |
81407ca5 JR |
3006 | pm_mask = PT_PRESENT_MASK; |
3007 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3008 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3009 | ||
17ac10ad | 3010 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3011 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad AK |
3012 | |
3013 | ASSERT(!VALID_PAGE(root)); | |
ad312c7c | 3014 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3015 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3016 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3017 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3018 | continue; |
3019 | } | |
6de4f3ad | 3020 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3021 | if (mmu_check_root(vcpu, root_gfn)) |
3022 | return 1; | |
5a7388c2 | 3023 | } |
8facbbff | 3024 | spin_lock(&vcpu->kvm->mmu_lock); |
24955b6c | 3025 | kvm_mmu_free_some_pages(vcpu); |
4db35314 | 3026 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, |
651dd37a | 3027 | PT32_ROOT_LEVEL, 0, |
f7d9c7b7 | 3028 | ACC_ALL, NULL); |
4db35314 AK |
3029 | root = __pa(sp->spt); |
3030 | ++sp->root_count; | |
8facbbff AK |
3031 | spin_unlock(&vcpu->kvm->mmu_lock); |
3032 | ||
81407ca5 | 3033 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3034 | } |
6292757f | 3035 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3036 | |
3037 | /* | |
3038 | * If we shadow a 32 bit page table with a long mode page | |
3039 | * table we enter this path. | |
3040 | */ | |
3041 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3042 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3043 | /* | |
3044 | * The additional page necessary for this is only | |
3045 | * allocated on demand. | |
3046 | */ | |
3047 | ||
3048 | u64 *lm_root; | |
3049 | ||
3050 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3051 | if (lm_root == NULL) | |
3052 | return 1; | |
3053 | ||
3054 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3055 | ||
3056 | vcpu->arch.mmu.lm_root = lm_root; | |
3057 | } | |
3058 | ||
3059 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3060 | } | |
3061 | ||
8986ecc0 | 3062 | return 0; |
17ac10ad AK |
3063 | } |
3064 | ||
651dd37a JR |
3065 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3066 | { | |
3067 | if (vcpu->arch.mmu.direct_map) | |
3068 | return mmu_alloc_direct_roots(vcpu); | |
3069 | else | |
3070 | return mmu_alloc_shadow_roots(vcpu); | |
3071 | } | |
3072 | ||
0ba73cda MT |
3073 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3074 | { | |
3075 | int i; | |
3076 | struct kvm_mmu_page *sp; | |
3077 | ||
81407ca5 JR |
3078 | if (vcpu->arch.mmu.direct_map) |
3079 | return; | |
3080 | ||
0ba73cda MT |
3081 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3082 | return; | |
6903074c | 3083 | |
bebb106a | 3084 | vcpu_clear_mmio_info(vcpu, ~0ul); |
0375f7fa | 3085 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3086 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3087 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3088 | sp = page_header(root); | |
3089 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3090 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3091 | return; |
3092 | } | |
3093 | for (i = 0; i < 4; ++i) { | |
3094 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3095 | ||
8986ecc0 | 3096 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3097 | root &= PT64_BASE_ADDR_MASK; |
3098 | sp = page_header(root); | |
3099 | mmu_sync_children(vcpu, sp); | |
3100 | } | |
3101 | } | |
0375f7fa | 3102 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3103 | } |
3104 | ||
3105 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3106 | { | |
3107 | spin_lock(&vcpu->kvm->mmu_lock); | |
3108 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3109 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3110 | } |
3111 | ||
1871c602 | 3112 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3113 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3114 | { |
ab9ae313 AK |
3115 | if (exception) |
3116 | exception->error_code = 0; | |
6aa8b732 AK |
3117 | return vaddr; |
3118 | } | |
3119 | ||
6539e738 | 3120 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3121 | u32 access, |
3122 | struct x86_exception *exception) | |
6539e738 | 3123 | { |
ab9ae313 AK |
3124 | if (exception) |
3125 | exception->error_code = 0; | |
6539e738 JR |
3126 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access); |
3127 | } | |
3128 | ||
ce88decf XG |
3129 | static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
3130 | { | |
3131 | if (direct) | |
3132 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3133 | ||
3134 | return vcpu_match_mmio_gva(vcpu, addr); | |
3135 | } | |
3136 | ||
3137 | ||
3138 | /* | |
3139 | * On direct hosts, the last spte is only allows two states | |
3140 | * for mmio page fault: | |
3141 | * - It is the mmio spte | |
3142 | * - It is zapped or it is being zapped. | |
3143 | * | |
3144 | * This function completely checks the spte when the last spte | |
3145 | * is not the mmio spte. | |
3146 | */ | |
3147 | static bool check_direct_spte_mmio_pf(u64 spte) | |
3148 | { | |
3149 | return __check_direct_spte_mmio_pf(spte); | |
3150 | } | |
3151 | ||
3152 | static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr) | |
3153 | { | |
3154 | struct kvm_shadow_walk_iterator iterator; | |
3155 | u64 spte = 0ull; | |
3156 | ||
3157 | walk_shadow_page_lockless_begin(vcpu); | |
3158 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) | |
3159 | if (!is_shadow_present_pte(spte)) | |
3160 | break; | |
3161 | walk_shadow_page_lockless_end(vcpu); | |
3162 | ||
3163 | return spte; | |
3164 | } | |
3165 | ||
3166 | /* | |
3167 | * If it is a real mmio page fault, return 1 and emulat the instruction | |
3168 | * directly, return 0 to let CPU fault again on the address, -1 is | |
3169 | * returned if bug is detected. | |
3170 | */ | |
3171 | int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct) | |
3172 | { | |
3173 | u64 spte; | |
3174 | ||
3175 | if (quickly_check_mmio_pf(vcpu, addr, direct)) | |
3176 | return 1; | |
3177 | ||
3178 | spte = walk_shadow_page_get_mmio_spte(vcpu, addr); | |
3179 | ||
3180 | if (is_mmio_spte(spte)) { | |
3181 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3182 | unsigned access = get_mmio_spte_access(spte); | |
3183 | ||
3184 | if (direct) | |
3185 | addr = 0; | |
4f022648 XG |
3186 | |
3187 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf XG |
3188 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
3189 | return 1; | |
3190 | } | |
3191 | ||
3192 | /* | |
3193 | * It's ok if the gva is remapped by other cpus on shadow guest, | |
3194 | * it's a BUG if the gfn is not a mmio page. | |
3195 | */ | |
3196 | if (direct && !check_direct_spte_mmio_pf(spte)) | |
3197 | return -1; | |
3198 | ||
3199 | /* | |
3200 | * If the page table is zapped by other cpus, let CPU fault again on | |
3201 | * the address. | |
3202 | */ | |
3203 | return 0; | |
3204 | } | |
3205 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common); | |
3206 | ||
3207 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, | |
3208 | u32 error_code, bool direct) | |
3209 | { | |
3210 | int ret; | |
3211 | ||
3212 | ret = handle_mmio_page_fault_common(vcpu, addr, direct); | |
3213 | WARN_ON(ret < 0); | |
3214 | return ret; | |
3215 | } | |
3216 | ||
6aa8b732 | 3217 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3218 | u32 error_code, bool prefault) |
6aa8b732 | 3219 | { |
e833240f | 3220 | gfn_t gfn; |
e2dec939 | 3221 | int r; |
6aa8b732 | 3222 | |
b8688d51 | 3223 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf XG |
3224 | |
3225 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3226 | return handle_mmio_page_fault(vcpu, gva, error_code, true); | |
3227 | ||
e2dec939 AK |
3228 | r = mmu_topup_memory_caches(vcpu); |
3229 | if (r) | |
3230 | return r; | |
714b93da | 3231 | |
6aa8b732 | 3232 | ASSERT(vcpu); |
ad312c7c | 3233 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3234 | |
e833240f | 3235 | gfn = gva >> PAGE_SHIFT; |
6aa8b732 | 3236 | |
e833240f | 3237 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3238 | error_code, gfn, prefault); |
6aa8b732 AK |
3239 | } |
3240 | ||
7e1fbeac | 3241 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3242 | { |
3243 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3244 | |
7c90705b | 3245 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3246 | arch.gfn = gfn; |
c4806acd | 3247 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3248 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 GN |
3249 | |
3250 | return kvm_setup_async_pf(vcpu, gva, gfn, &arch); | |
3251 | } | |
3252 | ||
3253 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3254 | { | |
3255 | if (unlikely(!irqchip_in_kernel(vcpu->kvm) || | |
3256 | kvm_event_needs_reinjection(vcpu))) | |
3257 | return false; | |
3258 | ||
3259 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3260 | } | |
3261 | ||
78b2c54a | 3262 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
612819c3 | 3263 | gva_t gva, pfn_t *pfn, bool write, bool *writable) |
af585b92 GN |
3264 | { |
3265 | bool async; | |
3266 | ||
612819c3 | 3267 | *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable); |
af585b92 GN |
3268 | |
3269 | if (!async) | |
3270 | return false; /* *pfn has correct page already */ | |
3271 | ||
78b2c54a | 3272 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3273 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3274 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3275 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3276 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3277 | return true; | |
3278 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3279 | return true; | |
3280 | } | |
3281 | ||
612819c3 | 3282 | *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable); |
af585b92 GN |
3283 | |
3284 | return false; | |
3285 | } | |
3286 | ||
56028d08 | 3287 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3288 | bool prefault) |
fb72d167 | 3289 | { |
35149e21 | 3290 | pfn_t pfn; |
fb72d167 | 3291 | int r; |
852e3c19 | 3292 | int level; |
936a5fe6 | 3293 | int force_pt_level; |
05da4558 | 3294 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3295 | unsigned long mmu_seq; |
612819c3 MT |
3296 | int write = error_code & PFERR_WRITE_MASK; |
3297 | bool map_writable; | |
fb72d167 JR |
3298 | |
3299 | ASSERT(vcpu); | |
3300 | ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa)); | |
3301 | ||
ce88decf XG |
3302 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
3303 | return handle_mmio_page_fault(vcpu, gpa, error_code, true); | |
3304 | ||
fb72d167 JR |
3305 | r = mmu_topup_memory_caches(vcpu); |
3306 | if (r) | |
3307 | return r; | |
3308 | ||
936a5fe6 AA |
3309 | force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn); |
3310 | if (likely(!force_pt_level)) { | |
3311 | level = mapping_level(vcpu, gfn); | |
3312 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
3313 | } else | |
3314 | level = PT_PAGE_TABLE_LEVEL; | |
852e3c19 | 3315 | |
c7ba5b48 XG |
3316 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3317 | return 0; | |
3318 | ||
e930bffe | 3319 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3320 | smp_rmb(); |
af585b92 | 3321 | |
78b2c54a | 3322 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3323 | return 0; |
3324 | ||
d7c55201 XG |
3325 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3326 | return r; | |
3327 | ||
fb72d167 | 3328 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3329 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3330 | goto out_unlock; |
fb72d167 | 3331 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
3332 | if (likely(!force_pt_level)) |
3333 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
612819c3 | 3334 | r = __direct_map(vcpu, gpa, write, map_writable, |
2ec4739d | 3335 | level, gfn, pfn, prefault); |
fb72d167 | 3336 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3337 | |
3338 | return r; | |
e930bffe AA |
3339 | |
3340 | out_unlock: | |
3341 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3342 | kvm_release_pfn_clean(pfn); | |
3343 | return 0; | |
fb72d167 JR |
3344 | } |
3345 | ||
6aa8b732 AK |
3346 | static void nonpaging_free(struct kvm_vcpu *vcpu) |
3347 | { | |
17ac10ad | 3348 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3349 | } |
3350 | ||
52fde8df JR |
3351 | static int nonpaging_init_context(struct kvm_vcpu *vcpu, |
3352 | struct kvm_mmu *context) | |
6aa8b732 | 3353 | { |
6aa8b732 AK |
3354 | context->new_cr3 = nonpaging_new_cr3; |
3355 | context->page_fault = nonpaging_page_fault; | |
6aa8b732 AK |
3356 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3357 | context->free = nonpaging_free; | |
e8bc217a | 3358 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3359 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3360 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3361 | context->root_level = 0; |
6aa8b732 | 3362 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3363 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3364 | context->direct_map = true; |
2d48a985 | 3365 | context->nx = false; |
6aa8b732 AK |
3366 | return 0; |
3367 | } | |
3368 | ||
d835dfec | 3369 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) |
6aa8b732 | 3370 | { |
1165f5fe | 3371 | ++vcpu->stat.tlb_flush; |
a8eeb04a | 3372 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
6aa8b732 AK |
3373 | } |
3374 | ||
3375 | static void paging_new_cr3(struct kvm_vcpu *vcpu) | |
3376 | { | |
9f8fe504 | 3377 | pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu)); |
cea0f0e7 | 3378 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3379 | } |
3380 | ||
5777ed34 JR |
3381 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3382 | { | |
9f8fe504 | 3383 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3384 | } |
3385 | ||
6389ee94 AK |
3386 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3387 | struct x86_exception *fault) | |
6aa8b732 | 3388 | { |
6389ee94 | 3389 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3390 | } |
3391 | ||
6aa8b732 AK |
3392 | static void paging_free(struct kvm_vcpu *vcpu) |
3393 | { | |
3394 | nonpaging_free(vcpu); | |
3395 | } | |
3396 | ||
8ea667f2 AK |
3397 | static inline void protect_clean_gpte(unsigned *access, unsigned gpte) |
3398 | { | |
3399 | unsigned mask; | |
3400 | ||
3401 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); | |
3402 | ||
3403 | mask = (unsigned)~ACC_WRITE_MASK; | |
3404 | /* Allow write access to dirty gptes */ | |
3405 | mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK; | |
3406 | *access &= mask; | |
3407 | } | |
3408 | ||
ce88decf XG |
3409 | static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access, |
3410 | int *nr_present) | |
3411 | { | |
3412 | if (unlikely(is_mmio_spte(*sptep))) { | |
3413 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3414 | mmu_spte_clear_no_track(sptep); | |
3415 | return true; | |
3416 | } | |
3417 | ||
3418 | (*nr_present)++; | |
3419 | mark_mmio_spte(sptep, gfn, access); | |
3420 | return true; | |
3421 | } | |
3422 | ||
3423 | return false; | |
3424 | } | |
3425 | ||
3d34adec AK |
3426 | static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte) |
3427 | { | |
3428 | unsigned access; | |
3429 | ||
3430 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
3431 | access &= ~(gpte >> PT64_NX_SHIFT); | |
3432 | ||
3433 | return access; | |
3434 | } | |
3435 | ||
6fd01b71 AK |
3436 | static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte) |
3437 | { | |
3438 | unsigned index; | |
3439 | ||
3440 | index = level - 1; | |
3441 | index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2); | |
3442 | return mmu->last_pte_bitmap & (1 << index); | |
3443 | } | |
3444 | ||
6aa8b732 AK |
3445 | #define PTTYPE 64 |
3446 | #include "paging_tmpl.h" | |
3447 | #undef PTTYPE | |
3448 | ||
3449 | #define PTTYPE 32 | |
3450 | #include "paging_tmpl.h" | |
3451 | #undef PTTYPE | |
3452 | ||
52fde8df | 3453 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4d6931c3 | 3454 | struct kvm_mmu *context) |
82725b20 | 3455 | { |
82725b20 DE |
3456 | int maxphyaddr = cpuid_maxphyaddr(vcpu); |
3457 | u64 exb_bit_rsvd = 0; | |
3458 | ||
2d48a985 | 3459 | if (!context->nx) |
82725b20 | 3460 | exb_bit_rsvd = rsvd_bits(63, 63); |
4d6931c3 | 3461 | switch (context->root_level) { |
82725b20 DE |
3462 | case PT32_ROOT_LEVEL: |
3463 | /* no rsvd bits for 2 level 4K page table entries */ | |
3464 | context->rsvd_bits_mask[0][1] = 0; | |
3465 | context->rsvd_bits_mask[0][0] = 0; | |
f815bce8 XG |
3466 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
3467 | ||
3468 | if (!is_pse(vcpu)) { | |
3469 | context->rsvd_bits_mask[1][1] = 0; | |
3470 | break; | |
3471 | } | |
3472 | ||
82725b20 DE |
3473 | if (is_cpuid_PSE36()) |
3474 | /* 36bits PSE 4MB page */ | |
3475 | context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); | |
3476 | else | |
3477 | /* 32 bits PSE 4MB page */ | |
3478 | context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); | |
82725b20 DE |
3479 | break; |
3480 | case PT32E_ROOT_LEVEL: | |
20c466b5 DE |
3481 | context->rsvd_bits_mask[0][2] = |
3482 | rsvd_bits(maxphyaddr, 63) | | |
3483 | rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ | |
82725b20 | 3484 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3485 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
82725b20 DE |
3486 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3487 | rsvd_bits(maxphyaddr, 62); /* PTE */ | |
3488 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | | |
3489 | rsvd_bits(maxphyaddr, 62) | | |
3490 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3491 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3492 | break; |
3493 | case PT64_ROOT_LEVEL: | |
3494 | context->rsvd_bits_mask[0][3] = exb_bit_rsvd | | |
3495 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3496 | context->rsvd_bits_mask[0][2] = exb_bit_rsvd | | |
3497 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); | |
3498 | context->rsvd_bits_mask[0][1] = exb_bit_rsvd | | |
4c26b4cd | 3499 | rsvd_bits(maxphyaddr, 51); |
82725b20 DE |
3500 | context->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
3501 | rsvd_bits(maxphyaddr, 51); | |
3502 | context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; | |
e04da980 JR |
3503 | context->rsvd_bits_mask[1][2] = exb_bit_rsvd | |
3504 | rsvd_bits(maxphyaddr, 51) | | |
3505 | rsvd_bits(13, 29); | |
82725b20 | 3506 | context->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3507 | rsvd_bits(maxphyaddr, 51) | |
3508 | rsvd_bits(13, 20); /* large page */ | |
f815bce8 | 3509 | context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0]; |
82725b20 DE |
3510 | break; |
3511 | } | |
3512 | } | |
3513 | ||
97d64b78 AK |
3514 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3515 | { | |
3516 | unsigned bit, byte, pfec; | |
3517 | u8 map; | |
3518 | bool fault, x, w, u, wf, uf, ff, smep; | |
3519 | ||
3520 | smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); | |
3521 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { | |
3522 | pfec = byte << 1; | |
3523 | map = 0; | |
3524 | wf = pfec & PFERR_WRITE_MASK; | |
3525 | uf = pfec & PFERR_USER_MASK; | |
3526 | ff = pfec & PFERR_FETCH_MASK; | |
3527 | for (bit = 0; bit < 8; ++bit) { | |
3528 | x = bit & ACC_EXEC_MASK; | |
3529 | w = bit & ACC_WRITE_MASK; | |
3530 | u = bit & ACC_USER_MASK; | |
3531 | ||
3532 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3533 | x |= !mmu->nx; | |
3534 | /* Allow supervisor writes if !cr0.wp */ | |
3535 | w |= !is_write_protection(vcpu) && !uf; | |
3536 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
3537 | x &= !(smep && u && !uf); | |
3538 | ||
3539 | fault = (ff && !x) || (uf && !u) || (wf && !w); | |
3540 | map |= fault << bit; | |
3541 | } | |
3542 | mmu->permissions[byte] = map; | |
3543 | } | |
3544 | } | |
3545 | ||
6fd01b71 AK |
3546 | static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
3547 | { | |
3548 | u8 map; | |
3549 | unsigned level, root_level = mmu->root_level; | |
3550 | const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */ | |
3551 | ||
3552 | if (root_level == PT32E_ROOT_LEVEL) | |
3553 | --root_level; | |
3554 | /* PT_PAGE_TABLE_LEVEL always terminates */ | |
3555 | map = 1 | (1 << ps_set_index); | |
3556 | for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) { | |
3557 | if (level <= PT_PDPE_LEVEL | |
3558 | && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu))) | |
3559 | map |= 1 << (ps_set_index | (level - 1)); | |
3560 | } | |
3561 | mmu->last_pte_bitmap = map; | |
3562 | } | |
3563 | ||
52fde8df JR |
3564 | static int paging64_init_context_common(struct kvm_vcpu *vcpu, |
3565 | struct kvm_mmu *context, | |
3566 | int level) | |
6aa8b732 | 3567 | { |
2d48a985 | 3568 | context->nx = is_nx(vcpu); |
4d6931c3 | 3569 | context->root_level = level; |
2d48a985 | 3570 | |
4d6931c3 | 3571 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3572 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3573 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3574 | |
3575 | ASSERT(is_pae(vcpu)); | |
3576 | context->new_cr3 = paging_new_cr3; | |
3577 | context->page_fault = paging64_page_fault; | |
6aa8b732 | 3578 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 3579 | context->sync_page = paging64_sync_page; |
a7052897 | 3580 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 3581 | context->update_pte = paging64_update_pte; |
6aa8b732 | 3582 | context->free = paging_free; |
17ac10ad | 3583 | context->shadow_root_level = level; |
17c3ba9d | 3584 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3585 | context->direct_map = false; |
6aa8b732 AK |
3586 | return 0; |
3587 | } | |
3588 | ||
52fde8df JR |
3589 | static int paging64_init_context(struct kvm_vcpu *vcpu, |
3590 | struct kvm_mmu *context) | |
17ac10ad | 3591 | { |
52fde8df | 3592 | return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
3593 | } |
3594 | ||
52fde8df JR |
3595 | static int paging32_init_context(struct kvm_vcpu *vcpu, |
3596 | struct kvm_mmu *context) | |
6aa8b732 | 3597 | { |
2d48a985 | 3598 | context->nx = false; |
4d6931c3 | 3599 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 3600 | |
4d6931c3 | 3601 | reset_rsvds_bits_mask(vcpu, context); |
97d64b78 | 3602 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3603 | update_last_pte_bitmap(vcpu, context); |
6aa8b732 AK |
3604 | |
3605 | context->new_cr3 = paging_new_cr3; | |
3606 | context->page_fault = paging32_page_fault; | |
6aa8b732 AK |
3607 | context->gva_to_gpa = paging32_gva_to_gpa; |
3608 | context->free = paging_free; | |
e8bc217a | 3609 | context->sync_page = paging32_sync_page; |
a7052897 | 3610 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 3611 | context->update_pte = paging32_update_pte; |
6aa8b732 | 3612 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3613 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3614 | context->direct_map = false; |
6aa8b732 AK |
3615 | return 0; |
3616 | } | |
3617 | ||
52fde8df JR |
3618 | static int paging32E_init_context(struct kvm_vcpu *vcpu, |
3619 | struct kvm_mmu *context) | |
6aa8b732 | 3620 | { |
52fde8df | 3621 | return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
3622 | } |
3623 | ||
fb72d167 JR |
3624 | static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
3625 | { | |
14dfe855 | 3626 | struct kvm_mmu *context = vcpu->arch.walk_mmu; |
fb72d167 | 3627 | |
c445f8ef | 3628 | context->base_role.word = 0; |
fb72d167 JR |
3629 | context->new_cr3 = nonpaging_new_cr3; |
3630 | context->page_fault = tdp_page_fault; | |
3631 | context->free = nonpaging_free; | |
e8bc217a | 3632 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3633 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3634 | context->update_pte = nonpaging_update_pte; |
67253af5 | 3635 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 3636 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3637 | context->direct_map = true; |
1c97f0a0 | 3638 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 3639 | context->get_cr3 = get_cr3; |
e4e517b4 | 3640 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 3641 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
3642 | |
3643 | if (!is_paging(vcpu)) { | |
2d48a985 | 3644 | context->nx = false; |
fb72d167 JR |
3645 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
3646 | context->root_level = 0; | |
3647 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3648 | context->nx = is_nx(vcpu); |
fb72d167 | 3649 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
3650 | reset_rsvds_bits_mask(vcpu, context); |
3651 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3652 | } else if (is_pae(vcpu)) { |
2d48a985 | 3653 | context->nx = is_nx(vcpu); |
fb72d167 | 3654 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
3655 | reset_rsvds_bits_mask(vcpu, context); |
3656 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 3657 | } else { |
2d48a985 | 3658 | context->nx = false; |
fb72d167 | 3659 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
3660 | reset_rsvds_bits_mask(vcpu, context); |
3661 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
3662 | } |
3663 | ||
97d64b78 | 3664 | update_permission_bitmask(vcpu, context); |
6fd01b71 | 3665 | update_last_pte_bitmap(vcpu, context); |
97d64b78 | 3666 | |
fb72d167 JR |
3667 | return 0; |
3668 | } | |
3669 | ||
52fde8df | 3670 | int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context) |
6aa8b732 | 3671 | { |
a770f6f2 | 3672 | int r; |
411c588d | 3673 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
6aa8b732 | 3674 | ASSERT(vcpu); |
ad312c7c | 3675 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 AK |
3676 | |
3677 | if (!is_paging(vcpu)) | |
52fde8df | 3678 | r = nonpaging_init_context(vcpu, context); |
a9058ecd | 3679 | else if (is_long_mode(vcpu)) |
52fde8df | 3680 | r = paging64_init_context(vcpu, context); |
6aa8b732 | 3681 | else if (is_pae(vcpu)) |
52fde8df | 3682 | r = paging32E_init_context(vcpu, context); |
6aa8b732 | 3683 | else |
52fde8df | 3684 | r = paging32_init_context(vcpu, context); |
a770f6f2 | 3685 | |
5b7e0102 | 3686 | vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu); |
f43addd4 | 3687 | vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu); |
411c588d AK |
3688 | vcpu->arch.mmu.base_role.smep_andnot_wp |
3689 | = smep && !is_write_protection(vcpu); | |
52fde8df JR |
3690 | |
3691 | return r; | |
3692 | } | |
3693 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
3694 | ||
3695 | static int init_kvm_softmmu(struct kvm_vcpu *vcpu) | |
3696 | { | |
14dfe855 | 3697 | int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu); |
52fde8df | 3698 | |
14dfe855 JR |
3699 | vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3; |
3700 | vcpu->arch.walk_mmu->get_cr3 = get_cr3; | |
e4e517b4 | 3701 | vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read; |
14dfe855 | 3702 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; |
a770f6f2 AK |
3703 | |
3704 | return r; | |
6aa8b732 AK |
3705 | } |
3706 | ||
02f59dc9 JR |
3707 | static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
3708 | { | |
3709 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
3710 | ||
3711 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 3712 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
3713 | g_context->inject_page_fault = kvm_inject_page_fault; |
3714 | ||
3715 | /* | |
3716 | * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The | |
3717 | * translation of l2_gpa to l1_gpa addresses is done using the | |
3718 | * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa | |
3719 | * functions between mmu and nested_mmu are swapped. | |
3720 | */ | |
3721 | if (!is_paging(vcpu)) { | |
2d48a985 | 3722 | g_context->nx = false; |
02f59dc9 JR |
3723 | g_context->root_level = 0; |
3724 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
3725 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 3726 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3727 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 3728 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3729 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3730 | } else if (is_pae(vcpu)) { | |
2d48a985 | 3731 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 3732 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 3733 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3734 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
3735 | } else { | |
2d48a985 | 3736 | g_context->nx = false; |
02f59dc9 | 3737 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 3738 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
3739 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
3740 | } | |
3741 | ||
97d64b78 | 3742 | update_permission_bitmask(vcpu, g_context); |
6fd01b71 | 3743 | update_last_pte_bitmap(vcpu, g_context); |
97d64b78 | 3744 | |
02f59dc9 JR |
3745 | return 0; |
3746 | } | |
3747 | ||
fb72d167 JR |
3748 | static int init_kvm_mmu(struct kvm_vcpu *vcpu) |
3749 | { | |
02f59dc9 JR |
3750 | if (mmu_is_nested(vcpu)) |
3751 | return init_kvm_nested_mmu(vcpu); | |
3752 | else if (tdp_enabled) | |
fb72d167 JR |
3753 | return init_kvm_tdp_mmu(vcpu); |
3754 | else | |
3755 | return init_kvm_softmmu(vcpu); | |
3756 | } | |
3757 | ||
6aa8b732 AK |
3758 | static void destroy_kvm_mmu(struct kvm_vcpu *vcpu) |
3759 | { | |
3760 | ASSERT(vcpu); | |
62ad0755 SY |
3761 | if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3762 | /* mmu.free() should set root_hpa = INVALID_PAGE */ | |
ad312c7c | 3763 | vcpu->arch.mmu.free(vcpu); |
6aa8b732 AK |
3764 | } |
3765 | ||
3766 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu) | |
17c3ba9d AK |
3767 | { |
3768 | destroy_kvm_mmu(vcpu); | |
f8f7e5ee | 3769 | return init_kvm_mmu(vcpu); |
17c3ba9d | 3770 | } |
8668a3c4 | 3771 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
3772 | |
3773 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 3774 | { |
714b93da AK |
3775 | int r; |
3776 | ||
e2dec939 | 3777 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
3778 | if (r) |
3779 | goto out; | |
8986ecc0 | 3780 | r = mmu_alloc_roots(vcpu); |
8facbbff | 3781 | spin_lock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3782 | mmu_sync_roots(vcpu); |
aaee2c94 | 3783 | spin_unlock(&vcpu->kvm->mmu_lock); |
8986ecc0 MT |
3784 | if (r) |
3785 | goto out; | |
3662cb1c | 3786 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 3787 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
3788 | out: |
3789 | return r; | |
6aa8b732 | 3790 | } |
17c3ba9d AK |
3791 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
3792 | ||
3793 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
3794 | { | |
3795 | mmu_free_roots(vcpu); | |
3796 | } | |
4b16184c | 3797 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 3798 | |
0028425f | 3799 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
3800 | struct kvm_mmu_page *sp, u64 *spte, |
3801 | const void *new) | |
0028425f | 3802 | { |
30945387 | 3803 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
3804 | ++vcpu->kvm->stat.mmu_pde_zapped; |
3805 | return; | |
30945387 | 3806 | } |
0028425f | 3807 | |
4cee5764 | 3808 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 3809 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
3810 | } |
3811 | ||
79539cec AK |
3812 | static bool need_remote_flush(u64 old, u64 new) |
3813 | { | |
3814 | if (!is_shadow_present_pte(old)) | |
3815 | return false; | |
3816 | if (!is_shadow_present_pte(new)) | |
3817 | return true; | |
3818 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
3819 | return true; | |
3820 | old ^= PT64_NX_MASK; | |
3821 | new ^= PT64_NX_MASK; | |
3822 | return (old & ~new & PT64_PERM_MASK) != 0; | |
3823 | } | |
3824 | ||
0671a8e7 XG |
3825 | static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page, |
3826 | bool remote_flush, bool local_flush) | |
79539cec | 3827 | { |
0671a8e7 XG |
3828 | if (zap_page) |
3829 | return; | |
3830 | ||
3831 | if (remote_flush) | |
79539cec | 3832 | kvm_flush_remote_tlbs(vcpu->kvm); |
0671a8e7 | 3833 | else if (local_flush) |
79539cec AK |
3834 | kvm_mmu_flush_tlb(vcpu); |
3835 | } | |
3836 | ||
889e5cbc XG |
3837 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
3838 | const u8 *new, int *bytes) | |
da4a00f0 | 3839 | { |
889e5cbc XG |
3840 | u64 gentry; |
3841 | int r; | |
72016f3a | 3842 | |
72016f3a AK |
3843 | /* |
3844 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
3845 | * as the current vcpu paging mode since we update the sptes only |
3846 | * when they have the same mode. | |
72016f3a | 3847 | */ |
889e5cbc | 3848 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 3849 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
3850 | *gpa &= ~(gpa_t)7; |
3851 | *bytes = 8; | |
3852 | r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8)); | |
72016f3a AK |
3853 | if (r) |
3854 | gentry = 0; | |
08e850c6 AK |
3855 | new = (const u8 *)&gentry; |
3856 | } | |
3857 | ||
889e5cbc | 3858 | switch (*bytes) { |
08e850c6 AK |
3859 | case 4: |
3860 | gentry = *(const u32 *)new; | |
3861 | break; | |
3862 | case 8: | |
3863 | gentry = *(const u64 *)new; | |
3864 | break; | |
3865 | default: | |
3866 | gentry = 0; | |
3867 | break; | |
72016f3a AK |
3868 | } |
3869 | ||
889e5cbc XG |
3870 | return gentry; |
3871 | } | |
3872 | ||
3873 | /* | |
3874 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
3875 | * or we may be forking, in which case it is better to unmap the page. | |
3876 | */ | |
a138fe75 | 3877 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 3878 | { |
a30f47cb XG |
3879 | /* |
3880 | * Skip write-flooding detected for the sp whose level is 1, because | |
3881 | * it can become unsync, then the guest page is not write-protected. | |
3882 | */ | |
f71fa31f | 3883 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 3884 | return false; |
3246af0e | 3885 | |
a30f47cb | 3886 | return ++sp->write_flooding_count >= 3; |
889e5cbc XG |
3887 | } |
3888 | ||
3889 | /* | |
3890 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
3891 | * indicate a page is not used as a page table. | |
3892 | */ | |
3893 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
3894 | int bytes) | |
3895 | { | |
3896 | unsigned offset, pte_size, misaligned; | |
3897 | ||
3898 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
3899 | gpa, bytes, sp->role.word); | |
3900 | ||
3901 | offset = offset_in_page(gpa); | |
3902 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
3903 | |
3904 | /* | |
3905 | * Sometimes, the OS only writes the last one bytes to update status | |
3906 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
3907 | */ | |
3908 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
3909 | return false; | |
3910 | ||
889e5cbc XG |
3911 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
3912 | misaligned |= bytes < 4; | |
3913 | ||
3914 | return misaligned; | |
3915 | } | |
3916 | ||
3917 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
3918 | { | |
3919 | unsigned page_offset, quadrant; | |
3920 | u64 *spte; | |
3921 | int level; | |
3922 | ||
3923 | page_offset = offset_in_page(gpa); | |
3924 | level = sp->role.level; | |
3925 | *nspte = 1; | |
3926 | if (!sp->role.cr4_pae) { | |
3927 | page_offset <<= 1; /* 32->64 */ | |
3928 | /* | |
3929 | * A 32-bit pde maps 4MB while the shadow pdes map | |
3930 | * only 2MB. So we need to double the offset again | |
3931 | * and zap two pdes instead of one. | |
3932 | */ | |
3933 | if (level == PT32_ROOT_LEVEL) { | |
3934 | page_offset &= ~7; /* kill rounding error */ | |
3935 | page_offset <<= 1; | |
3936 | *nspte = 2; | |
3937 | } | |
3938 | quadrant = page_offset >> PAGE_SHIFT; | |
3939 | page_offset &= ~PAGE_MASK; | |
3940 | if (quadrant != sp->role.quadrant) | |
3941 | return NULL; | |
3942 | } | |
3943 | ||
3944 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
3945 | return spte; | |
3946 | } | |
3947 | ||
3948 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, | |
3949 | const u8 *new, int bytes) | |
3950 | { | |
3951 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
3952 | union kvm_mmu_page_role mask = { .word = 0 }; | |
3953 | struct kvm_mmu_page *sp; | |
3954 | struct hlist_node *node; | |
3955 | LIST_HEAD(invalid_list); | |
3956 | u64 entry, gentry, *spte; | |
3957 | int npte; | |
a30f47cb | 3958 | bool remote_flush, local_flush, zap_page; |
889e5cbc XG |
3959 | |
3960 | /* | |
3961 | * If we don't have indirect shadow pages, it means no page is | |
3962 | * write-protected, so we can exit simply. | |
3963 | */ | |
3964 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
3965 | return; | |
3966 | ||
3967 | zap_page = remote_flush = local_flush = false; | |
3968 | ||
3969 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
3970 | ||
3971 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
3972 | ||
3973 | /* | |
3974 | * No need to care whether allocation memory is successful | |
3975 | * or not since pte prefetch is skiped if it does not have | |
3976 | * enough objects in the cache. | |
3977 | */ | |
3978 | mmu_topup_memory_caches(vcpu); | |
3979 | ||
3980 | spin_lock(&vcpu->kvm->mmu_lock); | |
3981 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 3982 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 3983 | |
fa1de2bf | 3984 | mask.cr0_wp = mask.cr4_pae = mask.nxe = 1; |
f41d335a | 3985 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) { |
a30f47cb | 3986 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 3987 | detect_write_flooding(sp)) { |
0671a8e7 | 3988 | zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
f41d335a | 3989 | &invalid_list); |
4cee5764 | 3990 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
3991 | continue; |
3992 | } | |
889e5cbc XG |
3993 | |
3994 | spte = get_written_sptes(sp, gpa, &npte); | |
3995 | if (!spte) | |
3996 | continue; | |
3997 | ||
0671a8e7 | 3998 | local_flush = true; |
ac1b714e | 3999 | while (npte--) { |
79539cec | 4000 | entry = *spte; |
38e3b2b2 | 4001 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4002 | if (gentry && |
4003 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4004 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4005 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
0671a8e7 XG |
4006 | if (!remote_flush && need_remote_flush(entry, *spte)) |
4007 | remote_flush = true; | |
ac1b714e | 4008 | ++spte; |
9b7a0325 | 4009 | } |
9b7a0325 | 4010 | } |
0671a8e7 | 4011 | mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush); |
d98ba053 | 4012 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
0375f7fa | 4013 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4014 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4015 | } |
4016 | ||
a436036b AK |
4017 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4018 | { | |
10589a46 MT |
4019 | gpa_t gpa; |
4020 | int r; | |
a436036b | 4021 | |
c5a78f2b | 4022 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4023 | return 0; |
4024 | ||
1871c602 | 4025 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4026 | |
10589a46 | 4027 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4028 | |
10589a46 | 4029 | return r; |
a436036b | 4030 | } |
577bdc49 | 4031 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4032 | |
22d95b12 | 4033 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu) |
ebeace86 | 4034 | { |
d98ba053 | 4035 | LIST_HEAD(invalid_list); |
103ad25a | 4036 | |
e0df7b9f | 4037 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES && |
3b80fffe | 4038 | !list_empty(&vcpu->kvm->arch.active_mmu_pages)) { |
4db35314 | 4039 | struct kvm_mmu_page *sp; |
ebeace86 | 4040 | |
f05e70ac | 4041 | sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev, |
4db35314 | 4042 | struct kvm_mmu_page, link); |
e0df7b9f | 4043 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4044 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4045 | } |
aa6bd187 | 4046 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4047 | } |
ebeace86 | 4048 | |
1cb3f3ae XG |
4049 | static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr) |
4050 | { | |
4051 | if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu)) | |
4052 | return vcpu_match_mmio_gpa(vcpu, addr); | |
4053 | ||
4054 | return vcpu_match_mmio_gva(vcpu, addr); | |
4055 | } | |
4056 | ||
dc25e89e AP |
4057 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4058 | void *insn, int insn_len) | |
3067714c | 4059 | { |
1cb3f3ae | 4060 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c AK |
4061 | enum emulation_result er; |
4062 | ||
56028d08 | 4063 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c AK |
4064 | if (r < 0) |
4065 | goto out; | |
4066 | ||
4067 | if (!r) { | |
4068 | r = 1; | |
4069 | goto out; | |
4070 | } | |
4071 | ||
1cb3f3ae XG |
4072 | if (is_mmio_page_fault(vcpu, cr2)) |
4073 | emulation_type = 0; | |
4074 | ||
4075 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); | |
3067714c AK |
4076 | |
4077 | switch (er) { | |
4078 | case EMULATE_DONE: | |
4079 | return 1; | |
4080 | case EMULATE_DO_MMIO: | |
4081 | ++vcpu->stat.mmio_exits; | |
6d77dbfc | 4082 | /* fall through */ |
3067714c | 4083 | case EMULATE_FAIL: |
3f5d18a9 | 4084 | return 0; |
3067714c AK |
4085 | default: |
4086 | BUG(); | |
4087 | } | |
4088 | out: | |
3067714c AK |
4089 | return r; |
4090 | } | |
4091 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4092 | ||
a7052897 MT |
4093 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4094 | { | |
a7052897 | 4095 | vcpu->arch.mmu.invlpg(vcpu, gva); |
a7052897 MT |
4096 | kvm_mmu_flush_tlb(vcpu); |
4097 | ++vcpu->stat.invlpg; | |
4098 | } | |
4099 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4100 | ||
18552672 JR |
4101 | void kvm_enable_tdp(void) |
4102 | { | |
4103 | tdp_enabled = true; | |
4104 | } | |
4105 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4106 | ||
5f4cb662 JR |
4107 | void kvm_disable_tdp(void) |
4108 | { | |
4109 | tdp_enabled = false; | |
4110 | } | |
4111 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4112 | ||
6aa8b732 AK |
4113 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4114 | { | |
ad312c7c | 4115 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4116 | if (vcpu->arch.mmu.lm_root != NULL) |
4117 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4118 | } |
4119 | ||
4120 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4121 | { | |
17ac10ad | 4122 | struct page *page; |
6aa8b732 AK |
4123 | int i; |
4124 | ||
4125 | ASSERT(vcpu); | |
4126 | ||
17ac10ad AK |
4127 | /* |
4128 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4129 | * Therefore we need to allocate shadow page tables in the first | |
4130 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4131 | */ | |
4132 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4133 | if (!page) | |
d7fa6ab2 WY |
4134 | return -ENOMEM; |
4135 | ||
ad312c7c | 4136 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4137 | for (i = 0; i < 4; ++i) |
ad312c7c | 4138 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4139 | |
6aa8b732 | 4140 | return 0; |
6aa8b732 AK |
4141 | } |
4142 | ||
8018c27b | 4143 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4144 | { |
6aa8b732 | 4145 | ASSERT(vcpu); |
e459e322 XG |
4146 | |
4147 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
4148 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4149 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4150 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4151 | |
8018c27b IM |
4152 | return alloc_mmu_pages(vcpu); |
4153 | } | |
6aa8b732 | 4154 | |
8018c27b IM |
4155 | int kvm_mmu_setup(struct kvm_vcpu *vcpu) |
4156 | { | |
4157 | ASSERT(vcpu); | |
ad312c7c | 4158 | ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4159 | |
8018c27b | 4160 | return init_kvm_mmu(vcpu); |
6aa8b732 AK |
4161 | } |
4162 | ||
90cb0529 | 4163 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) |
6aa8b732 | 4164 | { |
b99db1d3 TY |
4165 | struct kvm_memory_slot *memslot; |
4166 | gfn_t last_gfn; | |
4167 | int i; | |
6aa8b732 | 4168 | |
b99db1d3 TY |
4169 | memslot = id_to_memslot(kvm->memslots, slot); |
4170 | last_gfn = memslot->base_gfn + memslot->npages - 1; | |
6aa8b732 | 4171 | |
b99db1d3 TY |
4172 | for (i = PT_PAGE_TABLE_LEVEL; |
4173 | i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) { | |
4174 | unsigned long *rmapp; | |
4175 | unsigned long last_index, index; | |
6aa8b732 | 4176 | |
b99db1d3 TY |
4177 | rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL]; |
4178 | last_index = gfn_to_index(last_gfn, memslot->base_gfn, i); | |
da8dc75f | 4179 | |
b99db1d3 TY |
4180 | for (index = 0; index <= last_index; ++index, ++rmapp) { |
4181 | if (*rmapp) | |
4182 | __rmap_write_protect(kvm, rmapp, false); | |
8234b22e | 4183 | } |
6aa8b732 | 4184 | } |
b99db1d3 | 4185 | |
171d595d | 4186 | kvm_flush_remote_tlbs(kvm); |
6aa8b732 | 4187 | } |
37a7d8b0 | 4188 | |
90cb0529 | 4189 | void kvm_mmu_zap_all(struct kvm *kvm) |
e0fa826f | 4190 | { |
4db35314 | 4191 | struct kvm_mmu_page *sp, *node; |
d98ba053 | 4192 | LIST_HEAD(invalid_list); |
e0fa826f | 4193 | |
aaee2c94 | 4194 | spin_lock(&kvm->mmu_lock); |
3246af0e | 4195 | restart: |
f05e70ac | 4196 | list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) |
d98ba053 | 4197 | if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list)) |
3246af0e XG |
4198 | goto restart; |
4199 | ||
d98ba053 | 4200 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
aaee2c94 | 4201 | spin_unlock(&kvm->mmu_lock); |
e0fa826f DL |
4202 | } |
4203 | ||
3d56cbdf JK |
4204 | static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm, |
4205 | struct list_head *invalid_list) | |
3ee16c81 IE |
4206 | { |
4207 | struct kvm_mmu_page *page; | |
4208 | ||
85b70591 XG |
4209 | if (list_empty(&kvm->arch.active_mmu_pages)) |
4210 | return; | |
4211 | ||
3ee16c81 IE |
4212 | page = container_of(kvm->arch.active_mmu_pages.prev, |
4213 | struct kvm_mmu_page, link); | |
3d56cbdf | 4214 | kvm_mmu_prepare_zap_page(kvm, page, invalid_list); |
3ee16c81 IE |
4215 | } |
4216 | ||
1495f230 | 4217 | static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc) |
3ee16c81 IE |
4218 | { |
4219 | struct kvm *kvm; | |
1495f230 | 4220 | int nr_to_scan = sc->nr_to_scan; |
45221ab6 DH |
4221 | |
4222 | if (nr_to_scan == 0) | |
4223 | goto out; | |
3ee16c81 | 4224 | |
e935b837 | 4225 | raw_spin_lock(&kvm_lock); |
3ee16c81 IE |
4226 | |
4227 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4228 | int idx; |
d98ba053 | 4229 | LIST_HEAD(invalid_list); |
3ee16c81 | 4230 | |
35f2d16b TY |
4231 | /* |
4232 | * Never scan more than sc->nr_to_scan VM instances. | |
4233 | * Will not hit this condition practically since we do not try | |
4234 | * to shrink more than one VM and it is very unlikely to see | |
4235 | * !n_used_mmu_pages so many times. | |
4236 | */ | |
4237 | if (!nr_to_scan--) | |
4238 | break; | |
19526396 GN |
4239 | /* |
4240 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4241 | * here. We may skip a VM instance errorneosly, but we do not | |
4242 | * want to shrink a VM that only started to populate its MMU | |
4243 | * anyway. | |
4244 | */ | |
35f2d16b | 4245 | if (!kvm->arch.n_used_mmu_pages) |
19526396 | 4246 | continue; |
19526396 | 4247 | |
f656ce01 | 4248 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4249 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4250 | |
19526396 | 4251 | kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list); |
d98ba053 | 4252 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 4253 | |
3ee16c81 | 4254 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 4255 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 GN |
4256 | |
4257 | list_move_tail(&kvm->vm_list, &vm_list); | |
4258 | break; | |
3ee16c81 | 4259 | } |
3ee16c81 | 4260 | |
e935b837 | 4261 | raw_spin_unlock(&kvm_lock); |
3ee16c81 | 4262 | |
45221ab6 DH |
4263 | out: |
4264 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); | |
3ee16c81 IE |
4265 | } |
4266 | ||
4267 | static struct shrinker mmu_shrinker = { | |
4268 | .shrink = mmu_shrink, | |
4269 | .seeks = DEFAULT_SEEKS * 10, | |
4270 | }; | |
4271 | ||
2ddfd20e | 4272 | static void mmu_destroy_caches(void) |
b5a33a75 | 4273 | { |
53c07b18 XG |
4274 | if (pte_list_desc_cache) |
4275 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
4276 | if (mmu_page_header_cache) |
4277 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
4278 | } |
4279 | ||
4280 | int kvm_mmu_module_init(void) | |
4281 | { | |
53c07b18 XG |
4282 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
4283 | sizeof(struct pte_list_desc), | |
20c2df83 | 4284 | 0, 0, NULL); |
53c07b18 | 4285 | if (!pte_list_desc_cache) |
b5a33a75 AK |
4286 | goto nomem; |
4287 | ||
d3d25b04 AK |
4288 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
4289 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 4290 | 0, 0, NULL); |
d3d25b04 AK |
4291 | if (!mmu_page_header_cache) |
4292 | goto nomem; | |
4293 | ||
45bf21a8 WY |
4294 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0)) |
4295 | goto nomem; | |
4296 | ||
3ee16c81 IE |
4297 | register_shrinker(&mmu_shrinker); |
4298 | ||
b5a33a75 AK |
4299 | return 0; |
4300 | ||
4301 | nomem: | |
3ee16c81 | 4302 | mmu_destroy_caches(); |
b5a33a75 AK |
4303 | return -ENOMEM; |
4304 | } | |
4305 | ||
3ad82a7e ZX |
4306 | /* |
4307 | * Caculate mmu pages needed for kvm. | |
4308 | */ | |
4309 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
4310 | { | |
3ad82a7e ZX |
4311 | unsigned int nr_mmu_pages; |
4312 | unsigned int nr_pages = 0; | |
bc6678a3 | 4313 | struct kvm_memslots *slots; |
be6ba0f0 | 4314 | struct kvm_memory_slot *memslot; |
3ad82a7e | 4315 | |
90d83dc3 LJ |
4316 | slots = kvm_memslots(kvm); |
4317 | ||
be6ba0f0 XG |
4318 | kvm_for_each_memslot(memslot, slots) |
4319 | nr_pages += memslot->npages; | |
3ad82a7e ZX |
4320 | |
4321 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
4322 | nr_mmu_pages = max(nr_mmu_pages, | |
4323 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); | |
4324 | ||
4325 | return nr_mmu_pages; | |
4326 | } | |
4327 | ||
94d8b056 MT |
4328 | int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]) |
4329 | { | |
4330 | struct kvm_shadow_walk_iterator iterator; | |
c2a2ac2b | 4331 | u64 spte; |
94d8b056 MT |
4332 | int nr_sptes = 0; |
4333 | ||
c2a2ac2b XG |
4334 | walk_shadow_page_lockless_begin(vcpu); |
4335 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
4336 | sptes[iterator.level-1] = spte; | |
94d8b056 | 4337 | nr_sptes++; |
c2a2ac2b | 4338 | if (!is_shadow_present_pte(spte)) |
94d8b056 MT |
4339 | break; |
4340 | } | |
c2a2ac2b | 4341 | walk_shadow_page_lockless_end(vcpu); |
94d8b056 MT |
4342 | |
4343 | return nr_sptes; | |
4344 | } | |
4345 | EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy); | |
4346 | ||
c42fffe3 XG |
4347 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
4348 | { | |
4349 | ASSERT(vcpu); | |
4350 | ||
4351 | destroy_kvm_mmu(vcpu); | |
4352 | free_mmu_pages(vcpu); | |
4353 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
4354 | } |
4355 | ||
b034cf01 XG |
4356 | void kvm_mmu_module_exit(void) |
4357 | { | |
4358 | mmu_destroy_caches(); | |
4359 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
4360 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
4361 | mmu_audit_disable(); |
4362 | } |