Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
32 | #include <linux/module.h> | |
448353ca | 33 | #include <linux/swap.h> |
05da4558 | 34 | #include <linux/hugetlb.h> |
2f333bcb | 35 | #include <linux/compiler.h> |
bc6678a3 | 36 | #include <linux/srcu.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
bf998156 | 38 | #include <linux/uaccess.h> |
6aa8b732 | 39 | |
e495606d AK |
40 | #include <asm/page.h> |
41 | #include <asm/cmpxchg.h> | |
4e542370 | 42 | #include <asm/io.h> |
13673a90 | 43 | #include <asm/vmx.h> |
3d0c27ad | 44 | #include <asm/kvm_page_track.h> |
6aa8b732 | 45 | |
18552672 JR |
46 | /* |
47 | * When setting this variable to true it enables Two-Dimensional-Paging | |
48 | * where the hardware walks 2 page tables: | |
49 | * 1. the guest-virtual to guest-physical | |
50 | * 2. while doing 1. it walks guest-physical to host-physical | |
51 | * If the hardware supports that we don't need to do shadow paging. | |
52 | */ | |
2f333bcb | 53 | bool tdp_enabled = false; |
18552672 | 54 | |
8b1fe17c XG |
55 | enum { |
56 | AUDIT_PRE_PAGE_FAULT, | |
57 | AUDIT_POST_PAGE_FAULT, | |
58 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
59 | AUDIT_POST_PTE_WRITE, |
60 | AUDIT_PRE_SYNC, | |
61 | AUDIT_POST_SYNC | |
8b1fe17c | 62 | }; |
37a7d8b0 | 63 | |
8b1fe17c | 64 | #undef MMU_DEBUG |
37a7d8b0 AK |
65 | |
66 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
67 | static bool dbg = 0; |
68 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
69 | |
70 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
71 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 72 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 73 | #else |
37a7d8b0 AK |
74 | #define pgprintk(x...) do { } while (0) |
75 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 76 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 77 | #endif |
6aa8b732 | 78 | |
957ed9ef XG |
79 | #define PTE_PREFETCH_NUM 8 |
80 | ||
00763e41 | 81 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
82 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
83 | ||
6aa8b732 AK |
84 | #define PT64_LEVEL_BITS 9 |
85 | ||
86 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 87 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 88 | |
6aa8b732 AK |
89 | #define PT64_INDEX(address, level)\ |
90 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
91 | ||
92 | ||
93 | #define PT32_LEVEL_BITS 10 | |
94 | ||
95 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 96 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 97 | |
e04da980 JR |
98 | #define PT32_LVL_OFFSET_MASK(level) \ |
99 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
100 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
101 | |
102 | #define PT32_INDEX(address, level)\ | |
103 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
104 | ||
105 | ||
27aba766 | 106 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) |
6aa8b732 AK |
107 | #define PT64_DIR_BASE_ADDR_MASK \ |
108 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1)) | |
e04da980 JR |
109 | #define PT64_LVL_ADDR_MASK(level) \ |
110 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
111 | * PT64_LEVEL_BITS))) - 1)) | |
112 | #define PT64_LVL_OFFSET_MASK(level) \ | |
113 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
114 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
115 | |
116 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
117 | #define PT32_DIR_BASE_ADDR_MASK \ | |
118 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
119 | #define PT32_LVL_ADDR_MASK(level) \ |
120 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
121 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 122 | |
53166229 GN |
123 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
124 | | shadow_x_mask | shadow_nx_mask) | |
6aa8b732 | 125 | |
fe135d2c AK |
126 | #define ACC_EXEC_MASK 1 |
127 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
128 | #define ACC_USER_MASK PT_USER_MASK | |
129 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
130 | ||
90bb6fc5 AK |
131 | #include <trace/events/kvm.h> |
132 | ||
07420171 AK |
133 | #define CREATE_TRACE_POINTS |
134 | #include "mmutrace.h" | |
135 | ||
49fde340 XG |
136 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
137 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 138 | |
135f8c2b AK |
139 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
140 | ||
220f773a TY |
141 | /* make pte_list_desc fit well in cache line */ |
142 | #define PTE_LIST_EXT 3 | |
143 | ||
53c07b18 XG |
144 | struct pte_list_desc { |
145 | u64 *sptes[PTE_LIST_EXT]; | |
146 | struct pte_list_desc *more; | |
cd4a4e53 AK |
147 | }; |
148 | ||
2d11123a AK |
149 | struct kvm_shadow_walk_iterator { |
150 | u64 addr; | |
151 | hpa_t shadow_addr; | |
2d11123a | 152 | u64 *sptep; |
dd3bfd59 | 153 | int level; |
2d11123a AK |
154 | unsigned index; |
155 | }; | |
156 | ||
157 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
158 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
159 | shadow_walk_okay(&(_walker)); \ | |
160 | shadow_walk_next(&(_walker))) | |
161 | ||
c2a2ac2b XG |
162 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
163 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
164 | shadow_walk_okay(&(_walker)) && \ | |
165 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
166 | __shadow_walk_next(&(_walker), spte)) | |
167 | ||
53c07b18 | 168 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 169 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 170 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 171 | |
7b52345e SY |
172 | static u64 __read_mostly shadow_nx_mask; |
173 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
174 | static u64 __read_mostly shadow_user_mask; | |
175 | static u64 __read_mostly shadow_accessed_mask; | |
176 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf XG |
177 | static u64 __read_mostly shadow_mmio_mask; |
178 | ||
179 | static void mmu_spte_set(u64 *sptep, u64 spte); | |
e676505a | 180 | static void mmu_free_roots(struct kvm_vcpu *vcpu); |
ce88decf XG |
181 | |
182 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask) | |
183 | { | |
184 | shadow_mmio_mask = mmio_mask; | |
185 | } | |
186 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
187 | ||
f2fd125d | 188 | /* |
ee3d1570 DM |
189 | * the low bit of the generation number is always presumed to be zero. |
190 | * This disables mmio caching during memslot updates. The concept is | |
191 | * similar to a seqcount but instead of retrying the access we just punt | |
192 | * and ignore the cache. | |
193 | * | |
194 | * spte bits 3-11 are used as bits 1-9 of the generation number, | |
195 | * the bits 52-61 are used as bits 10-19 of the generation number. | |
f2fd125d | 196 | */ |
ee3d1570 | 197 | #define MMIO_SPTE_GEN_LOW_SHIFT 2 |
f2fd125d XG |
198 | #define MMIO_SPTE_GEN_HIGH_SHIFT 52 |
199 | ||
ee3d1570 DM |
200 | #define MMIO_GEN_SHIFT 20 |
201 | #define MMIO_GEN_LOW_SHIFT 10 | |
202 | #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2) | |
f8f55942 | 203 | #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1) |
f2fd125d XG |
204 | |
205 | static u64 generation_mmio_spte_mask(unsigned int gen) | |
206 | { | |
207 | u64 mask; | |
208 | ||
842bb26a | 209 | WARN_ON(gen & ~MMIO_GEN_MASK); |
f2fd125d XG |
210 | |
211 | mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT; | |
212 | mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT; | |
213 | return mask; | |
214 | } | |
215 | ||
216 | static unsigned int get_mmio_spte_generation(u64 spte) | |
217 | { | |
218 | unsigned int gen; | |
219 | ||
220 | spte &= ~shadow_mmio_mask; | |
221 | ||
222 | gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK; | |
223 | gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT; | |
224 | return gen; | |
225 | } | |
226 | ||
54bf36aa | 227 | static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu) |
f8f55942 | 228 | { |
54bf36aa | 229 | return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK; |
f8f55942 XG |
230 | } |
231 | ||
54bf36aa | 232 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 233 | unsigned access) |
ce88decf | 234 | { |
54bf36aa | 235 | unsigned int gen = kvm_current_mmio_generation(vcpu); |
f8f55942 | 236 | u64 mask = generation_mmio_spte_mask(gen); |
95b0430d | 237 | |
ce88decf | 238 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
f2fd125d | 239 | mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT; |
f2fd125d | 240 | |
f8f55942 | 241 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 242 | mmu_spte_set(sptep, mask); |
ce88decf XG |
243 | } |
244 | ||
245 | static bool is_mmio_spte(u64 spte) | |
246 | { | |
247 | return (spte & shadow_mmio_mask) == shadow_mmio_mask; | |
248 | } | |
249 | ||
250 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
251 | { | |
842bb26a | 252 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 253 | return (spte & ~mask) >> PAGE_SHIFT; |
ce88decf XG |
254 | } |
255 | ||
256 | static unsigned get_mmio_spte_access(u64 spte) | |
257 | { | |
842bb26a | 258 | u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 259 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
260 | } |
261 | ||
54bf36aa | 262 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 263 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
264 | { |
265 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 266 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
267 | return true; |
268 | } | |
269 | ||
270 | return false; | |
271 | } | |
c7addb90 | 272 | |
54bf36aa | 273 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 274 | { |
089504c0 XG |
275 | unsigned int kvm_gen, spte_gen; |
276 | ||
54bf36aa | 277 | kvm_gen = kvm_current_mmio_generation(vcpu); |
089504c0 XG |
278 | spte_gen = get_mmio_spte_generation(spte); |
279 | ||
280 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
281 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
282 | } |
283 | ||
7b52345e | 284 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 285 | u64 dirty_mask, u64 nx_mask, u64 x_mask) |
7b52345e SY |
286 | { |
287 | shadow_user_mask = user_mask; | |
288 | shadow_accessed_mask = accessed_mask; | |
289 | shadow_dirty_mask = dirty_mask; | |
290 | shadow_nx_mask = nx_mask; | |
291 | shadow_x_mask = x_mask; | |
292 | } | |
293 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
294 | ||
6aa8b732 AK |
295 | static int is_cpuid_PSE36(void) |
296 | { | |
297 | return 1; | |
298 | } | |
299 | ||
73b1087e AK |
300 | static int is_nx(struct kvm_vcpu *vcpu) |
301 | { | |
f6801dff | 302 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
303 | } |
304 | ||
c7addb90 AK |
305 | static int is_shadow_present_pte(u64 pte) |
306 | { | |
ce88decf | 307 | return pte & PT_PRESENT_MASK && !is_mmio_spte(pte); |
c7addb90 AK |
308 | } |
309 | ||
05da4558 MT |
310 | static int is_large_pte(u64 pte) |
311 | { | |
312 | return pte & PT_PAGE_SIZE_MASK; | |
313 | } | |
314 | ||
776e6633 MT |
315 | static int is_last_spte(u64 pte, int level) |
316 | { | |
317 | if (level == PT_PAGE_TABLE_LEVEL) | |
318 | return 1; | |
852e3c19 | 319 | if (is_large_pte(pte)) |
776e6633 MT |
320 | return 1; |
321 | return 0; | |
322 | } | |
323 | ||
ba049e93 | 324 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 325 | { |
35149e21 | 326 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
327 | } |
328 | ||
da928521 AK |
329 | static gfn_t pse36_gfn_delta(u32 gpte) |
330 | { | |
331 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
332 | ||
333 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
334 | } | |
335 | ||
603e0651 | 336 | #ifdef CONFIG_X86_64 |
d555c333 | 337 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 338 | { |
603e0651 | 339 | *sptep = spte; |
e663ee64 AK |
340 | } |
341 | ||
603e0651 | 342 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 343 | { |
603e0651 XG |
344 | *sptep = spte; |
345 | } | |
346 | ||
347 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
348 | { | |
349 | return xchg(sptep, spte); | |
350 | } | |
c2a2ac2b XG |
351 | |
352 | static u64 __get_spte_lockless(u64 *sptep) | |
353 | { | |
354 | return ACCESS_ONCE(*sptep); | |
355 | } | |
a9221dd5 | 356 | #else |
603e0651 XG |
357 | union split_spte { |
358 | struct { | |
359 | u32 spte_low; | |
360 | u32 spte_high; | |
361 | }; | |
362 | u64 spte; | |
363 | }; | |
a9221dd5 | 364 | |
c2a2ac2b XG |
365 | static void count_spte_clear(u64 *sptep, u64 spte) |
366 | { | |
367 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
368 | ||
369 | if (is_shadow_present_pte(spte)) | |
370 | return; | |
371 | ||
372 | /* Ensure the spte is completely set before we increase the count */ | |
373 | smp_wmb(); | |
374 | sp->clear_spte_count++; | |
375 | } | |
376 | ||
603e0651 XG |
377 | static void __set_spte(u64 *sptep, u64 spte) |
378 | { | |
379 | union split_spte *ssptep, sspte; | |
a9221dd5 | 380 | |
603e0651 XG |
381 | ssptep = (union split_spte *)sptep; |
382 | sspte = (union split_spte)spte; | |
383 | ||
384 | ssptep->spte_high = sspte.spte_high; | |
385 | ||
386 | /* | |
387 | * If we map the spte from nonpresent to present, We should store | |
388 | * the high bits firstly, then set present bit, so cpu can not | |
389 | * fetch this spte while we are setting the spte. | |
390 | */ | |
391 | smp_wmb(); | |
392 | ||
393 | ssptep->spte_low = sspte.spte_low; | |
a9221dd5 AK |
394 | } |
395 | ||
603e0651 XG |
396 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
397 | { | |
398 | union split_spte *ssptep, sspte; | |
399 | ||
400 | ssptep = (union split_spte *)sptep; | |
401 | sspte = (union split_spte)spte; | |
402 | ||
403 | ssptep->spte_low = sspte.spte_low; | |
404 | ||
405 | /* | |
406 | * If we map the spte from present to nonpresent, we should clear | |
407 | * present bit firstly to avoid vcpu fetch the old high bits. | |
408 | */ | |
409 | smp_wmb(); | |
410 | ||
411 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 412 | count_spte_clear(sptep, spte); |
603e0651 XG |
413 | } |
414 | ||
415 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
416 | { | |
417 | union split_spte *ssptep, sspte, orig; | |
418 | ||
419 | ssptep = (union split_spte *)sptep; | |
420 | sspte = (union split_spte)spte; | |
421 | ||
422 | /* xchg acts as a barrier before the setting of the high bits */ | |
423 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
424 | orig.spte_high = ssptep->spte_high; |
425 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 426 | count_spte_clear(sptep, spte); |
603e0651 XG |
427 | |
428 | return orig.spte; | |
429 | } | |
c2a2ac2b XG |
430 | |
431 | /* | |
432 | * The idea using the light way get the spte on x86_32 guest is from | |
433 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
434 | * |
435 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
436 | * coalesces them and we are running out of the MMU lock. Therefore | |
437 | * we need to protect against in-progress updates of the spte. | |
438 | * | |
439 | * Reading the spte while an update is in progress may get the old value | |
440 | * for the high part of the spte. The race is fine for a present->non-present | |
441 | * change (because the high part of the spte is ignored for non-present spte), | |
442 | * but for a present->present change we must reread the spte. | |
443 | * | |
444 | * All such changes are done in two steps (present->non-present and | |
445 | * non-present->present), hence it is enough to count the number of | |
446 | * present->non-present updates: if it changed while reading the spte, | |
447 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
448 | */ |
449 | static u64 __get_spte_lockless(u64 *sptep) | |
450 | { | |
451 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
452 | union split_spte spte, *orig = (union split_spte *)sptep; | |
453 | int count; | |
454 | ||
455 | retry: | |
456 | count = sp->clear_spte_count; | |
457 | smp_rmb(); | |
458 | ||
459 | spte.spte_low = orig->spte_low; | |
460 | smp_rmb(); | |
461 | ||
462 | spte.spte_high = orig->spte_high; | |
463 | smp_rmb(); | |
464 | ||
465 | if (unlikely(spte.spte_low != orig->spte_low || | |
466 | count != sp->clear_spte_count)) | |
467 | goto retry; | |
468 | ||
469 | return spte.spte; | |
470 | } | |
603e0651 XG |
471 | #endif |
472 | ||
c7ba5b48 XG |
473 | static bool spte_is_locklessly_modifiable(u64 spte) |
474 | { | |
feb3eb70 GN |
475 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
476 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
477 | } |
478 | ||
8672b721 XG |
479 | static bool spte_has_volatile_bits(u64 spte) |
480 | { | |
c7ba5b48 | 481 | /* |
6a6256f9 | 482 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
483 | * out of mmu-lock, it can ensure dirty bit is not lost, |
484 | * also, it can help us to get a stable is_writable_pte() | |
485 | * to ensure tlb flush is not missed. | |
486 | */ | |
487 | if (spte_is_locklessly_modifiable(spte)) | |
488 | return true; | |
489 | ||
8672b721 XG |
490 | if (!shadow_accessed_mask) |
491 | return false; | |
492 | ||
493 | if (!is_shadow_present_pte(spte)) | |
494 | return false; | |
495 | ||
4132779b XG |
496 | if ((spte & shadow_accessed_mask) && |
497 | (!is_writable_pte(spte) || (spte & shadow_dirty_mask))) | |
8672b721 XG |
498 | return false; |
499 | ||
500 | return true; | |
501 | } | |
502 | ||
4132779b XG |
503 | static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask) |
504 | { | |
505 | return (old_spte & bit_mask) && !(new_spte & bit_mask); | |
506 | } | |
507 | ||
7e71a59b KH |
508 | static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask) |
509 | { | |
510 | return (old_spte & bit_mask) != (new_spte & bit_mask); | |
511 | } | |
512 | ||
1df9f2dc XG |
513 | /* Rules for using mmu_spte_set: |
514 | * Set the sptep from nonpresent to present. | |
515 | * Note: the sptep being assigned *must* be either not present | |
516 | * or in a state where the hardware will not attempt to update | |
517 | * the spte. | |
518 | */ | |
519 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
520 | { | |
521 | WARN_ON(is_shadow_present_pte(*sptep)); | |
522 | __set_spte(sptep, new_spte); | |
523 | } | |
524 | ||
525 | /* Rules for using mmu_spte_update: | |
526 | * Update the state bits, it means the mapped pfn is not changged. | |
6e7d0354 XG |
527 | * |
528 | * Whenever we overwrite a writable spte with a read-only one we | |
529 | * should flush remote TLBs. Otherwise rmap_write_protect | |
530 | * will find a read-only spte, even though the writable spte | |
531 | * might be cached on a CPU's TLB, the return value indicates this | |
532 | * case. | |
1df9f2dc | 533 | */ |
6e7d0354 | 534 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) |
b79b93f9 | 535 | { |
c7ba5b48 | 536 | u64 old_spte = *sptep; |
6e7d0354 | 537 | bool ret = false; |
4132779b | 538 | |
afd28fe1 | 539 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 540 | |
6e7d0354 XG |
541 | if (!is_shadow_present_pte(old_spte)) { |
542 | mmu_spte_set(sptep, new_spte); | |
543 | return ret; | |
544 | } | |
4132779b | 545 | |
c7ba5b48 | 546 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 547 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 548 | else |
603e0651 | 549 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 550 | |
c7ba5b48 XG |
551 | /* |
552 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 553 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
554 | * spte_has_volatile_bits(). |
555 | */ | |
7f31c959 XG |
556 | if (spte_is_locklessly_modifiable(old_spte) && |
557 | !is_writable_pte(new_spte)) | |
6e7d0354 XG |
558 | ret = true; |
559 | ||
14f47605 YZ |
560 | if (!shadow_accessed_mask) { |
561 | /* | |
562 | * We don't set page dirty when dropping non-writable spte. | |
563 | * So do it now if the new spte is becoming non-writable. | |
564 | */ | |
565 | if (ret) | |
566 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 | 567 | return ret; |
14f47605 | 568 | } |
4132779b | 569 | |
7e71a59b KH |
570 | /* |
571 | * Flush TLB when accessed/dirty bits are changed in the page tables, | |
572 | * to guarantee consistency between TLB and page tables. | |
573 | */ | |
574 | if (spte_is_bit_changed(old_spte, new_spte, | |
575 | shadow_accessed_mask | shadow_dirty_mask)) | |
576 | ret = true; | |
577 | ||
4132779b XG |
578 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask)) |
579 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); | |
580 | if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask)) | |
581 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); | |
6e7d0354 XG |
582 | |
583 | return ret; | |
b79b93f9 AK |
584 | } |
585 | ||
1df9f2dc XG |
586 | /* |
587 | * Rules for using mmu_spte_clear_track_bits: | |
588 | * It sets the sptep from present to nonpresent, and track the | |
589 | * state bits, it is used to clear the last level sptep. | |
590 | */ | |
591 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
592 | { | |
ba049e93 | 593 | kvm_pfn_t pfn; |
1df9f2dc XG |
594 | u64 old_spte = *sptep; |
595 | ||
596 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 597 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 598 | else |
603e0651 | 599 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 600 | |
afd28fe1 | 601 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
602 | return 0; |
603 | ||
604 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
605 | |
606 | /* | |
607 | * KVM does not hold the refcount of the page used by | |
608 | * kvm mmu, before reclaiming the page, we should | |
609 | * unmap it from mmu first. | |
610 | */ | |
bf4bea8e | 611 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 612 | |
1df9f2dc XG |
613 | if (!shadow_accessed_mask || old_spte & shadow_accessed_mask) |
614 | kvm_set_pfn_accessed(pfn); | |
14f47605 YZ |
615 | if (old_spte & (shadow_dirty_mask ? shadow_dirty_mask : |
616 | PT_WRITABLE_MASK)) | |
1df9f2dc XG |
617 | kvm_set_pfn_dirty(pfn); |
618 | return 1; | |
619 | } | |
620 | ||
621 | /* | |
622 | * Rules for using mmu_spte_clear_no_track: | |
623 | * Directly clear spte without caring the state bits of sptep, | |
624 | * it is used to set the upper level spte. | |
625 | */ | |
626 | static void mmu_spte_clear_no_track(u64 *sptep) | |
627 | { | |
603e0651 | 628 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
629 | } |
630 | ||
c2a2ac2b XG |
631 | static u64 mmu_spte_get_lockless(u64 *sptep) |
632 | { | |
633 | return __get_spte_lockless(sptep); | |
634 | } | |
635 | ||
636 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) | |
637 | { | |
c142786c AK |
638 | /* |
639 | * Prevent page table teardown by making any free-er wait during | |
640 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
641 | */ | |
642 | local_irq_disable(); | |
36ca7e0a | 643 | |
c142786c AK |
644 | /* |
645 | * Make sure a following spte read is not reordered ahead of the write | |
646 | * to vcpu->mode. | |
647 | */ | |
36ca7e0a | 648 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
649 | } |
650 | ||
651 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
652 | { | |
c142786c AK |
653 | /* |
654 | * Make sure the write to vcpu->mode is not reordered in front of | |
655 | * reads to sptes. If it does, kvm_commit_zap_page() can see us | |
656 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. | |
657 | */ | |
36ca7e0a | 658 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 659 | local_irq_enable(); |
c2a2ac2b XG |
660 | } |
661 | ||
e2dec939 | 662 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 663 | struct kmem_cache *base_cache, int min) |
714b93da AK |
664 | { |
665 | void *obj; | |
666 | ||
667 | if (cache->nobjs >= min) | |
e2dec939 | 668 | return 0; |
714b93da | 669 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
2e3e5882 | 670 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL); |
714b93da | 671 | if (!obj) |
e2dec939 | 672 | return -ENOMEM; |
714b93da AK |
673 | cache->objects[cache->nobjs++] = obj; |
674 | } | |
e2dec939 | 675 | return 0; |
714b93da AK |
676 | } |
677 | ||
f759e2b4 XG |
678 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
679 | { | |
680 | return cache->nobjs; | |
681 | } | |
682 | ||
e8ad9a70 XG |
683 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
684 | struct kmem_cache *cache) | |
714b93da AK |
685 | { |
686 | while (mc->nobjs) | |
e8ad9a70 | 687 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
688 | } |
689 | ||
c1158e63 | 690 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 691 | int min) |
c1158e63 | 692 | { |
842f22ed | 693 | void *page; |
c1158e63 AK |
694 | |
695 | if (cache->nobjs >= min) | |
696 | return 0; | |
697 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
842f22ed | 698 | page = (void *)__get_free_page(GFP_KERNEL); |
c1158e63 AK |
699 | if (!page) |
700 | return -ENOMEM; | |
842f22ed | 701 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
702 | } |
703 | return 0; | |
704 | } | |
705 | ||
706 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
707 | { | |
708 | while (mc->nobjs) | |
c4d198d5 | 709 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
710 | } |
711 | ||
2e3e5882 | 712 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 713 | { |
e2dec939 AK |
714 | int r; |
715 | ||
53c07b18 | 716 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 717 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
718 | if (r) |
719 | goto out; | |
ad312c7c | 720 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
721 | if (r) |
722 | goto out; | |
ad312c7c | 723 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 724 | mmu_page_header_cache, 4); |
e2dec939 AK |
725 | out: |
726 | return r; | |
714b93da AK |
727 | } |
728 | ||
729 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
730 | { | |
53c07b18 XG |
731 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
732 | pte_list_desc_cache); | |
ad312c7c | 733 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
734 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
735 | mmu_page_header_cache); | |
714b93da AK |
736 | } |
737 | ||
80feb89a | 738 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
739 | { |
740 | void *p; | |
741 | ||
742 | BUG_ON(!mc->nobjs); | |
743 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
744 | return p; |
745 | } | |
746 | ||
53c07b18 | 747 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 748 | { |
80feb89a | 749 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
750 | } |
751 | ||
53c07b18 | 752 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 753 | { |
53c07b18 | 754 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
755 | } |
756 | ||
2032a93d LJ |
757 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
758 | { | |
759 | if (!sp->role.direct) | |
760 | return sp->gfns[index]; | |
761 | ||
762 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
763 | } | |
764 | ||
765 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
766 | { | |
767 | if (sp->role.direct) | |
768 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
769 | else | |
770 | sp->gfns[index] = gfn; | |
771 | } | |
772 | ||
05da4558 | 773 | /* |
d4dbf470 TY |
774 | * Return the pointer to the large page information for a given gfn, |
775 | * handling slots that are not large page aligned. | |
05da4558 | 776 | */ |
d4dbf470 TY |
777 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
778 | struct kvm_memory_slot *slot, | |
779 | int level) | |
05da4558 MT |
780 | { |
781 | unsigned long idx; | |
782 | ||
fb03cb6f | 783 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 784 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
785 | } |
786 | ||
547ffaed XG |
787 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
788 | gfn_t gfn, int count) | |
789 | { | |
790 | struct kvm_lpage_info *linfo; | |
791 | int i; | |
792 | ||
793 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
794 | linfo = lpage_info_slot(gfn, slot, i); | |
795 | linfo->disallow_lpage += count; | |
796 | WARN_ON(linfo->disallow_lpage < 0); | |
797 | } | |
798 | } | |
799 | ||
800 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
801 | { | |
802 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
803 | } | |
804 | ||
805 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
806 | { | |
807 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
808 | } | |
809 | ||
3ed1a478 | 810 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 811 | { |
699023e2 | 812 | struct kvm_memslots *slots; |
d25797b2 | 813 | struct kvm_memory_slot *slot; |
3ed1a478 | 814 | gfn_t gfn; |
05da4558 | 815 | |
56ca57f9 | 816 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 817 | gfn = sp->gfn; |
699023e2 PB |
818 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
819 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
820 | |
821 | /* the non-leaf shadow pages are keeping readonly. */ | |
822 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
823 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
824 | KVM_PAGE_TRACK_WRITE); | |
825 | ||
547ffaed | 826 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
827 | } |
828 | ||
3ed1a478 | 829 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 830 | { |
699023e2 | 831 | struct kvm_memslots *slots; |
d25797b2 | 832 | struct kvm_memory_slot *slot; |
3ed1a478 | 833 | gfn_t gfn; |
05da4558 | 834 | |
56ca57f9 | 835 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 836 | gfn = sp->gfn; |
699023e2 PB |
837 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
838 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
839 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
840 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
841 | KVM_PAGE_TRACK_WRITE); | |
842 | ||
547ffaed | 843 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
844 | } |
845 | ||
92f94f1e XG |
846 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
847 | struct kvm_memory_slot *slot) | |
05da4558 | 848 | { |
d4dbf470 | 849 | struct kvm_lpage_info *linfo; |
05da4558 MT |
850 | |
851 | if (slot) { | |
d4dbf470 | 852 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 853 | return !!linfo->disallow_lpage; |
05da4558 MT |
854 | } |
855 | ||
92f94f1e | 856 | return true; |
05da4558 MT |
857 | } |
858 | ||
92f94f1e XG |
859 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
860 | int level) | |
5225fdf8 TY |
861 | { |
862 | struct kvm_memory_slot *slot; | |
863 | ||
864 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 865 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
866 | } |
867 | ||
d25797b2 | 868 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 869 | { |
8f0b1ab6 | 870 | unsigned long page_size; |
d25797b2 | 871 | int i, ret = 0; |
05da4558 | 872 | |
8f0b1ab6 | 873 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 874 | |
8a3d08f1 | 875 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
876 | if (page_size >= KVM_HPAGE_SIZE(i)) |
877 | ret = i; | |
878 | else | |
879 | break; | |
880 | } | |
881 | ||
4c2155ce | 882 | return ret; |
05da4558 MT |
883 | } |
884 | ||
d8aacf5d TY |
885 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
886 | bool no_dirty_log) | |
887 | { | |
888 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
889 | return false; | |
890 | if (no_dirty_log && slot->dirty_bitmap) | |
891 | return false; | |
892 | ||
893 | return true; | |
894 | } | |
895 | ||
5d163b1c XG |
896 | static struct kvm_memory_slot * |
897 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
898 | bool no_dirty_log) | |
05da4558 MT |
899 | { |
900 | struct kvm_memory_slot *slot; | |
5d163b1c | 901 | |
54bf36aa | 902 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 903 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
904 | slot = NULL; |
905 | ||
906 | return slot; | |
907 | } | |
908 | ||
fd136902 TY |
909 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
910 | bool *force_pt_level) | |
936a5fe6 AA |
911 | { |
912 | int host_level, level, max_level; | |
d8aacf5d TY |
913 | struct kvm_memory_slot *slot; |
914 | ||
8c85ac1c TY |
915 | if (unlikely(*force_pt_level)) |
916 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 917 | |
8c85ac1c TY |
918 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
919 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
920 | if (unlikely(*force_pt_level)) |
921 | return PT_PAGE_TABLE_LEVEL; | |
922 | ||
d25797b2 JR |
923 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
924 | ||
925 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
926 | return host_level; | |
927 | ||
55dd98c3 | 928 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
929 | |
930 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 931 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 932 | break; |
d25797b2 JR |
933 | |
934 | return level - 1; | |
05da4558 MT |
935 | } |
936 | ||
290fc38d | 937 | /* |
018aabb5 | 938 | * About rmap_head encoding: |
cd4a4e53 | 939 | * |
018aabb5 TY |
940 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
941 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 942 | * pte_list_desc containing more mappings. |
018aabb5 TY |
943 | */ |
944 | ||
945 | /* | |
946 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 947 | */ |
53c07b18 | 948 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 949 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 950 | { |
53c07b18 | 951 | struct pte_list_desc *desc; |
53a27b39 | 952 | int i, count = 0; |
cd4a4e53 | 953 | |
018aabb5 | 954 | if (!rmap_head->val) { |
53c07b18 | 955 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
956 | rmap_head->val = (unsigned long)spte; |
957 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
958 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
959 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 960 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 961 | desc->sptes[1] = spte; |
018aabb5 | 962 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 963 | ++count; |
cd4a4e53 | 964 | } else { |
53c07b18 | 965 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 966 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 967 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 968 | desc = desc->more; |
53c07b18 | 969 | count += PTE_LIST_EXT; |
53a27b39 | 970 | } |
53c07b18 XG |
971 | if (desc->sptes[PTE_LIST_EXT-1]) { |
972 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
973 | desc = desc->more; |
974 | } | |
d555c333 | 975 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 976 | ++count; |
d555c333 | 977 | desc->sptes[i] = spte; |
cd4a4e53 | 978 | } |
53a27b39 | 979 | return count; |
cd4a4e53 AK |
980 | } |
981 | ||
53c07b18 | 982 | static void |
018aabb5 TY |
983 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
984 | struct pte_list_desc *desc, int i, | |
985 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
986 | { |
987 | int j; | |
988 | ||
53c07b18 | 989 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 990 | ; |
d555c333 AK |
991 | desc->sptes[i] = desc->sptes[j]; |
992 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
993 | if (j != 0) |
994 | return; | |
995 | if (!prev_desc && !desc->more) | |
018aabb5 | 996 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
997 | else |
998 | if (prev_desc) | |
999 | prev_desc->more = desc->more; | |
1000 | else | |
018aabb5 | 1001 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1002 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1003 | } |
1004 | ||
018aabb5 | 1005 | static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1006 | { |
53c07b18 XG |
1007 | struct pte_list_desc *desc; |
1008 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1009 | int i; |
1010 | ||
018aabb5 | 1011 | if (!rmap_head->val) { |
53c07b18 | 1012 | printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte); |
cd4a4e53 | 1013 | BUG(); |
018aabb5 | 1014 | } else if (!(rmap_head->val & 1)) { |
53c07b18 | 1015 | rmap_printk("pte_list_remove: %p 1->0\n", spte); |
018aabb5 | 1016 | if ((u64 *)rmap_head->val != spte) { |
53c07b18 | 1017 | printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte); |
cd4a4e53 AK |
1018 | BUG(); |
1019 | } | |
018aabb5 | 1020 | rmap_head->val = 0; |
cd4a4e53 | 1021 | } else { |
53c07b18 | 1022 | rmap_printk("pte_list_remove: %p many->many\n", spte); |
018aabb5 | 1023 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1024 | prev_desc = NULL; |
1025 | while (desc) { | |
018aabb5 | 1026 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1027 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1028 | pte_list_desc_remove_entry(rmap_head, |
1029 | desc, i, prev_desc); | |
cd4a4e53 AK |
1030 | return; |
1031 | } | |
018aabb5 | 1032 | } |
cd4a4e53 AK |
1033 | prev_desc = desc; |
1034 | desc = desc->more; | |
1035 | } | |
53c07b18 | 1036 | pr_err("pte_list_remove: %p many->many\n", spte); |
cd4a4e53 AK |
1037 | BUG(); |
1038 | } | |
1039 | } | |
1040 | ||
018aabb5 TY |
1041 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1042 | struct kvm_memory_slot *slot) | |
53c07b18 | 1043 | { |
77d11309 | 1044 | unsigned long idx; |
53c07b18 | 1045 | |
77d11309 | 1046 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1047 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1048 | } |
1049 | ||
018aabb5 TY |
1050 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1051 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1052 | { |
699023e2 | 1053 | struct kvm_memslots *slots; |
9b9b1492 TY |
1054 | struct kvm_memory_slot *slot; |
1055 | ||
699023e2 PB |
1056 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1057 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1058 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1059 | } |
1060 | ||
f759e2b4 XG |
1061 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1062 | { | |
1063 | struct kvm_mmu_memory_cache *cache; | |
1064 | ||
1065 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1066 | return mmu_memory_cache_free_objects(cache); | |
1067 | } | |
1068 | ||
53c07b18 XG |
1069 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1070 | { | |
1071 | struct kvm_mmu_page *sp; | |
018aabb5 | 1072 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1073 | |
53c07b18 XG |
1074 | sp = page_header(__pa(spte)); |
1075 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1076 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1077 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1078 | } |
1079 | ||
53c07b18 XG |
1080 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1081 | { | |
1082 | struct kvm_mmu_page *sp; | |
1083 | gfn_t gfn; | |
018aabb5 | 1084 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1085 | |
1086 | sp = page_header(__pa(spte)); | |
1087 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 TY |
1088 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
1089 | pte_list_remove(spte, rmap_head); | |
53c07b18 XG |
1090 | } |
1091 | ||
1e3f42f0 TY |
1092 | /* |
1093 | * Used by the following functions to iterate through the sptes linked by a | |
1094 | * rmap. All fields are private and not assumed to be used outside. | |
1095 | */ | |
1096 | struct rmap_iterator { | |
1097 | /* private fields */ | |
1098 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1099 | int pos; /* index of the sptep */ | |
1100 | }; | |
1101 | ||
1102 | /* | |
1103 | * Iteration must be started by this function. This should also be used after | |
1104 | * removing/dropping sptes from the rmap link because in such cases the | |
1105 | * information in the itererator may not be valid. | |
1106 | * | |
1107 | * Returns sptep if found, NULL otherwise. | |
1108 | */ | |
018aabb5 TY |
1109 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1110 | struct rmap_iterator *iter) | |
1e3f42f0 | 1111 | { |
77fbbbd2 TY |
1112 | u64 *sptep; |
1113 | ||
018aabb5 | 1114 | if (!rmap_head->val) |
1e3f42f0 TY |
1115 | return NULL; |
1116 | ||
018aabb5 | 1117 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1118 | iter->desc = NULL; |
77fbbbd2 TY |
1119 | sptep = (u64 *)rmap_head->val; |
1120 | goto out; | |
1e3f42f0 TY |
1121 | } |
1122 | ||
018aabb5 | 1123 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1124 | iter->pos = 0; |
77fbbbd2 TY |
1125 | sptep = iter->desc->sptes[iter->pos]; |
1126 | out: | |
1127 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1128 | return sptep; | |
1e3f42f0 TY |
1129 | } |
1130 | ||
1131 | /* | |
1132 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1133 | * | |
1134 | * Returns sptep if found, NULL otherwise. | |
1135 | */ | |
1136 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1137 | { | |
77fbbbd2 TY |
1138 | u64 *sptep; |
1139 | ||
1e3f42f0 TY |
1140 | if (iter->desc) { |
1141 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1142 | ++iter->pos; |
1143 | sptep = iter->desc->sptes[iter->pos]; | |
1144 | if (sptep) | |
77fbbbd2 | 1145 | goto out; |
1e3f42f0 TY |
1146 | } |
1147 | ||
1148 | iter->desc = iter->desc->more; | |
1149 | ||
1150 | if (iter->desc) { | |
1151 | iter->pos = 0; | |
1152 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1153 | sptep = iter->desc->sptes[iter->pos]; |
1154 | goto out; | |
1e3f42f0 TY |
1155 | } |
1156 | } | |
1157 | ||
1158 | return NULL; | |
77fbbbd2 TY |
1159 | out: |
1160 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1161 | return sptep; | |
1e3f42f0 TY |
1162 | } |
1163 | ||
018aabb5 TY |
1164 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1165 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1166 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1167 | |
c3707958 | 1168 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1169 | { |
1df9f2dc | 1170 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1171 | rmap_remove(kvm, sptep); |
be38d276 AK |
1172 | } |
1173 | ||
8e22f955 XG |
1174 | |
1175 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1176 | { | |
1177 | if (is_large_pte(*sptep)) { | |
1178 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1179 | PT_PAGE_TABLE_LEVEL); | |
1180 | drop_spte(kvm, sptep); | |
1181 | --kvm->stat.lpages; | |
1182 | return true; | |
1183 | } | |
1184 | ||
1185 | return false; | |
1186 | } | |
1187 | ||
1188 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1189 | { | |
1190 | if (__drop_large_spte(vcpu->kvm, sptep)) | |
1191 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1192 | } | |
1193 | ||
1194 | /* | |
49fde340 | 1195 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1196 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1197 | * |
b4619660 | 1198 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1199 | * protection: |
1200 | * - for dirty logging, the spte can be set to writable at anytime if | |
1201 | * its dirty bitmap is properly set. | |
1202 | * - for spte protection, the spte can be writable only after unsync-ing | |
1203 | * shadow page. | |
8e22f955 | 1204 | * |
c126d94f | 1205 | * Return true if tlb need be flushed. |
8e22f955 | 1206 | */ |
c126d94f | 1207 | static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1208 | { |
1209 | u64 spte = *sptep; | |
1210 | ||
49fde340 XG |
1211 | if (!is_writable_pte(spte) && |
1212 | !(pt_protect && spte_is_locklessly_modifiable(spte))) | |
d13bc5b5 XG |
1213 | return false; |
1214 | ||
1215 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1216 | ||
49fde340 XG |
1217 | if (pt_protect) |
1218 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1219 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1220 | |
c126d94f | 1221 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1222 | } |
1223 | ||
018aabb5 TY |
1224 | static bool __rmap_write_protect(struct kvm *kvm, |
1225 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1226 | bool pt_protect) |
98348e95 | 1227 | { |
1e3f42f0 TY |
1228 | u64 *sptep; |
1229 | struct rmap_iterator iter; | |
d13bc5b5 | 1230 | bool flush = false; |
374cbac0 | 1231 | |
018aabb5 | 1232 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c126d94f | 1233 | flush |= spte_write_protect(kvm, sptep, pt_protect); |
855149aa | 1234 | |
d13bc5b5 | 1235 | return flush; |
a0ed4607 TY |
1236 | } |
1237 | ||
f4b4b180 KH |
1238 | static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep) |
1239 | { | |
1240 | u64 spte = *sptep; | |
1241 | ||
1242 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1243 | ||
1244 | spte &= ~shadow_dirty_mask; | |
1245 | ||
1246 | return mmu_spte_update(sptep, spte); | |
1247 | } | |
1248 | ||
018aabb5 | 1249 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1250 | { |
1251 | u64 *sptep; | |
1252 | struct rmap_iterator iter; | |
1253 | bool flush = false; | |
1254 | ||
018aabb5 | 1255 | for_each_rmap_spte(rmap_head, &iter, sptep) |
f4b4b180 | 1256 | flush |= spte_clear_dirty(kvm, sptep); |
f4b4b180 KH |
1257 | |
1258 | return flush; | |
1259 | } | |
1260 | ||
1261 | static bool spte_set_dirty(struct kvm *kvm, u64 *sptep) | |
1262 | { | |
1263 | u64 spte = *sptep; | |
1264 | ||
1265 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1266 | ||
1267 | spte |= shadow_dirty_mask; | |
1268 | ||
1269 | return mmu_spte_update(sptep, spte); | |
1270 | } | |
1271 | ||
018aabb5 | 1272 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1273 | { |
1274 | u64 *sptep; | |
1275 | struct rmap_iterator iter; | |
1276 | bool flush = false; | |
1277 | ||
018aabb5 | 1278 | for_each_rmap_spte(rmap_head, &iter, sptep) |
f4b4b180 | 1279 | flush |= spte_set_dirty(kvm, sptep); |
f4b4b180 KH |
1280 | |
1281 | return flush; | |
1282 | } | |
1283 | ||
5dc99b23 | 1284 | /** |
3b0f1d01 | 1285 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1286 | * @kvm: kvm instance |
1287 | * @slot: slot to protect | |
1288 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1289 | * @mask: indicates which pages we should protect | |
1290 | * | |
1291 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1292 | * logging we do not have any such mappings. | |
1293 | */ | |
3b0f1d01 | 1294 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1295 | struct kvm_memory_slot *slot, |
1296 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1297 | { |
018aabb5 | 1298 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1299 | |
5dc99b23 | 1300 | while (mask) { |
018aabb5 TY |
1301 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1302 | PT_PAGE_TABLE_LEVEL, slot); | |
1303 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1304 | |
5dc99b23 TY |
1305 | /* clear the first set bit */ |
1306 | mask &= mask - 1; | |
1307 | } | |
374cbac0 AK |
1308 | } |
1309 | ||
f4b4b180 KH |
1310 | /** |
1311 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages | |
1312 | * @kvm: kvm instance | |
1313 | * @slot: slot to clear D-bit | |
1314 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1315 | * @mask: indicates which pages we should clear D-bit | |
1316 | * | |
1317 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1318 | */ | |
1319 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1320 | struct kvm_memory_slot *slot, | |
1321 | gfn_t gfn_offset, unsigned long mask) | |
1322 | { | |
018aabb5 | 1323 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1324 | |
1325 | while (mask) { | |
018aabb5 TY |
1326 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1327 | PT_PAGE_TABLE_LEVEL, slot); | |
1328 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1329 | |
1330 | /* clear the first set bit */ | |
1331 | mask &= mask - 1; | |
1332 | } | |
1333 | } | |
1334 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1335 | ||
3b0f1d01 KH |
1336 | /** |
1337 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1338 | * PT level pages. | |
1339 | * | |
1340 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1341 | * enable dirty logging for them. | |
1342 | * | |
1343 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1344 | * logging we do not have any such mappings. | |
1345 | */ | |
1346 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1347 | struct kvm_memory_slot *slot, | |
1348 | gfn_t gfn_offset, unsigned long mask) | |
1349 | { | |
88178fd4 KH |
1350 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1351 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1352 | mask); | |
1353 | else | |
1354 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1355 | } |
1356 | ||
aeecee2e XG |
1357 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1358 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1359 | { |
018aabb5 | 1360 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1361 | int i; |
2f84569f | 1362 | bool write_protected = false; |
95d4c16c | 1363 | |
8a3d08f1 | 1364 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1365 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1366 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1367 | } |
1368 | ||
1369 | return write_protected; | |
95d4c16c TY |
1370 | } |
1371 | ||
aeecee2e XG |
1372 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1373 | { | |
1374 | struct kvm_memory_slot *slot; | |
1375 | ||
1376 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1377 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1378 | } | |
1379 | ||
018aabb5 | 1380 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1381 | { |
1e3f42f0 TY |
1382 | u64 *sptep; |
1383 | struct rmap_iterator iter; | |
6a49f85c | 1384 | bool flush = false; |
e930bffe | 1385 | |
018aabb5 | 1386 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1387 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 TY |
1388 | |
1389 | drop_spte(kvm, sptep); | |
6a49f85c | 1390 | flush = true; |
e930bffe | 1391 | } |
1e3f42f0 | 1392 | |
6a49f85c XG |
1393 | return flush; |
1394 | } | |
1395 | ||
018aabb5 | 1396 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1397 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1398 | unsigned long data) | |
1399 | { | |
018aabb5 | 1400 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1401 | } |
1402 | ||
018aabb5 | 1403 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1404 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1405 | unsigned long data) | |
3da0dd43 | 1406 | { |
1e3f42f0 TY |
1407 | u64 *sptep; |
1408 | struct rmap_iterator iter; | |
3da0dd43 | 1409 | int need_flush = 0; |
1e3f42f0 | 1410 | u64 new_spte; |
3da0dd43 | 1411 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1412 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1413 | |
1414 | WARN_ON(pte_huge(*ptep)); | |
1415 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1416 | |
0d536790 | 1417 | restart: |
018aabb5 | 1418 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 ALC |
1419 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
1420 | sptep, *sptep, gfn, level); | |
1e3f42f0 | 1421 | |
3da0dd43 | 1422 | need_flush = 1; |
1e3f42f0 | 1423 | |
3da0dd43 | 1424 | if (pte_write(*ptep)) { |
1e3f42f0 | 1425 | drop_spte(kvm, sptep); |
0d536790 | 1426 | goto restart; |
3da0dd43 | 1427 | } else { |
1e3f42f0 | 1428 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1429 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1430 | ||
1431 | new_spte &= ~PT_WRITABLE_MASK; | |
1432 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
b79b93f9 | 1433 | new_spte &= ~shadow_accessed_mask; |
1e3f42f0 TY |
1434 | |
1435 | mmu_spte_clear_track_bits(sptep); | |
1436 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1437 | } |
1438 | } | |
1e3f42f0 | 1439 | |
3da0dd43 IE |
1440 | if (need_flush) |
1441 | kvm_flush_remote_tlbs(kvm); | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | ||
6ce1f4e2 XG |
1446 | struct slot_rmap_walk_iterator { |
1447 | /* input fields. */ | |
1448 | struct kvm_memory_slot *slot; | |
1449 | gfn_t start_gfn; | |
1450 | gfn_t end_gfn; | |
1451 | int start_level; | |
1452 | int end_level; | |
1453 | ||
1454 | /* output fields. */ | |
1455 | gfn_t gfn; | |
018aabb5 | 1456 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1457 | int level; |
1458 | ||
1459 | /* private field. */ | |
018aabb5 | 1460 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1461 | }; |
1462 | ||
1463 | static void | |
1464 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1465 | { | |
1466 | iterator->level = level; | |
1467 | iterator->gfn = iterator->start_gfn; | |
1468 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1469 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1470 | iterator->slot); | |
1471 | } | |
1472 | ||
1473 | static void | |
1474 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1475 | struct kvm_memory_slot *slot, int start_level, | |
1476 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1477 | { | |
1478 | iterator->slot = slot; | |
1479 | iterator->start_level = start_level; | |
1480 | iterator->end_level = end_level; | |
1481 | iterator->start_gfn = start_gfn; | |
1482 | iterator->end_gfn = end_gfn; | |
1483 | ||
1484 | rmap_walk_init_level(iterator, iterator->start_level); | |
1485 | } | |
1486 | ||
1487 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1488 | { | |
1489 | return !!iterator->rmap; | |
1490 | } | |
1491 | ||
1492 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1493 | { | |
1494 | if (++iterator->rmap <= iterator->end_rmap) { | |
1495 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1496 | return; | |
1497 | } | |
1498 | ||
1499 | if (++iterator->level > iterator->end_level) { | |
1500 | iterator->rmap = NULL; | |
1501 | return; | |
1502 | } | |
1503 | ||
1504 | rmap_walk_init_level(iterator, iterator->level); | |
1505 | } | |
1506 | ||
1507 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1508 | _start_gfn, _end_gfn, _iter_) \ | |
1509 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1510 | _end_level_, _start_gfn, _end_gfn); \ | |
1511 | slot_rmap_walk_okay(_iter_); \ | |
1512 | slot_rmap_walk_next(_iter_)) | |
1513 | ||
84504ef3 TY |
1514 | static int kvm_handle_hva_range(struct kvm *kvm, |
1515 | unsigned long start, | |
1516 | unsigned long end, | |
1517 | unsigned long data, | |
1518 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1519 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1520 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1521 | gfn_t gfn, |
1522 | int level, | |
84504ef3 | 1523 | unsigned long data)) |
e930bffe | 1524 | { |
bc6678a3 | 1525 | struct kvm_memslots *slots; |
be6ba0f0 | 1526 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1527 | struct slot_rmap_walk_iterator iterator; |
1528 | int ret = 0; | |
9da0e4d5 | 1529 | int i; |
bc6678a3 | 1530 | |
9da0e4d5 PB |
1531 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1532 | slots = __kvm_memslots(kvm, i); | |
1533 | kvm_for_each_memslot(memslot, slots) { | |
1534 | unsigned long hva_start, hva_end; | |
1535 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1536 | |
9da0e4d5 PB |
1537 | hva_start = max(start, memslot->userspace_addr); |
1538 | hva_end = min(end, memslot->userspace_addr + | |
1539 | (memslot->npages << PAGE_SHIFT)); | |
1540 | if (hva_start >= hva_end) | |
1541 | continue; | |
1542 | /* | |
1543 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1544 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1545 | */ | |
1546 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1547 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1548 | ||
1549 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1550 | PT_MAX_HUGEPAGE_LEVEL, | |
1551 | gfn_start, gfn_end - 1, | |
1552 | &iterator) | |
1553 | ret |= handler(kvm, iterator.rmap, memslot, | |
1554 | iterator.gfn, iterator.level, data); | |
1555 | } | |
e930bffe AA |
1556 | } |
1557 | ||
f395302e | 1558 | return ret; |
e930bffe AA |
1559 | } |
1560 | ||
84504ef3 TY |
1561 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1562 | unsigned long data, | |
018aabb5 TY |
1563 | int (*handler)(struct kvm *kvm, |
1564 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1565 | struct kvm_memory_slot *slot, |
8a9522d2 | 1566 | gfn_t gfn, int level, |
84504ef3 TY |
1567 | unsigned long data)) |
1568 | { | |
1569 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1570 | } |
1571 | ||
1572 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) | |
1573 | { | |
3da0dd43 IE |
1574 | return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp); |
1575 | } | |
1576 | ||
b3ae2096 TY |
1577 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1578 | { | |
1579 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1580 | } | |
1581 | ||
3da0dd43 IE |
1582 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
1583 | { | |
8a8365c5 | 1584 | kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1585 | } |
1586 | ||
018aabb5 | 1587 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1588 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1589 | unsigned long data) | |
e930bffe | 1590 | { |
1e3f42f0 | 1591 | u64 *sptep; |
79f702a6 | 1592 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1593 | int young = 0; |
1594 | ||
57128468 | 1595 | BUG_ON(!shadow_accessed_mask); |
534e38b4 | 1596 | |
018aabb5 | 1597 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3f6d8c8a | 1598 | if (*sptep & shadow_accessed_mask) { |
e930bffe | 1599 | young = 1; |
3f6d8c8a XH |
1600 | clear_bit((ffs(shadow_accessed_mask) - 1), |
1601 | (unsigned long *)sptep); | |
e930bffe | 1602 | } |
018aabb5 | 1603 | } |
0d536790 | 1604 | |
8a9522d2 | 1605 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1606 | return young; |
1607 | } | |
1608 | ||
018aabb5 | 1609 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1610 | struct kvm_memory_slot *slot, gfn_t gfn, |
1611 | int level, unsigned long data) | |
8ee53820 | 1612 | { |
1e3f42f0 TY |
1613 | u64 *sptep; |
1614 | struct rmap_iterator iter; | |
8ee53820 AA |
1615 | int young = 0; |
1616 | ||
1617 | /* | |
1618 | * If there's no access bit in the secondary pte set by the | |
1619 | * hardware it's up to gup-fast/gup to set the access bit in | |
1620 | * the primary pte or in the page structure. | |
1621 | */ | |
1622 | if (!shadow_accessed_mask) | |
1623 | goto out; | |
1624 | ||
018aabb5 | 1625 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3f6d8c8a | 1626 | if (*sptep & shadow_accessed_mask) { |
8ee53820 AA |
1627 | young = 1; |
1628 | break; | |
1629 | } | |
018aabb5 | 1630 | } |
8ee53820 AA |
1631 | out: |
1632 | return young; | |
1633 | } | |
1634 | ||
53a27b39 MT |
1635 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1636 | ||
852e3c19 | 1637 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1638 | { |
018aabb5 | 1639 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1640 | struct kvm_mmu_page *sp; |
1641 | ||
1642 | sp = page_header(__pa(spte)); | |
53a27b39 | 1643 | |
018aabb5 | 1644 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1645 | |
018aabb5 | 1646 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
53a27b39 MT |
1647 | kvm_flush_remote_tlbs(vcpu->kvm); |
1648 | } | |
1649 | ||
57128468 | 1650 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1651 | { |
57128468 ALC |
1652 | /* |
1653 | * In case of absence of EPT Access and Dirty Bits supports, | |
1654 | * emulate the accessed bit for EPT, by checking if this page has | |
1655 | * an EPT mapping, and clearing it if it does. On the next access, | |
1656 | * a new EPT mapping will be established. | |
1657 | * This has some overhead, but not as much as the cost of swapping | |
1658 | * out actively used pages or breaking up actively used hugepages. | |
1659 | */ | |
1660 | if (!shadow_accessed_mask) { | |
1661 | /* | |
1662 | * We are holding the kvm->mmu_lock, and we are blowing up | |
1663 | * shadow PTEs. MMU notifier consumers need to be kept at bay. | |
1664 | * This is correct as long as we don't decouple the mmu_lock | |
1665 | * protected regions (like invalidate_range_start|end does). | |
1666 | */ | |
1667 | kvm->mmu_notifier_seq++; | |
1668 | return kvm_handle_hva_range(kvm, start, end, 0, | |
1669 | kvm_unmap_rmapp); | |
1670 | } | |
1671 | ||
1672 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); | |
e930bffe AA |
1673 | } |
1674 | ||
8ee53820 AA |
1675 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1676 | { | |
1677 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1678 | } | |
1679 | ||
d6c69ee9 | 1680 | #ifdef MMU_DEBUG |
47ad8e68 | 1681 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1682 | { |
139bdb2d AK |
1683 | u64 *pos; |
1684 | u64 *end; | |
1685 | ||
47ad8e68 | 1686 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1687 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1688 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1689 | pos, *pos); |
6aa8b732 | 1690 | return 0; |
139bdb2d | 1691 | } |
6aa8b732 AK |
1692 | return 1; |
1693 | } | |
d6c69ee9 | 1694 | #endif |
6aa8b732 | 1695 | |
45221ab6 DH |
1696 | /* |
1697 | * This value is the sum of all of the kvm instances's | |
1698 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
1699 | * aggregate version in order to make the slab shrinker | |
1700 | * faster | |
1701 | */ | |
1702 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
1703 | { | |
1704 | kvm->arch.n_used_mmu_pages += nr; | |
1705 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
1706 | } | |
1707 | ||
834be0d8 | 1708 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 1709 | { |
fa4a2c08 | 1710 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 1711 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
1712 | list_del(&sp->link); |
1713 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
1714 | if (!sp->role.direct) |
1715 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 1716 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
1717 | } |
1718 | ||
cea0f0e7 AK |
1719 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
1720 | { | |
1ae0a13d | 1721 | return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1); |
cea0f0e7 AK |
1722 | } |
1723 | ||
714b93da | 1724 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 1725 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 1726 | { |
cea0f0e7 AK |
1727 | if (!parent_pte) |
1728 | return; | |
cea0f0e7 | 1729 | |
67052b35 | 1730 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1731 | } |
1732 | ||
4db35314 | 1733 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
1734 | u64 *parent_pte) |
1735 | { | |
67052b35 | 1736 | pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
1737 | } |
1738 | ||
bcdd9a93 XG |
1739 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
1740 | u64 *parent_pte) | |
1741 | { | |
1742 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 1743 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
1744 | } |
1745 | ||
47005792 | 1746 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 1747 | { |
67052b35 | 1748 | struct kvm_mmu_page *sp; |
7ddca7e4 | 1749 | |
80feb89a TY |
1750 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
1751 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 1752 | if (!direct) |
80feb89a | 1753 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 1754 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
1755 | |
1756 | /* | |
1757 | * The active_mmu_pages list is the FIFO list, do not move the | |
1758 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
1759 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
1760 | */ | |
67052b35 | 1761 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
1762 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
1763 | return sp; | |
ad8cfbe3 MT |
1764 | } |
1765 | ||
67052b35 | 1766 | static void mark_unsync(u64 *spte); |
1047df1f | 1767 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 1768 | { |
74c4e63a TY |
1769 | u64 *sptep; |
1770 | struct rmap_iterator iter; | |
1771 | ||
1772 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
1773 | mark_unsync(sptep); | |
1774 | } | |
0074ff63 MT |
1775 | } |
1776 | ||
67052b35 | 1777 | static void mark_unsync(u64 *spte) |
0074ff63 | 1778 | { |
67052b35 | 1779 | struct kvm_mmu_page *sp; |
1047df1f | 1780 | unsigned int index; |
0074ff63 | 1781 | |
67052b35 | 1782 | sp = page_header(__pa(spte)); |
1047df1f XG |
1783 | index = spte - sp->spt; |
1784 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 1785 | return; |
1047df1f | 1786 | if (sp->unsync_children++) |
0074ff63 | 1787 | return; |
1047df1f | 1788 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
1789 | } |
1790 | ||
e8bc217a | 1791 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 1792 | struct kvm_mmu_page *sp) |
e8bc217a | 1793 | { |
1f50f1b3 | 1794 | return 0; |
e8bc217a MT |
1795 | } |
1796 | ||
a7052897 MT |
1797 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
1798 | { | |
1799 | } | |
1800 | ||
0f53b5b1 XG |
1801 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
1802 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 1803 | const void *pte) |
0f53b5b1 XG |
1804 | { |
1805 | WARN_ON(1); | |
1806 | } | |
1807 | ||
60c8aec6 MT |
1808 | #define KVM_PAGE_ARRAY_NR 16 |
1809 | ||
1810 | struct kvm_mmu_pages { | |
1811 | struct mmu_page_and_offset { | |
1812 | struct kvm_mmu_page *sp; | |
1813 | unsigned int idx; | |
1814 | } page[KVM_PAGE_ARRAY_NR]; | |
1815 | unsigned int nr; | |
1816 | }; | |
1817 | ||
cded19f3 HE |
1818 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
1819 | int idx) | |
4731d4c7 | 1820 | { |
60c8aec6 | 1821 | int i; |
4731d4c7 | 1822 | |
60c8aec6 MT |
1823 | if (sp->unsync) |
1824 | for (i=0; i < pvec->nr; i++) | |
1825 | if (pvec->page[i].sp == sp) | |
1826 | return 0; | |
1827 | ||
1828 | pvec->page[pvec->nr].sp = sp; | |
1829 | pvec->page[pvec->nr].idx = idx; | |
1830 | pvec->nr++; | |
1831 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
1832 | } | |
1833 | ||
fd951457 TY |
1834 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
1835 | { | |
1836 | --sp->unsync_children; | |
1837 | WARN_ON((int)sp->unsync_children < 0); | |
1838 | __clear_bit(idx, sp->unsync_child_bitmap); | |
1839 | } | |
1840 | ||
60c8aec6 MT |
1841 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
1842 | struct kvm_mmu_pages *pvec) | |
1843 | { | |
1844 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 1845 | |
37178b8b | 1846 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 1847 | struct kvm_mmu_page *child; |
4731d4c7 MT |
1848 | u64 ent = sp->spt[i]; |
1849 | ||
fd951457 TY |
1850 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
1851 | clear_unsync_child_bit(sp, i); | |
1852 | continue; | |
1853 | } | |
7a8f1a74 XG |
1854 | |
1855 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
1856 | ||
1857 | if (child->unsync_children) { | |
1858 | if (mmu_pages_add(pvec, child, i)) | |
1859 | return -ENOSPC; | |
1860 | ||
1861 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
1862 | if (!ret) { |
1863 | clear_unsync_child_bit(sp, i); | |
1864 | continue; | |
1865 | } else if (ret > 0) { | |
7a8f1a74 | 1866 | nr_unsync_leaf += ret; |
fd951457 | 1867 | } else |
7a8f1a74 XG |
1868 | return ret; |
1869 | } else if (child->unsync) { | |
1870 | nr_unsync_leaf++; | |
1871 | if (mmu_pages_add(pvec, child, i)) | |
1872 | return -ENOSPC; | |
1873 | } else | |
fd951457 | 1874 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
1875 | } |
1876 | ||
60c8aec6 MT |
1877 | return nr_unsync_leaf; |
1878 | } | |
1879 | ||
e23d3fef XG |
1880 | #define INVALID_INDEX (-1) |
1881 | ||
60c8aec6 MT |
1882 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
1883 | struct kvm_mmu_pages *pvec) | |
1884 | { | |
0a47cd85 | 1885 | pvec->nr = 0; |
60c8aec6 MT |
1886 | if (!sp->unsync_children) |
1887 | return 0; | |
1888 | ||
e23d3fef | 1889 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 1890 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
1891 | } |
1892 | ||
4731d4c7 MT |
1893 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
1894 | { | |
1895 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 1896 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
1897 | sp->unsync = 0; |
1898 | --kvm->stat.mmu_unsync; | |
1899 | } | |
1900 | ||
7775834a XG |
1901 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
1902 | struct list_head *invalid_list); | |
1903 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
1904 | struct list_head *invalid_list); | |
4731d4c7 | 1905 | |
f34d251d XG |
1906 | /* |
1907 | * NOTE: we should pay more attention on the zapped-obsolete page | |
1908 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
1909 | * since it has been deleted from active_mmu_pages but still can be found | |
1910 | * at hast list. | |
1911 | * | |
1912 | * for_each_gfn_indirect_valid_sp has skipped that kind of page and | |
1913 | * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped | |
1914 | * all the obsolete pages. | |
1915 | */ | |
1044b030 TY |
1916 | #define for_each_gfn_sp(_kvm, _sp, _gfn) \ |
1917 | hlist_for_each_entry(_sp, \ | |
1918 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
1919 | if ((_sp)->gfn != (_gfn)) {} else | |
1920 | ||
1921 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
1922 | for_each_gfn_sp(_kvm, _sp, _gfn) \ | |
1923 | if ((_sp)->role.direct || (_sp)->role.invalid) {} else | |
7ae680eb | 1924 | |
f918b443 | 1925 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
1926 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
1927 | struct list_head *invalid_list) | |
4731d4c7 | 1928 | { |
5b7e0102 | 1929 | if (sp->role.cr4_pae != !!is_pae(vcpu)) { |
d98ba053 | 1930 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1931 | return false; |
4731d4c7 MT |
1932 | } |
1933 | ||
1f50f1b3 | 1934 | if (vcpu->arch.mmu.sync_page(vcpu, sp) == 0) { |
d98ba053 | 1935 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 1936 | return false; |
4731d4c7 MT |
1937 | } |
1938 | ||
1f50f1b3 | 1939 | return true; |
4731d4c7 MT |
1940 | } |
1941 | ||
35a70510 PB |
1942 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
1943 | struct list_head *invalid_list, | |
1944 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 1945 | { |
35a70510 PB |
1946 | if (!list_empty(invalid_list)) { |
1947 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
1948 | return; | |
1949 | } | |
d98ba053 | 1950 | |
35a70510 PB |
1951 | if (remote_flush) |
1952 | kvm_flush_remote_tlbs(vcpu->kvm); | |
1953 | else if (local_flush) | |
1954 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
1955 | } |
1956 | ||
e37fa785 XG |
1957 | #ifdef CONFIG_KVM_MMU_AUDIT |
1958 | #include "mmu_audit.c" | |
1959 | #else | |
1960 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
1961 | static void mmu_audit_disable(void) { } | |
1962 | #endif | |
1963 | ||
1f50f1b3 | 1964 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 1965 | struct list_head *invalid_list) |
1d9dc7e0 | 1966 | { |
9a43c5d9 PB |
1967 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
1968 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
1969 | } |
1970 | ||
9f1a122f | 1971 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
1972 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
1973 | struct list_head *invalid_list) | |
9f1a122f | 1974 | { |
9f1a122f | 1975 | struct kvm_mmu_page *s; |
2a74003a | 1976 | bool ret = false; |
9f1a122f | 1977 | |
b67bfe0d | 1978 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 1979 | if (!s->unsync) |
9f1a122f XG |
1980 | continue; |
1981 | ||
1982 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 1983 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
1984 | } |
1985 | ||
2a74003a | 1986 | return ret; |
9f1a122f XG |
1987 | } |
1988 | ||
60c8aec6 | 1989 | struct mmu_page_path { |
0a47cd85 PB |
1990 | struct kvm_mmu_page *parent[PT64_ROOT_LEVEL]; |
1991 | unsigned int idx[PT64_ROOT_LEVEL]; | |
4731d4c7 MT |
1992 | }; |
1993 | ||
60c8aec6 | 1994 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 1995 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
1996 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
1997 | i = mmu_pages_next(&pvec, &parents, i)) | |
1998 | ||
cded19f3 HE |
1999 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2000 | struct mmu_page_path *parents, | |
2001 | int i) | |
60c8aec6 MT |
2002 | { |
2003 | int n; | |
2004 | ||
2005 | for (n = i+1; n < pvec->nr; n++) { | |
2006 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2007 | unsigned idx = pvec->page[n].idx; |
2008 | int level = sp->role.level; | |
60c8aec6 | 2009 | |
0a47cd85 PB |
2010 | parents->idx[level-1] = idx; |
2011 | if (level == PT_PAGE_TABLE_LEVEL) | |
2012 | break; | |
60c8aec6 | 2013 | |
0a47cd85 | 2014 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2015 | } |
2016 | ||
2017 | return n; | |
2018 | } | |
2019 | ||
0a47cd85 PB |
2020 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2021 | struct mmu_page_path *parents) | |
2022 | { | |
2023 | struct kvm_mmu_page *sp; | |
2024 | int level; | |
2025 | ||
2026 | if (pvec->nr == 0) | |
2027 | return 0; | |
2028 | ||
e23d3fef XG |
2029 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2030 | ||
0a47cd85 PB |
2031 | sp = pvec->page[0].sp; |
2032 | level = sp->role.level; | |
2033 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2034 | ||
2035 | parents->parent[level-2] = sp; | |
2036 | ||
2037 | /* Also set up a sentinel. Further entries in pvec are all | |
2038 | * children of sp, so this element is never overwritten. | |
2039 | */ | |
2040 | parents->parent[level-1] = NULL; | |
2041 | return mmu_pages_next(pvec, parents, 0); | |
2042 | } | |
2043 | ||
cded19f3 | 2044 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2045 | { |
60c8aec6 MT |
2046 | struct kvm_mmu_page *sp; |
2047 | unsigned int level = 0; | |
2048 | ||
2049 | do { | |
2050 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2051 | sp = parents->parent[level]; |
2052 | if (!sp) | |
2053 | return; | |
2054 | ||
e23d3fef | 2055 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2056 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2057 | level++; |
0a47cd85 | 2058 | } while (!sp->unsync_children); |
60c8aec6 | 2059 | } |
4731d4c7 | 2060 | |
60c8aec6 MT |
2061 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2062 | struct kvm_mmu_page *parent) | |
2063 | { | |
2064 | int i; | |
2065 | struct kvm_mmu_page *sp; | |
2066 | struct mmu_page_path parents; | |
2067 | struct kvm_mmu_pages pages; | |
d98ba053 | 2068 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2069 | bool flush = false; |
60c8aec6 | 2070 | |
60c8aec6 | 2071 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2072 | bool protected = false; |
b1a36821 MT |
2073 | |
2074 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2075 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2076 | |
50c9e6f3 | 2077 | if (protected) { |
b1a36821 | 2078 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2079 | flush = false; |
2080 | } | |
b1a36821 | 2081 | |
60c8aec6 | 2082 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2083 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2084 | mmu_pages_clear_parents(&parents); |
2085 | } | |
50c9e6f3 PB |
2086 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2087 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2088 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2089 | flush = false; | |
2090 | } | |
60c8aec6 | 2091 | } |
50c9e6f3 PB |
2092 | |
2093 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2094 | } |
2095 | ||
a30f47cb XG |
2096 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2097 | { | |
e5691a81 | 2098 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2099 | } |
2100 | ||
2101 | static void clear_sp_write_flooding_count(u64 *spte) | |
2102 | { | |
2103 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2104 | ||
2105 | __clear_sp_write_flooding_count(sp); | |
2106 | } | |
2107 | ||
5304b8d3 XG |
2108 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2109 | { | |
2110 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2111 | } | |
2112 | ||
cea0f0e7 AK |
2113 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2114 | gfn_t gfn, | |
2115 | gva_t gaddr, | |
2116 | unsigned level, | |
f6e2c02b | 2117 | int direct, |
bb11c6c9 | 2118 | unsigned access) |
cea0f0e7 AK |
2119 | { |
2120 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2121 | unsigned quadrant; |
9f1a122f | 2122 | struct kvm_mmu_page *sp; |
9f1a122f | 2123 | bool need_sync = false; |
2a74003a PB |
2124 | bool flush = false; |
2125 | LIST_HEAD(invalid_list); | |
cea0f0e7 | 2126 | |
a770f6f2 | 2127 | role = vcpu->arch.mmu.base_role; |
cea0f0e7 | 2128 | role.level = level; |
f6e2c02b | 2129 | role.direct = direct; |
84b0c8c6 | 2130 | if (role.direct) |
5b7e0102 | 2131 | role.cr4_pae = 0; |
41074d07 | 2132 | role.access = access; |
c5a78f2b JR |
2133 | if (!vcpu->arch.mmu.direct_map |
2134 | && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2135 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2136 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2137 | role.quadrant = quadrant; | |
2138 | } | |
b67bfe0d | 2139 | for_each_gfn_sp(vcpu->kvm, sp, gfn) { |
7f52af74 XG |
2140 | if (is_obsolete_sp(vcpu->kvm, sp)) |
2141 | continue; | |
2142 | ||
7ae680eb XG |
2143 | if (!need_sync && sp->unsync) |
2144 | need_sync = true; | |
4731d4c7 | 2145 | |
7ae680eb XG |
2146 | if (sp->role.word != role.word) |
2147 | continue; | |
4731d4c7 | 2148 | |
2a74003a PB |
2149 | if (sp->unsync) { |
2150 | /* The page is good, but __kvm_sync_page might still end | |
2151 | * up zapping it. If so, break in order to rebuild it. | |
2152 | */ | |
2153 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2154 | break; | |
2155 | ||
2156 | WARN_ON(!list_empty(&invalid_list)); | |
2157 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2158 | } | |
e02aa901 | 2159 | |
98bba238 | 2160 | if (sp->unsync_children) |
a8eeb04a | 2161 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2162 | |
a30f47cb | 2163 | __clear_sp_write_flooding_count(sp); |
7ae680eb XG |
2164 | trace_kvm_mmu_get_page(sp, false); |
2165 | return sp; | |
2166 | } | |
47005792 | 2167 | |
dfc5aa00 | 2168 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2169 | |
2170 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2171 | ||
4db35314 AK |
2172 | sp->gfn = gfn; |
2173 | sp->role = role; | |
7ae680eb XG |
2174 | hlist_add_head(&sp->hash_link, |
2175 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2176 | if (!direct) { |
56ca57f9 XG |
2177 | /* |
2178 | * we should do write protection before syncing pages | |
2179 | * otherwise the content of the synced shadow page may | |
2180 | * be inconsistent with guest page table. | |
2181 | */ | |
2182 | account_shadowed(vcpu->kvm, sp); | |
2183 | if (level == PT_PAGE_TABLE_LEVEL && | |
2184 | rmap_write_protect(vcpu, gfn)) | |
b1a36821 | 2185 | kvm_flush_remote_tlbs(vcpu->kvm); |
9f1a122f | 2186 | |
9f1a122f | 2187 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2188 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2189 | } |
5304b8d3 | 2190 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2191 | clear_page(sp->spt); |
f691fe1d | 2192 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2193 | |
2194 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4db35314 | 2195 | return sp; |
cea0f0e7 AK |
2196 | } |
2197 | ||
2d11123a AK |
2198 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2199 | struct kvm_vcpu *vcpu, u64 addr) | |
2200 | { | |
2201 | iterator->addr = addr; | |
2202 | iterator->shadow_addr = vcpu->arch.mmu.root_hpa; | |
2203 | iterator->level = vcpu->arch.mmu.shadow_root_level; | |
81407ca5 JR |
2204 | |
2205 | if (iterator->level == PT64_ROOT_LEVEL && | |
2206 | vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL && | |
2207 | !vcpu->arch.mmu.direct_map) | |
2208 | --iterator->level; | |
2209 | ||
2d11123a AK |
2210 | if (iterator->level == PT32E_ROOT_LEVEL) { |
2211 | iterator->shadow_addr | |
2212 | = vcpu->arch.mmu.pae_root[(addr >> 30) & 3]; | |
2213 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; | |
2214 | --iterator->level; | |
2215 | if (!iterator->shadow_addr) | |
2216 | iterator->level = 0; | |
2217 | } | |
2218 | } | |
2219 | ||
2220 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) | |
2221 | { | |
2222 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2223 | return false; | |
4d88954d | 2224 | |
2d11123a AK |
2225 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2226 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2227 | return true; | |
2228 | } | |
2229 | ||
c2a2ac2b XG |
2230 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2231 | u64 spte) | |
2d11123a | 2232 | { |
c2a2ac2b | 2233 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2234 | iterator->level = 0; |
2235 | return; | |
2236 | } | |
2237 | ||
c2a2ac2b | 2238 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2239 | --iterator->level; |
2240 | } | |
2241 | ||
c2a2ac2b XG |
2242 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2243 | { | |
2244 | return __shadow_walk_next(iterator, *iterator->sptep); | |
2245 | } | |
2246 | ||
98bba238 TY |
2247 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2248 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2249 | { |
2250 | u64 spte; | |
2251 | ||
7a1638ce YZ |
2252 | BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK || |
2253 | VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); | |
2254 | ||
24db2734 | 2255 | spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK | |
0e3d0648 | 2256 | shadow_user_mask | shadow_x_mask | shadow_accessed_mask; |
24db2734 | 2257 | |
1df9f2dc | 2258 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2259 | |
2260 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2261 | ||
2262 | if (sp->unsync_children || sp->unsync) | |
2263 | mark_unsync(sptep); | |
32ef26a3 AK |
2264 | } |
2265 | ||
a357bd22 AK |
2266 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2267 | unsigned direct_access) | |
2268 | { | |
2269 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2270 | struct kvm_mmu_page *child; | |
2271 | ||
2272 | /* | |
2273 | * For the direct sp, if the guest pte's dirty bit | |
2274 | * changed form clean to dirty, it will corrupt the | |
2275 | * sp's access: allow writable in the read-only sp, | |
2276 | * so we should update the spte at this point to get | |
2277 | * a new sp with the correct access. | |
2278 | */ | |
2279 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2280 | if (child->role.access == direct_access) | |
2281 | return; | |
2282 | ||
bcdd9a93 | 2283 | drop_parent_pte(child, sptep); |
a357bd22 AK |
2284 | kvm_flush_remote_tlbs(vcpu->kvm); |
2285 | } | |
2286 | } | |
2287 | ||
505aef8f | 2288 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2289 | u64 *spte) |
2290 | { | |
2291 | u64 pte; | |
2292 | struct kvm_mmu_page *child; | |
2293 | ||
2294 | pte = *spte; | |
2295 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2296 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2297 | drop_spte(kvm, spte); |
505aef8f XG |
2298 | if (is_large_pte(pte)) |
2299 | --kvm->stat.lpages; | |
2300 | } else { | |
38e3b2b2 | 2301 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2302 | drop_parent_pte(child, spte); |
38e3b2b2 | 2303 | } |
505aef8f XG |
2304 | return true; |
2305 | } | |
2306 | ||
2307 | if (is_mmio_spte(pte)) | |
ce88decf | 2308 | mmu_spte_clear_no_track(spte); |
c3707958 | 2309 | |
505aef8f | 2310 | return false; |
38e3b2b2 XG |
2311 | } |
2312 | ||
90cb0529 | 2313 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2314 | struct kvm_mmu_page *sp) |
a436036b | 2315 | { |
697fe2e2 | 2316 | unsigned i; |
697fe2e2 | 2317 | |
38e3b2b2 XG |
2318 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2319 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2320 | } |
2321 | ||
31aa2b44 | 2322 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2323 | { |
1e3f42f0 TY |
2324 | u64 *sptep; |
2325 | struct rmap_iterator iter; | |
a436036b | 2326 | |
018aabb5 | 2327 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2328 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2329 | } |
2330 | ||
60c8aec6 | 2331 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2332 | struct kvm_mmu_page *parent, |
2333 | struct list_head *invalid_list) | |
4731d4c7 | 2334 | { |
60c8aec6 MT |
2335 | int i, zapped = 0; |
2336 | struct mmu_page_path parents; | |
2337 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2338 | |
60c8aec6 | 2339 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2340 | return 0; |
60c8aec6 | 2341 | |
60c8aec6 MT |
2342 | while (mmu_unsync_walk(parent, &pages)) { |
2343 | struct kvm_mmu_page *sp; | |
2344 | ||
2345 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2346 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2347 | mmu_pages_clear_parents(&parents); |
77662e00 | 2348 | zapped++; |
60c8aec6 | 2349 | } |
60c8aec6 MT |
2350 | } |
2351 | ||
2352 | return zapped; | |
4731d4c7 MT |
2353 | } |
2354 | ||
7775834a XG |
2355 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2356 | struct list_head *invalid_list) | |
31aa2b44 | 2357 | { |
4731d4c7 | 2358 | int ret; |
f691fe1d | 2359 | |
7775834a | 2360 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2361 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2362 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2363 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2364 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2365 | |
f6e2c02b | 2366 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2367 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2368 | |
4731d4c7 MT |
2369 | if (sp->unsync) |
2370 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2371 | if (!sp->root_count) { |
54a4f023 GJ |
2372 | /* Count self */ |
2373 | ret++; | |
7775834a | 2374 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2375 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2376 | } else { |
5b5c6a5a | 2377 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2378 | |
2379 | /* | |
2380 | * The obsolete pages can not be used on any vcpus. | |
2381 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2382 | */ | |
2383 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2384 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2385 | } |
7775834a XG |
2386 | |
2387 | sp->role.invalid = 1; | |
4731d4c7 | 2388 | return ret; |
a436036b AK |
2389 | } |
2390 | ||
7775834a XG |
2391 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2392 | struct list_head *invalid_list) | |
2393 | { | |
945315b9 | 2394 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2395 | |
2396 | if (list_empty(invalid_list)) | |
2397 | return; | |
2398 | ||
c142786c | 2399 | /* |
9753f529 LT |
2400 | * We need to make sure everyone sees our modifications to |
2401 | * the page tables and see changes to vcpu->mode here. The barrier | |
2402 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2403 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2404 | * | |
2405 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2406 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2407 | */ |
2408 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2409 | |
945315b9 | 2410 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2411 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2412 | kvm_mmu_free_page(sp); |
945315b9 | 2413 | } |
7775834a XG |
2414 | } |
2415 | ||
5da59607 TY |
2416 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2417 | struct list_head *invalid_list) | |
2418 | { | |
2419 | struct kvm_mmu_page *sp; | |
2420 | ||
2421 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2422 | return false; | |
2423 | ||
d74c0e6b GT |
2424 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2425 | struct kvm_mmu_page, link); | |
5da59607 TY |
2426 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
2427 | ||
2428 | return true; | |
2429 | } | |
2430 | ||
82ce2c96 IE |
2431 | /* |
2432 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2433 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2434 | */ |
49d5ca26 | 2435 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2436 | { |
d98ba053 | 2437 | LIST_HEAD(invalid_list); |
82ce2c96 | 2438 | |
b34cb590 TY |
2439 | spin_lock(&kvm->mmu_lock); |
2440 | ||
49d5ca26 | 2441 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2442 | /* Need to free some mmu pages to achieve the goal. */ |
2443 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2444 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2445 | break; | |
82ce2c96 | 2446 | |
aa6bd187 | 2447 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2448 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2449 | } |
82ce2c96 | 2450 | |
49d5ca26 | 2451 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2452 | |
2453 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2454 | } |
2455 | ||
1cb3f3ae | 2456 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2457 | { |
4db35314 | 2458 | struct kvm_mmu_page *sp; |
d98ba053 | 2459 | LIST_HEAD(invalid_list); |
a436036b AK |
2460 | int r; |
2461 | ||
9ad17b10 | 2462 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2463 | r = 0; |
1cb3f3ae | 2464 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2465 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2466 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2467 | sp->role.word); |
2468 | r = 1; | |
f41d335a | 2469 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2470 | } |
d98ba053 | 2471 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2472 | spin_unlock(&kvm->mmu_lock); |
2473 | ||
a436036b | 2474 | return r; |
cea0f0e7 | 2475 | } |
1cb3f3ae | 2476 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2477 | |
5c520e90 | 2478 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2479 | { |
2480 | trace_kvm_mmu_unsync_page(sp); | |
2481 | ++vcpu->kvm->stat.mmu_unsync; | |
2482 | sp->unsync = 1; | |
2483 | ||
2484 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2485 | } |
2486 | ||
3d0c27ad XG |
2487 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2488 | bool can_unsync) | |
4731d4c7 | 2489 | { |
5c520e90 | 2490 | struct kvm_mmu_page *sp; |
4731d4c7 | 2491 | |
3d0c27ad XG |
2492 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2493 | return true; | |
9cf5cf5a | 2494 | |
5c520e90 | 2495 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2496 | if (!can_unsync) |
3d0c27ad | 2497 | return true; |
36a2e677 | 2498 | |
5c520e90 XG |
2499 | if (sp->unsync) |
2500 | continue; | |
9cf5cf5a | 2501 | |
5c520e90 XG |
2502 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2503 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2504 | } |
3d0c27ad XG |
2505 | |
2506 | return false; | |
4731d4c7 MT |
2507 | } |
2508 | ||
ba049e93 | 2509 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2510 | { |
2511 | if (pfn_valid(pfn)) | |
2512 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)); | |
2513 | ||
2514 | return true; | |
2515 | } | |
2516 | ||
d555c333 | 2517 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2518 | unsigned pte_access, int level, |
ba049e93 | 2519 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2520 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2521 | { |
6e7d0354 | 2522 | u64 spte; |
1e73f9dd | 2523 | int ret = 0; |
64d4d521 | 2524 | |
54bf36aa | 2525 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2526 | return 0; |
2527 | ||
982c2565 | 2528 | spte = PT_PRESENT_MASK; |
947da538 | 2529 | if (!speculative) |
3201b5d9 | 2530 | spte |= shadow_accessed_mask; |
640d9b0d | 2531 | |
7b52345e SY |
2532 | if (pte_access & ACC_EXEC_MASK) |
2533 | spte |= shadow_x_mask; | |
2534 | else | |
2535 | spte |= shadow_nx_mask; | |
49fde340 | 2536 | |
1c4f1fd6 | 2537 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2538 | spte |= shadow_user_mask; |
49fde340 | 2539 | |
852e3c19 | 2540 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2541 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2542 | if (tdp_enabled) |
4b12f0de | 2543 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2544 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2545 | |
9bdbba13 | 2546 | if (host_writable) |
1403283a | 2547 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2548 | else |
2549 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2550 | |
35149e21 | 2551 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2552 | |
c2288505 | 2553 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2554 | |
c2193463 | 2555 | /* |
7751babd XG |
2556 | * Other vcpu creates new sp in the window between |
2557 | * mapping_level() and acquiring mmu-lock. We can | |
2558 | * allow guest to retry the access, the mapping can | |
2559 | * be fixed if guest refault. | |
c2193463 | 2560 | */ |
852e3c19 | 2561 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2562 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2563 | goto done; |
38187c83 | 2564 | |
49fde340 | 2565 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2566 | |
ecc5589f MT |
2567 | /* |
2568 | * Optimization: for pte sync, if spte was writable the hash | |
2569 | * lookup is unnecessary (and expensive). Write protection | |
2570 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2571 | * Same reasoning can be applied to dirty page accounting. | |
2572 | */ | |
8dae4445 | 2573 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2574 | goto set_pte; |
2575 | ||
4731d4c7 | 2576 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2577 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2578 | __func__, gfn); |
1e73f9dd | 2579 | ret = 1; |
1c4f1fd6 | 2580 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2581 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2582 | } |
2583 | } | |
2584 | ||
9b51a630 | 2585 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2586 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
9b51a630 KH |
2587 | spte |= shadow_dirty_mask; |
2588 | } | |
1c4f1fd6 | 2589 | |
38187c83 | 2590 | set_pte: |
6e7d0354 | 2591 | if (mmu_spte_update(sptep, spte)) |
b330aa0c | 2592 | kvm_flush_remote_tlbs(vcpu->kvm); |
be38d276 | 2593 | done: |
1e73f9dd MT |
2594 | return ret; |
2595 | } | |
2596 | ||
029499b4 | 2597 | static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
ba049e93 | 2598 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, |
029499b4 | 2599 | bool speculative, bool host_writable) |
1e73f9dd MT |
2600 | { |
2601 | int was_rmapped = 0; | |
53a27b39 | 2602 | int rmap_count; |
029499b4 | 2603 | bool emulate = false; |
1e73f9dd | 2604 | |
f7616203 XG |
2605 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
2606 | *sptep, write_fault, gfn); | |
1e73f9dd | 2607 | |
afd28fe1 | 2608 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
2609 | /* |
2610 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
2611 | * the parent of the now unreachable PTE. | |
2612 | */ | |
852e3c19 JR |
2613 | if (level > PT_PAGE_TABLE_LEVEL && |
2614 | !is_large_pte(*sptep)) { | |
1e73f9dd | 2615 | struct kvm_mmu_page *child; |
d555c333 | 2616 | u64 pte = *sptep; |
1e73f9dd MT |
2617 | |
2618 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 2619 | drop_parent_pte(child, sptep); |
3be2264b | 2620 | kvm_flush_remote_tlbs(vcpu->kvm); |
d555c333 | 2621 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 2622 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 2623 | spte_to_pfn(*sptep), pfn); |
c3707958 | 2624 | drop_spte(vcpu->kvm, sptep); |
91546356 | 2625 | kvm_flush_remote_tlbs(vcpu->kvm); |
6bed6b9e JR |
2626 | } else |
2627 | was_rmapped = 1; | |
1e73f9dd | 2628 | } |
852e3c19 | 2629 | |
c2288505 XG |
2630 | if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative, |
2631 | true, host_writable)) { | |
1e73f9dd | 2632 | if (write_fault) |
029499b4 | 2633 | emulate = true; |
77c3913b | 2634 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 2635 | } |
1e73f9dd | 2636 | |
029499b4 TY |
2637 | if (unlikely(is_mmio_spte(*sptep))) |
2638 | emulate = true; | |
ce88decf | 2639 | |
d555c333 | 2640 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 2641 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 2642 | is_large_pte(*sptep)? "2MB" : "4kB", |
a205bc19 JR |
2643 | *sptep & PT_PRESENT_MASK ?"RW":"R", gfn, |
2644 | *sptep, sptep); | |
d555c333 | 2645 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
2646 | ++vcpu->kvm->stat.lpages; |
2647 | ||
ffb61bb3 | 2648 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
2649 | if (!was_rmapped) { |
2650 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
2651 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
2652 | rmap_recycle(vcpu, sptep, gfn); | |
2653 | } | |
1c4f1fd6 | 2654 | } |
cb9aaa30 | 2655 | |
f3ac1a4b | 2656 | kvm_release_pfn_clean(pfn); |
029499b4 TY |
2657 | |
2658 | return emulate; | |
1c4f1fd6 AK |
2659 | } |
2660 | ||
ba049e93 | 2661 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
2662 | bool no_dirty_log) |
2663 | { | |
2664 | struct kvm_memory_slot *slot; | |
957ed9ef | 2665 | |
5d163b1c | 2666 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 2667 | if (!slot) |
6c8ee57b | 2668 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 2669 | |
037d92dc | 2670 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
2671 | } |
2672 | ||
2673 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
2674 | struct kvm_mmu_page *sp, | |
2675 | u64 *start, u64 *end) | |
2676 | { | |
2677 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 2678 | struct kvm_memory_slot *slot; |
957ed9ef XG |
2679 | unsigned access = sp->role.access; |
2680 | int i, ret; | |
2681 | gfn_t gfn; | |
2682 | ||
2683 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
2684 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
2685 | if (!slot) | |
957ed9ef XG |
2686 | return -1; |
2687 | ||
d9ef13c2 | 2688 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
2689 | if (ret <= 0) |
2690 | return -1; | |
2691 | ||
2692 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
2693 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
2694 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
2695 | |
2696 | return 0; | |
2697 | } | |
2698 | ||
2699 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
2700 | struct kvm_mmu_page *sp, u64 *sptep) | |
2701 | { | |
2702 | u64 *spte, *start = NULL; | |
2703 | int i; | |
2704 | ||
2705 | WARN_ON(!sp->role.direct); | |
2706 | ||
2707 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
2708 | spte = sp->spt + i; | |
2709 | ||
2710 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 2711 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
2712 | if (!start) |
2713 | continue; | |
2714 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
2715 | break; | |
2716 | start = NULL; | |
2717 | } else if (!start) | |
2718 | start = spte; | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
2723 | { | |
2724 | struct kvm_mmu_page *sp; | |
2725 | ||
2726 | /* | |
2727 | * Since it's no accessed bit on EPT, it's no way to | |
2728 | * distinguish between actually accessed translations | |
2729 | * and prefetched, so disable pte prefetch if EPT is | |
2730 | * enabled. | |
2731 | */ | |
2732 | if (!shadow_accessed_mask) | |
2733 | return; | |
2734 | ||
2735 | sp = page_header(__pa(sptep)); | |
2736 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2737 | return; | |
2738 | ||
2739 | __direct_pte_prefetch(vcpu, sp, sptep); | |
2740 | } | |
2741 | ||
7ee0e5b2 | 2742 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 2743 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 2744 | { |
9f652d21 | 2745 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 2746 | struct kvm_mmu_page *sp; |
b90a0e6c | 2747 | int emulate = 0; |
140754bc | 2748 | gfn_t pseudo_gfn; |
6aa8b732 | 2749 | |
989c6b34 MT |
2750 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2751 | return 0; | |
2752 | ||
9f652d21 | 2753 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 2754 | if (iterator.level == level) { |
029499b4 TY |
2755 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
2756 | write, level, gfn, pfn, prefault, | |
2757 | map_writable); | |
957ed9ef | 2758 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
2759 | ++vcpu->stat.pf_fixed; |
2760 | break; | |
6aa8b732 AK |
2761 | } |
2762 | ||
404381c5 | 2763 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 2764 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
2765 | u64 base_addr = iterator.addr; |
2766 | ||
2767 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
2768 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 2769 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 2770 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 2771 | |
98bba238 | 2772 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
2773 | } |
2774 | } | |
b90a0e6c | 2775 | return emulate; |
6aa8b732 AK |
2776 | } |
2777 | ||
77db5cbd | 2778 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 2779 | { |
77db5cbd HY |
2780 | siginfo_t info; |
2781 | ||
2782 | info.si_signo = SIGBUS; | |
2783 | info.si_errno = 0; | |
2784 | info.si_code = BUS_MCEERR_AR; | |
2785 | info.si_addr = (void __user *)address; | |
2786 | info.si_addr_lsb = PAGE_SHIFT; | |
bf998156 | 2787 | |
77db5cbd | 2788 | send_sig_info(SIGBUS, &info, tsk); |
bf998156 HY |
2789 | } |
2790 | ||
ba049e93 | 2791 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 2792 | { |
4d8b81ab XG |
2793 | /* |
2794 | * Do not cache the mmio info caused by writing the readonly gfn | |
2795 | * into the spte otherwise read access on readonly gfn also can | |
2796 | * caused mmio page fault and treat it as mmio access. | |
2797 | * Return 1 to tell kvm to emulate it. | |
2798 | */ | |
2799 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
2800 | return 1; | |
2801 | ||
e6c1502b | 2802 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 2803 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
bf998156 | 2804 | return 0; |
d7c55201 | 2805 | } |
edba23e5 | 2806 | |
d7c55201 | 2807 | return -EFAULT; |
bf998156 HY |
2808 | } |
2809 | ||
936a5fe6 | 2810 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
2811 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
2812 | int *levelp) | |
936a5fe6 | 2813 | { |
ba049e93 | 2814 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
2815 | gfn_t gfn = *gfnp; |
2816 | int level = *levelp; | |
2817 | ||
2818 | /* | |
2819 | * Check if it's a transparent hugepage. If this would be an | |
2820 | * hugetlbfs page, level wouldn't be set to | |
2821 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
2822 | * here. | |
2823 | */ | |
bf4bea8e | 2824 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 AA |
2825 | level == PT_PAGE_TABLE_LEVEL && |
2826 | PageTransCompound(pfn_to_page(pfn)) && | |
92f94f1e | 2827 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
2828 | unsigned long mask; |
2829 | /* | |
2830 | * mmu_notifier_retry was successful and we hold the | |
2831 | * mmu_lock here, so the pmd can't become splitting | |
2832 | * from under us, and in turn | |
2833 | * __split_huge_page_refcount() can't run from under | |
2834 | * us and we can safely transfer the refcount from | |
2835 | * PG_tail to PG_head as we switch the pfn to tail to | |
2836 | * head. | |
2837 | */ | |
2838 | *levelp = level = PT_DIRECTORY_LEVEL; | |
2839 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
2840 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
2841 | if (pfn & mask) { | |
2842 | gfn &= ~mask; | |
2843 | *gfnp = gfn; | |
2844 | kvm_release_pfn_clean(pfn); | |
2845 | pfn &= ~mask; | |
c3586667 | 2846 | kvm_get_pfn(pfn); |
936a5fe6 AA |
2847 | *pfnp = pfn; |
2848 | } | |
2849 | } | |
2850 | } | |
2851 | ||
d7c55201 | 2852 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 2853 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 2854 | { |
d7c55201 | 2855 | /* The pfn is invalid, report the error! */ |
81c52c56 | 2856 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 2857 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 2858 | return true; |
d7c55201 XG |
2859 | } |
2860 | ||
ce88decf | 2861 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 2862 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 2863 | |
798e88b3 | 2864 | return false; |
d7c55201 XG |
2865 | } |
2866 | ||
e5552fd2 | 2867 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 2868 | { |
1c118b82 XG |
2869 | /* |
2870 | * Do not fix the mmio spte with invalid generation number which | |
2871 | * need to be updated by slow page fault path. | |
2872 | */ | |
2873 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
2874 | return false; | |
2875 | ||
c7ba5b48 XG |
2876 | /* |
2877 | * #PF can be fast only if the shadow page table is present and it | |
2878 | * is caused by write-protect, that means we just need change the | |
2879 | * W bit of the spte which can be done out of mmu-lock. | |
2880 | */ | |
2881 | if (!(error_code & PFERR_PRESENT_MASK) || | |
2882 | !(error_code & PFERR_WRITE_MASK)) | |
2883 | return false; | |
2884 | ||
2885 | return true; | |
2886 | } | |
2887 | ||
2888 | static bool | |
92a476cb XG |
2889 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2890 | u64 *sptep, u64 spte) | |
c7ba5b48 | 2891 | { |
c7ba5b48 XG |
2892 | gfn_t gfn; |
2893 | ||
2894 | WARN_ON(!sp->role.direct); | |
2895 | ||
2896 | /* | |
2897 | * The gfn of direct spte is stable since it is calculated | |
2898 | * by sp->gfn. | |
2899 | */ | |
2900 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
2901 | ||
9b51a630 KH |
2902 | /* |
2903 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
2904 | * order to eliminate unnecessary PML logging. See comments in | |
2905 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
2906 | * enabled, so we do not do this. This might result in the same GPA | |
2907 | * to be logged in PML buffer again when the write really happens, and | |
2908 | * eventually to be called by mark_page_dirty twice. But it's also no | |
2909 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
2910 | * so non-PML cases won't be impacted. | |
2911 | * | |
2912 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
2913 | */ | |
c7ba5b48 | 2914 | if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte) |
54bf36aa | 2915 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
c7ba5b48 XG |
2916 | |
2917 | return true; | |
2918 | } | |
2919 | ||
2920 | /* | |
2921 | * Return value: | |
2922 | * - true: let the vcpu to access on the same address again. | |
2923 | * - false: let the real page fault path to fix it. | |
2924 | */ | |
2925 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
2926 | u32 error_code) | |
2927 | { | |
2928 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 2929 | struct kvm_mmu_page *sp; |
c7ba5b48 XG |
2930 | bool ret = false; |
2931 | u64 spte = 0ull; | |
2932 | ||
37f6a4e2 MT |
2933 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
2934 | return false; | |
2935 | ||
e5552fd2 | 2936 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
2937 | return false; |
2938 | ||
2939 | walk_shadow_page_lockless_begin(vcpu); | |
2940 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) | |
2941 | if (!is_shadow_present_pte(spte) || iterator.level < level) | |
2942 | break; | |
2943 | ||
2944 | /* | |
2945 | * If the mapping has been changed, let the vcpu fault on the | |
2946 | * same address again. | |
2947 | */ | |
afd28fe1 | 2948 | if (!is_shadow_present_pte(spte)) { |
c7ba5b48 XG |
2949 | ret = true; |
2950 | goto exit; | |
2951 | } | |
2952 | ||
92a476cb XG |
2953 | sp = page_header(__pa(iterator.sptep)); |
2954 | if (!is_last_spte(spte, sp->role.level)) | |
c7ba5b48 XG |
2955 | goto exit; |
2956 | ||
2957 | /* | |
2958 | * Check if it is a spurious fault caused by TLB lazily flushed. | |
2959 | * | |
2960 | * Need not check the access of upper level table entries since | |
2961 | * they are always ACC_ALL. | |
2962 | */ | |
2963 | if (is_writable_pte(spte)) { | |
2964 | ret = true; | |
2965 | goto exit; | |
2966 | } | |
2967 | ||
2968 | /* | |
2969 | * Currently, to simplify the code, only the spte write-protected | |
2970 | * by dirty-log can be fast fixed. | |
2971 | */ | |
2972 | if (!spte_is_locklessly_modifiable(spte)) | |
2973 | goto exit; | |
2974 | ||
c126d94f XG |
2975 | /* |
2976 | * Do not fix write-permission on the large spte since we only dirty | |
2977 | * the first page into the dirty-bitmap in fast_pf_fix_direct_spte() | |
2978 | * that means other pages are missed if its slot is dirty-logged. | |
2979 | * | |
2980 | * Instead, we let the slow page fault path create a normal spte to | |
2981 | * fix the access. | |
2982 | * | |
2983 | * See the comments in kvm_arch_commit_memory_region(). | |
2984 | */ | |
2985 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
2986 | goto exit; | |
2987 | ||
c7ba5b48 XG |
2988 | /* |
2989 | * Currently, fast page fault only works for direct mapping since | |
2990 | * the gfn is not stable for indirect shadow page. | |
2991 | * See Documentation/virtual/kvm/locking.txt to get more detail. | |
2992 | */ | |
92a476cb | 2993 | ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte); |
c7ba5b48 | 2994 | exit: |
a72faf25 XG |
2995 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
2996 | spte, ret); | |
c7ba5b48 XG |
2997 | walk_shadow_page_lockless_end(vcpu); |
2998 | ||
2999 | return ret; | |
3000 | } | |
3001 | ||
78b2c54a | 3002 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3003 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
450e0b41 | 3004 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3005 | |
c7ba5b48 XG |
3006 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3007 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3008 | { |
3009 | int r; | |
852e3c19 | 3010 | int level; |
fd136902 | 3011 | bool force_pt_level = false; |
ba049e93 | 3012 | kvm_pfn_t pfn; |
e930bffe | 3013 | unsigned long mmu_seq; |
c7ba5b48 | 3014 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3015 | |
fd136902 | 3016 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3017 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3018 | /* |
3019 | * This path builds a PAE pagetable - so we can map | |
3020 | * 2mb pages at maximum. Therefore check if the level | |
3021 | * is larger than that. | |
3022 | */ | |
3023 | if (level > PT_DIRECTORY_LEVEL) | |
3024 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3025 | |
936a5fe6 | 3026 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3027 | } |
05da4558 | 3028 | |
c7ba5b48 XG |
3029 | if (fast_page_fault(vcpu, v, level, error_code)) |
3030 | return 0; | |
3031 | ||
e930bffe | 3032 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3033 | smp_rmb(); |
060c2abe | 3034 | |
78b2c54a | 3035 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
060c2abe | 3036 | return 0; |
aaee2c94 | 3037 | |
d7c55201 XG |
3038 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3039 | return r; | |
d196e343 | 3040 | |
aaee2c94 | 3041 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3042 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3043 | goto out_unlock; |
450e0b41 | 3044 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3045 | if (likely(!force_pt_level)) |
3046 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3047 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3048 | spin_unlock(&vcpu->kvm->mmu_lock); |
3049 | ||
10589a46 | 3050 | return r; |
e930bffe AA |
3051 | |
3052 | out_unlock: | |
3053 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3054 | kvm_release_pfn_clean(pfn); | |
3055 | return 0; | |
10589a46 MT |
3056 | } |
3057 | ||
3058 | ||
17ac10ad AK |
3059 | static void mmu_free_roots(struct kvm_vcpu *vcpu) |
3060 | { | |
3061 | int i; | |
4db35314 | 3062 | struct kvm_mmu_page *sp; |
d98ba053 | 3063 | LIST_HEAD(invalid_list); |
17ac10ad | 3064 | |
ad312c7c | 3065 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
7b53aa56 | 3066 | return; |
35af577a | 3067 | |
81407ca5 JR |
3068 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL && |
3069 | (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL || | |
3070 | vcpu->arch.mmu.direct_map)) { | |
ad312c7c | 3071 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3072 | |
35af577a | 3073 | spin_lock(&vcpu->kvm->mmu_lock); |
4db35314 AK |
3074 | sp = page_header(root); |
3075 | --sp->root_count; | |
d98ba053 XG |
3076 | if (!sp->root_count && sp->role.invalid) { |
3077 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); | |
3078 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); | |
3079 | } | |
aaee2c94 | 3080 | spin_unlock(&vcpu->kvm->mmu_lock); |
35af577a | 3081 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3082 | return; |
3083 | } | |
35af577a GN |
3084 | |
3085 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3086 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3087 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3088 | |
417726a3 | 3089 | if (root) { |
417726a3 | 3090 | root &= PT64_BASE_ADDR_MASK; |
4db35314 AK |
3091 | sp = page_header(root); |
3092 | --sp->root_count; | |
2e53d63a | 3093 | if (!sp->root_count && sp->role.invalid) |
d98ba053 XG |
3094 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, |
3095 | &invalid_list); | |
417726a3 | 3096 | } |
ad312c7c | 3097 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 3098 | } |
d98ba053 | 3099 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3100 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3101 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
17ac10ad AK |
3102 | } |
3103 | ||
8986ecc0 MT |
3104 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3105 | { | |
3106 | int ret = 0; | |
3107 | ||
3108 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3109 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3110 | ret = 1; |
3111 | } | |
3112 | ||
3113 | return ret; | |
3114 | } | |
3115 | ||
651dd37a JR |
3116 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3117 | { | |
3118 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3119 | unsigned i; |
651dd37a JR |
3120 | |
3121 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3122 | spin_lock(&vcpu->kvm->mmu_lock); | |
450e0b41 | 3123 | make_mmu_pages_available(vcpu); |
bb11c6c9 | 3124 | sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3125 | ++sp->root_count; |
3126 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3127 | vcpu->arch.mmu.root_hpa = __pa(sp->spt); | |
3128 | } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) { | |
3129 | for (i = 0; i < 4; ++i) { | |
3130 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3131 | ||
fa4a2c08 | 3132 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3133 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3134 | make_mmu_pages_available(vcpu); |
649497d1 | 3135 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3136 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3137 | root = __pa(sp->spt); |
3138 | ++sp->root_count; | |
3139 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3140 | vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK; | |
651dd37a | 3141 | } |
6292757f | 3142 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
651dd37a JR |
3143 | } else |
3144 | BUG(); | |
3145 | ||
3146 | return 0; | |
3147 | } | |
3148 | ||
3149 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3150 | { |
4db35314 | 3151 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3152 | u64 pdptr, pm_mask; |
3153 | gfn_t root_gfn; | |
3154 | int i; | |
3bb65a22 | 3155 | |
5777ed34 | 3156 | root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3157 | |
651dd37a JR |
3158 | if (mmu_check_root(vcpu, root_gfn)) |
3159 | return 1; | |
3160 | ||
3161 | /* | |
3162 | * Do we shadow a long mode page table? If so we need to | |
3163 | * write-protect the guests page table root. | |
3164 | */ | |
3165 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { | |
ad312c7c | 3166 | hpa_t root = vcpu->arch.mmu.root_hpa; |
17ac10ad | 3167 | |
fa4a2c08 | 3168 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3169 | |
8facbbff | 3170 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3171 | make_mmu_pages_available(vcpu); |
651dd37a | 3172 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL, |
bb11c6c9 | 3173 | 0, ACC_ALL); |
4db35314 AK |
3174 | root = __pa(sp->spt); |
3175 | ++sp->root_count; | |
8facbbff | 3176 | spin_unlock(&vcpu->kvm->mmu_lock); |
ad312c7c | 3177 | vcpu->arch.mmu.root_hpa = root; |
8986ecc0 | 3178 | return 0; |
17ac10ad | 3179 | } |
f87f9288 | 3180 | |
651dd37a JR |
3181 | /* |
3182 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3183 | * or a PAE 3-level page table. In either case we need to be aware that |
3184 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3185 | */ |
81407ca5 JR |
3186 | pm_mask = PT_PRESENT_MASK; |
3187 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) | |
3188 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; | |
3189 | ||
17ac10ad | 3190 | for (i = 0; i < 4; ++i) { |
ad312c7c | 3191 | hpa_t root = vcpu->arch.mmu.pae_root[i]; |
17ac10ad | 3192 | |
fa4a2c08 | 3193 | MMU_WARN_ON(VALID_PAGE(root)); |
ad312c7c | 3194 | if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 3195 | pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i); |
43a3795a | 3196 | if (!is_present_gpte(pdptr)) { |
ad312c7c | 3197 | vcpu->arch.mmu.pae_root[i] = 0; |
417726a3 AK |
3198 | continue; |
3199 | } | |
6de4f3ad | 3200 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3201 | if (mmu_check_root(vcpu, root_gfn)) |
3202 | return 1; | |
5a7388c2 | 3203 | } |
8facbbff | 3204 | spin_lock(&vcpu->kvm->mmu_lock); |
450e0b41 | 3205 | make_mmu_pages_available(vcpu); |
bb11c6c9 TY |
3206 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3207 | 0, ACC_ALL); | |
4db35314 AK |
3208 | root = __pa(sp->spt); |
3209 | ++sp->root_count; | |
8facbbff AK |
3210 | spin_unlock(&vcpu->kvm->mmu_lock); |
3211 | ||
81407ca5 | 3212 | vcpu->arch.mmu.pae_root[i] = root | pm_mask; |
17ac10ad | 3213 | } |
6292757f | 3214 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root); |
81407ca5 JR |
3215 | |
3216 | /* | |
3217 | * If we shadow a 32 bit page table with a long mode page | |
3218 | * table we enter this path. | |
3219 | */ | |
3220 | if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) { | |
3221 | if (vcpu->arch.mmu.lm_root == NULL) { | |
3222 | /* | |
3223 | * The additional page necessary for this is only | |
3224 | * allocated on demand. | |
3225 | */ | |
3226 | ||
3227 | u64 *lm_root; | |
3228 | ||
3229 | lm_root = (void*)get_zeroed_page(GFP_KERNEL); | |
3230 | if (lm_root == NULL) | |
3231 | return 1; | |
3232 | ||
3233 | lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask; | |
3234 | ||
3235 | vcpu->arch.mmu.lm_root = lm_root; | |
3236 | } | |
3237 | ||
3238 | vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root); | |
3239 | } | |
3240 | ||
8986ecc0 | 3241 | return 0; |
17ac10ad AK |
3242 | } |
3243 | ||
651dd37a JR |
3244 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3245 | { | |
3246 | if (vcpu->arch.mmu.direct_map) | |
3247 | return mmu_alloc_direct_roots(vcpu); | |
3248 | else | |
3249 | return mmu_alloc_shadow_roots(vcpu); | |
3250 | } | |
3251 | ||
0ba73cda MT |
3252 | static void mmu_sync_roots(struct kvm_vcpu *vcpu) |
3253 | { | |
3254 | int i; | |
3255 | struct kvm_mmu_page *sp; | |
3256 | ||
81407ca5 JR |
3257 | if (vcpu->arch.mmu.direct_map) |
3258 | return; | |
3259 | ||
0ba73cda MT |
3260 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
3261 | return; | |
6903074c | 3262 | |
56f17dd3 | 3263 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
0375f7fa | 3264 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); |
81407ca5 | 3265 | if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) { |
0ba73cda MT |
3266 | hpa_t root = vcpu->arch.mmu.root_hpa; |
3267 | sp = page_header(root); | |
3268 | mmu_sync_children(vcpu, sp); | |
0375f7fa | 3269 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3270 | return; |
3271 | } | |
3272 | for (i = 0; i < 4; ++i) { | |
3273 | hpa_t root = vcpu->arch.mmu.pae_root[i]; | |
3274 | ||
8986ecc0 | 3275 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3276 | root &= PT64_BASE_ADDR_MASK; |
3277 | sp = page_header(root); | |
3278 | mmu_sync_children(vcpu, sp); | |
3279 | } | |
3280 | } | |
0375f7fa | 3281 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
0ba73cda MT |
3282 | } |
3283 | ||
3284 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) | |
3285 | { | |
3286 | spin_lock(&vcpu->kvm->mmu_lock); | |
3287 | mmu_sync_roots(vcpu); | |
6cffe8ca | 3288 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3289 | } |
bfd0a56b | 3290 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3291 | |
1871c602 | 3292 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3293 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3294 | { |
ab9ae313 AK |
3295 | if (exception) |
3296 | exception->error_code = 0; | |
6aa8b732 AK |
3297 | return vaddr; |
3298 | } | |
3299 | ||
6539e738 | 3300 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3301 | u32 access, |
3302 | struct x86_exception *exception) | |
6539e738 | 3303 | { |
ab9ae313 AK |
3304 | if (exception) |
3305 | exception->error_code = 0; | |
54987b7a | 3306 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3307 | } |
3308 | ||
d625b155 XG |
3309 | static bool |
3310 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3311 | { | |
3312 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3313 | ||
3314 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3315 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3316 | } | |
3317 | ||
3318 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3319 | { | |
3320 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3321 | } | |
3322 | ||
3323 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3324 | { | |
3325 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3326 | } | |
3327 | ||
ded58749 | 3328 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3329 | { |
3330 | if (direct) | |
3331 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3332 | ||
3333 | return vcpu_match_mmio_gva(vcpu, addr); | |
3334 | } | |
3335 | ||
47ab8751 XG |
3336 | /* return true if reserved bit is detected on spte. */ |
3337 | static bool | |
3338 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3339 | { |
3340 | struct kvm_shadow_walk_iterator iterator; | |
47ab8751 XG |
3341 | u64 sptes[PT64_ROOT_LEVEL], spte = 0ull; |
3342 | int root, leaf; | |
3343 | bool reserved = false; | |
ce88decf | 3344 | |
37f6a4e2 | 3345 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) |
47ab8751 | 3346 | goto exit; |
37f6a4e2 | 3347 | |
ce88decf | 3348 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3349 | |
29ecd660 PB |
3350 | for (shadow_walk_init(&iterator, vcpu, addr), |
3351 | leaf = root = iterator.level; | |
47ab8751 XG |
3352 | shadow_walk_okay(&iterator); |
3353 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3354 | spte = mmu_spte_get_lockless(iterator.sptep); |
3355 | ||
3356 | sptes[leaf - 1] = spte; | |
29ecd660 | 3357 | leaf--; |
47ab8751 | 3358 | |
ce88decf XG |
3359 | if (!is_shadow_present_pte(spte)) |
3360 | break; | |
47ab8751 XG |
3361 | |
3362 | reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte, | |
58c95070 | 3363 | iterator.level); |
47ab8751 XG |
3364 | } |
3365 | ||
ce88decf XG |
3366 | walk_shadow_page_lockless_end(vcpu); |
3367 | ||
47ab8751 XG |
3368 | if (reserved) { |
3369 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3370 | __func__, addr); | |
29ecd660 | 3371 | while (root > leaf) { |
47ab8751 XG |
3372 | pr_err("------ spte 0x%llx level %d.\n", |
3373 | sptes[root - 1], root); | |
3374 | root--; | |
3375 | } | |
3376 | } | |
3377 | exit: | |
3378 | *sptep = spte; | |
3379 | return reserved; | |
ce88decf XG |
3380 | } |
3381 | ||
450869d6 | 3382 | int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3383 | { |
3384 | u64 spte; | |
47ab8751 | 3385 | bool reserved; |
ce88decf | 3386 | |
ded58749 | 3387 | if (mmio_info_in_cache(vcpu, addr, direct)) |
b37fbea6 | 3388 | return RET_MMIO_PF_EMULATE; |
ce88decf | 3389 | |
47ab8751 | 3390 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3391 | if (WARN_ON(reserved)) |
47ab8751 | 3392 | return RET_MMIO_PF_BUG; |
ce88decf XG |
3393 | |
3394 | if (is_mmio_spte(spte)) { | |
3395 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3396 | unsigned access = get_mmio_spte_access(spte); | |
3397 | ||
54bf36aa | 3398 | if (!check_mmio_spte(vcpu, spte)) |
f8f55942 XG |
3399 | return RET_MMIO_PF_INVALID; |
3400 | ||
ce88decf XG |
3401 | if (direct) |
3402 | addr = 0; | |
4f022648 XG |
3403 | |
3404 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3405 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
b37fbea6 | 3406 | return RET_MMIO_PF_EMULATE; |
ce88decf XG |
3407 | } |
3408 | ||
ce88decf XG |
3409 | /* |
3410 | * If the page table is zapped by other cpus, let CPU fault again on | |
3411 | * the address. | |
3412 | */ | |
b37fbea6 | 3413 | return RET_MMIO_PF_RETRY; |
ce88decf | 3414 | } |
450869d6 | 3415 | EXPORT_SYMBOL_GPL(handle_mmio_page_fault); |
ce88decf | 3416 | |
3d0c27ad XG |
3417 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3418 | u32 error_code, gfn_t gfn) | |
3419 | { | |
3420 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3421 | return false; | |
3422 | ||
3423 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3424 | !(error_code & PFERR_WRITE_MASK)) | |
3425 | return false; | |
3426 | ||
3427 | /* | |
3428 | * guest is writing the page which is write tracked which can | |
3429 | * not be fixed by page fault handler. | |
3430 | */ | |
3431 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3432 | return true; | |
3433 | ||
3434 | return false; | |
3435 | } | |
3436 | ||
e5691a81 XG |
3437 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3438 | { | |
3439 | struct kvm_shadow_walk_iterator iterator; | |
3440 | u64 spte; | |
3441 | ||
3442 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3443 | return; | |
3444 | ||
3445 | walk_shadow_page_lockless_begin(vcpu); | |
3446 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3447 | clear_sp_write_flooding_count(iterator.sptep); | |
3448 | if (!is_shadow_present_pte(spte)) | |
3449 | break; | |
3450 | } | |
3451 | walk_shadow_page_lockless_end(vcpu); | |
3452 | } | |
3453 | ||
6aa8b732 | 3454 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3455 | u32 error_code, bool prefault) |
6aa8b732 | 3456 | { |
3d0c27ad | 3457 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3458 | int r; |
6aa8b732 | 3459 | |
b8688d51 | 3460 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3461 | |
3d0c27ad XG |
3462 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3463 | return 1; | |
ce88decf | 3464 | |
e2dec939 AK |
3465 | r = mmu_topup_memory_caches(vcpu); |
3466 | if (r) | |
3467 | return r; | |
714b93da | 3468 | |
fa4a2c08 | 3469 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
6aa8b732 | 3470 | |
6aa8b732 | 3471 | |
e833240f | 3472 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3473 | error_code, gfn, prefault); |
6aa8b732 AK |
3474 | } |
3475 | ||
7e1fbeac | 3476 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3477 | { |
3478 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3479 | |
7c90705b | 3480 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3481 | arch.gfn = gfn; |
c4806acd | 3482 | arch.direct_map = vcpu->arch.mmu.direct_map; |
fb67e14f | 3483 | arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu); |
af585b92 | 3484 | |
54bf36aa | 3485 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3486 | } |
3487 | ||
3488 | static bool can_do_async_pf(struct kvm_vcpu *vcpu) | |
3489 | { | |
35754c98 | 3490 | if (unlikely(!lapic_in_kernel(vcpu) || |
af585b92 GN |
3491 | kvm_event_needs_reinjection(vcpu))) |
3492 | return false; | |
3493 | ||
3494 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
3495 | } | |
3496 | ||
78b2c54a | 3497 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3498 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 3499 | { |
3520469d | 3500 | struct kvm_memory_slot *slot; |
af585b92 GN |
3501 | bool async; |
3502 | ||
54bf36aa | 3503 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
3504 | async = false; |
3505 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
3506 | if (!async) |
3507 | return false; /* *pfn has correct page already */ | |
3508 | ||
78b2c54a | 3509 | if (!prefault && can_do_async_pf(vcpu)) { |
c9b263d2 | 3510 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
3511 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
3512 | trace_kvm_async_pf_doublefault(gva, gfn); | |
3513 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
3514 | return true; | |
3515 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
3516 | return true; | |
3517 | } | |
3518 | ||
3520469d | 3519 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
3520 | return false; |
3521 | } | |
3522 | ||
6a39bbc5 XG |
3523 | static bool |
3524 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
3525 | { | |
3526 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
3527 | ||
3528 | gfn &= ~(page_num - 1); | |
3529 | ||
3530 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
3531 | } | |
3532 | ||
56028d08 | 3533 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 3534 | bool prefault) |
fb72d167 | 3535 | { |
ba049e93 | 3536 | kvm_pfn_t pfn; |
fb72d167 | 3537 | int r; |
852e3c19 | 3538 | int level; |
cd1872f0 | 3539 | bool force_pt_level; |
05da4558 | 3540 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 3541 | unsigned long mmu_seq; |
612819c3 MT |
3542 | int write = error_code & PFERR_WRITE_MASK; |
3543 | bool map_writable; | |
fb72d167 | 3544 | |
fa4a2c08 | 3545 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
fb72d167 | 3546 | |
3d0c27ad XG |
3547 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
3548 | return 1; | |
ce88decf | 3549 | |
fb72d167 JR |
3550 | r = mmu_topup_memory_caches(vcpu); |
3551 | if (r) | |
3552 | return r; | |
3553 | ||
fd136902 TY |
3554 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
3555 | PT_DIRECTORY_LEVEL); | |
3556 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 3557 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
3558 | if (level > PT_DIRECTORY_LEVEL && |
3559 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
3560 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 3561 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3562 | } |
852e3c19 | 3563 | |
c7ba5b48 XG |
3564 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
3565 | return 0; | |
3566 | ||
e930bffe | 3567 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3568 | smp_rmb(); |
af585b92 | 3569 | |
78b2c54a | 3570 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
af585b92 GN |
3571 | return 0; |
3572 | ||
d7c55201 XG |
3573 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
3574 | return r; | |
3575 | ||
fb72d167 | 3576 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3577 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3578 | goto out_unlock; |
450e0b41 | 3579 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
3580 | if (likely(!force_pt_level)) |
3581 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3582 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 3583 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
3584 | |
3585 | return r; | |
e930bffe AA |
3586 | |
3587 | out_unlock: | |
3588 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3589 | kvm_release_pfn_clean(pfn); | |
3590 | return 0; | |
fb72d167 JR |
3591 | } |
3592 | ||
8a3c1a33 PB |
3593 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
3594 | struct kvm_mmu *context) | |
6aa8b732 | 3595 | { |
6aa8b732 | 3596 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 3597 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 3598 | context->sync_page = nonpaging_sync_page; |
a7052897 | 3599 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 3600 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 3601 | context->root_level = 0; |
6aa8b732 | 3602 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 3603 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 3604 | context->direct_map = true; |
2d48a985 | 3605 | context->nx = false; |
6aa8b732 AK |
3606 | } |
3607 | ||
d8d173da | 3608 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu) |
6aa8b732 | 3609 | { |
cea0f0e7 | 3610 | mmu_free_roots(vcpu); |
6aa8b732 AK |
3611 | } |
3612 | ||
5777ed34 JR |
3613 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
3614 | { | |
9f8fe504 | 3615 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
3616 | } |
3617 | ||
6389ee94 AK |
3618 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
3619 | struct x86_exception *fault) | |
6aa8b732 | 3620 | { |
6389ee94 | 3621 | vcpu->arch.mmu.inject_page_fault(vcpu, fault); |
6aa8b732 AK |
3622 | } |
3623 | ||
54bf36aa | 3624 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 3625 | unsigned access, int *nr_present) |
ce88decf XG |
3626 | { |
3627 | if (unlikely(is_mmio_spte(*sptep))) { | |
3628 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
3629 | mmu_spte_clear_no_track(sptep); | |
3630 | return true; | |
3631 | } | |
3632 | ||
3633 | (*nr_present)++; | |
54bf36aa | 3634 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
3635 | return true; |
3636 | } | |
3637 | ||
3638 | return false; | |
3639 | } | |
3640 | ||
6bb69c9b PB |
3641 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
3642 | unsigned level, unsigned gpte) | |
6fd01b71 | 3643 | { |
6bb69c9b PB |
3644 | /* |
3645 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
3646 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
3647 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
3648 | */ | |
3649 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
6fd01b71 | 3650 | |
6bb69c9b PB |
3651 | /* |
3652 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
3653 | * If it is clear, there are no large pages at this level, so clear | |
3654 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
3655 | */ | |
3656 | gpte &= level - mmu->last_nonleaf_level; | |
3657 | ||
3658 | return gpte & PT_PAGE_SIZE_MASK; | |
6fd01b71 AK |
3659 | } |
3660 | ||
37406aaa NHE |
3661 | #define PTTYPE_EPT 18 /* arbitrary */ |
3662 | #define PTTYPE PTTYPE_EPT | |
3663 | #include "paging_tmpl.h" | |
3664 | #undef PTTYPE | |
3665 | ||
6aa8b732 AK |
3666 | #define PTTYPE 64 |
3667 | #include "paging_tmpl.h" | |
3668 | #undef PTTYPE | |
3669 | ||
3670 | #define PTTYPE 32 | |
3671 | #include "paging_tmpl.h" | |
3672 | #undef PTTYPE | |
3673 | ||
6dc98b86 XG |
3674 | static void |
3675 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
3676 | struct rsvd_bits_validate *rsvd_check, | |
3677 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 3678 | bool pse, bool amd) |
82725b20 | 3679 | { |
82725b20 | 3680 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 3681 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 3682 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 3683 | |
a0a64f50 | 3684 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 3685 | |
6dc98b86 | 3686 | if (!nx) |
82725b20 | 3687 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 3688 | if (!gbpages) |
5f7dde7b | 3689 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
3690 | |
3691 | /* | |
3692 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
3693 | * leaf entries) on AMD CPUs only. | |
3694 | */ | |
6fec2144 | 3695 | if (amd) |
a0c0feb5 PB |
3696 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
3697 | ||
6dc98b86 | 3698 | switch (level) { |
82725b20 DE |
3699 | case PT32_ROOT_LEVEL: |
3700 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
3701 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
3702 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
3703 | rsvd_check->rsvd_bits_mask[1][0] = | |
3704 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 3705 | |
6dc98b86 | 3706 | if (!pse) { |
a0a64f50 | 3707 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
3708 | break; |
3709 | } | |
3710 | ||
82725b20 DE |
3711 | if (is_cpuid_PSE36()) |
3712 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 3713 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
3714 | else |
3715 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 3716 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
3717 | break; |
3718 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 3719 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 3720 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 3721 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 3722 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 3723 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 3724 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 3725 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 3726 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
3727 | rsvd_bits(maxphyaddr, 62) | |
3728 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3729 | rsvd_check->rsvd_bits_mask[1][0] = |
3730 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3731 | break; |
3732 | case PT64_ROOT_LEVEL: | |
a0a64f50 XG |
3733 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
3734 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 3735 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3736 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
3737 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 3738 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
3739 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
3740 | rsvd_bits(maxphyaddr, 51); | |
3741 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
3742 | rsvd_bits(maxphyaddr, 51); | |
3743 | rsvd_check->rsvd_bits_mask[1][3] = | |
3744 | rsvd_check->rsvd_bits_mask[0][3]; | |
3745 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 3746 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 3747 | rsvd_bits(13, 29); |
a0a64f50 | 3748 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
3749 | rsvd_bits(maxphyaddr, 51) | |
3750 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
3751 | rsvd_check->rsvd_bits_mask[1][0] = |
3752 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
3753 | break; |
3754 | } | |
3755 | } | |
3756 | ||
6dc98b86 XG |
3757 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
3758 | struct kvm_mmu *context) | |
3759 | { | |
3760 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
3761 | cpuid_maxphyaddr(vcpu), context->root_level, | |
3762 | context->nx, guest_cpuid_has_gbpages(vcpu), | |
6fec2144 | 3763 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
3764 | } |
3765 | ||
81b8eebb XG |
3766 | static void |
3767 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
3768 | int maxphyaddr, bool execonly) | |
25d92081 | 3769 | { |
951f9fd7 | 3770 | u64 bad_mt_xwr; |
25d92081 | 3771 | |
a0a64f50 | 3772 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 3773 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 3774 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 3775 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 3776 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 3777 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 3778 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
3779 | |
3780 | /* large page */ | |
a0a64f50 XG |
3781 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
3782 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 3783 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 3784 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 3785 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 3786 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 3787 | |
951f9fd7 PB |
3788 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
3789 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
3790 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
3791 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
3792 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
3793 | if (!execonly) { | |
3794 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
3795 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 3796 | } |
951f9fd7 | 3797 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
3798 | } |
3799 | ||
81b8eebb XG |
3800 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
3801 | struct kvm_mmu *context, bool execonly) | |
3802 | { | |
3803 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
3804 | cpuid_maxphyaddr(vcpu), execonly); | |
3805 | } | |
3806 | ||
c258b62b XG |
3807 | /* |
3808 | * the page table on host is the shadow page table for the page | |
3809 | * table in guest or amd nested guest, its mmu features completely | |
3810 | * follow the features in guest. | |
3811 | */ | |
3812 | void | |
3813 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
3814 | { | |
5f0b8199 PB |
3815 | bool uses_nx = context->nx || context->base_role.smep_andnot_wp; |
3816 | ||
6fec2144 PB |
3817 | /* |
3818 | * Passing "true" to the last argument is okay; it adds a check | |
3819 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
3820 | */ | |
c258b62b XG |
3821 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
3822 | boot_cpu_data.x86_phys_bits, | |
5f0b8199 | 3823 | context->shadow_root_level, uses_nx, |
6fec2144 PB |
3824 | guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), |
3825 | true); | |
c258b62b XG |
3826 | } |
3827 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
3828 | ||
6fec2144 PB |
3829 | static inline bool boot_cpu_is_amd(void) |
3830 | { | |
3831 | WARN_ON_ONCE(!tdp_enabled); | |
3832 | return shadow_x_mask == 0; | |
3833 | } | |
3834 | ||
c258b62b XG |
3835 | /* |
3836 | * the direct page table on host, use as much mmu features as | |
3837 | * possible, however, kvm currently does not do execution-protection. | |
3838 | */ | |
3839 | static void | |
3840 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
3841 | struct kvm_mmu *context) | |
3842 | { | |
6fec2144 | 3843 | if (boot_cpu_is_amd()) |
c258b62b XG |
3844 | __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, |
3845 | boot_cpu_data.x86_phys_bits, | |
3846 | context->shadow_root_level, false, | |
6fec2144 | 3847 | cpu_has_gbpages, true, true); |
c258b62b XG |
3848 | else |
3849 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
3850 | boot_cpu_data.x86_phys_bits, | |
3851 | false); | |
3852 | ||
3853 | } | |
3854 | ||
3855 | /* | |
3856 | * as the comments in reset_shadow_zero_bits_mask() except it | |
3857 | * is the shadow page table for intel nested guest. | |
3858 | */ | |
3859 | static void | |
3860 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
3861 | struct kvm_mmu *context, bool execonly) | |
3862 | { | |
3863 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
3864 | boot_cpu_data.x86_phys_bits, execonly); | |
3865 | } | |
3866 | ||
edc90b7d XG |
3867 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
3868 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 AK |
3869 | { |
3870 | unsigned bit, byte, pfec; | |
3871 | u8 map; | |
66386ade | 3872 | bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0; |
97d64b78 | 3873 | |
66386ade | 3874 | cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
97ec8c06 | 3875 | cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
97d64b78 AK |
3876 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
3877 | pfec = byte << 1; | |
3878 | map = 0; | |
3879 | wf = pfec & PFERR_WRITE_MASK; | |
3880 | uf = pfec & PFERR_USER_MASK; | |
3881 | ff = pfec & PFERR_FETCH_MASK; | |
97ec8c06 FW |
3882 | /* |
3883 | * PFERR_RSVD_MASK bit is set in PFEC if the access is not | |
3884 | * subject to SMAP restrictions, and cleared otherwise. The | |
3885 | * bit is only meaningful if the SMAP bit is set in CR4. | |
3886 | */ | |
3887 | smapf = !(pfec & PFERR_RSVD_MASK); | |
97d64b78 AK |
3888 | for (bit = 0; bit < 8; ++bit) { |
3889 | x = bit & ACC_EXEC_MASK; | |
3890 | w = bit & ACC_WRITE_MASK; | |
3891 | u = bit & ACC_USER_MASK; | |
3892 | ||
25d92081 YZ |
3893 | if (!ept) { |
3894 | /* Not really needed: !nx will cause pte.nx to fault */ | |
3895 | x |= !mmu->nx; | |
3896 | /* Allow supervisor writes if !cr0.wp */ | |
3897 | w |= !is_write_protection(vcpu) && !uf; | |
3898 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
66386ade | 3899 | x &= !(cr4_smep && u && !uf); |
97ec8c06 FW |
3900 | |
3901 | /* | |
3902 | * SMAP:kernel-mode data accesses from user-mode | |
3903 | * mappings should fault. A fault is considered | |
3904 | * as a SMAP violation if all of the following | |
3905 | * conditions are ture: | |
3906 | * - X86_CR4_SMAP is set in CR4 | |
3907 | * - An user page is accessed | |
3908 | * - Page fault in kernel mode | |
3909 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
3910 | * | |
3911 | * Here, we cover the first three conditions. | |
3912 | * The fourth is computed dynamically in | |
3913 | * permission_fault() and is in smapf. | |
3914 | * | |
3915 | * Also, SMAP does not affect instruction | |
3916 | * fetches, add the !ff check here to make it | |
3917 | * clearer. | |
3918 | */ | |
3919 | smap = cr4_smap && u && !uf && !ff; | |
25d92081 YZ |
3920 | } else |
3921 | /* Not really needed: no U/S accesses on ept */ | |
3922 | u = 1; | |
97d64b78 | 3923 | |
97ec8c06 FW |
3924 | fault = (ff && !x) || (uf && !u) || (wf && !w) || |
3925 | (smapf && smap); | |
97d64b78 AK |
3926 | map |= fault << bit; |
3927 | } | |
3928 | mmu->permissions[byte] = map; | |
3929 | } | |
3930 | } | |
3931 | ||
2d344105 HH |
3932 | /* |
3933 | * PKU is an additional mechanism by which the paging controls access to | |
3934 | * user-mode addresses based on the value in the PKRU register. Protection | |
3935 | * key violations are reported through a bit in the page fault error code. | |
3936 | * Unlike other bits of the error code, the PK bit is not known at the | |
3937 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
3938 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
3939 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
3940 | * | |
3941 | * In particular the following conditions come from the error code, the | |
3942 | * page tables and the machine state: | |
3943 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
3944 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
3945 | * - PK is always zero if U=0 in the page tables | |
3946 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
3947 | * | |
3948 | * The PKRU bitmask caches the result of these four conditions. The error | |
3949 | * code (minus the P bit) and the page table's U bit form an index into the | |
3950 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
3951 | * with the two bits of the PKRU register corresponding to the protection key. | |
3952 | * For the first three conditions above the bits will be 00, thus masking | |
3953 | * away both AD and WD. For all reads or if the last condition holds, WD | |
3954 | * only will be masked away. | |
3955 | */ | |
3956 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
3957 | bool ept) | |
3958 | { | |
3959 | unsigned bit; | |
3960 | bool wp; | |
3961 | ||
3962 | if (ept) { | |
3963 | mmu->pkru_mask = 0; | |
3964 | return; | |
3965 | } | |
3966 | ||
3967 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
3968 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
3969 | mmu->pkru_mask = 0; | |
3970 | return; | |
3971 | } | |
3972 | ||
3973 | wp = is_write_protection(vcpu); | |
3974 | ||
3975 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
3976 | unsigned pfec, pkey_bits; | |
3977 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
3978 | ||
3979 | pfec = bit << 1; | |
3980 | ff = pfec & PFERR_FETCH_MASK; | |
3981 | uf = pfec & PFERR_USER_MASK; | |
3982 | wf = pfec & PFERR_WRITE_MASK; | |
3983 | ||
3984 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
3985 | pte_user = pfec & PFERR_RSVD_MASK; | |
3986 | ||
3987 | /* | |
3988 | * Only need to check the access which is not an | |
3989 | * instruction fetch and is to a user page. | |
3990 | */ | |
3991 | check_pkey = (!ff && pte_user); | |
3992 | /* | |
3993 | * write access is controlled by PKRU if it is a | |
3994 | * user access or CR0.WP = 1. | |
3995 | */ | |
3996 | check_write = check_pkey && wf && (uf || wp); | |
3997 | ||
3998 | /* PKRU.AD stops both read and write access. */ | |
3999 | pkey_bits = !!check_pkey; | |
4000 | /* PKRU.WD stops write access. */ | |
4001 | pkey_bits |= (!!check_write) << 1; | |
4002 | ||
4003 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4004 | } | |
4005 | } | |
4006 | ||
6bb69c9b | 4007 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4008 | { |
6bb69c9b PB |
4009 | unsigned root_level = mmu->root_level; |
4010 | ||
4011 | mmu->last_nonleaf_level = root_level; | |
4012 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4013 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4014 | } |
4015 | ||
8a3c1a33 PB |
4016 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4017 | struct kvm_mmu *context, | |
4018 | int level) | |
6aa8b732 | 4019 | { |
2d48a985 | 4020 | context->nx = is_nx(vcpu); |
4d6931c3 | 4021 | context->root_level = level; |
2d48a985 | 4022 | |
4d6931c3 | 4023 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4024 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4025 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4026 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4027 | |
fa4a2c08 | 4028 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4029 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4030 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4031 | context->sync_page = paging64_sync_page; |
a7052897 | 4032 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4033 | context->update_pte = paging64_update_pte; |
17ac10ad | 4034 | context->shadow_root_level = level; |
17c3ba9d | 4035 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4036 | context->direct_map = false; |
6aa8b732 AK |
4037 | } |
4038 | ||
8a3c1a33 PB |
4039 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4040 | struct kvm_mmu *context) | |
17ac10ad | 4041 | { |
8a3c1a33 | 4042 | paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL); |
17ac10ad AK |
4043 | } |
4044 | ||
8a3c1a33 PB |
4045 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4046 | struct kvm_mmu *context) | |
6aa8b732 | 4047 | { |
2d48a985 | 4048 | context->nx = false; |
4d6931c3 | 4049 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4050 | |
4d6931c3 | 4051 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4052 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4053 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4054 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4055 | |
6aa8b732 | 4056 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4057 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4058 | context->sync_page = paging32_sync_page; |
a7052897 | 4059 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4060 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4061 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
17c3ba9d | 4062 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4063 | context->direct_map = false; |
6aa8b732 AK |
4064 | } |
4065 | ||
8a3c1a33 PB |
4066 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4067 | struct kvm_mmu *context) | |
6aa8b732 | 4068 | { |
8a3c1a33 | 4069 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4070 | } |
4071 | ||
8a3c1a33 | 4072 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4073 | { |
ad896af0 | 4074 | struct kvm_mmu *context = &vcpu->arch.mmu; |
fb72d167 | 4075 | |
c445f8ef | 4076 | context->base_role.word = 0; |
699023e2 | 4077 | context->base_role.smm = is_smm(vcpu); |
fb72d167 | 4078 | context->page_fault = tdp_page_fault; |
e8bc217a | 4079 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4080 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4081 | context->update_pte = nonpaging_update_pte; |
67253af5 | 4082 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); |
fb72d167 | 4083 | context->root_hpa = INVALID_PAGE; |
c5a78f2b | 4084 | context->direct_map = true; |
1c97f0a0 | 4085 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4086 | context->get_cr3 = get_cr3; |
e4e517b4 | 4087 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4088 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4089 | |
4090 | if (!is_paging(vcpu)) { | |
2d48a985 | 4091 | context->nx = false; |
fb72d167 JR |
4092 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4093 | context->root_level = 0; | |
4094 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4095 | context->nx = is_nx(vcpu); |
fb72d167 | 4096 | context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 DB |
4097 | reset_rsvds_bits_mask(vcpu, context); |
4098 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4099 | } else if (is_pae(vcpu)) { |
2d48a985 | 4100 | context->nx = is_nx(vcpu); |
fb72d167 | 4101 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4102 | reset_rsvds_bits_mask(vcpu, context); |
4103 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4104 | } else { |
2d48a985 | 4105 | context->nx = false; |
fb72d167 | 4106 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4107 | reset_rsvds_bits_mask(vcpu, context); |
4108 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4109 | } |
4110 | ||
25d92081 | 4111 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4112 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4113 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4114 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4115 | } |
4116 | ||
ad896af0 | 4117 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) |
6aa8b732 | 4118 | { |
411c588d | 4119 | bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
edc90b7d | 4120 | bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); |
ad896af0 PB |
4121 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4122 | ||
fa4a2c08 | 4123 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
6aa8b732 AK |
4124 | |
4125 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4126 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4127 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4128 | paging64_init_context(vcpu, context); |
6aa8b732 | 4129 | else if (is_pae(vcpu)) |
8a3c1a33 | 4130 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4131 | else |
8a3c1a33 | 4132 | paging32_init_context(vcpu, context); |
a770f6f2 | 4133 | |
ad896af0 PB |
4134 | context->base_role.nxe = is_nx(vcpu); |
4135 | context->base_role.cr4_pae = !!is_pae(vcpu); | |
4136 | context->base_role.cr0_wp = is_write_protection(vcpu); | |
4137 | context->base_role.smep_andnot_wp | |
411c588d | 4138 | = smep && !is_write_protection(vcpu); |
edc90b7d XG |
4139 | context->base_role.smap_andnot_wp |
4140 | = smap && !is_write_protection(vcpu); | |
699023e2 | 4141 | context->base_role.smm = is_smm(vcpu); |
c258b62b | 4142 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4143 | } |
4144 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4145 | ||
ad896af0 | 4146 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly) |
155a97a3 | 4147 | { |
ad896af0 PB |
4148 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4149 | ||
fa4a2c08 | 4150 | MMU_WARN_ON(VALID_PAGE(context->root_hpa)); |
155a97a3 NHE |
4151 | |
4152 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(); | |
4153 | ||
4154 | context->nx = true; | |
155a97a3 NHE |
4155 | context->page_fault = ept_page_fault; |
4156 | context->gva_to_gpa = ept_gva_to_gpa; | |
4157 | context->sync_page = ept_sync_page; | |
4158 | context->invlpg = ept_invlpg; | |
4159 | context->update_pte = ept_update_pte; | |
155a97a3 NHE |
4160 | context->root_level = context->shadow_root_level; |
4161 | context->root_hpa = INVALID_PAGE; | |
4162 | context->direct_map = false; | |
4163 | ||
4164 | update_permission_bitmask(vcpu, context, true); | |
2d344105 | 4165 | update_pkru_bitmask(vcpu, context, true); |
155a97a3 | 4166 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4167 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4168 | } |
4169 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4170 | ||
8a3c1a33 | 4171 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4172 | { |
ad896af0 PB |
4173 | struct kvm_mmu *context = &vcpu->arch.mmu; |
4174 | ||
4175 | kvm_init_shadow_mmu(vcpu); | |
4176 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4177 | context->get_cr3 = get_cr3; | |
4178 | context->get_pdptr = kvm_pdptr_read; | |
4179 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4180 | } |
4181 | ||
8a3c1a33 | 4182 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 JR |
4183 | { |
4184 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; | |
4185 | ||
4186 | g_context->get_cr3 = get_cr3; | |
e4e517b4 | 4187 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4188 | g_context->inject_page_fault = kvm_inject_page_fault; |
4189 | ||
4190 | /* | |
0af2593b DM |
4191 | * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using |
4192 | * L1's nested page tables (e.g. EPT12). The nested translation | |
4193 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
4194 | * L2's page tables as the first level of translation and L1's | |
4195 | * nested page tables as the second level of translation. Basically | |
4196 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
4197 | */ |
4198 | if (!is_paging(vcpu)) { | |
2d48a985 | 4199 | g_context->nx = false; |
02f59dc9 JR |
4200 | g_context->root_level = 0; |
4201 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
4202 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4203 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4204 | g_context->root_level = PT64_ROOT_LEVEL; |
4d6931c3 | 4205 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4206 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4207 | } else if (is_pae(vcpu)) { | |
2d48a985 | 4208 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 4209 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 4210 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4211 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
4212 | } else { | |
2d48a985 | 4213 | g_context->nx = false; |
02f59dc9 | 4214 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 4215 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
4216 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
4217 | } | |
4218 | ||
25d92081 | 4219 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 4220 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 4221 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
4222 | } |
4223 | ||
8a3c1a33 | 4224 | static void init_kvm_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4225 | { |
02f59dc9 | 4226 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 4227 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 4228 | else if (tdp_enabled) |
e0c6db3e | 4229 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 4230 | else |
e0c6db3e | 4231 | init_kvm_softmmu(vcpu); |
fb72d167 JR |
4232 | } |
4233 | ||
8a3c1a33 | 4234 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 4235 | { |
95f93af4 | 4236 | kvm_mmu_unload(vcpu); |
8a3c1a33 | 4237 | init_kvm_mmu(vcpu); |
17c3ba9d | 4238 | } |
8668a3c4 | 4239 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
4240 | |
4241 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 4242 | { |
714b93da AK |
4243 | int r; |
4244 | ||
e2dec939 | 4245 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
4246 | if (r) |
4247 | goto out; | |
8986ecc0 | 4248 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 4249 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
4250 | if (r) |
4251 | goto out; | |
3662cb1c | 4252 | /* set_cr3() should ensure TLB has been flushed */ |
f43addd4 | 4253 | vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa); |
714b93da AK |
4254 | out: |
4255 | return r; | |
6aa8b732 | 4256 | } |
17c3ba9d AK |
4257 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
4258 | ||
4259 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
4260 | { | |
4261 | mmu_free_roots(vcpu); | |
95f93af4 | 4262 | WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
17c3ba9d | 4263 | } |
4b16184c | 4264 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 4265 | |
0028425f | 4266 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
4267 | struct kvm_mmu_page *sp, u64 *spte, |
4268 | const void *new) | |
0028425f | 4269 | { |
30945387 | 4270 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
4271 | ++vcpu->kvm->stat.mmu_pde_zapped; |
4272 | return; | |
30945387 | 4273 | } |
0028425f | 4274 | |
4cee5764 | 4275 | ++vcpu->kvm->stat.mmu_pte_updated; |
7c562522 | 4276 | vcpu->arch.mmu.update_pte(vcpu, sp, spte, new); |
0028425f AK |
4277 | } |
4278 | ||
79539cec AK |
4279 | static bool need_remote_flush(u64 old, u64 new) |
4280 | { | |
4281 | if (!is_shadow_present_pte(old)) | |
4282 | return false; | |
4283 | if (!is_shadow_present_pte(new)) | |
4284 | return true; | |
4285 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
4286 | return true; | |
53166229 GN |
4287 | old ^= shadow_nx_mask; |
4288 | new ^= shadow_nx_mask; | |
79539cec AK |
4289 | return (old & ~new & PT64_PERM_MASK) != 0; |
4290 | } | |
4291 | ||
889e5cbc XG |
4292 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
4293 | const u8 *new, int *bytes) | |
da4a00f0 | 4294 | { |
889e5cbc XG |
4295 | u64 gentry; |
4296 | int r; | |
72016f3a | 4297 | |
72016f3a AK |
4298 | /* |
4299 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
4300 | * as the current vcpu paging mode since we update the sptes only |
4301 | * when they have the same mode. | |
72016f3a | 4302 | */ |
889e5cbc | 4303 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 4304 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
4305 | *gpa &= ~(gpa_t)7; |
4306 | *bytes = 8; | |
54bf36aa | 4307 | r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8); |
72016f3a AK |
4308 | if (r) |
4309 | gentry = 0; | |
08e850c6 AK |
4310 | new = (const u8 *)&gentry; |
4311 | } | |
4312 | ||
889e5cbc | 4313 | switch (*bytes) { |
08e850c6 AK |
4314 | case 4: |
4315 | gentry = *(const u32 *)new; | |
4316 | break; | |
4317 | case 8: | |
4318 | gentry = *(const u64 *)new; | |
4319 | break; | |
4320 | default: | |
4321 | gentry = 0; | |
4322 | break; | |
72016f3a AK |
4323 | } |
4324 | ||
889e5cbc XG |
4325 | return gentry; |
4326 | } | |
4327 | ||
4328 | /* | |
4329 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
4330 | * or we may be forking, in which case it is better to unmap the page. | |
4331 | */ | |
a138fe75 | 4332 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 4333 | { |
a30f47cb XG |
4334 | /* |
4335 | * Skip write-flooding detected for the sp whose level is 1, because | |
4336 | * it can become unsync, then the guest page is not write-protected. | |
4337 | */ | |
f71fa31f | 4338 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 4339 | return false; |
3246af0e | 4340 | |
e5691a81 XG |
4341 | atomic_inc(&sp->write_flooding_count); |
4342 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
4343 | } |
4344 | ||
4345 | /* | |
4346 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
4347 | * indicate a page is not used as a page table. | |
4348 | */ | |
4349 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
4350 | int bytes) | |
4351 | { | |
4352 | unsigned offset, pte_size, misaligned; | |
4353 | ||
4354 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
4355 | gpa, bytes, sp->role.word); | |
4356 | ||
4357 | offset = offset_in_page(gpa); | |
4358 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
4359 | |
4360 | /* | |
4361 | * Sometimes, the OS only writes the last one bytes to update status | |
4362 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
4363 | */ | |
4364 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
4365 | return false; | |
4366 | ||
889e5cbc XG |
4367 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
4368 | misaligned |= bytes < 4; | |
4369 | ||
4370 | return misaligned; | |
4371 | } | |
4372 | ||
4373 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
4374 | { | |
4375 | unsigned page_offset, quadrant; | |
4376 | u64 *spte; | |
4377 | int level; | |
4378 | ||
4379 | page_offset = offset_in_page(gpa); | |
4380 | level = sp->role.level; | |
4381 | *nspte = 1; | |
4382 | if (!sp->role.cr4_pae) { | |
4383 | page_offset <<= 1; /* 32->64 */ | |
4384 | /* | |
4385 | * A 32-bit pde maps 4MB while the shadow pdes map | |
4386 | * only 2MB. So we need to double the offset again | |
4387 | * and zap two pdes instead of one. | |
4388 | */ | |
4389 | if (level == PT32_ROOT_LEVEL) { | |
4390 | page_offset &= ~7; /* kill rounding error */ | |
4391 | page_offset <<= 1; | |
4392 | *nspte = 2; | |
4393 | } | |
4394 | quadrant = page_offset >> PAGE_SHIFT; | |
4395 | page_offset &= ~PAGE_MASK; | |
4396 | if (quadrant != sp->role.quadrant) | |
4397 | return NULL; | |
4398 | } | |
4399 | ||
4400 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
4401 | return spte; | |
4402 | } | |
4403 | ||
13d268ca XG |
4404 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
4405 | const u8 *new, int bytes) | |
889e5cbc XG |
4406 | { |
4407 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 4408 | struct kvm_mmu_page *sp; |
889e5cbc XG |
4409 | LIST_HEAD(invalid_list); |
4410 | u64 entry, gentry, *spte; | |
4411 | int npte; | |
b8c67b7a | 4412 | bool remote_flush, local_flush; |
4141259b AM |
4413 | union kvm_mmu_page_role mask = { }; |
4414 | ||
4415 | mask.cr0_wp = 1; | |
4416 | mask.cr4_pae = 1; | |
4417 | mask.nxe = 1; | |
4418 | mask.smep_andnot_wp = 1; | |
4419 | mask.smap_andnot_wp = 1; | |
699023e2 | 4420 | mask.smm = 1; |
889e5cbc XG |
4421 | |
4422 | /* | |
4423 | * If we don't have indirect shadow pages, it means no page is | |
4424 | * write-protected, so we can exit simply. | |
4425 | */ | |
4426 | if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) | |
4427 | return; | |
4428 | ||
b8c67b7a | 4429 | remote_flush = local_flush = false; |
889e5cbc XG |
4430 | |
4431 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
4432 | ||
4433 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes); | |
4434 | ||
4435 | /* | |
4436 | * No need to care whether allocation memory is successful | |
4437 | * or not since pte prefetch is skiped if it does not have | |
4438 | * enough objects in the cache. | |
4439 | */ | |
4440 | mmu_topup_memory_caches(vcpu); | |
4441 | ||
4442 | spin_lock(&vcpu->kvm->mmu_lock); | |
4443 | ++vcpu->kvm->stat.mmu_pte_write; | |
0375f7fa | 4444 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 4445 | |
b67bfe0d | 4446 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 4447 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 4448 | detect_write_flooding(sp)) { |
b8c67b7a | 4449 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 4450 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
4451 | continue; |
4452 | } | |
889e5cbc XG |
4453 | |
4454 | spte = get_written_sptes(sp, gpa, &npte); | |
4455 | if (!spte) | |
4456 | continue; | |
4457 | ||
0671a8e7 | 4458 | local_flush = true; |
ac1b714e | 4459 | while (npte--) { |
79539cec | 4460 | entry = *spte; |
38e3b2b2 | 4461 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf XG |
4462 | if (gentry && |
4463 | !((sp->role.word ^ vcpu->arch.mmu.base_role.word) | |
f759e2b4 | 4464 | & mask.word) && rmap_can_add(vcpu)) |
7c562522 | 4465 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 4466 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 4467 | remote_flush = true; |
ac1b714e | 4468 | ++spte; |
9b7a0325 | 4469 | } |
9b7a0325 | 4470 | } |
b8c67b7a | 4471 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 4472 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 4473 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
4474 | } |
4475 | ||
a436036b AK |
4476 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
4477 | { | |
10589a46 MT |
4478 | gpa_t gpa; |
4479 | int r; | |
a436036b | 4480 | |
c5a78f2b | 4481 | if (vcpu->arch.mmu.direct_map) |
60f24784 AK |
4482 | return 0; |
4483 | ||
1871c602 | 4484 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 4485 | |
10589a46 | 4486 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 4487 | |
10589a46 | 4488 | return r; |
a436036b | 4489 | } |
577bdc49 | 4490 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 4491 | |
81f4f76b | 4492 | static void make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 4493 | { |
d98ba053 | 4494 | LIST_HEAD(invalid_list); |
103ad25a | 4495 | |
81f4f76b TY |
4496 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
4497 | return; | |
4498 | ||
5da59607 TY |
4499 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
4500 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
4501 | break; | |
ebeace86 | 4502 | |
4cee5764 | 4503 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 4504 | } |
aa6bd187 | 4505 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
ebeace86 | 4506 | } |
ebeace86 | 4507 | |
dc25e89e AP |
4508 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code, |
4509 | void *insn, int insn_len) | |
3067714c | 4510 | { |
1cb3f3ae | 4511 | int r, emulation_type = EMULTYPE_RETRY; |
3067714c | 4512 | enum emulation_result er; |
ded58749 | 4513 | bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu); |
3067714c | 4514 | |
e9ee956e TY |
4515 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
4516 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
4517 | if (r == RET_MMIO_PF_EMULATE) { | |
4518 | emulation_type = 0; | |
4519 | goto emulate; | |
4520 | } | |
4521 | if (r == RET_MMIO_PF_RETRY) | |
4522 | return 1; | |
4523 | if (r < 0) | |
4524 | return r; | |
4525 | } | |
3067714c | 4526 | |
56028d08 | 4527 | r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false); |
3067714c | 4528 | if (r < 0) |
e9ee956e TY |
4529 | return r; |
4530 | if (!r) | |
4531 | return 1; | |
3067714c | 4532 | |
ded58749 | 4533 | if (mmio_info_in_cache(vcpu, cr2, direct)) |
1cb3f3ae | 4534 | emulation_type = 0; |
e9ee956e | 4535 | emulate: |
1cb3f3ae | 4536 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
4537 | |
4538 | switch (er) { | |
4539 | case EMULATE_DONE: | |
4540 | return 1; | |
ac0a48c3 | 4541 | case EMULATE_USER_EXIT: |
3067714c | 4542 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 4543 | /* fall through */ |
3067714c | 4544 | case EMULATE_FAIL: |
3f5d18a9 | 4545 | return 0; |
3067714c AK |
4546 | default: |
4547 | BUG(); | |
4548 | } | |
3067714c AK |
4549 | } |
4550 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
4551 | ||
a7052897 MT |
4552 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
4553 | { | |
a7052897 | 4554 | vcpu->arch.mmu.invlpg(vcpu, gva); |
77c3913b | 4555 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a7052897 MT |
4556 | ++vcpu->stat.invlpg; |
4557 | } | |
4558 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
4559 | ||
18552672 JR |
4560 | void kvm_enable_tdp(void) |
4561 | { | |
4562 | tdp_enabled = true; | |
4563 | } | |
4564 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
4565 | ||
5f4cb662 JR |
4566 | void kvm_disable_tdp(void) |
4567 | { | |
4568 | tdp_enabled = false; | |
4569 | } | |
4570 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
4571 | ||
6aa8b732 AK |
4572 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
4573 | { | |
ad312c7c | 4574 | free_page((unsigned long)vcpu->arch.mmu.pae_root); |
81407ca5 JR |
4575 | if (vcpu->arch.mmu.lm_root != NULL) |
4576 | free_page((unsigned long)vcpu->arch.mmu.lm_root); | |
6aa8b732 AK |
4577 | } |
4578 | ||
4579 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
4580 | { | |
17ac10ad | 4581 | struct page *page; |
6aa8b732 AK |
4582 | int i; |
4583 | ||
17ac10ad AK |
4584 | /* |
4585 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
4586 | * Therefore we need to allocate shadow page tables in the first | |
4587 | * 4GB of memory, which happens to fit the DMA32 zone. | |
4588 | */ | |
4589 | page = alloc_page(GFP_KERNEL | __GFP_DMA32); | |
4590 | if (!page) | |
d7fa6ab2 WY |
4591 | return -ENOMEM; |
4592 | ||
ad312c7c | 4593 | vcpu->arch.mmu.pae_root = page_address(page); |
17ac10ad | 4594 | for (i = 0; i < 4; ++i) |
ad312c7c | 4595 | vcpu->arch.mmu.pae_root[i] = INVALID_PAGE; |
17ac10ad | 4596 | |
6aa8b732 | 4597 | return 0; |
6aa8b732 AK |
4598 | } |
4599 | ||
8018c27b | 4600 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 4601 | { |
e459e322 XG |
4602 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; |
4603 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; | |
4604 | vcpu->arch.mmu.translate_gpa = translate_gpa; | |
4605 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; | |
6aa8b732 | 4606 | |
8018c27b IM |
4607 | return alloc_mmu_pages(vcpu); |
4608 | } | |
6aa8b732 | 4609 | |
8a3c1a33 | 4610 | void kvm_mmu_setup(struct kvm_vcpu *vcpu) |
8018c27b | 4611 | { |
fa4a2c08 | 4612 | MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa)); |
2c264957 | 4613 | |
8a3c1a33 | 4614 | init_kvm_mmu(vcpu); |
6aa8b732 AK |
4615 | } |
4616 | ||
13d268ca XG |
4617 | void kvm_mmu_init_vm(struct kvm *kvm) |
4618 | { | |
4619 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4620 | ||
4621 | node->track_write = kvm_mmu_pte_write; | |
4622 | kvm_page_track_register_notifier(kvm, node); | |
4623 | } | |
4624 | ||
4625 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
4626 | { | |
4627 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
4628 | ||
4629 | kvm_page_track_unregister_notifier(kvm, node); | |
4630 | } | |
4631 | ||
1bad2b2a | 4632 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 4633 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
4634 | |
4635 | /* The caller should hold mmu-lock before calling this function. */ | |
4636 | static bool | |
4637 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4638 | slot_level_handler fn, int start_level, int end_level, | |
4639 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
4640 | { | |
4641 | struct slot_rmap_walk_iterator iterator; | |
4642 | bool flush = false; | |
4643 | ||
4644 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
4645 | end_gfn, &iterator) { | |
4646 | if (iterator.rmap) | |
4647 | flush |= fn(kvm, iterator.rmap); | |
4648 | ||
4649 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
4650 | if (flush && lock_flush_tlb) { | |
4651 | kvm_flush_remote_tlbs(kvm); | |
4652 | flush = false; | |
4653 | } | |
4654 | cond_resched_lock(&kvm->mmu_lock); | |
4655 | } | |
4656 | } | |
4657 | ||
4658 | if (flush && lock_flush_tlb) { | |
4659 | kvm_flush_remote_tlbs(kvm); | |
4660 | flush = false; | |
4661 | } | |
4662 | ||
4663 | return flush; | |
4664 | } | |
4665 | ||
4666 | static bool | |
4667 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4668 | slot_level_handler fn, int start_level, int end_level, | |
4669 | bool lock_flush_tlb) | |
4670 | { | |
4671 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
4672 | end_level, memslot->base_gfn, | |
4673 | memslot->base_gfn + memslot->npages - 1, | |
4674 | lock_flush_tlb); | |
4675 | } | |
4676 | ||
4677 | static bool | |
4678 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4679 | slot_level_handler fn, bool lock_flush_tlb) | |
4680 | { | |
4681 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4682 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4683 | } | |
4684 | ||
4685 | static bool | |
4686 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4687 | slot_level_handler fn, bool lock_flush_tlb) | |
4688 | { | |
4689 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
4690 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
4691 | } | |
4692 | ||
4693 | static bool | |
4694 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, | |
4695 | slot_level_handler fn, bool lock_flush_tlb) | |
4696 | { | |
4697 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
4698 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
4699 | } | |
4700 | ||
efdfe536 XG |
4701 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
4702 | { | |
4703 | struct kvm_memslots *slots; | |
4704 | struct kvm_memory_slot *memslot; | |
9da0e4d5 | 4705 | int i; |
efdfe536 XG |
4706 | |
4707 | spin_lock(&kvm->mmu_lock); | |
9da0e4d5 PB |
4708 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
4709 | slots = __kvm_memslots(kvm, i); | |
4710 | kvm_for_each_memslot(memslot, slots) { | |
4711 | gfn_t start, end; | |
4712 | ||
4713 | start = max(gfn_start, memslot->base_gfn); | |
4714 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
4715 | if (start >= end) | |
4716 | continue; | |
efdfe536 | 4717 | |
9da0e4d5 PB |
4718 | slot_handle_level_range(kvm, memslot, kvm_zap_rmapp, |
4719 | PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL, | |
4720 | start, end - 1, true); | |
4721 | } | |
efdfe536 XG |
4722 | } |
4723 | ||
4724 | spin_unlock(&kvm->mmu_lock); | |
4725 | } | |
4726 | ||
018aabb5 TY |
4727 | static bool slot_rmap_write_protect(struct kvm *kvm, |
4728 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 4729 | { |
018aabb5 | 4730 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
4731 | } |
4732 | ||
1c91cad4 KH |
4733 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
4734 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 4735 | { |
d77aa73c | 4736 | bool flush; |
6aa8b732 | 4737 | |
9d1beefb | 4738 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
4739 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
4740 | false); | |
9d1beefb | 4741 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
4742 | |
4743 | /* | |
4744 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
4745 | * which do tlb flush out of mmu-lock should be serialized by | |
4746 | * kvm->slots_lock otherwise tlb flush would be missed. | |
4747 | */ | |
4748 | lockdep_assert_held(&kvm->slots_lock); | |
4749 | ||
4750 | /* | |
4751 | * We can flush all the TLBs out of the mmu lock without TLB | |
4752 | * corruption since we just change the spte from writable to | |
4753 | * readonly so that we only need to care the case of changing | |
4754 | * spte from present to present (changing the spte from present | |
4755 | * to nonpresent will flush all the TLBs immediately), in other | |
4756 | * words, the only case we care is mmu_spte_update() where we | |
4757 | * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE | |
4758 | * instead of PT_WRITABLE_MASK, that means it does not depend | |
4759 | * on PT_WRITABLE_MASK anymore. | |
4760 | */ | |
d91ffee9 KH |
4761 | if (flush) |
4762 | kvm_flush_remote_tlbs(kvm); | |
6aa8b732 | 4763 | } |
37a7d8b0 | 4764 | |
3ea3b7fa | 4765 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 4766 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
4767 | { |
4768 | u64 *sptep; | |
4769 | struct rmap_iterator iter; | |
4770 | int need_tlb_flush = 0; | |
ba049e93 | 4771 | kvm_pfn_t pfn; |
3ea3b7fa WL |
4772 | struct kvm_mmu_page *sp; |
4773 | ||
0d536790 | 4774 | restart: |
018aabb5 | 4775 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
4776 | sp = page_header(__pa(sptep)); |
4777 | pfn = spte_to_pfn(*sptep); | |
4778 | ||
4779 | /* | |
decf6333 XG |
4780 | * We cannot do huge page mapping for indirect shadow pages, |
4781 | * which are found on the last rmap (level = 1) when not using | |
4782 | * tdp; such shadow pages are synced with the page table in | |
4783 | * the guest, and the guest page table is using 4K page size | |
4784 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
4785 | */ |
4786 | if (sp->role.direct && | |
4787 | !kvm_is_reserved_pfn(pfn) && | |
4788 | PageTransCompound(pfn_to_page(pfn))) { | |
4789 | drop_spte(kvm, sptep); | |
3ea3b7fa | 4790 | need_tlb_flush = 1; |
0d536790 XG |
4791 | goto restart; |
4792 | } | |
3ea3b7fa WL |
4793 | } |
4794 | ||
4795 | return need_tlb_flush; | |
4796 | } | |
4797 | ||
4798 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 4799 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 4800 | { |
f36f3f28 | 4801 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 4802 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
4803 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
4804 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
4805 | spin_unlock(&kvm->mmu_lock); |
4806 | } | |
4807 | ||
f4b4b180 KH |
4808 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
4809 | struct kvm_memory_slot *memslot) | |
4810 | { | |
d77aa73c | 4811 | bool flush; |
f4b4b180 KH |
4812 | |
4813 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 4814 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
4815 | spin_unlock(&kvm->mmu_lock); |
4816 | ||
4817 | lockdep_assert_held(&kvm->slots_lock); | |
4818 | ||
4819 | /* | |
4820 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
4821 | * function is only used for dirty logging, in which case flushing TLB | |
4822 | * out of mmu lock also guarantees no dirty pages will be lost in | |
4823 | * dirty_bitmap. | |
4824 | */ | |
4825 | if (flush) | |
4826 | kvm_flush_remote_tlbs(kvm); | |
4827 | } | |
4828 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
4829 | ||
4830 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
4831 | struct kvm_memory_slot *memslot) | |
4832 | { | |
d77aa73c | 4833 | bool flush; |
f4b4b180 KH |
4834 | |
4835 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
4836 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
4837 | false); | |
f4b4b180 KH |
4838 | spin_unlock(&kvm->mmu_lock); |
4839 | ||
4840 | /* see kvm_mmu_slot_remove_write_access */ | |
4841 | lockdep_assert_held(&kvm->slots_lock); | |
4842 | ||
4843 | if (flush) | |
4844 | kvm_flush_remote_tlbs(kvm); | |
4845 | } | |
4846 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
4847 | ||
4848 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
4849 | struct kvm_memory_slot *memslot) | |
4850 | { | |
d77aa73c | 4851 | bool flush; |
f4b4b180 KH |
4852 | |
4853 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 4854 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
4855 | spin_unlock(&kvm->mmu_lock); |
4856 | ||
4857 | lockdep_assert_held(&kvm->slots_lock); | |
4858 | ||
4859 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
4860 | if (flush) | |
4861 | kvm_flush_remote_tlbs(kvm); | |
4862 | } | |
4863 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
4864 | ||
e7d11c7a | 4865 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
4866 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
4867 | { | |
4868 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 4869 | int batch = 0; |
5304b8d3 XG |
4870 | |
4871 | restart: | |
4872 | list_for_each_entry_safe_reverse(sp, node, | |
4873 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
4874 | int ret; |
4875 | ||
5304b8d3 XG |
4876 | /* |
4877 | * No obsolete page exists before new created page since | |
4878 | * active_mmu_pages is the FIFO list. | |
4879 | */ | |
4880 | if (!is_obsolete_sp(kvm, sp)) | |
4881 | break; | |
4882 | ||
4883 | /* | |
5304b8d3 XG |
4884 | * Since we are reversely walking the list and the invalid |
4885 | * list will be moved to the head, skip the invalid page | |
4886 | * can help us to avoid the infinity list walking. | |
4887 | */ | |
4888 | if (sp->role.invalid) | |
4889 | continue; | |
4890 | ||
f34d251d XG |
4891 | /* |
4892 | * Need not flush tlb since we only zap the sp with invalid | |
4893 | * generation number. | |
4894 | */ | |
e7d11c7a | 4895 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 4896 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 4897 | batch = 0; |
5304b8d3 XG |
4898 | goto restart; |
4899 | } | |
4900 | ||
365c8868 XG |
4901 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
4902 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
4903 | batch += ret; |
4904 | ||
4905 | if (ret) | |
5304b8d3 XG |
4906 | goto restart; |
4907 | } | |
4908 | ||
f34d251d XG |
4909 | /* |
4910 | * Should flush tlb before free page tables since lockless-walking | |
4911 | * may use the pages. | |
4912 | */ | |
365c8868 | 4913 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
4914 | } |
4915 | ||
4916 | /* | |
4917 | * Fast invalidate all shadow pages and use lock-break technique | |
4918 | * to zap obsolete pages. | |
4919 | * | |
4920 | * It's required when memslot is being deleted or VM is being | |
4921 | * destroyed, in these cases, we should ensure that KVM MMU does | |
4922 | * not use any resource of the being-deleted slot or all slots | |
4923 | * after calling the function. | |
4924 | */ | |
4925 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
4926 | { | |
4927 | spin_lock(&kvm->mmu_lock); | |
35006126 | 4928 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
4929 | kvm->arch.mmu_valid_gen++; |
4930 | ||
f34d251d XG |
4931 | /* |
4932 | * Notify all vcpus to reload its shadow page table | |
4933 | * and flush TLB. Then all vcpus will switch to new | |
4934 | * shadow page table with the new mmu_valid_gen. | |
4935 | * | |
4936 | * Note: we should do this under the protection of | |
4937 | * mmu-lock, otherwise, vcpu would purge shadow page | |
4938 | * but miss tlb flush. | |
4939 | */ | |
4940 | kvm_reload_remote_mmus(kvm); | |
4941 | ||
5304b8d3 XG |
4942 | kvm_zap_obsolete_pages(kvm); |
4943 | spin_unlock(&kvm->mmu_lock); | |
4944 | } | |
4945 | ||
365c8868 XG |
4946 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
4947 | { | |
4948 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
4949 | } | |
4950 | ||
54bf36aa | 4951 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots) |
f8f55942 XG |
4952 | { |
4953 | /* | |
4954 | * The very rare case: if the generation-number is round, | |
4955 | * zap all shadow pages. | |
f8f55942 | 4956 | */ |
54bf36aa | 4957 | if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) { |
a629df7e | 4958 | printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 4959 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 4960 | } |
f8f55942 XG |
4961 | } |
4962 | ||
70534a73 DC |
4963 | static unsigned long |
4964 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
4965 | { |
4966 | struct kvm *kvm; | |
1495f230 | 4967 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 4968 | unsigned long freed = 0; |
3ee16c81 | 4969 | |
2f303b74 | 4970 | spin_lock(&kvm_lock); |
3ee16c81 IE |
4971 | |
4972 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 4973 | int idx; |
d98ba053 | 4974 | LIST_HEAD(invalid_list); |
3ee16c81 | 4975 | |
35f2d16b TY |
4976 | /* |
4977 | * Never scan more than sc->nr_to_scan VM instances. | |
4978 | * Will not hit this condition practically since we do not try | |
4979 | * to shrink more than one VM and it is very unlikely to see | |
4980 | * !n_used_mmu_pages so many times. | |
4981 | */ | |
4982 | if (!nr_to_scan--) | |
4983 | break; | |
19526396 GN |
4984 | /* |
4985 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
4986 | * here. We may skip a VM instance errorneosly, but we do not | |
4987 | * want to shrink a VM that only started to populate its MMU | |
4988 | * anyway. | |
4989 | */ | |
365c8868 XG |
4990 | if (!kvm->arch.n_used_mmu_pages && |
4991 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 4992 | continue; |
19526396 | 4993 | |
f656ce01 | 4994 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 4995 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 4996 | |
365c8868 XG |
4997 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
4998 | kvm_mmu_commit_zap_page(kvm, | |
4999 | &kvm->arch.zapped_obsolete_pages); | |
5000 | goto unlock; | |
5001 | } | |
5002 | ||
70534a73 DC |
5003 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5004 | freed++; | |
d98ba053 | 5005 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5006 | |
365c8868 | 5007 | unlock: |
3ee16c81 | 5008 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5009 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5010 | |
70534a73 DC |
5011 | /* |
5012 | * unfair on small ones | |
5013 | * per-vm shrinkers cry out | |
5014 | * sadness comes quickly | |
5015 | */ | |
19526396 GN |
5016 | list_move_tail(&kvm->vm_list, &vm_list); |
5017 | break; | |
3ee16c81 | 5018 | } |
3ee16c81 | 5019 | |
2f303b74 | 5020 | spin_unlock(&kvm_lock); |
70534a73 | 5021 | return freed; |
70534a73 DC |
5022 | } |
5023 | ||
5024 | static unsigned long | |
5025 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5026 | { | |
45221ab6 | 5027 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5028 | } |
5029 | ||
5030 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5031 | .count_objects = mmu_shrink_count, |
5032 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5033 | .seeks = DEFAULT_SEEKS * 10, |
5034 | }; | |
5035 | ||
2ddfd20e | 5036 | static void mmu_destroy_caches(void) |
b5a33a75 | 5037 | { |
53c07b18 XG |
5038 | if (pte_list_desc_cache) |
5039 | kmem_cache_destroy(pte_list_desc_cache); | |
d3d25b04 AK |
5040 | if (mmu_page_header_cache) |
5041 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
5042 | } |
5043 | ||
5044 | int kvm_mmu_module_init(void) | |
5045 | { | |
53c07b18 XG |
5046 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
5047 | sizeof(struct pte_list_desc), | |
20c2df83 | 5048 | 0, 0, NULL); |
53c07b18 | 5049 | if (!pte_list_desc_cache) |
b5a33a75 AK |
5050 | goto nomem; |
5051 | ||
d3d25b04 AK |
5052 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
5053 | sizeof(struct kvm_mmu_page), | |
20c2df83 | 5054 | 0, 0, NULL); |
d3d25b04 AK |
5055 | if (!mmu_page_header_cache) |
5056 | goto nomem; | |
5057 | ||
908c7f19 | 5058 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
45bf21a8 WY |
5059 | goto nomem; |
5060 | ||
3ee16c81 IE |
5061 | register_shrinker(&mmu_shrinker); |
5062 | ||
b5a33a75 AK |
5063 | return 0; |
5064 | ||
5065 | nomem: | |
3ee16c81 | 5066 | mmu_destroy_caches(); |
b5a33a75 AK |
5067 | return -ENOMEM; |
5068 | } | |
5069 | ||
3ad82a7e ZX |
5070 | /* |
5071 | * Caculate mmu pages needed for kvm. | |
5072 | */ | |
5073 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
5074 | { | |
3ad82a7e ZX |
5075 | unsigned int nr_mmu_pages; |
5076 | unsigned int nr_pages = 0; | |
bc6678a3 | 5077 | struct kvm_memslots *slots; |
be6ba0f0 | 5078 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 5079 | int i; |
3ad82a7e | 5080 | |
9da0e4d5 PB |
5081 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5082 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 5083 | |
9da0e4d5 PB |
5084 | kvm_for_each_memslot(memslot, slots) |
5085 | nr_pages += memslot->npages; | |
5086 | } | |
3ad82a7e ZX |
5087 | |
5088 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
5089 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 5090 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
5091 | |
5092 | return nr_mmu_pages; | |
5093 | } | |
5094 | ||
c42fffe3 XG |
5095 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
5096 | { | |
95f93af4 | 5097 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
5098 | free_mmu_pages(vcpu); |
5099 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
5100 | } |
5101 | ||
b034cf01 XG |
5102 | void kvm_mmu_module_exit(void) |
5103 | { | |
5104 | mmu_destroy_caches(); | |
5105 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
5106 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
5107 | mmu_audit_disable(); |
5108 | } |