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KVM: MMU: use proper cache object freeing function
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
836a1b3c 21#include "x86.h"
6de4f3ad 22#include "kvm_cache_regs.h"
e495606d 23
edf88417 24#include <linux/kvm_host.h>
6aa8b732
AK		 25#include <linux/types.h>
26#include <linux/string.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
29#include <linux/module.h>
448353ca 30#include <linux/swap.h>
05da4558 31#include <linux/hugetlb.h>
2f333bcb 32#include <linux/compiler.h>
bc6678a3 33#include <linux/srcu.h>
5a0e3ad6 34#include <linux/slab.h>
bf998156 35#include <linux/uaccess.h>
6aa8b732 36
e495606d
AK		 37#include <asm/page.h>
38#include <asm/cmpxchg.h>
4e542370 39#include <asm/io.h>
13673a90 40#include <asm/vmx.h>
6aa8b732 41
18552672
JR		 42/*
43 * When setting this variable to true it enables Two-Dimensional-Paging
44 * where the hardware walks 2 page tables:
45 * 1. the guest-virtual to guest-physical
46 * 2. while doing 1. it walks guest-physical to host-physical
47 * If the hardware supports that we don't need to do shadow paging.
48 */
2f333bcb 49bool tdp_enabled = false;
18552672 50
37a7d8b0
AK		 51#undef MMU_DEBUG
52
53#undef AUDIT
54
55#ifdef AUDIT
56static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
57#else
58static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
59#endif
60
61#ifdef MMU_DEBUG
62
63#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
64#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
65
66#else
67
68#define pgprintk(x...) do { } while (0)
69#define rmap_printk(x...) do { } while (0)
70
71#endif
72
73#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 74static int dbg = 0;
75module_param(dbg, bool, 0644);
37a7d8b0 76#endif
6aa8b732 77
582801a9
MT		 78static int oos_shadow = 1;
79module_param(oos_shadow, bool, 0644);
80
d6c69ee9
YD		 81#ifndef MMU_DEBUG
82#define ASSERT(x) do { } while (0)
83#else
6aa8b732
AK		 84#define ASSERT(x) \
85 if (!(x)) { \
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
88 }
d6c69ee9 89#endif
6aa8b732 90
6aa8b732
AK		 91#define PT_FIRST_AVAIL_BITS_SHIFT 9
92#define PT64_SECOND_AVAIL_BITS_SHIFT 52
93
6aa8b732
AK		 94#define VALID_PAGE(x) ((x) != INVALID_PAGE)
95
96#define PT64_LEVEL_BITS 9
97
98#define PT64_LEVEL_SHIFT(level) \
d77c26fc 99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 100
101#define PT64_LEVEL_MASK(level) \
102 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
103
104#define PT64_INDEX(address, level)\
105 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
106
107
108#define PT32_LEVEL_BITS 10
109
110#define PT32_LEVEL_SHIFT(level) \
d77c26fc 111 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 112
113#define PT32_LEVEL_MASK(level) \
114 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 115#define PT32_LVL_OFFSET_MASK(level) \
116 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 118
119#define PT32_INDEX(address, level)\
120 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
121
122
27aba766 123#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 124#define PT64_DIR_BASE_ADDR_MASK \
125 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 126#define PT64_LVL_ADDR_MASK(level) \
127 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
128 * PT64_LEVEL_BITS))) - 1))
129#define PT64_LVL_OFFSET_MASK(level) \
130 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
131 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 132
133#define PT32_BASE_ADDR_MASK PAGE_MASK
134#define PT32_DIR_BASE_ADDR_MASK \
135 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 136#define PT32_LVL_ADDR_MASK(level) \
137 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT32_LEVEL_BITS))) - 1))
6aa8b732 139
79539cec
AK		 140#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
141 | PT64_NX_MASK)
6aa8b732 142
cd4a4e53
AK		 143#define RMAP_EXT 4
144
fe135d2c
AK		 145#define ACC_EXEC_MASK 1
146#define ACC_WRITE_MASK PT_WRITABLE_MASK
147#define ACC_USER_MASK PT_USER_MASK
148#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
149
90bb6fc5
AK		 150#include <trace/events/kvm.h>
151
07420171
AK		 152#define CREATE_TRACE_POINTS
153#include "mmutrace.h"
154
1403283a
IE		 155#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
156
135f8c2b
AK		 157#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
158
cd4a4e53 159struct kvm_rmap_desc {
d555c333 160 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 161 struct kvm_rmap_desc *more;
162};
163
2d11123a
AK		 164struct kvm_shadow_walk_iterator {
165 u64 addr;
166 hpa_t shadow_addr;
167 int level;
168 u64 *sptep;
169 unsigned index;
170};
171
172#define for_each_shadow_entry(_vcpu, _addr, _walker) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
176
6b18493d 177typedef int (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp);
ad8cfbe3 178
b5a33a75
AK		 179static struct kmem_cache *pte_chain_cache;
180static struct kmem_cache *rmap_desc_cache;
d3d25b04 181static struct kmem_cache *mmu_page_header_cache;
b5a33a75 182
c7addb90
AK		 183static u64 __read_mostly shadow_trap_nonpresent_pte;
184static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 185static u64 __read_mostly shadow_base_present_pte;
186static u64 __read_mostly shadow_nx_mask;
187static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
188static u64 __read_mostly shadow_user_mask;
189static u64 __read_mostly shadow_accessed_mask;
190static u64 __read_mostly shadow_dirty_mask;
c7addb90 191
82725b20
DE		 192static inline u64 rsvd_bits(int s, int e)
193{
194 return ((1ULL << (e - s + 1)) - 1) << s;
195}
196
c7addb90
AK		 197void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
198{
199 shadow_trap_nonpresent_pte = trap_pte;
200 shadow_notrap_nonpresent_pte = notrap_pte;
201}
202EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
203
7b52345e
SY		 204void kvm_mmu_set_base_ptes(u64 base_pte)
205{
206 shadow_base_present_pte = base_pte;
207}
208EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
209
210void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 211 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 212{
213 shadow_user_mask = user_mask;
214 shadow_accessed_mask = accessed_mask;
215 shadow_dirty_mask = dirty_mask;
216 shadow_nx_mask = nx_mask;
217 shadow_x_mask = x_mask;
218}
219EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
220
3dbe1415 221static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 222{
4d4ec087 223 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 224}
225
226static int is_cpuid_PSE36(void)
227{
228 return 1;
229}
230
73b1087e
AK		 231static int is_nx(struct kvm_vcpu *vcpu)
232{
f6801dff 233 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 234}
235
c7addb90
AK		 236static int is_shadow_present_pte(u64 pte)
237{
c7addb90
AK		 238 return pte != shadow_trap_nonpresent_pte
239 && pte != shadow_notrap_nonpresent_pte;
240}
241
05da4558
MT		 242static int is_large_pte(u64 pte)
243{
244 return pte & PT_PAGE_SIZE_MASK;
245}
246
8dae4445 247static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 248{
249 return pte & PT_WRITABLE_MASK;
250}
251
43a3795a 252static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 253{
439e218a 254 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 255}
256
43a3795a 257static int is_rmap_spte(u64 pte)
cd4a4e53 258{
4b1a80fa 259 return is_shadow_present_pte(pte);
cd4a4e53
AK		 260}
261
776e6633
MT		 262static int is_last_spte(u64 pte, int level)
263{
264 if (level == PT_PAGE_TABLE_LEVEL)
265 return 1;
852e3c19 266 if (is_large_pte(pte))
776e6633
MT		 267 return 1;
268 return 0;
269}
270
35149e21 271static pfn_t spte_to_pfn(u64 pte)
0b49ea86 272{
35149e21 273 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 274}
275
da928521
AK		 276static gfn_t pse36_gfn_delta(u32 gpte)
277{
278 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
279
280 return (gpte & PT32_DIR_PSE36_MASK) << shift;
281}
282
d555c333 283static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 284{
285#ifdef CONFIG_X86_64
286 set_64bit((unsigned long *)sptep, spte);
287#else
288 set_64bit((unsigned long long *)sptep, spte);
289#endif
290}
291
e2dec939 292static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 293 struct kmem_cache *base_cache, int min)
714b93da
AK		 294{
295 void *obj;
296
297 if (cache->nobjs >= min)
e2dec939 298 return 0;
714b93da 299 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 300 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 301 if (!obj)
e2dec939 302 return -ENOMEM;
714b93da
AK		 303 cache->objects[cache->nobjs++] = obj;
304 }
e2dec939 305 return 0;
714b93da
AK		 306}
307
e8ad9a70
XG		 308static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
309 struct kmem_cache *cache)
714b93da
AK		 310{
311 while (mc->nobjs)
e8ad9a70 312 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
AK		 313}
314
c1158e63 315static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 316 int min)
c1158e63
AK		 317{
318 struct page *page;
319
320 if (cache->nobjs >= min)
321 return 0;
322 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 323 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 324 if (!page)
325 return -ENOMEM;
c1158e63
AK		 326 cache->objects[cache->nobjs++] = page_address(page);
327 }
328 return 0;
329}
330
331static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
332{
333 while (mc->nobjs)
c4d198d5 334 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 335}
336
2e3e5882 337static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 338{
e2dec939
AK		 339 int r;
340
ad312c7c 341 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 342 pte_chain_cache, 4);
e2dec939
AK		 343 if (r)
344 goto out;
ad312c7c 345 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 346 rmap_desc_cache, 4);
d3d25b04
AK		 347 if (r)
348 goto out;
ad312c7c 349 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 350 if (r)
351 goto out;
ad312c7c 352 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 353 mmu_page_header_cache, 4);
e2dec939
AK		 354out:
355 return r;
714b93da
AK		 356}
357
358static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
359{
e8ad9a70
XG		 360 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
361 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
ad312c7c 362 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG		 363 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
364 mmu_page_header_cache);
714b93da
AK		 365}
366
367static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
368 size_t size)
369{
370 void *p;
371
372 BUG_ON(!mc->nobjs);
373 p = mc->objects[--mc->nobjs];
714b93da
AK		 374 return p;
375}
376
714b93da
AK		 377static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
378{
ad312c7c 379 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 380 sizeof(struct kvm_pte_chain));
381}
382
90cb0529 383static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 384{
e8ad9a70 385 kmem_cache_free(pte_chain_cache, pc);
714b93da
AK		 386}
387
388static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
389{
ad312c7c 390 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 391 sizeof(struct kvm_rmap_desc));
392}
393
90cb0529 394static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 395{
e8ad9a70 396 kmem_cache_free(rmap_desc_cache, rd);
714b93da
AK		 397}
398
05da4558
MT		 399/*
400 * Return the pointer to the largepage write count for a given
401 * gfn, handling slots that are not large page aligned.
402 */
d25797b2
JR		 403static int *slot_largepage_idx(gfn_t gfn,
404 struct kvm_memory_slot *slot,
405 int level)
05da4558
MT		 406{
407 unsigned long idx;
408
d25797b2
JR		 409 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
410 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
411 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 412}
413
414static void account_shadowed(struct kvm *kvm, gfn_t gfn)
415{
d25797b2 416 struct kvm_memory_slot *slot;
05da4558 417 int *write_count;
d25797b2 418 int i;
05da4558 419
2843099f 420 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 421
422 slot = gfn_to_memslot_unaliased(kvm, gfn);
423 for (i = PT_DIRECTORY_LEVEL;
424 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
425 write_count = slot_largepage_idx(gfn, slot, i);
426 *write_count += 1;
427 }
05da4558
MT		 428}
429
430static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
431{
d25797b2 432 struct kvm_memory_slot *slot;
05da4558 433 int *write_count;
d25797b2 434 int i;
05da4558 435
2843099f 436 gfn = unalias_gfn(kvm, gfn);
77a1a715 437 slot = gfn_to_memslot_unaliased(kvm, gfn);
d25797b2
JR		 438 for (i = PT_DIRECTORY_LEVEL;
439 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d25797b2
JR		 440 write_count = slot_largepage_idx(gfn, slot, i);
441 *write_count -= 1;
442 WARN_ON(*write_count < 0);
443 }
05da4558
MT		 444}
445
d25797b2
JR		 446static int has_wrprotected_page(struct kvm *kvm,
447 gfn_t gfn,
448 int level)
05da4558 449{
2843099f 450 struct kvm_memory_slot *slot;
05da4558
MT		 451 int *largepage_idx;
452
2843099f
IE		 453 gfn = unalias_gfn(kvm, gfn);
454 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 455 if (slot) {
d25797b2 456 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 457 return *largepage_idx;
458 }
459
460 return 1;
461}
462
d25797b2 463static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 464{
8f0b1ab6 465 unsigned long page_size;
d25797b2 466 int i, ret = 0;
05da4558 467
8f0b1ab6 468 page_size = kvm_host_page_size(kvm, gfn);
05da4558 469
d25797b2
JR		 470 for (i = PT_PAGE_TABLE_LEVEL;
471 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
472 if (page_size >= KVM_HPAGE_SIZE(i))
473 ret = i;
474 else
475 break;
476 }
477
4c2155ce 478 return ret;
05da4558
MT		 479}
480
d25797b2 481static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 482{
483 struct kvm_memory_slot *slot;
878403b7 484 int host_level, level, max_level;
05da4558
MT		 485
486 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
487 if (slot && slot->dirty_bitmap)
d25797b2 488 return PT_PAGE_TABLE_LEVEL;
05da4558 489
d25797b2
JR		 490 host_level = host_mapping_level(vcpu->kvm, large_gfn);
491
492 if (host_level == PT_PAGE_TABLE_LEVEL)
493 return host_level;
494
878403b7
SY		 495 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
496 kvm_x86_ops->get_lpage_level() : host_level;
497
498 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 499 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
500 break;
d25797b2
JR		 501
502 return level - 1;
05da4558
MT		 503}
504
290fc38d
IE		 505/*
506 * Take gfn and return the reverse mapping to it.
507 * Note: gfn must be unaliased before this function get called
508 */
509
44ad9944 510static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 511{
512 struct kvm_memory_slot *slot;
05da4558 513 unsigned long idx;
290fc38d
IE		 514
515 slot = gfn_to_memslot(kvm, gfn);
44ad9944 516 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 517 return &slot->rmap[gfn - slot->base_gfn];
518
44ad9944
JR		 519 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
520 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 521
44ad9944 522 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 523}
524
cd4a4e53
AK		 525/*
526 * Reverse mapping data structures:
527 *
290fc38d
IE		 528 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
529 * that points to page_address(page).
cd4a4e53 530 *
290fc38d
IE		 531 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
532 * containing more mappings.
53a27b39
MT		 533 *
534 * Returns the number of rmap entries before the spte was added or zero if
535 * the spte was not added.
536 *
cd4a4e53 537 */
44ad9944 538static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 539{
4db35314 540 struct kvm_mmu_page *sp;
cd4a4e53 541 struct kvm_rmap_desc *desc;
290fc38d 542 unsigned long *rmapp;
53a27b39 543 int i, count = 0;
cd4a4e53 544
43a3795a 545 if (!is_rmap_spte(*spte))
53a27b39 546 return count;
290fc38d 547 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 548 sp = page_header(__pa(spte));
549 sp->gfns[spte - sp->spt] = gfn;
44ad9944 550 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 551 if (!*rmapp) {
cd4a4e53 552 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 553 *rmapp = (unsigned long)spte;
554 } else if (!(*rmapp & 1)) {
cd4a4e53 555 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 556 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 557 desc->sptes[0] = (u64 *)*rmapp;
558 desc->sptes[1] = spte;
290fc38d 559 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 560 } else {
561 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 562 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 563 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 564 desc = desc->more;
53a27b39
MT		 565 count += RMAP_EXT;
566 }
d555c333 567 if (desc->sptes[RMAP_EXT-1]) {
714b93da 568 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 569 desc = desc->more;
570 }
d555c333 571 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 572 ;
d555c333 573 desc->sptes[i] = spte;
cd4a4e53 574 }
53a27b39 575 return count;
cd4a4e53
AK		 576}
577
290fc38d 578static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 579 struct kvm_rmap_desc *desc,
580 int i,
581 struct kvm_rmap_desc *prev_desc)
582{
583 int j;
584
d555c333 585 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 586 ;
d555c333
AK		 587 desc->sptes[i] = desc->sptes[j];
588 desc->sptes[j] = NULL;
cd4a4e53
AK		 589 if (j != 0)
590 return;
591 if (!prev_desc && !desc->more)
d555c333 592 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 593 else
594 if (prev_desc)
595 prev_desc->more = desc->more;
596 else
290fc38d 597 *rmapp = (unsigned long)desc->more | 1;
90cb0529 598 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 599}
600
290fc38d 601static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 602{
cd4a4e53
AK		 603 struct kvm_rmap_desc *desc;
604 struct kvm_rmap_desc *prev_desc;
4db35314 605 struct kvm_mmu_page *sp;
35149e21 606 pfn_t pfn;
290fc38d 607 unsigned long *rmapp;
cd4a4e53
AK		 608 int i;
609
43a3795a 610 if (!is_rmap_spte(*spte))
cd4a4e53 611 return;
4db35314 612 sp = page_header(__pa(spte));
35149e21 613 pfn = spte_to_pfn(*spte);
7b52345e 614 if (*spte & shadow_accessed_mask)
35149e21 615 kvm_set_pfn_accessed(pfn);
8dae4445 616 if (is_writable_pte(*spte))
acb66dd0 617 kvm_set_pfn_dirty(pfn);
44ad9944 618 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 619 if (!*rmapp) {
cd4a4e53
AK		 620 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
621 BUG();
290fc38d 622 } else if (!(*rmapp & 1)) {
cd4a4e53 623 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 624 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 625 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
626 spte, *spte);
627 BUG();
628 }
290fc38d 629 *rmapp = 0;
cd4a4e53
AK		 630 } else {
631 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 632 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 633 prev_desc = NULL;
634 while (desc) {
d555c333
AK		 635 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
636 if (desc->sptes[i] == spte) {
290fc38d 637 rmap_desc_remove_entry(rmapp,
714b93da 638 desc, i,
cd4a4e53
AK		 639 prev_desc);
640 return;
641 }
642 prev_desc = desc;
643 desc = desc->more;
644 }
186a3e52 645 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
cd4a4e53
AK		 646 BUG();
647 }
648}
649
98348e95 650static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 651{
374cbac0 652 struct kvm_rmap_desc *desc;
98348e95
IE		 653 u64 *prev_spte;
654 int i;
655
656 if (!*rmapp)
657 return NULL;
658 else if (!(*rmapp & 1)) {
659 if (!spte)
660 return (u64 *)*rmapp;
661 return NULL;
662 }
663 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
98348e95
IE		 664 prev_spte = NULL;
665 while (desc) {
d555c333 666 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 667 if (prev_spte == spte)
d555c333
AK		 668 return desc->sptes[i];
669 prev_spte = desc->sptes[i];
98348e95
IE		 670 }
671 desc = desc->more;
672 }
673 return NULL;
674}
675
b1a36821 676static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 677{
290fc38d 678 unsigned long *rmapp;
374cbac0 679 u64 *spte;
44ad9944 680 int i, write_protected = 0;
374cbac0 681
4a4c9924 682 gfn = unalias_gfn(kvm, gfn);
44ad9944 683 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 684
98348e95
IE		 685 spte = rmap_next(kvm, rmapp, NULL);
686 while (spte) {
374cbac0 687 BUG_ON(!spte);
374cbac0 688 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 689 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 690 if (is_writable_pte(*spte)) {
d555c333 691 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 692 write_protected = 1;
693 }
9647c14c 694 spte = rmap_next(kvm, rmapp, spte);
374cbac0 695 }
855149aa 696 if (write_protected) {
35149e21 697 pfn_t pfn;
855149aa
IE		 698
699 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 700 pfn = spte_to_pfn(*spte);
701 kvm_set_pfn_dirty(pfn);
855149aa
IE		 702 }
703
05da4558 704 /* check for huge page mappings */
44ad9944
JR		 705 for (i = PT_DIRECTORY_LEVEL;
706 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
707 rmapp = gfn_to_rmap(kvm, gfn, i);
708 spte = rmap_next(kvm, rmapp, NULL);
709 while (spte) {
710 BUG_ON(!spte);
711 BUG_ON(!(*spte & PT_PRESENT_MASK));
712 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
713 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 714 if (is_writable_pte(*spte)) {
44ad9944
JR		 715 rmap_remove(kvm, spte);
716 --kvm->stat.lpages;
717 __set_spte(spte, shadow_trap_nonpresent_pte);
718 spte = NULL;
719 write_protected = 1;
720 }
721 spte = rmap_next(kvm, rmapp, spte);
05da4558 722 }
05da4558
MT		 723 }
724
b1a36821 725 return write_protected;
374cbac0
AK		 726}
727
8a8365c5
FD		 728static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
729 unsigned long data)
e930bffe
AA		 730{
731 u64 *spte;
732 int need_tlb_flush = 0;
733
734 while ((spte = rmap_next(kvm, rmapp, NULL))) {
735 BUG_ON(!(*spte & PT_PRESENT_MASK));
736 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
737 rmap_remove(kvm, spte);
d555c333 738 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 739 need_tlb_flush = 1;
740 }
741 return need_tlb_flush;
742}
743
8a8365c5
FD		 744static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
745 unsigned long data)
3da0dd43
IE		 746{
747 int need_flush = 0;
748 u64 *spte, new_spte;
749 pte_t *ptep = (pte_t *)data;
750 pfn_t new_pfn;
751
752 WARN_ON(pte_huge(*ptep));
753 new_pfn = pte_pfn(*ptep);
754 spte = rmap_next(kvm, rmapp, NULL);
755 while (spte) {
756 BUG_ON(!is_shadow_present_pte(*spte));
757 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
758 need_flush = 1;
759 if (pte_write(*ptep)) {
760 rmap_remove(kvm, spte);
761 __set_spte(spte, shadow_trap_nonpresent_pte);
762 spte = rmap_next(kvm, rmapp, NULL);
763 } else {
764 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
765 new_spte |= (u64)new_pfn << PAGE_SHIFT;
766
767 new_spte &= ~PT_WRITABLE_MASK;
768 new_spte &= ~SPTE_HOST_WRITEABLE;
8dae4445 769 if (is_writable_pte(*spte))
3da0dd43
IE		 770 kvm_set_pfn_dirty(spte_to_pfn(*spte));
771 __set_spte(spte, new_spte);
772 spte = rmap_next(kvm, rmapp, spte);
773 }
774 }
775 if (need_flush)
776 kvm_flush_remote_tlbs(kvm);
777
778 return 0;
779}
780
8a8365c5
FD		 781static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
782 unsigned long data,
3da0dd43 783 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 784 unsigned long data))
e930bffe 785{
852e3c19 786 int i, j;
90bb6fc5 787 int ret;
e930bffe 788 int retval = 0;
bc6678a3
MT		 789 struct kvm_memslots *slots;
790
90d83dc3 791 slots = kvm_memslots(kvm);
e930bffe 792
46a26bf5
MT		 793 for (i = 0; i < slots->nmemslots; i++) {
794 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 795 unsigned long start = memslot->userspace_addr;
796 unsigned long end;
797
e930bffe
AA		 798 end = start + (memslot->npages << PAGE_SHIFT);
799 if (hva >= start && hva < end) {
800 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 801
90bb6fc5 802 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 803
804 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
805 int idx = gfn_offset;
806 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
90bb6fc5 807 ret |= handler(kvm,
3da0dd43
IE		 808 &memslot->lpage_info[j][idx].rmap_pde,
809 data);
852e3c19 810 }
90bb6fc5
AK		 811 trace_kvm_age_page(hva, memslot, ret);
812 retval |= ret;
e930bffe
AA		 813 }
814 }
815
816 return retval;
817}
818
819int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
820{
3da0dd43
IE		 821 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
822}
823
824void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
825{
8a8365c5 826 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 827}
828
8a8365c5
FD		 829static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
830 unsigned long data)
e930bffe
AA		 831{
832 u64 *spte;
833 int young = 0;
834
6316e1c8
RR		 835 /*
836 * Emulate the accessed bit for EPT, by checking if this page has
837 * an EPT mapping, and clearing it if it does. On the next access,
838 * a new EPT mapping will be established.
839 * This has some overhead, but not as much as the cost of swapping
840 * out actively used pages or breaking up actively used hugepages.
841 */
534e38b4 842 if (!shadow_accessed_mask)
6316e1c8 843 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 844
e930bffe
AA		 845 spte = rmap_next(kvm, rmapp, NULL);
846 while (spte) {
847 int _young;
848 u64 _spte = *spte;
849 BUG_ON(!(_spte & PT_PRESENT_MASK));
850 _young = _spte & PT_ACCESSED_MASK;
851 if (_young) {
852 young = 1;
853 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
854 }
855 spte = rmap_next(kvm, rmapp, spte);
856 }
857 return young;
858}
859
53a27b39
MT		 860#define RMAP_RECYCLE_THRESHOLD 1000
861
852e3c19 862static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 863{
864 unsigned long *rmapp;
852e3c19
JR		 865 struct kvm_mmu_page *sp;
866
867 sp = page_header(__pa(spte));
53a27b39
MT		 868
869 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 870 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 871
3da0dd43 872 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 873 kvm_flush_remote_tlbs(vcpu->kvm);
874}
875
e930bffe
AA		 876int kvm_age_hva(struct kvm *kvm, unsigned long hva)
877{
3da0dd43 878 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 879}
880
d6c69ee9 881#ifdef MMU_DEBUG
47ad8e68 882static int is_empty_shadow_page(u64 *spt)
6aa8b732 883{
139bdb2d
AK		 884 u64 *pos;
885 u64 *end;
886
47ad8e68 887 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 888 if (is_shadow_present_pte(*pos)) {
b8688d51 889 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 890 pos, *pos);
6aa8b732 891 return 0;
139bdb2d 892 }
6aa8b732
AK		 893 return 1;
894}
d6c69ee9 895#endif
6aa8b732 896
4db35314 897static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 898{
4db35314
AK		 899 ASSERT(is_empty_shadow_page(sp->spt));
900 list_del(&sp->link);
901 __free_page(virt_to_page(sp->spt));
902 __free_page(virt_to_page(sp->gfns));
e8ad9a70 903 kmem_cache_free(mmu_page_header_cache, sp);
f05e70ac 904 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 905}
906
cea0f0e7
AK		 907static unsigned kvm_page_table_hashfn(gfn_t gfn)
908{
1ae0a13d 909 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 910}
911
25c0de2c
AK		 912static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
913 u64 *parent_pte)
6aa8b732 914{
4db35314 915 struct kvm_mmu_page *sp;
6aa8b732 916
ad312c7c
ZX		 917 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
918 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
919 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 920 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 921 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
291f26bc 922 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 923 sp->multimapped = 0;
924 sp->parent_pte = parent_pte;
f05e70ac 925 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 926 return sp;
6aa8b732
AK		 927}
928
714b93da 929static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 930 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 931{
932 struct kvm_pte_chain *pte_chain;
933 struct hlist_node *node;
934 int i;
935
936 if (!parent_pte)
937 return;
4db35314
AK		 938 if (!sp->multimapped) {
939 u64 *old = sp->parent_pte;
cea0f0e7
AK		 940
941 if (!old) {
4db35314 942 sp->parent_pte = parent_pte;
cea0f0e7
AK		 943 return;
944 }
4db35314 945 sp->multimapped = 1;
714b93da 946 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 947 INIT_HLIST_HEAD(&sp->parent_ptes);
948 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 949 pte_chain->parent_ptes[0] = old;
950 }
4db35314 951 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 952 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
953 continue;
954 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
955 if (!pte_chain->parent_ptes[i]) {
956 pte_chain->parent_ptes[i] = parent_pte;
957 return;
958 }
959 }
714b93da 960 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 961 BUG_ON(!pte_chain);
4db35314 962 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 963 pte_chain->parent_ptes[0] = parent_pte;
964}
965
4db35314 966static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 967 u64 *parent_pte)
968{
969 struct kvm_pte_chain *pte_chain;
970 struct hlist_node *node;
971 int i;
972
4db35314
AK		 973 if (!sp->multimapped) {
974 BUG_ON(sp->parent_pte != parent_pte);
975 sp->parent_pte = NULL;
cea0f0e7
AK		 976 return;
977 }
4db35314 978 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 979 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
980 if (!pte_chain->parent_ptes[i])
981 break;
982 if (pte_chain->parent_ptes[i] != parent_pte)
983 continue;
697fe2e2
AK		 984 while (i + 1 < NR_PTE_CHAIN_ENTRIES
985 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 986 pte_chain->parent_ptes[i]
987 = pte_chain->parent_ptes[i + 1];
988 ++i;
989 }
990 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 991 if (i == 0) {
992 hlist_del(&pte_chain->link);
90cb0529 993 mmu_free_pte_chain(pte_chain);
4db35314
AK		 994 if (hlist_empty(&sp->parent_ptes)) {
995 sp->multimapped = 0;
996 sp->parent_pte = NULL;
697fe2e2
AK		 997 }
998 }
cea0f0e7
AK		 999 return;
1000 }
1001 BUG();
1002}
1003
ad8cfbe3 1004
6b18493d 1005static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
ad8cfbe3
MT		 1006{
1007 struct kvm_pte_chain *pte_chain;
1008 struct hlist_node *node;
1009 struct kvm_mmu_page *parent_sp;
1010 int i;
1011
1012 if (!sp->multimapped && sp->parent_pte) {
1013 parent_sp = page_header(__pa(sp->parent_pte));
6b18493d
XG		 1014 fn(parent_sp);
1015 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1016 return;
1017 }
1018 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1019 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1020 if (!pte_chain->parent_ptes[i])
1021 break;
1022 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
6b18493d
XG		 1023 fn(parent_sp);
1024 mmu_parent_walk(parent_sp, fn);
ad8cfbe3
MT		 1025 }
1026}
1027
0074ff63
MT		 1028static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1029{
1030 unsigned int index;
1031 struct kvm_mmu_page *sp = page_header(__pa(spte));
1032
1033 index = spte - sp->spt;
60c8aec6
MT		 1034 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1035 sp->unsync_children++;
1036 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1037}
1038
1039static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1040{
1041 struct kvm_pte_chain *pte_chain;
1042 struct hlist_node *node;
1043 int i;
1044
1045 if (!sp->parent_pte)
1046 return;
1047
1048 if (!sp->multimapped) {
1049 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1050 return;
1051 }
1052
1053 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1054 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1055 if (!pte_chain->parent_ptes[i])
1056 break;
1057 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1058 }
1059}
1060
6b18493d 1061static int unsync_walk_fn(struct kvm_mmu_page *sp)
0074ff63 1062{
0074ff63
MT		 1063 kvm_mmu_update_parents_unsync(sp);
1064 return 1;
1065}
1066
6b18493d 1067static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1068{
6b18493d 1069 mmu_parent_walk(sp, unsync_walk_fn);
0074ff63
MT		 1070 kvm_mmu_update_parents_unsync(sp);
1071}
1072
d761a501
AK		 1073static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1074 struct kvm_mmu_page *sp)
1075{
1076 int i;
1077
1078 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1079 sp->spt[i] = shadow_trap_nonpresent_pte;
1080}
1081
e8bc217a
MT		 1082static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1083 struct kvm_mmu_page *sp)
1084{
1085 return 1;
1086}
1087
a7052897
MT		 1088static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1089{
1090}
1091
60c8aec6
MT		 1092#define KVM_PAGE_ARRAY_NR 16
1093
1094struct kvm_mmu_pages {
1095 struct mmu_page_and_offset {
1096 struct kvm_mmu_page *sp;
1097 unsigned int idx;
1098 } page[KVM_PAGE_ARRAY_NR];
1099 unsigned int nr;
1100};
1101
0074ff63
MT		 1102#define for_each_unsync_children(bitmap, idx) \
1103 for (idx = find_first_bit(bitmap, 512); \
1104 idx < 512; \
1105 idx = find_next_bit(bitmap, 512, idx+1))
1106
cded19f3
HE		 1107static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1108 int idx)
4731d4c7 1109{
60c8aec6 1110 int i;
4731d4c7 1111
60c8aec6
MT		 1112 if (sp->unsync)
1113 for (i=0; i < pvec->nr; i++)
1114 if (pvec->page[i].sp == sp)
1115 return 0;
1116
1117 pvec->page[pvec->nr].sp = sp;
1118 pvec->page[pvec->nr].idx = idx;
1119 pvec->nr++;
1120 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1121}
1122
1123static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1124 struct kvm_mmu_pages *pvec)
1125{
1126 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1127
0074ff63 1128 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1129 u64 ent = sp->spt[i];
1130
87917239 1131 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1132 struct kvm_mmu_page *child;
1133 child = page_header(ent & PT64_BASE_ADDR_MASK);
1134
1135 if (child->unsync_children) {
60c8aec6
MT		 1136 if (mmu_pages_add(pvec, child, i))
1137 return -ENOSPC;
1138
1139 ret = __mmu_unsync_walk(child, pvec);
1140 if (!ret)
1141 __clear_bit(i, sp->unsync_child_bitmap);
1142 else if (ret > 0)
1143 nr_unsync_leaf += ret;
1144 else
4731d4c7
MT		 1145 return ret;
1146 }
1147
1148 if (child->unsync) {
60c8aec6
MT		 1149 nr_unsync_leaf++;
1150 if (mmu_pages_add(pvec, child, i))
1151 return -ENOSPC;
4731d4c7
MT		 1152 }
1153 }
1154 }
1155
0074ff63 1156 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1157 sp->unsync_children = 0;
1158
60c8aec6
MT		 1159 return nr_unsync_leaf;
1160}
1161
1162static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1163 struct kvm_mmu_pages *pvec)
1164{
1165 if (!sp->unsync_children)
1166 return 0;
1167
1168 mmu_pages_add(pvec, sp, 0);
1169 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1170}
1171
4db35314 1172static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1173{
1174 unsigned index;
1175 struct hlist_head *bucket;
4db35314 1176 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1177 struct hlist_node *node;
1178
b8688d51 1179 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1180 index = kvm_page_table_hashfn(gfn);
f05e70ac 1181 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1182 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1183 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1184 && !sp->role.invalid) {
cea0f0e7 1185 pgprintk("%s: found role %x\n",
b8688d51 1186 __func__, sp->role.word);
4db35314 1187 return sp;
cea0f0e7
AK		 1188 }
1189 return NULL;
1190}
1191
4731d4c7
MT		 1192static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1193{
1194 WARN_ON(!sp->unsync);
5e1b3ddb 1195 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1196 sp->unsync = 0;
1197 --kvm->stat.mmu_unsync;
1198}
1199
1200static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1201
1202static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1203{
5b7e0102 1204 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
4731d4c7
MT		 1205 kvm_mmu_zap_page(vcpu->kvm, sp);
1206 return 1;
1207 }
1208
b1a36821
MT		 1209 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1210 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1211 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1212 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1213 kvm_mmu_zap_page(vcpu->kvm, sp);
1214 return 1;
1215 }
1216
1217 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1218 return 0;
1219}
1220
60c8aec6
MT		 1221struct mmu_page_path {
1222 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1223 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1224};
1225
60c8aec6
MT		 1226#define for_each_sp(pvec, sp, parents, i) \
1227 for (i = mmu_pages_next(&pvec, &parents, -1), \
1228 sp = pvec.page[i].sp; \
1229 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1230 i = mmu_pages_next(&pvec, &parents, i))
1231
cded19f3
HE		 1232static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1233 struct mmu_page_path *parents,
1234 int i)
60c8aec6
MT		 1235{
1236 int n;
1237
1238 for (n = i+1; n < pvec->nr; n++) {
1239 struct kvm_mmu_page *sp = pvec->page[n].sp;
1240
1241 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1242 parents->idx[0] = pvec->page[n].idx;
1243 return n;
1244 }
1245
1246 parents->parent[sp->role.level-2] = sp;
1247 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1248 }
1249
1250 return n;
1251}
1252
cded19f3 1253static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1254{
60c8aec6
MT		 1255 struct kvm_mmu_page *sp;
1256 unsigned int level = 0;
1257
1258 do {
1259 unsigned int idx = parents->idx[level];
4731d4c7 1260
60c8aec6
MT		 1261 sp = parents->parent[level];
1262 if (!sp)
1263 return;
1264
1265 --sp->unsync_children;
1266 WARN_ON((int)sp->unsync_children < 0);
1267 __clear_bit(idx, sp->unsync_child_bitmap);
1268 level++;
1269 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1270}
1271
60c8aec6
MT		 1272static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1273 struct mmu_page_path *parents,
1274 struct kvm_mmu_pages *pvec)
4731d4c7 1275{
60c8aec6
MT		 1276 parents->parent[parent->role.level-1] = NULL;
1277 pvec->nr = 0;
1278}
4731d4c7 1279
60c8aec6
MT		 1280static void mmu_sync_children(struct kvm_vcpu *vcpu,
1281 struct kvm_mmu_page *parent)
1282{
1283 int i;
1284 struct kvm_mmu_page *sp;
1285 struct mmu_page_path parents;
1286 struct kvm_mmu_pages pages;
1287
1288 kvm_mmu_pages_init(parent, &parents, &pages);
1289 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1290 int protected = 0;
1291
1292 for_each_sp(pages, sp, parents, i)
1293 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1294
1295 if (protected)
1296 kvm_flush_remote_tlbs(vcpu->kvm);
1297
60c8aec6
MT		 1298 for_each_sp(pages, sp, parents, i) {
1299 kvm_sync_page(vcpu, sp);
1300 mmu_pages_clear_parents(&parents);
1301 }
4731d4c7 1302 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1303 kvm_mmu_pages_init(parent, &parents, &pages);
1304 }
4731d4c7
MT		 1305}
1306
cea0f0e7
AK		 1307static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1308 gfn_t gfn,
1309 gva_t gaddr,
1310 unsigned level,
f6e2c02b 1311 int direct,
41074d07 1312 unsigned access,
f7d9c7b7 1313 u64 *parent_pte)
cea0f0e7
AK		 1314{
1315 union kvm_mmu_page_role role;
1316 unsigned index;
1317 unsigned quadrant;
1318 struct hlist_head *bucket;
4db35314 1319 struct kvm_mmu_page *sp;
4731d4c7 1320 struct hlist_node *node, *tmp;
cea0f0e7 1321
a770f6f2 1322 role = vcpu->arch.mmu.base_role;
cea0f0e7 1323 role.level = level;
f6e2c02b 1324 role.direct = direct;
84b0c8c6 1325 if (role.direct)
5b7e0102 1326 role.cr4_pae = 0;
41074d07 1327 role.access = access;
ad312c7c 1328 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1329 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1330 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1331 role.quadrant = quadrant;
1332 }
1ae0a13d 1333 index = kvm_page_table_hashfn(gfn);
f05e70ac 1334 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1335 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1336 if (sp->gfn == gfn) {
1337 if (sp->unsync)
1338 if (kvm_sync_page(vcpu, sp))
1339 continue;
1340
1341 if (sp->role.word != role.word)
1342 continue;
1343
4db35314 1344 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1345 if (sp->unsync_children) {
1346 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
6b18493d 1347 kvm_mmu_mark_parents_unsync(sp);
0074ff63 1348 }
f691fe1d 1349 trace_kvm_mmu_get_page(sp, false);
4db35314 1350 return sp;
cea0f0e7 1351 }
dfc5aa00 1352 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1353 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1354 if (!sp)
1355 return sp;
4db35314
AK		 1356 sp->gfn = gfn;
1357 sp->role = role;
1358 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1359 if (!direct) {
b1a36821
MT		 1360 if (rmap_write_protect(vcpu->kvm, gfn))
1361 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1362 account_shadowed(vcpu->kvm, gfn);
1363 }
131d8279
AK		 1364 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1365 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1366 else
1367 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1368 trace_kvm_mmu_get_page(sp, true);
4db35314 1369 return sp;
cea0f0e7
AK		 1370}
1371
2d11123a
AK		 1372static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1373 struct kvm_vcpu *vcpu, u64 addr)
1374{
1375 iterator->addr = addr;
1376 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1377 iterator->level = vcpu->arch.mmu.shadow_root_level;
1378 if (iterator->level == PT32E_ROOT_LEVEL) {
1379 iterator->shadow_addr
1380 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1381 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1382 --iterator->level;
1383 if (!iterator->shadow_addr)
1384 iterator->level = 0;
1385 }
1386}
1387
1388static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1389{
1390 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1391 return false;
4d88954d
MT		 1392
1393 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1394 if (is_large_pte(*iterator->sptep))
1395 return false;
1396
2d11123a
AK		 1397 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1398 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1399 return true;
1400}
1401
1402static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1403{
1404 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1405 --iterator->level;
1406}
1407
90cb0529 1408static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1409 struct kvm_mmu_page *sp)
a436036b 1410{
697fe2e2
AK		 1411 unsigned i;
1412 u64 *pt;
1413 u64 ent;
1414
4db35314 1415 pt = sp->spt;
697fe2e2 1416
697fe2e2
AK		 1417 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1418 ent = pt[i];
1419
05da4558 1420 if (is_shadow_present_pte(ent)) {
776e6633 1421 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1422 ent &= PT64_BASE_ADDR_MASK;
1423 mmu_page_remove_parent_pte(page_header(ent),
1424 &pt[i]);
1425 } else {
776e6633
MT		 1426 if (is_large_pte(ent))
1427 --kvm->stat.lpages;
05da4558
MT		 1428 rmap_remove(kvm, &pt[i]);
1429 }
1430 }
c7addb90 1431 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1432 }
a436036b
AK		 1433}
1434
4db35314 1435static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1436{
4db35314 1437 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1438}
1439
12b7d28f
AK		 1440static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1441{
1442 int i;
988a2cae 1443 struct kvm_vcpu *vcpu;
12b7d28f 1444
988a2cae
GN		 1445 kvm_for_each_vcpu(i, vcpu, kvm)
1446 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1447}
1448
31aa2b44 1449static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1450{
1451 u64 *parent_pte;
1452
4db35314
AK		 1453 while (sp->multimapped || sp->parent_pte) {
1454 if (!sp->multimapped)
1455 parent_pte = sp->parent_pte;
a436036b
AK		 1456 else {
1457 struct kvm_pte_chain *chain;
1458
4db35314 1459 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1460 struct kvm_pte_chain, link);
1461 parent_pte = chain->parent_ptes[0];
1462 }
697fe2e2 1463 BUG_ON(!parent_pte);
4db35314 1464 kvm_mmu_put_page(sp, parent_pte);
d555c333 1465 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1466 }
31aa2b44
AK		 1467}
1468
60c8aec6
MT		 1469static int mmu_zap_unsync_children(struct kvm *kvm,
1470 struct kvm_mmu_page *parent)
4731d4c7 1471{
60c8aec6
MT		 1472 int i, zapped = 0;
1473 struct mmu_page_path parents;
1474 struct kvm_mmu_pages pages;
4731d4c7 1475
60c8aec6 1476 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1477 return 0;
60c8aec6
MT		 1478
1479 kvm_mmu_pages_init(parent, &parents, &pages);
1480 while (mmu_unsync_walk(parent, &pages)) {
1481 struct kvm_mmu_page *sp;
1482
1483 for_each_sp(pages, sp, parents, i) {
1484 kvm_mmu_zap_page(kvm, sp);
1485 mmu_pages_clear_parents(&parents);
77662e00 1486 zapped++;
60c8aec6 1487 }
60c8aec6
MT		 1488 kvm_mmu_pages_init(parent, &parents, &pages);
1489 }
1490
1491 return zapped;
4731d4c7
MT		 1492}
1493
07385413 1494static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1495{
4731d4c7 1496 int ret;
f691fe1d
AK		 1497
1498 trace_kvm_mmu_zap_page(sp);
31aa2b44 1499 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1500 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1501 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1502 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1503 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1504 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1505 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1506 if (sp->unsync)
1507 kvm_unlink_unsync_page(kvm, sp);
4db35314 1508 if (!sp->root_count) {
54a4f023
GJ		 1509 /* Count self */
1510 ret++;
4db35314
AK		 1511 hlist_del(&sp->hash_link);
1512 kvm_mmu_free_page(kvm, sp);
2e53d63a 1513 } else {
2e53d63a 1514 sp->role.invalid = 1;
5b5c6a5a 1515 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1516 kvm_reload_remote_mmus(kvm);
1517 }
12b7d28f 1518 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1519 return ret;
a436036b
AK		 1520}
1521
82ce2c96
IE		 1522/*
1523 * Changing the number of mmu pages allocated to the vm
1524 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1525 */
1526void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1527{
025dbbf3
MT		 1528 int used_pages;
1529
1530 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1531 used_pages = max(0, used_pages);
1532
82ce2c96
IE		 1533 /*
1534 * If we set the number of mmu pages to be smaller be than the
1535 * number of actived pages , we must to free some mmu pages before we
1536 * change the value
1537 */
1538
025dbbf3 1539 if (used_pages > kvm_nr_mmu_pages) {
77662e00
XG		 1540 while (used_pages > kvm_nr_mmu_pages &&
1541 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1542 struct kvm_mmu_page *page;
1543
f05e70ac 1544 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1545 struct kvm_mmu_page, link);
77662e00 1546 used_pages -= kvm_mmu_zap_page(kvm, page);
82ce2c96 1547 }
77662e00 1548 kvm_nr_mmu_pages = used_pages;
f05e70ac 1549 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1550 }
1551 else
f05e70ac
ZX		 1552 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1553 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1554
f05e70ac 1555 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1556}
1557
f67a46f4 1558static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1559{
1560 unsigned index;
1561 struct hlist_head *bucket;
4db35314 1562 struct kvm_mmu_page *sp;
a436036b
AK		 1563 struct hlist_node *node, *n;
1564 int r;
1565
b8688d51 1566 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1567 r = 0;
1ae0a13d 1568 index = kvm_page_table_hashfn(gfn);
f05e70ac 1569 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1570restart:
4db35314 1571 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1572 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1573 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1574 sp->role.word);
a436036b 1575 r = 1;
07385413 1576 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1577 goto restart;
a436036b
AK		 1578 }
1579 return r;
cea0f0e7
AK		 1580}
1581
f67a46f4 1582static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1583{
4677a3b6
AK		 1584 unsigned index;
1585 struct hlist_head *bucket;
4db35314 1586 struct kvm_mmu_page *sp;
4677a3b6 1587 struct hlist_node *node, *nn;
97a0a01e 1588
4677a3b6
AK		 1589 index = kvm_page_table_hashfn(gfn);
1590 bucket = &kvm->arch.mmu_page_hash[index];
3246af0e 1591restart:
4677a3b6 1592 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1593 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1594 && !sp->role.invalid) {
1595 pgprintk("%s: zap %lx %x\n",
1596 __func__, gfn, sp->role.word);
77662e00 1597 if (kvm_mmu_zap_page(kvm, sp))
3246af0e 1598 goto restart;
4677a3b6 1599 }
97a0a01e
AK		 1600 }
1601}
1602
38c335f1 1603static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1604{
bc6678a3 1605 int slot = memslot_id(kvm, gfn);
4db35314 1606 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1607
291f26bc 1608 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1609}
1610
6844dec6
MT		 1611static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1612{
1613 int i;
1614 u64 *pt = sp->spt;
1615
1616 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1617 return;
1618
1619 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1620 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1621 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1622 }
1623}
1624
74be52e3
SY		 1625/*
1626 * The function is based on mtrr_type_lookup() in
1627 * arch/x86/kernel/cpu/mtrr/generic.c
1628 */
1629static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1630 u64 start, u64 end)
1631{
1632 int i;
1633 u64 base, mask;
1634 u8 prev_match, curr_match;
1635 int num_var_ranges = KVM_NR_VAR_MTRR;
1636
1637 if (!mtrr_state->enabled)
1638 return 0xFF;
1639
1640 /* Make end inclusive end, instead of exclusive */
1641 end--;
1642
1643 /* Look in fixed ranges. Just return the type as per start */
1644 if (mtrr_state->have_fixed && (start < 0x100000)) {
1645 int idx;
1646
1647 if (start < 0x80000) {
1648 idx = 0;
1649 idx += (start >> 16);
1650 return mtrr_state->fixed_ranges[idx];
1651 } else if (start < 0xC0000) {
1652 idx = 1 * 8;
1653 idx += ((start - 0x80000) >> 14);
1654 return mtrr_state->fixed_ranges[idx];
1655 } else if (start < 0x1000000) {
1656 idx = 3 * 8;
1657 idx += ((start - 0xC0000) >> 12);
1658 return mtrr_state->fixed_ranges[idx];
1659 }
1660 }
1661
1662 /*
1663 * Look in variable ranges
1664 * Look of multiple ranges matching this address and pick type
1665 * as per MTRR precedence
1666 */
1667 if (!(mtrr_state->enabled & 2))
1668 return mtrr_state->def_type;
1669
1670 prev_match = 0xFF;
1671 for (i = 0; i < num_var_ranges; ++i) {
1672 unsigned short start_state, end_state;
1673
1674 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1675 continue;
1676
1677 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1678 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1679 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1680 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1681
1682 start_state = ((start & mask) == (base & mask));
1683 end_state = ((end & mask) == (base & mask));
1684 if (start_state != end_state)
1685 return 0xFE;
1686
1687 if ((start & mask) != (base & mask))
1688 continue;
1689
1690 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1691 if (prev_match == 0xFF) {
1692 prev_match = curr_match;
1693 continue;
1694 }
1695
1696 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1697 curr_match == MTRR_TYPE_UNCACHABLE)
1698 return MTRR_TYPE_UNCACHABLE;
1699
1700 if ((prev_match == MTRR_TYPE_WRBACK &&
1701 curr_match == MTRR_TYPE_WRTHROUGH) ||
1702 (prev_match == MTRR_TYPE_WRTHROUGH &&
1703 curr_match == MTRR_TYPE_WRBACK)) {
1704 prev_match = MTRR_TYPE_WRTHROUGH;
1705 curr_match = MTRR_TYPE_WRTHROUGH;
1706 }
1707
1708 if (prev_match != curr_match)
1709 return MTRR_TYPE_UNCACHABLE;
1710 }
1711
1712 if (prev_match != 0xFF)
1713 return prev_match;
1714
1715 return mtrr_state->def_type;
1716}
1717
4b12f0de 1718u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1719{
1720 u8 mtrr;
1721
1722 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1723 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1724 if (mtrr == 0xfe || mtrr == 0xff)
1725 mtrr = MTRR_TYPE_WRBACK;
1726 return mtrr;
1727}
4b12f0de 1728EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1729
4731d4c7
MT		 1730static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1731{
1732 unsigned index;
1733 struct hlist_head *bucket;
1734 struct kvm_mmu_page *s;
1735 struct hlist_node *node, *n;
1736
1737 index = kvm_page_table_hashfn(sp->gfn);
1738 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1739 /* don't unsync if pagetable is shadowed with multiple roles */
1740 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1741 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1742 continue;
1743 if (s->role.word != sp->role.word)
1744 return 1;
1745 }
5e1b3ddb 1746 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1747 ++vcpu->kvm->stat.mmu_unsync;
1748 sp->unsync = 1;
6cffe8ca 1749
6b18493d 1750 kvm_mmu_mark_parents_unsync(sp);
6cffe8ca 1751
4731d4c7
MT		 1752 mmu_convert_notrap(sp);
1753 return 0;
1754}
1755
1756static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1757 bool can_unsync)
1758{
1759 struct kvm_mmu_page *shadow;
1760
1761 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1762 if (shadow) {
1763 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1764 return 1;
1765 if (shadow->unsync)
1766 return 0;
582801a9 1767 if (can_unsync && oos_shadow)
4731d4c7
MT		 1768 return kvm_unsync_page(vcpu, shadow);
1769 return 1;
1770 }
1771 return 0;
1772}
1773
d555c333 1774static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1775 unsigned pte_access, int user_fault,
852e3c19 1776 int write_fault, int dirty, int level,
c2d0ee46 1777 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1778 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1779{
1780 u64 spte;
1e73f9dd 1781 int ret = 0;
64d4d521 1782
1c4f1fd6
AK		 1783 /*
1784 * We don't set the accessed bit, since we sometimes want to see
1785 * whether the guest actually used the pte (in order to detect
1786 * demand paging).
1787 */
7b52345e 1788 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1789 if (!speculative)
3201b5d9 1790 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1791 if (!dirty)
1792 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1793 if (pte_access & ACC_EXEC_MASK)
1794 spte |= shadow_x_mask;
1795 else
1796 spte |= shadow_nx_mask;
1c4f1fd6 1797 if (pte_access & ACC_USER_MASK)
7b52345e 1798 spte |= shadow_user_mask;
852e3c19 1799 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1800 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1801 if (tdp_enabled)
1802 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1803 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1804
1403283a
IE		 1805 if (reset_host_protection)
1806 spte |= SPTE_HOST_WRITEABLE;
1807
35149e21 1808 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1809
1810 if ((pte_access & ACC_WRITE_MASK)
1811 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1812
852e3c19
JR		 1813 if (level > PT_PAGE_TABLE_LEVEL &&
1814 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1815 ret = 1;
1816 spte = shadow_trap_nonpresent_pte;
1817 goto set_pte;
1818 }
1819
1c4f1fd6 1820 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1821
69325a12
AK		 1822 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1823 spte &= ~PT_USER_MASK;
1824
ecc5589f
MT		 1825 /*
1826 * Optimization: for pte sync, if spte was writable the hash
1827 * lookup is unnecessary (and expensive). Write protection
1828 * is responsibility of mmu_get_page / kvm_sync_page.
1829 * Same reasoning can be applied to dirty page accounting.
1830 */
8dae4445 1831 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 1832 goto set_pte;
1833
4731d4c7 1834 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1835 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1836 __func__, gfn);
1e73f9dd 1837 ret = 1;
1c4f1fd6 1838 pte_access &= ~ACC_WRITE_MASK;
8dae4445 1839 if (is_writable_pte(spte))
1c4f1fd6 1840 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1841 }
1842 }
1843
1c4f1fd6
AK		 1844 if (pte_access & ACC_WRITE_MASK)
1845 mark_page_dirty(vcpu->kvm, gfn);
1846
38187c83 1847set_pte:
d555c333 1848 __set_spte(sptep, spte);
1e73f9dd
MT		 1849 return ret;
1850}
1851
d555c333 1852static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1853 unsigned pt_access, unsigned pte_access,
1854 int user_fault, int write_fault, int dirty,
852e3c19 1855 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1856 pfn_t pfn, bool speculative,
1857 bool reset_host_protection)
1e73f9dd
MT		 1858{
1859 int was_rmapped = 0;
8dae4445 1860 int was_writable = is_writable_pte(*sptep);
53a27b39 1861 int rmap_count;
1e73f9dd
MT		 1862
1863 pgprintk("%s: spte %llx access %x write_fault %d"
1864 " user_fault %d gfn %lx\n",
d555c333 1865 __func__, *sptep, pt_access,
1e73f9dd
MT		 1866 write_fault, user_fault, gfn);
1867
d555c333 1868 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1869 /*
1870 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1871 * the parent of the now unreachable PTE.
1872 */
852e3c19
JR		 1873 if (level > PT_PAGE_TABLE_LEVEL &&
1874 !is_large_pte(*sptep)) {
1e73f9dd 1875 struct kvm_mmu_page *child;
d555c333 1876 u64 pte = *sptep;
1e73f9dd
MT		 1877
1878 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333 1879 mmu_page_remove_parent_pte(child, sptep);
3be2264b
MT		 1880 __set_spte(sptep, shadow_trap_nonpresent_pte);
1881 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 1882 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1883 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1884 spte_to_pfn(*sptep), pfn);
1885 rmap_remove(vcpu->kvm, sptep);
91546356
XG		 1886 __set_spte(sptep, shadow_trap_nonpresent_pte);
1887 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR		 1888 } else
1889 was_rmapped = 1;
1e73f9dd 1890 }
852e3c19 1891
d555c333 1892 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1893 dirty, level, gfn, pfn, speculative, true,
1894 reset_host_protection)) {
1e73f9dd
MT		 1895 if (write_fault)
1896 *ptwrite = 1;
a378b4e6
MT		 1897 kvm_x86_ops->tlb_flush(vcpu);
1898 }
1e73f9dd 1899
d555c333 1900 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1901 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1902 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1903 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1904 *sptep, sptep);
d555c333 1905 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1906 ++vcpu->kvm->stat.lpages;
1907
d555c333 1908 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1909 if (!was_rmapped) {
44ad9944 1910 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1911 kvm_release_pfn_clean(pfn);
53a27b39 1912 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1913 rmap_recycle(vcpu, sptep, gfn);
75e68e60 1914 } else {
8dae4445 1915 if (was_writable)
35149e21 1916 kvm_release_pfn_dirty(pfn);
75e68e60 1917 else
35149e21 1918 kvm_release_pfn_clean(pfn);
1c4f1fd6 1919 }
1b7fcd32 1920 if (speculative) {
d555c333 1921 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1922 vcpu->arch.last_pte_gfn = gfn;
1923 }
1c4f1fd6
AK		 1924}
1925
6aa8b732
AK		 1926static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1927{
1928}
1929
9f652d21 1930static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1931 int level, gfn_t gfn, pfn_t pfn)
140754bc 1932{
9f652d21 1933 struct kvm_shadow_walk_iterator iterator;
140754bc 1934 struct kvm_mmu_page *sp;
9f652d21 1935 int pt_write = 0;
140754bc 1936 gfn_t pseudo_gfn;
6aa8b732 1937
9f652d21 1938 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1939 if (iterator.level == level) {
9f652d21
AK		 1940 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1941 0, write, 1, &pt_write,
1403283a 1942 level, gfn, pfn, false, true);
9f652d21
AK		 1943 ++vcpu->stat.pf_fixed;
1944 break;
6aa8b732
AK		 1945 }
1946
9f652d21
AK		 1947 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1948 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1949 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1950 iterator.level - 1,
1951 1, ACC_ALL, iterator.sptep);
1952 if (!sp) {
1953 pgprintk("nonpaging_map: ENOMEM\n");
1954 kvm_release_pfn_clean(pfn);
1955 return -ENOMEM;
1956 }
140754bc 1957
d555c333
AK		 1958 __set_spte(iterator.sptep,
1959 __pa(sp->spt)
1960 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1961 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1962 }
1963 }
1964 return pt_write;
6aa8b732
AK		 1965}
1966
bf998156
HY		 1967static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
1968{
1969 char buf[1];
1970 void __user *hva;
1971 int r;
1972
1973 /* Touch the page, so send SIGBUS */
1974 hva = (void __user *)gfn_to_hva(kvm, gfn);
1975 r = copy_from_user(buf, hva, 1);
1976}
1977
1978static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
1979{
1980 kvm_release_pfn_clean(pfn);
1981 if (is_hwpoison_pfn(pfn)) {
1982 kvm_send_hwpoison_signal(kvm, gfn);
1983 return 0;
1984 }
1985 return 1;
1986}
1987
10589a46
MT		 1988static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1989{
1990 int r;
852e3c19 1991 int level;
35149e21 1992 pfn_t pfn;
e930bffe 1993 unsigned long mmu_seq;
aaee2c94 1994
852e3c19
JR		 1995 level = mapping_level(vcpu, gfn);
1996
1997 /*
1998 * This path builds a PAE pagetable - so we can map 2mb pages at
1999 * maximum. Therefore check if the level is larger than that.
2000 */
2001 if (level > PT_DIRECTORY_LEVEL)
2002 level = PT_DIRECTORY_LEVEL;
2003
2004 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2005
e930bffe 2006 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2007 smp_rmb();
35149e21 2008 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2009
d196e343 2010 /* mmio */
bf998156
HY		 2011 if (is_error_pfn(pfn))
2012 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2013
aaee2c94 2014 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2015 if (mmu_notifier_retry(vcpu, mmu_seq))
2016 goto out_unlock;
eb787d10 2017 kvm_mmu_free_some_pages(vcpu);
852e3c19 2018 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2019 spin_unlock(&vcpu->kvm->mmu_lock);
2020
aaee2c94 2021
10589a46 2022 return r;
e930bffe
AA		 2023
2024out_unlock:
2025 spin_unlock(&vcpu->kvm->mmu_lock);
2026 kvm_release_pfn_clean(pfn);
2027 return 0;
10589a46
MT		 2028}
2029
2030
17ac10ad
AK		 2031static void mmu_free_roots(struct kvm_vcpu *vcpu)
2032{
2033 int i;
4db35314 2034 struct kvm_mmu_page *sp;
17ac10ad 2035
ad312c7c 2036 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2037 return;
aaee2c94 2038 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2039 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2040 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2041
4db35314
AK		 2042 sp = page_header(root);
2043 --sp->root_count;
2e53d63a
MT		 2044 if (!sp->root_count && sp->role.invalid)
2045 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2046 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2047 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2048 return;
2049 }
17ac10ad 2050 for (i = 0; i < 4; ++i) {
ad312c7c 2051 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2052
417726a3 2053 if (root) {
417726a3 2054 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2055 sp = page_header(root);
2056 --sp->root_count;
2e53d63a
MT		 2057 if (!sp->root_count && sp->role.invalid)
2058 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2059 }
ad312c7c 2060 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2061 }
aaee2c94 2062 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2063 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2064}
2065
8986ecc0
MT		 2066static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2067{
2068 int ret = 0;
2069
2070 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2071 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2072 ret = 1;
2073 }
2074
2075 return ret;
2076}
2077
2078static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2079{
2080 int i;
cea0f0e7 2081 gfn_t root_gfn;
4db35314 2082 struct kvm_mmu_page *sp;
f6e2c02b 2083 int direct = 0;
6de4f3ad 2084 u64 pdptr;
3bb65a22 2085
ad312c7c 2086 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2087
ad312c7c
ZX		 2088 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2089 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2090
2091 ASSERT(!VALID_PAGE(root));
8986ecc0
MT		 2092 if (mmu_check_root(vcpu, root_gfn))
2093 return 1;
5a7388c2
EN		 2094 if (tdp_enabled) {
2095 direct = 1;
2096 root_gfn = 0;
2097 }
8facbbff 2098 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2099 kvm_mmu_free_some_pages(vcpu);
4db35314 2100 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2101 PT64_ROOT_LEVEL, direct,
fb72d167 2102 ACC_ALL, NULL);
4db35314
AK		 2103 root = __pa(sp->spt);
2104 ++sp->root_count;
8facbbff 2105 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2106 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2107 return 0;
17ac10ad 2108 }
f6e2c02b 2109 direct = !is_paging(vcpu);
17ac10ad 2110 for (i = 0; i < 4; ++i) {
ad312c7c 2111 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2112
2113 ASSERT(!VALID_PAGE(root));
ad312c7c 2114 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2115 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2116 if (!is_present_gpte(pdptr)) {
ad312c7c 2117 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2118 continue;
2119 }
6de4f3ad 2120 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2121 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2122 root_gfn = 0;
8986ecc0
MT		 2123 if (mmu_check_root(vcpu, root_gfn))
2124 return 1;
5a7388c2
EN		 2125 if (tdp_enabled) {
2126 direct = 1;
2127 root_gfn = i << 30;
2128 }
8facbbff 2129 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2130 kvm_mmu_free_some_pages(vcpu);
4db35314 2131 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2132 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2133 ACC_ALL, NULL);
4db35314
AK		 2134 root = __pa(sp->spt);
2135 ++sp->root_count;
8facbbff
AK		 2136 spin_unlock(&vcpu->kvm->mmu_lock);
2137
ad312c7c 2138 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2139 }
ad312c7c 2140 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2141 return 0;
17ac10ad
AK		 2142}
2143
0ba73cda
MT		 2144static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2145{
2146 int i;
2147 struct kvm_mmu_page *sp;
2148
2149 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2150 return;
2151 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2152 hpa_t root = vcpu->arch.mmu.root_hpa;
2153 sp = page_header(root);
2154 mmu_sync_children(vcpu, sp);
2155 return;
2156 }
2157 for (i = 0; i < 4; ++i) {
2158 hpa_t root = vcpu->arch.mmu.pae_root[i];
2159
8986ecc0 2160 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2161 root &= PT64_BASE_ADDR_MASK;
2162 sp = page_header(root);
2163 mmu_sync_children(vcpu, sp);
2164 }
2165 }
2166}
2167
2168void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2169{
2170 spin_lock(&vcpu->kvm->mmu_lock);
2171 mmu_sync_roots(vcpu);
6cffe8ca 2172 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2173}
2174
1871c602
GN		 2175static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2176 u32 access, u32 *error)
6aa8b732 2177{
1871c602
GN		 2178 if (error)
2179 *error = 0;
6aa8b732
AK		 2180 return vaddr;
2181}
2182
2183static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2184 u32 error_code)
6aa8b732 2185{
e833240f 2186 gfn_t gfn;
e2dec939 2187 int r;
6aa8b732 2188
b8688d51 2189 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2190 r = mmu_topup_memory_caches(vcpu);
2191 if (r)
2192 return r;
714b93da 2193
6aa8b732 2194 ASSERT(vcpu);
ad312c7c 2195 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2196
e833240f 2197 gfn = gva >> PAGE_SHIFT;
6aa8b732 2198
e833240f
AK		 2199 return nonpaging_map(vcpu, gva & PAGE_MASK,
2200 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2201}
2202
fb72d167
JR		 2203static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2204 u32 error_code)
2205{
35149e21 2206 pfn_t pfn;
fb72d167 2207 int r;
852e3c19 2208 int level;
05da4558 2209 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2210 unsigned long mmu_seq;
fb72d167
JR		 2211
2212 ASSERT(vcpu);
2213 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2214
2215 r = mmu_topup_memory_caches(vcpu);
2216 if (r)
2217 return r;
2218
852e3c19
JR		 2219 level = mapping_level(vcpu, gfn);
2220
2221 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2222
e930bffe 2223 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2224 smp_rmb();
35149e21 2225 pfn = gfn_to_pfn(vcpu->kvm, gfn);
bf998156
HY		 2226 if (is_error_pfn(pfn))
2227 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2228 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2229 if (mmu_notifier_retry(vcpu, mmu_seq))
2230 goto out_unlock;
fb72d167
JR		 2231 kvm_mmu_free_some_pages(vcpu);
2232 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2233 level, gfn, pfn);
fb72d167 2234 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2235
2236 return r;
e930bffe
AA		 2237
2238out_unlock:
2239 spin_unlock(&vcpu->kvm->mmu_lock);
2240 kvm_release_pfn_clean(pfn);
2241 return 0;
fb72d167
JR		 2242}
2243
6aa8b732
AK		 2244static void nonpaging_free(struct kvm_vcpu *vcpu)
2245{
17ac10ad 2246 mmu_free_roots(vcpu);
6aa8b732
AK		 2247}
2248
2249static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2250{
ad312c7c 2251 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2252
2253 context->new_cr3 = nonpaging_new_cr3;
2254 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2255 context->gva_to_gpa = nonpaging_gva_to_gpa;
2256 context->free = nonpaging_free;
c7addb90 2257 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2258 context->sync_page = nonpaging_sync_page;
a7052897 2259 context->invlpg = nonpaging_invlpg;
cea0f0e7 2260 context->root_level = 0;
6aa8b732 2261 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2262 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2263 return 0;
2264}
2265
d835dfec 2266void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2267{
1165f5fe 2268 ++vcpu->stat.tlb_flush;
cbdd1bea 2269 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2270}
2271
2272static void paging_new_cr3(struct kvm_vcpu *vcpu)
2273{
b8688d51 2274 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2275 mmu_free_roots(vcpu);
6aa8b732
AK		 2276}
2277
6aa8b732
AK		 2278static void inject_page_fault(struct kvm_vcpu *vcpu,
2279 u64 addr,
2280 u32 err_code)
2281{
c3c91fee 2282 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2283}
2284
6aa8b732
AK		 2285static void paging_free(struct kvm_vcpu *vcpu)
2286{
2287 nonpaging_free(vcpu);
2288}
2289
82725b20
DE		 2290static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2291{
2292 int bit7;
2293
2294 bit7 = (gpte >> 7) & 1;
2295 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2296}
2297
6aa8b732
AK		 2298#define PTTYPE 64
2299#include "paging_tmpl.h"
2300#undef PTTYPE
2301
2302#define PTTYPE 32
2303#include "paging_tmpl.h"
2304#undef PTTYPE
2305
82725b20
DE		 2306static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2307{
2308 struct kvm_mmu *context = &vcpu->arch.mmu;
2309 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2310 u64 exb_bit_rsvd = 0;
2311
2312 if (!is_nx(vcpu))
2313 exb_bit_rsvd = rsvd_bits(63, 63);
2314 switch (level) {
2315 case PT32_ROOT_LEVEL:
2316 /* no rsvd bits for 2 level 4K page table entries */
2317 context->rsvd_bits_mask[0][1] = 0;
2318 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2319 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2320
2321 if (!is_pse(vcpu)) {
2322 context->rsvd_bits_mask[1][1] = 0;
2323 break;
2324 }
2325
82725b20
DE		 2326 if (is_cpuid_PSE36())
2327 /* 36bits PSE 4MB page */
2328 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2329 else
2330 /* 32 bits PSE 4MB page */
2331 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2332 break;
2333 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2334 context->rsvd_bits_mask[0][2] =
2335 rsvd_bits(maxphyaddr, 63) |
2336 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2337 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2338 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2339 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2340 rsvd_bits(maxphyaddr, 62); /* PTE */
2341 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2342 rsvd_bits(maxphyaddr, 62) |
2343 rsvd_bits(13, 20); /* large page */
f815bce8 2344 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2345 break;
2346 case PT64_ROOT_LEVEL:
2347 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2348 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2349 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2350 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2351 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2352 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2353 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2354 rsvd_bits(maxphyaddr, 51);
2355 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2356 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2357 rsvd_bits(maxphyaddr, 51) |
2358 rsvd_bits(13, 29);
82725b20 2359 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2360 rsvd_bits(maxphyaddr, 51) |
2361 rsvd_bits(13, 20); /* large page */
f815bce8 2362 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2363 break;
2364 }
2365}
2366
17ac10ad 2367static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2368{
ad312c7c 2369 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2370
2371 ASSERT(is_pae(vcpu));
2372 context->new_cr3 = paging_new_cr3;
2373 context->page_fault = paging64_page_fault;
6aa8b732 2374 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2375 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2376 context->sync_page = paging64_sync_page;
a7052897 2377 context->invlpg = paging64_invlpg;
6aa8b732 2378 context->free = paging_free;
17ac10ad
AK		 2379 context->root_level = level;
2380 context->shadow_root_level = level;
17c3ba9d 2381 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2382 return 0;
2383}
2384
17ac10ad
AK		 2385static int paging64_init_context(struct kvm_vcpu *vcpu)
2386{
82725b20 2387 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2388 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2389}
2390
6aa8b732
AK		 2391static int paging32_init_context(struct kvm_vcpu *vcpu)
2392{
ad312c7c 2393 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2394
82725b20 2395 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2396 context->new_cr3 = paging_new_cr3;
2397 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2398 context->gva_to_gpa = paging32_gva_to_gpa;
2399 context->free = paging_free;
c7addb90 2400 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2401 context->sync_page = paging32_sync_page;
a7052897 2402 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2403 context->root_level = PT32_ROOT_LEVEL;
2404 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2405 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2406 return 0;
2407}
2408
2409static int paging32E_init_context(struct kvm_vcpu *vcpu)
2410{
82725b20 2411 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2412 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2413}
2414
fb72d167
JR		 2415static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2416{
2417 struct kvm_mmu *context = &vcpu->arch.mmu;
2418
2419 context->new_cr3 = nonpaging_new_cr3;
2420 context->page_fault = tdp_page_fault;
2421 context->free = nonpaging_free;
2422 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2423 context->sync_page = nonpaging_sync_page;
a7052897 2424 context->invlpg = nonpaging_invlpg;
67253af5 2425 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2426 context->root_hpa = INVALID_PAGE;
2427
2428 if (!is_paging(vcpu)) {
2429 context->gva_to_gpa = nonpaging_gva_to_gpa;
2430 context->root_level = 0;
2431 } else if (is_long_mode(vcpu)) {
82725b20 2432 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2433 context->gva_to_gpa = paging64_gva_to_gpa;
2434 context->root_level = PT64_ROOT_LEVEL;
2435 } else if (is_pae(vcpu)) {
82725b20 2436 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2437 context->gva_to_gpa = paging64_gva_to_gpa;
2438 context->root_level = PT32E_ROOT_LEVEL;
2439 } else {
82725b20 2440 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2441 context->gva_to_gpa = paging32_gva_to_gpa;
2442 context->root_level = PT32_ROOT_LEVEL;
2443 }
2444
2445 return 0;
2446}
2447
2448static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2449{
a770f6f2
AK		 2450 int r;
2451
6aa8b732 2452 ASSERT(vcpu);
ad312c7c 2453 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2454
2455 if (!is_paging(vcpu))
a770f6f2 2456 r = nonpaging_init_context(vcpu);
a9058ecd 2457 else if (is_long_mode(vcpu))
a770f6f2 2458 r = paging64_init_context(vcpu);
6aa8b732 2459 else if (is_pae(vcpu))
a770f6f2 2460 r = paging32E_init_context(vcpu);
6aa8b732 2461 else
a770f6f2
AK		 2462 r = paging32_init_context(vcpu);
2463
5b7e0102 2464 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3dbe1415 2465 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
a770f6f2
AK		 2466
2467 return r;
6aa8b732
AK		 2468}
2469
fb72d167
JR		 2470static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2471{
35149e21
AL		 2472 vcpu->arch.update_pte.pfn = bad_pfn;
2473
fb72d167
JR		 2474 if (tdp_enabled)
2475 return init_kvm_tdp_mmu(vcpu);
2476 else
2477 return init_kvm_softmmu(vcpu);
2478}
2479
6aa8b732
AK		 2480static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2481{
2482 ASSERT(vcpu);
62ad0755
SY		 2483 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2484 /* mmu.free() should set root_hpa = INVALID_PAGE */
ad312c7c 2485 vcpu->arch.mmu.free(vcpu);
6aa8b732
AK		 2486}
2487
2488int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2489{
2490 destroy_kvm_mmu(vcpu);
2491 return init_kvm_mmu(vcpu);
2492}
8668a3c4 2493EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2494
2495int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2496{
714b93da
AK		 2497 int r;
2498
e2dec939 2499 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2500 if (r)
2501 goto out;
8986ecc0 2502 r = mmu_alloc_roots(vcpu);
8facbbff 2503 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 2504 mmu_sync_roots(vcpu);
aaee2c94 2505 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2506 if (r)
2507 goto out;
3662cb1c 2508 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2509 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2510out:
2511 return r;
6aa8b732 2512}
17c3ba9d
AK		 2513EXPORT_SYMBOL_GPL(kvm_mmu_load);
2514
2515void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2516{
2517 mmu_free_roots(vcpu);
2518}
6aa8b732 2519
09072daf 2520static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2521 struct kvm_mmu_page *sp,
ac1b714e
AK		 2522 u64 *spte)
2523{
2524 u64 pte;
2525 struct kvm_mmu_page *child;
2526
2527 pte = *spte;
c7addb90 2528 if (is_shadow_present_pte(pte)) {
776e6633 2529 if (is_last_spte(pte, sp->role.level))
290fc38d 2530 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2531 else {
2532 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2533 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2534 }
2535 }
d555c333 2536 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2537 if (is_large_pte(pte))
2538 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2539}
2540
0028425f 2541static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2542 struct kvm_mmu_page *sp,
0028425f 2543 u64 *spte,
489f1d65 2544 const void *new)
0028425f 2545{
30945387 2546 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2547 ++vcpu->kvm->stat.mmu_pde_zapped;
2548 return;
30945387 2549 }
0028425f 2550
4cee5764 2551 ++vcpu->kvm->stat.mmu_pte_updated;
5b7e0102 2552 if (!sp->role.cr4_pae)
489f1d65 2553 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2554 else
489f1d65 2555 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2556}
2557
79539cec
AK		 2558static bool need_remote_flush(u64 old, u64 new)
2559{
2560 if (!is_shadow_present_pte(old))
2561 return false;
2562 if (!is_shadow_present_pte(new))
2563 return true;
2564 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2565 return true;
2566 old ^= PT64_NX_MASK;
2567 new ^= PT64_NX_MASK;
2568 return (old & ~new & PT64_PERM_MASK) != 0;
2569}
2570
2571static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2572{
2573 if (need_remote_flush(old, new))
2574 kvm_flush_remote_tlbs(vcpu->kvm);
2575 else
2576 kvm_mmu_flush_tlb(vcpu);
2577}
2578
12b7d28f
AK		 2579static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2580{
ad312c7c 2581 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2582
7b52345e 2583 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2584}
2585
d7824fff 2586static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
72016f3a 2587 u64 gpte)
d7824fff
AK		 2588{
2589 gfn_t gfn;
35149e21 2590 pfn_t pfn;
d7824fff 2591
43a3795a 2592 if (!is_present_gpte(gpte))
d7824fff
AK		 2593 return;
2594 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2595
e930bffe 2596 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2597 smp_rmb();
35149e21 2598 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2599
35149e21
AL		 2600 if (is_error_pfn(pfn)) {
2601 kvm_release_pfn_clean(pfn);
d196e343
AK		 2602 return;
2603 }
d7824fff 2604 vcpu->arch.update_pte.gfn = gfn;
35149e21 2605 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2606}
2607
1b7fcd32
AK		 2608static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2609{
2610 u64 *spte = vcpu->arch.last_pte_updated;
2611
2612 if (spte
2613 && vcpu->arch.last_pte_gfn == gfn
2614 && shadow_accessed_mask
2615 && !(*spte & shadow_accessed_mask)
2616 && is_shadow_present_pte(*spte))
2617 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2618}
2619
09072daf 2620void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2621 const u8 *new, int bytes,
2622 bool guest_initiated)
da4a00f0 2623{
9b7a0325 2624 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2625 struct kvm_mmu_page *sp;
0e7bc4b9 2626 struct hlist_node *node, *n;
9b7a0325
AK		 2627 struct hlist_head *bucket;
2628 unsigned index;
489f1d65 2629 u64 entry, gentry;
9b7a0325 2630 u64 *spte;
9b7a0325 2631 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2632 unsigned pte_size;
9b7a0325 2633 unsigned page_offset;
0e7bc4b9 2634 unsigned misaligned;
fce0657f 2635 unsigned quadrant;
9b7a0325 2636 int level;
86a5ba02 2637 int flooded = 0;
ac1b714e 2638 int npte;
489f1d65 2639 int r;
08e850c6 2640 int invlpg_counter;
9b7a0325 2641
b8688d51 2642 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 2643
08e850c6 2644 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 2645
2646 /*
2647 * Assume that the pte write on a page table of the same type
2648 * as the current vcpu paging mode. This is nearly always true
2649 * (might be false while changing modes). Note it is verified later
2650 * by update_pte().
2651 */
08e850c6 2652 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 2653 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 2654 if (is_pae(vcpu)) {
2655 gpa &= ~(gpa_t)7;
2656 bytes = 8;
2657 }
2658 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 2659 if (r)
2660 gentry = 0;
08e850c6
AK		 2661 new = (const u8 *)&gentry;
2662 }
2663
2664 switch (bytes) {
2665 case 4:
2666 gentry = *(const u32 *)new;
2667 break;
2668 case 8:
2669 gentry = *(const u64 *)new;
2670 break;
2671 default:
2672 gentry = 0;
2673 break;
72016f3a
AK		 2674 }
2675
2676 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
aaee2c94 2677 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 2678 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
2679 gentry = 0;
1b7fcd32 2680 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2681 kvm_mmu_free_some_pages(vcpu);
4cee5764 2682 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2683 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2684 if (guest_initiated) {
2685 if (gfn == vcpu->arch.last_pt_write_gfn
2686 && !last_updated_pte_accessed(vcpu)) {
2687 ++vcpu->arch.last_pt_write_count;
2688 if (vcpu->arch.last_pt_write_count >= 3)
2689 flooded = 1;
2690 } else {
2691 vcpu->arch.last_pt_write_gfn = gfn;
2692 vcpu->arch.last_pt_write_count = 1;
2693 vcpu->arch.last_pte_updated = NULL;
2694 }
86a5ba02 2695 }
1ae0a13d 2696 index = kvm_page_table_hashfn(gfn);
f05e70ac 2697 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
3246af0e
XG		 2698
2699restart:
4db35314 2700 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2701 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2702 continue;
5b7e0102 2703 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 2704 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2705 misaligned |= bytes < 4;
86a5ba02 2706 if (misaligned || flooded) {
0e7bc4b9
AK		 2707 /*
2708 * Misaligned accesses are too much trouble to fix
2709 * up; also, they usually indicate a page is not used
2710 * as a page table.
86a5ba02
AK		 2711 *
2712 * If we're seeing too many writes to a page,
2713 * it may no longer be a page table, or we may be
2714 * forking, in which case it is better to unmap the
2715 * page.
0e7bc4b9
AK		 2716 */
2717 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2718 gpa, bytes, sp->role.word);
07385413 2719 if (kvm_mmu_zap_page(vcpu->kvm, sp))
3246af0e 2720 goto restart;
4cee5764 2721 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2722 continue;
2723 }
9b7a0325 2724 page_offset = offset;
4db35314 2725 level = sp->role.level;
ac1b714e 2726 npte = 1;
5b7e0102 2727 if (!sp->role.cr4_pae) {
ac1b714e
AK		 2728 page_offset <<= 1; /* 32->64 */
2729 /*
2730 * A 32-bit pde maps 4MB while the shadow pdes map
2731 * only 2MB. So we need to double the offset again
2732 * and zap two pdes instead of one.
2733 */
2734 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2735 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2736 page_offset <<= 1;
2737 npte = 2;
2738 }
fce0657f 2739 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2740 page_offset &= ~PAGE_MASK;
4db35314 2741 if (quadrant != sp->role.quadrant)
fce0657f 2742 continue;
9b7a0325 2743 }
4db35314 2744 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 2745 while (npte--) {
79539cec 2746 entry = *spte;
4db35314 2747 mmu_pte_write_zap_pte(vcpu, sp, spte);
72016f3a
AK		 2748 if (gentry)
2749 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
79539cec 2750 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2751 ++spte;
9b7a0325 2752 }
9b7a0325 2753 }
c7addb90 2754 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2755 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2756 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2757 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2758 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2759 }
da4a00f0
AK		 2760}
2761
a436036b
AK		 2762int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2763{
10589a46
MT		 2764 gpa_t gpa;
2765 int r;
a436036b 2766
60f24784
AK		 2767 if (tdp_enabled)
2768 return 0;
2769
1871c602 2770 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 2771
aaee2c94 2772 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2773 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2774 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2775 return r;
a436036b 2776}
577bdc49 2777EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2778
22d95b12 2779void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2780{
3b80fffe
IE		 2781 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2782 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2783 struct kvm_mmu_page *sp;
ebeace86 2784
f05e70ac 2785 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2786 struct kvm_mmu_page, link);
2787 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2788 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2789 }
2790}
ebeace86 2791
3067714c
AK		 2792int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2793{
2794 int r;
2795 enum emulation_result er;
2796
ad312c7c 2797 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2798 if (r < 0)
2799 goto out;
2800
2801 if (!r) {
2802 r = 1;
2803 goto out;
2804 }
2805
b733bfb5
AK		 2806 r = mmu_topup_memory_caches(vcpu);
2807 if (r)
2808 goto out;
2809
851ba692 2810 er = emulate_instruction(vcpu, cr2, error_code, 0);
3067714c
AK		 2811
2812 switch (er) {
2813 case EMULATE_DONE:
2814 return 1;
2815 case EMULATE_DO_MMIO:
2816 ++vcpu->stat.mmio_exits;
6d77dbfc 2817 /* fall through */
3067714c 2818 case EMULATE_FAIL:
3f5d18a9 2819 return 0;
3067714c
AK		 2820 default:
2821 BUG();
2822 }
2823out:
3067714c
AK		 2824 return r;
2825}
2826EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2827
a7052897
MT		 2828void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2829{
a7052897 2830 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2831 kvm_mmu_flush_tlb(vcpu);
2832 ++vcpu->stat.invlpg;
2833}
2834EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2835
18552672
JR		 2836void kvm_enable_tdp(void)
2837{
2838 tdp_enabled = true;
2839}
2840EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2841
5f4cb662
JR		 2842void kvm_disable_tdp(void)
2843{
2844 tdp_enabled = false;
2845}
2846EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2847
6aa8b732
AK		 2848static void free_mmu_pages(struct kvm_vcpu *vcpu)
2849{
ad312c7c 2850 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2851}
2852
2853static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2854{
17ac10ad 2855 struct page *page;
6aa8b732
AK		 2856 int i;
2857
2858 ASSERT(vcpu);
2859
17ac10ad
AK		 2860 /*
2861 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2862 * Therefore we need to allocate shadow page tables in the first
2863 * 4GB of memory, which happens to fit the DMA32 zone.
2864 */
2865 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2866 if (!page)
d7fa6ab2
WY		 2867 return -ENOMEM;
2868
ad312c7c 2869 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2870 for (i = 0; i < 4; ++i)
ad312c7c 2871 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2872
6aa8b732 2873 return 0;
6aa8b732
AK		 2874}
2875
8018c27b 2876int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2877{
6aa8b732 2878 ASSERT(vcpu);
ad312c7c 2879 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2880
8018c27b
IM		 2881 return alloc_mmu_pages(vcpu);
2882}
6aa8b732 2883
8018c27b
IM		 2884int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2885{
2886 ASSERT(vcpu);
ad312c7c 2887 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2888
8018c27b 2889 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2890}
2891
2892void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2893{
2894 ASSERT(vcpu);
2895
2896 destroy_kvm_mmu(vcpu);
2897 free_mmu_pages(vcpu);
714b93da 2898 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2899}
2900
90cb0529 2901void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2902{
4db35314 2903 struct kvm_mmu_page *sp;
6aa8b732 2904
f05e70ac 2905 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2906 int i;
2907 u64 *pt;
2908
291f26bc 2909 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2910 continue;
2911
4db35314 2912 pt = sp->spt;
6aa8b732
AK		 2913 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2914 /* avoid RMW */
9647c14c 2915 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2916 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2917 }
171d595d 2918 kvm_flush_remote_tlbs(kvm);
6aa8b732 2919}
37a7d8b0 2920
90cb0529 2921void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2922{
4db35314 2923 struct kvm_mmu_page *sp, *node;
e0fa826f 2924
aaee2c94 2925 spin_lock(&kvm->mmu_lock);
3246af0e 2926restart:
f05e70ac 2927 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413 2928 if (kvm_mmu_zap_page(kvm, sp))
3246af0e
XG		 2929 goto restart;
2930
aaee2c94 2931 spin_unlock(&kvm->mmu_lock);
e0fa826f 2932
90cb0529 2933 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2934}
2935
d35b8dd9 2936static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
3ee16c81
IE		 2937{
2938 struct kvm_mmu_page *page;
2939
2940 page = container_of(kvm->arch.active_mmu_pages.prev,
2941 struct kvm_mmu_page, link);
54a4f023 2942 return kvm_mmu_zap_page(kvm, page);
3ee16c81
IE		 2943}
2944
7f8275d0 2945static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3ee16c81
IE		 2946{
2947 struct kvm *kvm;
2948 struct kvm *kvm_freed = NULL;
2949 int cache_count = 0;
2950
2951 spin_lock(&kvm_lock);
2952
2953 list_for_each_entry(kvm, &vm_list, vm_list) {
d35b8dd9 2954 int npages, idx, freed_pages;
3ee16c81 2955
f656ce01 2956 idx = srcu_read_lock(&kvm->srcu);
3ee16c81
IE		 2957 spin_lock(&kvm->mmu_lock);
2958 npages = kvm->arch.n_alloc_mmu_pages -
2959 kvm->arch.n_free_mmu_pages;
2960 cache_count += npages;
2961 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
d35b8dd9
GJ		 2962 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm);
2963 cache_count -= freed_pages;
3ee16c81
IE		 2964 kvm_freed = kvm;
2965 }
2966 nr_to_scan--;
2967
2968 spin_unlock(&kvm->mmu_lock);
f656ce01 2969 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 2970 }
2971 if (kvm_freed)
2972 list_move_tail(&kvm_freed->vm_list, &vm_list);
2973
2974 spin_unlock(&kvm_lock);
2975
2976 return cache_count;
2977}
2978
2979static struct shrinker mmu_shrinker = {
2980 .shrink = mmu_shrink,
2981 .seeks = DEFAULT_SEEKS * 10,
2982};
2983
2ddfd20e 2984static void mmu_destroy_caches(void)
b5a33a75
AK		 2985{
2986 if (pte_chain_cache)
2987 kmem_cache_destroy(pte_chain_cache);
2988 if (rmap_desc_cache)
2989 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2990 if (mmu_page_header_cache)
2991 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2992}
2993
3ee16c81
IE		 2994void kvm_mmu_module_exit(void)
2995{
2996 mmu_destroy_caches();
2997 unregister_shrinker(&mmu_shrinker);
2998}
2999
b5a33a75
AK		 3000int kvm_mmu_module_init(void)
3001{
3002 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3003 sizeof(struct kvm_pte_chain),
20c2df83 3004 0, 0, NULL);
b5a33a75
AK		 3005 if (!pte_chain_cache)
3006 goto nomem;
3007 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3008 sizeof(struct kvm_rmap_desc),
20c2df83 3009 0, 0, NULL);
b5a33a75
AK		 3010 if (!rmap_desc_cache)
3011 goto nomem;
3012
d3d25b04
AK		 3013 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3014 sizeof(struct kvm_mmu_page),
20c2df83 3015 0, 0, NULL);
d3d25b04
AK		 3016 if (!mmu_page_header_cache)
3017 goto nomem;
3018
3ee16c81
IE		 3019 register_shrinker(&mmu_shrinker);
3020
b5a33a75
AK		 3021 return 0;
3022
3023nomem:
3ee16c81 3024 mmu_destroy_caches();
b5a33a75
AK		 3025 return -ENOMEM;
3026}
3027
3ad82a7e
ZX		 3028/*
3029 * Caculate mmu pages needed for kvm.
3030 */
3031unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3032{
3033 int i;
3034 unsigned int nr_mmu_pages;
3035 unsigned int nr_pages = 0;
bc6678a3 3036 struct kvm_memslots *slots;
3ad82a7e 3037
90d83dc3
LJ		 3038 slots = kvm_memslots(kvm);
3039
bc6678a3
MT		 3040 for (i = 0; i < slots->nmemslots; i++)
3041 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3042
3043 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3044 nr_mmu_pages = max(nr_mmu_pages,
3045 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3046
3047 return nr_mmu_pages;
3048}
3049
2f333bcb
MT		 3050static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3051 unsigned len)
3052{
3053 if (len > buffer->len)
3054 return NULL;
3055 return buffer->ptr;
3056}
3057
3058static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3059 unsigned len)
3060{
3061 void *ret;
3062
3063 ret = pv_mmu_peek_buffer(buffer, len);
3064 if (!ret)
3065 return ret;
3066 buffer->ptr += len;
3067 buffer->len -= len;
3068 buffer->processed += len;
3069 return ret;
3070}
3071
3072static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3073 gpa_t addr, gpa_t value)
3074{
3075 int bytes = 8;
3076 int r;
3077
3078 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3079 bytes = 4;
3080
3081 r = mmu_topup_memory_caches(vcpu);
3082 if (r)
3083 return r;
3084
3200f405 3085 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3086 return -EFAULT;
3087
3088 return 1;
3089}
3090
3091static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3092{
a8cd0244 3093 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3094 return 1;
3095}
3096
3097static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3098{
3099 spin_lock(&vcpu->kvm->mmu_lock);
3100 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3101 spin_unlock(&vcpu->kvm->mmu_lock);
3102 return 1;
3103}
3104
3105static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3106 struct kvm_pv_mmu_op_buffer *buffer)
3107{
3108 struct kvm_mmu_op_header *header;
3109
3110 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3111 if (!header)
3112 return 0;
3113 switch (header->op) {
3114 case KVM_MMU_OP_WRITE_PTE: {
3115 struct kvm_mmu_op_write_pte *wpte;
3116
3117 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3118 if (!wpte)
3119 return 0;
3120 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3121 wpte->pte_val);
3122 }
3123 case KVM_MMU_OP_FLUSH_TLB: {
3124 struct kvm_mmu_op_flush_tlb *ftlb;
3125
3126 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3127 if (!ftlb)
3128 return 0;
3129 return kvm_pv_mmu_flush_tlb(vcpu);
3130 }
3131 case KVM_MMU_OP_RELEASE_PT: {
3132 struct kvm_mmu_op_release_pt *rpt;
3133
3134 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3135 if (!rpt)
3136 return 0;
3137 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3138 }
3139 default: return 0;
3140 }
3141}
3142
3143int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3144 gpa_t addr, unsigned long *ret)
3145{
3146 int r;
6ad18fba 3147 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3148
6ad18fba
DH		 3149 buffer->ptr = buffer->buf;
3150 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3151 buffer->processed = 0;
2f333bcb 3152
6ad18fba 3153 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3154 if (r)
3155 goto out;
3156
6ad18fba
DH		 3157 while (buffer->len) {
3158 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3159 if (r < 0)
3160 goto out;
3161 if (r == 0)
3162 break;
3163 }
3164
3165 r = 1;
3166out:
6ad18fba 3167 *ret = buffer->processed;
2f333bcb
MT		 3168 return r;
3169}
3170
94d8b056
MT		 3171int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3172{
3173 struct kvm_shadow_walk_iterator iterator;
3174 int nr_sptes = 0;
3175
3176 spin_lock(&vcpu->kvm->mmu_lock);
3177 for_each_shadow_entry(vcpu, addr, iterator) {
3178 sptes[iterator.level-1] = *iterator.sptep;
3179 nr_sptes++;
3180 if (!is_shadow_present_pte(*iterator.sptep))
3181 break;
3182 }
3183 spin_unlock(&vcpu->kvm->mmu_lock);
3184
3185 return nr_sptes;
3186}
3187EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3188
37a7d8b0
AK		 3189#ifdef AUDIT
3190
3191static const char *audit_msg;
3192
3193static gva_t canonicalize(gva_t gva)
3194{
3195#ifdef CONFIG_X86_64
3196 gva = (long long)(gva << 16) >> 16;
3197#endif
3198 return gva;
3199}
3200
08a3732b 3201
805d32de 3202typedef void (*inspect_spte_fn) (struct kvm *kvm, u64 *sptep);
08a3732b
MT		 3203
3204static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3205 inspect_spte_fn fn)
3206{
3207 int i;
3208
3209 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3210 u64 ent = sp->spt[i];
3211
3212 if (is_shadow_present_pte(ent)) {
2920d728 3213 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3214 struct kvm_mmu_page *child;
3215 child = page_header(ent & PT64_BASE_ADDR_MASK);
3216 __mmu_spte_walk(kvm, child, fn);
2920d728 3217 } else
805d32de 3218 fn(kvm, &sp->spt[i]);
08a3732b
MT		 3219 }
3220 }
3221}
3222
3223static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3224{
3225 int i;
3226 struct kvm_mmu_page *sp;
3227
3228 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3229 return;
3230 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3231 hpa_t root = vcpu->arch.mmu.root_hpa;
3232 sp = page_header(root);
3233 __mmu_spte_walk(vcpu->kvm, sp, fn);
3234 return;
3235 }
3236 for (i = 0; i < 4; ++i) {
3237 hpa_t root = vcpu->arch.mmu.pae_root[i];
3238
3239 if (root && VALID_PAGE(root)) {
3240 root &= PT64_BASE_ADDR_MASK;
3241 sp = page_header(root);
3242 __mmu_spte_walk(vcpu->kvm, sp, fn);
3243 }
3244 }
3245 return;
3246}
3247
37a7d8b0
AK		 3248static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3249 gva_t va, int level)
3250{
3251 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3252 int i;
3253 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3254
3255 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3256 u64 ent = pt[i];
3257
c7addb90 3258 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3259 continue;
3260
3261 va = canonicalize(va);
2920d728
MT		 3262 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3263 audit_mappings_page(vcpu, ent, va, level - 1);
3264 else {
1871c602 3265 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
34382539
JK		 3266 gfn_t gfn = gpa >> PAGE_SHIFT;
3267 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3268 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3269
2aaf65e8
MT		 3270 if (is_error_pfn(pfn)) {
3271 kvm_release_pfn_clean(pfn);
3272 continue;
3273 }
3274
c7addb90 3275 if (is_shadow_present_pte(ent)
37a7d8b0 3276 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3277 printk(KERN_ERR "xx audit error: (%s) levels %d"
3278 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3279 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3280 va, gpa, hpa, ent,
3281 is_shadow_present_pte(ent));
c7addb90
AK		 3282 else if (ent == shadow_notrap_nonpresent_pte
3283 && !is_error_hpa(hpa))
3284 printk(KERN_ERR "audit: (%s) notrap shadow,"
3285 " valid guest gva %lx\n", audit_msg, va);
35149e21 3286 kvm_release_pfn_clean(pfn);
c7addb90 3287
37a7d8b0
AK		 3288 }
3289 }
3290}
3291
3292static void audit_mappings(struct kvm_vcpu *vcpu)
3293{
1ea252af 3294 unsigned i;
37a7d8b0 3295
ad312c7c
ZX		 3296 if (vcpu->arch.mmu.root_level == 4)
3297 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3298 else
3299 for (i = 0; i < 4; ++i)
ad312c7c 3300 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3301 audit_mappings_page(vcpu,
ad312c7c 3302 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3303 i << 30,
3304 2);
3305}
3306
3307static int count_rmaps(struct kvm_vcpu *vcpu)
3308{
805d32de
XG		 3309 struct kvm *kvm = vcpu->kvm;
3310 struct kvm_memslots *slots;
37a7d8b0 3311 int nmaps = 0;
bc6678a3 3312 int i, j, k, idx;
37a7d8b0 3313
bc6678a3 3314 idx = srcu_read_lock(&kvm->srcu);
90d83dc3 3315 slots = kvm_memslots(kvm);
37a7d8b0 3316 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
bc6678a3 3317 struct kvm_memory_slot *m = &slots->memslots[i];
37a7d8b0
AK		 3318 struct kvm_rmap_desc *d;
3319
3320 for (j = 0; j < m->npages; ++j) {
290fc38d 3321 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3322
290fc38d 3323 if (!*rmapp)
37a7d8b0 3324 continue;
290fc38d 3325 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3326 ++nmaps;
3327 continue;
3328 }
290fc38d 3329 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3330 while (d) {
3331 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3332 if (d->sptes[k])
37a7d8b0
AK		 3333 ++nmaps;
3334 else
3335 break;
3336 d = d->more;
3337 }
3338 }
3339 }
bc6678a3 3340 srcu_read_unlock(&kvm->srcu, idx);
37a7d8b0
AK		 3341 return nmaps;
3342}
3343
805d32de 3344void inspect_spte_has_rmap(struct kvm *kvm, u64 *sptep)
08a3732b
MT		 3345{
3346 unsigned long *rmapp;
3347 struct kvm_mmu_page *rev_sp;
3348 gfn_t gfn;
3349
3350 if (*sptep & PT_WRITABLE_MASK) {
3351 rev_sp = page_header(__pa(sptep));
3352 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3353
3354 if (!gfn_to_memslot(kvm, gfn)) {
3355 if (!printk_ratelimit())
3356 return;
3357 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3358 audit_msg, gfn);
3359 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
805d32de 3360 audit_msg, (long int)(sptep - rev_sp->spt),
08a3732b
MT		 3361 rev_sp->gfn);
3362 dump_stack();
3363 return;
3364 }
3365
2920d728 3366 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
805d32de 3367 rev_sp->role.level);
08a3732b
MT		 3368 if (!*rmapp) {
3369 if (!printk_ratelimit())
3370 return;
3371 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3372 audit_msg, *sptep);
3373 dump_stack();
3374 }
3375 }
3376
3377}
3378
3379void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3380{
3381 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3382}
3383
3384static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3385{
4db35314 3386 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3387 int i;
3388
f05e70ac 3389 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3390 u64 *pt = sp->spt;
37a7d8b0 3391
4db35314 3392 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3393 continue;
3394
3395 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3396 u64 ent = pt[i];
3397
3398 if (!(ent & PT_PRESENT_MASK))
3399 continue;
3400 if (!(ent & PT_WRITABLE_MASK))
3401 continue;
805d32de 3402 inspect_spte_has_rmap(vcpu->kvm, &pt[i]);
37a7d8b0
AK		 3403 }
3404 }
08a3732b 3405 return;
37a7d8b0
AK		 3406}
3407
3408static void audit_rmap(struct kvm_vcpu *vcpu)
3409{
08a3732b
MT		 3410 check_writable_mappings_rmap(vcpu);
3411 count_rmaps(vcpu);
37a7d8b0
AK		 3412}
3413
3414static void audit_write_protection(struct kvm_vcpu *vcpu)
3415{
4db35314 3416 struct kvm_mmu_page *sp;
290fc38d
IE		 3417 struct kvm_memory_slot *slot;
3418 unsigned long *rmapp;
e58b0f9e 3419 u64 *spte;
290fc38d 3420 gfn_t gfn;
37a7d8b0 3421
f05e70ac 3422 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3423 if (sp->role.direct)
37a7d8b0 3424 continue;
e58b0f9e
MT		 3425 if (sp->unsync)
3426 continue;
37a7d8b0 3427
4db35314 3428 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3429 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3430 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3431
3432 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3433 while (spte) {
3434 if (*spte & PT_WRITABLE_MASK)
3435 printk(KERN_ERR "%s: (%s) shadow page has "
3436 "writable mappings: gfn %lx role %x\n",
b8688d51 3437 __func__, audit_msg, sp->gfn,
4db35314 3438 sp->role.word);
e58b0f9e
MT		 3439 spte = rmap_next(vcpu->kvm, rmapp, spte);
3440 }
37a7d8b0
AK		 3441 }
3442}
3443
3444static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3445{
3446 int olddbg = dbg;
3447
3448 dbg = 0;
3449 audit_msg = msg;
3450 audit_rmap(vcpu);
3451 audit_write_protection(vcpu);
2aaf65e8
MT		 3452 if (strcmp("pre pte write", audit_msg) != 0)
3453 audit_mappings(vcpu);
08a3732b 3454 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3455 dbg = olddbg;
3456}
3457
3458#endif
Linux kernel - Deliverables
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