[deliverable/linux.git] / arch / x86 / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#define CMPXCHG cmpxchg
	#else
	#define CMPXCHG cmpxchg64
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
	#define CMPXCHG cmpxchg
#else
	#error Invalid PTTYPE value
#endif

#define gpte_to_gfn FNAME(gpte_to_gfn)
#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
	unsigned pt_access;
	unsigned pte_access;
	gfn_t gfn;
	u32 error_code;
};

static gfn_t gpte_to_gfn(pt_element_t gpte)
{
	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
{
	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
			 gfn_t table_gfn, unsigned index,
			 pt_element_t orig_pte, pt_element_t new_pte)
{
	pt_element_t ret;
	pt_element_t *table;
	struct page *page;

	down_read(&current->mm->mmap_sem);
	page = gfn_to_page(kvm, table_gfn);
	up_read(&current->mm->mmap_sem);

	table = kmap_atomic(page, KM_USER0);

	ret = CMPXCHG(&table[index], orig_pte, new_pte);

	kunmap_atomic(table, KM_USER0);

	kvm_release_page_dirty(page);

	return (ret != orig_pte);
}

static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
{
	unsigned access;

	access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
#if PTTYPE == 64
	if (is_nx(vcpu))
		access &= ~(gpte >> PT64_NX_SHIFT);
#endif
	return access;
}

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index, pt_access, pte_access;
	gpa_t pte_gpa;

	pgprintk("%s: addr %lx\n", __func__, addr);
walk:
	walker->level = vcpu->arch.mmu.root_level;
	pte = vcpu->arch.cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
		if (!is_present_pte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	pt_access = ACC_ALL;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = gpte_to_gfn(pte);
		pte_gpa = gfn_to_gpa(table_gfn);
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		walker->pte_gpa[walker->level - 1] = pte_gpa;
		pgprintk("%s: table_gfn[%d] %lx\n", __func__,
			 walker->level - 1, table_gfn);

		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));

		if (!is_present_pte(pte))
			goto not_present;

		if (write_fault && !is_writeble_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
			    index, pte, pte|PT_ACCESSED_MASK))
				goto walk;
			pte |= PT_ACCESSED_MASK;
		}

		pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);

		walker->ptes[walker->level - 1] = pte;

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = gpte_to_gfn(pte);
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (pte & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = gpte_to_gfn_pde(pte);
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			if (PTTYPE == 32 && is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);
			break;
		}

		pt_access = pte_access;
		--walker->level;
	}

	if (write_fault && !is_dirty_pte(pte)) {
		bool ret;

		mark_page_dirty(vcpu->kvm, table_gfn);
		ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
			    pte|PT_DIRTY_MASK);
		if (ret)
			goto walk;
		pte |= PT_DIRTY_MASK;
		kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
		walker->ptes[walker->level - 1] = pte;
	}

	walker->pt_access = pt_access;
	walker->pte_access = pte_access;
	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
		 __func__, (u64)pte, pt_access, pte_access);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte)
{
	pt_element_t gpte;
	unsigned pte_access;
	pfn_t pfn;
	int largepage = vcpu->arch.update_pte.largepage;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
		return;
	pfn = vcpu->arch.update_pte.pfn;
	if (is_error_pfn(pfn))
		return;
	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
		return;
	kvm_get_pfn(pfn);
	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
		     gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
		     pfn, true);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int largepage,
			 int *ptwrite, pfn_t pfn)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;
	unsigned access = walker->pt_access;

	if (!is_present_pte(walker->ptes[walker->level - 1]))
		return NULL;

	shadow_addr = vcpu->arch.mmu.root_hpa;
	level = vcpu->arch.mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (largepage && level == PT_DIRECTORY_LEVEL)
			break;

		if (is_shadow_present_pte(*shadow_ent)
		    && !is_large_pte(*shadow_ent)) {
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			continue;
		}

		if (is_large_pte(*shadow_ent))
			rmap_remove(vcpu->kvm, shadow_ent);

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			if (!is_dirty_pte(walker->ptes[level - 1]))
				access &= ~ACC_WRITE_MASK;
			table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, access,
					       shadow_ent);
		if (!metaphysical) {
			int r;
			pt_element_t curr_pte;
			r = kvm_read_guest_atomic(vcpu->kvm,
						  walker->pte_gpa[level - 2],
						  &curr_pte, sizeof(curr_pte));
			if (r || curr_pte != walker->ptes[level - 2]) {
				kvm_release_pfn_clean(pfn);
				return NULL;
			}
		}
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		set_shadow_pte(shadow_ent, shadow_pte);
	}

	mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
		     user_fault, write_fault,
		     walker->ptes[walker->level-1] & PT_DIRTY_MASK,
		     ptwrite, largepage, walker->gfn, pfn, false);

	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;
	pfn_t pfn;
	int largepage = 0;
	unsigned long mmu_seq;

	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __func__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	down_read(&current->mm->mmap_sem);
	if (walker.level == PT_DIRECTORY_LEVEL) {
		gfn_t large_gfn;
		large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
		if (is_largepage_backed(vcpu, large_gfn)) {
			walker.gfn = large_gfn;
			largepage = 1;
		}
	}
	mmu_seq = vcpu->kvm->mmu_notifier_seq;
	/* implicit mb(), we'll read before PT lock is unlocked */
	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
	up_read(&current->mm->mmap_sem);

	/* mmio */
	if (is_error_pfn(pfn)) {
		pgprintk("gfn %lx is mmio\n", walker.gfn);
		kvm_release_pfn_clean(pfn);
		return 1;
	}

	spin_lock(&vcpu->kvm->mmu_lock);
	if (mmu_notifier_retry(vcpu, mmu_seq))
		goto out_unlock;
	kvm_mmu_free_some_pages(vcpu);
	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  largepage, &write_pt, pfn);

	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");
	spin_unlock(&vcpu->kvm->mmu_lock);

	return write_pt;

out_unlock:
	spin_unlock(&vcpu->kvm->mmu_lock);
	kvm_release_pfn_clean(pfn);
	return 0;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = gfn_to_gpa(walker.gfn);
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i, j, offset, r;
	pt_element_t pt[256 / sizeof(pt_element_t)];
	gpa_t pte_gpa;

	if (sp->role.metaphysical
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	pte_gpa = gfn_to_gpa(sp->gfn);
	if (PTTYPE == 32) {
		offset = sp->role.quadrant << PT64_LEVEL_BITS;
		pte_gpa += offset * sizeof(pt_element_t);
	}

	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
		r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
		pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
		for (j = 0; j < ARRAY_SIZE(pt); ++j)
			if (r || is_present_pte(pt[j]))
				sp->spt[i+j] = shadow_trap_nonpresent_pte;
			else
				sp->spt[i+j] = shadow_notrap_nonpresent_pte;
	}
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
#undef gpte_to_gfn
#undef gpte_to_gfn_pde
#undef CMPXCHG
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
6aa8b732	32	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	33	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	34	#ifdef CONFIG_X86_64
cea0f0e7 AK	35	#define PT_MAX_FULL_LEVELS 4
b3e4e63f	36	#define CMPXCHG cmpxchg
cea0f0e7	37	#else
b3e4e63f	38	#define CMPXCHG cmpxchg64
cea0f0e7 AK	39	#define PT_MAX_FULL_LEVELS 2
cea0f0e7 AK	40	#endif
6aa8b732 AK	41	#elif PTTYPE == 32
	42	#define pt_element_t u32
	43	#define guest_walker guest_walker32
	44	#define FNAME(name) paging##32_##name
	45	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	46	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	47	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
6aa8b732	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	49	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
b3e4e63f	51	#define CMPXCHG cmpxchg
6aa8b732 AK	52	#else
	53	#error Invalid PTTYPE value
	54	#endif
	55
5fb07ddb AK	56	#define gpte_to_gfn FNAME(gpte_to_gfn)
	57	#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
	58
6aa8b732 AK	59	/*
	60	* The guest_walker structure emulates the behavior of the hardware page
	61	* table walker.
	62	*/
	63	struct guest_walker {
	64	int level;
cea0f0e7	65	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
7819026e MT	66	pt_element_t ptes[PT_MAX_FULL_LEVELS];
7819026e MT	67	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
fe135d2c AK	68	unsigned pt_access;
fe135d2c AK	69	unsigned pte_access;
815af8d4	70	gfn_t gfn;
7993ba43	71	u32 error_code;
6aa8b732 AK	72	};
6aa8b732 AK	73
5fb07ddb AK	74	static gfn_t gpte_to_gfn(pt_element_t gpte)
	75	{
	76	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
	77	}
	78
	79	static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
	80	{
	81	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
	82	}
	83
b3e4e63f MT	84	static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
	85	gfn_t table_gfn, unsigned index,
	86	pt_element_t orig_pte, pt_element_t new_pte)
	87	{
	88	pt_element_t ret;
	89	pt_element_t *table;
	90	struct page *page;
	91
72dc67a6	92	down_read(&current->mm->mmap_sem);
b3e4e63f	93	page = gfn_to_page(kvm, table_gfn);
72dc67a6 IE	94	up_read(&current->mm->mmap_sem);
72dc67a6 IE	95
b3e4e63f MT	96	table = kmap_atomic(page, KM_USER0);
	97
	98	ret = CMPXCHG(&table[index], orig_pte, new_pte);
	99
	100	kunmap_atomic(table, KM_USER0);
	101
	102	kvm_release_page_dirty(page);
	103
	104	return (ret != orig_pte);
	105	}
	106
bedbe4ee AK	107	static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
	108	{
	109	unsigned access;
	110
	111	access = (gpte & (PT_WRITABLE_MASK \| PT_USER_MASK)) \| ACC_EXEC_MASK;
	112	#if PTTYPE == 64
	113	if (is_nx(vcpu))
	114	access &= ~(gpte >> PT64_NX_SHIFT);
	115	#endif
	116	return access;
	117	}
	118
ac79c978 AK	119	/*
	120	* Fetch a guest pte for a guest virtual address
	121	*/
7993ba43 AK	122	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	123	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	124	int write_fault, int user_fault, int fetch_fault)
6aa8b732	125	{
42bf3f0a	126	pt_element_t pte;
cea0f0e7	127	gfn_t table_gfn;
fe135d2c	128	unsigned index, pt_access, pte_access;
42bf3f0a	129	gpa_t pte_gpa;
6aa8b732	130
b8688d51	131	pgprintk("%s: addr %lx\n", __func__, addr);
b3e4e63f	132	walk:
ad312c7c ZX	133	walker->level = vcpu->arch.mmu.root_level;
ad312c7c ZX	134	pte = vcpu->arch.cr3;
1b0973bd AK	135	#if PTTYPE == 64
1b0973bd AK	136	if (!is_long_mode(vcpu)) {
ad312c7c	137	pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
42bf3f0a	138	if (!is_present_pte(pte))
7993ba43	139	goto not_present;
1b0973bd AK	140	--walker->level;
	141	}
	142	#endif
a9058ecd	143	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
24993d53	144	(vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	145
fe135d2c	146	pt_access = ACC_ALL;
ac79c978 AK	147
ac79c978 AK	148	for (;;) {
42bf3f0a	149	index = PT_INDEX(addr, walker->level);
ac79c978	150
5fb07ddb	151	table_gfn = gpte_to_gfn(pte);
1755fbcc	152	pte_gpa = gfn_to_gpa(table_gfn);
ec8d4eae	153	pte_gpa += index * sizeof(pt_element_t);
42bf3f0a	154	walker->table_gfn[walker->level - 1] = table_gfn;
7819026e	155	walker->pte_gpa[walker->level - 1] = pte_gpa;
b8688d51	156	pgprintk("%s: table_gfn[%d] %lx\n", __func__,
42bf3f0a AK	157	walker->level - 1, table_gfn);
42bf3f0a AK	158
ec8d4eae	159	kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	160
42bf3f0a AK	161	if (!is_present_pte(pte))
7993ba43 AK	162	goto not_present;
7993ba43 AK	163
42bf3f0a	164	if (write_fault && !is_writeble_pte(pte))
7993ba43 AK	165	if (user_fault \|\| is_write_protection(vcpu))
	166	goto access_error;
	167
42bf3f0a	168	if (user_fault && !(pte & PT_USER_MASK))
7993ba43 AK	169	goto access_error;
7993ba43 AK	170
73b1087e	171	#if PTTYPE == 64
42bf3f0a	172	if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
73b1087e AK	173	goto access_error;
	174	#endif
	175
42bf3f0a	176	if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86	177	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	178	if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
	179	index, pte, pte\|PT_ACCESSED_MASK))
	180	goto walk;
42bf3f0a	181	pte \|= PT_ACCESSED_MASK;
bf3f8e86	182	}
815af8d4	183
bedbe4ee	184	pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
fe135d2c	185
7819026e MT	186	walker->ptes[walker->level - 1] = pte;
7819026e MT	187
815af8d4	188	if (walker->level == PT_PAGE_TABLE_LEVEL) {
5fb07ddb	189	walker->gfn = gpte_to_gfn(pte);
815af8d4 AK	190	break;
	191	}
	192
	193	if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a	194	&& (pte & PT_PAGE_SIZE_MASK)
815af8d4	195	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
5fb07ddb	196	walker->gfn = gpte_to_gfn_pde(pte);
815af8d4	197	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
da928521 AK	198	if (PTTYPE == 32 && is_cpuid_PSE36())
da928521 AK	199	walker->gfn += pse36_gfn_delta(pte);
ac79c978	200	break;
815af8d4	201	}
ac79c978	202
fe135d2c	203	pt_access = pte_access;
ac79c978 AK	204	--walker->level;
ac79c978 AK	205	}
42bf3f0a AK	206
42bf3f0a AK	207	if (write_fault && !is_dirty_pte(pte)) {
b3e4e63f MT	208	bool ret;
b3e4e63f MT	209
42bf3f0a	210	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	211	ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
	212	pte\|PT_DIRTY_MASK);
	213	if (ret)
	214	goto walk;
42bf3f0a	215	pte \|= PT_DIRTY_MASK;
42bf3f0a	216	kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
7819026e	217	walker->ptes[walker->level - 1] = pte;
42bf3f0a AK	218	}
42bf3f0a AK	219
fe135d2c AK	220	walker->pt_access = pt_access;
	221	walker->pte_access = pte_access;
	222	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
b8688d51	223	__func__, (u64)pte, pt_access, pte_access);
7993ba43 AK	224	return 1;
	225
	226	not_present:
	227	walker->error_code = 0;
	228	goto err;
	229
	230	access_error:
	231	walker->error_code = PFERR_PRESENT_MASK;
	232
	233	err:
	234	if (write_fault)
	235	walker->error_code \|= PFERR_WRITE_MASK;
	236	if (user_fault)
	237	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	238	if (fetch_fault)
73b1087e AK	239	walker->error_code \|= PFERR_FETCH_MASK;
fe551881	240	return 0;
6aa8b732 AK	241	}
6aa8b732 AK	242
0028425f	243	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
489f1d65	244	u64 spte, const void pte)
0028425f AK	245	{
0028425f AK	246	pt_element_t gpte;
41074d07	247	unsigned pte_access;
35149e21	248	pfn_t pfn;
05da4558	249	int largepage = vcpu->arch.update_pte.largepage;
0028425f	250
0028425f	251	gpte = (const pt_element_t )pte;
c7addb90	252	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
489f1d65	253	if (!is_present_pte(gpte))
c7addb90 AK	254	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	255	return;
	256	}
b8688d51	257	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
41074d07	258	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
d7824fff AK	259	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
d7824fff AK	260	return;
35149e21 AL	261	pfn = vcpu->arch.update_pte.pfn;
35149e21 AL	262	if (is_error_pfn(pfn))
d7824fff	263	return;
e930bffe AA	264	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
e930bffe AA	265	return;
35149e21	266	kvm_get_pfn(pfn);
1c4f1fd6	267	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
05da4558	268	gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
35149e21	269	pfn, true);
0028425f AK	270	}
0028425f AK	271
6aa8b732 AK	272	/*
	273	* Fetch a shadow pte for a specific level in the paging hierarchy.
	274	*/
	275	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e	276	struct guest_walker *walker,
05da4558	277	int user_fault, int write_fault, int largepage,
35149e21	278	int *ptwrite, pfn_t pfn)
6aa8b732 AK	279	{
	280	hpa_t shadow_addr;
	281	int level;
ef0197e8	282	u64 *shadow_ent;
fe135d2c	283	unsigned access = walker->pt_access;
ac79c978	284
7819026e	285	if (!is_present_pte(walker->ptes[walker->level - 1]))
ac79c978	286	return NULL;
6aa8b732	287
ad312c7c ZX	288	shadow_addr = vcpu->arch.mmu.root_hpa;
ad312c7c ZX	289	level = vcpu->arch.mmu.shadow_root_level;
aef3d3fe	290	if (level == PT32E_ROOT_LEVEL) {
ad312c7c	291	shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
aef3d3fe AK	292	shadow_addr &= PT64_BASE_ADDR_MASK;
	293	--level;
	294	}
6aa8b732 AK	295
	296	for (; ; level--) {
	297	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	298	struct kvm_mmu_page *shadow_page;
8c7bb723	299	u64 shadow_pte;
cea0f0e7 AK	300	int metaphysical;
cea0f0e7 AK	301	gfn_t table_gfn;
6aa8b732	302
ef0197e8	303	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
5882842f DE	304	if (level == PT_PAGE_TABLE_LEVEL)
5882842f DE	305	break;
05da4558 MT	306
	307	if (largepage && level == PT_DIRECTORY_LEVEL)
	308	break;
	309
	310	if (is_shadow_present_pte(*shadow_ent)
	311	&& !is_large_pte(*shadow_ent)) {
6aa8b732	312	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
6aa8b732 AK	313	continue;
	314	}
	315
05da4558 MT	316	if (is_large_pte(*shadow_ent))
	317	rmap_remove(vcpu->kvm, shadow_ent);
	318
cea0f0e7 AK	319	if (level - 1 == PT_PAGE_TABLE_LEVEL
	320	&& walker->level == PT_DIRECTORY_LEVEL) {
	321	metaphysical = 1;
7819026e	322	if (!is_dirty_pte(walker->ptes[level - 1]))
fe135d2c	323	access &= ~ACC_WRITE_MASK;
7819026e	324	table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
cea0f0e7 AK	325	} else {
	326	metaphysical = 0;
	327	table_gfn = walker->table_gfn[level - 2];
	328	}
	329	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
fe135d2c	330	metaphysical, access,
f7d9c7b7 AK	331	shadow_ent);
f7d9c7b7 AK	332	if (!metaphysical) {
7ec54588	333	int r;
7819026e	334	pt_element_t curr_pte;
7ec54588 MT	335	r = kvm_read_guest_atomic(vcpu->kvm,
	336	walker->pte_gpa[level - 2],
	337	&curr_pte, sizeof(curr_pte));
d7824fff	338	if (r \|\| curr_pte != walker->ptes[level - 2]) {
35149e21	339	kvm_release_pfn_clean(pfn);
7819026e	340	return NULL;
d7824fff	341	}
7819026e	342	}
47ad8e68	343	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	344	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	345	\| PT_WRITABLE_MASK \| PT_USER_MASK;
cd5998eb	346	set_shadow_pte(shadow_ent, shadow_pte);
6aa8b732	347	}
ef0197e8	348
1c4f1fd6	349	mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
7819026e MT	350	user_fault, write_fault,
7819026e MT	351	walker->ptes[walker->level-1] & PT_DIRTY_MASK,
35149e21	352	ptwrite, largepage, walker->gfn, pfn, false);
050e6499	353
ef0197e8	354	return shadow_ent;
6aa8b732 AK	355	}
6aa8b732 AK	356
6aa8b732 AK	357	/*
	358	* Page fault handler. There are several causes for a page fault:
	359	* - there is no shadow pte for the guest pte
	360	* - write access through a shadow pte marked read only so that we can set
	361	* the dirty bit
	362	* - write access to a shadow pte marked read only so we can update the page
	363	* dirty bitmap, when userspace requests it
	364	* - mmio access; in this case we will never install a present shadow pte
	365	* - normal guest page fault due to the guest pte marked not present, not
	366	* writable, or not executable
	367	*
e2dec939 AK	368	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	369	* a negative value on error.
6aa8b732 AK	370	*/
	371	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	372	u32 error_code)
	373	{
	374	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	375	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	376	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	377	struct guest_walker walker;
6aa8b732 AK	378	u64 *shadow_pte;
cea0f0e7	379	int write_pt = 0;
e2dec939	380	int r;
35149e21	381	pfn_t pfn;
05da4558	382	int largepage = 0;
e930bffe	383	unsigned long mmu_seq;
6aa8b732	384
b8688d51	385	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
37a7d8b0	386	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	387
e2dec939 AK	388	r = mmu_topup_memory_caches(vcpu);
	389	if (r)
	390	return r;
714b93da	391
6aa8b732 AK	392	/*
	393	* Look up the shadow pte for the faulting address.
	394	*/
73b1087e AK	395	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	396	fetch_fault);
6aa8b732 AK	397
	398	/*
	399	* The page is not mapped by the guest. Let the guest handle it.
	400	*/
7993ba43	401	if (!r) {
b8688d51	402	pgprintk("%s: guest page fault\n", __func__);
7993ba43	403	inject_page_fault(vcpu, addr, walker.error_code);
ad312c7c	404	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	405	return 0;
	406	}
	407
72dc67a6	408	down_read(&current->mm->mmap_sem);
05da4558 MT	409	if (walker.level == PT_DIRECTORY_LEVEL) {
	410	gfn_t large_gfn;
	411	large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
	412	if (is_largepage_backed(vcpu, large_gfn)) {
	413	walker.gfn = large_gfn;
	414	largepage = 1;
	415	}
	416	}
e930bffe AA	417	mmu_seq = vcpu->kvm->mmu_notifier_seq;
e930bffe AA	418	/* implicit mb(), we'll read before PT lock is unlocked */
35149e21	419	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
72dc67a6	420	up_read(&current->mm->mmap_sem);
d7824fff	421
d196e343	422	/* mmio */
35149e21	423	if (is_error_pfn(pfn)) {
ebb0e626	424	pgprintk("gfn %lx is mmio\n", walker.gfn);
35149e21	425	kvm_release_pfn_clean(pfn);
d196e343 AK	426	return 1;
	427	}
	428
aaee2c94	429	spin_lock(&vcpu->kvm->mmu_lock);
e930bffe AA	430	if (mmu_notifier_retry(vcpu, mmu_seq))
e930bffe AA	431	goto out_unlock;
eb787d10	432	kvm_mmu_free_some_pages(vcpu);
97a0a01e	433	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
35149e21	434	largepage, &write_pt, pfn);
05da4558	435
b8688d51	436	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
97a0a01e	437	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	438
a25f7e1f	439	if (!write_pt)
ad312c7c	440	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
a25f7e1f	441
1165f5fe	442	++vcpu->stat.pf_fixed;
37a7d8b0	443	kvm_mmu_audit(vcpu, "post page fault (fixed)");
aaee2c94	444	spin_unlock(&vcpu->kvm->mmu_lock);
6aa8b732	445
cea0f0e7	446	return write_pt;
e930bffe AA	447
	448	out_unlock:
	449	spin_unlock(&vcpu->kvm->mmu_lock);
	450	kvm_release_pfn_clean(pfn);
	451	return 0;
6aa8b732 AK	452	}
	453
	454	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	455	{
	456	struct guest_walker walker;
e119d117 AK	457	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	458	int r;
6aa8b732	459
e119d117	460	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	461
e119d117	462	if (r) {
1755fbcc	463	gpa = gfn_to_gpa(walker.gfn);
e119d117	464	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	465	}
	466
	467	return gpa;
	468	}
	469
c7addb90 AK	470	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	471	struct kvm_mmu_page *sp)
	472	{
eab9f71f AK	473	int i, j, offset, r;
	474	pt_element_t pt[256 / sizeof(pt_element_t)];
	475	gpa_t pte_gpa;
c7addb90	476
e5a4c8ca AK	477	if (sp->role.metaphysical
e5a4c8ca AK	478	\|\| (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90 AK	479	nonpaging_prefetch_page(vcpu, sp);
	480	return;
	481	}
	482
eab9f71f AK	483	pte_gpa = gfn_to_gpa(sp->gfn);
eab9f71f AK	484	if (PTTYPE == 32) {
e5a4c8ca	485	offset = sp->role.quadrant << PT64_LEVEL_BITS;
eab9f71f AK	486	pte_gpa += offset * sizeof(pt_element_t);
eab9f71f AK	487	}
7ec54588	488
eab9f71f AK	489	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
	490	r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
	491	pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
	492	for (j = 0; j < ARRAY_SIZE(pt); ++j)
	493	if (r \|\| is_present_pte(pt[j]))
	494	sp->spt[i+j] = shadow_trap_nonpresent_pte;
	495	else
	496	sp->spt[i+j] = shadow_notrap_nonpresent_pte;
7ec54588	497	}
c7addb90 AK	498	}
c7addb90 AK	499
6aa8b732 AK	500	#undef pt_element_t
	501	#undef guest_walker
	502	#undef FNAME
	503	#undef PT_BASE_ADDR_MASK
	504	#undef PT_INDEX
6aa8b732	505	#undef PT_LEVEL_MASK
6aa8b732	506	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	507	#undef PT_LEVEL_BITS
cea0f0e7	508	#undef PT_MAX_FULL_LEVELS
5fb07ddb AK	509	#undef gpte_to_gfn
5fb07ddb AK	510	#undef gpte_to_gfn_pde
b3e4e63f	511	#undef CMPXCHG