[deliverable/linux.git] / arch / x86 / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#define CMPXCHG cmpxchg
	#else
	#define CMPXCHG cmpxchg64
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
	#define CMPXCHG cmpxchg
#else
	#error Invalid PTTYPE value
#endif

#define gpte_to_gfn FNAME(gpte_to_gfn)
#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
	unsigned pt_access;
	unsigned pte_access;
	gfn_t gfn;
	u32 error_code;
};

static gfn_t gpte_to_gfn(pt_element_t gpte)
{
	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
{
	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
			 gfn_t table_gfn, unsigned index,
			 pt_element_t orig_pte, pt_element_t new_pte)
{
	pt_element_t ret;
	pt_element_t *table;
	struct page *page;

	page = gfn_to_page(kvm, table_gfn);

	table = kmap_atomic(page, KM_USER0);
	ret = CMPXCHG(&table[index], orig_pte, new_pte);
	kunmap_atomic(table, KM_USER0);

	kvm_release_page_dirty(page);

	return (ret != orig_pte);
}

static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
{
	unsigned access;

	access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
#if PTTYPE == 64
	if (is_nx(vcpu))
		access &= ~(gpte >> PT64_NX_SHIFT);
#endif
	return access;
}

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index, pt_access, pte_access;
	gpa_t pte_gpa;

	pgprintk("%s: addr %lx\n", __func__, addr);
walk:
	walker->level = vcpu->arch.mmu.root_level;
	pte = vcpu->arch.cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
		if (!is_present_pte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	pt_access = ACC_ALL;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = gpte_to_gfn(pte);
		pte_gpa = gfn_to_gpa(table_gfn);
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		walker->pte_gpa[walker->level - 1] = pte_gpa;
		pgprintk("%s: table_gfn[%d] %lx\n", __func__,
			 walker->level - 1, table_gfn);

		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));

		if (!is_present_pte(pte))
			goto not_present;

		if (write_fault && !is_writeble_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
			    index, pte, pte|PT_ACCESSED_MASK))
				goto walk;
			pte |= PT_ACCESSED_MASK;
		}

		pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);

		walker->ptes[walker->level - 1] = pte;

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = gpte_to_gfn(pte);
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (pte & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = gpte_to_gfn_pde(pte);
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			if (PTTYPE == 32 && is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);
			break;
		}

		pt_access = pte_access;
		--walker->level;
	}

	if (write_fault && !is_dirty_pte(pte)) {
		bool ret;

		mark_page_dirty(vcpu->kvm, table_gfn);
		ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
			    pte|PT_DIRTY_MASK);
		if (ret)
			goto walk;
		pte |= PT_DIRTY_MASK;
		walker->ptes[walker->level - 1] = pte;
	}

	walker->pt_access = pt_access;
	walker->pte_access = pte_access;
	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
		 __func__, (u64)pte, pt_access, pte_access);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte)
{
	pt_element_t gpte;
	unsigned pte_access;
	pfn_t pfn;
	int largepage = vcpu->arch.update_pte.largepage;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
		return;
	pfn = vcpu->arch.update_pte.pfn;
	if (is_error_pfn(pfn))
		return;
	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
		return;
	kvm_get_pfn(pfn);
	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
		     gpte & PT_DIRTY_MASK, NULL, largepage,
		     gpte & PT_GLOBAL_MASK, gpte_to_gfn(gpte),
		     pfn, true);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *gw,
			 int user_fault, int write_fault, int largepage,
			 int *ptwrite, pfn_t pfn)
{
	unsigned access = gw->pt_access;
	struct kvm_mmu_page *shadow_page;
	u64 spte, *sptep;
	int direct;
	gfn_t table_gfn;
	int r;
	int level;
	pt_element_t curr_pte;
	struct kvm_shadow_walk_iterator iterator;

	if (!is_present_pte(gw->ptes[gw->level - 1]))
		return NULL;

	for_each_shadow_entry(vcpu, addr, iterator) {
		level = iterator.level;
		sptep = iterator.sptep;
		if (level == PT_PAGE_TABLE_LEVEL
		    || (largepage && level == PT_DIRECTORY_LEVEL)) {
			mmu_set_spte(vcpu, sptep, access,
				     gw->pte_access & access,
				     user_fault, write_fault,
				     gw->ptes[gw->level-1] & PT_DIRTY_MASK,
				     ptwrite, largepage,
				     gw->ptes[gw->level-1] & PT_GLOBAL_MASK,
				     gw->gfn, pfn, false);
			break;
		}

		if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
			continue;

		if (is_large_pte(*sptep)) {
			rmap_remove(vcpu->kvm, sptep);
			set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
			kvm_flush_remote_tlbs(vcpu->kvm);
		}

		if (level == PT_DIRECTORY_LEVEL
		    && gw->level == PT_DIRECTORY_LEVEL) {
			direct = 1;
			if (!is_dirty_pte(gw->ptes[level - 1]))
				access &= ~ACC_WRITE_MASK;
			table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
		} else {
			direct = 0;
			table_gfn = gw->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       direct, access, sptep);
		if (!direct) {
			r = kvm_read_guest_atomic(vcpu->kvm,
						  gw->pte_gpa[level - 2],
						  &curr_pte, sizeof(curr_pte));
			if (r || curr_pte != gw->ptes[level - 2]) {
				kvm_mmu_put_page(shadow_page, sptep);
				kvm_release_pfn_clean(pfn);
				sptep = NULL;
				break;
			}
		}

		spte = __pa(shadow_page->spt)
			| PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*sptep = spte;
	}

	return sptep;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;
	pfn_t pfn;
	int largepage = 0;
	unsigned long mmu_seq;

	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the guest pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __func__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	if (walker.level == PT_DIRECTORY_LEVEL) {
		gfn_t large_gfn;
		large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
		if (is_largepage_backed(vcpu, large_gfn)) {
			walker.gfn = large_gfn;
			largepage = 1;
		}
	}
	mmu_seq = vcpu->kvm->mmu_notifier_seq;
	smp_rmb();
	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);

	/* mmio */
	if (is_error_pfn(pfn)) {
		pgprintk("gfn %lx is mmio\n", walker.gfn);
		kvm_release_pfn_clean(pfn);
		return 1;
	}

	spin_lock(&vcpu->kvm->mmu_lock);
	if (mmu_notifier_retry(vcpu, mmu_seq))
		goto out_unlock;
	kvm_mmu_free_some_pages(vcpu);
	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  largepage, &write_pt, pfn);

	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");
	spin_unlock(&vcpu->kvm->mmu_lock);

	return write_pt;

out_unlock:
	spin_unlock(&vcpu->kvm->mmu_lock);
	kvm_release_pfn_clean(pfn);
	return 0;
}

static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
{
	struct kvm_shadow_walk_iterator iterator;
	pt_element_t gpte;
	gpa_t pte_gpa = -1;
	int level;
	u64 *sptep;
	int need_flush = 0;

	spin_lock(&vcpu->kvm->mmu_lock);

	for_each_shadow_entry(vcpu, gva, iterator) {
		level = iterator.level;
		sptep = iterator.sptep;

		/* FIXME: properly handle invlpg on large guest pages */
		if (level == PT_PAGE_TABLE_LEVEL ||
		    ((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) {
			struct kvm_mmu_page *sp = page_header(__pa(sptep));

			pte_gpa = (sp->gfn << PAGE_SHIFT);
			pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);

			if (is_shadow_present_pte(*sptep)) {
				rmap_remove(vcpu->kvm, sptep);
				if (is_large_pte(*sptep))
					--vcpu->kvm->stat.lpages;
				need_flush = 1;
			}
			set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
			break;
		}

		if (!is_shadow_present_pte(*sptep))
			break;
	}

	if (need_flush)
		kvm_flush_remote_tlbs(vcpu->kvm);
	spin_unlock(&vcpu->kvm->mmu_lock);

	if (pte_gpa == -1)
		return;
	if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
				  sizeof(pt_element_t)))
		return;
	if (is_present_pte(gpte) && (gpte & PT_ACCESSED_MASK)) {
		if (mmu_topup_memory_caches(vcpu))
			return;
		kvm_mmu_pte_write(vcpu, pte_gpa, (const u8 *)&gpte,
				  sizeof(pt_element_t), 0);
	}
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = gfn_to_gpa(walker.gfn);
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i, j, offset, r;
	pt_element_t pt[256 / sizeof(pt_element_t)];
	gpa_t pte_gpa;

	if (sp->role.direct
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	pte_gpa = gfn_to_gpa(sp->gfn);
	if (PTTYPE == 32) {
		offset = sp->role.quadrant << PT64_LEVEL_BITS;
		pte_gpa += offset * sizeof(pt_element_t);
	}

	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
		r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
		pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
		for (j = 0; j < ARRAY_SIZE(pt); ++j)
			if (r || is_present_pte(pt[j]))
				sp->spt[i+j] = shadow_trap_nonpresent_pte;
			else
				sp->spt[i+j] = shadow_notrap_nonpresent_pte;
	}
}

/*
 * Using the cached information from sp->gfns is safe because:
 * - The spte has a reference to the struct page, so the pfn for a given gfn
 *   can't change unless all sptes pointing to it are nuked first.
 * - Alias changes zap the entire shadow cache.
 */
static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
{
	int i, offset, nr_present;

	offset = nr_present = 0;

	if (PTTYPE == 32)
		offset = sp->role.quadrant << PT64_LEVEL_BITS;

	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
		unsigned pte_access;
		pt_element_t gpte;
		gpa_t pte_gpa;
		gfn_t gfn = sp->gfns[i];

		if (!is_shadow_present_pte(sp->spt[i]))
			continue;

		pte_gpa = gfn_to_gpa(sp->gfn);
		pte_gpa += (i+offset) * sizeof(pt_element_t);

		if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
					  sizeof(pt_element_t)))
			return -EINVAL;

		if (gpte_to_gfn(gpte) != gfn || !is_present_pte(gpte) ||
		    !(gpte & PT_ACCESSED_MASK)) {
			u64 nonpresent;

			rmap_remove(vcpu->kvm, &sp->spt[i]);
			if (is_present_pte(gpte))
				nonpresent = shadow_trap_nonpresent_pte;
			else
				nonpresent = shadow_notrap_nonpresent_pte;
			set_shadow_pte(&sp->spt[i], nonpresent);
			continue;
		}

		nr_present++;
		pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
		set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
			 is_dirty_pte(gpte), 0, gpte & PT_GLOBAL_MASK, gfn,
			 spte_to_pfn(sp->spt[i]), true, false);
	}

	return !nr_present;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
#undef gpte_to_gfn
#undef gpte_to_gfn_pde
#undef CMPXCHG
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
6aa8b732	32	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	33	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	34	#ifdef CONFIG_X86_64
cea0f0e7 AK	35	#define PT_MAX_FULL_LEVELS 4
b3e4e63f	36	#define CMPXCHG cmpxchg
cea0f0e7	37	#else
b3e4e63f	38	#define CMPXCHG cmpxchg64
cea0f0e7 AK	39	#define PT_MAX_FULL_LEVELS 2
cea0f0e7 AK	40	#endif
6aa8b732 AK	41	#elif PTTYPE == 32
	42	#define pt_element_t u32
	43	#define guest_walker guest_walker32
	44	#define FNAME(name) paging##32_##name
	45	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	46	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	47	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
6aa8b732	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	49	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
b3e4e63f	51	#define CMPXCHG cmpxchg
6aa8b732 AK	52	#else
	53	#error Invalid PTTYPE value
	54	#endif
	55
5fb07ddb AK	56	#define gpte_to_gfn FNAME(gpte_to_gfn)
	57	#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
	58
6aa8b732 AK	59	/*
	60	* The guest_walker structure emulates the behavior of the hardware page
	61	* table walker.
	62	*/
	63	struct guest_walker {
	64	int level;
cea0f0e7	65	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
7819026e MT	66	pt_element_t ptes[PT_MAX_FULL_LEVELS];
7819026e MT	67	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
fe135d2c AK	68	unsigned pt_access;
fe135d2c AK	69	unsigned pte_access;
815af8d4	70	gfn_t gfn;
7993ba43	71	u32 error_code;
6aa8b732 AK	72	};
6aa8b732 AK	73
5fb07ddb AK	74	static gfn_t gpte_to_gfn(pt_element_t gpte)
	75	{
	76	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
	77	}
	78
	79	static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
	80	{
	81	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
	82	}
	83
b3e4e63f MT	84	static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
	85	gfn_t table_gfn, unsigned index,
	86	pt_element_t orig_pte, pt_element_t new_pte)
	87	{
	88	pt_element_t ret;
	89	pt_element_t *table;
	90	struct page *page;
	91
	92	page = gfn_to_page(kvm, table_gfn);
72dc67a6	93
b3e4e63f	94	table = kmap_atomic(page, KM_USER0);
b3e4e63f	95	ret = CMPXCHG(&table[index], orig_pte, new_pte);
b3e4e63f MT	96	kunmap_atomic(table, KM_USER0);
	97
	98	kvm_release_page_dirty(page);
	99
	100	return (ret != orig_pte);
	101	}
	102
bedbe4ee AK	103	static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
	104	{
	105	unsigned access;
	106
	107	access = (gpte & (PT_WRITABLE_MASK \| PT_USER_MASK)) \| ACC_EXEC_MASK;
	108	#if PTTYPE == 64
	109	if (is_nx(vcpu))
	110	access &= ~(gpte >> PT64_NX_SHIFT);
	111	#endif
	112	return access;
	113	}
	114
ac79c978 AK	115	/*
	116	* Fetch a guest pte for a guest virtual address
	117	*/
7993ba43 AK	118	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	119	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	120	int write_fault, int user_fault, int fetch_fault)
6aa8b732	121	{
42bf3f0a	122	pt_element_t pte;
cea0f0e7	123	gfn_t table_gfn;
fe135d2c	124	unsigned index, pt_access, pte_access;
42bf3f0a	125	gpa_t pte_gpa;
6aa8b732	126
b8688d51	127	pgprintk("%s: addr %lx\n", __func__, addr);
b3e4e63f	128	walk:
ad312c7c ZX	129	walker->level = vcpu->arch.mmu.root_level;
ad312c7c ZX	130	pte = vcpu->arch.cr3;
1b0973bd AK	131	#if PTTYPE == 64
1b0973bd AK	132	if (!is_long_mode(vcpu)) {
ad312c7c	133	pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
42bf3f0a	134	if (!is_present_pte(pte))
7993ba43	135	goto not_present;
1b0973bd AK	136	--walker->level;
	137	}
	138	#endif
a9058ecd	139	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
24993d53	140	(vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	141
fe135d2c	142	pt_access = ACC_ALL;
ac79c978 AK	143
ac79c978 AK	144	for (;;) {
42bf3f0a	145	index = PT_INDEX(addr, walker->level);
ac79c978	146
5fb07ddb	147	table_gfn = gpte_to_gfn(pte);
1755fbcc	148	pte_gpa = gfn_to_gpa(table_gfn);
ec8d4eae	149	pte_gpa += index * sizeof(pt_element_t);
42bf3f0a	150	walker->table_gfn[walker->level - 1] = table_gfn;
7819026e	151	walker->pte_gpa[walker->level - 1] = pte_gpa;
b8688d51	152	pgprintk("%s: table_gfn[%d] %lx\n", __func__,
42bf3f0a AK	153	walker->level - 1, table_gfn);
42bf3f0a AK	154
ec8d4eae	155	kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	156
42bf3f0a AK	157	if (!is_present_pte(pte))
7993ba43 AK	158	goto not_present;
7993ba43 AK	159
42bf3f0a	160	if (write_fault && !is_writeble_pte(pte))
7993ba43 AK	161	if (user_fault \|\| is_write_protection(vcpu))
	162	goto access_error;
	163
42bf3f0a	164	if (user_fault && !(pte & PT_USER_MASK))
7993ba43 AK	165	goto access_error;
7993ba43 AK	166
73b1087e	167	#if PTTYPE == 64
42bf3f0a	168	if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
73b1087e AK	169	goto access_error;
	170	#endif
	171
42bf3f0a	172	if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86	173	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	174	if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
	175	index, pte, pte\|PT_ACCESSED_MASK))
	176	goto walk;
42bf3f0a	177	pte \|= PT_ACCESSED_MASK;
bf3f8e86	178	}
815af8d4	179
bedbe4ee	180	pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
fe135d2c	181
7819026e MT	182	walker->ptes[walker->level - 1] = pte;
7819026e MT	183
815af8d4	184	if (walker->level == PT_PAGE_TABLE_LEVEL) {
5fb07ddb	185	walker->gfn = gpte_to_gfn(pte);
815af8d4 AK	186	break;
	187	}
	188
	189	if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a	190	&& (pte & PT_PAGE_SIZE_MASK)
815af8d4	191	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
5fb07ddb	192	walker->gfn = gpte_to_gfn_pde(pte);
815af8d4	193	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
da928521 AK	194	if (PTTYPE == 32 && is_cpuid_PSE36())
da928521 AK	195	walker->gfn += pse36_gfn_delta(pte);
ac79c978	196	break;
815af8d4	197	}
ac79c978	198
fe135d2c	199	pt_access = pte_access;
ac79c978 AK	200	--walker->level;
ac79c978 AK	201	}
42bf3f0a AK	202
42bf3f0a AK	203	if (write_fault && !is_dirty_pte(pte)) {
b3e4e63f MT	204	bool ret;
b3e4e63f MT	205
42bf3f0a	206	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	207	ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
	208	pte\|PT_DIRTY_MASK);
	209	if (ret)
	210	goto walk;
42bf3f0a	211	pte \|= PT_DIRTY_MASK;
7819026e	212	walker->ptes[walker->level - 1] = pte;
42bf3f0a AK	213	}
42bf3f0a AK	214
fe135d2c AK	215	walker->pt_access = pt_access;
	216	walker->pte_access = pte_access;
	217	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
b8688d51	218	__func__, (u64)pte, pt_access, pte_access);
7993ba43 AK	219	return 1;
	220
	221	not_present:
	222	walker->error_code = 0;
	223	goto err;
	224
	225	access_error:
	226	walker->error_code = PFERR_PRESENT_MASK;
	227
	228	err:
	229	if (write_fault)
	230	walker->error_code \|= PFERR_WRITE_MASK;
	231	if (user_fault)
	232	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	233	if (fetch_fault)
73b1087e AK	234	walker->error_code \|= PFERR_FETCH_MASK;
fe551881	235	return 0;
6aa8b732 AK	236	}
6aa8b732 AK	237
0028425f	238	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
489f1d65	239	u64 spte, const void pte)
0028425f AK	240	{
0028425f AK	241	pt_element_t gpte;
41074d07	242	unsigned pte_access;
35149e21	243	pfn_t pfn;
05da4558	244	int largepage = vcpu->arch.update_pte.largepage;
0028425f	245
0028425f	246	gpte = (const pt_element_t )pte;
c7addb90	247	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
489f1d65	248	if (!is_present_pte(gpte))
c7addb90 AK	249	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	250	return;
	251	}
b8688d51	252	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
41074d07	253	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
d7824fff AK	254	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
d7824fff AK	255	return;
35149e21 AL	256	pfn = vcpu->arch.update_pte.pfn;
35149e21 AL	257	if (is_error_pfn(pfn))
d7824fff	258	return;
e930bffe AA	259	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
e930bffe AA	260	return;
35149e21	261	kvm_get_pfn(pfn);
1c4f1fd6	262	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
6cffe8ca MT	263	gpte & PT_DIRTY_MASK, NULL, largepage,
6cffe8ca MT	264	gpte & PT_GLOBAL_MASK, gpte_to_gfn(gpte),
35149e21	265	pfn, true);
0028425f AK	266	}
0028425f AK	267
6aa8b732 AK	268	/*
	269	* Fetch a shadow pte for a specific level in the paging hierarchy.
	270	*/
e7a04c99 AK	271	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
	272	struct guest_walker *gw,
	273	int user_fault, int write_fault, int largepage,
	274	int *ptwrite, pfn_t pfn)
6aa8b732	275	{
abb9e0b8 AK	276	unsigned access = gw->pt_access;
abb9e0b8 AK	277	struct kvm_mmu_page *shadow_page;
e7a04c99	278	u64 spte, *sptep;
f6e2c02b	279	int direct;
abb9e0b8 AK	280	gfn_t table_gfn;
abb9e0b8 AK	281	int r;
e7a04c99	282	int level;
abb9e0b8	283	pt_element_t curr_pte;
e7a04c99	284	struct kvm_shadow_walk_iterator iterator;
abb9e0b8	285
e7a04c99 AK	286	if (!is_present_pte(gw->ptes[gw->level - 1]))
e7a04c99 AK	287	return NULL;
6aa8b732	288
e7a04c99 AK	289	for_each_shadow_entry(vcpu, addr, iterator) {
	290	level = iterator.level;
	291	sptep = iterator.sptep;
	292	if (level == PT_PAGE_TABLE_LEVEL
	293	\|\| (largepage && level == PT_DIRECTORY_LEVEL)) {
	294	mmu_set_spte(vcpu, sptep, access,
	295	gw->pte_access & access,
	296	user_fault, write_fault,
	297	gw->ptes[gw->level-1] & PT_DIRTY_MASK,
	298	ptwrite, largepage,
	299	gw->ptes[gw->level-1] & PT_GLOBAL_MASK,
	300	gw->gfn, pfn, false);
	301	break;
	302	}
6aa8b732	303
e7a04c99 AK	304	if (is_shadow_present_pte(sptep) && !is_large_pte(sptep))
e7a04c99 AK	305	continue;
abb9e0b8	306
e7a04c99	307	if (is_large_pte(*sptep)) {
c5bc2242	308	rmap_remove(vcpu->kvm, sptep);
e7a04c99 AK	309	set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
e7a04c99 AK	310	kvm_flush_remote_tlbs(vcpu->kvm);
7819026e	311	}
ef0197e8	312
e7a04c99 AK	313	if (level == PT_DIRECTORY_LEVEL
e7a04c99 AK	314	&& gw->level == PT_DIRECTORY_LEVEL) {
f6e2c02b	315	direct = 1;
e7a04c99 AK	316	if (!is_dirty_pte(gw->ptes[level - 1]))
	317	access &= ~ACC_WRITE_MASK;
	318	table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
	319	} else {
f6e2c02b	320	direct = 0;
e7a04c99 AK	321	table_gfn = gw->table_gfn[level - 2];
	322	}
	323	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
f6e2c02b AK	324	direct, access, sptep);
f6e2c02b AK	325	if (!direct) {
e7a04c99 AK	326	r = kvm_read_guest_atomic(vcpu->kvm,
	327	gw->pte_gpa[level - 2],
	328	&curr_pte, sizeof(curr_pte));
	329	if (r \|\| curr_pte != gw->ptes[level - 2]) {
	330	kvm_mmu_put_page(shadow_page, sptep);
	331	kvm_release_pfn_clean(pfn);
	332	sptep = NULL;
	333	break;
	334	}
	335	}
abb9e0b8	336
e7a04c99 AK	337	spte = __pa(shadow_page->spt)
	338	\| PT_PRESENT_MASK \| PT_ACCESSED_MASK
	339	\| PT_WRITABLE_MASK \| PT_USER_MASK;
	340	*sptep = spte;
	341	}
050e6499	342
e7a04c99	343	return sptep;
6aa8b732 AK	344	}
6aa8b732 AK	345
6aa8b732 AK	346	/*
	347	* Page fault handler. There are several causes for a page fault:
	348	* - there is no shadow pte for the guest pte
	349	* - write access through a shadow pte marked read only so that we can set
	350	* the dirty bit
	351	* - write access to a shadow pte marked read only so we can update the page
	352	* dirty bitmap, when userspace requests it
	353	* - mmio access; in this case we will never install a present shadow pte
	354	* - normal guest page fault due to the guest pte marked not present, not
	355	* writable, or not executable
	356	*
e2dec939 AK	357	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	358	* a negative value on error.
6aa8b732 AK	359	*/
	360	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	361	u32 error_code)
	362	{
	363	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	364	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	365	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	366	struct guest_walker walker;
6aa8b732 AK	367	u64 *shadow_pte;
cea0f0e7	368	int write_pt = 0;
e2dec939	369	int r;
35149e21	370	pfn_t pfn;
05da4558	371	int largepage = 0;
e930bffe	372	unsigned long mmu_seq;
6aa8b732	373
b8688d51	374	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
37a7d8b0	375	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	376
e2dec939 AK	377	r = mmu_topup_memory_caches(vcpu);
	378	if (r)
	379	return r;
714b93da	380
6aa8b732	381	/*
a8b876b1	382	* Look up the guest pte for the faulting address.
6aa8b732	383	*/
73b1087e AK	384	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	385	fetch_fault);
6aa8b732 AK	386
	387	/*
	388	* The page is not mapped by the guest. Let the guest handle it.
	389	*/
7993ba43	390	if (!r) {
b8688d51	391	pgprintk("%s: guest page fault\n", __func__);
7993ba43	392	inject_page_fault(vcpu, addr, walker.error_code);
ad312c7c	393	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	394	return 0;
	395	}
	396
05da4558 MT	397	if (walker.level == PT_DIRECTORY_LEVEL) {
	398	gfn_t large_gfn;
	399	large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
	400	if (is_largepage_backed(vcpu, large_gfn)) {
	401	walker.gfn = large_gfn;
	402	largepage = 1;
	403	}
	404	}
e930bffe	405	mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce	406	smp_rmb();
35149e21	407	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
d7824fff	408
d196e343	409	/* mmio */
35149e21	410	if (is_error_pfn(pfn)) {
ebb0e626	411	pgprintk("gfn %lx is mmio\n", walker.gfn);
35149e21	412	kvm_release_pfn_clean(pfn);
d196e343 AK	413	return 1;
	414	}
	415
aaee2c94	416	spin_lock(&vcpu->kvm->mmu_lock);
e930bffe AA	417	if (mmu_notifier_retry(vcpu, mmu_seq))
e930bffe AA	418	goto out_unlock;
eb787d10	419	kvm_mmu_free_some_pages(vcpu);
97a0a01e	420	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
35149e21	421	largepage, &write_pt, pfn);
05da4558	422
b8688d51	423	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
97a0a01e	424	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	425
a25f7e1f	426	if (!write_pt)
ad312c7c	427	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
a25f7e1f	428
1165f5fe	429	++vcpu->stat.pf_fixed;
37a7d8b0	430	kvm_mmu_audit(vcpu, "post page fault (fixed)");
aaee2c94	431	spin_unlock(&vcpu->kvm->mmu_lock);
6aa8b732	432
cea0f0e7	433	return write_pt;
e930bffe AA	434
	435	out_unlock:
	436	spin_unlock(&vcpu->kvm->mmu_lock);
	437	kvm_release_pfn_clean(pfn);
	438	return 0;
6aa8b732 AK	439	}
6aa8b732 AK	440
a461930b	441	static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
a7052897	442	{
a461930b AK	443	struct kvm_shadow_walk_iterator iterator;
	444	pt_element_t gpte;
	445	gpa_t pte_gpa = -1;
	446	int level;
	447	u64 *sptep;
4539b358	448	int need_flush = 0;
a461930b AK	449
a461930b AK	450	spin_lock(&vcpu->kvm->mmu_lock);
a7052897	451
a461930b AK	452	for_each_shadow_entry(vcpu, gva, iterator) {
	453	level = iterator.level;
	454	sptep = iterator.sptep;
ad218f85	455
a461930b AK	456	/* FIXME: properly handle invlpg on large guest pages */
	457	if (level == PT_PAGE_TABLE_LEVEL \|\|
	458	((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) {
	459	struct kvm_mmu_page *sp = page_header(__pa(sptep));
ad218f85	460
a461930b AK	461	pte_gpa = (sp->gfn << PAGE_SHIFT);
	462	pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
	463
	464	if (is_shadow_present_pte(*sptep)) {
	465	rmap_remove(vcpu->kvm, sptep);
	466	if (is_large_pte(*sptep))
	467	--vcpu->kvm->stat.lpages;
4539b358	468	need_flush = 1;
a461930b AK	469	}
	470	set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
	471	break;
87917239	472	}
a7052897	473
a461930b AK	474	if (!is_shadow_present_pte(*sptep))
	475	break;
	476	}
a7052897	477
4539b358 AA	478	if (need_flush)
4539b358 AA	479	kvm_flush_remote_tlbs(vcpu->kvm);
ad218f85	480	spin_unlock(&vcpu->kvm->mmu_lock);
a461930b AK	481
a461930b AK	482	if (pte_gpa == -1)
ad218f85	483	return;
a461930b	484	if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
ad218f85 MT	485	sizeof(pt_element_t)))
	486	return;
	487	if (is_present_pte(gpte) && (gpte & PT_ACCESSED_MASK)) {
	488	if (mmu_topup_memory_caches(vcpu))
	489	return;
a461930b	490	kvm_mmu_pte_write(vcpu, pte_gpa, (const u8 *)&gpte,
ad218f85 MT	491	sizeof(pt_element_t), 0);
ad218f85 MT	492	}
a7052897 MT	493	}
a7052897 MT	494
6aa8b732 AK	495	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	496	{
	497	struct guest_walker walker;
e119d117 AK	498	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	499	int r;
6aa8b732	500
e119d117	501	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	502
e119d117	503	if (r) {
1755fbcc	504	gpa = gfn_to_gpa(walker.gfn);
e119d117	505	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	506	}
	507
	508	return gpa;
	509	}
	510
c7addb90 AK	511	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	512	struct kvm_mmu_page *sp)
	513	{
eab9f71f AK	514	int i, j, offset, r;
	515	pt_element_t pt[256 / sizeof(pt_element_t)];
	516	gpa_t pte_gpa;
c7addb90	517
f6e2c02b	518	if (sp->role.direct
e5a4c8ca	519	\|\| (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90 AK	520	nonpaging_prefetch_page(vcpu, sp);
	521	return;
	522	}
	523
eab9f71f AK	524	pte_gpa = gfn_to_gpa(sp->gfn);
eab9f71f AK	525	if (PTTYPE == 32) {
e5a4c8ca	526	offset = sp->role.quadrant << PT64_LEVEL_BITS;
eab9f71f AK	527	pte_gpa += offset * sizeof(pt_element_t);
eab9f71f AK	528	}
7ec54588	529
eab9f71f AK	530	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
	531	r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
	532	pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
	533	for (j = 0; j < ARRAY_SIZE(pt); ++j)
	534	if (r \|\| is_present_pte(pt[j]))
	535	sp->spt[i+j] = shadow_trap_nonpresent_pte;
	536	else
	537	sp->spt[i+j] = shadow_notrap_nonpresent_pte;
7ec54588	538	}
c7addb90 AK	539	}
c7addb90 AK	540
e8bc217a MT	541	/*
	542	* Using the cached information from sp->gfns is safe because:
	543	* - The spte has a reference to the struct page, so the pfn for a given gfn
	544	* can't change unless all sptes pointing to it are nuked first.
	545	* - Alias changes zap the entire shadow cache.
	546	*/
	547	static int FNAME(sync_page)(struct kvm_vcpu vcpu, struct kvm_mmu_page sp)
	548	{
	549	int i, offset, nr_present;
	550
	551	offset = nr_present = 0;
	552
	553	if (PTTYPE == 32)
	554	offset = sp->role.quadrant << PT64_LEVEL_BITS;
	555
	556	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
	557	unsigned pte_access;
	558	pt_element_t gpte;
	559	gpa_t pte_gpa;
	560	gfn_t gfn = sp->gfns[i];
	561
	562	if (!is_shadow_present_pte(sp->spt[i]))
	563	continue;
	564
	565	pte_gpa = gfn_to_gpa(sp->gfn);
	566	pte_gpa += (i+offset) * sizeof(pt_element_t);
	567
	568	if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
	569	sizeof(pt_element_t)))
	570	return -EINVAL;
	571
	572	if (gpte_to_gfn(gpte) != gfn \|\| !is_present_pte(gpte) \|\|
	573	!(gpte & PT_ACCESSED_MASK)) {
	574	u64 nonpresent;
	575
	576	rmap_remove(vcpu->kvm, &sp->spt[i]);
	577	if (is_present_pte(gpte))
	578	nonpresent = shadow_trap_nonpresent_pte;
	579	else
	580	nonpresent = shadow_notrap_nonpresent_pte;
	581	set_shadow_pte(&sp->spt[i], nonpresent);
	582	continue;
	583	}
	584
	585	nr_present++;
	586	pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
	587	set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
6cffe8ca	588	is_dirty_pte(gpte), 0, gpte & PT_GLOBAL_MASK, gfn,
4731d4c7	589	spte_to_pfn(sp->spt[i]), true, false);
e8bc217a MT	590	}
	591
	592	return !nr_present;
	593	}
	594
6aa8b732 AK	595	#undef pt_element_t
	596	#undef guest_walker
	597	#undef FNAME
	598	#undef PT_BASE_ADDR_MASK
	599	#undef PT_INDEX
6aa8b732	600	#undef PT_LEVEL_MASK
6aa8b732	601	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	602	#undef PT_LEVEL_BITS
cea0f0e7	603	#undef PT_MAX_FULL_LEVELS
5fb07ddb AK	604	#undef gpte_to_gfn
5fb07ddb AK	605	#undef gpte_to_gfn_pde
b3e4e63f	606	#undef CMPXCHG