Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
a78484c6 | 81 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
b3e4e63f MT |
82 | gfn_t table_gfn, unsigned index, |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
84 | { | |
85 | pt_element_t ret; | |
86 | pt_element_t *table; | |
87 | struct page *page; | |
a78484c6 | 88 | gpa_t gpa; |
b3e4e63f | 89 | |
a78484c6 RJ |
90 | gpa = mmu->translate_gpa(vcpu, table_gfn << PAGE_SHIFT, |
91 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
92 | if (gpa == UNMAPPED_GVA) | |
93 | return -EFAULT; | |
94 | ||
95 | page = gfn_to_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
72dc67a6 | 96 | |
b3e4e63f | 97 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 98 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
99 | kunmap_atomic(table, KM_USER0); |
100 | ||
101 | kvm_release_page_dirty(page); | |
102 | ||
103 | return (ret != orig_pte); | |
104 | } | |
105 | ||
bedbe4ee AK |
106 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
107 | { | |
108 | unsigned access; | |
109 | ||
110 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
111 | #if PTTYPE == 64 | |
2d48a985 | 112 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
113 | access &= ~(gpte >> PT64_NX_SHIFT); |
114 | #endif | |
115 | return access; | |
116 | } | |
117 | ||
ac79c978 AK |
118 | /* |
119 | * Fetch a guest pte for a guest virtual address | |
120 | */ | |
1e301feb JR |
121 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
122 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 123 | gva_t addr, u32 access) |
6aa8b732 | 124 | { |
42bf3f0a | 125 | pt_element_t pte; |
cea0f0e7 | 126 | gfn_t table_gfn; |
f59c1d2d | 127 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 128 | gpa_t pte_gpa; |
f59c1d2d | 129 | bool eperm, present, rsvd_fault; |
33770780 XG |
130 | int offset, write_fault, user_fault, fetch_fault; |
131 | ||
132 | write_fault = access & PFERR_WRITE_MASK; | |
133 | user_fault = access & PFERR_USER_MASK; | |
134 | fetch_fault = access & PFERR_FETCH_MASK; | |
6aa8b732 | 135 | |
07420171 AK |
136 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
137 | fetch_fault); | |
b3e4e63f | 138 | walk: |
f59c1d2d AK |
139 | present = true; |
140 | eperm = rsvd_fault = false; | |
1e301feb JR |
141 | walker->level = mmu->root_level; |
142 | pte = mmu->get_cr3(vcpu); | |
143 | ||
1b0973bd | 144 | #if PTTYPE == 64 |
1e301feb | 145 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 146 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 147 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
148 | if (!is_present_gpte(pte)) { |
149 | present = false; | |
150 | goto error; | |
151 | } | |
1b0973bd AK |
152 | --walker->level; |
153 | } | |
154 | #endif | |
a9058ecd | 155 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 156 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 157 | |
fe135d2c | 158 | pt_access = ACC_ALL; |
ac79c978 AK |
159 | |
160 | for (;;) { | |
42bf3f0a | 161 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 162 | |
5fb07ddb | 163 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
164 | offset = index * sizeof(pt_element_t); |
165 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 166 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 167 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 168 | |
2329d46d JR |
169 | if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte, |
170 | offset, sizeof(pte), | |
171 | PFERR_USER_MASK|PFERR_WRITE_MASK)) { | |
f59c1d2d AK |
172 | present = false; |
173 | break; | |
174 | } | |
a6085fba | 175 | |
07420171 | 176 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 177 | |
f59c1d2d AK |
178 | if (!is_present_gpte(pte)) { |
179 | present = false; | |
180 | break; | |
181 | } | |
7993ba43 | 182 | |
3241f22d | 183 | if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) { |
f59c1d2d AK |
184 | rsvd_fault = true; |
185 | break; | |
186 | } | |
82725b20 | 187 | |
8dae4445 | 188 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 189 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 190 | eperm = true; |
7993ba43 | 191 | |
42bf3f0a | 192 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 193 | eperm = true; |
7993ba43 | 194 | |
73b1087e | 195 | #if PTTYPE == 64 |
24222c2f | 196 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 197 | eperm = true; |
73b1087e AK |
198 | #endif |
199 | ||
f59c1d2d | 200 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
a78484c6 | 201 | int ret; |
07420171 AK |
202 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
203 | sizeof(pte)); | |
a78484c6 RJ |
204 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, table_gfn, |
205 | index, pte, pte|PT_ACCESSED_MASK); | |
206 | if (ret < 0) { | |
207 | present = false; | |
208 | break; | |
209 | } else if (ret) | |
b3e4e63f | 210 | goto walk; |
a78484c6 | 211 | |
f3b8c964 | 212 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 213 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 214 | } |
815af8d4 | 215 | |
bedbe4ee | 216 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 217 | |
7819026e MT |
218 | walker->ptes[walker->level - 1] = pte; |
219 | ||
e04da980 JR |
220 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
221 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 222 | is_large_pte(pte) && |
e04da980 JR |
223 | (PTTYPE == 64 || is_pse(vcpu))) || |
224 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 225 | is_large_pte(pte) && |
1e301feb | 226 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 227 | int lvl = walker->level; |
2329d46d JR |
228 | gpa_t real_gpa; |
229 | gfn_t gfn; | |
33770780 | 230 | u32 ac; |
e04da980 | 231 | |
2329d46d JR |
232 | gfn = gpte_to_gfn_lvl(pte, lvl); |
233 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
234 | |
235 | if (PTTYPE == 32 && | |
236 | walker->level == PT_DIRECTORY_LEVEL && | |
237 | is_cpuid_PSE36()) | |
2329d46d JR |
238 | gfn += pse36_gfn_delta(pte); |
239 | ||
33770780 | 240 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
241 | |
242 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 243 | ac); |
2329d46d JR |
244 | if (real_gpa == UNMAPPED_GVA) |
245 | return 0; | |
246 | ||
247 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 248 | |
ac79c978 | 249 | break; |
815af8d4 | 250 | } |
ac79c978 | 251 | |
fe135d2c | 252 | pt_access = pte_access; |
ac79c978 AK |
253 | --walker->level; |
254 | } | |
42bf3f0a | 255 | |
f59c1d2d AK |
256 | if (!present || eperm || rsvd_fault) |
257 | goto error; | |
258 | ||
43a3795a | 259 | if (write_fault && !is_dirty_gpte(pte)) { |
a78484c6 | 260 | int ret; |
b3e4e63f | 261 | |
07420171 | 262 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
a78484c6 | 263 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, table_gfn, index, pte, |
b3e4e63f | 264 | pte|PT_DIRTY_MASK); |
a78484c6 RJ |
265 | if (ret < 0) { |
266 | present = false; | |
267 | goto error; | |
268 | } else if (ret) | |
b3e4e63f | 269 | goto walk; |
a78484c6 | 270 | |
f3b8c964 | 271 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 272 | pte |= PT_DIRTY_MASK; |
7819026e | 273 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
274 | } |
275 | ||
fe135d2c AK |
276 | walker->pt_access = pt_access; |
277 | walker->pte_access = pte_access; | |
278 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 279 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
280 | return 1; |
281 | ||
f59c1d2d | 282 | error: |
8c28d031 AK |
283 | walker->fault.vector = PF_VECTOR; |
284 | walker->fault.error_code_valid = true; | |
285 | walker->fault.error_code = 0; | |
f59c1d2d | 286 | if (present) |
8c28d031 | 287 | walker->fault.error_code |= PFERR_PRESENT_MASK; |
20bd40dc | 288 | |
8c28d031 | 289 | walker->fault.error_code |= write_fault | user_fault; |
20bd40dc | 290 | |
2d48a985 | 291 | if (fetch_fault && mmu->nx) |
8c28d031 | 292 | walker->fault.error_code |= PFERR_FETCH_MASK; |
82725b20 | 293 | if (rsvd_fault) |
8c28d031 | 294 | walker->fault.error_code |= PFERR_RSVD_MASK; |
8df25a32 | 295 | |
6389ee94 AK |
296 | walker->fault.address = addr; |
297 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 298 | |
8c28d031 | 299 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 300 | return 0; |
6aa8b732 AK |
301 | } |
302 | ||
1e301feb | 303 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 304 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
305 | { |
306 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 307 | access); |
1e301feb JR |
308 | } |
309 | ||
6539e738 JR |
310 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
311 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 312 | u32 access) |
6539e738 JR |
313 | { |
314 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 315 | addr, access); |
6539e738 JR |
316 | } |
317 | ||
407c61c6 XG |
318 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
319 | struct kvm_mmu_page *sp, u64 *spte, | |
320 | pt_element_t gpte) | |
321 | { | |
322 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
323 | ||
324 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
325 | goto no_present; | |
326 | ||
327 | if (!is_present_gpte(gpte)) { | |
328 | if (!sp->unsync) | |
329 | nonpresent = shadow_notrap_nonpresent_pte; | |
330 | goto no_present; | |
331 | } | |
332 | ||
333 | if (!(gpte & PT_ACCESSED_MASK)) | |
334 | goto no_present; | |
335 | ||
336 | return false; | |
337 | ||
338 | no_present: | |
339 | drop_spte(vcpu->kvm, spte, nonpresent); | |
340 | return true; | |
341 | } | |
342 | ||
ac3cd03c | 343 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 344 | u64 *spte, const void *pte) |
0028425f AK |
345 | { |
346 | pt_element_t gpte; | |
41074d07 | 347 | unsigned pte_access; |
35149e21 | 348 | pfn_t pfn; |
0028425f | 349 | |
0028425f | 350 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 351 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 352 | return; |
407c61c6 | 353 | |
b8688d51 | 354 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 355 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
0f53b5b1 XG |
356 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
357 | if (is_error_pfn(pfn)) { | |
358 | kvm_release_pfn_clean(pfn); | |
d7824fff | 359 | return; |
0f53b5b1 | 360 | } |
0f53b5b1 | 361 | |
1403283a | 362 | /* |
0d2eb44f | 363 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
364 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
365 | */ | |
ac3cd03c | 366 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 367 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 368 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
369 | } |
370 | ||
39c8c672 AK |
371 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
372 | struct guest_walker *gw, int level) | |
373 | { | |
39c8c672 | 374 | pt_element_t curr_pte; |
189be38d XG |
375 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
376 | u64 mask; | |
377 | int r, index; | |
378 | ||
379 | if (level == PT_PAGE_TABLE_LEVEL) { | |
380 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
381 | base_gpa = pte_gpa & ~mask; | |
382 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
383 | ||
384 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
385 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
386 | curr_pte = gw->prefetch_ptes[index]; | |
387 | } else | |
388 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 389 | &curr_pte, sizeof(curr_pte)); |
189be38d | 390 | |
39c8c672 AK |
391 | return r || curr_pte != gw->ptes[level - 1]; |
392 | } | |
393 | ||
189be38d XG |
394 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
395 | u64 *sptep) | |
957ed9ef XG |
396 | { |
397 | struct kvm_mmu_page *sp; | |
189be38d | 398 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 399 | u64 *spte; |
189be38d | 400 | int i; |
957ed9ef XG |
401 | |
402 | sp = page_header(__pa(sptep)); | |
403 | ||
404 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
405 | return; | |
406 | ||
407 | if (sp->role.direct) | |
408 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
409 | ||
410 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
411 | spte = sp->spt + i; |
412 | ||
413 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
414 | pt_element_t gpte; | |
415 | unsigned pte_access; | |
416 | gfn_t gfn; | |
417 | pfn_t pfn; | |
418 | bool dirty; | |
419 | ||
420 | if (spte == sptep) | |
421 | continue; | |
422 | ||
423 | if (*spte != shadow_trap_nonpresent_pte) | |
424 | continue; | |
425 | ||
426 | gpte = gptep[i]; | |
427 | ||
407c61c6 | 428 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
429 | continue; |
430 | ||
431 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
432 | gfn = gpte_to_gfn(gpte); | |
433 | dirty = is_dirty_gpte(gpte); | |
434 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
435 | (pte_access & ACC_WRITE_MASK) && dirty); | |
436 | if (is_error_pfn(pfn)) { | |
437 | kvm_release_pfn_clean(pfn); | |
438 | break; | |
439 | } | |
440 | ||
441 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
442 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
443 | pfn, true, true); | |
444 | } | |
445 | } | |
446 | ||
6aa8b732 AK |
447 | /* |
448 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
449 | */ | |
e7a04c99 AK |
450 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
451 | struct guest_walker *gw, | |
7e4e4056 | 452 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
453 | int *ptwrite, pfn_t pfn, bool map_writable, |
454 | bool prefault) | |
6aa8b732 | 455 | { |
abb9e0b8 | 456 | unsigned access = gw->pt_access; |
5991b332 | 457 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 458 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 459 | int top_level; |
84754cd8 | 460 | unsigned direct_access; |
24157aaf | 461 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 462 | |
43a3795a | 463 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 464 | return NULL; |
6aa8b732 | 465 | |
84754cd8 XG |
466 | direct_access = gw->pt_access & gw->pte_access; |
467 | if (!dirty) | |
468 | direct_access &= ~ACC_WRITE_MASK; | |
469 | ||
5991b332 AK |
470 | top_level = vcpu->arch.mmu.root_level; |
471 | if (top_level == PT32E_ROOT_LEVEL) | |
472 | top_level = PT32_ROOT_LEVEL; | |
473 | /* | |
474 | * Verify that the top-level gpte is still there. Since the page | |
475 | * is a root page, it is either write protected (and cannot be | |
476 | * changed from now on) or it is invalid (in which case, we don't | |
477 | * really care if it changes underneath us after this point). | |
478 | */ | |
479 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
480 | goto out_gpte_changed; | |
481 | ||
24157aaf AK |
482 | for (shadow_walk_init(&it, vcpu, addr); |
483 | shadow_walk_okay(&it) && it.level > gw->level; | |
484 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
485 | gfn_t table_gfn; |
486 | ||
24157aaf | 487 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 488 | |
5991b332 | 489 | sp = NULL; |
24157aaf AK |
490 | if (!is_shadow_present_pte(*it.sptep)) { |
491 | table_gfn = gw->table_gfn[it.level - 2]; | |
492 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
493 | false, access, it.sptep); | |
5991b332 | 494 | } |
0b3c9333 AK |
495 | |
496 | /* | |
497 | * Verify that the gpte in the page we've just write | |
498 | * protected is still there. | |
499 | */ | |
24157aaf | 500 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 501 | goto out_gpte_changed; |
abb9e0b8 | 502 | |
5991b332 | 503 | if (sp) |
24157aaf | 504 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 505 | } |
050e6499 | 506 | |
0b3c9333 | 507 | for (; |
24157aaf AK |
508 | shadow_walk_okay(&it) && it.level > hlevel; |
509 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
510 | gfn_t direct_gfn; |
511 | ||
24157aaf | 512 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 513 | |
24157aaf | 514 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 515 | |
24157aaf | 516 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
517 | continue; |
518 | ||
24157aaf | 519 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 520 | |
24157aaf AK |
521 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
522 | true, direct_access, it.sptep); | |
523 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
524 | } |
525 | ||
24157aaf AK |
526 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
527 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 528 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 529 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 530 | |
24157aaf | 531 | return it.sptep; |
0b3c9333 AK |
532 | |
533 | out_gpte_changed: | |
5991b332 | 534 | if (sp) |
24157aaf | 535 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
536 | kvm_release_pfn_clean(pfn); |
537 | return NULL; | |
6aa8b732 AK |
538 | } |
539 | ||
6aa8b732 AK |
540 | /* |
541 | * Page fault handler. There are several causes for a page fault: | |
542 | * - there is no shadow pte for the guest pte | |
543 | * - write access through a shadow pte marked read only so that we can set | |
544 | * the dirty bit | |
545 | * - write access to a shadow pte marked read only so we can update the page | |
546 | * dirty bitmap, when userspace requests it | |
547 | * - mmio access; in this case we will never install a present shadow pte | |
548 | * - normal guest page fault due to the guest pte marked not present, not | |
549 | * writable, or not executable | |
550 | * | |
e2dec939 AK |
551 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
552 | * a negative value on error. | |
6aa8b732 | 553 | */ |
56028d08 | 554 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 555 | bool prefault) |
6aa8b732 AK |
556 | { |
557 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
558 | int user_fault = error_code & PFERR_USER_MASK; |
559 | struct guest_walker walker; | |
d555c333 | 560 | u64 *sptep; |
cea0f0e7 | 561 | int write_pt = 0; |
e2dec939 | 562 | int r; |
35149e21 | 563 | pfn_t pfn; |
7e4e4056 | 564 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 565 | int force_pt_level; |
e930bffe | 566 | unsigned long mmu_seq; |
612819c3 | 567 | bool map_writable; |
6aa8b732 | 568 | |
b8688d51 | 569 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 570 | |
e2dec939 AK |
571 | r = mmu_topup_memory_caches(vcpu); |
572 | if (r) | |
573 | return r; | |
714b93da | 574 | |
6aa8b732 | 575 | /* |
a8b876b1 | 576 | * Look up the guest pte for the faulting address. |
6aa8b732 | 577 | */ |
33770780 | 578 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
579 | |
580 | /* | |
581 | * The page is not mapped by the guest. Let the guest handle it. | |
582 | */ | |
7993ba43 | 583 | if (!r) { |
b8688d51 | 584 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
585 | if (!prefault) { |
586 | inject_page_fault(vcpu, &walker.fault); | |
587 | /* reset fork detector */ | |
588 | vcpu->arch.last_pt_write_count = 0; | |
589 | } | |
6aa8b732 AK |
590 | return 0; |
591 | } | |
592 | ||
936a5fe6 AA |
593 | if (walker.level >= PT_DIRECTORY_LEVEL) |
594 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
595 | else | |
596 | force_pt_level = 1; | |
597 | if (!force_pt_level) { | |
7e4e4056 JR |
598 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
599 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 600 | } |
7e4e4056 | 601 | |
e930bffe | 602 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 603 | smp_rmb(); |
af585b92 | 604 | |
78b2c54a | 605 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 606 | &map_writable)) |
af585b92 | 607 | return 0; |
d7824fff | 608 | |
d196e343 | 609 | /* mmio */ |
bf998156 HY |
610 | if (is_error_pfn(pfn)) |
611 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 612 | |
aaee2c94 | 613 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
614 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
615 | goto out_unlock; | |
bc32ce21 | 616 | |
8b1fe17c | 617 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 618 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
619 | if (!force_pt_level) |
620 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 621 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 622 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 623 | (void)sptep; |
b8688d51 | 624 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 625 | sptep, *sptep, write_pt); |
cea0f0e7 | 626 | |
a25f7e1f | 627 | if (!write_pt) |
ad312c7c | 628 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 629 | |
1165f5fe | 630 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 631 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 632 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 633 | |
cea0f0e7 | 634 | return write_pt; |
e930bffe AA |
635 | |
636 | out_unlock: | |
637 | spin_unlock(&vcpu->kvm->mmu_lock); | |
638 | kvm_release_pfn_clean(pfn); | |
639 | return 0; | |
6aa8b732 AK |
640 | } |
641 | ||
a461930b | 642 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 643 | { |
a461930b | 644 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 645 | struct kvm_mmu_page *sp; |
08e850c6 | 646 | gpa_t pte_gpa = -1; |
a461930b AK |
647 | int level; |
648 | u64 *sptep; | |
4539b358 | 649 | int need_flush = 0; |
a461930b AK |
650 | |
651 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 652 | |
a461930b AK |
653 | for_each_shadow_entry(vcpu, gva, iterator) { |
654 | level = iterator.level; | |
655 | sptep = iterator.sptep; | |
ad218f85 | 656 | |
f78978aa | 657 | sp = page_header(__pa(sptep)); |
884a0ff0 | 658 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 659 | int offset, shift; |
08e850c6 | 660 | |
f78978aa XG |
661 | if (!sp->unsync) |
662 | break; | |
663 | ||
22c9b2d1 XG |
664 | shift = PAGE_SHIFT - |
665 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
666 | offset = sp->role.quadrant << shift; | |
667 | ||
668 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 669 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
670 | |
671 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
672 | if (is_large_pte(*sptep)) |
673 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
674 | drop_spte(vcpu->kvm, sptep, |
675 | shadow_trap_nonpresent_pte); | |
4539b358 | 676 | need_flush = 1; |
be38d276 AK |
677 | } else |
678 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 679 | break; |
87917239 | 680 | } |
a7052897 | 681 | |
f78978aa | 682 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
683 | break; |
684 | } | |
a7052897 | 685 | |
4539b358 AA |
686 | if (need_flush) |
687 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
688 | |
689 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
690 | ||
ad218f85 | 691 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
692 | |
693 | if (pte_gpa == -1) | |
694 | return; | |
695 | ||
696 | if (mmu_topup_memory_caches(vcpu)) | |
697 | return; | |
698 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
699 | } |
700 | ||
1871c602 | 701 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 702 | struct x86_exception *exception) |
6aa8b732 AK |
703 | { |
704 | struct guest_walker walker; | |
e119d117 AK |
705 | gpa_t gpa = UNMAPPED_GVA; |
706 | int r; | |
6aa8b732 | 707 | |
33770780 | 708 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 709 | |
e119d117 | 710 | if (r) { |
1755fbcc | 711 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 712 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
713 | } else if (exception) |
714 | *exception = walker.fault; | |
6aa8b732 AK |
715 | |
716 | return gpa; | |
717 | } | |
718 | ||
6539e738 | 719 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
720 | u32 access, |
721 | struct x86_exception *exception) | |
6539e738 JR |
722 | { |
723 | struct guest_walker walker; | |
724 | gpa_t gpa = UNMAPPED_GVA; | |
725 | int r; | |
726 | ||
33770780 | 727 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
728 | |
729 | if (r) { | |
730 | gpa = gfn_to_gpa(walker.gfn); | |
731 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
732 | } else if (exception) |
733 | *exception = walker.fault; | |
6539e738 JR |
734 | |
735 | return gpa; | |
736 | } | |
737 | ||
c7addb90 AK |
738 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
739 | struct kvm_mmu_page *sp) | |
740 | { | |
eab9f71f AK |
741 | int i, j, offset, r; |
742 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
743 | gpa_t pte_gpa; | |
c7addb90 | 744 | |
f6e2c02b | 745 | if (sp->role.direct |
e5a4c8ca | 746 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
747 | nonpaging_prefetch_page(vcpu, sp); |
748 | return; | |
749 | } | |
750 | ||
eab9f71f AK |
751 | pte_gpa = gfn_to_gpa(sp->gfn); |
752 | if (PTTYPE == 32) { | |
e5a4c8ca | 753 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
754 | pte_gpa += offset * sizeof(pt_element_t); |
755 | } | |
7ec54588 | 756 | |
eab9f71f AK |
757 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
758 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
759 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
760 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 761 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
762 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
763 | else | |
764 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 765 | } |
c7addb90 AK |
766 | } |
767 | ||
e8bc217a MT |
768 | /* |
769 | * Using the cached information from sp->gfns is safe because: | |
770 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
771 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
772 | * |
773 | * Note: | |
774 | * We should flush all tlbs if spte is dropped even though guest is | |
775 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
776 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
777 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
778 | * freed pages. | |
779 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 780 | */ |
a4a8e6f7 | 781 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
782 | { |
783 | int i, offset, nr_present; | |
9bdbba13 | 784 | bool host_writable; |
51fb60d8 | 785 | gpa_t first_pte_gpa; |
e8bc217a MT |
786 | |
787 | offset = nr_present = 0; | |
788 | ||
2032a93d LJ |
789 | /* direct kvm_mmu_page can not be unsync. */ |
790 | BUG_ON(sp->role.direct); | |
791 | ||
e8bc217a MT |
792 | if (PTTYPE == 32) |
793 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
794 | ||
51fb60d8 GJ |
795 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
796 | ||
e8bc217a MT |
797 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
798 | unsigned pte_access; | |
799 | pt_element_t gpte; | |
800 | gpa_t pte_gpa; | |
f55c3f41 | 801 | gfn_t gfn; |
e8bc217a MT |
802 | |
803 | if (!is_shadow_present_pte(sp->spt[i])) | |
804 | continue; | |
805 | ||
51fb60d8 | 806 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
807 | |
808 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
809 | sizeof(pt_element_t))) | |
810 | return -EINVAL; | |
811 | ||
f55c3f41 | 812 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
813 | |
814 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 815 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
816 | continue; |
817 | } | |
818 | ||
819 | if (gfn != sp->gfns[i]) { | |
820 | drop_spte(vcpu->kvm, &sp->spt[i], | |
821 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 822 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
823 | continue; |
824 | } | |
825 | ||
826 | nr_present++; | |
827 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
f8e453b0 XG |
828 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
829 | ||
e8bc217a | 830 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 831 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 832 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 833 | host_writable); |
e8bc217a MT |
834 | } |
835 | ||
836 | return !nr_present; | |
837 | } | |
838 | ||
6aa8b732 AK |
839 | #undef pt_element_t |
840 | #undef guest_walker | |
841 | #undef FNAME | |
842 | #undef PT_BASE_ADDR_MASK | |
843 | #undef PT_INDEX | |
e04da980 JR |
844 | #undef PT_LVL_ADDR_MASK |
845 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 846 | #undef PT_LEVEL_BITS |
cea0f0e7 | 847 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 848 | #undef gpte_to_gfn |
e04da980 | 849 | #undef gpte_to_gfn_lvl |
b3e4e63f | 850 | #undef CMPXCHG |