Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
b3e4e63f MT |
81 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
82 | gfn_t table_gfn, unsigned index, | |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
84 | { | |
85 | pt_element_t ret; | |
86 | pt_element_t *table; | |
87 | struct page *page; | |
88 | ||
89 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 90 | |
b3e4e63f | 91 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 92 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
93 | kunmap_atomic(table, KM_USER0); |
94 | ||
95 | kvm_release_page_dirty(page); | |
96 | ||
97 | return (ret != orig_pte); | |
98 | } | |
99 | ||
bedbe4ee AK |
100 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
101 | { | |
102 | unsigned access; | |
103 | ||
104 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
105 | #if PTTYPE == 64 | |
2d48a985 | 106 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
107 | access &= ~(gpte >> PT64_NX_SHIFT); |
108 | #endif | |
109 | return access; | |
110 | } | |
111 | ||
ac79c978 AK |
112 | /* |
113 | * Fetch a guest pte for a guest virtual address | |
114 | */ | |
1e301feb JR |
115 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
116 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 117 | gva_t addr, u32 access) |
6aa8b732 | 118 | { |
42bf3f0a | 119 | pt_element_t pte; |
cea0f0e7 | 120 | gfn_t table_gfn; |
f59c1d2d | 121 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 122 | gpa_t pte_gpa; |
f59c1d2d | 123 | bool eperm, present, rsvd_fault; |
33770780 XG |
124 | int offset, write_fault, user_fault, fetch_fault; |
125 | ||
126 | write_fault = access & PFERR_WRITE_MASK; | |
127 | user_fault = access & PFERR_USER_MASK; | |
128 | fetch_fault = access & PFERR_FETCH_MASK; | |
6aa8b732 | 129 | |
07420171 AK |
130 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
131 | fetch_fault); | |
b3e4e63f | 132 | walk: |
f59c1d2d AK |
133 | present = true; |
134 | eperm = rsvd_fault = false; | |
1e301feb JR |
135 | walker->level = mmu->root_level; |
136 | pte = mmu->get_cr3(vcpu); | |
137 | ||
1b0973bd | 138 | #if PTTYPE == 64 |
1e301feb | 139 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 140 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 141 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
142 | if (!is_present_gpte(pte)) { |
143 | present = false; | |
144 | goto error; | |
145 | } | |
1b0973bd AK |
146 | --walker->level; |
147 | } | |
148 | #endif | |
a9058ecd | 149 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 150 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 151 | |
fe135d2c | 152 | pt_access = ACC_ALL; |
ac79c978 AK |
153 | |
154 | for (;;) { | |
42bf3f0a | 155 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 156 | |
5fb07ddb | 157 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
158 | offset = index * sizeof(pt_element_t); |
159 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 160 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 161 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 162 | |
2329d46d JR |
163 | if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte, |
164 | offset, sizeof(pte), | |
165 | PFERR_USER_MASK|PFERR_WRITE_MASK)) { | |
f59c1d2d AK |
166 | present = false; |
167 | break; | |
168 | } | |
a6085fba | 169 | |
07420171 | 170 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 171 | |
f59c1d2d AK |
172 | if (!is_present_gpte(pte)) { |
173 | present = false; | |
174 | break; | |
175 | } | |
7993ba43 | 176 | |
3241f22d | 177 | if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) { |
f59c1d2d AK |
178 | rsvd_fault = true; |
179 | break; | |
180 | } | |
82725b20 | 181 | |
8dae4445 | 182 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 183 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 184 | eperm = true; |
7993ba43 | 185 | |
42bf3f0a | 186 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 187 | eperm = true; |
7993ba43 | 188 | |
73b1087e | 189 | #if PTTYPE == 64 |
24222c2f | 190 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 191 | eperm = true; |
73b1087e AK |
192 | #endif |
193 | ||
f59c1d2d | 194 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
07420171 AK |
195 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
196 | sizeof(pte)); | |
b3e4e63f MT |
197 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
198 | index, pte, pte|PT_ACCESSED_MASK)) | |
199 | goto walk; | |
f3b8c964 | 200 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 201 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 202 | } |
815af8d4 | 203 | |
bedbe4ee | 204 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 205 | |
7819026e MT |
206 | walker->ptes[walker->level - 1] = pte; |
207 | ||
e04da980 JR |
208 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
209 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 210 | is_large_pte(pte) && |
e04da980 JR |
211 | (PTTYPE == 64 || is_pse(vcpu))) || |
212 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 213 | is_large_pte(pte) && |
1e301feb | 214 | mmu->root_level == PT64_ROOT_LEVEL)) { |
e04da980 | 215 | int lvl = walker->level; |
2329d46d JR |
216 | gpa_t real_gpa; |
217 | gfn_t gfn; | |
33770780 | 218 | u32 ac; |
e04da980 | 219 | |
2329d46d JR |
220 | gfn = gpte_to_gfn_lvl(pte, lvl); |
221 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
222 | |
223 | if (PTTYPE == 32 && | |
224 | walker->level == PT_DIRECTORY_LEVEL && | |
225 | is_cpuid_PSE36()) | |
2329d46d JR |
226 | gfn += pse36_gfn_delta(pte); |
227 | ||
33770780 | 228 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
229 | |
230 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 231 | ac); |
2329d46d JR |
232 | if (real_gpa == UNMAPPED_GVA) |
233 | return 0; | |
234 | ||
235 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 236 | |
ac79c978 | 237 | break; |
815af8d4 | 238 | } |
ac79c978 | 239 | |
fe135d2c | 240 | pt_access = pte_access; |
ac79c978 AK |
241 | --walker->level; |
242 | } | |
42bf3f0a | 243 | |
f59c1d2d AK |
244 | if (!present || eperm || rsvd_fault) |
245 | goto error; | |
246 | ||
43a3795a | 247 | if (write_fault && !is_dirty_gpte(pte)) { |
b3e4e63f MT |
248 | bool ret; |
249 | ||
07420171 | 250 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
b3e4e63f MT |
251 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
252 | pte|PT_DIRTY_MASK); | |
253 | if (ret) | |
254 | goto walk; | |
f3b8c964 | 255 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 256 | pte |= PT_DIRTY_MASK; |
7819026e | 257 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
258 | } |
259 | ||
fe135d2c AK |
260 | walker->pt_access = pt_access; |
261 | walker->pte_access = pte_access; | |
262 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 263 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
264 | return 1; |
265 | ||
f59c1d2d | 266 | error: |
8c28d031 AK |
267 | walker->fault.vector = PF_VECTOR; |
268 | walker->fault.error_code_valid = true; | |
269 | walker->fault.error_code = 0; | |
f59c1d2d | 270 | if (present) |
8c28d031 | 271 | walker->fault.error_code |= PFERR_PRESENT_MASK; |
20bd40dc | 272 | |
8c28d031 | 273 | walker->fault.error_code |= write_fault | user_fault; |
20bd40dc | 274 | |
2d48a985 | 275 | if (fetch_fault && mmu->nx) |
8c28d031 | 276 | walker->fault.error_code |= PFERR_FETCH_MASK; |
82725b20 | 277 | if (rsvd_fault) |
8c28d031 | 278 | walker->fault.error_code |= PFERR_RSVD_MASK; |
8df25a32 | 279 | |
6389ee94 AK |
280 | walker->fault.address = addr; |
281 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 282 | |
8c28d031 | 283 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 284 | return 0; |
6aa8b732 AK |
285 | } |
286 | ||
1e301feb | 287 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 288 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
289 | { |
290 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 291 | access); |
1e301feb JR |
292 | } |
293 | ||
6539e738 JR |
294 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
295 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 296 | u32 access) |
6539e738 JR |
297 | { |
298 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 299 | addr, access); |
6539e738 JR |
300 | } |
301 | ||
407c61c6 XG |
302 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
303 | struct kvm_mmu_page *sp, u64 *spte, | |
304 | pt_element_t gpte) | |
305 | { | |
306 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
307 | ||
308 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
309 | goto no_present; | |
310 | ||
311 | if (!is_present_gpte(gpte)) { | |
312 | if (!sp->unsync) | |
313 | nonpresent = shadow_notrap_nonpresent_pte; | |
314 | goto no_present; | |
315 | } | |
316 | ||
317 | if (!(gpte & PT_ACCESSED_MASK)) | |
318 | goto no_present; | |
319 | ||
320 | return false; | |
321 | ||
322 | no_present: | |
323 | drop_spte(vcpu->kvm, spte, nonpresent); | |
324 | return true; | |
325 | } | |
326 | ||
ac3cd03c | 327 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
0f53b5b1 | 328 | u64 *spte, const void *pte, unsigned long mmu_seq) |
0028425f AK |
329 | { |
330 | pt_element_t gpte; | |
41074d07 | 331 | unsigned pte_access; |
35149e21 | 332 | pfn_t pfn; |
0028425f | 333 | |
0028425f | 334 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 335 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 336 | return; |
407c61c6 | 337 | |
b8688d51 | 338 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 339 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
0f53b5b1 XG |
340 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
341 | if (is_error_pfn(pfn)) { | |
342 | kvm_release_pfn_clean(pfn); | |
d7824fff | 343 | return; |
0f53b5b1 XG |
344 | } |
345 | if (mmu_notifier_retry(vcpu, mmu_seq)) | |
e930bffe | 346 | return; |
0f53b5b1 | 347 | |
1403283a | 348 | /* |
0d2eb44f | 349 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
350 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
351 | */ | |
ac3cd03c | 352 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 353 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 354 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
355 | } |
356 | ||
39c8c672 AK |
357 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
358 | struct guest_walker *gw, int level) | |
359 | { | |
39c8c672 | 360 | pt_element_t curr_pte; |
189be38d XG |
361 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
362 | u64 mask; | |
363 | int r, index; | |
364 | ||
365 | if (level == PT_PAGE_TABLE_LEVEL) { | |
366 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
367 | base_gpa = pte_gpa & ~mask; | |
368 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
369 | ||
370 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
371 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
372 | curr_pte = gw->prefetch_ptes[index]; | |
373 | } else | |
374 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 375 | &curr_pte, sizeof(curr_pte)); |
189be38d | 376 | |
39c8c672 AK |
377 | return r || curr_pte != gw->ptes[level - 1]; |
378 | } | |
379 | ||
189be38d XG |
380 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
381 | u64 *sptep) | |
957ed9ef XG |
382 | { |
383 | struct kvm_mmu_page *sp; | |
189be38d | 384 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 385 | u64 *spte; |
189be38d | 386 | int i; |
957ed9ef XG |
387 | |
388 | sp = page_header(__pa(sptep)); | |
389 | ||
390 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
391 | return; | |
392 | ||
393 | if (sp->role.direct) | |
394 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
395 | ||
396 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
397 | spte = sp->spt + i; |
398 | ||
399 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
400 | pt_element_t gpte; | |
401 | unsigned pte_access; | |
402 | gfn_t gfn; | |
403 | pfn_t pfn; | |
404 | bool dirty; | |
405 | ||
406 | if (spte == sptep) | |
407 | continue; | |
408 | ||
409 | if (*spte != shadow_trap_nonpresent_pte) | |
410 | continue; | |
411 | ||
412 | gpte = gptep[i]; | |
413 | ||
407c61c6 | 414 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
415 | continue; |
416 | ||
417 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
418 | gfn = gpte_to_gfn(gpte); | |
419 | dirty = is_dirty_gpte(gpte); | |
420 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
421 | (pte_access & ACC_WRITE_MASK) && dirty); | |
422 | if (is_error_pfn(pfn)) { | |
423 | kvm_release_pfn_clean(pfn); | |
424 | break; | |
425 | } | |
426 | ||
427 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
428 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
429 | pfn, true, true); | |
430 | } | |
431 | } | |
432 | ||
6aa8b732 AK |
433 | /* |
434 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
435 | */ | |
e7a04c99 AK |
436 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
437 | struct guest_walker *gw, | |
7e4e4056 | 438 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
439 | int *ptwrite, pfn_t pfn, bool map_writable, |
440 | bool prefault) | |
6aa8b732 | 441 | { |
abb9e0b8 | 442 | unsigned access = gw->pt_access; |
5991b332 | 443 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 444 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 445 | int top_level; |
84754cd8 | 446 | unsigned direct_access; |
24157aaf | 447 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 448 | |
43a3795a | 449 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 450 | return NULL; |
6aa8b732 | 451 | |
84754cd8 XG |
452 | direct_access = gw->pt_access & gw->pte_access; |
453 | if (!dirty) | |
454 | direct_access &= ~ACC_WRITE_MASK; | |
455 | ||
5991b332 AK |
456 | top_level = vcpu->arch.mmu.root_level; |
457 | if (top_level == PT32E_ROOT_LEVEL) | |
458 | top_level = PT32_ROOT_LEVEL; | |
459 | /* | |
460 | * Verify that the top-level gpte is still there. Since the page | |
461 | * is a root page, it is either write protected (and cannot be | |
462 | * changed from now on) or it is invalid (in which case, we don't | |
463 | * really care if it changes underneath us after this point). | |
464 | */ | |
465 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
466 | goto out_gpte_changed; | |
467 | ||
24157aaf AK |
468 | for (shadow_walk_init(&it, vcpu, addr); |
469 | shadow_walk_okay(&it) && it.level > gw->level; | |
470 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
471 | gfn_t table_gfn; |
472 | ||
24157aaf | 473 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 474 | |
5991b332 | 475 | sp = NULL; |
24157aaf AK |
476 | if (!is_shadow_present_pte(*it.sptep)) { |
477 | table_gfn = gw->table_gfn[it.level - 2]; | |
478 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
479 | false, access, it.sptep); | |
5991b332 | 480 | } |
0b3c9333 AK |
481 | |
482 | /* | |
483 | * Verify that the gpte in the page we've just write | |
484 | * protected is still there. | |
485 | */ | |
24157aaf | 486 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 487 | goto out_gpte_changed; |
abb9e0b8 | 488 | |
5991b332 | 489 | if (sp) |
24157aaf | 490 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 491 | } |
050e6499 | 492 | |
0b3c9333 | 493 | for (; |
24157aaf AK |
494 | shadow_walk_okay(&it) && it.level > hlevel; |
495 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
496 | gfn_t direct_gfn; |
497 | ||
24157aaf | 498 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 499 | |
24157aaf | 500 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 501 | |
24157aaf | 502 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
503 | continue; |
504 | ||
24157aaf | 505 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 506 | |
24157aaf AK |
507 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
508 | true, direct_access, it.sptep); | |
509 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
510 | } |
511 | ||
24157aaf AK |
512 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
513 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 514 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 515 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 516 | |
24157aaf | 517 | return it.sptep; |
0b3c9333 AK |
518 | |
519 | out_gpte_changed: | |
5991b332 | 520 | if (sp) |
24157aaf | 521 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
522 | kvm_release_pfn_clean(pfn); |
523 | return NULL; | |
6aa8b732 AK |
524 | } |
525 | ||
6aa8b732 AK |
526 | /* |
527 | * Page fault handler. There are several causes for a page fault: | |
528 | * - there is no shadow pte for the guest pte | |
529 | * - write access through a shadow pte marked read only so that we can set | |
530 | * the dirty bit | |
531 | * - write access to a shadow pte marked read only so we can update the page | |
532 | * dirty bitmap, when userspace requests it | |
533 | * - mmio access; in this case we will never install a present shadow pte | |
534 | * - normal guest page fault due to the guest pte marked not present, not | |
535 | * writable, or not executable | |
536 | * | |
e2dec939 AK |
537 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
538 | * a negative value on error. | |
6aa8b732 | 539 | */ |
56028d08 | 540 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 541 | bool prefault) |
6aa8b732 AK |
542 | { |
543 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
544 | int user_fault = error_code & PFERR_USER_MASK; |
545 | struct guest_walker walker; | |
d555c333 | 546 | u64 *sptep; |
cea0f0e7 | 547 | int write_pt = 0; |
e2dec939 | 548 | int r; |
35149e21 | 549 | pfn_t pfn; |
7e4e4056 | 550 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 551 | int force_pt_level; |
e930bffe | 552 | unsigned long mmu_seq; |
612819c3 | 553 | bool map_writable; |
6aa8b732 | 554 | |
b8688d51 | 555 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 556 | |
e2dec939 AK |
557 | r = mmu_topup_memory_caches(vcpu); |
558 | if (r) | |
559 | return r; | |
714b93da | 560 | |
6aa8b732 | 561 | /* |
a8b876b1 | 562 | * Look up the guest pte for the faulting address. |
6aa8b732 | 563 | */ |
33770780 | 564 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
565 | |
566 | /* | |
567 | * The page is not mapped by the guest. Let the guest handle it. | |
568 | */ | |
7993ba43 | 569 | if (!r) { |
b8688d51 | 570 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
571 | if (!prefault) { |
572 | inject_page_fault(vcpu, &walker.fault); | |
573 | /* reset fork detector */ | |
574 | vcpu->arch.last_pt_write_count = 0; | |
575 | } | |
6aa8b732 AK |
576 | return 0; |
577 | } | |
578 | ||
936a5fe6 AA |
579 | if (walker.level >= PT_DIRECTORY_LEVEL) |
580 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
581 | else | |
582 | force_pt_level = 1; | |
583 | if (!force_pt_level) { | |
7e4e4056 JR |
584 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
585 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 586 | } |
7e4e4056 | 587 | |
e930bffe | 588 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 589 | smp_rmb(); |
af585b92 | 590 | |
78b2c54a | 591 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 592 | &map_writable)) |
af585b92 | 593 | return 0; |
d7824fff | 594 | |
d196e343 | 595 | /* mmio */ |
bf998156 HY |
596 | if (is_error_pfn(pfn)) |
597 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 598 | |
aaee2c94 | 599 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
600 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
601 | goto out_unlock; | |
bc32ce21 | 602 | |
8b1fe17c | 603 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 604 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
605 | if (!force_pt_level) |
606 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 607 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 608 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 609 | (void)sptep; |
b8688d51 | 610 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 611 | sptep, *sptep, write_pt); |
cea0f0e7 | 612 | |
a25f7e1f | 613 | if (!write_pt) |
ad312c7c | 614 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 615 | |
1165f5fe | 616 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 617 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 618 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 619 | |
cea0f0e7 | 620 | return write_pt; |
e930bffe AA |
621 | |
622 | out_unlock: | |
623 | spin_unlock(&vcpu->kvm->mmu_lock); | |
624 | kvm_release_pfn_clean(pfn); | |
625 | return 0; | |
6aa8b732 AK |
626 | } |
627 | ||
a461930b | 628 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 629 | { |
a461930b | 630 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 631 | struct kvm_mmu_page *sp; |
08e850c6 | 632 | gpa_t pte_gpa = -1; |
a461930b AK |
633 | int level; |
634 | u64 *sptep; | |
4539b358 | 635 | int need_flush = 0; |
a461930b AK |
636 | |
637 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 638 | |
a461930b AK |
639 | for_each_shadow_entry(vcpu, gva, iterator) { |
640 | level = iterator.level; | |
641 | sptep = iterator.sptep; | |
ad218f85 | 642 | |
f78978aa | 643 | sp = page_header(__pa(sptep)); |
884a0ff0 | 644 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 645 | int offset, shift; |
08e850c6 | 646 | |
f78978aa XG |
647 | if (!sp->unsync) |
648 | break; | |
649 | ||
22c9b2d1 XG |
650 | shift = PAGE_SHIFT - |
651 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
652 | offset = sp->role.quadrant << shift; | |
653 | ||
654 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 655 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
656 | |
657 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
658 | if (is_large_pte(*sptep)) |
659 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
660 | drop_spte(vcpu->kvm, sptep, |
661 | shadow_trap_nonpresent_pte); | |
4539b358 | 662 | need_flush = 1; |
be38d276 AK |
663 | } else |
664 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 665 | break; |
87917239 | 666 | } |
a7052897 | 667 | |
f78978aa | 668 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
669 | break; |
670 | } | |
a7052897 | 671 | |
4539b358 AA |
672 | if (need_flush) |
673 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
674 | |
675 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
676 | ||
ad218f85 | 677 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
678 | |
679 | if (pte_gpa == -1) | |
680 | return; | |
681 | ||
682 | if (mmu_topup_memory_caches(vcpu)) | |
683 | return; | |
684 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
685 | } |
686 | ||
1871c602 | 687 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 688 | struct x86_exception *exception) |
6aa8b732 AK |
689 | { |
690 | struct guest_walker walker; | |
e119d117 AK |
691 | gpa_t gpa = UNMAPPED_GVA; |
692 | int r; | |
6aa8b732 | 693 | |
33770780 | 694 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 695 | |
e119d117 | 696 | if (r) { |
1755fbcc | 697 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 698 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
699 | } else if (exception) |
700 | *exception = walker.fault; | |
6aa8b732 AK |
701 | |
702 | return gpa; | |
703 | } | |
704 | ||
6539e738 | 705 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
706 | u32 access, |
707 | struct x86_exception *exception) | |
6539e738 JR |
708 | { |
709 | struct guest_walker walker; | |
710 | gpa_t gpa = UNMAPPED_GVA; | |
711 | int r; | |
712 | ||
33770780 | 713 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
714 | |
715 | if (r) { | |
716 | gpa = gfn_to_gpa(walker.gfn); | |
717 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
718 | } else if (exception) |
719 | *exception = walker.fault; | |
6539e738 JR |
720 | |
721 | return gpa; | |
722 | } | |
723 | ||
c7addb90 AK |
724 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
725 | struct kvm_mmu_page *sp) | |
726 | { | |
eab9f71f AK |
727 | int i, j, offset, r; |
728 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
729 | gpa_t pte_gpa; | |
c7addb90 | 730 | |
f6e2c02b | 731 | if (sp->role.direct |
e5a4c8ca | 732 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
733 | nonpaging_prefetch_page(vcpu, sp); |
734 | return; | |
735 | } | |
736 | ||
eab9f71f AK |
737 | pte_gpa = gfn_to_gpa(sp->gfn); |
738 | if (PTTYPE == 32) { | |
e5a4c8ca | 739 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
740 | pte_gpa += offset * sizeof(pt_element_t); |
741 | } | |
7ec54588 | 742 | |
eab9f71f AK |
743 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
744 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
745 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
746 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 747 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
748 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
749 | else | |
750 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 751 | } |
c7addb90 AK |
752 | } |
753 | ||
e8bc217a MT |
754 | /* |
755 | * Using the cached information from sp->gfns is safe because: | |
756 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
757 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
758 | * |
759 | * Note: | |
760 | * We should flush all tlbs if spte is dropped even though guest is | |
761 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
762 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
763 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
764 | * freed pages. | |
765 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 766 | */ |
a4a8e6f7 | 767 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
768 | { |
769 | int i, offset, nr_present; | |
9bdbba13 | 770 | bool host_writable; |
51fb60d8 | 771 | gpa_t first_pte_gpa; |
e8bc217a MT |
772 | |
773 | offset = nr_present = 0; | |
774 | ||
2032a93d LJ |
775 | /* direct kvm_mmu_page can not be unsync. */ |
776 | BUG_ON(sp->role.direct); | |
777 | ||
e8bc217a MT |
778 | if (PTTYPE == 32) |
779 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
780 | ||
51fb60d8 GJ |
781 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
782 | ||
e8bc217a MT |
783 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
784 | unsigned pte_access; | |
785 | pt_element_t gpte; | |
786 | gpa_t pte_gpa; | |
f55c3f41 | 787 | gfn_t gfn; |
e8bc217a MT |
788 | |
789 | if (!is_shadow_present_pte(sp->spt[i])) | |
790 | continue; | |
791 | ||
51fb60d8 | 792 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
793 | |
794 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
795 | sizeof(pt_element_t))) | |
796 | return -EINVAL; | |
797 | ||
f55c3f41 | 798 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
799 | |
800 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 801 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
802 | continue; |
803 | } | |
804 | ||
805 | if (gfn != sp->gfns[i]) { | |
806 | drop_spte(vcpu->kvm, &sp->spt[i], | |
807 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 808 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
809 | continue; |
810 | } | |
811 | ||
812 | nr_present++; | |
813 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
f8e453b0 XG |
814 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
815 | ||
e8bc217a | 816 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 817 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 818 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 819 | host_writable); |
e8bc217a MT |
820 | } |
821 | ||
822 | return !nr_present; | |
823 | } | |
824 | ||
6aa8b732 AK |
825 | #undef pt_element_t |
826 | #undef guest_walker | |
827 | #undef FNAME | |
828 | #undef PT_BASE_ADDR_MASK | |
829 | #undef PT_INDEX | |
e04da980 JR |
830 | #undef PT_LVL_ADDR_MASK |
831 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 832 | #undef PT_LEVEL_BITS |
cea0f0e7 | 833 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 834 | #undef gpte_to_gfn |
e04da980 | 835 | #undef gpte_to_gfn_lvl |
b3e4e63f | 836 | #undef CMPXCHG |