Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
37406aaa NHE |
26 | /* |
27 | * This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro | |
28 | * uses for EPT without A/D paging type. | |
29 | */ | |
30 | extern u64 __pure __using_nonexistent_pte_bit(void) | |
31 | __compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT"); | |
32 | ||
6aa8b732 AK |
33 | #if PTTYPE == 64 |
34 | #define pt_element_t u64 | |
35 | #define guest_walker guest_walker64 | |
36 | #define FNAME(name) paging##64_##name | |
37 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
38 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
39 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 40 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 41 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
d8089bac GN |
42 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
43 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
44 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
45 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
cea0f0e7 AK |
46 | #ifdef CONFIG_X86_64 |
47 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 48 | #define CMPXCHG cmpxchg |
cea0f0e7 | 49 | #else |
b3e4e63f | 50 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
51 | #define PT_MAX_FULL_LEVELS 2 |
52 | #endif | |
6aa8b732 AK |
53 | #elif PTTYPE == 32 |
54 | #define pt_element_t u32 | |
55 | #define guest_walker guest_walker32 | |
56 | #define FNAME(name) paging##32_##name | |
57 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
58 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
59 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 60 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 61 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 62 | #define PT_MAX_FULL_LEVELS 2 |
d8089bac GN |
63 | #define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK |
64 | #define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK | |
65 | #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT | |
66 | #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT | |
b3e4e63f | 67 | #define CMPXCHG cmpxchg |
37406aaa NHE |
68 | #elif PTTYPE == PTTYPE_EPT |
69 | #define pt_element_t u64 | |
70 | #define guest_walker guest_walkerEPT | |
71 | #define FNAME(name) ept_##name | |
72 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
73 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) | |
74 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
75 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
76 | #define PT_LEVEL_BITS PT64_LEVEL_BITS | |
77 | #define PT_GUEST_ACCESSED_MASK 0 | |
78 | #define PT_GUEST_DIRTY_MASK 0 | |
79 | #define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit() | |
80 | #define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit() | |
81 | #define CMPXCHG cmpxchg64 | |
82 | #define PT_MAX_FULL_LEVELS 4 | |
6aa8b732 AK |
83 | #else |
84 | #error Invalid PTTYPE value | |
85 | #endif | |
86 | ||
e04da980 JR |
87 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
88 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 89 | |
6aa8b732 AK |
90 | /* |
91 | * The guest_walker structure emulates the behavior of the hardware page | |
92 | * table walker. | |
93 | */ | |
94 | struct guest_walker { | |
95 | int level; | |
8cbc7069 | 96 | unsigned max_level; |
cea0f0e7 | 97 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 98 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 99 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 100 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 101 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
ba6a3541 | 102 | bool pte_writable[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
103 | unsigned pt_access; |
104 | unsigned pte_access; | |
815af8d4 | 105 | gfn_t gfn; |
8c28d031 | 106 | struct x86_exception fault; |
6aa8b732 AK |
107 | }; |
108 | ||
e04da980 | 109 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 110 | { |
e04da980 | 111 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
112 | } |
113 | ||
0ad805a0 NHE |
114 | static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte) |
115 | { | |
116 | unsigned mask; | |
117 | ||
61719a8f GN |
118 | /* dirty bit is not supported, so no need to track it */ |
119 | if (!PT_GUEST_DIRTY_MASK) | |
120 | return; | |
121 | ||
0ad805a0 NHE |
122 | BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK); |
123 | ||
124 | mask = (unsigned)~ACC_WRITE_MASK; | |
125 | /* Allow write access to dirty gptes */ | |
d8089bac GN |
126 | mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & |
127 | PT_WRITABLE_MASK; | |
0ad805a0 NHE |
128 | *access &= mask; |
129 | } | |
130 | ||
131 | static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level) | |
132 | { | |
25d92081 | 133 | int bit7 = (gpte >> 7) & 1, low6 = gpte & 0x3f; |
0ad805a0 | 134 | |
25d92081 YZ |
135 | return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) | |
136 | ((mmu->bad_mt_xwr & (1ull << low6)) != 0); | |
0ad805a0 NHE |
137 | } |
138 | ||
139 | static inline int FNAME(is_present_gpte)(unsigned long pte) | |
140 | { | |
37406aaa | 141 | #if PTTYPE != PTTYPE_EPT |
0ad805a0 | 142 | return is_present_gpte(pte); |
37406aaa NHE |
143 | #else |
144 | return pte & 7; | |
145 | #endif | |
0ad805a0 NHE |
146 | } |
147 | ||
a78484c6 | 148 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
149 | pt_element_t __user *ptep_user, unsigned index, |
150 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 151 | { |
c8cfbb55 | 152 | int npages; |
b3e4e63f MT |
153 | pt_element_t ret; |
154 | pt_element_t *table; | |
155 | struct page *page; | |
156 | ||
c8cfbb55 TY |
157 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
158 | /* Check if the user is doing something meaningless. */ | |
159 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
160 | return -EFAULT; |
161 | ||
8fd75e12 | 162 | table = kmap_atomic(page); |
b3e4e63f | 163 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 164 | kunmap_atomic(table); |
b3e4e63f MT |
165 | |
166 | kvm_release_page_dirty(page); | |
167 | ||
168 | return (ret != orig_pte); | |
169 | } | |
170 | ||
0ad805a0 NHE |
171 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
172 | struct kvm_mmu_page *sp, u64 *spte, | |
173 | u64 gpte) | |
174 | { | |
175 | if (FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
176 | goto no_present; | |
177 | ||
178 | if (!FNAME(is_present_gpte)(gpte)) | |
179 | goto no_present; | |
180 | ||
61719a8f GN |
181 | /* if accessed bit is not supported prefetch non accessed gpte */ |
182 | if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK)) | |
0ad805a0 NHE |
183 | goto no_present; |
184 | ||
185 | return false; | |
186 | ||
187 | no_present: | |
188 | drop_spte(vcpu->kvm, spte); | |
189 | return true; | |
190 | } | |
191 | ||
192 | static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte) | |
193 | { | |
194 | unsigned access; | |
37406aaa NHE |
195 | #if PTTYPE == PTTYPE_EPT |
196 | access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) | | |
197 | ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) | | |
198 | ACC_USER_MASK; | |
199 | #else | |
0ad805a0 NHE |
200 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; |
201 | access &= ~(gpte >> PT64_NX_SHIFT); | |
37406aaa | 202 | #endif |
0ad805a0 NHE |
203 | |
204 | return access; | |
205 | } | |
206 | ||
8cbc7069 AK |
207 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
208 | struct kvm_mmu *mmu, | |
209 | struct guest_walker *walker, | |
210 | int write_fault) | |
211 | { | |
212 | unsigned level, index; | |
213 | pt_element_t pte, orig_pte; | |
214 | pt_element_t __user *ptep_user; | |
215 | gfn_t table_gfn; | |
216 | int ret; | |
217 | ||
61719a8f GN |
218 | /* dirty/accessed bits are not supported, so no need to update them */ |
219 | if (!PT_GUEST_DIRTY_MASK) | |
220 | return 0; | |
221 | ||
8cbc7069 AK |
222 | for (level = walker->max_level; level >= walker->level; --level) { |
223 | pte = orig_pte = walker->ptes[level - 1]; | |
224 | table_gfn = walker->table_gfn[level - 1]; | |
225 | ptep_user = walker->ptep_user[level - 1]; | |
226 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
d8089bac | 227 | if (!(pte & PT_GUEST_ACCESSED_MASK)) { |
8cbc7069 | 228 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 229 | pte |= PT_GUEST_ACCESSED_MASK; |
8cbc7069 | 230 | } |
0ad805a0 | 231 | if (level == walker->level && write_fault && |
d8089bac | 232 | !(pte & PT_GUEST_DIRTY_MASK)) { |
8cbc7069 | 233 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
d8089bac | 234 | pte |= PT_GUEST_DIRTY_MASK; |
8cbc7069 AK |
235 | } |
236 | if (pte == orig_pte) | |
237 | continue; | |
238 | ||
ba6a3541 PB |
239 | /* |
240 | * If the slot is read-only, simply do not process the accessed | |
241 | * and dirty bits. This is the correct thing to do if the slot | |
242 | * is ROM, and page tables in read-as-ROM/write-as-MMIO slots | |
243 | * are only supported if the accessed and dirty bits are already | |
244 | * set in the ROM (so that MMIO writes are never needed). | |
245 | * | |
246 | * Note that NPT does not allow this at all and faults, since | |
247 | * it always wants nested page table entries for the guest | |
248 | * page tables to be writable. And EPT works but will simply | |
249 | * overwrite the read-only memory to set the accessed and dirty | |
250 | * bits. | |
251 | */ | |
252 | if (unlikely(!walker->pte_writable[level - 1])) | |
253 | continue; | |
254 | ||
8cbc7069 AK |
255 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); |
256 | if (ret) | |
257 | return ret; | |
258 | ||
259 | mark_page_dirty(vcpu->kvm, table_gfn); | |
260 | walker->ptes[level] = pte; | |
261 | } | |
262 | return 0; | |
263 | } | |
264 | ||
ac79c978 AK |
265 | /* |
266 | * Fetch a guest pte for a guest virtual address | |
267 | */ | |
1e301feb JR |
268 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
269 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 270 | gva_t addr, u32 access) |
6aa8b732 | 271 | { |
8cbc7069 | 272 | int ret; |
42bf3f0a | 273 | pt_element_t pte; |
b7233635 | 274 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 275 | gfn_t table_gfn; |
b0cfeb5d | 276 | unsigned index, pt_access, pte_access, accessed_dirty; |
42bf3f0a | 277 | gpa_t pte_gpa; |
134291bf TY |
278 | int offset; |
279 | const int write_fault = access & PFERR_WRITE_MASK; | |
280 | const int user_fault = access & PFERR_USER_MASK; | |
281 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
282 | u16 errcode = 0; | |
13d22b6a AK |
283 | gpa_t real_gpa; |
284 | gfn_t gfn; | |
6aa8b732 | 285 | |
6fbc2770 | 286 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 287 | retry_walk: |
1e301feb JR |
288 | walker->level = mmu->root_level; |
289 | pte = mmu->get_cr3(vcpu); | |
290 | ||
1b0973bd | 291 | #if PTTYPE == 64 |
1e301feb | 292 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 293 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 294 | trace_kvm_mmu_paging_element(pte, walker->level); |
0ad805a0 | 295 | if (!FNAME(is_present_gpte)(pte)) |
f59c1d2d | 296 | goto error; |
1b0973bd AK |
297 | --walker->level; |
298 | } | |
299 | #endif | |
8cbc7069 | 300 | walker->max_level = walker->level; |
a9058ecd | 301 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 302 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 303 | |
d8089bac | 304 | accessed_dirty = PT_GUEST_ACCESSED_MASK; |
13d22b6a AK |
305 | pt_access = pte_access = ACC_ALL; |
306 | ++walker->level; | |
ac79c978 | 307 | |
13d22b6a | 308 | do { |
6e2ca7d1 TY |
309 | gfn_t real_gfn; |
310 | unsigned long host_addr; | |
311 | ||
13d22b6a AK |
312 | pt_access &= pte_access; |
313 | --walker->level; | |
314 | ||
42bf3f0a | 315 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 316 | |
5fb07ddb | 317 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
318 | offset = index * sizeof(pt_element_t); |
319 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 320 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 321 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 322 | |
6e2ca7d1 TY |
323 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
324 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
325 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
326 | goto error; | |
6e2ca7d1 TY |
327 | real_gfn = gpa_to_gfn(real_gfn); |
328 | ||
ba6a3541 PB |
329 | host_addr = gfn_to_hva_prot(vcpu->kvm, real_gfn, |
330 | &walker->pte_writable[walker->level - 1]); | |
134291bf TY |
331 | if (unlikely(kvm_is_error_hva(host_addr))) |
332 | goto error; | |
6e2ca7d1 TY |
333 | |
334 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
335 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
336 | goto error; | |
8cbc7069 | 337 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 338 | |
07420171 | 339 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 340 | |
0ad805a0 | 341 | if (unlikely(!FNAME(is_present_gpte)(pte))) |
134291bf | 342 | goto error; |
7993ba43 | 343 | |
0ad805a0 NHE |
344 | if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, |
345 | walker->level))) { | |
134291bf TY |
346 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
347 | goto error; | |
f59c1d2d | 348 | } |
82725b20 | 349 | |
b514c30f | 350 | accessed_dirty &= pte; |
0ad805a0 | 351 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
73b1087e | 352 | |
7819026e | 353 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 354 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 355 | |
71331a1d | 356 | if (unlikely(permission_fault(mmu, pte_access, access))) { |
134291bf | 357 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 358 | goto error; |
134291bf | 359 | } |
f59c1d2d | 360 | |
13d22b6a AK |
361 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
362 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
363 | ||
364 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
365 | gfn += pse36_gfn_delta(pte); | |
366 | ||
c5421519 | 367 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access); |
13d22b6a AK |
368 | if (real_gpa == UNMAPPED_GVA) |
369 | return 0; | |
370 | ||
371 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
372 | ||
8ea667f2 | 373 | if (!write_fault) |
0ad805a0 | 374 | FNAME(protect_clean_gpte)(&pte_access, pte); |
908e7d79 GN |
375 | else |
376 | /* | |
61719a8f GN |
377 | * On a write fault, fold the dirty bit into accessed_dirty. |
378 | * For modes without A/D bits support accessed_dirty will be | |
379 | * always clear. | |
908e7d79 | 380 | */ |
d8089bac GN |
381 | accessed_dirty &= pte >> |
382 | (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT); | |
b514c30f AK |
383 | |
384 | if (unlikely(!accessed_dirty)) { | |
385 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
386 | if (unlikely(ret < 0)) | |
387 | goto error; | |
388 | else if (ret) | |
389 | goto retry_walk; | |
390 | } | |
42bf3f0a | 391 | |
fe135d2c AK |
392 | walker->pt_access = pt_access; |
393 | walker->pte_access = pte_access; | |
394 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 395 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
396 | return 1; |
397 | ||
f59c1d2d | 398 | error: |
134291bf | 399 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
400 | if (fetch_fault && (mmu->nx || |
401 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 402 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 403 | |
134291bf TY |
404 | walker->fault.vector = PF_VECTOR; |
405 | walker->fault.error_code_valid = true; | |
406 | walker->fault.error_code = errcode; | |
25d92081 YZ |
407 | |
408 | #if PTTYPE == PTTYPE_EPT | |
409 | /* | |
410 | * Use PFERR_RSVD_MASK in error_code to to tell if EPT | |
411 | * misconfiguration requires to be injected. The detection is | |
412 | * done by is_rsvd_bits_set() above. | |
413 | * | |
414 | * We set up the value of exit_qualification to inject: | |
415 | * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation | |
416 | * [5:3] - Calculated by the page walk of the guest EPT page tables | |
417 | * [7:8] - Derived from [7:8] of real exit_qualification | |
418 | * | |
419 | * The other bits are set to 0. | |
420 | */ | |
421 | if (!(errcode & PFERR_RSVD_MASK)) { | |
422 | vcpu->arch.exit_qualification &= 0x187; | |
423 | vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3; | |
424 | } | |
425 | #endif | |
6389ee94 AK |
426 | walker->fault.address = addr; |
427 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 428 | |
8c28d031 | 429 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 430 | return 0; |
6aa8b732 AK |
431 | } |
432 | ||
1e301feb | 433 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 434 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
435 | { |
436 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 437 | access); |
1e301feb JR |
438 | } |
439 | ||
37406aaa | 440 | #if PTTYPE != PTTYPE_EPT |
6539e738 JR |
441 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
442 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 443 | u32 access) |
6539e738 JR |
444 | { |
445 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 446 | addr, access); |
6539e738 | 447 | } |
37406aaa | 448 | #endif |
6539e738 | 449 | |
bd6360cc XG |
450 | static bool |
451 | FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
452 | u64 *spte, pt_element_t gpte, bool no_dirty_log) | |
0028425f | 453 | { |
41074d07 | 454 | unsigned pte_access; |
bd6360cc | 455 | gfn_t gfn; |
35149e21 | 456 | pfn_t pfn; |
0028425f | 457 | |
0ad805a0 | 458 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
bd6360cc | 459 | return false; |
407c61c6 | 460 | |
b8688d51 | 461 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
bd6360cc XG |
462 | |
463 | gfn = gpte_to_gfn(gpte); | |
0ad805a0 NHE |
464 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
465 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
bd6360cc XG |
466 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
467 | no_dirty_log && (pte_access & ACC_WRITE_MASK)); | |
81c52c56 | 468 | if (is_error_pfn(pfn)) |
bd6360cc | 469 | return false; |
0f53b5b1 | 470 | |
1403283a | 471 | /* |
bd6360cc XG |
472 | * we call mmu_set_spte() with host_writable = true because |
473 | * pte_prefetch_gfn_to_pfn always gets a writable pfn. | |
1403283a | 474 | */ |
f7616203 XG |
475 | mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL, |
476 | gfn, pfn, true, true); | |
bd6360cc XG |
477 | |
478 | return true; | |
479 | } | |
480 | ||
481 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, | |
482 | u64 *spte, const void *pte) | |
483 | { | |
484 | pt_element_t gpte = *(const pt_element_t *)pte; | |
485 | ||
486 | FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false); | |
0028425f AK |
487 | } |
488 | ||
39c8c672 AK |
489 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
490 | struct guest_walker *gw, int level) | |
491 | { | |
39c8c672 | 492 | pt_element_t curr_pte; |
189be38d XG |
493 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
494 | u64 mask; | |
495 | int r, index; | |
496 | ||
497 | if (level == PT_PAGE_TABLE_LEVEL) { | |
498 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
499 | base_gpa = pte_gpa & ~mask; | |
500 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
501 | ||
502 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
503 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
504 | curr_pte = gw->prefetch_ptes[index]; | |
505 | } else | |
506 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 507 | &curr_pte, sizeof(curr_pte)); |
189be38d | 508 | |
39c8c672 AK |
509 | return r || curr_pte != gw->ptes[level - 1]; |
510 | } | |
511 | ||
189be38d XG |
512 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
513 | u64 *sptep) | |
957ed9ef XG |
514 | { |
515 | struct kvm_mmu_page *sp; | |
189be38d | 516 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 517 | u64 *spte; |
189be38d | 518 | int i; |
957ed9ef XG |
519 | |
520 | sp = page_header(__pa(sptep)); | |
521 | ||
522 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
523 | return; | |
524 | ||
525 | if (sp->role.direct) | |
526 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
527 | ||
528 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
529 | spte = sp->spt + i; |
530 | ||
531 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
957ed9ef XG |
532 | if (spte == sptep) |
533 | continue; | |
534 | ||
c3707958 | 535 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
536 | continue; |
537 | ||
bd6360cc | 538 | if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true)) |
957ed9ef | 539 | break; |
957ed9ef XG |
540 | } |
541 | } | |
542 | ||
6aa8b732 AK |
543 | /* |
544 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
d4878f24 XG |
545 | * If the guest tries to write a write-protected page, we need to |
546 | * emulate this operation, return 1 to indicate this case. | |
6aa8b732 | 547 | */ |
d4878f24 | 548 | static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
e7a04c99 | 549 | struct guest_walker *gw, |
c2288505 | 550 | int write_fault, int hlevel, |
d4878f24 | 551 | pfn_t pfn, bool map_writable, bool prefault) |
6aa8b732 | 552 | { |
5991b332 | 553 | struct kvm_mmu_page *sp = NULL; |
24157aaf | 554 | struct kvm_shadow_walk_iterator it; |
d4878f24 XG |
555 | unsigned direct_access, access = gw->pt_access; |
556 | int top_level, emulate = 0; | |
abb9e0b8 | 557 | |
b36c7a7c | 558 | direct_access = gw->pte_access; |
84754cd8 | 559 | |
5991b332 AK |
560 | top_level = vcpu->arch.mmu.root_level; |
561 | if (top_level == PT32E_ROOT_LEVEL) | |
562 | top_level = PT32_ROOT_LEVEL; | |
563 | /* | |
564 | * Verify that the top-level gpte is still there. Since the page | |
565 | * is a root page, it is either write protected (and cannot be | |
566 | * changed from now on) or it is invalid (in which case, we don't | |
567 | * really care if it changes underneath us after this point). | |
568 | */ | |
569 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
570 | goto out_gpte_changed; | |
571 | ||
24157aaf AK |
572 | for (shadow_walk_init(&it, vcpu, addr); |
573 | shadow_walk_okay(&it) && it.level > gw->level; | |
574 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
575 | gfn_t table_gfn; |
576 | ||
a30f47cb | 577 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 578 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 579 | |
5991b332 | 580 | sp = NULL; |
24157aaf AK |
581 | if (!is_shadow_present_pte(*it.sptep)) { |
582 | table_gfn = gw->table_gfn[it.level - 2]; | |
583 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
584 | false, access, it.sptep); | |
5991b332 | 585 | } |
0b3c9333 AK |
586 | |
587 | /* | |
588 | * Verify that the gpte in the page we've just write | |
589 | * protected is still there. | |
590 | */ | |
24157aaf | 591 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 592 | goto out_gpte_changed; |
abb9e0b8 | 593 | |
5991b332 | 594 | if (sp) |
7a1638ce | 595 | link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK); |
e7a04c99 | 596 | } |
050e6499 | 597 | |
0b3c9333 | 598 | for (; |
24157aaf AK |
599 | shadow_walk_okay(&it) && it.level > hlevel; |
600 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
601 | gfn_t direct_gfn; |
602 | ||
a30f47cb | 603 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 604 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 605 | |
24157aaf | 606 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 607 | |
24157aaf | 608 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
609 | continue; |
610 | ||
24157aaf | 611 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 612 | |
24157aaf AK |
613 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
614 | true, direct_access, it.sptep); | |
7a1638ce | 615 | link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK); |
0b3c9333 AK |
616 | } |
617 | ||
a30f47cb | 618 | clear_sp_write_flooding_count(it.sptep); |
f7616203 XG |
619 | mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate, |
620 | it.level, gw->gfn, pfn, prefault, map_writable); | |
189be38d | 621 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 622 | |
d4878f24 | 623 | return emulate; |
0b3c9333 AK |
624 | |
625 | out_gpte_changed: | |
5991b332 | 626 | if (sp) |
24157aaf | 627 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 | 628 | kvm_release_pfn_clean(pfn); |
d4878f24 | 629 | return 0; |
6aa8b732 AK |
630 | } |
631 | ||
7751babd XG |
632 | /* |
633 | * To see whether the mapped gfn can write its page table in the current | |
634 | * mapping. | |
635 | * | |
636 | * It is the helper function of FNAME(page_fault). When guest uses large page | |
637 | * size to map the writable gfn which is used as current page table, we should | |
638 | * force kvm to use small page size to map it because new shadow page will be | |
639 | * created when kvm establishes shadow page table that stop kvm using large | |
640 | * page size. Do it early can avoid unnecessary #PF and emulation. | |
641 | * | |
93c05d3e XG |
642 | * @write_fault_to_shadow_pgtable will return true if the fault gfn is |
643 | * currently used as its page table. | |
644 | * | |
7751babd XG |
645 | * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok |
646 | * since the PDPT is always shadowed, that means, we can not use large page | |
647 | * size to map the gfn which is used as PDPT. | |
648 | */ | |
649 | static bool | |
650 | FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu, | |
93c05d3e XG |
651 | struct guest_walker *walker, int user_fault, |
652 | bool *write_fault_to_shadow_pgtable) | |
7751babd XG |
653 | { |
654 | int level; | |
655 | gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); | |
93c05d3e | 656 | bool self_changed = false; |
7751babd XG |
657 | |
658 | if (!(walker->pte_access & ACC_WRITE_MASK || | |
659 | (!is_write_protection(vcpu) && !user_fault))) | |
660 | return false; | |
661 | ||
93c05d3e XG |
662 | for (level = walker->level; level <= walker->max_level; level++) { |
663 | gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1]; | |
664 | ||
665 | self_changed |= !(gfn & mask); | |
666 | *write_fault_to_shadow_pgtable |= !gfn; | |
667 | } | |
7751babd | 668 | |
93c05d3e | 669 | return self_changed; |
7751babd XG |
670 | } |
671 | ||
6aa8b732 AK |
672 | /* |
673 | * Page fault handler. There are several causes for a page fault: | |
674 | * - there is no shadow pte for the guest pte | |
675 | * - write access through a shadow pte marked read only so that we can set | |
676 | * the dirty bit | |
677 | * - write access to a shadow pte marked read only so we can update the page | |
678 | * dirty bitmap, when userspace requests it | |
679 | * - mmio access; in this case we will never install a present shadow pte | |
680 | * - normal guest page fault due to the guest pte marked not present, not | |
681 | * writable, or not executable | |
682 | * | |
e2dec939 AK |
683 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
684 | * a negative value on error. | |
6aa8b732 | 685 | */ |
56028d08 | 686 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 687 | bool prefault) |
6aa8b732 AK |
688 | { |
689 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
690 | int user_fault = error_code & PFERR_USER_MASK; |
691 | struct guest_walker walker; | |
e2dec939 | 692 | int r; |
35149e21 | 693 | pfn_t pfn; |
7e4e4056 | 694 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 695 | int force_pt_level; |
e930bffe | 696 | unsigned long mmu_seq; |
93c05d3e | 697 | bool map_writable, is_self_change_mapping; |
6aa8b732 | 698 | |
b8688d51 | 699 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 700 | |
f8f55942 XG |
701 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
702 | r = handle_mmio_page_fault(vcpu, addr, error_code, | |
ce88decf | 703 | mmu_is_nested(vcpu)); |
f8f55942 XG |
704 | if (likely(r != RET_MMIO_PF_INVALID)) |
705 | return r; | |
706 | }; | |
ce88decf | 707 | |
e2dec939 AK |
708 | r = mmu_topup_memory_caches(vcpu); |
709 | if (r) | |
710 | return r; | |
714b93da | 711 | |
6aa8b732 | 712 | /* |
a8b876b1 | 713 | * Look up the guest pte for the faulting address. |
6aa8b732 | 714 | */ |
33770780 | 715 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
716 | |
717 | /* | |
718 | * The page is not mapped by the guest. Let the guest handle it. | |
719 | */ | |
7993ba43 | 720 | if (!r) { |
b8688d51 | 721 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 722 | if (!prefault) |
fb67e14f | 723 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 724 | |
6aa8b732 AK |
725 | return 0; |
726 | } | |
727 | ||
93c05d3e XG |
728 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
729 | ||
730 | is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu, | |
731 | &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable); | |
732 | ||
936a5fe6 | 733 | if (walker.level >= PT_DIRECTORY_LEVEL) |
7751babd | 734 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn) |
93c05d3e | 735 | || is_self_change_mapping; |
936a5fe6 AA |
736 | else |
737 | force_pt_level = 1; | |
738 | if (!force_pt_level) { | |
7e4e4056 JR |
739 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
740 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 741 | } |
7e4e4056 | 742 | |
e930bffe | 743 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 744 | smp_rmb(); |
af585b92 | 745 | |
78b2c54a | 746 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 747 | &map_writable)) |
af585b92 | 748 | return 0; |
d7824fff | 749 | |
d7c55201 XG |
750 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
751 | walker.gfn, pfn, walker.pte_access, &r)) | |
752 | return r; | |
753 | ||
c2288505 XG |
754 | /* |
755 | * Do not change pte_access if the pfn is a mmio page, otherwise | |
756 | * we will cache the incorrect access into mmio spte. | |
757 | */ | |
758 | if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) && | |
759 | !is_write_protection(vcpu) && !user_fault && | |
760 | !is_noslot_pfn(pfn)) { | |
761 | walker.pte_access |= ACC_WRITE_MASK; | |
762 | walker.pte_access &= ~ACC_USER_MASK; | |
763 | ||
764 | /* | |
765 | * If we converted a user page to a kernel page, | |
766 | * so that the kernel can write to it when cr0.wp=0, | |
767 | * then we should prevent the kernel from executing it | |
768 | * if SMEP is enabled. | |
769 | */ | |
770 | if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
771 | walker.pte_access &= ~ACC_EXEC_MASK; | |
772 | } | |
773 | ||
aaee2c94 | 774 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 775 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 776 | goto out_unlock; |
bc32ce21 | 777 | |
0375f7fa | 778 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
450e0b41 | 779 | make_mmu_pages_available(vcpu); |
936a5fe6 AA |
780 | if (!force_pt_level) |
781 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
c2288505 | 782 | r = FNAME(fetch)(vcpu, addr, &walker, write_fault, |
d4878f24 | 783 | level, pfn, map_writable, prefault); |
1165f5fe | 784 | ++vcpu->stat.pf_fixed; |
0375f7fa | 785 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 786 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 787 | |
d4878f24 | 788 | return r; |
e930bffe AA |
789 | |
790 | out_unlock: | |
791 | spin_unlock(&vcpu->kvm->mmu_lock); | |
792 | kvm_release_pfn_clean(pfn); | |
793 | return 0; | |
6aa8b732 AK |
794 | } |
795 | ||
505aef8f XG |
796 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
797 | { | |
798 | int offset = 0; | |
799 | ||
f71fa31f | 800 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
801 | |
802 | if (PTTYPE == 32) | |
803 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
804 | ||
805 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
806 | } | |
807 | ||
a461930b | 808 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 809 | { |
a461930b | 810 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 811 | struct kvm_mmu_page *sp; |
a461930b AK |
812 | int level; |
813 | u64 *sptep; | |
814 | ||
bebb106a XG |
815 | vcpu_clear_mmio_info(vcpu, gva); |
816 | ||
f57f2ef5 XG |
817 | /* |
818 | * No need to check return value here, rmap_can_add() can | |
819 | * help us to skip pte prefetch later. | |
820 | */ | |
821 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 822 | |
f57f2ef5 | 823 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
824 | for_each_shadow_entry(vcpu, gva, iterator) { |
825 | level = iterator.level; | |
826 | sptep = iterator.sptep; | |
ad218f85 | 827 | |
f78978aa | 828 | sp = page_header(__pa(sptep)); |
884a0ff0 | 829 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
830 | pt_element_t gpte; |
831 | gpa_t pte_gpa; | |
832 | ||
f78978aa XG |
833 | if (!sp->unsync) |
834 | break; | |
835 | ||
505aef8f | 836 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 837 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 838 | |
505aef8f XG |
839 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
840 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
841 | |
842 | if (!rmap_can_add(vcpu)) | |
843 | break; | |
844 | ||
845 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
846 | sizeof(pt_element_t))) | |
847 | break; | |
848 | ||
849 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 850 | } |
a7052897 | 851 | |
f78978aa | 852 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
853 | break; |
854 | } | |
ad218f85 | 855 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
856 | } |
857 | ||
1871c602 | 858 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 859 | struct x86_exception *exception) |
6aa8b732 AK |
860 | { |
861 | struct guest_walker walker; | |
e119d117 AK |
862 | gpa_t gpa = UNMAPPED_GVA; |
863 | int r; | |
6aa8b732 | 864 | |
33770780 | 865 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 866 | |
e119d117 | 867 | if (r) { |
1755fbcc | 868 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 869 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
870 | } else if (exception) |
871 | *exception = walker.fault; | |
6aa8b732 AK |
872 | |
873 | return gpa; | |
874 | } | |
875 | ||
37406aaa | 876 | #if PTTYPE != PTTYPE_EPT |
6539e738 | 877 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
878 | u32 access, |
879 | struct x86_exception *exception) | |
6539e738 JR |
880 | { |
881 | struct guest_walker walker; | |
882 | gpa_t gpa = UNMAPPED_GVA; | |
883 | int r; | |
884 | ||
33770780 | 885 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
886 | |
887 | if (r) { | |
888 | gpa = gfn_to_gpa(walker.gfn); | |
889 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
890 | } else if (exception) |
891 | *exception = walker.fault; | |
6539e738 JR |
892 | |
893 | return gpa; | |
894 | } | |
37406aaa | 895 | #endif |
6539e738 | 896 | |
e8bc217a MT |
897 | /* |
898 | * Using the cached information from sp->gfns is safe because: | |
899 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
900 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
901 | * |
902 | * Note: | |
903 | * We should flush all tlbs if spte is dropped even though guest is | |
904 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
905 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
906 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
907 | * freed pages. | |
908 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 909 | */ |
a4a8e6f7 | 910 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 911 | { |
505aef8f | 912 | int i, nr_present = 0; |
9bdbba13 | 913 | bool host_writable; |
51fb60d8 | 914 | gpa_t first_pte_gpa; |
e8bc217a | 915 | |
2032a93d LJ |
916 | /* direct kvm_mmu_page can not be unsync. */ |
917 | BUG_ON(sp->role.direct); | |
918 | ||
505aef8f | 919 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 920 | |
e8bc217a MT |
921 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
922 | unsigned pte_access; | |
923 | pt_element_t gpte; | |
924 | gpa_t pte_gpa; | |
f55c3f41 | 925 | gfn_t gfn; |
e8bc217a | 926 | |
ce88decf | 927 | if (!sp->spt[i]) |
e8bc217a MT |
928 | continue; |
929 | ||
51fb60d8 | 930 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
931 | |
932 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
933 | sizeof(pt_element_t))) | |
934 | return -EINVAL; | |
935 | ||
0ad805a0 | 936 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 937 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
938 | continue; |
939 | } | |
940 | ||
ce88decf XG |
941 | gfn = gpte_to_gfn(gpte); |
942 | pte_access = sp->role.access; | |
0ad805a0 NHE |
943 | pte_access &= FNAME(gpte_access)(vcpu, gpte); |
944 | FNAME(protect_clean_gpte)(&pte_access, gpte); | |
ce88decf | 945 | |
f2fd125d XG |
946 | if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access, |
947 | &nr_present)) | |
ce88decf XG |
948 | continue; |
949 | ||
407c61c6 | 950 | if (gfn != sp->gfns[i]) { |
c3707958 | 951 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 952 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
953 | continue; |
954 | } | |
955 | ||
956 | nr_present++; | |
ce88decf | 957 | |
f8e453b0 XG |
958 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
959 | ||
c2288505 | 960 | set_spte(vcpu, &sp->spt[i], pte_access, |
640d9b0d | 961 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 962 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 963 | host_writable); |
e8bc217a MT |
964 | } |
965 | ||
966 | return !nr_present; | |
967 | } | |
968 | ||
6aa8b732 AK |
969 | #undef pt_element_t |
970 | #undef guest_walker | |
971 | #undef FNAME | |
972 | #undef PT_BASE_ADDR_MASK | |
973 | #undef PT_INDEX | |
e04da980 JR |
974 | #undef PT_LVL_ADDR_MASK |
975 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 976 | #undef PT_LEVEL_BITS |
cea0f0e7 | 977 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 978 | #undef gpte_to_gfn |
e04da980 | 979 | #undef gpte_to_gfn_lvl |
b3e4e63f | 980 | #undef CMPXCHG |
d8089bac GN |
981 | #undef PT_GUEST_ACCESSED_MASK |
982 | #undef PT_GUEST_DIRTY_MASK | |
983 | #undef PT_GUEST_DIRTY_SHIFT | |
984 | #undef PT_GUEST_ACCESSED_SHIFT |