Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
cea0f0e7 | 66 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 67 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 68 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 69 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
70 | unsigned pt_access; |
71 | unsigned pte_access; | |
815af8d4 | 72 | gfn_t gfn; |
8c28d031 | 73 | struct x86_exception fault; |
6aa8b732 AK |
74 | }; |
75 | ||
e04da980 | 76 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 77 | { |
e04da980 | 78 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
79 | } |
80 | ||
a78484c6 | 81 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
82 | pt_element_t __user *ptep_user, unsigned index, |
83 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 84 | { |
c8cfbb55 | 85 | int npages; |
b3e4e63f MT |
86 | pt_element_t ret; |
87 | pt_element_t *table; | |
88 | struct page *page; | |
89 | ||
c8cfbb55 TY |
90 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
91 | /* Check if the user is doing something meaningless. */ | |
92 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
93 | return -EFAULT; |
94 | ||
b3e4e63f | 95 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 96 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
97 | kunmap_atomic(table, KM_USER0); |
98 | ||
99 | kvm_release_page_dirty(page); | |
100 | ||
101 | return (ret != orig_pte); | |
102 | } | |
103 | ||
bedbe4ee AK |
104 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
105 | { | |
106 | unsigned access; | |
107 | ||
108 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
109 | #if PTTYPE == 64 | |
2d48a985 | 110 | if (vcpu->arch.mmu.nx) |
bedbe4ee AK |
111 | access &= ~(gpte >> PT64_NX_SHIFT); |
112 | #endif | |
113 | return access; | |
114 | } | |
115 | ||
3c8c652a TY |
116 | static bool FNAME(is_last_gpte)(struct guest_walker *walker, |
117 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
118 | pt_element_t gpte) | |
119 | { | |
120 | if (walker->level == PT_PAGE_TABLE_LEVEL) | |
121 | return true; | |
122 | ||
123 | if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) && | |
124 | (PTTYPE == 64 || is_pse(vcpu))) | |
125 | return true; | |
126 | ||
127 | if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) && | |
128 | (mmu->root_level == PT64_ROOT_LEVEL)) | |
129 | return true; | |
130 | ||
131 | return false; | |
132 | } | |
133 | ||
ac79c978 AK |
134 | /* |
135 | * Fetch a guest pte for a guest virtual address | |
136 | */ | |
1e301feb JR |
137 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
138 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 139 | gva_t addr, u32 access) |
6aa8b732 | 140 | { |
42bf3f0a | 141 | pt_element_t pte; |
b7233635 | 142 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 143 | gfn_t table_gfn; |
f59c1d2d | 144 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 145 | gpa_t pte_gpa; |
134291bf TY |
146 | bool eperm; |
147 | int offset; | |
148 | const int write_fault = access & PFERR_WRITE_MASK; | |
149 | const int user_fault = access & PFERR_USER_MASK; | |
150 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
151 | u16 errcode = 0; | |
6aa8b732 | 152 | |
07420171 AK |
153 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
154 | fetch_fault); | |
92c1c1e8 | 155 | retry_walk: |
134291bf | 156 | eperm = false; |
1e301feb JR |
157 | walker->level = mmu->root_level; |
158 | pte = mmu->get_cr3(vcpu); | |
159 | ||
1b0973bd | 160 | #if PTTYPE == 64 |
1e301feb | 161 | if (walker->level == PT32E_ROOT_LEVEL) { |
d41d1895 | 162 | pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3); |
07420171 | 163 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 164 | if (!is_present_gpte(pte)) |
f59c1d2d | 165 | goto error; |
1b0973bd AK |
166 | --walker->level; |
167 | } | |
168 | #endif | |
a9058ecd | 169 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 170 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 171 | |
fe135d2c | 172 | pt_access = ACC_ALL; |
ac79c978 AK |
173 | |
174 | for (;;) { | |
6e2ca7d1 TY |
175 | gfn_t real_gfn; |
176 | unsigned long host_addr; | |
177 | ||
42bf3f0a | 178 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 179 | |
5fb07ddb | 180 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
181 | offset = index * sizeof(pt_element_t); |
182 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 183 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 184 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 185 | |
6e2ca7d1 TY |
186 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
187 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
188 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
189 | goto error; | |
6e2ca7d1 TY |
190 | real_gfn = gpa_to_gfn(real_gfn); |
191 | ||
192 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
193 | if (unlikely(kvm_is_error_hva(host_addr))) |
194 | goto error; | |
6e2ca7d1 TY |
195 | |
196 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
197 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
198 | goto error; | |
a6085fba | 199 | |
07420171 | 200 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 201 | |
134291bf TY |
202 | if (unlikely(!is_present_gpte(pte))) |
203 | goto error; | |
7993ba43 | 204 | |
781e0743 AK |
205 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
206 | walker->level))) { | |
134291bf TY |
207 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
208 | goto error; | |
f59c1d2d | 209 | } |
82725b20 | 210 | |
bebb106a XG |
211 | if (!check_write_user_access(vcpu, write_fault, user_fault, |
212 | pte)) | |
f59c1d2d | 213 | eperm = true; |
7993ba43 | 214 | |
73b1087e | 215 | #if PTTYPE == 64 |
781e0743 | 216 | if (unlikely(fetch_fault && (pte & PT64_NX_MASK))) |
f59c1d2d | 217 | eperm = true; |
73b1087e AK |
218 | #endif |
219 | ||
134291bf | 220 | if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) { |
a78484c6 | 221 | int ret; |
07420171 AK |
222 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
223 | sizeof(pte)); | |
c8cfbb55 TY |
224 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
225 | pte, pte|PT_ACCESSED_MASK); | |
134291bf TY |
226 | if (unlikely(ret < 0)) |
227 | goto error; | |
228 | else if (ret) | |
92c1c1e8 | 229 | goto retry_walk; |
a78484c6 | 230 | |
f3b8c964 | 231 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 232 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 233 | } |
815af8d4 | 234 | |
bedbe4ee | 235 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 236 | |
7819026e MT |
237 | walker->ptes[walker->level - 1] = pte; |
238 | ||
3c8c652a | 239 | if (FNAME(is_last_gpte)(walker, vcpu, mmu, pte)) { |
e04da980 | 240 | int lvl = walker->level; |
2329d46d JR |
241 | gpa_t real_gpa; |
242 | gfn_t gfn; | |
33770780 | 243 | u32 ac; |
e04da980 | 244 | |
e57d4a35 YW |
245 | /* check if the kernel is fetching from user page */ |
246 | if (unlikely(pte_access & PT_USER_MASK) && | |
247 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)) | |
248 | if (fetch_fault && !user_fault) | |
249 | eperm = true; | |
250 | ||
2329d46d JR |
251 | gfn = gpte_to_gfn_lvl(pte, lvl); |
252 | gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT; | |
e04da980 JR |
253 | |
254 | if (PTTYPE == 32 && | |
255 | walker->level == PT_DIRECTORY_LEVEL && | |
256 | is_cpuid_PSE36()) | |
2329d46d JR |
257 | gfn += pse36_gfn_delta(pte); |
258 | ||
33770780 | 259 | ac = write_fault | fetch_fault | user_fault; |
2329d46d JR |
260 | |
261 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), | |
33770780 | 262 | ac); |
2329d46d JR |
263 | if (real_gpa == UNMAPPED_GVA) |
264 | return 0; | |
265 | ||
266 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
e04da980 | 267 | |
ac79c978 | 268 | break; |
815af8d4 | 269 | } |
ac79c978 | 270 | |
fe135d2c | 271 | pt_access = pte_access; |
ac79c978 AK |
272 | --walker->level; |
273 | } | |
42bf3f0a | 274 | |
134291bf TY |
275 | if (unlikely(eperm)) { |
276 | errcode |= PFERR_PRESENT_MASK; | |
f59c1d2d | 277 | goto error; |
134291bf | 278 | } |
f59c1d2d | 279 | |
781e0743 | 280 | if (write_fault && unlikely(!is_dirty_gpte(pte))) { |
a78484c6 | 281 | int ret; |
b3e4e63f | 282 | |
07420171 | 283 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
c8cfbb55 TY |
284 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, |
285 | pte, pte|PT_DIRTY_MASK); | |
134291bf | 286 | if (unlikely(ret < 0)) |
a78484c6 | 287 | goto error; |
134291bf | 288 | else if (ret) |
92c1c1e8 | 289 | goto retry_walk; |
a78484c6 | 290 | |
f3b8c964 | 291 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 292 | pte |= PT_DIRTY_MASK; |
7819026e | 293 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
294 | } |
295 | ||
fe135d2c AK |
296 | walker->pt_access = pt_access; |
297 | walker->pte_access = pte_access; | |
298 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 299 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
300 | return 1; |
301 | ||
f59c1d2d | 302 | error: |
134291bf | 303 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
304 | if (fetch_fault && (mmu->nx || |
305 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 306 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 307 | |
134291bf TY |
308 | walker->fault.vector = PF_VECTOR; |
309 | walker->fault.error_code_valid = true; | |
310 | walker->fault.error_code = errcode; | |
6389ee94 AK |
311 | walker->fault.address = addr; |
312 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 313 | |
8c28d031 | 314 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 315 | return 0; |
6aa8b732 AK |
316 | } |
317 | ||
1e301feb | 318 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 319 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
320 | { |
321 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 322 | access); |
1e301feb JR |
323 | } |
324 | ||
6539e738 JR |
325 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
326 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 327 | u32 access) |
6539e738 JR |
328 | { |
329 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 330 | addr, access); |
6539e738 JR |
331 | } |
332 | ||
407c61c6 XG |
333 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
334 | struct kvm_mmu_page *sp, u64 *spte, | |
335 | pt_element_t gpte) | |
336 | { | |
337 | u64 nonpresent = shadow_trap_nonpresent_pte; | |
338 | ||
339 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) | |
340 | goto no_present; | |
341 | ||
342 | if (!is_present_gpte(gpte)) { | |
343 | if (!sp->unsync) | |
344 | nonpresent = shadow_notrap_nonpresent_pte; | |
345 | goto no_present; | |
346 | } | |
347 | ||
348 | if (!(gpte & PT_ACCESSED_MASK)) | |
349 | goto no_present; | |
350 | ||
351 | return false; | |
352 | ||
353 | no_present: | |
354 | drop_spte(vcpu->kvm, spte, nonpresent); | |
355 | return true; | |
356 | } | |
357 | ||
ac3cd03c | 358 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 359 | u64 *spte, const void *pte) |
0028425f AK |
360 | { |
361 | pt_element_t gpte; | |
41074d07 | 362 | unsigned pte_access; |
35149e21 | 363 | pfn_t pfn; |
0028425f | 364 | |
0028425f | 365 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 366 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 367 | return; |
407c61c6 | 368 | |
b8688d51 | 369 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 370 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
0f53b5b1 XG |
371 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
372 | if (is_error_pfn(pfn)) { | |
373 | kvm_release_pfn_clean(pfn); | |
d7824fff | 374 | return; |
0f53b5b1 | 375 | } |
0f53b5b1 | 376 | |
1403283a | 377 | /* |
0d2eb44f | 378 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
379 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
380 | */ | |
ac3cd03c | 381 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 382 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 383 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
384 | } |
385 | ||
39c8c672 AK |
386 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
387 | struct guest_walker *gw, int level) | |
388 | { | |
39c8c672 | 389 | pt_element_t curr_pte; |
189be38d XG |
390 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
391 | u64 mask; | |
392 | int r, index; | |
393 | ||
394 | if (level == PT_PAGE_TABLE_LEVEL) { | |
395 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
396 | base_gpa = pte_gpa & ~mask; | |
397 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
398 | ||
399 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
400 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
401 | curr_pte = gw->prefetch_ptes[index]; | |
402 | } else | |
403 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 404 | &curr_pte, sizeof(curr_pte)); |
189be38d | 405 | |
39c8c672 AK |
406 | return r || curr_pte != gw->ptes[level - 1]; |
407 | } | |
408 | ||
189be38d XG |
409 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
410 | u64 *sptep) | |
957ed9ef XG |
411 | { |
412 | struct kvm_mmu_page *sp; | |
189be38d | 413 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 414 | u64 *spte; |
189be38d | 415 | int i; |
957ed9ef XG |
416 | |
417 | sp = page_header(__pa(sptep)); | |
418 | ||
419 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
420 | return; | |
421 | ||
422 | if (sp->role.direct) | |
423 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
424 | ||
425 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
426 | spte = sp->spt + i; |
427 | ||
428 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
429 | pt_element_t gpte; | |
430 | unsigned pte_access; | |
431 | gfn_t gfn; | |
432 | pfn_t pfn; | |
433 | bool dirty; | |
434 | ||
435 | if (spte == sptep) | |
436 | continue; | |
437 | ||
438 | if (*spte != shadow_trap_nonpresent_pte) | |
439 | continue; | |
440 | ||
441 | gpte = gptep[i]; | |
442 | ||
407c61c6 | 443 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
444 | continue; |
445 | ||
446 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
447 | gfn = gpte_to_gfn(gpte); | |
448 | dirty = is_dirty_gpte(gpte); | |
449 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
450 | (pte_access & ACC_WRITE_MASK) && dirty); | |
451 | if (is_error_pfn(pfn)) { | |
452 | kvm_release_pfn_clean(pfn); | |
453 | break; | |
454 | } | |
455 | ||
456 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
457 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
458 | pfn, true, true); | |
459 | } | |
460 | } | |
461 | ||
6aa8b732 AK |
462 | /* |
463 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
464 | */ | |
e7a04c99 AK |
465 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
466 | struct guest_walker *gw, | |
7e4e4056 | 467 | int user_fault, int write_fault, int hlevel, |
fb67e14f XG |
468 | int *ptwrite, pfn_t pfn, bool map_writable, |
469 | bool prefault) | |
6aa8b732 | 470 | { |
abb9e0b8 | 471 | unsigned access = gw->pt_access; |
5991b332 | 472 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 473 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 474 | int top_level; |
84754cd8 | 475 | unsigned direct_access; |
24157aaf | 476 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 477 | |
43a3795a | 478 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 479 | return NULL; |
6aa8b732 | 480 | |
84754cd8 XG |
481 | direct_access = gw->pt_access & gw->pte_access; |
482 | if (!dirty) | |
483 | direct_access &= ~ACC_WRITE_MASK; | |
484 | ||
5991b332 AK |
485 | top_level = vcpu->arch.mmu.root_level; |
486 | if (top_level == PT32E_ROOT_LEVEL) | |
487 | top_level = PT32_ROOT_LEVEL; | |
488 | /* | |
489 | * Verify that the top-level gpte is still there. Since the page | |
490 | * is a root page, it is either write protected (and cannot be | |
491 | * changed from now on) or it is invalid (in which case, we don't | |
492 | * really care if it changes underneath us after this point). | |
493 | */ | |
494 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
495 | goto out_gpte_changed; | |
496 | ||
24157aaf AK |
497 | for (shadow_walk_init(&it, vcpu, addr); |
498 | shadow_walk_okay(&it) && it.level > gw->level; | |
499 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
500 | gfn_t table_gfn; |
501 | ||
24157aaf | 502 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 503 | |
5991b332 | 504 | sp = NULL; |
24157aaf AK |
505 | if (!is_shadow_present_pte(*it.sptep)) { |
506 | table_gfn = gw->table_gfn[it.level - 2]; | |
507 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
508 | false, access, it.sptep); | |
5991b332 | 509 | } |
0b3c9333 AK |
510 | |
511 | /* | |
512 | * Verify that the gpte in the page we've just write | |
513 | * protected is still there. | |
514 | */ | |
24157aaf | 515 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 516 | goto out_gpte_changed; |
abb9e0b8 | 517 | |
5991b332 | 518 | if (sp) |
24157aaf | 519 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 520 | } |
050e6499 | 521 | |
0b3c9333 | 522 | for (; |
24157aaf AK |
523 | shadow_walk_okay(&it) && it.level > hlevel; |
524 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
525 | gfn_t direct_gfn; |
526 | ||
24157aaf | 527 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 528 | |
24157aaf | 529 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 530 | |
24157aaf | 531 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
532 | continue; |
533 | ||
24157aaf | 534 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 535 | |
24157aaf AK |
536 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
537 | true, direct_access, it.sptep); | |
538 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
539 | } |
540 | ||
24157aaf AK |
541 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
542 | user_fault, write_fault, dirty, ptwrite, it.level, | |
fb67e14f | 543 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 544 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 545 | |
24157aaf | 546 | return it.sptep; |
0b3c9333 AK |
547 | |
548 | out_gpte_changed: | |
5991b332 | 549 | if (sp) |
24157aaf | 550 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
551 | kvm_release_pfn_clean(pfn); |
552 | return NULL; | |
6aa8b732 AK |
553 | } |
554 | ||
6aa8b732 AK |
555 | /* |
556 | * Page fault handler. There are several causes for a page fault: | |
557 | * - there is no shadow pte for the guest pte | |
558 | * - write access through a shadow pte marked read only so that we can set | |
559 | * the dirty bit | |
560 | * - write access to a shadow pte marked read only so we can update the page | |
561 | * dirty bitmap, when userspace requests it | |
562 | * - mmio access; in this case we will never install a present shadow pte | |
563 | * - normal guest page fault due to the guest pte marked not present, not | |
564 | * writable, or not executable | |
565 | * | |
e2dec939 AK |
566 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
567 | * a negative value on error. | |
6aa8b732 | 568 | */ |
56028d08 | 569 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 570 | bool prefault) |
6aa8b732 AK |
571 | { |
572 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
573 | int user_fault = error_code & PFERR_USER_MASK; |
574 | struct guest_walker walker; | |
d555c333 | 575 | u64 *sptep; |
cea0f0e7 | 576 | int write_pt = 0; |
e2dec939 | 577 | int r; |
35149e21 | 578 | pfn_t pfn; |
7e4e4056 | 579 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 580 | int force_pt_level; |
e930bffe | 581 | unsigned long mmu_seq; |
612819c3 | 582 | bool map_writable; |
6aa8b732 | 583 | |
b8688d51 | 584 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 585 | |
e2dec939 AK |
586 | r = mmu_topup_memory_caches(vcpu); |
587 | if (r) | |
588 | return r; | |
714b93da | 589 | |
6aa8b732 | 590 | /* |
a8b876b1 | 591 | * Look up the guest pte for the faulting address. |
6aa8b732 | 592 | */ |
33770780 | 593 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
594 | |
595 | /* | |
596 | * The page is not mapped by the guest. Let the guest handle it. | |
597 | */ | |
7993ba43 | 598 | if (!r) { |
b8688d51 | 599 | pgprintk("%s: guest page fault\n", __func__); |
fb67e14f XG |
600 | if (!prefault) { |
601 | inject_page_fault(vcpu, &walker.fault); | |
602 | /* reset fork detector */ | |
603 | vcpu->arch.last_pt_write_count = 0; | |
604 | } | |
6aa8b732 AK |
605 | return 0; |
606 | } | |
607 | ||
936a5fe6 AA |
608 | if (walker.level >= PT_DIRECTORY_LEVEL) |
609 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
610 | else | |
611 | force_pt_level = 1; | |
612 | if (!force_pt_level) { | |
7e4e4056 JR |
613 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
614 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 615 | } |
7e4e4056 | 616 | |
e930bffe | 617 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 618 | smp_rmb(); |
af585b92 | 619 | |
78b2c54a | 620 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 621 | &map_writable)) |
af585b92 | 622 | return 0; |
d7824fff | 623 | |
d196e343 | 624 | /* mmio */ |
bebb106a XG |
625 | if (is_error_pfn(pfn)) { |
626 | unsigned access = walker.pte_access; | |
627 | bool dirty = is_dirty_gpte(walker.ptes[walker.level - 1]); | |
628 | ||
629 | if (!dirty) | |
630 | access &= ~ACC_WRITE_MASK; | |
631 | ||
632 | return kvm_handle_bad_page(vcpu, mmu_is_nested(vcpu) ? 0 : | |
633 | addr, access, walker.gfn, pfn); | |
634 | } | |
d196e343 | 635 | |
aaee2c94 | 636 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
637 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
638 | goto out_unlock; | |
bc32ce21 | 639 | |
8b1fe17c | 640 | trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 641 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
642 | if (!force_pt_level) |
643 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 644 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
fb67e14f | 645 | level, &write_pt, pfn, map_writable, prefault); |
a24e8099 | 646 | (void)sptep; |
b8688d51 | 647 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 648 | sptep, *sptep, write_pt); |
cea0f0e7 | 649 | |
a25f7e1f | 650 | if (!write_pt) |
ad312c7c | 651 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 652 | |
1165f5fe | 653 | ++vcpu->stat.pf_fixed; |
8b1fe17c | 654 | trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 655 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 656 | |
cea0f0e7 | 657 | return write_pt; |
e930bffe AA |
658 | |
659 | out_unlock: | |
660 | spin_unlock(&vcpu->kvm->mmu_lock); | |
661 | kvm_release_pfn_clean(pfn); | |
662 | return 0; | |
6aa8b732 AK |
663 | } |
664 | ||
a461930b | 665 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 666 | { |
a461930b | 667 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 668 | struct kvm_mmu_page *sp; |
08e850c6 | 669 | gpa_t pte_gpa = -1; |
a461930b AK |
670 | int level; |
671 | u64 *sptep; | |
4539b358 | 672 | int need_flush = 0; |
a461930b | 673 | |
bebb106a XG |
674 | vcpu_clear_mmio_info(vcpu, gva); |
675 | ||
a461930b | 676 | spin_lock(&vcpu->kvm->mmu_lock); |
a7052897 | 677 | |
a461930b AK |
678 | for_each_shadow_entry(vcpu, gva, iterator) { |
679 | level = iterator.level; | |
680 | sptep = iterator.sptep; | |
ad218f85 | 681 | |
f78978aa | 682 | sp = page_header(__pa(sptep)); |
884a0ff0 | 683 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 684 | int offset, shift; |
08e850c6 | 685 | |
f78978aa XG |
686 | if (!sp->unsync) |
687 | break; | |
688 | ||
22c9b2d1 XG |
689 | shift = PAGE_SHIFT - |
690 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
691 | offset = sp->role.quadrant << shift; | |
692 | ||
693 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 694 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
695 | |
696 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
697 | if (is_large_pte(*sptep)) |
698 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
699 | drop_spte(vcpu->kvm, sptep, |
700 | shadow_trap_nonpresent_pte); | |
4539b358 | 701 | need_flush = 1; |
be38d276 AK |
702 | } else |
703 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 704 | break; |
87917239 | 705 | } |
a7052897 | 706 | |
f78978aa | 707 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
708 | break; |
709 | } | |
a7052897 | 710 | |
4539b358 AA |
711 | if (need_flush) |
712 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
713 | |
714 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
715 | ||
ad218f85 | 716 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
717 | |
718 | if (pte_gpa == -1) | |
719 | return; | |
720 | ||
721 | if (mmu_topup_memory_caches(vcpu)) | |
722 | return; | |
723 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
724 | } |
725 | ||
1871c602 | 726 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 727 | struct x86_exception *exception) |
6aa8b732 AK |
728 | { |
729 | struct guest_walker walker; | |
e119d117 AK |
730 | gpa_t gpa = UNMAPPED_GVA; |
731 | int r; | |
6aa8b732 | 732 | |
33770780 | 733 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 734 | |
e119d117 | 735 | if (r) { |
1755fbcc | 736 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 737 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
738 | } else if (exception) |
739 | *exception = walker.fault; | |
6aa8b732 AK |
740 | |
741 | return gpa; | |
742 | } | |
743 | ||
6539e738 | 744 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
745 | u32 access, |
746 | struct x86_exception *exception) | |
6539e738 JR |
747 | { |
748 | struct guest_walker walker; | |
749 | gpa_t gpa = UNMAPPED_GVA; | |
750 | int r; | |
751 | ||
33770780 | 752 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
753 | |
754 | if (r) { | |
755 | gpa = gfn_to_gpa(walker.gfn); | |
756 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
757 | } else if (exception) |
758 | *exception = walker.fault; | |
6539e738 JR |
759 | |
760 | return gpa; | |
761 | } | |
762 | ||
c7addb90 AK |
763 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
764 | struct kvm_mmu_page *sp) | |
765 | { | |
eab9f71f AK |
766 | int i, j, offset, r; |
767 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
768 | gpa_t pte_gpa; | |
c7addb90 | 769 | |
f6e2c02b | 770 | if (sp->role.direct |
e5a4c8ca | 771 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
772 | nonpaging_prefetch_page(vcpu, sp); |
773 | return; | |
774 | } | |
775 | ||
eab9f71f AK |
776 | pte_gpa = gfn_to_gpa(sp->gfn); |
777 | if (PTTYPE == 32) { | |
e5a4c8ca | 778 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
779 | pte_gpa += offset * sizeof(pt_element_t); |
780 | } | |
7ec54588 | 781 | |
eab9f71f AK |
782 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
783 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
784 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
785 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 786 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
787 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
788 | else | |
789 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 790 | } |
c7addb90 AK |
791 | } |
792 | ||
e8bc217a MT |
793 | /* |
794 | * Using the cached information from sp->gfns is safe because: | |
795 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
796 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
797 | * |
798 | * Note: | |
799 | * We should flush all tlbs if spte is dropped even though guest is | |
800 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
801 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
802 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
803 | * freed pages. | |
804 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 805 | */ |
a4a8e6f7 | 806 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a MT |
807 | { |
808 | int i, offset, nr_present; | |
9bdbba13 | 809 | bool host_writable; |
51fb60d8 | 810 | gpa_t first_pte_gpa; |
e8bc217a MT |
811 | |
812 | offset = nr_present = 0; | |
813 | ||
2032a93d LJ |
814 | /* direct kvm_mmu_page can not be unsync. */ |
815 | BUG_ON(sp->role.direct); | |
816 | ||
e8bc217a MT |
817 | if (PTTYPE == 32) |
818 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
819 | ||
51fb60d8 GJ |
820 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
821 | ||
e8bc217a MT |
822 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
823 | unsigned pte_access; | |
824 | pt_element_t gpte; | |
825 | gpa_t pte_gpa; | |
f55c3f41 | 826 | gfn_t gfn; |
e8bc217a MT |
827 | |
828 | if (!is_shadow_present_pte(sp->spt[i])) | |
829 | continue; | |
830 | ||
51fb60d8 | 831 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
832 | |
833 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
834 | sizeof(pt_element_t))) | |
835 | return -EINVAL; | |
836 | ||
f55c3f41 | 837 | gfn = gpte_to_gfn(gpte); |
407c61c6 XG |
838 | |
839 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { | |
a4ee1ca4 | 840 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
841 | continue; |
842 | } | |
843 | ||
844 | if (gfn != sp->gfns[i]) { | |
845 | drop_spte(vcpu->kvm, &sp->spt[i], | |
846 | shadow_trap_nonpresent_pte); | |
a4ee1ca4 | 847 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
848 | continue; |
849 | } | |
850 | ||
851 | nr_present++; | |
852 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
f8e453b0 XG |
853 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
854 | ||
e8bc217a | 855 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 856 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 857 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 858 | host_writable); |
e8bc217a MT |
859 | } |
860 | ||
861 | return !nr_present; | |
862 | } | |
863 | ||
6aa8b732 AK |
864 | #undef pt_element_t |
865 | #undef guest_walker | |
866 | #undef FNAME | |
867 | #undef PT_BASE_ADDR_MASK | |
868 | #undef PT_INDEX | |
e04da980 JR |
869 | #undef PT_LVL_ADDR_MASK |
870 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 871 | #undef PT_LEVEL_BITS |
cea0f0e7 | 872 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 873 | #undef gpte_to_gfn |
e04da980 | 874 | #undef gpte_to_gfn_lvl |
b3e4e63f | 875 | #undef CMPXCHG |