[deliverable/linux.git] / arch / x86 / kvm / pmu.c

/*
 * Kernel-based Virtual Machine -- Performance Monitoring Unit support
 *
 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
 *
 * Authors:
 *   Avi Kivity   <avi@redhat.com>
 *   Gleb Natapov <gleb@redhat.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

#include <linux/types.h>
#include <linux/kvm_host.h>
#include <linux/perf_event.h>
#include <asm/perf_event.h>
#include "x86.h"
#include "cpuid.h"
#include "lapic.h"
#include "pmu.h"

static struct kvm_event_hw_type_mapping arch_events[] = {
	/* Index must match CPUID 0x0A.EBX bit vector */
	[0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
	[2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES  },
	[3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
	[4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
	[5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
	[6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
	[7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
};

/* mapping between fixed pmc index and arch_events array */
static int fixed_pmc_events[] = {1, 0, 7};

static bool pmc_is_gp(struct kvm_pmc *pmc)
{
	return pmc->type == KVM_PMC_GP;
}

static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
{
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);

	return pmu->counter_bitmask[pmc->type];
}

static inline bool pmc_is_enabled(struct kvm_pmc *pmc)
{
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
}

static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
					 u32 base)
{
	if (msr >= base && msr < base + pmu->nr_arch_gp_counters)
		return &pmu->gp_counters[msr - base];
	return NULL;
}

static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
{
	int base = MSR_CORE_PERF_FIXED_CTR0;
	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
		return &pmu->fixed_counters[msr - base];
	return NULL;
}

static inline struct kvm_pmc *get_fixed_pmc_idx(struct kvm_pmu *pmu, int idx)
{
	return get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + idx);
}

static struct kvm_pmc *global_idx_to_pmc(struct kvm_pmu *pmu, int idx)
{
	if (idx < INTEL_PMC_IDX_FIXED)
		return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0);
	else
		return get_fixed_pmc_idx(pmu, idx - INTEL_PMC_IDX_FIXED);
}

void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
{
	if (vcpu->arch.apic)
		kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
}

static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
{
	struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);

	kvm_pmu_deliver_pmi(vcpu);
}

static void kvm_perf_overflow(struct perf_event *perf_event,
			      struct perf_sample_data *data,
			      struct pt_regs *regs)
{
	struct kvm_pmc *pmc = perf_event->overflow_handler_context;
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);

	if (!test_and_set_bit(pmc->idx,
			      (unsigned long *)&pmu->reprogram_pmi)) {
		__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
		kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
	}
}

static void kvm_perf_overflow_intr(struct perf_event *perf_event,
				   struct perf_sample_data *data,
				   struct pt_regs *regs)
{
	struct kvm_pmc *pmc = perf_event->overflow_handler_context;
	struct kvm_pmu *pmu = pmc_to_pmu(pmc);

	if (!test_and_set_bit(pmc->idx,
			      (unsigned long *)&pmu->reprogram_pmi)) {
		__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
		kvm_make_request(KVM_REQ_PMU, pmc->vcpu);

		/*
		 * Inject PMI. If vcpu was in a guest mode during NMI PMI
		 * can be ejected on a guest mode re-entry. Otherwise we can't
		 * be sure that vcpu wasn't executing hlt instruction at the
		 * time of vmexit and is not going to re-enter guest mode until
		 * woken up. So we should wake it, but this is impossible from
		 * NMI context. Do it from irq work instead.
		 */
		if (!kvm_is_in_guest())
			irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
		else
			kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
	}
}

static u64 pmc_read_counter(struct kvm_pmc *pmc)
{
	u64 counter, enabled, running;

	counter = pmc->counter;

	if (pmc->perf_event)
		counter += perf_event_read_value(pmc->perf_event,
						 &enabled, &running);

	/* FIXME: Scaling needed? */

	return counter & pmc_bitmask(pmc);
}

static void pmc_stop_counter(struct kvm_pmc *pmc)
{
	if (pmc->perf_event) {
		pmc->counter = pmc_read_counter(pmc);
		perf_event_release_kernel(pmc->perf_event);
		pmc->perf_event = NULL;
	}
}

static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
				  unsigned config, bool exclude_user,
				  bool exclude_kernel, bool intr,
				  bool in_tx, bool in_tx_cp)
{
	struct perf_event *event;
	struct perf_event_attr attr = {
		.type = type,
		.size = sizeof(attr),
		.pinned = true,
		.exclude_idle = true,
		.exclude_host = 1,
		.exclude_user = exclude_user,
		.exclude_kernel = exclude_kernel,
		.config = config,
	};

	if (in_tx)
		attr.config |= HSW_IN_TX;
	if (in_tx_cp)
		attr.config |= HSW_IN_TX_CHECKPOINTED;

	attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);

	event = perf_event_create_kernel_counter(&attr, -1, current,
						 intr ? kvm_perf_overflow_intr :
						 kvm_perf_overflow, pmc);
	if (IS_ERR(event)) {
		printk_once("kvm_pmu: event creation failed %ld\n",
			    PTR_ERR(event));
		return;
	}

	pmc->perf_event = event;
	clear_bit(pmc->idx, (unsigned long*)&pmc_to_pmu(pmc)->reprogram_pmi);
}

static unsigned find_arch_event(struct kvm_pmu *pmu, u8 event_select,
		u8 unit_mask)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(arch_events); i++)
		if (arch_events[i].eventsel == event_select
				&& arch_events[i].unit_mask == unit_mask
				&& (pmu->available_event_types & (1 << i)))
			break;

	if (i == ARRAY_SIZE(arch_events))
		return PERF_COUNT_HW_MAX;

	return arch_events[i].event_type;
}

static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
{
	unsigned config, type = PERF_TYPE_RAW;
	u8 event_select, unit_mask;

	if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
		printk_once("kvm pmu: pin control bit is ignored\n");

	pmc->eventsel = eventsel;

	pmc_stop_counter(pmc);

	if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
		return;

	event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
	unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;

	if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
			  ARCH_PERFMON_EVENTSEL_INV |
			  ARCH_PERFMON_EVENTSEL_CMASK |
			  HSW_IN_TX |
			  HSW_IN_TX_CHECKPOINTED))) {
		config = find_arch_event(pmc_to_pmu(pmc), event_select,
				unit_mask);
		if (config != PERF_COUNT_HW_MAX)
			type = PERF_TYPE_HARDWARE;
	}

	if (type == PERF_TYPE_RAW)
		config = eventsel & X86_RAW_EVENT_MASK;

	pmc_reprogram_counter(pmc, type, config,
			      !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
			      !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
			      eventsel & ARCH_PERFMON_EVENTSEL_INT,
			      (eventsel & HSW_IN_TX),
			      (eventsel & HSW_IN_TX_CHECKPOINTED));
}

static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
{
	unsigned en_field = ctrl & 0x3;
	bool pmi = ctrl & 0x8;

	pmc_stop_counter(pmc);

	if (!en_field || !pmc_is_enabled(pmc))
		return;

	pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
			      arch_events[fixed_pmc_events[idx]].event_type,
			      !(en_field & 0x2), /* exclude user */
			      !(en_field & 0x1), /* exclude kernel */
			      pmi, false, false);
}

static inline u8 fixed_ctrl_field(u64 ctrl, int idx)
{
	return (ctrl >> (idx * 4)) & 0xf;
}

static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
{
	int i;

	for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
		u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
		u8 new_ctrl = fixed_ctrl_field(data, i);
		struct kvm_pmc *pmc = get_fixed_pmc_idx(pmu, i);

		if (old_ctrl == new_ctrl)
			continue;

		reprogram_fixed_counter(pmc, new_ctrl, i);
	}

	pmu->fixed_ctr_ctrl = data;
}

static void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
{
	struct kvm_pmc *pmc = global_idx_to_pmc(pmu, pmc_idx);

	if (!pmc)
		return;

	if (pmc_is_gp(pmc))
		reprogram_gp_counter(pmc, pmc->eventsel);
	else {
		int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
		u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);

		reprogram_fixed_counter(pmc, ctrl, idx);
	}
}

static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
{
	int bit;
	u64 diff = pmu->global_ctrl ^ data;

	pmu->global_ctrl = data;

	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
		reprogram_counter(pmu, bit);
}

bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	int ret;

	switch (msr) {
	case MSR_CORE_PERF_FIXED_CTR_CTRL:
	case MSR_CORE_PERF_GLOBAL_STATUS:
	case MSR_CORE_PERF_GLOBAL_CTRL:
	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
		ret = pmu->version > 1;
		break;
	default:
		ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)
			|| get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0)
			|| get_fixed_pmc(pmu, msr);
		break;
	}
	return ret;
}

int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_pmc *pmc;

	switch (index) {
	case MSR_CORE_PERF_FIXED_CTR_CTRL:
		*data = pmu->fixed_ctr_ctrl;
		return 0;
	case MSR_CORE_PERF_GLOBAL_STATUS:
		*data = pmu->global_status;
		return 0;
	case MSR_CORE_PERF_GLOBAL_CTRL:
		*data = pmu->global_ctrl;
		return 0;
	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
		*data = pmu->global_ovf_ctrl;
		return 0;
	default:
		if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
				(pmc = get_fixed_pmc(pmu, index))) {
			*data = pmc_read_counter(pmc);
			return 0;
		} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
			*data = pmc->eventsel;
			return 0;
		}
	}
	return 1;
}

int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_pmc *pmc;
	u32 index = msr_info->index;
	u64 data = msr_info->data;

	switch (index) {
	case MSR_CORE_PERF_FIXED_CTR_CTRL:
		if (pmu->fixed_ctr_ctrl == data)
			return 0;
		if (!(data & 0xfffffffffffff444ull)) {
			reprogram_fixed_counters(pmu, data);
			return 0;
		}
		break;
	case MSR_CORE_PERF_GLOBAL_STATUS:
		if (msr_info->host_initiated) {
			pmu->global_status = data;
			return 0;
		}
		break; /* RO MSR */
	case MSR_CORE_PERF_GLOBAL_CTRL:
		if (pmu->global_ctrl == data)
			return 0;
		if (!(data & pmu->global_ctrl_mask)) {
			global_ctrl_changed(pmu, data);
			return 0;
		}
		break;
	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
		if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
			if (!msr_info->host_initiated)
				pmu->global_status &= ~data;
			pmu->global_ovf_ctrl = data;
			return 0;
		}
		break;
	default:
		if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
				(pmc = get_fixed_pmc(pmu, index))) {
			if (!msr_info->host_initiated)
				data = (s64)(s32)data;
			pmc->counter += data - pmc_read_counter(pmc);
			return 0;
		} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
			if (data == pmc->eventsel)
				return 0;
			if (!(data & pmu->reserved_bits)) {
				reprogram_gp_counter(pmc, data);
				return 0;
			}
		}
	}
	return 1;
}

/* check if idx is a valid index to access PMU */
int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	bool fixed = idx & (1u << 30);
	idx &= ~(3u << 30);
	return (!fixed && idx >= pmu->nr_arch_gp_counters) ||
		(fixed && idx >= pmu->nr_arch_fixed_counters);
}

int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	bool fast_mode = idx & (1u << 31);
	bool fixed = idx & (1u << 30);
	struct kvm_pmc *counters;
	u64 ctr_val;

	idx &= ~(3u << 30);
	if (!fixed && idx >= pmu->nr_arch_gp_counters)
		return 1;
	if (fixed && idx >= pmu->nr_arch_fixed_counters)
		return 1;
	counters = fixed ? pmu->fixed_counters : pmu->gp_counters;

	ctr_val = pmc_read_counter(&counters[idx]);
	if (fast_mode)
		ctr_val = (u32)ctr_val;

	*data = ctr_val;
	return 0;
}

/* refresh PMU settings. This function generally is called when underlying
 * settings are changed (such as changes of PMU CPUID by guest VMs), which
 * should rarely happen.
 */
void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	struct kvm_cpuid_entry2 *entry;
	union cpuid10_eax eax;
	union cpuid10_edx edx;

	pmu->nr_arch_gp_counters = 0;
	pmu->nr_arch_fixed_counters = 0;
	pmu->counter_bitmask[KVM_PMC_GP] = 0;
	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
	pmu->version = 0;
	pmu->reserved_bits = 0xffffffff00200000ull;

	entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
	if (!entry)
		return;
	eax.full = entry->eax;
	edx.full = entry->edx;

	pmu->version = eax.split.version_id;
	if (!pmu->version)
		return;

	pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
					INTEL_PMC_MAX_GENERIC);
	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
	pmu->available_event_types = ~entry->ebx &
					((1ull << eax.split.mask_length) - 1);

	if (pmu->version == 1) {
		pmu->nr_arch_fixed_counters = 0;
	} else {
		pmu->nr_arch_fixed_counters =
			min_t(int, edx.split.num_counters_fixed,
				INTEL_PMC_MAX_FIXED);
		pmu->counter_bitmask[KVM_PMC_FIXED] =
			((u64)1 << edx.split.bit_width_fixed) - 1;
	}

	pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
	pmu->global_ctrl_mask = ~pmu->global_ctrl;

	entry = kvm_find_cpuid_entry(vcpu, 7, 0);
	if (entry &&
	    (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
	    (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
		pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;
}

void kvm_pmu_init(struct kvm_vcpu *vcpu)
{
	int i;
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);

	memset(pmu, 0, sizeof(*pmu));
	for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
		pmu->gp_counters[i].type = KVM_PMC_GP;
		pmu->gp_counters[i].vcpu = vcpu;
		pmu->gp_counters[i].idx = i;
	}
	for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
		pmu->fixed_counters[i].type = KVM_PMC_FIXED;
		pmu->fixed_counters[i].vcpu = vcpu;
		pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
	}
	init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
	kvm_pmu_refresh(vcpu);
}

void kvm_pmu_reset(struct kvm_vcpu *vcpu)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	int i;

	irq_work_sync(&pmu->irq_work);
	for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
		struct kvm_pmc *pmc = &pmu->gp_counters[i];
		pmc_stop_counter(pmc);
		pmc->counter = pmc->eventsel = 0;
	}

	for (i = 0; i < INTEL_PMC_MAX_FIXED; i++)
		pmc_stop_counter(&pmu->fixed_counters[i]);

	pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
		pmu->global_ovf_ctrl = 0;
}

void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
{
	kvm_pmu_reset(vcpu);
}

void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
{
	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
	u64 bitmask;
	int bit;

	bitmask = pmu->reprogram_pmi;

	for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) {
		struct kvm_pmc *pmc = global_idx_to_pmc(pmu, bit);

		if (unlikely(!pmc || !pmc->perf_event)) {
			clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi);
			continue;
		}

		reprogram_counter(pmu, bit);
	}
}
Commit	Line	Data
f5132b01	1	/*
c7a7062f	2	* Kernel-based Virtual Machine -- Performance Monitoring Unit support
f5132b01 GN	3	*
	4	* Copyright 2011 Red Hat, Inc. and/or its affiliates.
	5	*
	6	* Authors:
	7	* Avi Kivity <avi@redhat.com>
	8	* Gleb Natapov <gleb@redhat.com>
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
	12	*
	13	*/
	14
	15	#include <linux/types.h>
	16	#include <linux/kvm_host.h>
	17	#include <linux/perf_event.h>
d27aa7f1	18	#include <asm/perf_event.h>
f5132b01 GN	19	#include "x86.h"
	20	#include "cpuid.h"
	21	#include "lapic.h"
474a5bb9	22	#include "pmu.h"
f5132b01	23
474a5bb9	24	static struct kvm_event_hw_type_mapping arch_events[] = {
f5132b01 GN	25	/* Index must match CPUID 0x0A.EBX bit vector */
	26	[0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
	27	[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
	28	[2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES },
	29	[3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
	30	[4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
	31	[5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
	32	[6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
62079d8a	33	[7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
f5132b01 GN	34	};
	35
	36	/* mapping between fixed pmc index and arch_events array */
52eb5a6d	37	static int fixed_pmc_events[] = {1, 0, 7};
f5132b01 GN	38
	39	static bool pmc_is_gp(struct kvm_pmc *pmc)
	40	{
	41	return pmc->type == KVM_PMC_GP;
	42	}
	43
	44	static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
	45	{
212dba12	46	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
f5132b01 GN	47
	48	return pmu->counter_bitmask[pmc->type];
	49	}
	50
c6702c9d	51	static inline bool pmc_is_enabled(struct kvm_pmc *pmc)
f5132b01	52	{
212dba12	53	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
f5132b01 GN	54	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
	55	}
	56
	57	static inline struct kvm_pmc get_gp_pmc(struct kvm_pmu pmu, u32 msr,
	58	u32 base)
	59	{
	60	if (msr >= base && msr < base + pmu->nr_arch_gp_counters)
	61	return &pmu->gp_counters[msr - base];
	62	return NULL;
	63	}
	64
	65	static inline struct kvm_pmc get_fixed_pmc(struct kvm_pmu pmu, u32 msr)
	66	{
	67	int base = MSR_CORE_PERF_FIXED_CTR0;
	68	if (msr >= base && msr < base + pmu->nr_arch_fixed_counters)
	69	return &pmu->fixed_counters[msr - base];
	70	return NULL;
	71	}
	72
	73	static inline struct kvm_pmc get_fixed_pmc_idx(struct kvm_pmu pmu, int idx)
	74	{
	75	return get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + idx);
	76	}
	77
	78	static struct kvm_pmc global_idx_to_pmc(struct kvm_pmu pmu, int idx)
	79	{
15c7ad51	80	if (idx < INTEL_PMC_IDX_FIXED)
f5132b01 GN	81	return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0);
f5132b01 GN	82	else
15c7ad51	83	return get_fixed_pmc_idx(pmu, idx - INTEL_PMC_IDX_FIXED);
f5132b01 GN	84	}
f5132b01 GN	85
c6702c9d	86	void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
f5132b01 GN	87	{
	88	if (vcpu->arch.apic)
	89	kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
	90	}
	91
c6702c9d	92	static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
f5132b01	93	{
212dba12 WH	94	struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
212dba12 WH	95	struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
f5132b01	96
c6702c9d	97	kvm_pmu_deliver_pmi(vcpu);
f5132b01 GN	98	}
	99
	100	static void kvm_perf_overflow(struct perf_event *perf_event,
	101	struct perf_sample_data *data,
	102	struct pt_regs *regs)
	103	{
	104	struct kvm_pmc *pmc = perf_event->overflow_handler_context;
212dba12	105	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
e84cfe4c WH	106
	107	if (!test_and_set_bit(pmc->idx,
	108	(unsigned long *)&pmu->reprogram_pmi)) {
671bd993 NA	109	__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
	110	kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
	111	}
f5132b01 GN	112	}
	113
	114	static void kvm_perf_overflow_intr(struct perf_event *perf_event,
e84cfe4c WH	115	struct perf_sample_data *data,
e84cfe4c WH	116	struct pt_regs *regs)
f5132b01 GN	117	{
f5132b01 GN	118	struct kvm_pmc *pmc = perf_event->overflow_handler_context;
212dba12	119	struct kvm_pmu *pmu = pmc_to_pmu(pmc);
e84cfe4c WH	120
	121	if (!test_and_set_bit(pmc->idx,
	122	(unsigned long *)&pmu->reprogram_pmi)) {
671bd993	123	__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
f5132b01	124	kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
e84cfe4c	125
f5132b01 GN	126	/*
	127	* Inject PMI. If vcpu was in a guest mode during NMI PMI
	128	* can be ejected on a guest mode re-entry. Otherwise we can't
	129	* be sure that vcpu wasn't executing hlt instruction at the
e84cfe4c	130	* time of vmexit and is not going to re-enter guest mode until
f5132b01 GN	131	* woken up. So we should wake it, but this is impossible from
	132	* NMI context. Do it from irq work instead.
	133	*/
	134	if (!kvm_is_in_guest())
212dba12	135	irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
f5132b01 GN	136	else
	137	kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
	138	}
	139	}
	140
c6702c9d	141	static u64 pmc_read_counter(struct kvm_pmc *pmc)
f5132b01 GN	142	{
	143	u64 counter, enabled, running;
	144
	145	counter = pmc->counter;
	146
	147	if (pmc->perf_event)
	148	counter += perf_event_read_value(pmc->perf_event,
	149	&enabled, &running);
	150
	151	/* FIXME: Scaling needed? */
	152
	153	return counter & pmc_bitmask(pmc);
	154	}
	155
c6702c9d	156	static void pmc_stop_counter(struct kvm_pmc *pmc)
f5132b01 GN	157	{
f5132b01 GN	158	if (pmc->perf_event) {
c6702c9d	159	pmc->counter = pmc_read_counter(pmc);
f5132b01 GN	160	perf_event_release_kernel(pmc->perf_event);
	161	pmc->perf_event = NULL;
	162	}
	163	}
	164
c6702c9d	165	static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
e84cfe4c WH	166	unsigned config, bool exclude_user,
	167	bool exclude_kernel, bool intr,
	168	bool in_tx, bool in_tx_cp)
f5132b01 GN	169	{
	170	struct perf_event *event;
	171	struct perf_event_attr attr = {
	172	.type = type,
	173	.size = sizeof(attr),
	174	.pinned = true,
	175	.exclude_idle = true,
	176	.exclude_host = 1,
	177	.exclude_user = exclude_user,
	178	.exclude_kernel = exclude_kernel,
	179	.config = config,
	180	};
e84cfe4c	181
103af0a9 AK	182	if (in_tx)
	183	attr.config \|= HSW_IN_TX;
	184	if (in_tx_cp)
	185	attr.config \|= HSW_IN_TX_CHECKPOINTED;
f5132b01 GN	186
	187	attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
	188
	189	event = perf_event_create_kernel_counter(&attr, -1, current,
	190	intr ? kvm_perf_overflow_intr :
	191	kvm_perf_overflow, pmc);
	192	if (IS_ERR(event)) {
e84cfe4c WH	193	printk_once("kvm_pmu: event creation failed %ld\n",
e84cfe4c WH	194	PTR_ERR(event));
f5132b01 GN	195	return;
	196	}
	197
	198	pmc->perf_event = event;
212dba12	199	clear_bit(pmc->idx, (unsigned long*)&pmc_to_pmu(pmc)->reprogram_pmi);
f5132b01 GN	200	}
	201
	202	static unsigned find_arch_event(struct kvm_pmu *pmu, u8 event_select,
	203	u8 unit_mask)
	204	{
	205	int i;
	206
	207	for (i = 0; i < ARRAY_SIZE(arch_events); i++)
	208	if (arch_events[i].eventsel == event_select
	209	&& arch_events[i].unit_mask == unit_mask
	210	&& (pmu->available_event_types & (1 << i)))
	211	break;
	212
	213	if (i == ARRAY_SIZE(arch_events))
	214	return PERF_COUNT_HW_MAX;
	215
	216	return arch_events[i].event_type;
	217	}
	218
	219	static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
	220	{
	221	unsigned config, type = PERF_TYPE_RAW;
	222	u8 event_select, unit_mask;
	223
a7b9d2cc GN	224	if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
	225	printk_once("kvm pmu: pin control bit is ignored\n");
	226
f5132b01 GN	227	pmc->eventsel = eventsel;
f5132b01 GN	228
c6702c9d	229	pmc_stop_counter(pmc);
f5132b01	230
c6702c9d	231	if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) \|\| !pmc_is_enabled(pmc))
f5132b01 GN	232	return;
	233
	234	event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
	235	unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
	236
fac33683	237	if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE \|
e84cfe4c WH	238	ARCH_PERFMON_EVENTSEL_INV \|
	239	ARCH_PERFMON_EVENTSEL_CMASK \|
	240	HSW_IN_TX \|
	241	HSW_IN_TX_CHECKPOINTED))) {
212dba12	242	config = find_arch_event(pmc_to_pmu(pmc), event_select,
f5132b01 GN	243	unit_mask);
	244	if (config != PERF_COUNT_HW_MAX)
	245	type = PERF_TYPE_HARDWARE;
	246	}
	247
	248	if (type == PERF_TYPE_RAW)
	249	config = eventsel & X86_RAW_EVENT_MASK;
	250
c6702c9d	251	pmc_reprogram_counter(pmc, type, config,
e84cfe4c WH	252	!(eventsel & ARCH_PERFMON_EVENTSEL_USR),
	253	!(eventsel & ARCH_PERFMON_EVENTSEL_OS),
	254	eventsel & ARCH_PERFMON_EVENTSEL_INT,
	255	(eventsel & HSW_IN_TX),
	256	(eventsel & HSW_IN_TX_CHECKPOINTED));
f5132b01 GN	257	}
f5132b01 GN	258
e84cfe4c	259	static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
f5132b01	260	{
e84cfe4c WH	261	unsigned en_field = ctrl & 0x3;
e84cfe4c WH	262	bool pmi = ctrl & 0x8;
f5132b01	263
c6702c9d	264	pmc_stop_counter(pmc);
f5132b01	265
e84cfe4c	266	if (!en_field \|\| !pmc_is_enabled(pmc))
f5132b01 GN	267	return;
f5132b01 GN	268
c6702c9d	269	pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
e84cfe4c WH	270	arch_events[fixed_pmc_events[idx]].event_type,
	271	!(en_field & 0x2), /* exclude user */
	272	!(en_field & 0x1), /* exclude kernel */
	273	pmi, false, false);
f5132b01 GN	274	}
f5132b01 GN	275
c6702c9d	276	static inline u8 fixed_ctrl_field(u64 ctrl, int idx)
f5132b01 GN	277	{
	278	return (ctrl >> (idx * 4)) & 0xf;
	279	}
	280
	281	static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
	282	{
	283	int i;
	284
	285	for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
e84cfe4c WH	286	u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
e84cfe4c WH	287	u8 new_ctrl = fixed_ctrl_field(data, i);
f5132b01 GN	288	struct kvm_pmc *pmc = get_fixed_pmc_idx(pmu, i);
f5132b01 GN	289
e84cfe4c	290	if (old_ctrl == new_ctrl)
f5132b01 GN	291	continue;
f5132b01 GN	292
e84cfe4c	293	reprogram_fixed_counter(pmc, new_ctrl, i);
f5132b01 GN	294	}
	295
	296	pmu->fixed_ctr_ctrl = data;
	297	}
	298
e84cfe4c	299	static void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
f5132b01	300	{
e84cfe4c	301	struct kvm_pmc *pmc = global_idx_to_pmc(pmu, pmc_idx);
f5132b01 GN	302
	303	if (!pmc)
	304	return;
	305
	306	if (pmc_is_gp(pmc))
	307	reprogram_gp_counter(pmc, pmc->eventsel);
	308	else {
e84cfe4c WH	309	int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
	310	u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
	311
	312	reprogram_fixed_counter(pmc, ctrl, idx);
f5132b01 GN	313	}
	314	}
	315
	316	static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
	317	{
	318	int bit;
	319	u64 diff = pmu->global_ctrl ^ data;
	320
	321	pmu->global_ctrl = data;
	322
	323	for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
c6702c9d	324	reprogram_counter(pmu, bit);
f5132b01 GN	325	}
f5132b01 GN	326
c6702c9d	327	bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
f5132b01	328	{
212dba12	329	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01 GN	330	int ret;
	331
	332	switch (msr) {
	333	case MSR_CORE_PERF_FIXED_CTR_CTRL:
	334	case MSR_CORE_PERF_GLOBAL_STATUS:
	335	case MSR_CORE_PERF_GLOBAL_CTRL:
	336	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
	337	ret = pmu->version > 1;
	338	break;
	339	default:
	340	ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)
	341	\|\| get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0)
	342	\|\| get_fixed_pmc(pmu, msr);
	343	break;
	344	}
	345	return ret;
	346	}
	347
	348	int kvm_pmu_get_msr(struct kvm_vcpu vcpu, u32 index, u64 data)
	349	{
212dba12	350	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01 GN	351	struct kvm_pmc *pmc;
	352
	353	switch (index) {
	354	case MSR_CORE_PERF_FIXED_CTR_CTRL:
	355	*data = pmu->fixed_ctr_ctrl;
	356	return 0;
	357	case MSR_CORE_PERF_GLOBAL_STATUS:
	358	*data = pmu->global_status;
	359	return 0;
	360	case MSR_CORE_PERF_GLOBAL_CTRL:
	361	*data = pmu->global_ctrl;
	362	return 0;
	363	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
	364	*data = pmu->global_ovf_ctrl;
	365	return 0;
	366	default:
	367	if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) \|\|
	368	(pmc = get_fixed_pmc(pmu, index))) {
c6702c9d	369	*data = pmc_read_counter(pmc);
f5132b01 GN	370	return 0;
	371	} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
	372	*data = pmc->eventsel;
	373	return 0;
	374	}
	375	}
	376	return 1;
	377	}
	378
afd80d85	379	int kvm_pmu_set_msr(struct kvm_vcpu vcpu, struct msr_data msr_info)
f5132b01	380	{
212dba12	381	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01	382	struct kvm_pmc *pmc;
afd80d85 PB	383	u32 index = msr_info->index;
afd80d85 PB	384	u64 data = msr_info->data;
f5132b01 GN	385
	386	switch (index) {
	387	case MSR_CORE_PERF_FIXED_CTR_CTRL:
	388	if (pmu->fixed_ctr_ctrl == data)
	389	return 0;
fea52953	390	if (!(data & 0xfffffffffffff444ull)) {
f5132b01 GN	391	reprogram_fixed_counters(pmu, data);
	392	return 0;
	393	}
	394	break;
	395	case MSR_CORE_PERF_GLOBAL_STATUS:
afd80d85 PB	396	if (msr_info->host_initiated) {
	397	pmu->global_status = data;
	398	return 0;
	399	}
f5132b01 GN	400	break; /* RO MSR */
	401	case MSR_CORE_PERF_GLOBAL_CTRL:
	402	if (pmu->global_ctrl == data)
	403	return 0;
	404	if (!(data & pmu->global_ctrl_mask)) {
	405	global_ctrl_changed(pmu, data);
	406	return 0;
	407	}
	408	break;
	409	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
	410	if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
afd80d85 PB	411	if (!msr_info->host_initiated)
afd80d85 PB	412	pmu->global_status &= ~data;
f5132b01 GN	413	pmu->global_ovf_ctrl = data;
	414	return 0;
	415	}
	416	break;
	417	default:
	418	if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) \|\|
	419	(pmc = get_fixed_pmc(pmu, index))) {
afd80d85 PB	420	if (!msr_info->host_initiated)
afd80d85 PB	421	data = (s64)(s32)data;
c6702c9d	422	pmc->counter += data - pmc_read_counter(pmc);
f5132b01 GN	423	return 0;
	424	} else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
	425	if (data == pmc->eventsel)
	426	return 0;
103af0a9	427	if (!(data & pmu->reserved_bits)) {
f5132b01 GN	428	reprogram_gp_counter(pmc, data);
	429	return 0;
	430	}
	431	}
	432	}
	433	return 1;
	434	}
	435
e84cfe4c WH	436	/* check if idx is a valid index to access PMU */
e84cfe4c WH	437	int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx)
67f4d428	438	{
212dba12	439	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
e84cfe4c WH	440	bool fixed = idx & (1u << 30);
	441	idx &= ~(3u << 30);
	442	return (!fixed && idx >= pmu->nr_arch_gp_counters) \|\|
	443	(fixed && idx >= pmu->nr_arch_fixed_counters);
67f4d428 NA	444	}
67f4d428 NA	445
e84cfe4c	446	int kvm_pmu_rdpmc(struct kvm_vcpu vcpu, unsigned idx, u64 data)
f5132b01	447	{
212dba12	448	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
e84cfe4c WH	449	bool fast_mode = idx & (1u << 31);
e84cfe4c WH	450	bool fixed = idx & (1u << 30);
f5132b01	451	struct kvm_pmc *counters;
e84cfe4c	452	u64 ctr_val;
f5132b01	453
e84cfe4c WH	454	idx &= ~(3u << 30);
e84cfe4c WH	455	if (!fixed && idx >= pmu->nr_arch_gp_counters)
f5132b01	456	return 1;
e84cfe4c	457	if (fixed && idx >= pmu->nr_arch_fixed_counters)
f5132b01 GN	458	return 1;
f5132b01 GN	459	counters = fixed ? pmu->fixed_counters : pmu->gp_counters;
e84cfe4c WH	460
e84cfe4c WH	461	ctr_val = pmc_read_counter(&counters[idx]);
f5132b01	462	if (fast_mode)
e84cfe4c	463	ctr_val = (u32)ctr_val;
f5132b01	464
e84cfe4c	465	*data = ctr_val;
f5132b01 GN	466	return 0;
	467	}
	468
e84cfe4c WH	469	/* refresh PMU settings. This function generally is called when underlying
	470	* settings are changed (such as changes of PMU CPUID by guest VMs), which
	471	* should rarely happen.
	472	*/
c6702c9d	473	void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
f5132b01	474	{
212dba12	475	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01	476	struct kvm_cpuid_entry2 *entry;
d27aa7f1 NA	477	union cpuid10_eax eax;
d27aa7f1 NA	478	union cpuid10_edx edx;
f5132b01 GN	479
	480	pmu->nr_arch_gp_counters = 0;
	481	pmu->nr_arch_fixed_counters = 0;
	482	pmu->counter_bitmask[KVM_PMC_GP] = 0;
	483	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
	484	pmu->version = 0;
103af0a9	485	pmu->reserved_bits = 0xffffffff00200000ull;
f5132b01 GN	486
	487	entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
	488	if (!entry)
	489	return;
d27aa7f1 NA	490	eax.full = entry->eax;
d27aa7f1 NA	491	edx.full = entry->edx;
f5132b01	492
d27aa7f1	493	pmu->version = eax.split.version_id;
f5132b01 GN	494	if (!pmu->version)
	495	return;
	496
d27aa7f1 NA	497	pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
	498	INTEL_PMC_MAX_GENERIC);
	499	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
	500	pmu->available_event_types = ~entry->ebx &
	501	((1ull << eax.split.mask_length) - 1);
f5132b01 GN	502
f5132b01 GN	503	if (pmu->version == 1) {
f19a0c2c GN	504	pmu->nr_arch_fixed_counters = 0;
f19a0c2c GN	505	} else {
d27aa7f1 NA	506	pmu->nr_arch_fixed_counters =
d27aa7f1 NA	507	min_t(int, edx.split.num_counters_fixed,
15c7ad51	508	INTEL_PMC_MAX_FIXED);
f19a0c2c	509	pmu->counter_bitmask[KVM_PMC_FIXED] =
d27aa7f1	510	((u64)1 << edx.split.bit_width_fixed) - 1;
f5132b01 GN	511	}
f5132b01 GN	512
f19a0c2c	513	pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) \|
15c7ad51	514	(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
f19a0c2c	515	pmu->global_ctrl_mask = ~pmu->global_ctrl;
103af0a9 AK	516
	517	entry = kvm_find_cpuid_entry(vcpu, 7, 0);
	518	if (entry &&
	519	(boot_cpu_has(X86_FEATURE_HLE) \|\| boot_cpu_has(X86_FEATURE_RTM)) &&
	520	(entry->ebx & (X86_FEATURE_HLE\|X86_FEATURE_RTM)))
	521	pmu->reserved_bits ^= HSW_IN_TX\|HSW_IN_TX_CHECKPOINTED;
f5132b01 GN	522	}
	523
	524	void kvm_pmu_init(struct kvm_vcpu *vcpu)
	525	{
	526	int i;
212dba12	527	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01 GN	528
f5132b01 GN	529	memset(pmu, 0, sizeof(*pmu));
15c7ad51	530	for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
f5132b01 GN	531	pmu->gp_counters[i].type = KVM_PMC_GP;
	532	pmu->gp_counters[i].vcpu = vcpu;
	533	pmu->gp_counters[i].idx = i;
	534	}
15c7ad51	535	for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
f5132b01 GN	536	pmu->fixed_counters[i].type = KVM_PMC_FIXED;
f5132b01 GN	537	pmu->fixed_counters[i].vcpu = vcpu;
15c7ad51	538	pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
f5132b01	539	}
c6702c9d WH	540	init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
c6702c9d WH	541	kvm_pmu_refresh(vcpu);
f5132b01 GN	542	}
	543
	544	void kvm_pmu_reset(struct kvm_vcpu *vcpu)
	545	{
212dba12	546	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01 GN	547	int i;
	548
	549	irq_work_sync(&pmu->irq_work);
15c7ad51	550	for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
f5132b01	551	struct kvm_pmc *pmc = &pmu->gp_counters[i];
c6702c9d	552	pmc_stop_counter(pmc);
f5132b01 GN	553	pmc->counter = pmc->eventsel = 0;
	554	}
	555
15c7ad51	556	for (i = 0; i < INTEL_PMC_MAX_FIXED; i++)
c6702c9d	557	pmc_stop_counter(&pmu->fixed_counters[i]);
f5132b01 GN	558
	559	pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
	560	pmu->global_ovf_ctrl = 0;
	561	}
	562
	563	void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
	564	{
	565	kvm_pmu_reset(vcpu);
	566	}
	567
c6702c9d	568	void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
f5132b01	569	{
212dba12	570	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
f5132b01 GN	571	u64 bitmask;
	572	int bit;
	573
	574	bitmask = pmu->reprogram_pmi;
	575
	576	for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) {
	577	struct kvm_pmc *pmc = global_idx_to_pmc(pmu, bit);
	578
	579	if (unlikely(!pmc \|\| !pmc->perf_event)) {
	580	clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi);
	581	continue;
	582	}
	583
c6702c9d	584	reprogram_counter(pmu, bit);
f5132b01 GN	585	}
f5132b01 GN	586	}