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KVM: SVM: Add clean-bit for CR2 register
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64 100 /* cache for intercepts of the guest */
4ee546b4 101 u32 intercept_cr;
3aed041a 102 u32 intercept_dr;
aad42c64
JR		 103 u32 intercept_exceptions;
104 u64 intercept;
105
5bd2edc3
JR		 106 /* Nested Paging related state */
107 u64 nested_cr3;
e6aa9abd
JR		 108};
109
323c3d80
JR		 110#define MSRPM_OFFSETS 16
111static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
112
6c8166a7
AK		 113struct vcpu_svm {
114 struct kvm_vcpu vcpu;
115 struct vmcb *vmcb;
116 unsigned long vmcb_pa;
117 struct svm_cpu_data *svm_data;
118 uint64_t asid_generation;
119 uint64_t sysenter_esp;
120 uint64_t sysenter_eip;
121
122 u64 next_rip;
123
124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 125 struct {
dacccfdd
AK		 126 u16 fs;
127 u16 gs;
128 u16 ldt;
afe9e66f
AK		 129 u64 gs_base;
130 } host;
6c8166a7
AK		 131
132 u32 *msrpm;
6c8166a7 133
e6aa9abd 134 struct nested_state nested;
6be7d306
JK		 135
136 bool nmi_singlestep;
66b7138f
JK		 137
138 unsigned int3_injected;
139 unsigned long int3_rip;
631bc487 140 u32 apf_reason;
6c8166a7
AK		 141};
142
455716fa
JR		 143#define MSR_INVALID 0xffffffffU
144
ac72a9b7
JR		 145static struct svm_direct_access_msrs {
146 u32 index; /* Index of the MSR */
147 bool always; /* True if intercept is always on */
148} direct_access_msrs[] = {
8c06585d 149 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 150 { .index = MSR_IA32_SYSENTER_CS, .always = true },
151#ifdef CONFIG_X86_64
152 { .index = MSR_GS_BASE, .always = true },
153 { .index = MSR_FS_BASE, .always = true },
154 { .index = MSR_KERNEL_GS_BASE, .always = true },
155 { .index = MSR_LSTAR, .always = true },
156 { .index = MSR_CSTAR, .always = true },
157 { .index = MSR_SYSCALL_MASK, .always = true },
158#endif
159 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
160 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
161 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
162 { .index = MSR_IA32_LASTINTTOIP, .always = false },
163 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 164};
165
709ddebf
JR		 166/* enable NPT for AMD64 and X86 with PAE */
167#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168static bool npt_enabled = true;
169#else
e0231715 170static bool npt_enabled;
709ddebf 171#endif
6c7dac72
JR		 172static int npt = 1;
173
174module_param(npt, int, S_IRUGO);
e3da3acd 175
4b6e4dca 176static int nested = 1;
236de055
AG		 177module_param(nested, int, S_IRUGO);
178
44874f84 179static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 180static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 181
410e4d57 182static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 183static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 184static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 185static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
186 bool has_error_code, u32 error_code);
187
8d28fec4 188enum {
116a0a23
JR		 189 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
190 pause filter count */
f56838e4 191 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
d48086d1 192 VMCB_ASID, /* ASID */
decdbf6a 193 VMCB_INTR, /* int_ctl, int_vector */
b2747166 194 VMCB_NPT, /* npt_en, nCR3, gPAT */
dcca1a65 195 VMCB_CR, /* CR0, CR3, CR4, EFER */
72214b96 196 VMCB_DR, /* DR6, DR7 */
17a703cb 197 VMCB_DT, /* GDT, IDT */
060d0c9a 198 VMCB_SEG, /* CS, DS, SS, ES, CPL */
0574dec0 199 VMCB_CR2, /* CR2 only */
8d28fec4
RJ		 200 VMCB_DIRTY_MAX,
201};
202
0574dec0
JR		 203/* TPR and CR2 are always written before VMRUN */
204#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
8d28fec4
RJ		 205
206static inline void mark_all_dirty(struct vmcb *vmcb)
207{
208 vmcb->control.clean = 0;
209}
210
211static inline void mark_all_clean(struct vmcb *vmcb)
212{
213 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
214 & ~VMCB_ALWAYS_DIRTY_MASK;
215}
216
217static inline void mark_dirty(struct vmcb *vmcb, int bit)
218{
219 vmcb->control.clean &= ~(1 << bit);
220}
221
a2fa3e9f
GH		 222static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
223{
fb3f0f51 224 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 225}
226
384c6368
JR		 227static void recalc_intercepts(struct vcpu_svm *svm)
228{
229 struct vmcb_control_area *c, *h;
230 struct nested_state *g;
231
116a0a23
JR		 232 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
233
384c6368
JR		 234 if (!is_guest_mode(&svm->vcpu))
235 return;
236
237 c = &svm->vmcb->control;
238 h = &svm->nested.hsave->control;
239 g = &svm->nested;
240
4ee546b4 241 c->intercept_cr = h->intercept_cr | g->intercept_cr;
3aed041a 242 c->intercept_dr = h->intercept_dr | g->intercept_dr;
384c6368
JR		 243 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
244 c->intercept = h->intercept | g->intercept;
245}
246
4ee546b4
RJ		 247static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
248{
249 if (is_guest_mode(&svm->vcpu))
250 return svm->nested.hsave;
251 else
252 return svm->vmcb;
253}
254
255static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
256{
257 struct vmcb *vmcb = get_host_vmcb(svm);
258
259 vmcb->control.intercept_cr |= (1U << bit);
260
261 recalc_intercepts(svm);
262}
263
264static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
265{
266 struct vmcb *vmcb = get_host_vmcb(svm);
267
268 vmcb->control.intercept_cr &= ~(1U << bit);
269
270 recalc_intercepts(svm);
271}
272
273static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
274{
275 struct vmcb *vmcb = get_host_vmcb(svm);
276
277 return vmcb->control.intercept_cr & (1U << bit);
278}
279
3aed041a
JR		 280static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
281{
282 struct vmcb *vmcb = get_host_vmcb(svm);
283
284 vmcb->control.intercept_dr |= (1U << bit);
285
286 recalc_intercepts(svm);
287}
288
289static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
290{
291 struct vmcb *vmcb = get_host_vmcb(svm);
292
293 vmcb->control.intercept_dr &= ~(1U << bit);
294
295 recalc_intercepts(svm);
296}
297
18c918c5
JR		 298static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
299{
300 struct vmcb *vmcb = get_host_vmcb(svm);
301
302 vmcb->control.intercept_exceptions |= (1U << bit);
303
304 recalc_intercepts(svm);
305}
306
307static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
308{
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept_exceptions &= ~(1U << bit);
312
313 recalc_intercepts(svm);
314}
315
8a05a1b8
JR		 316static inline void set_intercept(struct vcpu_svm *svm, int bit)
317{
318 struct vmcb *vmcb = get_host_vmcb(svm);
319
320 vmcb->control.intercept |= (1ULL << bit);
321
322 recalc_intercepts(svm);
323}
324
325static inline void clr_intercept(struct vcpu_svm *svm, int bit)
326{
327 struct vmcb *vmcb = get_host_vmcb(svm);
328
329 vmcb->control.intercept &= ~(1ULL << bit);
330
331 recalc_intercepts(svm);
332}
333
2af9194d
JR		 334static inline void enable_gif(struct vcpu_svm *svm)
335{
336 svm->vcpu.arch.hflags |= HF_GIF_MASK;
337}
338
339static inline void disable_gif(struct vcpu_svm *svm)
340{
341 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
342}
343
344static inline bool gif_set(struct vcpu_svm *svm)
345{
346 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
347}
348
4866d5e3 349static unsigned long iopm_base;
6aa8b732
AK		 350
351struct kvm_ldttss_desc {
352 u16 limit0;
353 u16 base0;
e0231715
JR		 354 unsigned base1:8, type:5, dpl:2, p:1;
355 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 356 u32 base3;
357 u32 zero1;
358} __attribute__((packed));
359
360struct svm_cpu_data {
361 int cpu;
362
5008fdf5
AK		 363 u64 asid_generation;
364 u32 max_asid;
365 u32 next_asid;
6aa8b732
AK		 366 struct kvm_ldttss_desc *tss_desc;
367
368 struct page *save_area;
369};
370
371static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 372static uint32_t svm_features;
6aa8b732
AK		 373
374struct svm_init_data {
375 int cpu;
376 int r;
377};
378
379static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
380
9d8f549d 381#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 382#define MSRS_RANGE_SIZE 2048
383#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
384
455716fa
JR		 385static u32 svm_msrpm_offset(u32 msr)
386{
387 u32 offset;
388 int i;
389
390 for (i = 0; i < NUM_MSR_MAPS; i++) {
391 if (msr < msrpm_ranges[i] ||
392 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
393 continue;
394
395 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
396 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
397
398 /* Now we have the u8 offset - but need the u32 offset */
399 return offset / 4;
400 }
401
402 /* MSR not in any range */
403 return MSR_INVALID;
404}
405
6aa8b732
AK		 406#define MAX_INST_SIZE 15
407
6aa8b732
AK		 408static inline void clgi(void)
409{
4ecac3fd 410 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 411}
412
413static inline void stgi(void)
414{
4ecac3fd 415 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 416}
417
418static inline void invlpga(unsigned long addr, u32 asid)
419{
e0231715 420 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 421}
422
6aa8b732
AK		 423static inline void force_new_asid(struct kvm_vcpu *vcpu)
424{
a2fa3e9f 425 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 426}
427
428static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
429{
430 force_new_asid(vcpu);
431}
432
4b16184c
JR		 433static int get_npt_level(void)
434{
435#ifdef CONFIG_X86_64
436 return PT64_ROOT_LEVEL;
437#else
438 return PT32E_ROOT_LEVEL;
439#endif
440}
441
6aa8b732
AK		 442static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
443{
6dc696d4 444 vcpu->arch.efer = efer;
709ddebf 445 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 446 efer &= ~EFER_LME;
6aa8b732 447
9962d032 448 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
dcca1a65 449 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
6aa8b732
AK		 450}
451
6aa8b732
AK		 452static int is_external_interrupt(u32 info)
453{
454 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
455 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
456}
457
2809f5d2
GC		 458static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
459{
460 struct vcpu_svm *svm = to_svm(vcpu);
461 u32 ret = 0;
462
463 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 464 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 465 return ret & mask;
466}
467
468static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
469{
470 struct vcpu_svm *svm = to_svm(vcpu);
471
472 if (mask == 0)
473 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
474 else
475 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
476
477}
478
6aa8b732
AK		 479static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
480{
a2fa3e9f
GH		 481 struct vcpu_svm *svm = to_svm(vcpu);
482
6bc31bdc
AP		 483 if (svm->vmcb->control.next_rip != 0)
484 svm->next_rip = svm->vmcb->control.next_rip;
485
a2fa3e9f 486 if (!svm->next_rip) {
851ba692 487 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 488 EMULATE_DONE)
489 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 490 return;
491 }
5fdbf976
MT		 492 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
493 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
494 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 495
5fdbf976 496 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 497 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 498}
499
116a4752 500static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 501 bool has_error_code, u32 error_code,
502 bool reinject)
116a4752
JK		 503{
504 struct vcpu_svm *svm = to_svm(vcpu);
505
e0231715
JR		 506 /*
507 * If we are within a nested VM we'd better #VMEXIT and let the guest
508 * handle the exception
509 */
ce7ddec4
JR		 510 if (!reinject &&
511 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 512 return;
513
2a6b20b8 514 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 515 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
516
517 /*
518 * For guest debugging where we have to reinject #BP if some
519 * INT3 is guest-owned:
520 * Emulate nRIP by moving RIP forward. Will fail if injection
521 * raises a fault that is not intercepted. Still better than
522 * failing in all cases.
523 */
524 skip_emulated_instruction(&svm->vcpu);
525 rip = kvm_rip_read(&svm->vcpu);
526 svm->int3_rip = rip + svm->vmcb->save.cs.base;
527 svm->int3_injected = rip - old_rip;
528 }
529
116a4752
JK		 530 svm->vmcb->control.event_inj = nr
531 | SVM_EVTINJ_VALID
532 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
533 | SVM_EVTINJ_TYPE_EXEPT;
534 svm->vmcb->control.event_inj_err = error_code;
535}
536
67ec6607
JR		 537static void svm_init_erratum_383(void)
538{
539 u32 low, high;
540 int err;
541 u64 val;
542
1be85a6d 543 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 544 return;
545
546 /* Use _safe variants to not break nested virtualization */
547 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
548 if (err)
549 return;
550
551 val |= (1ULL << 47);
552
553 low = lower_32_bits(val);
554 high = upper_32_bits(val);
555
556 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
557
558 erratum_383_found = true;
559}
560
6aa8b732
AK		 561static int has_svm(void)
562{
63d1142f 563 const char *msg;
6aa8b732 564
63d1142f 565 if (!cpu_has_svm(&msg)) {
ff81ff10 566 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 567 return 0;
568 }
569
6aa8b732
AK		 570 return 1;
571}
572
573static void svm_hardware_disable(void *garbage)
574{
2c8dceeb 575 cpu_svm_disable();
6aa8b732
AK		 576}
577
10474ae8 578static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 579{
580
0fe1e009 581 struct svm_cpu_data *sd;
6aa8b732 582 uint64_t efer;
89a27f4d 583 struct desc_ptr gdt_descr;
6aa8b732
AK		 584 struct desc_struct *gdt;
585 int me = raw_smp_processor_id();
586
10474ae8
AG		 587 rdmsrl(MSR_EFER, efer);
588 if (efer & EFER_SVME)
589 return -EBUSY;
590
6aa8b732 591 if (!has_svm()) {
e6732a5a
ZA		 592 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
593 me);
10474ae8 594 return -EINVAL;
6aa8b732 595 }
0fe1e009 596 sd = per_cpu(svm_data, me);
6aa8b732 597
0fe1e009 598 if (!sd) {
e6732a5a 599 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 600 me);
10474ae8 601 return -EINVAL;
6aa8b732
AK		 602 }
603
0fe1e009
TH		 604 sd->asid_generation = 1;
605 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
606 sd->next_asid = sd->max_asid + 1;
6aa8b732 607
d6ab1ed4 608 native_store_gdt(&gdt_descr);
89a27f4d 609 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 610 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 611
9962d032 612 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 613
d0316554 614 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 615
67ec6607
JR		 616 svm_init_erratum_383();
617
10474ae8 618 return 0;
6aa8b732
AK		 619}
620
0da1db75
JR		 621static void svm_cpu_uninit(int cpu)
622{
0fe1e009 623 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 624
0fe1e009 625 if (!sd)
0da1db75
JR		 626 return;
627
628 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 629 __free_page(sd->save_area);
630 kfree(sd);
0da1db75
JR		 631}
632
6aa8b732
AK		 633static int svm_cpu_init(int cpu)
634{
0fe1e009 635 struct svm_cpu_data *sd;
6aa8b732
AK		 636 int r;
637
0fe1e009
TH		 638 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
639 if (!sd)
6aa8b732 640 return -ENOMEM;
0fe1e009
TH		 641 sd->cpu = cpu;
642 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 643 r = -ENOMEM;
0fe1e009 644 if (!sd->save_area)
6aa8b732
AK		 645 goto err_1;
646
0fe1e009 647 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 648
649 return 0;
650
651err_1:
0fe1e009 652 kfree(sd);
6aa8b732
AK		 653 return r;
654
655}
656
ac72a9b7
JR		 657static bool valid_msr_intercept(u32 index)
658{
659 int i;
660
661 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
662 if (direct_access_msrs[i].index == index)
663 return true;
664
665 return false;
666}
667
bfc733a7
RR		 668static void set_msr_interception(u32 *msrpm, unsigned msr,
669 int read, int write)
6aa8b732 670{
455716fa
JR		 671 u8 bit_read, bit_write;
672 unsigned long tmp;
673 u32 offset;
6aa8b732 674
ac72a9b7
JR		 675 /*
676 * If this warning triggers extend the direct_access_msrs list at the
677 * beginning of the file
678 */
679 WARN_ON(!valid_msr_intercept(msr));
680
455716fa
JR		 681 offset = svm_msrpm_offset(msr);
682 bit_read = 2 * (msr & 0x0f);
683 bit_write = 2 * (msr & 0x0f) + 1;
684 tmp = msrpm[offset];
685
686 BUG_ON(offset == MSR_INVALID);
687
688 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
689 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
690
691 msrpm[offset] = tmp;
6aa8b732
AK		 692}
693
f65c229c 694static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 695{
696 int i;
697
f65c229c
JR		 698 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
699
ac72a9b7
JR		 700 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
701 if (!direct_access_msrs[i].always)
702 continue;
703
704 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
705 }
f65c229c
JR		 706}
707
323c3d80
JR		 708static void add_msr_offset(u32 offset)
709{
710 int i;
711
712 for (i = 0; i < MSRPM_OFFSETS; ++i) {
713
714 /* Offset already in list? */
715 if (msrpm_offsets[i] == offset)
bfc733a7 716 return;
323c3d80
JR		 717
718 /* Slot used by another offset? */
719 if (msrpm_offsets[i] != MSR_INVALID)
720 continue;
721
722 /* Add offset to list */
723 msrpm_offsets[i] = offset;
724
725 return;
6aa8b732 726 }
323c3d80
JR		 727
728 /*
729 * If this BUG triggers the msrpm_offsets table has an overflow. Just
730 * increase MSRPM_OFFSETS in this case.
731 */
bfc733a7 732 BUG();
6aa8b732
AK		 733}
734
323c3d80 735static void init_msrpm_offsets(void)
f65c229c 736{
323c3d80 737 int i;
f65c229c 738
323c3d80
JR		 739 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
740
741 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
742 u32 offset;
743
744 offset = svm_msrpm_offset(direct_access_msrs[i].index);
745 BUG_ON(offset == MSR_INVALID);
746
747 add_msr_offset(offset);
748 }
f65c229c
JR		 749}
750
24e09cbf
JR		 751static void svm_enable_lbrv(struct vcpu_svm *svm)
752{
753 u32 *msrpm = svm->msrpm;
754
755 svm->vmcb->control.lbr_ctl = 1;
756 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
757 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
758 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
759 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
760}
761
762static void svm_disable_lbrv(struct vcpu_svm *svm)
763{
764 u32 *msrpm = svm->msrpm;
765
766 svm->vmcb->control.lbr_ctl = 0;
767 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
768 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
769 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
770 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
771}
772
6aa8b732
AK		 773static __init int svm_hardware_setup(void)
774{
775 int cpu;
776 struct page *iopm_pages;
f65c229c 777 void *iopm_va;
6aa8b732
AK		 778 int r;
779
6aa8b732
AK		 780 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
781
782 if (!iopm_pages)
783 return -ENOMEM;
c8681339
AL		 784
785 iopm_va = page_address(iopm_pages);
786 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 787 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
788
323c3d80
JR		 789 init_msrpm_offsets();
790
50a37eb4
JR		 791 if (boot_cpu_has(X86_FEATURE_NX))
792 kvm_enable_efer_bits(EFER_NX);
793
1b2fd70c
AG		 794 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
795 kvm_enable_efer_bits(EFER_FFXSR);
796
236de055
AG		 797 if (nested) {
798 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 799 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 800 }
801
3230bb47 802 for_each_possible_cpu(cpu) {
6aa8b732
AK		 803 r = svm_cpu_init(cpu);
804 if (r)
f65c229c 805 goto err;
6aa8b732 806 }
33bd6a0b
JR		 807
808 svm_features = cpuid_edx(SVM_CPUID_FUNC);
809
2a6b20b8 810 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 811 npt_enabled = false;
812
6c7dac72
JR		 813 if (npt_enabled && !npt) {
814 printk(KERN_INFO "kvm: Nested Paging disabled\n");
815 npt_enabled = false;
816 }
817
18552672 818 if (npt_enabled) {
e3da3acd 819 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 820 kvm_enable_tdp();
5f4cb662
JR		 821 } else
822 kvm_disable_tdp();
e3da3acd 823
6aa8b732
AK		 824 return 0;
825
f65c229c 826err:
6aa8b732
AK		 827 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
828 iopm_base = 0;
829 return r;
830}
831
832static __exit void svm_hardware_unsetup(void)
833{
0da1db75
JR		 834 int cpu;
835
3230bb47 836 for_each_possible_cpu(cpu)
0da1db75
JR		 837 svm_cpu_uninit(cpu);
838
6aa8b732 839 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 840 iopm_base = 0;
6aa8b732
AK		 841}
842
843static void init_seg(struct vmcb_seg *seg)
844{
845 seg->selector = 0;
846 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 847 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 848 seg->limit = 0xffff;
849 seg->base = 0;
850}
851
852static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
853{
854 seg->selector = 0;
855 seg->attrib = SVM_SELECTOR_P_MASK | type;
856 seg->limit = 0xffff;
857 seg->base = 0;
858}
859
f4e1b3c8
ZA		 860static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
861{
862 struct vcpu_svm *svm = to_svm(vcpu);
863 u64 g_tsc_offset = 0;
864
2030753d 865 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 866 g_tsc_offset = svm->vmcb->control.tsc_offset -
867 svm->nested.hsave->control.tsc_offset;
868 svm->nested.hsave->control.tsc_offset = offset;
869 }
870
871 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23
JR		 872
873 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
f4e1b3c8
ZA		 874}
875
e48672fa
ZA		 876static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
877{
878 struct vcpu_svm *svm = to_svm(vcpu);
879
880 svm->vmcb->control.tsc_offset += adjustment;
2030753d 881 if (is_guest_mode(vcpu))
e48672fa 882 svm->nested.hsave->control.tsc_offset += adjustment;
116a0a23 883 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
e48672fa
ZA		 884}
885
e6101a96 886static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 887{
e6101a96
JR		 888 struct vmcb_control_area *control = &svm->vmcb->control;
889 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 890
bff78274 891 svm->vcpu.fpu_active = 1;
4ee546b4 892 svm->vcpu.arch.hflags = 0;
bff78274 893
4ee546b4
RJ		 894 set_cr_intercept(svm, INTERCEPT_CR0_READ);
895 set_cr_intercept(svm, INTERCEPT_CR3_READ);
896 set_cr_intercept(svm, INTERCEPT_CR4_READ);
897 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
898 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
899 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
900 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 901
3aed041a
JR		 902 set_dr_intercept(svm, INTERCEPT_DR0_READ);
903 set_dr_intercept(svm, INTERCEPT_DR1_READ);
904 set_dr_intercept(svm, INTERCEPT_DR2_READ);
905 set_dr_intercept(svm, INTERCEPT_DR3_READ);
906 set_dr_intercept(svm, INTERCEPT_DR4_READ);
907 set_dr_intercept(svm, INTERCEPT_DR5_READ);
908 set_dr_intercept(svm, INTERCEPT_DR6_READ);
909 set_dr_intercept(svm, INTERCEPT_DR7_READ);
910
911 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
914 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
915 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
916 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
917 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
918 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
6aa8b732 919
18c918c5
JR		 920 set_exception_intercept(svm, PF_VECTOR);
921 set_exception_intercept(svm, UD_VECTOR);
922 set_exception_intercept(svm, MC_VECTOR);
6aa8b732 923
8a05a1b8
JR		 924 set_intercept(svm, INTERCEPT_INTR);
925 set_intercept(svm, INTERCEPT_NMI);
926 set_intercept(svm, INTERCEPT_SMI);
927 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
928 set_intercept(svm, INTERCEPT_CPUID);
929 set_intercept(svm, INTERCEPT_INVD);
930 set_intercept(svm, INTERCEPT_HLT);
931 set_intercept(svm, INTERCEPT_INVLPG);
932 set_intercept(svm, INTERCEPT_INVLPGA);
933 set_intercept(svm, INTERCEPT_IOIO_PROT);
934 set_intercept(svm, INTERCEPT_MSR_PROT);
935 set_intercept(svm, INTERCEPT_TASK_SWITCH);
936 set_intercept(svm, INTERCEPT_SHUTDOWN);
937 set_intercept(svm, INTERCEPT_VMRUN);
938 set_intercept(svm, INTERCEPT_VMMCALL);
939 set_intercept(svm, INTERCEPT_VMLOAD);
940 set_intercept(svm, INTERCEPT_VMSAVE);
941 set_intercept(svm, INTERCEPT_STGI);
942 set_intercept(svm, INTERCEPT_CLGI);
943 set_intercept(svm, INTERCEPT_SKINIT);
944 set_intercept(svm, INTERCEPT_WBINVD);
945 set_intercept(svm, INTERCEPT_MONITOR);
946 set_intercept(svm, INTERCEPT_MWAIT);
6aa8b732
AK		 947
948 control->iopm_base_pa = iopm_base;
f65c229c 949 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 950 control->int_ctl = V_INTR_MASKING_MASK;
951
952 init_seg(&save->es);
953 init_seg(&save->ss);
954 init_seg(&save->ds);
955 init_seg(&save->fs);
956 init_seg(&save->gs);
957
958 save->cs.selector = 0xf000;
959 /* Executable/Readable Code Segment */
960 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
961 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
962 save->cs.limit = 0xffff;
d92899a0
AK		 963 /*
964 * cs.base should really be 0xffff0000, but vmx can't handle that, so
965 * be consistent with it.
966 *
967 * Replace when we have real mode working for vmx.
968 */
969 save->cs.base = 0xf0000;
6aa8b732
AK		 970
971 save->gdtr.limit = 0xffff;
972 save->idtr.limit = 0xffff;
973
974 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
975 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
976
eaa48512 977 svm_set_efer(&svm->vcpu, 0);
d77c26fc 978 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 979 save->dr7 = 0x400;
980 save->rflags = 2;
981 save->rip = 0x0000fff0;
5fdbf976 982 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 983
e0231715
JR		 984 /*
985 * This is the guest-visible cr0 value.
18fa000a 986 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 987 */
678041ad
MT		 988 svm->vcpu.arch.cr0 = 0;
989 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 990
66aee91a 991 save->cr4 = X86_CR4_PAE;
6aa8b732 992 /* rdx = ?? */
709ddebf
JR		 993
994 if (npt_enabled) {
995 /* Setup VMCB for Nested Paging */
996 control->nested_ctl = 1;
8a05a1b8
JR		 997 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
998 clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 999 clr_exception_intercept(svm, PF_VECTOR);
4ee546b4
RJ		 1000 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1001 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
709ddebf 1002 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 1003 save->cr3 = 0;
1004 save->cr4 = 0;
1005 }
a79d2f18 1006 force_new_asid(&svm->vcpu);
1371d904 1007
e6aa9abd 1008 svm->nested.vmcb = 0;
2af9194d
JR		 1009 svm->vcpu.arch.hflags = 0;
1010
2a6b20b8 1011 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998 1012 control->pause_filter_count = 3000;
8a05a1b8 1013 set_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1014 }
1015
8d28fec4
RJ		 1016 mark_all_dirty(svm->vmcb);
1017
2af9194d 1018 enable_gif(svm);
6aa8b732
AK		 1019}
1020
e00c8cf2 1021static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 1022{
1023 struct vcpu_svm *svm = to_svm(vcpu);
1024
e6101a96 1025 init_vmcb(svm);
70433389 1026
c5af89b6 1027 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 1028 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 1029 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1030 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 1031 }
5fdbf976
MT		 1032 vcpu->arch.regs_avail = ~0;
1033 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 1034
1035 return 0;
04d2cc77
AK		 1036}
1037
fb3f0f51 1038static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 1039{
a2fa3e9f 1040 struct vcpu_svm *svm;
6aa8b732 1041 struct page *page;
f65c229c 1042 struct page *msrpm_pages;
b286d5d8 1043 struct page *hsave_page;
3d6368ef 1044 struct page *nested_msrpm_pages;
fb3f0f51 1045 int err;
6aa8b732 1046
c16f862d 1047 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 1048 if (!svm) {
1049 err = -ENOMEM;
1050 goto out;
1051 }
1052
1053 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1054 if (err)
1055 goto free_svm;
1056
b7af4043 1057 err = -ENOMEM;
6aa8b732 1058 page = alloc_page(GFP_KERNEL);
b7af4043 1059 if (!page)
fb3f0f51 1060 goto uninit;
6aa8b732 1061
f65c229c
JR		 1062 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1063 if (!msrpm_pages)
b7af4043 1064 goto free_page1;
3d6368ef
AG		 1065
1066 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1067 if (!nested_msrpm_pages)
b7af4043 1068 goto free_page2;
f65c229c 1069
b286d5d8
AG		 1070 hsave_page = alloc_page(GFP_KERNEL);
1071 if (!hsave_page)
b7af4043
TY		 1072 goto free_page3;
1073
e6aa9abd 1074 svm->nested.hsave = page_address(hsave_page);
b286d5d8 1075
b7af4043
TY		 1076 svm->msrpm = page_address(msrpm_pages);
1077 svm_vcpu_init_msrpm(svm->msrpm);
1078
e6aa9abd 1079 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 1080 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 1081
a2fa3e9f
GH		 1082 svm->vmcb = page_address(page);
1083 clear_page(svm->vmcb);
1084 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1085 svm->asid_generation = 0;
e6101a96 1086 init_vmcb(svm);
99e3e30a 1087 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 1088
10ab25cd
JK		 1089 err = fx_init(&svm->vcpu);
1090 if (err)
1091 goto free_page4;
1092
ad312c7c 1093 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 1094 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 1095 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1096
fb3f0f51 1097 return &svm->vcpu;
36241b8c 1098
10ab25cd
JK		 1099free_page4:
1100 __free_page(hsave_page);
b7af4043
TY		 1101free_page3:
1102 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1103free_page2:
1104 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1105free_page1:
1106 __free_page(page);
fb3f0f51
RR		 1107uninit:
1108 kvm_vcpu_uninit(&svm->vcpu);
1109free_svm:
a4770347 1110 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 1111out:
1112 return ERR_PTR(err);
6aa8b732
AK		 1113}
1114
1115static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1116{
a2fa3e9f
GH		 1117 struct vcpu_svm *svm = to_svm(vcpu);
1118
fb3f0f51 1119 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 1120 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 1121 __free_page(virt_to_page(svm->nested.hsave));
1122 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 1123 kvm_vcpu_uninit(vcpu);
a4770347 1124 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 1125}
1126
15ad7146 1127static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1128{
a2fa3e9f 1129 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 1130 int i;
0cc5064d 1131
0cc5064d 1132 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1133 svm->asid_generation = 0;
8d28fec4 1134 mark_all_dirty(svm->vmcb);
0cc5064d 1135 }
94dfbdb3 1136
82ca2d10
AK		 1137#ifdef CONFIG_X86_64
1138 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1139#endif
dacccfdd
AK		 1140 savesegment(fs, svm->host.fs);
1141 savesegment(gs, svm->host.gs);
1142 svm->host.ldt = kvm_read_ldt();
1143
94dfbdb3 1144 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1145 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1146}
1147
1148static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1149{
a2fa3e9f 1150 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1151 int i;
1152
e1beb1d3 1153 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1154 kvm_load_ldt(svm->host.ldt);
1155#ifdef CONFIG_X86_64
1156 loadsegment(fs, svm->host.fs);
1157 load_gs_index(svm->host.gs);
1158 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1159#else
1160 loadsegment(gs, svm->host.gs);
1161#endif
94dfbdb3 1162 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1163 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1164}
1165
6aa8b732
AK		 1166static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1167{
a2fa3e9f 1168 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1169}
1170
1171static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1172{
a2fa3e9f 1173 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1174}
1175
6de4f3ad
AK		 1176static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1177{
1178 switch (reg) {
1179 case VCPU_EXREG_PDPTR:
1180 BUG_ON(!npt_enabled);
ff03a073 1181 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1182 break;
1183 default:
1184 BUG();
1185 }
1186}
1187
f0b85051
AG		 1188static void svm_set_vintr(struct vcpu_svm *svm)
1189{
8a05a1b8 1190 set_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1191}
1192
1193static void svm_clear_vintr(struct vcpu_svm *svm)
1194{
8a05a1b8 1195 clr_intercept(svm, INTERCEPT_VINTR);
f0b85051
AG		 1196}
1197
6aa8b732
AK		 1198static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1199{
a2fa3e9f 1200 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1201
1202 switch (seg) {
1203 case VCPU_SREG_CS: return &save->cs;
1204 case VCPU_SREG_DS: return &save->ds;
1205 case VCPU_SREG_ES: return &save->es;
1206 case VCPU_SREG_FS: return &save->fs;
1207 case VCPU_SREG_GS: return &save->gs;
1208 case VCPU_SREG_SS: return &save->ss;
1209 case VCPU_SREG_TR: return &save->tr;
1210 case VCPU_SREG_LDTR: return &save->ldtr;
1211 }
1212 BUG();
8b6d44c7 1213 return NULL;
6aa8b732
AK		 1214}
1215
1216static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1217{
1218 struct vmcb_seg *s = svm_seg(vcpu, seg);
1219
1220 return s->base;
1221}
1222
1223static void svm_get_segment(struct kvm_vcpu *vcpu,
1224 struct kvm_segment *var, int seg)
1225{
1226 struct vmcb_seg *s = svm_seg(vcpu, seg);
1227
1228 var->base = s->base;
1229 var->limit = s->limit;
1230 var->selector = s->selector;
1231 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1232 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1233 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1234 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1235 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1236 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1237 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1238 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1239
e0231715
JR		 1240 /*
1241 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1242 * for cross vendor migration purposes by "not present"
1243 */
1244 var->unusable = !var->present || (var->type == 0);
1245
1fbdc7a5
AP		 1246 switch (seg) {
1247 case VCPU_SREG_CS:
1248 /*
1249 * SVM always stores 0 for the 'G' bit in the CS selector in
1250 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1251 * Intel's VMENTRY has a check on the 'G' bit.
1252 */
25022acc 1253 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1254 break;
1255 case VCPU_SREG_TR:
1256 /*
1257 * Work around a bug where the busy flag in the tr selector
1258 * isn't exposed
1259 */
c0d09828 1260 var->type |= 0x2;
1fbdc7a5
AP		 1261 break;
1262 case VCPU_SREG_DS:
1263 case VCPU_SREG_ES:
1264 case VCPU_SREG_FS:
1265 case VCPU_SREG_GS:
1266 /*
1267 * The accessed bit must always be set in the segment
1268 * descriptor cache, although it can be cleared in the
1269 * descriptor, the cached bit always remains at 1. Since
1270 * Intel has a check on this, set it here to support
1271 * cross-vendor migration.
1272 */
1273 if (!var->unusable)
1274 var->type |= 0x1;
1275 break;
b586eb02 1276 case VCPU_SREG_SS:
e0231715
JR		 1277 /*
1278 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1279 * descriptor is left as 1, although the whole segment has
1280 * been made unusable. Clear it here to pass an Intel VMX
1281 * entry check when cross vendor migrating.
1282 */
1283 if (var->unusable)
1284 var->db = 0;
1285 break;
1fbdc7a5 1286 }
6aa8b732
AK		 1287}
1288
2e4d2653
IE		 1289static int svm_get_cpl(struct kvm_vcpu *vcpu)
1290{
1291 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1292
1293 return save->cpl;
1294}
1295
89a27f4d 1296static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1297{
a2fa3e9f
GH		 1298 struct vcpu_svm *svm = to_svm(vcpu);
1299
89a27f4d
GN		 1300 dt->size = svm->vmcb->save.idtr.limit;
1301 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1302}
1303
89a27f4d 1304static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1305{
a2fa3e9f
GH		 1306 struct vcpu_svm *svm = to_svm(vcpu);
1307
89a27f4d
GN		 1308 svm->vmcb->save.idtr.limit = dt->size;
1309 svm->vmcb->save.idtr.base = dt->address ;
17a703cb 1310 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1311}
1312
89a27f4d 1313static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1314{
a2fa3e9f
GH		 1315 struct vcpu_svm *svm = to_svm(vcpu);
1316
89a27f4d
GN		 1317 dt->size = svm->vmcb->save.gdtr.limit;
1318 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1319}
1320
89a27f4d 1321static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1322{
a2fa3e9f
GH		 1323 struct vcpu_svm *svm = to_svm(vcpu);
1324
89a27f4d
GN		 1325 svm->vmcb->save.gdtr.limit = dt->size;
1326 svm->vmcb->save.gdtr.base = dt->address ;
17a703cb 1327 mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1328}
1329
e8467fda
AK		 1330static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1331{
1332}
1333
25c4c276 1334static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1335{
1336}
1337
d225157b
AK		 1338static void update_cr0_intercept(struct vcpu_svm *svm)
1339{
1340 ulong gcr0 = svm->vcpu.arch.cr0;
1341 u64 *hcr0 = &svm->vmcb->save.cr0;
1342
1343 if (!svm->vcpu.fpu_active)
1344 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1345 else
1346 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1347 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1348
dcca1a65 1349 mark_dirty(svm->vmcb, VMCB_CR);
d225157b
AK		 1350
1351 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
4ee546b4
RJ		 1352 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1353 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1354 } else {
4ee546b4
RJ		 1355 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1356 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1357 }
1358}
1359
6aa8b732
AK		 1360static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1361{
a2fa3e9f
GH		 1362 struct vcpu_svm *svm = to_svm(vcpu);
1363
2030753d 1364 if (is_guest_mode(vcpu)) {
7f5d8b56
JR		 1365 /*
1366 * We are here because we run in nested mode, the host kvm
1367 * intercepts cr0 writes but the l1 hypervisor does not.
1368 * But the L1 hypervisor may intercept selective cr0 writes.
1369 * This needs to be checked here.
1370 */
1371 unsigned long old, new;
1372
1373 /* Remove bits that would trigger a real cr0 write intercept */
1374 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1375 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1376
1377 if (old == new) {
1378 /* cr0 write with ts and mp unchanged */
1379 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1380 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1381 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1382 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1383 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1384 return;
cda00082 1385 }
7f5d8b56
JR		 1386 }
1387 }
1388
05b3e0c2 1389#ifdef CONFIG_X86_64
f6801dff 1390 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1391 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1392 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1393 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1394 }
1395
d77c26fc 1396 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1397 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1398 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1399 }
1400 }
1401#endif
ad312c7c 1402 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1403
1404 if (!npt_enabled)
1405 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1406
1407 if (!vcpu->fpu_active)
334df50a 1408 cr0 |= X86_CR0_TS;
709ddebf
JR		 1409 /*
1410 * re-enable caching here because the QEMU bios
1411 * does not do it - this results in some delay at
1412 * reboot
1413 */
1414 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1415 svm->vmcb->save.cr0 = cr0;
dcca1a65 1416 mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1417 update_cr0_intercept(svm);
6aa8b732
AK		 1418}
1419
1420static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1421{
6394b649 1422 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1423 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1424
1425 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1426 force_new_asid(vcpu);
6394b649 1427
ec077263
JR		 1428 vcpu->arch.cr4 = cr4;
1429 if (!npt_enabled)
1430 cr4 |= X86_CR4_PAE;
6394b649 1431 cr4 |= host_cr4_mce;
ec077263 1432 to_svm(vcpu)->vmcb->save.cr4 = cr4;
dcca1a65 1433 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
6aa8b732
AK		 1434}
1435
1436static void svm_set_segment(struct kvm_vcpu *vcpu,
1437 struct kvm_segment *var, int seg)
1438{
a2fa3e9f 1439 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1440 struct vmcb_seg *s = svm_seg(vcpu, seg);
1441
1442 s->base = var->base;
1443 s->limit = var->limit;
1444 s->selector = var->selector;
1445 if (var->unusable)
1446 s->attrib = 0;
1447 else {
1448 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1449 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1450 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1451 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1452 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1453 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1454 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1455 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1456 }
1457 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1458 svm->vmcb->save.cpl
1459 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1460 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1461
060d0c9a 1462 mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1463}
1464
44c11430 1465static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1466{
d0bfb940
JK		 1467 struct vcpu_svm *svm = to_svm(vcpu);
1468
18c918c5
JR		 1469 clr_exception_intercept(svm, DB_VECTOR);
1470 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1471
6be7d306 1472 if (svm->nmi_singlestep)
18c918c5 1473 set_exception_intercept(svm, DB_VECTOR);
44c11430 1474
d0bfb940
JK		 1475 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1476 if (vcpu->guest_debug &
1477 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
18c918c5 1478 set_exception_intercept(svm, DB_VECTOR);
d0bfb940 1479 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1480 set_exception_intercept(svm, BP_VECTOR);
d0bfb940
JK		 1481 } else
1482 vcpu->guest_debug = 0;
44c11430
GN		 1483}
1484
355be0b9 1485static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1486{
44c11430
GN		 1487 struct vcpu_svm *svm = to_svm(vcpu);
1488
ae675ef0
JK		 1489 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1490 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1491 else
1492 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1493
72214b96
JR		 1494 mark_dirty(svm->vmcb, VMCB_DR);
1495
355be0b9 1496 update_db_intercept(vcpu);
6aa8b732
AK		 1497}
1498
0fe1e009 1499static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1500{
0fe1e009
TH		 1501 if (sd->next_asid > sd->max_asid) {
1502 ++sd->asid_generation;
1503 sd->next_asid = 1;
a2fa3e9f 1504 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1505 }
1506
0fe1e009
TH		 1507 svm->asid_generation = sd->asid_generation;
1508 svm->vmcb->control.asid = sd->next_asid++;
d48086d1
JR		 1509
1510 mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1511}
1512
020df079 1513static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1514{
42dbaa5a 1515 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1516
020df079 1517 svm->vmcb->save.dr7 = value;
72214b96 1518 mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1519}
1520
851ba692 1521static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1522{
631bc487 1523 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1524 u32 error_code;
631bc487 1525 int r = 1;
6aa8b732 1526
631bc487
GN		 1527 switch (svm->apf_reason) {
1528 default:
1529 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1530
631bc487
GN		 1531 trace_kvm_page_fault(fault_address, error_code);
1532 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1533 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1534 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1535 break;
1536 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1537 svm->apf_reason = 0;
1538 local_irq_disable();
1539 kvm_async_pf_task_wait(fault_address);
1540 local_irq_enable();
1541 break;
1542 case KVM_PV_REASON_PAGE_READY:
1543 svm->apf_reason = 0;
1544 local_irq_disable();
1545 kvm_async_pf_task_wake(fault_address);
1546 local_irq_enable();
1547 break;
1548 }
1549 return r;
6aa8b732
AK		 1550}
1551
851ba692 1552static int db_interception(struct vcpu_svm *svm)
d0bfb940 1553{
851ba692
AK		 1554 struct kvm_run *kvm_run = svm->vcpu.run;
1555
d0bfb940 1556 if (!(svm->vcpu.guest_debug &
44c11430 1557 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1558 !svm->nmi_singlestep) {
d0bfb940
JK		 1559 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1560 return 1;
1561 }
44c11430 1562
6be7d306
JK		 1563 if (svm->nmi_singlestep) {
1564 svm->nmi_singlestep = false;
44c11430
GN		 1565 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1566 svm->vmcb->save.rflags &=
1567 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1568 update_db_intercept(&svm->vcpu);
1569 }
1570
1571 if (svm->vcpu.guest_debug &
e0231715 1572 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1573 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1574 kvm_run->debug.arch.pc =
1575 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1576 kvm_run->debug.arch.exception = DB_VECTOR;
1577 return 0;
1578 }
1579
1580 return 1;
d0bfb940
JK		 1581}
1582
851ba692 1583static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1584{
851ba692
AK		 1585 struct kvm_run *kvm_run = svm->vcpu.run;
1586
d0bfb940
JK		 1587 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1588 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1589 kvm_run->debug.arch.exception = BP_VECTOR;
1590 return 0;
1591}
1592
851ba692 1593static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1594{
1595 int er;
1596
851ba692 1597 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1598 if (er != EMULATE_DONE)
7ee5d940 1599 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1600 return 1;
1601}
1602
6b52d186 1603static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1604{
6b52d186 1605 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7 1606
18c918c5 1607 clr_exception_intercept(svm, NM_VECTOR);
66a562f7 1608
e756fc62 1609 svm->vcpu.fpu_active = 1;
d225157b 1610 update_cr0_intercept(svm);
6b52d186 1611}
a2fa3e9f 1612
6b52d186
AK		 1613static int nm_interception(struct vcpu_svm *svm)
1614{
1615 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1616 return 1;
7807fa6c
AL		 1617}
1618
67ec6607
JR		 1619static bool is_erratum_383(void)
1620{
1621 int err, i;
1622 u64 value;
1623
1624 if (!erratum_383_found)
1625 return false;
1626
1627 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1628 if (err)
1629 return false;
1630
1631 /* Bit 62 may or may not be set for this mce */
1632 value &= ~(1ULL << 62);
1633
1634 if (value != 0xb600000000010015ULL)
1635 return false;
1636
1637 /* Clear MCi_STATUS registers */
1638 for (i = 0; i < 6; ++i)
1639 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1640
1641 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1642 if (!err) {
1643 u32 low, high;
1644
1645 value &= ~(1ULL << 2);
1646 low = lower_32_bits(value);
1647 high = upper_32_bits(value);
1648
1649 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1650 }
1651
1652 /* Flush tlb to evict multi-match entries */
1653 __flush_tlb_all();
1654
1655 return true;
1656}
1657
fe5913e4 1658static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1659{
67ec6607
JR		 1660 if (is_erratum_383()) {
1661 /*
1662 * Erratum 383 triggered. Guest state is corrupt so kill the
1663 * guest.
1664 */
1665 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1666
a8eeb04a 1667 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1668
1669 return;
1670 }
1671
53371b50
JR		 1672 /*
1673 * On an #MC intercept the MCE handler is not called automatically in
1674 * the host. So do it by hand here.
1675 */
1676 asm volatile (
1677 "int $0x12\n");
1678 /* not sure if we ever come back to this point */
1679
fe5913e4
JR		 1680 return;
1681}
1682
1683static int mc_interception(struct vcpu_svm *svm)
1684{
53371b50
JR		 1685 return 1;
1686}
1687
851ba692 1688static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1689{
851ba692
AK		 1690 struct kvm_run *kvm_run = svm->vcpu.run;
1691
46fe4ddd
JR		 1692 /*
1693 * VMCB is undefined after a SHUTDOWN intercept
1694 * so reinitialize it.
1695 */
a2fa3e9f 1696 clear_page(svm->vmcb);
e6101a96 1697 init_vmcb(svm);
46fe4ddd
JR		 1698
1699 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1700 return 0;
1701}
1702
851ba692 1703static int io_interception(struct vcpu_svm *svm)
6aa8b732 1704{
cf8f70bf 1705 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1706 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1707 int size, in, string;
039576c0 1708 unsigned port;
6aa8b732 1709
e756fc62 1710 ++svm->vcpu.stat.io_exits;
e70669ab 1711 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1712 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1713 if (string || in)
6d77dbfc 1714 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1715
039576c0
AK		 1716 port = io_info >> 16;
1717 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1718 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1719 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1720
1721 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1722}
1723
851ba692 1724static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1725{
1726 return 1;
1727}
1728
851ba692 1729static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1730{
1731 ++svm->vcpu.stat.irq_exits;
1732 return 1;
1733}
1734
851ba692 1735static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1736{
1737 return 1;
1738}
1739
851ba692 1740static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1741{
5fdbf976 1742 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1743 skip_emulated_instruction(&svm->vcpu);
1744 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1745}
1746
851ba692 1747static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1748{
5fdbf976 1749 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1750 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1751 kvm_emulate_hypercall(&svm->vcpu);
1752 return 1;
02e235bc
AK		 1753}
1754
5bd2edc3
JR		 1755static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1756{
1757 struct vcpu_svm *svm = to_svm(vcpu);
1758
1759 return svm->nested.nested_cr3;
1760}
1761
1762static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1763 unsigned long root)
1764{
1765 struct vcpu_svm *svm = to_svm(vcpu);
1766
1767 svm->vmcb->control.nested_cr3 = root;
b2747166 1768 mark_dirty(svm->vmcb, VMCB_NPT);
5bd2edc3
JR		 1769 force_new_asid(vcpu);
1770}
1771
6389ee94
AK		 1772static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1773 struct x86_exception *fault)
5bd2edc3
JR		 1774{
1775 struct vcpu_svm *svm = to_svm(vcpu);
1776
1777 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1778 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1779 svm->vmcb->control.exit_info_1 = fault->error_code;
1780 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1781
1782 nested_svm_vmexit(svm);
1783}
1784
4b16184c
JR		 1785static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1786{
1787 int r;
1788
1789 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1790
1791 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1792 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1793 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1794 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1795 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1796
1797 return r;
1798}
1799
1800static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1801{
1802 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1803}
1804
c0725420
AG		 1805static int nested_svm_check_permissions(struct vcpu_svm *svm)
1806{
f6801dff 1807 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1808 || !is_paging(&svm->vcpu)) {
1809 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1810 return 1;
1811 }
1812
1813 if (svm->vmcb->save.cpl) {
1814 kvm_inject_gp(&svm->vcpu, 0);
1815 return 1;
1816 }
1817
1818 return 0;
1819}
1820
cf74a78b
AG		 1821static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1822 bool has_error_code, u32 error_code)
1823{
b8e88bc8
JR		 1824 int vmexit;
1825
2030753d 1826 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1827 return 0;
cf74a78b 1828
0295ad7d
JR		 1829 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1830 svm->vmcb->control.exit_code_hi = 0;
1831 svm->vmcb->control.exit_info_1 = error_code;
1832 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1833
b8e88bc8
JR		 1834 vmexit = nested_svm_intercept(svm);
1835 if (vmexit == NESTED_EXIT_DONE)
1836 svm->nested.exit_required = true;
1837
1838 return vmexit;
cf74a78b
AG		 1839}
1840
8fe54654
JR		 1841/* This function returns true if it is save to enable the irq window */
1842static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1843{
2030753d 1844 if (!is_guest_mode(&svm->vcpu))
8fe54654 1845 return true;
cf74a78b 1846
26666957 1847 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1848 return true;
cf74a78b 1849
26666957 1850 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1851 return false;
cf74a78b 1852
a0a07cd2
GN		 1853 /*
1854 * if vmexit was already requested (by intercepted exception
1855 * for instance) do not overwrite it with "external interrupt"
1856 * vmexit.
1857 */
1858 if (svm->nested.exit_required)
1859 return false;
1860
197717d5
JR		 1861 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1862 svm->vmcb->control.exit_info_1 = 0;
1863 svm->vmcb->control.exit_info_2 = 0;
26666957 1864
cd3ff653
JR		 1865 if (svm->nested.intercept & 1ULL) {
1866 /*
1867 * The #vmexit can't be emulated here directly because this
1868 * code path runs with irqs and preemtion disabled. A
1869 * #vmexit emulation might sleep. Only signal request for
1870 * the #vmexit here.
1871 */
1872 svm->nested.exit_required = true;
236649de 1873 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1874 return false;
cf74a78b
AG		 1875 }
1876
8fe54654 1877 return true;
cf74a78b
AG		 1878}
1879
887f500c
JR		 1880/* This function returns true if it is save to enable the nmi window */
1881static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1882{
2030753d 1883 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1884 return true;
1885
1886 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1887 return true;
1888
1889 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1890 svm->nested.exit_required = true;
1891
1892 return false;
cf74a78b
AG		 1893}
1894
7597f129 1895static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1896{
1897 struct page *page;
1898
6c3bd3d7
JR		 1899 might_sleep();
1900
34f80cfa 1901 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1902 if (is_error_page(page))
1903 goto error;
1904
7597f129
JR		 1905 *_page = page;
1906
1907 return kmap(page);
34f80cfa
JR		 1908
1909error:
1910 kvm_release_page_clean(page);
1911 kvm_inject_gp(&svm->vcpu, 0);
1912
1913 return NULL;
1914}
1915
7597f129 1916static void nested_svm_unmap(struct page *page)
34f80cfa 1917{
7597f129 1918 kunmap(page);
34f80cfa
JR		 1919 kvm_release_page_dirty(page);
1920}
34f80cfa 1921
ce2ac085
JR		 1922static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1923{
1924 unsigned port;
1925 u8 val, bit;
1926 u64 gpa;
34f80cfa 1927
ce2ac085
JR		 1928 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1929 return NESTED_EXIT_HOST;
34f80cfa 1930
ce2ac085
JR		 1931 port = svm->vmcb->control.exit_info_1 >> 16;
1932 gpa = svm->nested.vmcb_iopm + (port / 8);
1933 bit = port % 8;
1934 val = 0;
1935
1936 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1937 val &= (1 << bit);
1938
1939 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1940}
1941
d2477826 1942static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1943{
0d6b3537
JR		 1944 u32 offset, msr, value;
1945 int write, mask;
4c2161ae 1946
3d62d9aa 1947 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1948 return NESTED_EXIT_HOST;
3d62d9aa 1949
0d6b3537
JR		 1950 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1951 offset = svm_msrpm_offset(msr);
1952 write = svm->vmcb->control.exit_info_1 & 1;
1953 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1954
0d6b3537
JR		 1955 if (offset == MSR_INVALID)
1956 return NESTED_EXIT_DONE;
4c2161ae 1957
0d6b3537
JR		 1958 /* Offset is in 32 bit units but need in 8 bit units */
1959 offset *= 4;
4c2161ae 1960
0d6b3537
JR		 1961 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1962 return NESTED_EXIT_DONE;
3d62d9aa 1963
0d6b3537 1964 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1965}
1966
410e4d57 1967static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1968{
cf74a78b 1969 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1970
410e4d57
JR		 1971 switch (exit_code) {
1972 case SVM_EXIT_INTR:
1973 case SVM_EXIT_NMI:
ff47a49b 1974 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1975 return NESTED_EXIT_HOST;
410e4d57 1976 case SVM_EXIT_NPF:
e0231715 1977 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1978 if (npt_enabled)
1979 return NESTED_EXIT_HOST;
1980 break;
410e4d57 1981 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1982 /* When we're shadowing, trap PFs, but not async PF */
1983 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1984 return NESTED_EXIT_HOST;
1985 break;
66a562f7
JR		 1986 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1987 nm_interception(svm);
1988 break;
410e4d57
JR		 1989 default:
1990 break;
cf74a78b
AG		 1991 }
1992
410e4d57
JR		 1993 return NESTED_EXIT_CONTINUE;
1994}
1995
1996/*
1997 * If this function returns true, this #vmexit was already handled
1998 */
b8e88bc8 1999static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 2000{
2001 u32 exit_code = svm->vmcb->control.exit_code;
2002 int vmexit = NESTED_EXIT_HOST;
2003
cf74a78b 2004 switch (exit_code) {
9c4e40b9 2005 case SVM_EXIT_MSR:
3d62d9aa 2006 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 2007 break;
ce2ac085
JR		 2008 case SVM_EXIT_IOIO:
2009 vmexit = nested_svm_intercept_ioio(svm);
2010 break;
4ee546b4
RJ		 2011 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2012 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2013 if (svm->nested.intercept_cr & bit)
410e4d57 2014 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2015 break;
2016 }
3aed041a
JR		 2017 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2018 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2019 if (svm->nested.intercept_dr & bit)
410e4d57 2020 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2021 break;
2022 }
2023 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2024 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 2025 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 2026 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 2027 /* async page fault always cause vmexit */
2028 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2029 svm->apf_reason != 0)
2030 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2031 break;
2032 }
228070b1
JR		 2033 case SVM_EXIT_ERR: {
2034 vmexit = NESTED_EXIT_DONE;
2035 break;
2036 }
cf74a78b
AG		 2037 default: {
2038 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 2039 if (svm->nested.intercept & exit_bits)
410e4d57 2040 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 2041 }
2042 }
2043
b8e88bc8
JR		 2044 return vmexit;
2045}
2046
2047static int nested_svm_exit_handled(struct vcpu_svm *svm)
2048{
2049 int vmexit;
2050
2051 vmexit = nested_svm_intercept(svm);
2052
2053 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 2054 nested_svm_vmexit(svm);
9c4e40b9
JR		 2055
2056 return vmexit;
cf74a78b
AG		 2057}
2058
0460a979
JR		 2059static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2060{
2061 struct vmcb_control_area *dst = &dst_vmcb->control;
2062 struct vmcb_control_area *from = &from_vmcb->control;
2063
4ee546b4 2064 dst->intercept_cr = from->intercept_cr;
3aed041a 2065 dst->intercept_dr = from->intercept_dr;
0460a979
JR		 2066 dst->intercept_exceptions = from->intercept_exceptions;
2067 dst->intercept = from->intercept;
2068 dst->iopm_base_pa = from->iopm_base_pa;
2069 dst->msrpm_base_pa = from->msrpm_base_pa;
2070 dst->tsc_offset = from->tsc_offset;
2071 dst->asid = from->asid;
2072 dst->tlb_ctl = from->tlb_ctl;
2073 dst->int_ctl = from->int_ctl;
2074 dst->int_vector = from->int_vector;
2075 dst->int_state = from->int_state;
2076 dst->exit_code = from->exit_code;
2077 dst->exit_code_hi = from->exit_code_hi;
2078 dst->exit_info_1 = from->exit_info_1;
2079 dst->exit_info_2 = from->exit_info_2;
2080 dst->exit_int_info = from->exit_int_info;
2081 dst->exit_int_info_err = from->exit_int_info_err;
2082 dst->nested_ctl = from->nested_ctl;
2083 dst->event_inj = from->event_inj;
2084 dst->event_inj_err = from->event_inj_err;
2085 dst->nested_cr3 = from->nested_cr3;
2086 dst->lbr_ctl = from->lbr_ctl;
2087}
2088
34f80cfa 2089static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 2090{
34f80cfa 2091 struct vmcb *nested_vmcb;
e6aa9abd 2092 struct vmcb *hsave = svm->nested.hsave;
33740e40 2093 struct vmcb *vmcb = svm->vmcb;
7597f129 2094 struct page *page;
cf74a78b 2095
17897f36
JR		 2096 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2097 vmcb->control.exit_info_1,
2098 vmcb->control.exit_info_2,
2099 vmcb->control.exit_int_info,
2100 vmcb->control.exit_int_info_err);
2101
7597f129 2102 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2103 if (!nested_vmcb)
2104 return 1;
2105
2030753d
JR		 2106 /* Exit Guest-Mode */
2107 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 2108 svm->nested.vmcb = 0;
2109
cf74a78b 2110 /* Give the current vmcb to the guest */
33740e40
JR		 2111 disable_gif(svm);
2112
2113 nested_vmcb->save.es = vmcb->save.es;
2114 nested_vmcb->save.cs = vmcb->save.cs;
2115 nested_vmcb->save.ss = vmcb->save.ss;
2116 nested_vmcb->save.ds = vmcb->save.ds;
2117 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2118 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2119 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2120 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2121 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2122 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2123 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2124 nested_vmcb->save.rflags = vmcb->save.rflags;
2125 nested_vmcb->save.rip = vmcb->save.rip;
2126 nested_vmcb->save.rsp = vmcb->save.rsp;
2127 nested_vmcb->save.rax = vmcb->save.rax;
2128 nested_vmcb->save.dr7 = vmcb->save.dr7;
2129 nested_vmcb->save.dr6 = vmcb->save.dr6;
2130 nested_vmcb->save.cpl = vmcb->save.cpl;
2131
2132 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2133 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2134 nested_vmcb->control.int_state = vmcb->control.int_state;
2135 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2136 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2137 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2138 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2139 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2140 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2141 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2142
2143 /*
2144 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2145 * to make sure that we do not lose injected events. So check event_inj
2146 * here and copy it to exit_int_info if it is valid.
2147 * Exit_int_info and event_inj can't be both valid because the case
2148 * below only happens on a VMRUN instruction intercept which has
2149 * no valid exit_int_info set.
2150 */
2151 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2152 struct vmcb_control_area *nc = &nested_vmcb->control;
2153
2154 nc->exit_int_info = vmcb->control.event_inj;
2155 nc->exit_int_info_err = vmcb->control.event_inj_err;
2156 }
2157
33740e40
JR		 2158 nested_vmcb->control.tlb_ctl = 0;
2159 nested_vmcb->control.event_inj = 0;
2160 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2161
2162 /* We always set V_INTR_MASKING and remember the old value in hflags */
2163 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2164 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2165
cf74a78b 2166 /* Restore the original control entries */
0460a979 2167 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2168
219b65dc
AG		 2169 kvm_clear_exception_queue(&svm->vcpu);
2170 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2171
4b16184c
JR		 2172 svm->nested.nested_cr3 = 0;
2173
cf74a78b
AG		 2174 /* Restore selected save entries */
2175 svm->vmcb->save.es = hsave->save.es;
2176 svm->vmcb->save.cs = hsave->save.cs;
2177 svm->vmcb->save.ss = hsave->save.ss;
2178 svm->vmcb->save.ds = hsave->save.ds;
2179 svm->vmcb->save.gdtr = hsave->save.gdtr;
2180 svm->vmcb->save.idtr = hsave->save.idtr;
2181 svm->vmcb->save.rflags = hsave->save.rflags;
2182 svm_set_efer(&svm->vcpu, hsave->save.efer);
2183 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2184 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2185 if (npt_enabled) {
2186 svm->vmcb->save.cr3 = hsave->save.cr3;
2187 svm->vcpu.arch.cr3 = hsave->save.cr3;
2188 } else {
2390218b 2189 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2190 }
2191 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2192 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2193 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2194 svm->vmcb->save.dr7 = 0;
2195 svm->vmcb->save.cpl = 0;
2196 svm->vmcb->control.exit_int_info = 0;
2197
8d28fec4
RJ		 2198 mark_all_dirty(svm->vmcb);
2199
7597f129 2200 nested_svm_unmap(page);
cf74a78b 2201
4b16184c 2202 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2203 kvm_mmu_reset_context(&svm->vcpu);
2204 kvm_mmu_load(&svm->vcpu);
2205
2206 return 0;
2207}
3d6368ef 2208
9738b2c9 2209static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2210{
323c3d80
JR		 2211 /*
2212 * This function merges the msr permission bitmaps of kvm and the
2213 * nested vmcb. It is omptimized in that it only merges the parts where
2214 * the kvm msr permission bitmap may contain zero bits
2215 */
3d6368ef 2216 int i;
9738b2c9 2217
323c3d80
JR		 2218 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2219 return true;
9738b2c9 2220
323c3d80
JR		 2221 for (i = 0; i < MSRPM_OFFSETS; i++) {
2222 u32 value, p;
2223 u64 offset;
9738b2c9 2224
323c3d80
JR		 2225 if (msrpm_offsets[i] == 0xffffffff)
2226 break;
3d6368ef 2227
0d6b3537
JR		 2228 p = msrpm_offsets[i];
2229 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2230
2231 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2232 return false;
2233
2234 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2235 }
3d6368ef 2236
323c3d80 2237 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2238
2239 return true;
3d6368ef
AG		 2240}
2241
52c65a30
JR		 2242static bool nested_vmcb_checks(struct vmcb *vmcb)
2243{
2244 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2245 return false;
2246
dbe77584
JR		 2247 if (vmcb->control.asid == 0)
2248 return false;
2249
4b16184c
JR		 2250 if (vmcb->control.nested_ctl && !npt_enabled)
2251 return false;
2252
52c65a30
JR		 2253 return true;
2254}
2255
9738b2c9 2256static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2257{
9738b2c9 2258 struct vmcb *nested_vmcb;
e6aa9abd 2259 struct vmcb *hsave = svm->nested.hsave;
defbba56 2260 struct vmcb *vmcb = svm->vmcb;
7597f129 2261 struct page *page;
06fc7772 2262 u64 vmcb_gpa;
3d6368ef 2263
06fc7772 2264 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2265
7597f129 2266 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2267 if (!nested_vmcb)
2268 return false;
2269
52c65a30
JR		 2270 if (!nested_vmcb_checks(nested_vmcb)) {
2271 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2272 nested_vmcb->control.exit_code_hi = 0;
2273 nested_vmcb->control.exit_info_1 = 0;
2274 nested_vmcb->control.exit_info_2 = 0;
2275
2276 nested_svm_unmap(page);
2277
2278 return false;
2279 }
2280
b75f4eb3 2281 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2282 nested_vmcb->save.rip,
2283 nested_vmcb->control.int_ctl,
2284 nested_vmcb->control.event_inj,
2285 nested_vmcb->control.nested_ctl);
2286
4ee546b4
RJ		 2287 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2288 nested_vmcb->control.intercept_cr >> 16,
2e554e8d
JR		 2289 nested_vmcb->control.intercept_exceptions,
2290 nested_vmcb->control.intercept);
2291
3d6368ef 2292 /* Clear internal status */
219b65dc
AG		 2293 kvm_clear_exception_queue(&svm->vcpu);
2294 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2295
e0231715
JR		 2296 /*
2297 * Save the old vmcb, so we don't need to pick what we save, but can
2298 * restore everything when a VMEXIT occurs
2299 */
defbba56
JR		 2300 hsave->save.es = vmcb->save.es;
2301 hsave->save.cs = vmcb->save.cs;
2302 hsave->save.ss = vmcb->save.ss;
2303 hsave->save.ds = vmcb->save.ds;
2304 hsave->save.gdtr = vmcb->save.gdtr;
2305 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2306 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2307 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2308 hsave->save.cr4 = svm->vcpu.arch.cr4;
2309 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2310 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2311 hsave->save.rsp = vmcb->save.rsp;
2312 hsave->save.rax = vmcb->save.rax;
2313 if (npt_enabled)
2314 hsave->save.cr3 = vmcb->save.cr3;
2315 else
2316 hsave->save.cr3 = svm->vcpu.arch.cr3;
2317
0460a979 2318 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2319
2320 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2321 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2322 else
2323 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2324
4b16184c
JR		 2325 if (nested_vmcb->control.nested_ctl) {
2326 kvm_mmu_unload(&svm->vcpu);
2327 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2328 nested_svm_init_mmu_context(&svm->vcpu);
2329 }
2330
3d6368ef
AG		 2331 /* Load the nested guest state */
2332 svm->vmcb->save.es = nested_vmcb->save.es;
2333 svm->vmcb->save.cs = nested_vmcb->save.cs;
2334 svm->vmcb->save.ss = nested_vmcb->save.ss;
2335 svm->vmcb->save.ds = nested_vmcb->save.ds;
2336 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2337 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2338 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2339 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2340 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2341 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2342 if (npt_enabled) {
2343 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2344 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2345 } else
2390218b 2346 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2347
2348 /* Guest paging mode is active - reset mmu */
2349 kvm_mmu_reset_context(&svm->vcpu);
2350
defbba56 2351 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2352 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2353 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2354 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2355
3d6368ef
AG		 2356 /* In case we don't even reach vcpu_run, the fields are not updated */
2357 svm->vmcb->save.rax = nested_vmcb->save.rax;
2358 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2359 svm->vmcb->save.rip = nested_vmcb->save.rip;
2360 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2361 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2362 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2363
f7138538 2364 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2365 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2366
aad42c64 2367 /* cache intercepts */
4ee546b4 2368 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3aed041a 2369 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
aad42c64
JR		 2370 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2371 svm->nested.intercept = nested_vmcb->control.intercept;
2372
3d6368ef 2373 force_new_asid(&svm->vcpu);
3d6368ef 2374 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2375 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2376 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2377 else
2378 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2379
88ab24ad
JR		 2380 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2381 /* We only want the cr8 intercept bits of the guest */
4ee546b4
RJ		 2382 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2383 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
88ab24ad
JR		 2384 }
2385
0d945bd9 2386 /* We don't want to see VMMCALLs from a nested guest */
8a05a1b8 2387 clr_intercept(svm, INTERCEPT_VMMCALL);
0d945bd9 2388
88ab24ad 2389 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2390 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2391 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2392 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2393 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2394 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2395
7597f129 2396 nested_svm_unmap(page);
9738b2c9 2397
2030753d
JR		 2398 /* Enter Guest-Mode */
2399 enter_guest_mode(&svm->vcpu);
2400
384c6368
JR		 2401 /*
2402 * Merge guest and host intercepts - must be called with vcpu in
2403 * guest-mode to take affect here
2404 */
2405 recalc_intercepts(svm);
2406
06fc7772 2407 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2408
2af9194d 2409 enable_gif(svm);
3d6368ef 2410
8d28fec4
RJ		 2411 mark_all_dirty(svm->vmcb);
2412
9738b2c9 2413 return true;
3d6368ef
AG		 2414}
2415
9966bf68 2416static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2417{
2418 to_vmcb->save.fs = from_vmcb->save.fs;
2419 to_vmcb->save.gs = from_vmcb->save.gs;
2420 to_vmcb->save.tr = from_vmcb->save.tr;
2421 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2422 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2423 to_vmcb->save.star = from_vmcb->save.star;
2424 to_vmcb->save.lstar = from_vmcb->save.lstar;
2425 to_vmcb->save.cstar = from_vmcb->save.cstar;
2426 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2427 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2428 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2429 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2430}
2431
851ba692 2432static int vmload_interception(struct vcpu_svm *svm)
5542675b 2433{
9966bf68 2434 struct vmcb *nested_vmcb;
7597f129 2435 struct page *page;
9966bf68 2436
5542675b
AG		 2437 if (nested_svm_check_permissions(svm))
2438 return 1;
2439
2440 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2441 skip_emulated_instruction(&svm->vcpu);
2442
7597f129 2443 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2444 if (!nested_vmcb)
2445 return 1;
2446
2447 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2448 nested_svm_unmap(page);
5542675b
AG		 2449
2450 return 1;
2451}
2452
851ba692 2453static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2454{
9966bf68 2455 struct vmcb *nested_vmcb;
7597f129 2456 struct page *page;
9966bf68 2457
5542675b
AG		 2458 if (nested_svm_check_permissions(svm))
2459 return 1;
2460
2461 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2462 skip_emulated_instruction(&svm->vcpu);
2463
7597f129 2464 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2465 if (!nested_vmcb)
2466 return 1;
2467
2468 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2469 nested_svm_unmap(page);
5542675b
AG		 2470
2471 return 1;
2472}
2473
851ba692 2474static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2475{
3d6368ef
AG		 2476 if (nested_svm_check_permissions(svm))
2477 return 1;
2478
b75f4eb3
RJ		 2479 /* Save rip after vmrun instruction */
2480 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2481
9738b2c9 2482 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2483 return 1;
2484
9738b2c9 2485 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2486 goto failed;
2487
2488 return 1;
2489
2490failed:
2491
2492 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2493 svm->vmcb->control.exit_code_hi = 0;
2494 svm->vmcb->control.exit_info_1 = 0;
2495 svm->vmcb->control.exit_info_2 = 0;
2496
2497 nested_svm_vmexit(svm);
3d6368ef
AG		 2498
2499 return 1;
2500}
2501
851ba692 2502static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2503{
2504 if (nested_svm_check_permissions(svm))
2505 return 1;
2506
2507 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2508 skip_emulated_instruction(&svm->vcpu);
3842d135 2509 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2510
2af9194d 2511 enable_gif(svm);
1371d904
AG		 2512
2513 return 1;
2514}
2515
851ba692 2516static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2517{
2518 if (nested_svm_check_permissions(svm))
2519 return 1;
2520
2521 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2522 skip_emulated_instruction(&svm->vcpu);
2523
2af9194d 2524 disable_gif(svm);
1371d904
AG		 2525
2526 /* After a CLGI no interrupts should come */
2527 svm_clear_vintr(svm);
2528 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2529
decdbf6a
JR		 2530 mark_dirty(svm->vmcb, VMCB_INTR);
2531
1371d904
AG		 2532 return 1;
2533}
2534
851ba692 2535static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2536{
2537 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2538
ec1ff790
JR		 2539 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2540 vcpu->arch.regs[VCPU_REGS_RAX]);
2541
ff092385
AG		 2542 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2543 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2544
2545 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2546 skip_emulated_instruction(&svm->vcpu);
2547 return 1;
2548}
2549
532a46b9
JR		 2550static int skinit_interception(struct vcpu_svm *svm)
2551{
2552 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2553
2554 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2555 return 1;
2556}
2557
851ba692 2558static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2559{
7ee5d940 2560 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2561 return 1;
2562}
2563
851ba692 2564static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2565{
37817f29 2566 u16 tss_selector;
64a7ec06
GN		 2567 int reason;
2568 int int_type = svm->vmcb->control.exit_int_info &
2569 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2570 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2571 uint32_t type =
2572 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2573 uint32_t idt_v =
2574 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2575 bool has_error_code = false;
2576 u32 error_code = 0;
37817f29
IE		 2577
2578 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2579
37817f29
IE		 2580 if (svm->vmcb->control.exit_info_2 &
2581 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2582 reason = TASK_SWITCH_IRET;
2583 else if (svm->vmcb->control.exit_info_2 &
2584 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2585 reason = TASK_SWITCH_JMP;
fe8e7f83 2586 else if (idt_v)
64a7ec06
GN		 2587 reason = TASK_SWITCH_GATE;
2588 else
2589 reason = TASK_SWITCH_CALL;
2590
fe8e7f83
GN		 2591 if (reason == TASK_SWITCH_GATE) {
2592 switch (type) {
2593 case SVM_EXITINTINFO_TYPE_NMI:
2594 svm->vcpu.arch.nmi_injected = false;
2595 break;
2596 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2597 if (svm->vmcb->control.exit_info_2 &
2598 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2599 has_error_code = true;
2600 error_code =
2601 (u32)svm->vmcb->control.exit_info_2;
2602 }
fe8e7f83
GN		 2603 kvm_clear_exception_queue(&svm->vcpu);
2604 break;
2605 case SVM_EXITINTINFO_TYPE_INTR:
2606 kvm_clear_interrupt_queue(&svm->vcpu);
2607 break;
2608 default:
2609 break;
2610 }
2611 }
64a7ec06 2612
8317c298
GN		 2613 if (reason != TASK_SWITCH_GATE ||
2614 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2615 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2616 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2617 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2618
acb54517
GN		 2619 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2620 has_error_code, error_code) == EMULATE_FAIL) {
2621 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2622 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2623 svm->vcpu.run->internal.ndata = 0;
2624 return 0;
2625 }
2626 return 1;
6aa8b732
AK		 2627}
2628
851ba692 2629static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2630{
5fdbf976 2631 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2632 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2633 return 1;
6aa8b732
AK		 2634}
2635
851ba692 2636static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2637{
2638 ++svm->vcpu.stat.nmi_window_exits;
8a05a1b8 2639 clr_intercept(svm, INTERCEPT_IRET);
44c11430 2640 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2641 return 1;
2642}
2643
851ba692 2644static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2645{
6d77dbfc 2646 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2647}
2648
851ba692 2649static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2650{
6d77dbfc 2651 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2652}
2653
cda00082
JR		 2654static int cr0_write_interception(struct vcpu_svm *svm)
2655{
2656 struct kvm_vcpu *vcpu = &svm->vcpu;
2657 int r;
2658
2659 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2660
2661 if (svm->nested.vmexit_rip) {
2662 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2663 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2664 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2665 svm->nested.vmexit_rip = 0;
2666 }
2667
2668 return r == EMULATE_DONE;
2669}
2670
851ba692 2671static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2672{
851ba692
AK		 2673 struct kvm_run *kvm_run = svm->vcpu.run;
2674
0a5fff19
GN		 2675 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2676 /* instruction emulation calls kvm_set_cr8() */
851ba692 2677 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273 2678 if (irqchip_in_kernel(svm->vcpu.kvm)) {
4ee546b4 2679 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1d075434 2680 return 1;
95ba8273 2681 }
0a5fff19
GN		 2682 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2683 return 1;
1d075434
JR		 2684 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2685 return 0;
2686}
2687
6aa8b732
AK		 2688static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2689{
a2fa3e9f
GH		 2690 struct vcpu_svm *svm = to_svm(vcpu);
2691
6aa8b732 2692 switch (ecx) {
af24a4e4 2693 case MSR_IA32_TSC: {
4cc70310 2694 struct vmcb *vmcb = get_host_vmcb(svm);
6aa8b732 2695
4cc70310 2696 *data = vmcb->control.tsc_offset + native_read_tsc();
6aa8b732
AK		 2697 break;
2698 }
8c06585d 2699 case MSR_STAR:
a2fa3e9f 2700 *data = svm->vmcb->save.star;
6aa8b732 2701 break;
0e859cac 2702#ifdef CONFIG_X86_64
6aa8b732 2703 case MSR_LSTAR:
a2fa3e9f 2704 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2705 break;
2706 case MSR_CSTAR:
a2fa3e9f 2707 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2708 break;
2709 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2710 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2711 break;
2712 case MSR_SYSCALL_MASK:
a2fa3e9f 2713 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2714 break;
2715#endif
2716 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2717 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2718 break;
2719 case MSR_IA32_SYSENTER_EIP:
017cb99e 2720 *data = svm->sysenter_eip;
6aa8b732
AK		 2721 break;
2722 case MSR_IA32_SYSENTER_ESP:
017cb99e 2723 *data = svm->sysenter_esp;
6aa8b732 2724 break;
e0231715
JR		 2725 /*
2726 * Nobody will change the following 5 values in the VMCB so we can
2727 * safely return them on rdmsr. They will always be 0 until LBRV is
2728 * implemented.
2729 */
a2938c80
JR		 2730 case MSR_IA32_DEBUGCTLMSR:
2731 *data = svm->vmcb->save.dbgctl;
2732 break;
2733 case MSR_IA32_LASTBRANCHFROMIP:
2734 *data = svm->vmcb->save.br_from;
2735 break;
2736 case MSR_IA32_LASTBRANCHTOIP:
2737 *data = svm->vmcb->save.br_to;
2738 break;
2739 case MSR_IA32_LASTINTFROMIP:
2740 *data = svm->vmcb->save.last_excp_from;
2741 break;
2742 case MSR_IA32_LASTINTTOIP:
2743 *data = svm->vmcb->save.last_excp_to;
2744 break;
b286d5d8 2745 case MSR_VM_HSAVE_PA:
e6aa9abd 2746 *data = svm->nested.hsave_msr;
b286d5d8 2747 break;
eb6f302e 2748 case MSR_VM_CR:
4a810181 2749 *data = svm->nested.vm_cr_msr;
eb6f302e 2750 break;
c8a73f18
AG		 2751 case MSR_IA32_UCODE_REV:
2752 *data = 0x01000065;
2753 break;
6aa8b732 2754 default:
3bab1f5d 2755 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2756 }
2757 return 0;
2758}
2759
851ba692 2760static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2761{
ad312c7c 2762 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2763 u64 data;
2764
59200273
AK		 2765 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2766 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2767 kvm_inject_gp(&svm->vcpu, 0);
59200273 2768 } else {
229456fc 2769 trace_kvm_msr_read(ecx, data);
af9ca2d7 2770
5fdbf976 2771 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2772 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2773 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2774 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2775 }
2776 return 1;
2777}
2778
4a810181
JR		 2779static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2780{
2781 struct vcpu_svm *svm = to_svm(vcpu);
2782 int svm_dis, chg_mask;
2783
2784 if (data & ~SVM_VM_CR_VALID_MASK)
2785 return 1;
2786
2787 chg_mask = SVM_VM_CR_VALID_MASK;
2788
2789 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2790 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2791
2792 svm->nested.vm_cr_msr &= ~chg_mask;
2793 svm->nested.vm_cr_msr |= (data & chg_mask);
2794
2795 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2796
2797 /* check for svm_disable while efer.svme is set */
2798 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2799 return 1;
2800
2801 return 0;
2802}
2803
6aa8b732
AK		 2804static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2805{
a2fa3e9f
GH		 2806 struct vcpu_svm *svm = to_svm(vcpu);
2807
6aa8b732 2808 switch (ecx) {
f4e1b3c8 2809 case MSR_IA32_TSC:
99e3e30a 2810 kvm_write_tsc(vcpu, data);
6aa8b732 2811 break;
8c06585d 2812 case MSR_STAR:
a2fa3e9f 2813 svm->vmcb->save.star = data;
6aa8b732 2814 break;
49b14f24 2815#ifdef CONFIG_X86_64
6aa8b732 2816 case MSR_LSTAR:
a2fa3e9f 2817 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2818 break;
2819 case MSR_CSTAR:
a2fa3e9f 2820 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2821 break;
2822 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2823 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2824 break;
2825 case MSR_SYSCALL_MASK:
a2fa3e9f 2826 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2827 break;
2828#endif
2829 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2830 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2831 break;
2832 case MSR_IA32_SYSENTER_EIP:
017cb99e 2833 svm->sysenter_eip = data;
a2fa3e9f 2834 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2835 break;
2836 case MSR_IA32_SYSENTER_ESP:
017cb99e 2837 svm->sysenter_esp = data;
a2fa3e9f 2838 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2839 break;
a2938c80 2840 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2841 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 2842 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2843 __func__, data);
24e09cbf
JR		 2844 break;
2845 }
2846 if (data & DEBUGCTL_RESERVED_BITS)
2847 return 1;
2848
2849 svm->vmcb->save.dbgctl = data;
2850 if (data & (1ULL<<0))
2851 svm_enable_lbrv(svm);
2852 else
2853 svm_disable_lbrv(svm);
a2938c80 2854 break;
b286d5d8 2855 case MSR_VM_HSAVE_PA:
e6aa9abd 2856 svm->nested.hsave_msr = data;
62b9abaa 2857 break;
3c5d0a44 2858 case MSR_VM_CR:
4a810181 2859 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2860 case MSR_VM_IGNNE:
3c5d0a44
AG		 2861 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2862 break;
6aa8b732 2863 default:
3bab1f5d 2864 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2865 }
2866 return 0;
2867}
2868
851ba692 2869static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2870{
ad312c7c 2871 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2872 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2873 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2874
af9ca2d7 2875
5fdbf976 2876 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2877 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2878 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2879 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2880 } else {
2881 trace_kvm_msr_write(ecx, data);
e756fc62 2882 skip_emulated_instruction(&svm->vcpu);
59200273 2883 }
6aa8b732
AK		 2884 return 1;
2885}
2886
851ba692 2887static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2888{
e756fc62 2889 if (svm->vmcb->control.exit_info_1)
851ba692 2890 return wrmsr_interception(svm);
6aa8b732 2891 else
851ba692 2892 return rdmsr_interception(svm);
6aa8b732
AK		 2893}
2894
851ba692 2895static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2896{
851ba692
AK		 2897 struct kvm_run *kvm_run = svm->vcpu.run;
2898
3842d135 2899 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2900 svm_clear_vintr(svm);
85f455f7 2901 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
decdbf6a 2902 mark_dirty(svm->vmcb, VMCB_INTR);
c1150d8c
DL		 2903 /*
2904 * If the user space waits to inject interrupts, exit as soon as
2905 * possible
2906 */
8061823a
GN		 2907 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2908 kvm_run->request_interrupt_window &&
2909 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2910 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2911 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2912 return 0;
2913 }
2914
2915 return 1;
2916}
2917
565d0998
ML		 2918static int pause_interception(struct vcpu_svm *svm)
2919{
2920 kvm_vcpu_on_spin(&(svm->vcpu));
2921 return 1;
2922}
2923
851ba692 2924static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2925 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2926 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2927 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2928 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2929 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2930 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2931 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2932 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2933 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2934 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2935 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2936 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2937 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2938 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2939 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2940 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2941 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2942 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2943 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2944 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2945 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2946 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2947 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2948 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2949 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2950 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2951 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2952 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2953 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2954 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2955 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2956 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2957 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2958 [SVM_EXIT_SMI] = nop_on_interception,
2959 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2960 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2961 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2962 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2963 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2964 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2965 [SVM_EXIT_HLT] = halt_interception,
a7052897 2966 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2967 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2968 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2969 [SVM_EXIT_MSR] = msr_interception,
2970 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2971 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2972 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2973 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2974 [SVM_EXIT_VMLOAD] = vmload_interception,
2975 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2976 [SVM_EXIT_STGI] = stgi_interception,
2977 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2978 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2979 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2980 [SVM_EXIT_MONITOR] = invalid_op_interception,
2981 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2982 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2983};
2984
3f10c846
JR		 2985void dump_vmcb(struct kvm_vcpu *vcpu)
2986{
2987 struct vcpu_svm *svm = to_svm(vcpu);
2988 struct vmcb_control_area *control = &svm->vmcb->control;
2989 struct vmcb_save_area *save = &svm->vmcb->save;
2990
2991 pr_err("VMCB Control Area:\n");
4ee546b4
RJ		 2992 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
2993 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
3aed041a
JR		 2994 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
2995 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
3f10c846
JR		 2996 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2997 pr_err("intercepts: %016llx\n", control->intercept);
2998 pr_err("pause filter count: %d\n", control->pause_filter_count);
2999 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
3000 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
3001 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
3002 pr_err("asid: %d\n", control->asid);
3003 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
3004 pr_err("int_ctl: %08x\n", control->int_ctl);
3005 pr_err("int_vector: %08x\n", control->int_vector);
3006 pr_err("int_state: %08x\n", control->int_state);
3007 pr_err("exit_code: %08x\n", control->exit_code);
3008 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3009 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3010 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3011 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3012 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3013 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3014 pr_err("event_inj: %08x\n", control->event_inj);
3015 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3016 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3017 pr_err("next_rip: %016llx\n", control->next_rip);
3018 pr_err("VMCB State Save Area:\n");
3019 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3020 save->es.selector, save->es.attrib,
3021 save->es.limit, save->es.base);
3022 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3023 save->cs.selector, save->cs.attrib,
3024 save->cs.limit, save->cs.base);
3025 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3026 save->ss.selector, save->ss.attrib,
3027 save->ss.limit, save->ss.base);
3028 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3029 save->ds.selector, save->ds.attrib,
3030 save->ds.limit, save->ds.base);
3031 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3032 save->fs.selector, save->fs.attrib,
3033 save->fs.limit, save->fs.base);
3034 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3035 save->gs.selector, save->gs.attrib,
3036 save->gs.limit, save->gs.base);
3037 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3038 save->gdtr.selector, save->gdtr.attrib,
3039 save->gdtr.limit, save->gdtr.base);
3040 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3041 save->ldtr.selector, save->ldtr.attrib,
3042 save->ldtr.limit, save->ldtr.base);
3043 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3044 save->idtr.selector, save->idtr.attrib,
3045 save->idtr.limit, save->idtr.base);
3046 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3047 save->tr.selector, save->tr.attrib,
3048 save->tr.limit, save->tr.base);
3049 pr_err("cpl: %d efer: %016llx\n",
3050 save->cpl, save->efer);
3051 pr_err("cr0: %016llx cr2: %016llx\n",
3052 save->cr0, save->cr2);
3053 pr_err("cr3: %016llx cr4: %016llx\n",
3054 save->cr3, save->cr4);
3055 pr_err("dr6: %016llx dr7: %016llx\n",
3056 save->dr6, save->dr7);
3057 pr_err("rip: %016llx rflags: %016llx\n",
3058 save->rip, save->rflags);
3059 pr_err("rsp: %016llx rax: %016llx\n",
3060 save->rsp, save->rax);
3061 pr_err("star: %016llx lstar: %016llx\n",
3062 save->star, save->lstar);
3063 pr_err("cstar: %016llx sfmask: %016llx\n",
3064 save->cstar, save->sfmask);
3065 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3066 save->kernel_gs_base, save->sysenter_cs);
3067 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3068 save->sysenter_esp, save->sysenter_eip);
3069 pr_err("gpat: %016llx dbgctl: %016llx\n",
3070 save->g_pat, save->dbgctl);
3071 pr_err("br_from: %016llx br_to: %016llx\n",
3072 save->br_from, save->br_to);
3073 pr_err("excp_from: %016llx excp_to: %016llx\n",
3074 save->last_excp_from, save->last_excp_to);
3075
3076}
3077
586f9607
AK		 3078static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3079{
3080 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3081
3082 *info1 = control->exit_info_1;
3083 *info2 = control->exit_info_2;
3084}
3085
851ba692 3086static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3087{
04d2cc77 3088 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3089 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3090 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3091
aa17911e 3092 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
af9ca2d7 3093
4ee546b4 3094 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2be4fc7a
JR		 3095 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3096 if (npt_enabled)
3097 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3098
cd3ff653
JR		 3099 if (unlikely(svm->nested.exit_required)) {
3100 nested_svm_vmexit(svm);
3101 svm->nested.exit_required = false;
3102
3103 return 1;
3104 }
3105
2030753d 3106 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3107 int vmexit;
3108
d8cabddf
JR		 3109 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3110 svm->vmcb->control.exit_info_1,
3111 svm->vmcb->control.exit_info_2,
3112 svm->vmcb->control.exit_int_info,
3113 svm->vmcb->control.exit_int_info_err);
3114
410e4d57
JR		 3115 vmexit = nested_svm_exit_special(svm);
3116
3117 if (vmexit == NESTED_EXIT_CONTINUE)
3118 vmexit = nested_svm_exit_handled(svm);
3119
3120 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3121 return 1;
cf74a78b
AG		 3122 }
3123
a5c3832d
JR		 3124 svm_complete_interrupts(svm);
3125
04d2cc77
AK		 3126 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3127 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3128 kvm_run->fail_entry.hardware_entry_failure_reason
3129 = svm->vmcb->control.exit_code;
3f10c846
JR		 3130 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3131 dump_vmcb(vcpu);
04d2cc77
AK		 3132 return 0;
3133 }
3134
a2fa3e9f 3135 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3136 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3137 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3138 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3139 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3140 "exit_code 0x%x\n",
b8688d51 3141 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3142 exit_code);
3143
9d8f549d 3144 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3145 || !svm_exit_handlers[exit_code]) {
6aa8b732 3146 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3147 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3148 return 0;
3149 }
3150
851ba692 3151 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3152}
3153
3154static void reload_tss(struct kvm_vcpu *vcpu)
3155{
3156 int cpu = raw_smp_processor_id();
3157
0fe1e009
TH		 3158 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3159 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3160 load_TR_desc();
3161}
3162
e756fc62 3163static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3164{
3165 int cpu = raw_smp_processor_id();
3166
0fe1e009 3167 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3168
a2fa3e9f 3169 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3170 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3171 if (svm->asid_generation != sd->asid_generation)
3172 new_asid(svm, sd);
6aa8b732
AK		 3173}
3174
95ba8273
GN		 3175static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3176{
3177 struct vcpu_svm *svm = to_svm(vcpu);
3178
3179 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3180 vcpu->arch.hflags |= HF_NMI_MASK;
8a05a1b8 3181 set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3182 ++vcpu->stat.nmi_injections;
3183}
6aa8b732 3184
85f455f7 3185static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3186{
3187 struct vmcb_control_area *control;
3188
e756fc62 3189 control = &svm->vmcb->control;
85f455f7 3190 control->int_vector = irq;
6aa8b732
AK		 3191 control->int_ctl &= ~V_INTR_PRIO_MASK;
3192 control->int_ctl |= V_IRQ_MASK |
3193 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
decdbf6a 3194 mark_dirty(svm->vmcb, VMCB_INTR);
6aa8b732
AK		 3195}
3196
66fd3f7f 3197static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3198{
3199 struct vcpu_svm *svm = to_svm(vcpu);
3200
2af9194d 3201 BUG_ON(!(gif_set(svm)));
cf74a78b 3202
9fb2d2b4
GN		 3203 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3204 ++vcpu->stat.irq_injections;
3205
219b65dc
AG		 3206 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3207 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3208}
3209
95ba8273 3210static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3211{
3212 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3213
2030753d 3214 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3215 return;
3216
95ba8273 3217 if (irr == -1)
aaacfc9a
JR		 3218 return;
3219
95ba8273 3220 if (tpr >= irr)
4ee546b4 3221 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3222}
aaacfc9a 3223
95ba8273
GN		 3224static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3225{
3226 struct vcpu_svm *svm = to_svm(vcpu);
3227 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3228 int ret;
3229 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3230 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3231 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3232
3233 return ret;
aaacfc9a
JR		 3234}
3235
3cfc3092
JK		 3236static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3237{
3238 struct vcpu_svm *svm = to_svm(vcpu);
3239
3240 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3241}
3242
3243static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3244{
3245 struct vcpu_svm *svm = to_svm(vcpu);
3246
3247 if (masked) {
3248 svm->vcpu.arch.hflags |= HF_NMI_MASK;
8a05a1b8 3249 set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3250 } else {
3251 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
8a05a1b8 3252 clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3253 }
3254}
3255
78646121
GN		 3256static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3257{
3258 struct vcpu_svm *svm = to_svm(vcpu);
3259 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3260 int ret;
3261
3262 if (!gif_set(svm) ||
3263 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3264 return 0;
3265
3266 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3267
2030753d 3268 if (is_guest_mode(vcpu))
7fcdb510
JR		 3269 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3270
3271 return ret;
78646121
GN		 3272}
3273
9222be18 3274static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3275{
219b65dc 3276 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3277
e0231715
JR		 3278 /*
3279 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3280 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3281 * get that intercept, this function will be called again though and
3282 * we'll get the vintr intercept.
3283 */
8fe54654 3284 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3285 svm_set_vintr(svm);
3286 svm_inject_irq(svm, 0x0);
3287 }
85f455f7
ED		 3288}
3289
95ba8273 3290static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3291{
04d2cc77 3292 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3293
44c11430
GN		 3294 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3295 == HF_NMI_MASK)
3296 return; /* IRET will cause a vm exit */
3297
e0231715
JR		 3298 /*
3299 * Something prevents NMI from been injected. Single step over possible
3300 * problem (IRET or exception injection or interrupt shadow)
3301 */
6be7d306 3302 svm->nmi_singlestep = true;
44c11430
GN		 3303 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3304 update_db_intercept(vcpu);
c1150d8c
DL		 3305}
3306
cbc94022
IE		 3307static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3308{
3309 return 0;
3310}
3311
d9e368d6
AK		 3312static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3313{
3314 force_new_asid(vcpu);
3315}
3316
04d2cc77
AK		 3317static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3318{
3319}
3320
d7bf8221
JR		 3321static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3322{
3323 struct vcpu_svm *svm = to_svm(vcpu);
3324
2030753d 3325 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3326 return;
3327
4ee546b4 3328 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3329 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3330 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3331 }
3332}
3333
649d6864
JR		 3334static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3335{
3336 struct vcpu_svm *svm = to_svm(vcpu);
3337 u64 cr8;
3338
2030753d 3339 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3340 return;
3341
649d6864
JR		 3342 cr8 = kvm_get_cr8(vcpu);
3343 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3344 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3345}
3346
9222be18
GN		 3347static void svm_complete_interrupts(struct vcpu_svm *svm)
3348{
3349 u8 vector;
3350 int type;
3351 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3352 unsigned int3_injected = svm->int3_injected;
3353
3354 svm->int3_injected = 0;
9222be18 3355
3842d135 3356 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3357 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3358 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3359 }
44c11430 3360
9222be18
GN		 3361 svm->vcpu.arch.nmi_injected = false;
3362 kvm_clear_exception_queue(&svm->vcpu);
3363 kvm_clear_interrupt_queue(&svm->vcpu);
3364
3365 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3366 return;
3367
3842d135
AK		 3368 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3369
9222be18
GN		 3370 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3371 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3372
3373 switch (type) {
3374 case SVM_EXITINTINFO_TYPE_NMI:
3375 svm->vcpu.arch.nmi_injected = true;
3376 break;
3377 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3378 /*
3379 * In case of software exceptions, do not reinject the vector,
3380 * but re-execute the instruction instead. Rewind RIP first
3381 * if we emulated INT3 before.
3382 */
3383 if (kvm_exception_is_soft(vector)) {
3384 if (vector == BP_VECTOR && int3_injected &&
3385 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3386 kvm_rip_write(&svm->vcpu,
3387 kvm_rip_read(&svm->vcpu) -
3388 int3_injected);
9222be18 3389 break;
66b7138f 3390 }
9222be18
GN		 3391 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3392 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3393 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3394
3395 } else
ce7ddec4 3396 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3397 break;
3398 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3399 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3400 break;
3401 default:
3402 break;
3403 }
3404}
3405
b463a6f7
AK		 3406static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3407{
3408 struct vcpu_svm *svm = to_svm(vcpu);
3409 struct vmcb_control_area *control = &svm->vmcb->control;
3410
3411 control->exit_int_info = control->event_inj;
3412 control->exit_int_info_err = control->event_inj_err;
3413 control->event_inj = 0;
3414 svm_complete_interrupts(svm);
3415}
3416
80e31d4f
AK		 3417#ifdef CONFIG_X86_64
3418#define R "r"
3419#else
3420#define R "e"
3421#endif
3422
851ba692 3423static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3424{
a2fa3e9f 3425 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3426
2041a06a
JR		 3427 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3428 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3429 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3430
cd3ff653
JR		 3431 /*
3432 * A vmexit emulation is required before the vcpu can be executed
3433 * again.
3434 */
3435 if (unlikely(svm->nested.exit_required))
3436 return;
3437
e756fc62 3438 pre_svm_run(svm);
6aa8b732 3439
649d6864
JR		 3440 sync_lapic_to_cr8(vcpu);
3441
cda0ffdd 3442 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3443
04d2cc77
AK		 3444 clgi();
3445
3446 local_irq_enable();
36241b8c 3447
6aa8b732 3448 asm volatile (
80e31d4f
AK		 3449 "push %%"R"bp; \n\t"
3450 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3451 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3452 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3453 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3454 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3455 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3456#ifdef CONFIG_X86_64
fb3f0f51
RR		 3457 "mov %c[r8](%[svm]), %%r8 \n\t"
3458 "mov %c[r9](%[svm]), %%r9 \n\t"
3459 "mov %c[r10](%[svm]), %%r10 \n\t"
3460 "mov %c[r11](%[svm]), %%r11 \n\t"
3461 "mov %c[r12](%[svm]), %%r12 \n\t"
3462 "mov %c[r13](%[svm]), %%r13 \n\t"
3463 "mov %c[r14](%[svm]), %%r14 \n\t"
3464 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3465#endif
3466
6aa8b732 3467 /* Enter guest mode */
80e31d4f
AK		 3468 "push %%"R"ax \n\t"
3469 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3470 __ex(SVM_VMLOAD) "\n\t"
3471 __ex(SVM_VMRUN) "\n\t"
3472 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3473 "pop %%"R"ax \n\t"
6aa8b732
AK		 3474
3475 /* Save guest registers, load host registers */
80e31d4f
AK		 3476 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3477 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3478 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3479 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3480 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3481 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3482#ifdef CONFIG_X86_64
fb3f0f51
RR		 3483 "mov %%r8, %c[r8](%[svm]) \n\t"
3484 "mov %%r9, %c[r9](%[svm]) \n\t"
3485 "mov %%r10, %c[r10](%[svm]) \n\t"
3486 "mov %%r11, %c[r11](%[svm]) \n\t"
3487 "mov %%r12, %c[r12](%[svm]) \n\t"
3488 "mov %%r13, %c[r13](%[svm]) \n\t"
3489 "mov %%r14, %c[r14](%[svm]) \n\t"
3490 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3491#endif
80e31d4f 3492 "pop %%"R"bp"
6aa8b732 3493 :
fb3f0f51 3494 : [svm]"a"(svm),
6aa8b732 3495 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3496 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3497 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3498 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3499 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3500 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3501 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3502#ifdef CONFIG_X86_64
ad312c7c
ZX		 3503 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3504 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3505 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3506 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3507 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3508 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3509 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3510 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3511#endif
54a08c04 3512 : "cc", "memory"
80e31d4f 3513 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3514#ifdef CONFIG_X86_64
54a08c04
LV		 3515 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3516#endif
3517 );
6aa8b732 3518
82ca2d10
AK		 3519#ifdef CONFIG_X86_64
3520 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3521#else
dacccfdd 3522 loadsegment(fs, svm->host.fs);
9581d442 3523#endif
6aa8b732
AK		 3524
3525 reload_tss(vcpu);
3526
56ba47dd
AK		 3527 local_irq_disable();
3528
3529 stgi();
3530
13c34e07
AK		 3531 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3532 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3533 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3534 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3535
d7bf8221
JR		 3536 sync_cr8_to_lapic(vcpu);
3537
a2fa3e9f 3538 svm->next_rip = 0;
9222be18 3539
631bc487
GN		 3540 /* if exit due to PF check for async PF */
3541 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3542 svm->apf_reason = kvm_read_and_reset_pf_reason();
3543
6de4f3ad
AK		 3544 if (npt_enabled) {
3545 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3546 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3547 }
fe5913e4
JR		 3548
3549 /*
3550 * We need to handle MC intercepts here before the vcpu has a chance to
3551 * change the physical cpu
3552 */
3553 if (unlikely(svm->vmcb->control.exit_code ==
3554 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3555 svm_handle_mce(svm);
8d28fec4
RJ		 3556
3557 mark_all_clean(svm->vmcb);
6aa8b732
AK		 3558}
3559
80e31d4f
AK		 3560#undef R
3561
6aa8b732
AK		 3562static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3563{
a2fa3e9f
GH		 3564 struct vcpu_svm *svm = to_svm(vcpu);
3565
3566 svm->vmcb->save.cr3 = root;
dcca1a65 3567 mark_dirty(svm->vmcb, VMCB_CR);
6aa8b732
AK		 3568 force_new_asid(vcpu);
3569}
3570
1c97f0a0
JR		 3571static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3572{
3573 struct vcpu_svm *svm = to_svm(vcpu);
3574
3575 svm->vmcb->control.nested_cr3 = root;
b2747166 3576 mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0
JR		 3577
3578 /* Also sync guest cr3 here in case we live migrate */
3579 svm->vmcb->save.cr3 = vcpu->arch.cr3;
dcca1a65 3580 mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3581
3582 force_new_asid(vcpu);
3583}
3584
6aa8b732
AK		 3585static int is_disabled(void)
3586{
6031a61c
JR		 3587 u64 vm_cr;
3588
3589 rdmsrl(MSR_VM_CR, vm_cr);
3590 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3591 return 1;
3592
6aa8b732
AK		 3593 return 0;
3594}
3595
102d8325
IM		 3596static void
3597svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3598{
3599 /*
3600 * Patch in the VMMCALL instruction:
3601 */
3602 hypercall[0] = 0x0f;
3603 hypercall[1] = 0x01;
3604 hypercall[2] = 0xd9;
102d8325
IM		 3605}
3606
002c7f7c
YS		 3607static void svm_check_processor_compat(void *rtn)
3608{
3609 *(int *)rtn = 0;
3610}
3611
774ead3a
AK		 3612static bool svm_cpu_has_accelerated_tpr(void)
3613{
3614 return false;
3615}
3616
4b12f0de 3617static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3618{
3619 return 0;
3620}
3621
0e851880
SY		 3622static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3623{
3624}
3625
d4330ef2
JR		 3626static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3627{
c2c63a49 3628 switch (func) {
24d1b15f
JR		 3629 case 0x00000001:
3630 /* Mask out xsave bit as long as it is not supported by SVM */
3631 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3632 break;
4c62a2dc
JR		 3633 case 0x80000001:
3634 if (nested)
3635 entry->ecx |= (1 << 2); /* Set SVM bit */
3636 break;
c2c63a49
JR		 3637 case 0x8000000A:
3638 entry->eax = 1; /* SVM revision 1 */
3639 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3640 ASID emulation to nested SVM */
3641 entry->ecx = 0; /* Reserved */
7a190667
JR		 3642 entry->edx = 0; /* Per default do not support any
3643 additional features */
3644
3645 /* Support next_rip if host supports it */
2a6b20b8 3646 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3647 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3648
3d4aeaad
JR		 3649 /* Support NPT for the guest if enabled */
3650 if (npt_enabled)
3651 entry->edx |= SVM_FEATURE_NPT;
3652
c2c63a49
JR		 3653 break;
3654 }
d4330ef2
JR		 3655}
3656
229456fc 3657static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3658 { SVM_EXIT_READ_CR0, "read_cr0" },
3659 { SVM_EXIT_READ_CR3, "read_cr3" },
3660 { SVM_EXIT_READ_CR4, "read_cr4" },
3661 { SVM_EXIT_READ_CR8, "read_cr8" },
3662 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3663 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3664 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3665 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3666 { SVM_EXIT_READ_DR0, "read_dr0" },
3667 { SVM_EXIT_READ_DR1, "read_dr1" },
3668 { SVM_EXIT_READ_DR2, "read_dr2" },
3669 { SVM_EXIT_READ_DR3, "read_dr3" },
3670 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3671 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3672 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3673 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3674 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3675 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3676 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3677 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3678 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3679 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3680 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3681 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3682 { SVM_EXIT_INTR, "interrupt" },
3683 { SVM_EXIT_NMI, "nmi" },
3684 { SVM_EXIT_SMI, "smi" },
3685 { SVM_EXIT_INIT, "init" },
3686 { SVM_EXIT_VINTR, "vintr" },
3687 { SVM_EXIT_CPUID, "cpuid" },
3688 { SVM_EXIT_INVD, "invd" },
3689 { SVM_EXIT_HLT, "hlt" },
3690 { SVM_EXIT_INVLPG, "invlpg" },
3691 { SVM_EXIT_INVLPGA, "invlpga" },
3692 { SVM_EXIT_IOIO, "io" },
3693 { SVM_EXIT_MSR, "msr" },
3694 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3695 { SVM_EXIT_SHUTDOWN, "shutdown" },
3696 { SVM_EXIT_VMRUN, "vmrun" },
3697 { SVM_EXIT_VMMCALL, "hypercall" },
3698 { SVM_EXIT_VMLOAD, "vmload" },
3699 { SVM_EXIT_VMSAVE, "vmsave" },
3700 { SVM_EXIT_STGI, "stgi" },
3701 { SVM_EXIT_CLGI, "clgi" },
3702 { SVM_EXIT_SKINIT, "skinit" },
3703 { SVM_EXIT_WBINVD, "wbinvd" },
3704 { SVM_EXIT_MONITOR, "monitor" },
3705 { SVM_EXIT_MWAIT, "mwait" },
3706 { SVM_EXIT_NPF, "npf" },
3707 { -1, NULL }
3708};
3709
17cc3935 3710static int svm_get_lpage_level(void)
344f414f 3711{
17cc3935 3712 return PT_PDPE_LEVEL;
344f414f
JR		 3713}
3714
4e47c7a6
SY		 3715static bool svm_rdtscp_supported(void)
3716{
3717 return false;
3718}
3719
f5f48ee1
SY		 3720static bool svm_has_wbinvd_exit(void)
3721{
3722 return true;
3723}
3724
02daab21
AK		 3725static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3726{
3727 struct vcpu_svm *svm = to_svm(vcpu);
3728
18c918c5 3729 set_exception_intercept(svm, NM_VECTOR);
66a562f7 3730 update_cr0_intercept(svm);
02daab21
AK		 3731}
3732
cbdd1bea 3733static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3734 .cpu_has_kvm_support = has_svm,
3735 .disabled_by_bios = is_disabled,
3736 .hardware_setup = svm_hardware_setup,
3737 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3738 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3739 .hardware_enable = svm_hardware_enable,
3740 .hardware_disable = svm_hardware_disable,
774ead3a 3741 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3742
3743 .vcpu_create = svm_create_vcpu,
3744 .vcpu_free = svm_free_vcpu,
04d2cc77 3745 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3746
04d2cc77 3747 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3748 .vcpu_load = svm_vcpu_load,
3749 .vcpu_put = svm_vcpu_put,
3750
3751 .set_guest_debug = svm_guest_debug,
3752 .get_msr = svm_get_msr,
3753 .set_msr = svm_set_msr,
3754 .get_segment_base = svm_get_segment_base,
3755 .get_segment = svm_get_segment,
3756 .set_segment = svm_set_segment,
2e4d2653 3757 .get_cpl = svm_get_cpl,
1747fb71 3758 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3759 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3760 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3761 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3762 .set_cr3 = svm_set_cr3,
3763 .set_cr4 = svm_set_cr4,
3764 .set_efer = svm_set_efer,
3765 .get_idt = svm_get_idt,
3766 .set_idt = svm_set_idt,
3767 .get_gdt = svm_get_gdt,
3768 .set_gdt = svm_set_gdt,
020df079 3769 .set_dr7 = svm_set_dr7,
6de4f3ad 3770 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3771 .get_rflags = svm_get_rflags,
3772 .set_rflags = svm_set_rflags,
6b52d186 3773 .fpu_activate = svm_fpu_activate,
02daab21 3774 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3775
6aa8b732 3776 .tlb_flush = svm_flush_tlb,
6aa8b732 3777
6aa8b732 3778 .run = svm_vcpu_run,
04d2cc77 3779 .handle_exit = handle_exit,
6aa8b732 3780 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3781 .set_interrupt_shadow = svm_set_interrupt_shadow,
3782 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3783 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3784 .set_irq = svm_set_irq,
95ba8273 3785 .set_nmi = svm_inject_nmi,
298101da 3786 .queue_exception = svm_queue_exception,
b463a6f7 3787 .cancel_injection = svm_cancel_injection,
78646121 3788 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3789 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3790 .get_nmi_mask = svm_get_nmi_mask,
3791 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3792 .enable_nmi_window = enable_nmi_window,
3793 .enable_irq_window = enable_irq_window,
3794 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3795
3796 .set_tss_addr = svm_set_tss_addr,
67253af5 3797 .get_tdp_level = get_npt_level,
4b12f0de 3798 .get_mt_mask = svm_get_mt_mask,
229456fc 3799
586f9607 3800 .get_exit_info = svm_get_exit_info,
229456fc 3801 .exit_reasons_str = svm_exit_reasons_str,
586f9607 3802
17cc3935 3803 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3804
3805 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3806
3807 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3808
3809 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3810
3811 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3812
3813 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3814 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3815
3816 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3817};
3818
3819static int __init svm_init(void)
3820{
cb498ea2 3821 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3822 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3823}
3824
3825static void __exit svm_exit(void)
3826{
cb498ea2 3827 kvm_exit();
6aa8b732
AK		 3828}
3829
3830module_init(svm_init)
3831module_exit(svm_exit)
Linux kernel - Deliverables
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