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KVM: SVM: Use svm_msrpm_offset in nested_svm_exit_handled_msr
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
66b7138f 50#define SVM_FEATURE_NRIP (1 << 3)
565d0998 51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
aad42c64 82
cd3ff653
JR		 83 /* A VMEXIT is required but not yet emulated */
84 bool exit_required;
85
aad42c64
JR		 86 /* cache for intercepts of the guest */
87 u16 intercept_cr_read;
88 u16 intercept_cr_write;
89 u16 intercept_dr_read;
90 u16 intercept_dr_write;
91 u32 intercept_exceptions;
92 u64 intercept;
93
e6aa9abd
JR		 94};
95
323c3d80
JR		 96#define MSRPM_OFFSETS 16
97static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
98
6c8166a7
AK		 99struct vcpu_svm {
100 struct kvm_vcpu vcpu;
101 struct vmcb *vmcb;
102 unsigned long vmcb_pa;
103 struct svm_cpu_data *svm_data;
104 uint64_t asid_generation;
105 uint64_t sysenter_esp;
106 uint64_t sysenter_eip;
107
108 u64 next_rip;
109
110 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
111 u64 host_gs_base;
6c8166a7
AK		 112
113 u32 *msrpm;
6c8166a7 114
e6aa9abd 115 struct nested_state nested;
6be7d306
JK		 116
117 bool nmi_singlestep;
66b7138f
JK		 118
119 unsigned int3_injected;
120 unsigned long int3_rip;
6c8166a7
AK		 121};
122
455716fa
JR		 123#define MSR_INVALID 0xffffffffU
124
ac72a9b7
JR		 125static struct svm_direct_access_msrs {
126 u32 index; /* Index of the MSR */
127 bool always; /* True if intercept is always on */
128} direct_access_msrs[] = {
129 { .index = MSR_K6_STAR, .always = true },
130 { .index = MSR_IA32_SYSENTER_CS, .always = true },
131#ifdef CONFIG_X86_64
132 { .index = MSR_GS_BASE, .always = true },
133 { .index = MSR_FS_BASE, .always = true },
134 { .index = MSR_KERNEL_GS_BASE, .always = true },
135 { .index = MSR_LSTAR, .always = true },
136 { .index = MSR_CSTAR, .always = true },
137 { .index = MSR_SYSCALL_MASK, .always = true },
138#endif
139 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
140 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
141 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
142 { .index = MSR_IA32_LASTINTTOIP, .always = false },
143 { .index = MSR_INVALID, .always = false },
144};
145
709ddebf
JR		 146/* enable NPT for AMD64 and X86 with PAE */
147#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
148static bool npt_enabled = true;
149#else
e0231715 150static bool npt_enabled;
709ddebf 151#endif
6c7dac72
JR		 152static int npt = 1;
153
154module_param(npt, int, S_IRUGO);
e3da3acd 155
4b6e4dca 156static int nested = 1;
236de055
AG		 157module_param(nested, int, S_IRUGO);
158
44874f84 159static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 160static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 161
410e4d57 162static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 163static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 164static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 165static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
166 bool has_error_code, u32 error_code);
167
a2fa3e9f
GH		 168static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
169{
fb3f0f51 170 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 171}
172
3d6368ef
AG		 173static inline bool is_nested(struct vcpu_svm *svm)
174{
e6aa9abd 175 return svm->nested.vmcb;
3d6368ef
AG		 176}
177
2af9194d
JR		 178static inline void enable_gif(struct vcpu_svm *svm)
179{
180 svm->vcpu.arch.hflags |= HF_GIF_MASK;
181}
182
183static inline void disable_gif(struct vcpu_svm *svm)
184{
185 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
186}
187
188static inline bool gif_set(struct vcpu_svm *svm)
189{
190 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
191}
192
4866d5e3 193static unsigned long iopm_base;
6aa8b732
AK		 194
195struct kvm_ldttss_desc {
196 u16 limit0;
197 u16 base0;
e0231715
JR		 198 unsigned base1:8, type:5, dpl:2, p:1;
199 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 200 u32 base3;
201 u32 zero1;
202} __attribute__((packed));
203
204struct svm_cpu_data {
205 int cpu;
206
5008fdf5
AK		 207 u64 asid_generation;
208 u32 max_asid;
209 u32 next_asid;
6aa8b732
AK		 210 struct kvm_ldttss_desc *tss_desc;
211
212 struct page *save_area;
213};
214
215static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 216static uint32_t svm_features;
6aa8b732
AK		 217
218struct svm_init_data {
219 int cpu;
220 int r;
221};
222
223static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
224
9d8f549d 225#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 226#define MSRS_RANGE_SIZE 2048
227#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
228
455716fa
JR		 229static u32 svm_msrpm_offset(u32 msr)
230{
231 u32 offset;
232 int i;
233
234 for (i = 0; i < NUM_MSR_MAPS; i++) {
235 if (msr < msrpm_ranges[i] ||
236 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
237 continue;
238
239 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
240 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
241
242 /* Now we have the u8 offset - but need the u32 offset */
243 return offset / 4;
244 }
245
246 /* MSR not in any range */
247 return MSR_INVALID;
248}
249
6aa8b732
AK		 250#define MAX_INST_SIZE 15
251
80b7706e
JR		 252static inline u32 svm_has(u32 feat)
253{
254 return svm_features & feat;
255}
256
6aa8b732
AK		 257static inline void clgi(void)
258{
4ecac3fd 259 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 260}
261
262static inline void stgi(void)
263{
4ecac3fd 264 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 265}
266
267static inline void invlpga(unsigned long addr, u32 asid)
268{
e0231715 269 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 270}
271
6aa8b732
AK		 272static inline void force_new_asid(struct kvm_vcpu *vcpu)
273{
a2fa3e9f 274 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 275}
276
277static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
278{
279 force_new_asid(vcpu);
280}
281
282static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
283{
709ddebf 284 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 285 efer &= ~EFER_LME;
6aa8b732 286
9962d032 287 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 288 vcpu->arch.efer = efer;
6aa8b732
AK		 289}
290
6aa8b732
AK		 291static int is_external_interrupt(u32 info)
292{
293 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
294 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
295}
296
2809f5d2
GC		 297static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
298{
299 struct vcpu_svm *svm = to_svm(vcpu);
300 u32 ret = 0;
301
302 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 303 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 304 return ret & mask;
305}
306
307static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
308{
309 struct vcpu_svm *svm = to_svm(vcpu);
310
311 if (mask == 0)
312 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
313 else
314 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
315
316}
317
6aa8b732
AK		 318static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
319{
a2fa3e9f
GH		 320 struct vcpu_svm *svm = to_svm(vcpu);
321
322 if (!svm->next_rip) {
851ba692 323 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 324 EMULATE_DONE)
325 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 326 return;
327 }
5fdbf976
MT		 328 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
329 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
330 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 331
5fdbf976 332 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 333 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 334}
335
116a4752
JK		 336static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
337 bool has_error_code, u32 error_code)
338{
339 struct vcpu_svm *svm = to_svm(vcpu);
340
e0231715
JR		 341 /*
342 * If we are within a nested VM we'd better #VMEXIT and let the guest
343 * handle the exception
344 */
116a4752
JK		 345 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
346 return;
347
66b7138f
JK		 348 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
349 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
350
351 /*
352 * For guest debugging where we have to reinject #BP if some
353 * INT3 is guest-owned:
354 * Emulate nRIP by moving RIP forward. Will fail if injection
355 * raises a fault that is not intercepted. Still better than
356 * failing in all cases.
357 */
358 skip_emulated_instruction(&svm->vcpu);
359 rip = kvm_rip_read(&svm->vcpu);
360 svm->int3_rip = rip + svm->vmcb->save.cs.base;
361 svm->int3_injected = rip - old_rip;
362 }
363
116a4752
JK		 364 svm->vmcb->control.event_inj = nr
365 | SVM_EVTINJ_VALID
366 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
367 | SVM_EVTINJ_TYPE_EXEPT;
368 svm->vmcb->control.event_inj_err = error_code;
369}
370
6aa8b732
AK		 371static int has_svm(void)
372{
63d1142f 373 const char *msg;
6aa8b732 374
63d1142f 375 if (!cpu_has_svm(&msg)) {
ff81ff10 376 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 377 return 0;
378 }
379
6aa8b732
AK		 380 return 1;
381}
382
383static void svm_hardware_disable(void *garbage)
384{
2c8dceeb 385 cpu_svm_disable();
6aa8b732
AK		 386}
387
10474ae8 388static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 389{
390
0fe1e009 391 struct svm_cpu_data *sd;
6aa8b732 392 uint64_t efer;
89a27f4d 393 struct desc_ptr gdt_descr;
6aa8b732
AK		 394 struct desc_struct *gdt;
395 int me = raw_smp_processor_id();
396
10474ae8
AG		 397 rdmsrl(MSR_EFER, efer);
398 if (efer & EFER_SVME)
399 return -EBUSY;
400
6aa8b732 401 if (!has_svm()) {
e6732a5a
ZA		 402 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
403 me);
10474ae8 404 return -EINVAL;
6aa8b732 405 }
0fe1e009 406 sd = per_cpu(svm_data, me);
6aa8b732 407
0fe1e009 408 if (!sd) {
e6732a5a 409 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 410 me);
10474ae8 411 return -EINVAL;
6aa8b732
AK		 412 }
413
0fe1e009
TH		 414 sd->asid_generation = 1;
415 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
416 sd->next_asid = sd->max_asid + 1;
6aa8b732 417
d6ab1ed4 418 native_store_gdt(&gdt_descr);
89a27f4d 419 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 420 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 421
9962d032 422 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 423
d0316554 424 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 425
426 return 0;
6aa8b732
AK		 427}
428
0da1db75
JR		 429static void svm_cpu_uninit(int cpu)
430{
0fe1e009 431 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 432
0fe1e009 433 if (!sd)
0da1db75
JR		 434 return;
435
436 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 437 __free_page(sd->save_area);
438 kfree(sd);
0da1db75
JR		 439}
440
6aa8b732
AK		 441static int svm_cpu_init(int cpu)
442{
0fe1e009 443 struct svm_cpu_data *sd;
6aa8b732
AK		 444 int r;
445
0fe1e009
TH		 446 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
447 if (!sd)
6aa8b732 448 return -ENOMEM;
0fe1e009
TH		 449 sd->cpu = cpu;
450 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 451 r = -ENOMEM;
0fe1e009 452 if (!sd->save_area)
6aa8b732
AK		 453 goto err_1;
454
0fe1e009 455 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 456
457 return 0;
458
459err_1:
0fe1e009 460 kfree(sd);
6aa8b732
AK		 461 return r;
462
463}
464
ac72a9b7
JR		 465static bool valid_msr_intercept(u32 index)
466{
467 int i;
468
469 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
470 if (direct_access_msrs[i].index == index)
471 return true;
472
473 return false;
474}
475
bfc733a7
RR		 476static void set_msr_interception(u32 *msrpm, unsigned msr,
477 int read, int write)
6aa8b732 478{
455716fa
JR		 479 u8 bit_read, bit_write;
480 unsigned long tmp;
481 u32 offset;
6aa8b732 482
ac72a9b7
JR		 483 /*
484 * If this warning triggers extend the direct_access_msrs list at the
485 * beginning of the file
486 */
487 WARN_ON(!valid_msr_intercept(msr));
488
455716fa
JR		 489 offset = svm_msrpm_offset(msr);
490 bit_read = 2 * (msr & 0x0f);
491 bit_write = 2 * (msr & 0x0f) + 1;
492 tmp = msrpm[offset];
493
494 BUG_ON(offset == MSR_INVALID);
495
496 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
497 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
498
499 msrpm[offset] = tmp;
6aa8b732
AK		 500}
501
f65c229c
JR		 502static void svm_vcpu_init_msrpm(u32 *msrpm)
503{
ac72a9b7
JR		 504 int i;
505
f65c229c
JR		 506 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
507
ac72a9b7
JR		 508 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
509 if (!direct_access_msrs[i].always)
510 continue;
511
512 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
513 }
f65c229c
JR		 514}
515
323c3d80
JR		 516static void add_msr_offset(u32 offset)
517{
518 int i;
519
520 for (i = 0; i < MSRPM_OFFSETS; ++i) {
521
522 /* Offset already in list? */
523 if (msrpm_offsets[i] == offset)
524 return;
525
526 /* Slot used by another offset? */
527 if (msrpm_offsets[i] != MSR_INVALID)
528 continue;
529
530 /* Add offset to list */
531 msrpm_offsets[i] = offset;
532
533 return;
534 }
535
536 /*
537 * If this BUG triggers the msrpm_offsets table has an overflow. Just
538 * increase MSRPM_OFFSETS in this case.
539 */
540 BUG();
541}
542
543static void init_msrpm_offsets(void)
544{
545 int i;
546
547 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
548
549 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
550 u32 offset;
551
552 offset = svm_msrpm_offset(direct_access_msrs[i].index);
553 BUG_ON(offset == MSR_INVALID);
554
555 add_msr_offset(offset);
556 }
557}
558
24e09cbf
JR		 559static void svm_enable_lbrv(struct vcpu_svm *svm)
560{
561 u32 *msrpm = svm->msrpm;
562
563 svm->vmcb->control.lbr_ctl = 1;
564 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
565 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
566 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
567 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
568}
569
570static void svm_disable_lbrv(struct vcpu_svm *svm)
571{
572 u32 *msrpm = svm->msrpm;
573
574 svm->vmcb->control.lbr_ctl = 0;
575 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
576 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
577 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
578 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
579}
580
6aa8b732
AK		 581static __init int svm_hardware_setup(void)
582{
583 int cpu;
584 struct page *iopm_pages;
f65c229c 585 void *iopm_va;
6aa8b732
AK		 586 int r;
587
6aa8b732
AK		 588 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
589
590 if (!iopm_pages)
591 return -ENOMEM;
c8681339
AL		 592
593 iopm_va = page_address(iopm_pages);
594 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 595 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
596
323c3d80
JR		 597 init_msrpm_offsets();
598
50a37eb4
JR		 599 if (boot_cpu_has(X86_FEATURE_NX))
600 kvm_enable_efer_bits(EFER_NX);
601
1b2fd70c
AG		 602 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
603 kvm_enable_efer_bits(EFER_FFXSR);
604
236de055
AG		 605 if (nested) {
606 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
607 kvm_enable_efer_bits(EFER_SVME);
608 }
609
3230bb47 610 for_each_possible_cpu(cpu) {
6aa8b732
AK		 611 r = svm_cpu_init(cpu);
612 if (r)
f65c229c 613 goto err;
6aa8b732 614 }
33bd6a0b
JR		 615
616 svm_features = cpuid_edx(SVM_CPUID_FUNC);
617
e3da3acd
JR		 618 if (!svm_has(SVM_FEATURE_NPT))
619 npt_enabled = false;
620
6c7dac72
JR		 621 if (npt_enabled && !npt) {
622 printk(KERN_INFO "kvm: Nested Paging disabled\n");
623 npt_enabled = false;
624 }
625
18552672 626 if (npt_enabled) {
e3da3acd 627 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 628 kvm_enable_tdp();
5f4cb662
JR		 629 } else
630 kvm_disable_tdp();
e3da3acd 631
6aa8b732
AK		 632 return 0;
633
f65c229c 634err:
6aa8b732
AK		 635 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
636 iopm_base = 0;
637 return r;
638}
639
640static __exit void svm_hardware_unsetup(void)
641{
0da1db75
JR		 642 int cpu;
643
3230bb47 644 for_each_possible_cpu(cpu)
0da1db75
JR		 645 svm_cpu_uninit(cpu);
646
6aa8b732 647 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 648 iopm_base = 0;
6aa8b732
AK		 649}
650
651static void init_seg(struct vmcb_seg *seg)
652{
653 seg->selector = 0;
654 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 655 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 656 seg->limit = 0xffff;
657 seg->base = 0;
658}
659
660static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
661{
662 seg->selector = 0;
663 seg->attrib = SVM_SELECTOR_P_MASK | type;
664 seg->limit = 0xffff;
665 seg->base = 0;
666}
667
e6101a96 668static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 669{
e6101a96
JR		 670 struct vmcb_control_area *control = &svm->vmcb->control;
671 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 672
bff78274
AK		 673 svm->vcpu.fpu_active = 1;
674
e0231715 675 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 676 INTERCEPT_CR3_MASK |
649d6864 677 INTERCEPT_CR4_MASK;
6aa8b732 678
e0231715 679 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 680 INTERCEPT_CR3_MASK |
80a8119c
AK		 681 INTERCEPT_CR4_MASK |
682 INTERCEPT_CR8_MASK;
6aa8b732 683
e0231715 684 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 685 INTERCEPT_DR1_MASK |
686 INTERCEPT_DR2_MASK |
727f5a23
JK		 687 INTERCEPT_DR3_MASK |
688 INTERCEPT_DR4_MASK |
689 INTERCEPT_DR5_MASK |
690 INTERCEPT_DR6_MASK |
691 INTERCEPT_DR7_MASK;
6aa8b732 692
e0231715 693 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 694 INTERCEPT_DR1_MASK |
695 INTERCEPT_DR2_MASK |
696 INTERCEPT_DR3_MASK |
727f5a23 697 INTERCEPT_DR4_MASK |
6aa8b732 698 INTERCEPT_DR5_MASK |
727f5a23 699 INTERCEPT_DR6_MASK |
6aa8b732
AK		 700 INTERCEPT_DR7_MASK;
701
7aa81cc0 702 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 703 (1 << UD_VECTOR) |
704 (1 << MC_VECTOR);
6aa8b732
AK		 705
706
e0231715 707 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 708 (1ULL << INTERCEPT_NMI) |
0152527b 709 (1ULL << INTERCEPT_SMI) |
d225157b 710 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 711 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 712 (1ULL << INTERCEPT_INVD) |
6aa8b732 713 (1ULL << INTERCEPT_HLT) |
a7052897 714 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 715 (1ULL << INTERCEPT_INVLPGA) |
716 (1ULL << INTERCEPT_IOIO_PROT) |
717 (1ULL << INTERCEPT_MSR_PROT) |
718 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 719 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 720 (1ULL << INTERCEPT_VMRUN) |
721 (1ULL << INTERCEPT_VMMCALL) |
722 (1ULL << INTERCEPT_VMLOAD) |
723 (1ULL << INTERCEPT_VMSAVE) |
724 (1ULL << INTERCEPT_STGI) |
725 (1ULL << INTERCEPT_CLGI) |
916ce236 726 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 727 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 728 (1ULL << INTERCEPT_MONITOR) |
729 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 730
731 control->iopm_base_pa = iopm_base;
f65c229c 732 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 733 control->tsc_offset = 0;
6aa8b732
AK		 734 control->int_ctl = V_INTR_MASKING_MASK;
735
736 init_seg(&save->es);
737 init_seg(&save->ss);
738 init_seg(&save->ds);
739 init_seg(&save->fs);
740 init_seg(&save->gs);
741
742 save->cs.selector = 0xf000;
743 /* Executable/Readable Code Segment */
744 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
745 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
746 save->cs.limit = 0xffff;
d92899a0
AK		 747 /*
748 * cs.base should really be 0xffff0000, but vmx can't handle that, so
749 * be consistent with it.
750 *
751 * Replace when we have real mode working for vmx.
752 */
753 save->cs.base = 0xf0000;
6aa8b732
AK		 754
755 save->gdtr.limit = 0xffff;
756 save->idtr.limit = 0xffff;
757
758 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
759 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
760
9962d032 761 save->efer = EFER_SVME;
d77c26fc 762 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 763 save->dr7 = 0x400;
764 save->rflags = 2;
765 save->rip = 0x0000fff0;
5fdbf976 766 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 767
e0231715
JR		 768 /*
769 * This is the guest-visible cr0 value.
18fa000a 770 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 771 */
18fa000a
EH		 772 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
773 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
774
66aee91a 775 save->cr4 = X86_CR4_PAE;
6aa8b732 776 /* rdx = ?? */
709ddebf
JR		 777
778 if (npt_enabled) {
779 /* Setup VMCB for Nested Paging */
780 control->nested_ctl = 1;
a7052897
MT		 781 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
782 (1ULL << INTERCEPT_INVLPG));
709ddebf 783 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 784 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
785 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 786 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 787 save->cr3 = 0;
788 save->cr4 = 0;
789 }
a79d2f18 790 force_new_asid(&svm->vcpu);
1371d904 791
e6aa9abd 792 svm->nested.vmcb = 0;
2af9194d
JR		 793 svm->vcpu.arch.hflags = 0;
794
565d0998
ML		 795 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
796 control->pause_filter_count = 3000;
797 control->intercept |= (1ULL << INTERCEPT_PAUSE);
798 }
799
2af9194d 800 enable_gif(svm);
6aa8b732
AK		 801}
802
e00c8cf2 803static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 804{
805 struct vcpu_svm *svm = to_svm(vcpu);
806
e6101a96 807 init_vmcb(svm);
70433389 808
c5af89b6 809 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 810 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 811 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
812 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 813 }
5fdbf976
MT		 814 vcpu->arch.regs_avail = ~0;
815 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 816
817 return 0;
04d2cc77
AK		 818}
819
fb3f0f51 820static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 821{
a2fa3e9f 822 struct vcpu_svm *svm;
6aa8b732 823 struct page *page;
f65c229c 824 struct page *msrpm_pages;
b286d5d8 825 struct page *hsave_page;
3d6368ef 826 struct page *nested_msrpm_pages;
fb3f0f51 827 int err;
6aa8b732 828
c16f862d 829 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 830 if (!svm) {
831 err = -ENOMEM;
832 goto out;
833 }
834
835 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
836 if (err)
837 goto free_svm;
838
b7af4043 839 err = -ENOMEM;
6aa8b732 840 page = alloc_page(GFP_KERNEL);
b7af4043 841 if (!page)
fb3f0f51 842 goto uninit;
6aa8b732 843
f65c229c
JR		 844 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
845 if (!msrpm_pages)
b7af4043 846 goto free_page1;
3d6368ef
AG		 847
848 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
849 if (!nested_msrpm_pages)
b7af4043 850 goto free_page2;
f65c229c 851
b286d5d8
AG		 852 hsave_page = alloc_page(GFP_KERNEL);
853 if (!hsave_page)
b7af4043
TY		 854 goto free_page3;
855
e6aa9abd 856 svm->nested.hsave = page_address(hsave_page);
b286d5d8 857
b7af4043
TY		 858 svm->msrpm = page_address(msrpm_pages);
859 svm_vcpu_init_msrpm(svm->msrpm);
860
e6aa9abd 861 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 862 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 863
a2fa3e9f
GH		 864 svm->vmcb = page_address(page);
865 clear_page(svm->vmcb);
866 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
867 svm->asid_generation = 0;
e6101a96 868 init_vmcb(svm);
a2fa3e9f 869
fb3f0f51 870 fx_init(&svm->vcpu);
ad312c7c 871 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 872 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 873 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 874
fb3f0f51 875 return &svm->vcpu;
36241b8c 876
b7af4043
TY		 877free_page3:
878 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
879free_page2:
880 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
881free_page1:
882 __free_page(page);
fb3f0f51
RR		 883uninit:
884 kvm_vcpu_uninit(&svm->vcpu);
885free_svm:
a4770347 886 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 887out:
888 return ERR_PTR(err);
6aa8b732
AK		 889}
890
891static void svm_free_vcpu(struct kvm_vcpu *vcpu)
892{
a2fa3e9f
GH		 893 struct vcpu_svm *svm = to_svm(vcpu);
894
fb3f0f51 895 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 896 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 897 __free_page(virt_to_page(svm->nested.hsave));
898 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 899 kvm_vcpu_uninit(vcpu);
a4770347 900 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 901}
902
15ad7146 903static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 904{
a2fa3e9f 905 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 906 int i;
0cc5064d 907
0cc5064d 908 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 909 u64 delta;
0cc5064d 910
953899b6
JR		 911 if (check_tsc_unstable()) {
912 /*
913 * Make sure that the guest sees a monotonically
914 * increasing TSC.
915 */
916 delta = vcpu->arch.host_tsc - native_read_tsc();
917 svm->vmcb->control.tsc_offset += delta;
918 if (is_nested(svm))
919 svm->nested.hsave->control.tsc_offset += delta;
920 }
0cc5064d 921 vcpu->cpu = cpu;
2f599714 922 kvm_migrate_timers(vcpu);
4b656b12 923 svm->asid_generation = 0;
0cc5064d 924 }
94dfbdb3
AL		 925
926 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 927 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 928}
929
930static void svm_vcpu_put(struct kvm_vcpu *vcpu)
931{
a2fa3e9f 932 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 933 int i;
934
e1beb1d3 935 ++vcpu->stat.host_state_reload;
94dfbdb3 936 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 937 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 938
e935d48e 939 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 940}
941
6aa8b732
AK		 942static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
943{
a2fa3e9f 944 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 945}
946
947static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
948{
a2fa3e9f 949 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 950}
951
6de4f3ad
AK		 952static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
953{
954 switch (reg) {
955 case VCPU_EXREG_PDPTR:
956 BUG_ON(!npt_enabled);
957 load_pdptrs(vcpu, vcpu->arch.cr3);
958 break;
959 default:
960 BUG();
961 }
962}
963
f0b85051
AG		 964static void svm_set_vintr(struct vcpu_svm *svm)
965{
966 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
967}
968
969static void svm_clear_vintr(struct vcpu_svm *svm)
970{
971 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
972}
973
6aa8b732
AK		 974static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
975{
a2fa3e9f 976 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 977
978 switch (seg) {
979 case VCPU_SREG_CS: return &save->cs;
980 case VCPU_SREG_DS: return &save->ds;
981 case VCPU_SREG_ES: return &save->es;
982 case VCPU_SREG_FS: return &save->fs;
983 case VCPU_SREG_GS: return &save->gs;
984 case VCPU_SREG_SS: return &save->ss;
985 case VCPU_SREG_TR: return &save->tr;
986 case VCPU_SREG_LDTR: return &save->ldtr;
987 }
988 BUG();
8b6d44c7 989 return NULL;
6aa8b732
AK		 990}
991
992static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
993{
994 struct vmcb_seg *s = svm_seg(vcpu, seg);
995
996 return s->base;
997}
998
999static void svm_get_segment(struct kvm_vcpu *vcpu,
1000 struct kvm_segment *var, int seg)
1001{
1002 struct vmcb_seg *s = svm_seg(vcpu, seg);
1003
1004 var->base = s->base;
1005 var->limit = s->limit;
1006 var->selector = s->selector;
1007 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1008 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1009 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1010 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1011 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1012 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1013 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1014 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1015
e0231715
JR		 1016 /*
1017 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1018 * for cross vendor migration purposes by "not present"
1019 */
1020 var->unusable = !var->present || (var->type == 0);
1021
1fbdc7a5
AP		 1022 switch (seg) {
1023 case VCPU_SREG_CS:
1024 /*
1025 * SVM always stores 0 for the 'G' bit in the CS selector in
1026 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1027 * Intel's VMENTRY has a check on the 'G' bit.
1028 */
25022acc 1029 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1030 break;
1031 case VCPU_SREG_TR:
1032 /*
1033 * Work around a bug where the busy flag in the tr selector
1034 * isn't exposed
1035 */
c0d09828 1036 var->type |= 0x2;
1fbdc7a5
AP		 1037 break;
1038 case VCPU_SREG_DS:
1039 case VCPU_SREG_ES:
1040 case VCPU_SREG_FS:
1041 case VCPU_SREG_GS:
1042 /*
1043 * The accessed bit must always be set in the segment
1044 * descriptor cache, although it can be cleared in the
1045 * descriptor, the cached bit always remains at 1. Since
1046 * Intel has a check on this, set it here to support
1047 * cross-vendor migration.
1048 */
1049 if (!var->unusable)
1050 var->type |= 0x1;
1051 break;
b586eb02 1052 case VCPU_SREG_SS:
e0231715
JR		 1053 /*
1054 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1055 * descriptor is left as 1, although the whole segment has
1056 * been made unusable. Clear it here to pass an Intel VMX
1057 * entry check when cross vendor migrating.
1058 */
1059 if (var->unusable)
1060 var->db = 0;
1061 break;
1fbdc7a5 1062 }
6aa8b732
AK		 1063}
1064
2e4d2653
IE		 1065static int svm_get_cpl(struct kvm_vcpu *vcpu)
1066{
1067 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1068
1069 return save->cpl;
1070}
1071
89a27f4d 1072static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1073{
a2fa3e9f
GH		 1074 struct vcpu_svm *svm = to_svm(vcpu);
1075
89a27f4d
GN		 1076 dt->size = svm->vmcb->save.idtr.limit;
1077 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1078}
1079
89a27f4d 1080static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1081{
a2fa3e9f
GH		 1082 struct vcpu_svm *svm = to_svm(vcpu);
1083
89a27f4d
GN		 1084 svm->vmcb->save.idtr.limit = dt->size;
1085 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1086}
1087
89a27f4d 1088static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1089{
a2fa3e9f
GH		 1090 struct vcpu_svm *svm = to_svm(vcpu);
1091
89a27f4d
GN		 1092 dt->size = svm->vmcb->save.gdtr.limit;
1093 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1094}
1095
89a27f4d 1096static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1097{
a2fa3e9f
GH		 1098 struct vcpu_svm *svm = to_svm(vcpu);
1099
89a27f4d
GN		 1100 svm->vmcb->save.gdtr.limit = dt->size;
1101 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1102}
1103
e8467fda
AK		 1104static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1105{
1106}
1107
25c4c276 1108static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1109{
1110}
1111
d225157b
AK		 1112static void update_cr0_intercept(struct vcpu_svm *svm)
1113{
66a562f7 1114 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1115 ulong gcr0 = svm->vcpu.arch.cr0;
1116 u64 *hcr0 = &svm->vmcb->save.cr0;
1117
1118 if (!svm->vcpu.fpu_active)
1119 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1120 else
1121 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1122 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1123
1124
1125 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1126 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1127 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1128 if (is_nested(svm)) {
1129 struct vmcb *hsave = svm->nested.hsave;
1130
1131 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1132 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1133 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1134 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1135 }
d225157b
AK		 1136 } else {
1137 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1138 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1139 if (is_nested(svm)) {
1140 struct vmcb *hsave = svm->nested.hsave;
1141
1142 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1143 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1144 }
d225157b
AK		 1145 }
1146}
1147
6aa8b732
AK		 1148static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1149{
a2fa3e9f
GH		 1150 struct vcpu_svm *svm = to_svm(vcpu);
1151
7f5d8b56
JR		 1152 if (is_nested(svm)) {
1153 /*
1154 * We are here because we run in nested mode, the host kvm
1155 * intercepts cr0 writes but the l1 hypervisor does not.
1156 * But the L1 hypervisor may intercept selective cr0 writes.
1157 * This needs to be checked here.
1158 */
1159 unsigned long old, new;
1160
1161 /* Remove bits that would trigger a real cr0 write intercept */
1162 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1163 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1164
1165 if (old == new) {
1166 /* cr0 write with ts and mp unchanged */
1167 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1168 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1169 return;
1170 }
1171 }
1172
05b3e0c2 1173#ifdef CONFIG_X86_64
f6801dff 1174 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1175 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1176 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1177 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1178 }
1179
d77c26fc 1180 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1181 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1182 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1183 }
1184 }
1185#endif
ad312c7c 1186 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1187
1188 if (!npt_enabled)
1189 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1190
1191 if (!vcpu->fpu_active)
334df50a 1192 cr0 |= X86_CR0_TS;
709ddebf
JR		 1193 /*
1194 * re-enable caching here because the QEMU bios
1195 * does not do it - this results in some delay at
1196 * reboot
1197 */
1198 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1199 svm->vmcb->save.cr0 = cr0;
d225157b 1200 update_cr0_intercept(svm);
6aa8b732
AK		 1201}
1202
1203static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1204{
6394b649 1205 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1206 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1207
1208 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1209 force_new_asid(vcpu);
6394b649 1210
ec077263
JR		 1211 vcpu->arch.cr4 = cr4;
1212 if (!npt_enabled)
1213 cr4 |= X86_CR4_PAE;
6394b649 1214 cr4 |= host_cr4_mce;
ec077263 1215 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1216}
1217
1218static void svm_set_segment(struct kvm_vcpu *vcpu,
1219 struct kvm_segment *var, int seg)
1220{
a2fa3e9f 1221 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1222 struct vmcb_seg *s = svm_seg(vcpu, seg);
1223
1224 s->base = var->base;
1225 s->limit = var->limit;
1226 s->selector = var->selector;
1227 if (var->unusable)
1228 s->attrib = 0;
1229 else {
1230 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1231 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1232 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1233 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1234 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1235 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1236 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1237 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1238 }
1239 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1240 svm->vmcb->save.cpl
1241 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1242 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1243
1244}
1245
44c11430 1246static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1247{
d0bfb940
JK		 1248 struct vcpu_svm *svm = to_svm(vcpu);
1249
d0bfb940
JK		 1250 svm->vmcb->control.intercept_exceptions &=
1251 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1252
6be7d306 1253 if (svm->nmi_singlestep)
44c11430
GN		 1254 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1255
d0bfb940
JK		 1256 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1257 if (vcpu->guest_debug &
1258 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1259 svm->vmcb->control.intercept_exceptions |=
1260 1 << DB_VECTOR;
1261 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1262 svm->vmcb->control.intercept_exceptions |=
1263 1 << BP_VECTOR;
1264 } else
1265 vcpu->guest_debug = 0;
44c11430
GN		 1266}
1267
355be0b9 1268static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1269{
44c11430
GN		 1270 struct vcpu_svm *svm = to_svm(vcpu);
1271
ae675ef0
JK		 1272 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1273 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1274 else
1275 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1276
355be0b9 1277 update_db_intercept(vcpu);
6aa8b732
AK		 1278}
1279
1280static void load_host_msrs(struct kvm_vcpu *vcpu)
1281{
94dfbdb3 1282#ifdef CONFIG_X86_64
a2fa3e9f 1283 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1284#endif
6aa8b732
AK		 1285}
1286
1287static void save_host_msrs(struct kvm_vcpu *vcpu)
1288{
94dfbdb3 1289#ifdef CONFIG_X86_64
a2fa3e9f 1290 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1291#endif
6aa8b732
AK		 1292}
1293
0fe1e009 1294static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1295{
0fe1e009
TH		 1296 if (sd->next_asid > sd->max_asid) {
1297 ++sd->asid_generation;
1298 sd->next_asid = 1;
a2fa3e9f 1299 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1300 }
1301
0fe1e009
TH		 1302 svm->asid_generation = sd->asid_generation;
1303 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1304}
1305
c76de350 1306static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1307{
42dbaa5a 1308 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1309
1310 switch (dr) {
1311 case 0 ... 3:
c76de350 1312 *dest = vcpu->arch.db[dr];
42dbaa5a 1313 break;
c76de350
JK		 1314 case 4:
1315 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1316 return EMULATE_FAIL; /* will re-inject UD */
1317 /* fall through */
42dbaa5a
JK		 1318 case 6:
1319 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1320 *dest = vcpu->arch.dr6;
42dbaa5a 1321 else
c76de350 1322 *dest = svm->vmcb->save.dr6;
42dbaa5a 1323 break;
c76de350
JK		 1324 case 5:
1325 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1326 return EMULATE_FAIL; /* will re-inject UD */
1327 /* fall through */
42dbaa5a
JK		 1328 case 7:
1329 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1330 *dest = vcpu->arch.dr7;
42dbaa5a 1331 else
c76de350 1332 *dest = svm->vmcb->save.dr7;
42dbaa5a 1333 break;
42dbaa5a
JK		 1334 }
1335
c76de350 1336 return EMULATE_DONE;
6aa8b732
AK		 1337}
1338
c76de350 1339static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1340{
a2fa3e9f
GH		 1341 struct vcpu_svm *svm = to_svm(vcpu);
1342
6aa8b732
AK		 1343 switch (dr) {
1344 case 0 ... 3:
42dbaa5a
JK		 1345 vcpu->arch.db[dr] = value;
1346 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1347 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1348 break;
1349 case 4:
1350 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1351 return EMULATE_FAIL; /* will re-inject UD */
1352 /* fall through */
42dbaa5a 1353 case 6:
42dbaa5a 1354 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1355 break;
1356 case 5:
1357 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1358 return EMULATE_FAIL; /* will re-inject UD */
1359 /* fall through */
42dbaa5a 1360 case 7:
42dbaa5a
JK		 1361 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1362 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1363 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1364 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1365 }
c76de350 1366 break;
6aa8b732 1367 }
c76de350
JK		 1368
1369 return EMULATE_DONE;
6aa8b732
AK		 1370}
1371
851ba692 1372static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1373{
6aa8b732
AK		 1374 u64 fault_address;
1375 u32 error_code;
6aa8b732 1376
a2fa3e9f
GH		 1377 fault_address = svm->vmcb->control.exit_info_2;
1378 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1379
229456fc 1380 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1381 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1382 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1383 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1384}
1385
851ba692 1386static int db_interception(struct vcpu_svm *svm)
d0bfb940 1387{
851ba692
AK		 1388 struct kvm_run *kvm_run = svm->vcpu.run;
1389
d0bfb940 1390 if (!(svm->vcpu.guest_debug &
44c11430 1391 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1392 !svm->nmi_singlestep) {
d0bfb940
JK		 1393 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1394 return 1;
1395 }
44c11430 1396
6be7d306
JK		 1397 if (svm->nmi_singlestep) {
1398 svm->nmi_singlestep = false;
44c11430
GN		 1399 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1400 svm->vmcb->save.rflags &=
1401 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1402 update_db_intercept(&svm->vcpu);
1403 }
1404
1405 if (svm->vcpu.guest_debug &
e0231715 1406 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1407 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1408 kvm_run->debug.arch.pc =
1409 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1410 kvm_run->debug.arch.exception = DB_VECTOR;
1411 return 0;
1412 }
1413
1414 return 1;
d0bfb940
JK		 1415}
1416
851ba692 1417static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1418{
851ba692
AK		 1419 struct kvm_run *kvm_run = svm->vcpu.run;
1420
d0bfb940
JK		 1421 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1422 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1423 kvm_run->debug.arch.exception = BP_VECTOR;
1424 return 0;
1425}
1426
851ba692 1427static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1428{
1429 int er;
1430
851ba692 1431 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1432 if (er != EMULATE_DONE)
7ee5d940 1433 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1434 return 1;
1435}
1436
6b52d186 1437static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1438{
6b52d186 1439 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1440 u32 excp;
1441
1442 if (is_nested(svm)) {
1443 u32 h_excp, n_excp;
1444
1445 h_excp = svm->nested.hsave->control.intercept_exceptions;
1446 n_excp = svm->nested.intercept_exceptions;
1447 h_excp &= ~(1 << NM_VECTOR);
1448 excp = h_excp | n_excp;
1449 } else {
1450 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1451 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1452 }
1453
1454 svm->vmcb->control.intercept_exceptions = excp;
1455
e756fc62 1456 svm->vcpu.fpu_active = 1;
d225157b 1457 update_cr0_intercept(svm);
6b52d186 1458}
a2fa3e9f 1459
6b52d186
AK		 1460static int nm_interception(struct vcpu_svm *svm)
1461{
1462 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1463 return 1;
7807fa6c
AL		 1464}
1465
851ba692 1466static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1467{
1468 /*
1469 * On an #MC intercept the MCE handler is not called automatically in
1470 * the host. So do it by hand here.
1471 */
1472 asm volatile (
1473 "int $0x12\n");
1474 /* not sure if we ever come back to this point */
1475
1476 return 1;
1477}
1478
851ba692 1479static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1480{
851ba692
AK		 1481 struct kvm_run *kvm_run = svm->vcpu.run;
1482
46fe4ddd
JR		 1483 /*
1484 * VMCB is undefined after a SHUTDOWN intercept
1485 * so reinitialize it.
1486 */
a2fa3e9f 1487 clear_page(svm->vmcb);
e6101a96 1488 init_vmcb(svm);
46fe4ddd
JR		 1489
1490 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1491 return 0;
1492}
1493
851ba692 1494static int io_interception(struct vcpu_svm *svm)
6aa8b732 1495{
d77c26fc 1496 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1497 int size, in, string;
039576c0 1498 unsigned port;
6aa8b732 1499
e756fc62 1500 ++svm->vcpu.stat.io_exits;
6aa8b732 1501
a2fa3e9f 1502 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1503
e70669ab
LV		 1504 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1505
1506 if (string) {
3427318f 1507 if (emulate_instruction(&svm->vcpu,
851ba692 1508 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1509 return 0;
1510 return 1;
1511 }
1512
039576c0
AK		 1513 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1514 port = io_info >> 16;
1515 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1516
e93f36bc 1517 skip_emulated_instruction(&svm->vcpu);
851ba692 1518 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1519}
1520
851ba692 1521static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1522{
1523 return 1;
1524}
1525
851ba692 1526static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1527{
1528 ++svm->vcpu.stat.irq_exits;
1529 return 1;
1530}
1531
851ba692 1532static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1533{
1534 return 1;
1535}
1536
851ba692 1537static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1538{
5fdbf976 1539 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1540 skip_emulated_instruction(&svm->vcpu);
1541 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1542}
1543
851ba692 1544static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1545{
5fdbf976 1546 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1547 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1548 kvm_emulate_hypercall(&svm->vcpu);
1549 return 1;
02e235bc
AK		 1550}
1551
c0725420
AG		 1552static int nested_svm_check_permissions(struct vcpu_svm *svm)
1553{
f6801dff 1554 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1555 || !is_paging(&svm->vcpu)) {
1556 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1557 return 1;
1558 }
1559
1560 if (svm->vmcb->save.cpl) {
1561 kvm_inject_gp(&svm->vcpu, 0);
1562 return 1;
1563 }
1564
1565 return 0;
1566}
1567
cf74a78b
AG		 1568static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1569 bool has_error_code, u32 error_code)
1570{
b8e88bc8
JR		 1571 int vmexit;
1572
0295ad7d
JR		 1573 if (!is_nested(svm))
1574 return 0;
cf74a78b 1575
0295ad7d
JR		 1576 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1577 svm->vmcb->control.exit_code_hi = 0;
1578 svm->vmcb->control.exit_info_1 = error_code;
1579 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1580
b8e88bc8
JR		 1581 vmexit = nested_svm_intercept(svm);
1582 if (vmexit == NESTED_EXIT_DONE)
1583 svm->nested.exit_required = true;
1584
1585 return vmexit;
cf74a78b
AG		 1586}
1587
8fe54654
JR		 1588/* This function returns true if it is save to enable the irq window */
1589static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1590{
26666957 1591 if (!is_nested(svm))
8fe54654 1592 return true;
cf74a78b 1593
26666957 1594 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1595 return true;
cf74a78b 1596
26666957 1597 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1598 return false;
cf74a78b 1599
197717d5
JR		 1600 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1601 svm->vmcb->control.exit_info_1 = 0;
1602 svm->vmcb->control.exit_info_2 = 0;
26666957 1603
cd3ff653
JR		 1604 if (svm->nested.intercept & 1ULL) {
1605 /*
1606 * The #vmexit can't be emulated here directly because this
1607 * code path runs with irqs and preemtion disabled. A
1608 * #vmexit emulation might sleep. Only signal request for
1609 * the #vmexit here.
1610 */
1611 svm->nested.exit_required = true;
236649de 1612 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1613 return false;
cf74a78b
AG		 1614 }
1615
8fe54654 1616 return true;
cf74a78b
AG		 1617}
1618
887f500c
JR		 1619/* This function returns true if it is save to enable the nmi window */
1620static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1621{
1622 if (!is_nested(svm))
1623 return true;
1624
1625 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1626 return true;
1627
1628 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1629 svm->nested.exit_required = true;
1630
1631 return false;
1632}
1633
7597f129 1634static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1635{
1636 struct page *page;
1637
6c3bd3d7
JR		 1638 might_sleep();
1639
34f80cfa 1640 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1641 if (is_error_page(page))
1642 goto error;
1643
7597f129
JR		 1644 *_page = page;
1645
1646 return kmap(page);
34f80cfa
JR		 1647
1648error:
1649 kvm_release_page_clean(page);
1650 kvm_inject_gp(&svm->vcpu, 0);
1651
1652 return NULL;
1653}
1654
7597f129 1655static void nested_svm_unmap(struct page *page)
34f80cfa 1656{
7597f129 1657 kunmap(page);
34f80cfa
JR		 1658 kvm_release_page_dirty(page);
1659}
1660
d2477826 1661static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1662{
0d6b3537
JR		 1663 u32 offset, msr, value;
1664 int write, mask;
4c2161ae 1665
3d62d9aa 1666 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1667 return NESTED_EXIT_HOST;
3d62d9aa 1668
0d6b3537
JR		 1669 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1670 offset = svm_msrpm_offset(msr);
1671 write = svm->vmcb->control.exit_info_1 & 1;
1672 mask = 1 << ((2 * (msr & 0xf)) + write);
4c2161ae 1673
0d6b3537
JR		 1674 if (offset == MSR_INVALID)
1675 return NESTED_EXIT_DONE;
3d62d9aa 1676
0d6b3537
JR		 1677 /* Offset is in 32 bit units but need in 8 bit units */
1678 offset *= 4;
1679
1680 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1681 return NESTED_EXIT_DONE;
1682
1683 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1684}
1685
410e4d57 1686static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1687{
cf74a78b 1688 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1689
410e4d57
JR		 1690 switch (exit_code) {
1691 case SVM_EXIT_INTR:
1692 case SVM_EXIT_NMI:
1693 return NESTED_EXIT_HOST;
410e4d57 1694 case SVM_EXIT_NPF:
e0231715 1695 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1696 if (npt_enabled)
1697 return NESTED_EXIT_HOST;
1698 break;
410e4d57 1699 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1700 /* When we're shadowing, trap PFs */
410e4d57
JR		 1701 if (!npt_enabled)
1702 return NESTED_EXIT_HOST;
1703 break;
66a562f7
JR		 1704 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1705 nm_interception(svm);
1706 break;
410e4d57
JR		 1707 default:
1708 break;
cf74a78b
AG		 1709 }
1710
410e4d57
JR		 1711 return NESTED_EXIT_CONTINUE;
1712}
1713
1714/*
1715 * If this function returns true, this #vmexit was already handled
1716 */
b8e88bc8 1717static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1718{
1719 u32 exit_code = svm->vmcb->control.exit_code;
1720 int vmexit = NESTED_EXIT_HOST;
1721
cf74a78b 1722 switch (exit_code) {
9c4e40b9 1723 case SVM_EXIT_MSR:
3d62d9aa 1724 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1725 break;
cf74a78b
AG		 1726 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1727 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1728 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1729 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1730 break;
1731 }
1732 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1733 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1734 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1735 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1736 break;
1737 }
1738 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1739 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1740 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1741 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1742 break;
1743 }
1744 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1745 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1746 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1747 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1748 break;
1749 }
1750 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1751 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1752 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1753 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1754 break;
1755 }
1756 default: {
1757 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1758 if (svm->nested.intercept & exit_bits)
410e4d57 1759 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1760 }
1761 }
1762
b8e88bc8
JR		 1763 return vmexit;
1764}
1765
1766static int nested_svm_exit_handled(struct vcpu_svm *svm)
1767{
1768 int vmexit;
1769
1770 vmexit = nested_svm_intercept(svm);
1771
1772 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1773 nested_svm_vmexit(svm);
9c4e40b9
JR		 1774
1775 return vmexit;
cf74a78b
AG		 1776}
1777
0460a979
JR		 1778static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1779{
1780 struct vmcb_control_area *dst = &dst_vmcb->control;
1781 struct vmcb_control_area *from = &from_vmcb->control;
1782
1783 dst->intercept_cr_read = from->intercept_cr_read;
1784 dst->intercept_cr_write = from->intercept_cr_write;
1785 dst->intercept_dr_read = from->intercept_dr_read;
1786 dst->intercept_dr_write = from->intercept_dr_write;
1787 dst->intercept_exceptions = from->intercept_exceptions;
1788 dst->intercept = from->intercept;
1789 dst->iopm_base_pa = from->iopm_base_pa;
1790 dst->msrpm_base_pa = from->msrpm_base_pa;
1791 dst->tsc_offset = from->tsc_offset;
1792 dst->asid = from->asid;
1793 dst->tlb_ctl = from->tlb_ctl;
1794 dst->int_ctl = from->int_ctl;
1795 dst->int_vector = from->int_vector;
1796 dst->int_state = from->int_state;
1797 dst->exit_code = from->exit_code;
1798 dst->exit_code_hi = from->exit_code_hi;
1799 dst->exit_info_1 = from->exit_info_1;
1800 dst->exit_info_2 = from->exit_info_2;
1801 dst->exit_int_info = from->exit_int_info;
1802 dst->exit_int_info_err = from->exit_int_info_err;
1803 dst->nested_ctl = from->nested_ctl;
1804 dst->event_inj = from->event_inj;
1805 dst->event_inj_err = from->event_inj_err;
1806 dst->nested_cr3 = from->nested_cr3;
1807 dst->lbr_ctl = from->lbr_ctl;
1808}
1809
34f80cfa 1810static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1811{
34f80cfa 1812 struct vmcb *nested_vmcb;
e6aa9abd 1813 struct vmcb *hsave = svm->nested.hsave;
33740e40 1814 struct vmcb *vmcb = svm->vmcb;
7597f129 1815 struct page *page;
cf74a78b 1816
17897f36
JR		 1817 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1818 vmcb->control.exit_info_1,
1819 vmcb->control.exit_info_2,
1820 vmcb->control.exit_int_info,
1821 vmcb->control.exit_int_info_err);
1822
7597f129 1823 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1824 if (!nested_vmcb)
1825 return 1;
1826
06fc7772
JR		 1827 /* Exit nested SVM mode */
1828 svm->nested.vmcb = 0;
1829
cf74a78b 1830 /* Give the current vmcb to the guest */
33740e40
JR		 1831 disable_gif(svm);
1832
1833 nested_vmcb->save.es = vmcb->save.es;
1834 nested_vmcb->save.cs = vmcb->save.cs;
1835 nested_vmcb->save.ss = vmcb->save.ss;
1836 nested_vmcb->save.ds = vmcb->save.ds;
1837 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1838 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1839 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1840 if (npt_enabled)
1841 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1842 else
1843 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1844 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1845 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1846 nested_vmcb->save.rflags = vmcb->save.rflags;
1847 nested_vmcb->save.rip = vmcb->save.rip;
1848 nested_vmcb->save.rsp = vmcb->save.rsp;
1849 nested_vmcb->save.rax = vmcb->save.rax;
1850 nested_vmcb->save.dr7 = vmcb->save.dr7;
1851 nested_vmcb->save.dr6 = vmcb->save.dr6;
1852 nested_vmcb->save.cpl = vmcb->save.cpl;
1853
1854 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1855 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1856 nested_vmcb->control.int_state = vmcb->control.int_state;
1857 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1858 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1859 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1860 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1861 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1862 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1863
1864 /*
1865 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1866 * to make sure that we do not lose injected events. So check event_inj
1867 * here and copy it to exit_int_info if it is valid.
1868 * Exit_int_info and event_inj can't be both valid because the case
1869 * below only happens on a VMRUN instruction intercept which has
1870 * no valid exit_int_info set.
1871 */
1872 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1873 struct vmcb_control_area *nc = &nested_vmcb->control;
1874
1875 nc->exit_int_info = vmcb->control.event_inj;
1876 nc->exit_int_info_err = vmcb->control.event_inj_err;
1877 }
1878
33740e40
JR		 1879 nested_vmcb->control.tlb_ctl = 0;
1880 nested_vmcb->control.event_inj = 0;
1881 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1882
1883 /* We always set V_INTR_MASKING and remember the old value in hflags */
1884 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1885 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1886
cf74a78b 1887 /* Restore the original control entries */
0460a979 1888 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1889
219b65dc
AG		 1890 kvm_clear_exception_queue(&svm->vcpu);
1891 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1892
1893 /* Restore selected save entries */
1894 svm->vmcb->save.es = hsave->save.es;
1895 svm->vmcb->save.cs = hsave->save.cs;
1896 svm->vmcb->save.ss = hsave->save.ss;
1897 svm->vmcb->save.ds = hsave->save.ds;
1898 svm->vmcb->save.gdtr = hsave->save.gdtr;
1899 svm->vmcb->save.idtr = hsave->save.idtr;
1900 svm->vmcb->save.rflags = hsave->save.rflags;
1901 svm_set_efer(&svm->vcpu, hsave->save.efer);
1902 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1903 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1904 if (npt_enabled) {
1905 svm->vmcb->save.cr3 = hsave->save.cr3;
1906 svm->vcpu.arch.cr3 = hsave->save.cr3;
1907 } else {
1908 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1909 }
1910 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1911 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1912 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1913 svm->vmcb->save.dr7 = 0;
1914 svm->vmcb->save.cpl = 0;
1915 svm->vmcb->control.exit_int_info = 0;
1916
7597f129 1917 nested_svm_unmap(page);
cf74a78b
AG		 1918
1919 kvm_mmu_reset_context(&svm->vcpu);
1920 kvm_mmu_load(&svm->vcpu);
1921
1922 return 0;
1923}
3d6368ef 1924
9738b2c9 1925static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1926{
323c3d80
JR		 1927 /*
1928 * This function merges the msr permission bitmaps of kvm and the
1929 * nested vmcb. It is omptimized in that it only merges the parts where
1930 * the kvm msr permission bitmap may contain zero bits
1931 */
3d6368ef 1932 int i;
9738b2c9 1933
323c3d80
JR		 1934 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1935 return true;
9738b2c9 1936
323c3d80
JR		 1937 for (i = 0; i < MSRPM_OFFSETS; i++) {
1938 u32 value, p;
1939 u64 offset;
9738b2c9 1940
323c3d80
JR		 1941 if (msrpm_offsets[i] == 0xffffffff)
1942 break;
3d6368ef 1943
0d6b3537
JR		 1944 p = msrpm_offsets[i];
1945 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 1946
1947 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1948 return false;
1949
1950 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1951 }
1952
1953 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 1954
1955 return true;
3d6368ef
AG		 1956}
1957
9738b2c9 1958static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1959{
9738b2c9 1960 struct vmcb *nested_vmcb;
e6aa9abd 1961 struct vmcb *hsave = svm->nested.hsave;
defbba56 1962 struct vmcb *vmcb = svm->vmcb;
7597f129 1963 struct page *page;
06fc7772
JR		 1964 u64 vmcb_gpa;
1965
1966 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1967
7597f129 1968 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1969 if (!nested_vmcb)
1970 return false;
1971
ecf1405d 1972 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1973 nested_vmcb->save.rip,
1974 nested_vmcb->control.int_ctl,
1975 nested_vmcb->control.event_inj,
1976 nested_vmcb->control.nested_ctl);
1977
2e554e8d
JR		 1978 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1979 nested_vmcb->control.intercept_cr_write,
1980 nested_vmcb->control.intercept_exceptions,
1981 nested_vmcb->control.intercept);
1982
3d6368ef 1983 /* Clear internal status */
219b65dc
AG		 1984 kvm_clear_exception_queue(&svm->vcpu);
1985 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 1986
e0231715
JR		 1987 /*
1988 * Save the old vmcb, so we don't need to pick what we save, but can
1989 * restore everything when a VMEXIT occurs
1990 */
defbba56
JR		 1991 hsave->save.es = vmcb->save.es;
1992 hsave->save.cs = vmcb->save.cs;
1993 hsave->save.ss = vmcb->save.ss;
1994 hsave->save.ds = vmcb->save.ds;
1995 hsave->save.gdtr = vmcb->save.gdtr;
1996 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1997 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1998 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1999 hsave->save.cr4 = svm->vcpu.arch.cr4;
2000 hsave->save.rflags = vmcb->save.rflags;
2001 hsave->save.rip = svm->next_rip;
2002 hsave->save.rsp = vmcb->save.rsp;
2003 hsave->save.rax = vmcb->save.rax;
2004 if (npt_enabled)
2005 hsave->save.cr3 = vmcb->save.cr3;
2006 else
2007 hsave->save.cr3 = svm->vcpu.arch.cr3;
2008
0460a979 2009 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2010
2011 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2012 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2013 else
2014 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2015
2016 /* Load the nested guest state */
2017 svm->vmcb->save.es = nested_vmcb->save.es;
2018 svm->vmcb->save.cs = nested_vmcb->save.cs;
2019 svm->vmcb->save.ss = nested_vmcb->save.ss;
2020 svm->vmcb->save.ds = nested_vmcb->save.ds;
2021 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2022 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2023 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2024 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2025 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2026 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2027 if (npt_enabled) {
2028 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2029 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2030 } else
3d6368ef 2031 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2032
2033 /* Guest paging mode is active - reset mmu */
2034 kvm_mmu_reset_context(&svm->vcpu);
2035
defbba56 2036 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2037 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2038 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2039 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2040
3d6368ef
AG		 2041 /* In case we don't even reach vcpu_run, the fields are not updated */
2042 svm->vmcb->save.rax = nested_vmcb->save.rax;
2043 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2044 svm->vmcb->save.rip = nested_vmcb->save.rip;
2045 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2046 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2047 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2048
e6aa9abd 2049 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 2050
aad42c64
JR		 2051 /* cache intercepts */
2052 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2053 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2054 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2055 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2056 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2057 svm->nested.intercept = nested_vmcb->control.intercept;
2058
3d6368ef 2059 force_new_asid(&svm->vcpu);
3d6368ef 2060 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2061 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2062 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2063 else
2064 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2065
88ab24ad
JR		 2066 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2067 /* We only want the cr8 intercept bits of the guest */
2068 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2069 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2070 }
2071
e0231715
JR		 2072 /*
2073 * We don't want a nested guest to be more powerful than the guest, so
2074 * all intercepts are ORed
2075 */
88ab24ad
JR		 2076 svm->vmcb->control.intercept_cr_read |=
2077 nested_vmcb->control.intercept_cr_read;
2078 svm->vmcb->control.intercept_cr_write |=
2079 nested_vmcb->control.intercept_cr_write;
2080 svm->vmcb->control.intercept_dr_read |=
2081 nested_vmcb->control.intercept_dr_read;
2082 svm->vmcb->control.intercept_dr_write |=
2083 nested_vmcb->control.intercept_dr_write;
2084 svm->vmcb->control.intercept_exceptions |=
2085 nested_vmcb->control.intercept_exceptions;
2086
2087 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2088
2089 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2090 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2091 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2092 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2093 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2094 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2095
7597f129 2096 nested_svm_unmap(page);
9738b2c9 2097
06fc7772
JR		 2098 /* nested_vmcb is our indicator if nested SVM is activated */
2099 svm->nested.vmcb = vmcb_gpa;
2100
2af9194d 2101 enable_gif(svm);
3d6368ef 2102
9738b2c9 2103 return true;
3d6368ef
AG		 2104}
2105
9966bf68 2106static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2107{
2108 to_vmcb->save.fs = from_vmcb->save.fs;
2109 to_vmcb->save.gs = from_vmcb->save.gs;
2110 to_vmcb->save.tr = from_vmcb->save.tr;
2111 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2112 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2113 to_vmcb->save.star = from_vmcb->save.star;
2114 to_vmcb->save.lstar = from_vmcb->save.lstar;
2115 to_vmcb->save.cstar = from_vmcb->save.cstar;
2116 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2117 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2118 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2119 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2120}
2121
851ba692 2122static int vmload_interception(struct vcpu_svm *svm)
5542675b 2123{
9966bf68 2124 struct vmcb *nested_vmcb;
7597f129 2125 struct page *page;
9966bf68 2126
5542675b
AG		 2127 if (nested_svm_check_permissions(svm))
2128 return 1;
2129
2130 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2131 skip_emulated_instruction(&svm->vcpu);
2132
7597f129 2133 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2134 if (!nested_vmcb)
2135 return 1;
2136
2137 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2138 nested_svm_unmap(page);
5542675b
AG		 2139
2140 return 1;
2141}
2142
851ba692 2143static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2144{
9966bf68 2145 struct vmcb *nested_vmcb;
7597f129 2146 struct page *page;
9966bf68 2147
5542675b
AG		 2148 if (nested_svm_check_permissions(svm))
2149 return 1;
2150
2151 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2152 skip_emulated_instruction(&svm->vcpu);
2153
7597f129 2154 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2155 if (!nested_vmcb)
2156 return 1;
2157
2158 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2159 nested_svm_unmap(page);
5542675b
AG		 2160
2161 return 1;
2162}
2163
851ba692 2164static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2165{
3d6368ef
AG		 2166 if (nested_svm_check_permissions(svm))
2167 return 1;
2168
2169 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2170 skip_emulated_instruction(&svm->vcpu);
2171
9738b2c9 2172 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2173 return 1;
2174
9738b2c9 2175 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2176 goto failed;
2177
2178 return 1;
2179
2180failed:
2181
2182 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2183 svm->vmcb->control.exit_code_hi = 0;
2184 svm->vmcb->control.exit_info_1 = 0;
2185 svm->vmcb->control.exit_info_2 = 0;
2186
2187 nested_svm_vmexit(svm);
3d6368ef
AG		 2188
2189 return 1;
2190}
2191
851ba692 2192static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2193{
2194 if (nested_svm_check_permissions(svm))
2195 return 1;
2196
2197 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2198 skip_emulated_instruction(&svm->vcpu);
2199
2af9194d 2200 enable_gif(svm);
1371d904
AG		 2201
2202 return 1;
2203}
2204
851ba692 2205static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2206{
2207 if (nested_svm_check_permissions(svm))
2208 return 1;
2209
2210 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2211 skip_emulated_instruction(&svm->vcpu);
2212
2af9194d 2213 disable_gif(svm);
1371d904
AG		 2214
2215 /* After a CLGI no interrupts should come */
2216 svm_clear_vintr(svm);
2217 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2218
2219 return 1;
2220}
2221
851ba692 2222static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2223{
2224 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2225
ec1ff790
JR		 2226 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2227 vcpu->arch.regs[VCPU_REGS_RAX]);
2228
ff092385
AG		 2229 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2230 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2231
2232 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2233 skip_emulated_instruction(&svm->vcpu);
2234 return 1;
2235}
2236
532a46b9
JR		 2237static int skinit_interception(struct vcpu_svm *svm)
2238{
2239 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2240
2241 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2242 return 1;
2243}
2244
851ba692 2245static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2246{
7ee5d940 2247 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2248 return 1;
2249}
2250
851ba692 2251static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2252{
37817f29 2253 u16 tss_selector;
64a7ec06
GN		 2254 int reason;
2255 int int_type = svm->vmcb->control.exit_int_info &
2256 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2257 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2258 uint32_t type =
2259 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2260 uint32_t idt_v =
2261 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2262
2263 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2264
37817f29
IE		 2265 if (svm->vmcb->control.exit_info_2 &
2266 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2267 reason = TASK_SWITCH_IRET;
2268 else if (svm->vmcb->control.exit_info_2 &
2269 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2270 reason = TASK_SWITCH_JMP;
fe8e7f83 2271 else if (idt_v)
64a7ec06
GN		 2272 reason = TASK_SWITCH_GATE;
2273 else
2274 reason = TASK_SWITCH_CALL;
2275
fe8e7f83
GN		 2276 if (reason == TASK_SWITCH_GATE) {
2277 switch (type) {
2278 case SVM_EXITINTINFO_TYPE_NMI:
2279 svm->vcpu.arch.nmi_injected = false;
2280 break;
2281 case SVM_EXITINTINFO_TYPE_EXEPT:
2282 kvm_clear_exception_queue(&svm->vcpu);
2283 break;
2284 case SVM_EXITINTINFO_TYPE_INTR:
2285 kvm_clear_interrupt_queue(&svm->vcpu);
2286 break;
2287 default:
2288 break;
2289 }
2290 }
64a7ec06 2291
8317c298
GN		 2292 if (reason != TASK_SWITCH_GATE ||
2293 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2294 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2295 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2296 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2297
2298 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2299}
2300
851ba692 2301static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2302{
5fdbf976 2303 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2304 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2305 return 1;
6aa8b732
AK		 2306}
2307
851ba692 2308static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2309{
2310 ++svm->vcpu.stat.nmi_window_exits;
2311 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2312 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2313 return 1;
2314}
2315
851ba692 2316static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2317{
851ba692 2318 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2319 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2320 return 1;
2321}
2322
851ba692 2323static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2324{
851ba692 2325 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2326 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2327 return 1;
2328}
2329
851ba692 2330static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2331{
851ba692
AK		 2332 struct kvm_run *kvm_run = svm->vcpu.run;
2333
0a5fff19
GN		 2334 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2335 /* instruction emulation calls kvm_set_cr8() */
851ba692 2336 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2337 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2338 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2339 return 1;
95ba8273 2340 }
0a5fff19
GN		 2341 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2342 return 1;
1d075434
JR		 2343 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2344 return 0;
2345}
2346
6aa8b732
AK		 2347static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2348{
a2fa3e9f
GH		 2349 struct vcpu_svm *svm = to_svm(vcpu);
2350
6aa8b732 2351 switch (ecx) {
af24a4e4 2352 case MSR_IA32_TSC: {
20824f30 2353 u64 tsc_offset;
6aa8b732 2354
20824f30
JR		 2355 if (is_nested(svm))
2356 tsc_offset = svm->nested.hsave->control.tsc_offset;
2357 else
2358 tsc_offset = svm->vmcb->control.tsc_offset;
2359
2360 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2361 break;
2362 }
0e859cac 2363 case MSR_K6_STAR:
a2fa3e9f 2364 *data = svm->vmcb->save.star;
6aa8b732 2365 break;
0e859cac 2366#ifdef CONFIG_X86_64
6aa8b732 2367 case MSR_LSTAR:
a2fa3e9f 2368 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2369 break;
2370 case MSR_CSTAR:
a2fa3e9f 2371 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2372 break;
2373 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2374 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2375 break;
2376 case MSR_SYSCALL_MASK:
a2fa3e9f 2377 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2378 break;
2379#endif
2380 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2381 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2382 break;
2383 case MSR_IA32_SYSENTER_EIP:
017cb99e 2384 *data = svm->sysenter_eip;
6aa8b732
AK		 2385 break;
2386 case MSR_IA32_SYSENTER_ESP:
017cb99e 2387 *data = svm->sysenter_esp;
6aa8b732 2388 break;
e0231715
JR		 2389 /*
2390 * Nobody will change the following 5 values in the VMCB so we can
2391 * safely return them on rdmsr. They will always be 0 until LBRV is
2392 * implemented.
2393 */
a2938c80
JR		 2394 case MSR_IA32_DEBUGCTLMSR:
2395 *data = svm->vmcb->save.dbgctl;
2396 break;
2397 case MSR_IA32_LASTBRANCHFROMIP:
2398 *data = svm->vmcb->save.br_from;
2399 break;
2400 case MSR_IA32_LASTBRANCHTOIP:
2401 *data = svm->vmcb->save.br_to;
2402 break;
2403 case MSR_IA32_LASTINTFROMIP:
2404 *data = svm->vmcb->save.last_excp_from;
2405 break;
2406 case MSR_IA32_LASTINTTOIP:
2407 *data = svm->vmcb->save.last_excp_to;
2408 break;
b286d5d8 2409 case MSR_VM_HSAVE_PA:
e6aa9abd 2410 *data = svm->nested.hsave_msr;
b286d5d8 2411 break;
eb6f302e 2412 case MSR_VM_CR:
4a810181 2413 *data = svm->nested.vm_cr_msr;
eb6f302e 2414 break;
c8a73f18
AG		 2415 case MSR_IA32_UCODE_REV:
2416 *data = 0x01000065;
2417 break;
6aa8b732 2418 default:
3bab1f5d 2419 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2420 }
2421 return 0;
2422}
2423
851ba692 2424static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2425{
ad312c7c 2426 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2427 u64 data;
2428
59200273
AK		 2429 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2430 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2431 kvm_inject_gp(&svm->vcpu, 0);
59200273 2432 } else {
229456fc 2433 trace_kvm_msr_read(ecx, data);
af9ca2d7 2434
5fdbf976 2435 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2436 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2437 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2438 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2439 }
2440 return 1;
2441}
2442
4a810181
JR		 2443static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2444{
2445 struct vcpu_svm *svm = to_svm(vcpu);
2446 int svm_dis, chg_mask;
2447
2448 if (data & ~SVM_VM_CR_VALID_MASK)
2449 return 1;
2450
2451 chg_mask = SVM_VM_CR_VALID_MASK;
2452
2453 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2454 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2455
2456 svm->nested.vm_cr_msr &= ~chg_mask;
2457 svm->nested.vm_cr_msr |= (data & chg_mask);
2458
2459 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2460
2461 /* check for svm_disable while efer.svme is set */
2462 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2463 return 1;
2464
2465 return 0;
2466}
2467
6aa8b732
AK		 2468static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2469{
a2fa3e9f
GH		 2470 struct vcpu_svm *svm = to_svm(vcpu);
2471
6aa8b732 2472 switch (ecx) {
af24a4e4 2473 case MSR_IA32_TSC: {
20824f30
JR		 2474 u64 tsc_offset = data - native_read_tsc();
2475 u64 g_tsc_offset = 0;
2476
2477 if (is_nested(svm)) {
2478 g_tsc_offset = svm->vmcb->control.tsc_offset -
2479 svm->nested.hsave->control.tsc_offset;
2480 svm->nested.hsave->control.tsc_offset = tsc_offset;
2481 }
2482
2483 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2484
6aa8b732
AK		 2485 break;
2486 }
0e859cac 2487 case MSR_K6_STAR:
a2fa3e9f 2488 svm->vmcb->save.star = data;
6aa8b732 2489 break;
49b14f24 2490#ifdef CONFIG_X86_64
6aa8b732 2491 case MSR_LSTAR:
a2fa3e9f 2492 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2493 break;
2494 case MSR_CSTAR:
a2fa3e9f 2495 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2496 break;
2497 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2498 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2499 break;
2500 case MSR_SYSCALL_MASK:
a2fa3e9f 2501 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2502 break;
2503#endif
2504 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2505 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2506 break;
2507 case MSR_IA32_SYSENTER_EIP:
017cb99e 2508 svm->sysenter_eip = data;
a2fa3e9f 2509 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2510 break;
2511 case MSR_IA32_SYSENTER_ESP:
017cb99e 2512 svm->sysenter_esp = data;
a2fa3e9f 2513 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2514 break;
a2938c80 2515 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2516 if (!svm_has(SVM_FEATURE_LBRV)) {
2517 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2518 __func__, data);
24e09cbf
JR		 2519 break;
2520 }
2521 if (data & DEBUGCTL_RESERVED_BITS)
2522 return 1;
2523
2524 svm->vmcb->save.dbgctl = data;
2525 if (data & (1ULL<<0))
2526 svm_enable_lbrv(svm);
2527 else
2528 svm_disable_lbrv(svm);
a2938c80 2529 break;
b286d5d8 2530 case MSR_VM_HSAVE_PA:
e6aa9abd 2531 svm->nested.hsave_msr = data;
62b9abaa 2532 break;
3c5d0a44 2533 case MSR_VM_CR:
4a810181 2534 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2535 case MSR_VM_IGNNE:
3c5d0a44
AG		 2536 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2537 break;
6aa8b732 2538 default:
3bab1f5d 2539 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2540 }
2541 return 0;
2542}
2543
851ba692 2544static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2545{
ad312c7c 2546 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2547 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2548 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2549
af9ca2d7 2550
5fdbf976 2551 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2552 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2553 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2554 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2555 } else {
2556 trace_kvm_msr_write(ecx, data);
e756fc62 2557 skip_emulated_instruction(&svm->vcpu);
59200273 2558 }
6aa8b732
AK		 2559 return 1;
2560}
2561
851ba692 2562static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2563{
e756fc62 2564 if (svm->vmcb->control.exit_info_1)
851ba692 2565 return wrmsr_interception(svm);
6aa8b732 2566 else
851ba692 2567 return rdmsr_interception(svm);
6aa8b732
AK		 2568}
2569
851ba692 2570static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2571{
851ba692
AK		 2572 struct kvm_run *kvm_run = svm->vcpu.run;
2573
f0b85051 2574 svm_clear_vintr(svm);
85f455f7 2575 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2576 /*
2577 * If the user space waits to inject interrupts, exit as soon as
2578 * possible
2579 */
8061823a
GN		 2580 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2581 kvm_run->request_interrupt_window &&
2582 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2583 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2584 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2585 return 0;
2586 }
2587
2588 return 1;
2589}
2590
565d0998
ML		 2591static int pause_interception(struct vcpu_svm *svm)
2592{
2593 kvm_vcpu_on_spin(&(svm->vcpu));
2594 return 1;
2595}
2596
851ba692 2597static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2598 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2599 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2600 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2601 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2602 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2603 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2604 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2605 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2606 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2607 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2608 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2609 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2610 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2611 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2612 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2613 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2614 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2615 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2616 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2617 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2618 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2619 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2620 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2621 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2622 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2623 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2624 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2625 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2626 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2627 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2628 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2629 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2630 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2631 [SVM_EXIT_SMI] = nop_on_interception,
2632 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2633 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2634 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2635 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2636 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2637 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2638 [SVM_EXIT_HLT] = halt_interception,
a7052897 2639 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2640 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2641 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2642 [SVM_EXIT_MSR] = msr_interception,
2643 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2644 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2645 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2646 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2647 [SVM_EXIT_VMLOAD] = vmload_interception,
2648 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2649 [SVM_EXIT_STGI] = stgi_interception,
2650 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2651 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2652 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2653 [SVM_EXIT_MONITOR] = invalid_op_interception,
2654 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2655 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2656};
2657
851ba692 2658static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2659{
04d2cc77 2660 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2661 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2662 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2663
229456fc 2664 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2665
cd3ff653
JR		 2666 if (unlikely(svm->nested.exit_required)) {
2667 nested_svm_vmexit(svm);
2668 svm->nested.exit_required = false;
2669
2670 return 1;
2671 }
2672
cf74a78b 2673 if (is_nested(svm)) {
410e4d57
JR		 2674 int vmexit;
2675
d8cabddf
JR		 2676 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2677 svm->vmcb->control.exit_info_1,
2678 svm->vmcb->control.exit_info_2,
2679 svm->vmcb->control.exit_int_info,
2680 svm->vmcb->control.exit_int_info_err);
2681
410e4d57
JR		 2682 vmexit = nested_svm_exit_special(svm);
2683
2684 if (vmexit == NESTED_EXIT_CONTINUE)
2685 vmexit = nested_svm_exit_handled(svm);
2686
2687 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2688 return 1;
cf74a78b
AG		 2689 }
2690
a5c3832d
JR		 2691 svm_complete_interrupts(svm);
2692
888f9f3e 2693 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2694 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2695 if (npt_enabled)
709ddebf 2696 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2697
2698 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2699 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2700 kvm_run->fail_entry.hardware_entry_failure_reason
2701 = svm->vmcb->control.exit_code;
2702 return 0;
2703 }
2704
a2fa3e9f 2705 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2706 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2707 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2708 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2709 "exit_code 0x%x\n",
b8688d51 2710 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2711 exit_code);
2712
9d8f549d 2713 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2714 || !svm_exit_handlers[exit_code]) {
6aa8b732 2715 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2716 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2717 return 0;
2718 }
2719
851ba692 2720 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2721}
2722
2723static void reload_tss(struct kvm_vcpu *vcpu)
2724{
2725 int cpu = raw_smp_processor_id();
2726
0fe1e009
TH		 2727 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2728 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2729 load_TR_desc();
2730}
2731
e756fc62 2732static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2733{
2734 int cpu = raw_smp_processor_id();
2735
0fe1e009 2736 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2737
a2fa3e9f 2738 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2739 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2740 if (svm->asid_generation != sd->asid_generation)
2741 new_asid(svm, sd);
6aa8b732
AK		 2742}
2743
95ba8273
GN		 2744static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2745{
2746 struct vcpu_svm *svm = to_svm(vcpu);
2747
2748 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2749 vcpu->arch.hflags |= HF_NMI_MASK;
2750 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2751 ++vcpu->stat.nmi_injections;
2752}
6aa8b732 2753
85f455f7 2754static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2755{
2756 struct vmcb_control_area *control;
2757
229456fc 2758 trace_kvm_inj_virq(irq);
af9ca2d7 2759
fa89a817 2760 ++svm->vcpu.stat.irq_injections;
e756fc62 2761 control = &svm->vmcb->control;
85f455f7 2762 control->int_vector = irq;
6aa8b732
AK		 2763 control->int_ctl &= ~V_INTR_PRIO_MASK;
2764 control->int_ctl |= V_IRQ_MASK |
2765 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2766}
2767
66fd3f7f 2768static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2769{
2770 struct vcpu_svm *svm = to_svm(vcpu);
2771
2af9194d 2772 BUG_ON(!(gif_set(svm)));
cf74a78b 2773
219b65dc
AG		 2774 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2775 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2776}
2777
95ba8273 2778static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2779{
2780 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2781
88ab24ad
JR		 2782 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2783 return;
2784
95ba8273 2785 if (irr == -1)
aaacfc9a
JR		 2786 return;
2787
95ba8273
GN		 2788 if (tpr >= irr)
2789 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2790}
aaacfc9a 2791
95ba8273
GN		 2792static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2793{
2794 struct vcpu_svm *svm = to_svm(vcpu);
2795 struct vmcb *vmcb = svm->vmcb;
2796 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2797 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2798}
2799
3cfc3092
JK		 2800static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2801{
2802 struct vcpu_svm *svm = to_svm(vcpu);
2803
2804 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2805}
2806
2807static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2808{
2809 struct vcpu_svm *svm = to_svm(vcpu);
2810
2811 if (masked) {
2812 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2813 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2814 } else {
2815 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2816 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2817 }
2818}
2819
78646121
GN		 2820static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2821{
2822 struct vcpu_svm *svm = to_svm(vcpu);
2823 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2824 int ret;
2825
2826 if (!gif_set(svm) ||
2827 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2828 return 0;
2829
2830 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2831
2832 if (is_nested(svm))
2833 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2834
2835 return ret;
78646121
GN		 2836}
2837
9222be18 2838static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2839{
219b65dc 2840 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2841
e0231715
JR		 2842 /*
2843 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2844 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2845 * get that intercept, this function will be called again though and
2846 * we'll get the vintr intercept.
2847 */
8fe54654 2848 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2849 svm_set_vintr(svm);
2850 svm_inject_irq(svm, 0x0);
2851 }
85f455f7
ED		 2852}
2853
95ba8273 2854static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2855{
04d2cc77 2856 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2857
44c11430
GN		 2858 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2859 == HF_NMI_MASK)
2860 return; /* IRET will cause a vm exit */
2861
e0231715
JR		 2862 /*
2863 * Something prevents NMI from been injected. Single step over possible
2864 * problem (IRET or exception injection or interrupt shadow)
2865 */
887f500c
JR		 2866 if (gif_set(svm) && nested_svm_nmi(svm)) {
2867 svm->nmi_singlestep = true;
2868 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2869 update_db_intercept(vcpu);
2870 }
c1150d8c
DL		 2871}
2872
cbc94022
IE		 2873static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2874{
2875 return 0;
2876}
2877
d9e368d6
AK		 2878static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2879{
2880 force_new_asid(vcpu);
2881}
2882
04d2cc77
AK		 2883static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2884{
2885}
2886
d7bf8221
JR		 2887static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2888{
2889 struct vcpu_svm *svm = to_svm(vcpu);
2890
88ab24ad
JR		 2891 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2892 return;
2893
d7bf8221
JR		 2894 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2895 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2896 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2897 }
2898}
2899
649d6864
JR		 2900static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2901{
2902 struct vcpu_svm *svm = to_svm(vcpu);
2903 u64 cr8;
2904
88ab24ad
JR		 2905 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2906 return;
2907
649d6864
JR		 2908 cr8 = kvm_get_cr8(vcpu);
2909 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2910 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2911}
2912
9222be18
GN		 2913static void svm_complete_interrupts(struct vcpu_svm *svm)
2914{
2915 u8 vector;
2916 int type;
2917 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2918 unsigned int3_injected = svm->int3_injected;
2919
2920 svm->int3_injected = 0;
9222be18 2921
44c11430
GN		 2922 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2923 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2924
9222be18
GN		 2925 svm->vcpu.arch.nmi_injected = false;
2926 kvm_clear_exception_queue(&svm->vcpu);
2927 kvm_clear_interrupt_queue(&svm->vcpu);
2928
2929 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2930 return;
2931
2932 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2933 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2934
2935 switch (type) {
2936 case SVM_EXITINTINFO_TYPE_NMI:
2937 svm->vcpu.arch.nmi_injected = true;
2938 break;
2939 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2940 if (is_nested(svm))
2941 break;
66b7138f
JK		 2942 /*
2943 * In case of software exceptions, do not reinject the vector,
2944 * but re-execute the instruction instead. Rewind RIP first
2945 * if we emulated INT3 before.
2946 */
2947 if (kvm_exception_is_soft(vector)) {
2948 if (vector == BP_VECTOR && int3_injected &&
2949 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2950 kvm_rip_write(&svm->vcpu,
2951 kvm_rip_read(&svm->vcpu) -
2952 int3_injected);
9222be18 2953 break;
66b7138f 2954 }
9222be18
GN		 2955 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2956 u32 err = svm->vmcb->control.exit_int_info_err;
2957 kvm_queue_exception_e(&svm->vcpu, vector, err);
2958
2959 } else
2960 kvm_queue_exception(&svm->vcpu, vector);
2961 break;
2962 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2963 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2964 break;
2965 default:
2966 break;
2967 }
2968}
2969
80e31d4f
AK		 2970#ifdef CONFIG_X86_64
2971#define R "r"
2972#else
2973#define R "e"
2974#endif
2975
851ba692 2976static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2977{
a2fa3e9f 2978 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2979 u16 fs_selector;
2980 u16 gs_selector;
2981 u16 ldt_selector;
d9e368d6 2982
cd3ff653
JR		 2983 /*
2984 * A vmexit emulation is required before the vcpu can be executed
2985 * again.
2986 */
2987 if (unlikely(svm->nested.exit_required))
2988 return;
2989
5fdbf976
MT		 2990 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2991 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2992 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2993
e756fc62 2994 pre_svm_run(svm);
6aa8b732 2995
649d6864
JR		 2996 sync_lapic_to_cr8(vcpu);
2997
6aa8b732 2998 save_host_msrs(vcpu);
d6e88aec
AK		 2999 fs_selector = kvm_read_fs();
3000 gs_selector = kvm_read_gs();
3001 ldt_selector = kvm_read_ldt();
cda0ffdd 3002 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3003 /* required for live migration with NPT */
3004 if (npt_enabled)
3005 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3006
04d2cc77
AK		 3007 clgi();
3008
3009 local_irq_enable();
36241b8c 3010
6aa8b732 3011 asm volatile (
80e31d4f
AK		 3012 "push %%"R"bp; \n\t"
3013 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3014 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3015 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3016 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3017 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3018 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3019#ifdef CONFIG_X86_64
fb3f0f51
RR		 3020 "mov %c[r8](%[svm]), %%r8 \n\t"
3021 "mov %c[r9](%[svm]), %%r9 \n\t"
3022 "mov %c[r10](%[svm]), %%r10 \n\t"
3023 "mov %c[r11](%[svm]), %%r11 \n\t"
3024 "mov %c[r12](%[svm]), %%r12 \n\t"
3025 "mov %c[r13](%[svm]), %%r13 \n\t"
3026 "mov %c[r14](%[svm]), %%r14 \n\t"
3027 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3028#endif
3029
6aa8b732 3030 /* Enter guest mode */
80e31d4f
AK		 3031 "push %%"R"ax \n\t"
3032 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3033 __ex(SVM_VMLOAD) "\n\t"
3034 __ex(SVM_VMRUN) "\n\t"
3035 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3036 "pop %%"R"ax \n\t"
6aa8b732
AK		 3037
3038 /* Save guest registers, load host registers */
80e31d4f
AK		 3039 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3040 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3041 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3042 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3043 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3044 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3045#ifdef CONFIG_X86_64
fb3f0f51
RR		 3046 "mov %%r8, %c[r8](%[svm]) \n\t"
3047 "mov %%r9, %c[r9](%[svm]) \n\t"
3048 "mov %%r10, %c[r10](%[svm]) \n\t"
3049 "mov %%r11, %c[r11](%[svm]) \n\t"
3050 "mov %%r12, %c[r12](%[svm]) \n\t"
3051 "mov %%r13, %c[r13](%[svm]) \n\t"
3052 "mov %%r14, %c[r14](%[svm]) \n\t"
3053 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3054#endif
80e31d4f 3055 "pop %%"R"bp"
6aa8b732 3056 :
fb3f0f51 3057 : [svm]"a"(svm),
6aa8b732 3058 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3059 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3060 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3061 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3062 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3063 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3064 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3065#ifdef CONFIG_X86_64
ad312c7c
ZX		 3066 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3067 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3068 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3069 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3070 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3071 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3072 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3073 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3074#endif
54a08c04 3075 : "cc", "memory"
80e31d4f 3076 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3077#ifdef CONFIG_X86_64
54a08c04
LV		 3078 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3079#endif
3080 );
6aa8b732 3081
ad312c7c 3082 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3083 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3084 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3085 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3086
d6e88aec
AK		 3087 kvm_load_fs(fs_selector);
3088 kvm_load_gs(gs_selector);
3089 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3090 load_host_msrs(vcpu);
3091
3092 reload_tss(vcpu);
3093
56ba47dd
AK		 3094 local_irq_disable();
3095
3096 stgi();
3097
d7bf8221
JR		 3098 sync_cr8_to_lapic(vcpu);
3099
a2fa3e9f 3100 svm->next_rip = 0;
9222be18 3101
6de4f3ad
AK		 3102 if (npt_enabled) {
3103 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3104 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3105 }
6aa8b732
AK		 3106}
3107
80e31d4f
AK		 3108#undef R
3109
6aa8b732
AK		 3110static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3111{
a2fa3e9f
GH		 3112 struct vcpu_svm *svm = to_svm(vcpu);
3113
709ddebf
JR		 3114 if (npt_enabled) {
3115 svm->vmcb->control.nested_cr3 = root;
3116 force_new_asid(vcpu);
3117 return;
3118 }
3119
a2fa3e9f 3120 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3121 force_new_asid(vcpu);
3122}
3123
6aa8b732
AK		 3124static int is_disabled(void)
3125{
6031a61c
JR		 3126 u64 vm_cr;
3127
3128 rdmsrl(MSR_VM_CR, vm_cr);
3129 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3130 return 1;
3131
6aa8b732
AK		 3132 return 0;
3133}
3134
102d8325
IM		 3135static void
3136svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3137{
3138 /*
3139 * Patch in the VMMCALL instruction:
3140 */
3141 hypercall[0] = 0x0f;
3142 hypercall[1] = 0x01;
3143 hypercall[2] = 0xd9;
102d8325
IM		 3144}
3145
002c7f7c
YS		 3146static void svm_check_processor_compat(void *rtn)
3147{
3148 *(int *)rtn = 0;
3149}
3150
774ead3a
AK		 3151static bool svm_cpu_has_accelerated_tpr(void)
3152{
3153 return false;
3154}
3155
67253af5
SY		 3156static int get_npt_level(void)
3157{
3158#ifdef CONFIG_X86_64
3159 return PT64_ROOT_LEVEL;
3160#else
3161 return PT32E_ROOT_LEVEL;
3162#endif
3163}
3164
4b12f0de 3165static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3166{
3167 return 0;
3168}
3169
0e851880
SY		 3170static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3171{
3172}
3173
229456fc 3174static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3175 { SVM_EXIT_READ_CR0, "read_cr0" },
3176 { SVM_EXIT_READ_CR3, "read_cr3" },
3177 { SVM_EXIT_READ_CR4, "read_cr4" },
3178 { SVM_EXIT_READ_CR8, "read_cr8" },
3179 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3180 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3181 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3182 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3183 { SVM_EXIT_READ_DR0, "read_dr0" },
3184 { SVM_EXIT_READ_DR1, "read_dr1" },
3185 { SVM_EXIT_READ_DR2, "read_dr2" },
3186 { SVM_EXIT_READ_DR3, "read_dr3" },
3187 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3188 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3189 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3190 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3191 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3192 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3193 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3194 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3195 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3196 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3197 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3198 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3199 { SVM_EXIT_INTR, "interrupt" },
3200 { SVM_EXIT_NMI, "nmi" },
3201 { SVM_EXIT_SMI, "smi" },
3202 { SVM_EXIT_INIT, "init" },
3203 { SVM_EXIT_VINTR, "vintr" },
3204 { SVM_EXIT_CPUID, "cpuid" },
3205 { SVM_EXIT_INVD, "invd" },
3206 { SVM_EXIT_HLT, "hlt" },
3207 { SVM_EXIT_INVLPG, "invlpg" },
3208 { SVM_EXIT_INVLPGA, "invlpga" },
3209 { SVM_EXIT_IOIO, "io" },
3210 { SVM_EXIT_MSR, "msr" },
3211 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3212 { SVM_EXIT_SHUTDOWN, "shutdown" },
3213 { SVM_EXIT_VMRUN, "vmrun" },
3214 { SVM_EXIT_VMMCALL, "hypercall" },
3215 { SVM_EXIT_VMLOAD, "vmload" },
3216 { SVM_EXIT_VMSAVE, "vmsave" },
3217 { SVM_EXIT_STGI, "stgi" },
3218 { SVM_EXIT_CLGI, "clgi" },
3219 { SVM_EXIT_SKINIT, "skinit" },
3220 { SVM_EXIT_WBINVD, "wbinvd" },
3221 { SVM_EXIT_MONITOR, "monitor" },
3222 { SVM_EXIT_MWAIT, "mwait" },
3223 { SVM_EXIT_NPF, "npf" },
3224 { -1, NULL }
3225};
3226
17cc3935 3227static int svm_get_lpage_level(void)
344f414f 3228{
17cc3935 3229 return PT_PDPE_LEVEL;
344f414f
JR		 3230}
3231
4e47c7a6
SY		 3232static bool svm_rdtscp_supported(void)
3233{
3234 return false;
3235}
3236
02daab21
AK		 3237static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3238{
3239 struct vcpu_svm *svm = to_svm(vcpu);
3240
02daab21 3241 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3242 if (is_nested(svm))
3243 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3244 update_cr0_intercept(svm);
02daab21
AK		 3245}
3246
cbdd1bea 3247static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3248 .cpu_has_kvm_support = has_svm,
3249 .disabled_by_bios = is_disabled,
3250 .hardware_setup = svm_hardware_setup,
3251 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3252 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3253 .hardware_enable = svm_hardware_enable,
3254 .hardware_disable = svm_hardware_disable,
774ead3a 3255 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3256
3257 .vcpu_create = svm_create_vcpu,
3258 .vcpu_free = svm_free_vcpu,
04d2cc77 3259 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3260
04d2cc77 3261 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3262 .vcpu_load = svm_vcpu_load,
3263 .vcpu_put = svm_vcpu_put,
3264
3265 .set_guest_debug = svm_guest_debug,
3266 .get_msr = svm_get_msr,
3267 .set_msr = svm_set_msr,
3268 .get_segment_base = svm_get_segment_base,
3269 .get_segment = svm_get_segment,
3270 .set_segment = svm_set_segment,
2e4d2653 3271 .get_cpl = svm_get_cpl,
1747fb71 3272 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3273 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3274 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3275 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3276 .set_cr3 = svm_set_cr3,
3277 .set_cr4 = svm_set_cr4,
3278 .set_efer = svm_set_efer,
3279 .get_idt = svm_get_idt,
3280 .set_idt = svm_set_idt,
3281 .get_gdt = svm_get_gdt,
3282 .set_gdt = svm_set_gdt,
3283 .get_dr = svm_get_dr,
3284 .set_dr = svm_set_dr,
6de4f3ad 3285 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3286 .get_rflags = svm_get_rflags,
3287 .set_rflags = svm_set_rflags,
6b52d186 3288 .fpu_activate = svm_fpu_activate,
02daab21 3289 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3290
6aa8b732 3291 .tlb_flush = svm_flush_tlb,
6aa8b732 3292
6aa8b732 3293 .run = svm_vcpu_run,
04d2cc77 3294 .handle_exit = handle_exit,
6aa8b732 3295 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3296 .set_interrupt_shadow = svm_set_interrupt_shadow,
3297 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3298 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3299 .set_irq = svm_set_irq,
95ba8273 3300 .set_nmi = svm_inject_nmi,
298101da 3301 .queue_exception = svm_queue_exception,
78646121 3302 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3303 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3304 .get_nmi_mask = svm_get_nmi_mask,
3305 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3306 .enable_nmi_window = enable_nmi_window,
3307 .enable_irq_window = enable_irq_window,
3308 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3309
3310 .set_tss_addr = svm_set_tss_addr,
67253af5 3311 .get_tdp_level = get_npt_level,
4b12f0de 3312 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3313
3314 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3315 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3316
3317 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3318
3319 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3320};
3321
3322static int __init svm_init(void)
3323{
cb498ea2 3324 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3325 THIS_MODULE);
6aa8b732
AK		 3326}
3327
3328static void __exit svm_exit(void)
3329{
cb498ea2 3330 kvm_exit();
6aa8b732
AK		 3331}
3332
3333module_init(svm_init)
3334module_exit(svm_exit)
Linux kernel - Deliverables
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