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KVM: SVM: Add function to recalculate intercept masks
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
9611c187 7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
631bc487 34#include <asm/kvm_para.h>
6aa8b732 35
63d1142f 36#include <asm/virtext.h>
229456fc 37#include "trace.h"
63d1142f 38
4ecac3fd
AK		 39#define __ex(x) __kvm_handle_fault_on_reboot(x)
40
6aa8b732
AK		 41MODULE_AUTHOR("Qumranet");
42MODULE_LICENSE("GPL");
43
44#define IOPM_ALLOC_ORDER 2
45#define MSRPM_ALLOC_ORDER 1
46
6aa8b732
AK		 47#define SEG_TYPE_LDT 2
48#define SEG_TYPE_BUSY_TSS16 3
49
6bc31bdc
AP		 50#define SVM_FEATURE_NPT (1 << 0)
51#define SVM_FEATURE_LBRV (1 << 1)
52#define SVM_FEATURE_SVML (1 << 2)
53#define SVM_FEATURE_NRIP (1 << 3)
54#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 55
410e4d57
JR		 56#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59
24e09cbf
JR		 60#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61
67ec6607
JR		 62static bool erratum_383_found __read_mostly;
63
6c8166a7
AK		 64static const u32 host_save_user_msrs[] = {
65#ifdef CONFIG_X86_64
66 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
67 MSR_FS_BASE,
68#endif
69 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
70};
71
72#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
73
74struct kvm_vcpu;
75
e6aa9abd
JR		 76struct nested_state {
77 struct vmcb *hsave;
78 u64 hsave_msr;
4a810181 79 u64 vm_cr_msr;
e6aa9abd
JR		 80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
ce2ac085 87 u64 vmcb_iopm;
aad42c64 88
cd3ff653
JR		 89 /* A VMEXIT is required but not yet emulated */
90 bool exit_required;
91
cda00082
JR		 92 /*
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
95 */
96 unsigned long vmexit_rip;
97 unsigned long vmexit_rsp;
98 unsigned long vmexit_rax;
99
aad42c64
JR		 100 /* cache for intercepts of the guest */
101 u16 intercept_cr_read;
102 u16 intercept_cr_write;
103 u16 intercept_dr_read;
104 u16 intercept_dr_write;
105 u32 intercept_exceptions;
106 u64 intercept;
107
5bd2edc3
JR		 108 /* Nested Paging related state */
109 u64 nested_cr3;
e6aa9abd
JR		 110};
111
323c3d80
JR		 112#define MSRPM_OFFSETS 16
113static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
114
6c8166a7
AK		 115struct vcpu_svm {
116 struct kvm_vcpu vcpu;
117 struct vmcb *vmcb;
118 unsigned long vmcb_pa;
119 struct svm_cpu_data *svm_data;
120 uint64_t asid_generation;
121 uint64_t sysenter_esp;
122 uint64_t sysenter_eip;
123
124 u64 next_rip;
125
126 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
afe9e66f 127 struct {
dacccfdd
AK		 128 u16 fs;
129 u16 gs;
130 u16 ldt;
afe9e66f
AK		 131 u64 gs_base;
132 } host;
6c8166a7
AK		 133
134 u32 *msrpm;
6c8166a7 135
e6aa9abd 136 struct nested_state nested;
6be7d306
JK		 137
138 bool nmi_singlestep;
66b7138f
JK		 139
140 unsigned int3_injected;
141 unsigned long int3_rip;
631bc487 142 u32 apf_reason;
6c8166a7
AK		 143};
144
455716fa
JR		 145#define MSR_INVALID 0xffffffffU
146
ac72a9b7
JR		 147static struct svm_direct_access_msrs {
148 u32 index; /* Index of the MSR */
149 bool always; /* True if intercept is always on */
150} direct_access_msrs[] = {
8c06585d 151 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 152 { .index = MSR_IA32_SYSENTER_CS, .always = true },
153#ifdef CONFIG_X86_64
154 { .index = MSR_GS_BASE, .always = true },
155 { .index = MSR_FS_BASE, .always = true },
156 { .index = MSR_KERNEL_GS_BASE, .always = true },
157 { .index = MSR_LSTAR, .always = true },
158 { .index = MSR_CSTAR, .always = true },
159 { .index = MSR_SYSCALL_MASK, .always = true },
160#endif
161 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
162 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
163 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
164 { .index = MSR_IA32_LASTINTTOIP, .always = false },
165 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 166};
167
709ddebf
JR		 168/* enable NPT for AMD64 and X86 with PAE */
169#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
170static bool npt_enabled = true;
171#else
e0231715 172static bool npt_enabled;
709ddebf 173#endif
6c7dac72
JR		 174static int npt = 1;
175
176module_param(npt, int, S_IRUGO);
e3da3acd 177
4b6e4dca 178static int nested = 1;
236de055
AG		 179module_param(nested, int, S_IRUGO);
180
44874f84 181static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 182static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 183
410e4d57 184static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 185static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 186static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 187static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
188 bool has_error_code, u32 error_code);
189
a2fa3e9f
GH		 190static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
191{
fb3f0f51 192 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 193}
194
384c6368
JR		 195static void recalc_intercepts(struct vcpu_svm *svm)
196{
197 struct vmcb_control_area *c, *h;
198 struct nested_state *g;
199
200 if (!is_guest_mode(&svm->vcpu))
201 return;
202
203 c = &svm->vmcb->control;
204 h = &svm->nested.hsave->control;
205 g = &svm->nested;
206
207 c->intercept_cr_read = h->intercept_cr_read | g->intercept_cr_read;
208 c->intercept_cr_write = h->intercept_cr_write | g->intercept_cr_write;
209 c->intercept_dr_read = h->intercept_dr_read | g->intercept_dr_read;
210 c->intercept_dr_write = h->intercept_dr_write | g->intercept_dr_write;
211 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
212 c->intercept = h->intercept | g->intercept;
213}
214
2af9194d
JR		 215static inline void enable_gif(struct vcpu_svm *svm)
216{
217 svm->vcpu.arch.hflags |= HF_GIF_MASK;
218}
219
220static inline void disable_gif(struct vcpu_svm *svm)
221{
222 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
223}
224
225static inline bool gif_set(struct vcpu_svm *svm)
226{
227 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
228}
229
4866d5e3 230static unsigned long iopm_base;
6aa8b732
AK		 231
232struct kvm_ldttss_desc {
233 u16 limit0;
234 u16 base0;
e0231715
JR		 235 unsigned base1:8, type:5, dpl:2, p:1;
236 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 237 u32 base3;
238 u32 zero1;
239} __attribute__((packed));
240
241struct svm_cpu_data {
242 int cpu;
243
5008fdf5
AK		 244 u64 asid_generation;
245 u32 max_asid;
246 u32 next_asid;
6aa8b732
AK		 247 struct kvm_ldttss_desc *tss_desc;
248
249 struct page *save_area;
250};
251
252static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 253static uint32_t svm_features;
6aa8b732
AK		 254
255struct svm_init_data {
256 int cpu;
257 int r;
258};
259
260static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
261
9d8f549d 262#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 263#define MSRS_RANGE_SIZE 2048
264#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
265
455716fa
JR		 266static u32 svm_msrpm_offset(u32 msr)
267{
268 u32 offset;
269 int i;
270
271 for (i = 0; i < NUM_MSR_MAPS; i++) {
272 if (msr < msrpm_ranges[i] ||
273 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
274 continue;
275
276 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
277 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
278
279 /* Now we have the u8 offset - but need the u32 offset */
280 return offset / 4;
281 }
282
283 /* MSR not in any range */
284 return MSR_INVALID;
285}
286
6aa8b732
AK		 287#define MAX_INST_SIZE 15
288
6aa8b732
AK		 289static inline void clgi(void)
290{
4ecac3fd 291 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 292}
293
294static inline void stgi(void)
295{
4ecac3fd 296 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 297}
298
299static inline void invlpga(unsigned long addr, u32 asid)
300{
e0231715 301 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 302}
303
6aa8b732
AK		 304static inline void force_new_asid(struct kvm_vcpu *vcpu)
305{
a2fa3e9f 306 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 307}
308
309static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
310{
311 force_new_asid(vcpu);
312}
313
4b16184c
JR		 314static int get_npt_level(void)
315{
316#ifdef CONFIG_X86_64
317 return PT64_ROOT_LEVEL;
318#else
319 return PT32E_ROOT_LEVEL;
320#endif
321}
322
6aa8b732
AK		 323static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
324{
6dc696d4 325 vcpu->arch.efer = efer;
709ddebf 326 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 327 efer &= ~EFER_LME;
6aa8b732 328
9962d032 329 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 330}
331
6aa8b732
AK		 332static int is_external_interrupt(u32 info)
333{
334 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
335 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
336}
337
2809f5d2
GC		 338static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
339{
340 struct vcpu_svm *svm = to_svm(vcpu);
341 u32 ret = 0;
342
343 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 344 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 345 return ret & mask;
346}
347
348static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
349{
350 struct vcpu_svm *svm = to_svm(vcpu);
351
352 if (mask == 0)
353 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
354 else
355 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
356
357}
358
6aa8b732
AK		 359static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
360{
a2fa3e9f
GH		 361 struct vcpu_svm *svm = to_svm(vcpu);
362
6bc31bdc
AP		 363 if (svm->vmcb->control.next_rip != 0)
364 svm->next_rip = svm->vmcb->control.next_rip;
365
a2fa3e9f 366 if (!svm->next_rip) {
851ba692 367 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 368 EMULATE_DONE)
369 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 370 return;
371 }
5fdbf976
MT		 372 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
373 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
374 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 375
5fdbf976 376 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 377 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 378}
379
116a4752 380static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 381 bool has_error_code, u32 error_code,
382 bool reinject)
116a4752
JK		 383{
384 struct vcpu_svm *svm = to_svm(vcpu);
385
e0231715
JR		 386 /*
387 * If we are within a nested VM we'd better #VMEXIT and let the guest
388 * handle the exception
389 */
ce7ddec4
JR		 390 if (!reinject &&
391 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 392 return;
393
2a6b20b8 394 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
66b7138f
JK		 395 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
396
397 /*
398 * For guest debugging where we have to reinject #BP if some
399 * INT3 is guest-owned:
400 * Emulate nRIP by moving RIP forward. Will fail if injection
401 * raises a fault that is not intercepted. Still better than
402 * failing in all cases.
403 */
404 skip_emulated_instruction(&svm->vcpu);
405 rip = kvm_rip_read(&svm->vcpu);
406 svm->int3_rip = rip + svm->vmcb->save.cs.base;
407 svm->int3_injected = rip - old_rip;
408 }
409
116a4752
JK		 410 svm->vmcb->control.event_inj = nr
411 | SVM_EVTINJ_VALID
412 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
413 | SVM_EVTINJ_TYPE_EXEPT;
414 svm->vmcb->control.event_inj_err = error_code;
415}
416
67ec6607
JR		 417static void svm_init_erratum_383(void)
418{
419 u32 low, high;
420 int err;
421 u64 val;
422
1be85a6d 423 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 424 return;
425
426 /* Use _safe variants to not break nested virtualization */
427 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
428 if (err)
429 return;
430
431 val |= (1ULL << 47);
432
433 low = lower_32_bits(val);
434 high = upper_32_bits(val);
435
436 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
437
438 erratum_383_found = true;
439}
440
6aa8b732
AK		 441static int has_svm(void)
442{
63d1142f 443 const char *msg;
6aa8b732 444
63d1142f 445 if (!cpu_has_svm(&msg)) {
ff81ff10 446 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 447 return 0;
448 }
449
6aa8b732
AK		 450 return 1;
451}
452
453static void svm_hardware_disable(void *garbage)
454{
2c8dceeb 455 cpu_svm_disable();
6aa8b732
AK		 456}
457
10474ae8 458static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 459{
460
0fe1e009 461 struct svm_cpu_data *sd;
6aa8b732 462 uint64_t efer;
89a27f4d 463 struct desc_ptr gdt_descr;
6aa8b732
AK		 464 struct desc_struct *gdt;
465 int me = raw_smp_processor_id();
466
10474ae8
AG		 467 rdmsrl(MSR_EFER, efer);
468 if (efer & EFER_SVME)
469 return -EBUSY;
470
6aa8b732 471 if (!has_svm()) {
e6732a5a
ZA		 472 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
473 me);
10474ae8 474 return -EINVAL;
6aa8b732 475 }
0fe1e009 476 sd = per_cpu(svm_data, me);
6aa8b732 477
0fe1e009 478 if (!sd) {
e6732a5a 479 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 480 me);
10474ae8 481 return -EINVAL;
6aa8b732
AK		 482 }
483
0fe1e009
TH		 484 sd->asid_generation = 1;
485 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
486 sd->next_asid = sd->max_asid + 1;
6aa8b732 487
d6ab1ed4 488 native_store_gdt(&gdt_descr);
89a27f4d 489 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 490 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 491
9962d032 492 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 493
d0316554 494 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 495
67ec6607
JR		 496 svm_init_erratum_383();
497
10474ae8 498 return 0;
6aa8b732
AK		 499}
500
0da1db75
JR		 501static void svm_cpu_uninit(int cpu)
502{
0fe1e009 503 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 504
0fe1e009 505 if (!sd)
0da1db75
JR		 506 return;
507
508 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 509 __free_page(sd->save_area);
510 kfree(sd);
0da1db75
JR		 511}
512
6aa8b732
AK		 513static int svm_cpu_init(int cpu)
514{
0fe1e009 515 struct svm_cpu_data *sd;
6aa8b732
AK		 516 int r;
517
0fe1e009
TH		 518 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
519 if (!sd)
6aa8b732 520 return -ENOMEM;
0fe1e009
TH		 521 sd->cpu = cpu;
522 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 523 r = -ENOMEM;
0fe1e009 524 if (!sd->save_area)
6aa8b732
AK		 525 goto err_1;
526
0fe1e009 527 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 528
529 return 0;
530
531err_1:
0fe1e009 532 kfree(sd);
6aa8b732
AK		 533 return r;
534
535}
536
ac72a9b7
JR		 537static bool valid_msr_intercept(u32 index)
538{
539 int i;
540
541 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
542 if (direct_access_msrs[i].index == index)
543 return true;
544
545 return false;
546}
547
bfc733a7
RR		 548static void set_msr_interception(u32 *msrpm, unsigned msr,
549 int read, int write)
6aa8b732 550{
455716fa
JR		 551 u8 bit_read, bit_write;
552 unsigned long tmp;
553 u32 offset;
6aa8b732 554
ac72a9b7
JR		 555 /*
556 * If this warning triggers extend the direct_access_msrs list at the
557 * beginning of the file
558 */
559 WARN_ON(!valid_msr_intercept(msr));
560
455716fa
JR		 561 offset = svm_msrpm_offset(msr);
562 bit_read = 2 * (msr & 0x0f);
563 bit_write = 2 * (msr & 0x0f) + 1;
564 tmp = msrpm[offset];
565
566 BUG_ON(offset == MSR_INVALID);
567
568 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
569 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
570
571 msrpm[offset] = tmp;
6aa8b732
AK		 572}
573
f65c229c 574static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 575{
576 int i;
577
f65c229c
JR		 578 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
579
ac72a9b7
JR		 580 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
581 if (!direct_access_msrs[i].always)
582 continue;
583
584 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
585 }
f65c229c
JR		 586}
587
323c3d80
JR		 588static void add_msr_offset(u32 offset)
589{
590 int i;
591
592 for (i = 0; i < MSRPM_OFFSETS; ++i) {
593
594 /* Offset already in list? */
595 if (msrpm_offsets[i] == offset)
bfc733a7 596 return;
323c3d80
JR		 597
598 /* Slot used by another offset? */
599 if (msrpm_offsets[i] != MSR_INVALID)
600 continue;
601
602 /* Add offset to list */
603 msrpm_offsets[i] = offset;
604
605 return;
6aa8b732 606 }
323c3d80
JR		 607
608 /*
609 * If this BUG triggers the msrpm_offsets table has an overflow. Just
610 * increase MSRPM_OFFSETS in this case.
611 */
bfc733a7 612 BUG();
6aa8b732
AK		 613}
614
323c3d80 615static void init_msrpm_offsets(void)
f65c229c 616{
323c3d80 617 int i;
f65c229c 618
323c3d80
JR		 619 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
620
621 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
622 u32 offset;
623
624 offset = svm_msrpm_offset(direct_access_msrs[i].index);
625 BUG_ON(offset == MSR_INVALID);
626
627 add_msr_offset(offset);
628 }
f65c229c
JR		 629}
630
24e09cbf
JR		 631static void svm_enable_lbrv(struct vcpu_svm *svm)
632{
633 u32 *msrpm = svm->msrpm;
634
635 svm->vmcb->control.lbr_ctl = 1;
636 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
637 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
638 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
639 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
640}
641
642static void svm_disable_lbrv(struct vcpu_svm *svm)
643{
644 u32 *msrpm = svm->msrpm;
645
646 svm->vmcb->control.lbr_ctl = 0;
647 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
648 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
649 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
650 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
651}
652
6aa8b732
AK		 653static __init int svm_hardware_setup(void)
654{
655 int cpu;
656 struct page *iopm_pages;
f65c229c 657 void *iopm_va;
6aa8b732
AK		 658 int r;
659
6aa8b732
AK		 660 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
661
662 if (!iopm_pages)
663 return -ENOMEM;
c8681339
AL		 664
665 iopm_va = page_address(iopm_pages);
666 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 667 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
668
323c3d80
JR		 669 init_msrpm_offsets();
670
50a37eb4
JR		 671 if (boot_cpu_has(X86_FEATURE_NX))
672 kvm_enable_efer_bits(EFER_NX);
673
1b2fd70c
AG		 674 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
675 kvm_enable_efer_bits(EFER_FFXSR);
676
236de055
AG		 677 if (nested) {
678 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 679 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 680 }
681
3230bb47 682 for_each_possible_cpu(cpu) {
6aa8b732
AK		 683 r = svm_cpu_init(cpu);
684 if (r)
f65c229c 685 goto err;
6aa8b732 686 }
33bd6a0b
JR		 687
688 svm_features = cpuid_edx(SVM_CPUID_FUNC);
689
2a6b20b8 690 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 691 npt_enabled = false;
692
6c7dac72
JR		 693 if (npt_enabled && !npt) {
694 printk(KERN_INFO "kvm: Nested Paging disabled\n");
695 npt_enabled = false;
696 }
697
18552672 698 if (npt_enabled) {
e3da3acd 699 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 700 kvm_enable_tdp();
5f4cb662
JR		 701 } else
702 kvm_disable_tdp();
e3da3acd 703
6aa8b732
AK		 704 return 0;
705
f65c229c 706err:
6aa8b732
AK		 707 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
708 iopm_base = 0;
709 return r;
710}
711
712static __exit void svm_hardware_unsetup(void)
713{
0da1db75
JR		 714 int cpu;
715
3230bb47 716 for_each_possible_cpu(cpu)
0da1db75
JR		 717 svm_cpu_uninit(cpu);
718
6aa8b732 719 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 720 iopm_base = 0;
6aa8b732
AK		 721}
722
723static void init_seg(struct vmcb_seg *seg)
724{
725 seg->selector = 0;
726 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 727 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 728 seg->limit = 0xffff;
729 seg->base = 0;
730}
731
732static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
733{
734 seg->selector = 0;
735 seg->attrib = SVM_SELECTOR_P_MASK | type;
736 seg->limit = 0xffff;
737 seg->base = 0;
738}
739
f4e1b3c8
ZA		 740static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
741{
742 struct vcpu_svm *svm = to_svm(vcpu);
743 u64 g_tsc_offset = 0;
744
2030753d 745 if (is_guest_mode(vcpu)) {
f4e1b3c8
ZA		 746 g_tsc_offset = svm->vmcb->control.tsc_offset -
747 svm->nested.hsave->control.tsc_offset;
748 svm->nested.hsave->control.tsc_offset = offset;
749 }
750
751 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
752}
753
e48672fa
ZA		 754static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
755{
756 struct vcpu_svm *svm = to_svm(vcpu);
757
758 svm->vmcb->control.tsc_offset += adjustment;
2030753d 759 if (is_guest_mode(vcpu))
e48672fa
ZA		 760 svm->nested.hsave->control.tsc_offset += adjustment;
761}
762
e6101a96 763static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 764{
e6101a96
JR		 765 struct vmcb_control_area *control = &svm->vmcb->control;
766 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 767
bff78274
AK		 768 svm->vcpu.fpu_active = 1;
769
e0231715 770 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 771 INTERCEPT_CR3_MASK |
649d6864 772 INTERCEPT_CR4_MASK;
6aa8b732 773
e0231715 774 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 775 INTERCEPT_CR3_MASK |
80a8119c
AK		 776 INTERCEPT_CR4_MASK |
777 INTERCEPT_CR8_MASK;
6aa8b732 778
e0231715 779 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 780 INTERCEPT_DR1_MASK |
781 INTERCEPT_DR2_MASK |
727f5a23
JK		 782 INTERCEPT_DR3_MASK |
783 INTERCEPT_DR4_MASK |
784 INTERCEPT_DR5_MASK |
785 INTERCEPT_DR6_MASK |
786 INTERCEPT_DR7_MASK;
6aa8b732 787
e0231715 788 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 789 INTERCEPT_DR1_MASK |
790 INTERCEPT_DR2_MASK |
791 INTERCEPT_DR3_MASK |
727f5a23 792 INTERCEPT_DR4_MASK |
6aa8b732 793 INTERCEPT_DR5_MASK |
727f5a23 794 INTERCEPT_DR6_MASK |
6aa8b732
AK		 795 INTERCEPT_DR7_MASK;
796
7aa81cc0 797 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 798 (1 << UD_VECTOR) |
799 (1 << MC_VECTOR);
6aa8b732
AK		 800
801
e0231715 802 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 803 (1ULL << INTERCEPT_NMI) |
0152527b 804 (1ULL << INTERCEPT_SMI) |
d225157b 805 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 806 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 807 (1ULL << INTERCEPT_INVD) |
6aa8b732 808 (1ULL << INTERCEPT_HLT) |
a7052897 809 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 810 (1ULL << INTERCEPT_INVLPGA) |
811 (1ULL << INTERCEPT_IOIO_PROT) |
812 (1ULL << INTERCEPT_MSR_PROT) |
813 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 814 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 815 (1ULL << INTERCEPT_VMRUN) |
816 (1ULL << INTERCEPT_VMMCALL) |
817 (1ULL << INTERCEPT_VMLOAD) |
818 (1ULL << INTERCEPT_VMSAVE) |
819 (1ULL << INTERCEPT_STGI) |
820 (1ULL << INTERCEPT_CLGI) |
916ce236 821 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 822 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 823 (1ULL << INTERCEPT_MONITOR) |
824 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 825
826 control->iopm_base_pa = iopm_base;
f65c229c 827 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 828 control->int_ctl = V_INTR_MASKING_MASK;
829
830 init_seg(&save->es);
831 init_seg(&save->ss);
832 init_seg(&save->ds);
833 init_seg(&save->fs);
834 init_seg(&save->gs);
835
836 save->cs.selector = 0xf000;
837 /* Executable/Readable Code Segment */
838 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
839 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
840 save->cs.limit = 0xffff;
d92899a0
AK		 841 /*
842 * cs.base should really be 0xffff0000, but vmx can't handle that, so
843 * be consistent with it.
844 *
845 * Replace when we have real mode working for vmx.
846 */
847 save->cs.base = 0xf0000;
6aa8b732
AK		 848
849 save->gdtr.limit = 0xffff;
850 save->idtr.limit = 0xffff;
851
852 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
853 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
854
eaa48512 855 svm_set_efer(&svm->vcpu, 0);
d77c26fc 856 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 857 save->dr7 = 0x400;
858 save->rflags = 2;
859 save->rip = 0x0000fff0;
5fdbf976 860 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 861
e0231715
JR		 862 /*
863 * This is the guest-visible cr0 value.
18fa000a 864 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 865 */
678041ad
MT		 866 svm->vcpu.arch.cr0 = 0;
867 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
18fa000a 868
66aee91a 869 save->cr4 = X86_CR4_PAE;
6aa8b732 870 /* rdx = ?? */
709ddebf
JR		 871
872 if (npt_enabled) {
873 /* Setup VMCB for Nested Paging */
874 control->nested_ctl = 1;
a7052897
MT		 875 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
876 (1ULL << INTERCEPT_INVLPG));
709ddebf 877 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 878 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
879 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 880 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 881 save->cr3 = 0;
882 save->cr4 = 0;
883 }
a79d2f18 884 force_new_asid(&svm->vcpu);
1371d904 885
e6aa9abd 886 svm->nested.vmcb = 0;
2af9194d
JR		 887 svm->vcpu.arch.hflags = 0;
888
2a6b20b8 889 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
565d0998
ML		 890 control->pause_filter_count = 3000;
891 control->intercept |= (1ULL << INTERCEPT_PAUSE);
892 }
893
2af9194d 894 enable_gif(svm);
6aa8b732
AK		 895}
896
e00c8cf2 897static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 898{
899 struct vcpu_svm *svm = to_svm(vcpu);
900
e6101a96 901 init_vmcb(svm);
70433389 902
c5af89b6 903 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 904 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 905 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
906 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 907 }
5fdbf976
MT		 908 vcpu->arch.regs_avail = ~0;
909 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 910
911 return 0;
04d2cc77
AK		 912}
913
fb3f0f51 914static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 915{
a2fa3e9f 916 struct vcpu_svm *svm;
6aa8b732 917 struct page *page;
f65c229c 918 struct page *msrpm_pages;
b286d5d8 919 struct page *hsave_page;
3d6368ef 920 struct page *nested_msrpm_pages;
fb3f0f51 921 int err;
6aa8b732 922
c16f862d 923 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 924 if (!svm) {
925 err = -ENOMEM;
926 goto out;
927 }
928
929 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
930 if (err)
931 goto free_svm;
932
b7af4043 933 err = -ENOMEM;
6aa8b732 934 page = alloc_page(GFP_KERNEL);
b7af4043 935 if (!page)
fb3f0f51 936 goto uninit;
6aa8b732 937
f65c229c
JR		 938 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
939 if (!msrpm_pages)
b7af4043 940 goto free_page1;
3d6368ef
AG		 941
942 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
943 if (!nested_msrpm_pages)
b7af4043 944 goto free_page2;
f65c229c 945
b286d5d8
AG		 946 hsave_page = alloc_page(GFP_KERNEL);
947 if (!hsave_page)
b7af4043
TY		 948 goto free_page3;
949
e6aa9abd 950 svm->nested.hsave = page_address(hsave_page);
b286d5d8 951
b7af4043
TY		 952 svm->msrpm = page_address(msrpm_pages);
953 svm_vcpu_init_msrpm(svm->msrpm);
954
e6aa9abd 955 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 956 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 957
a2fa3e9f
GH		 958 svm->vmcb = page_address(page);
959 clear_page(svm->vmcb);
960 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
961 svm->asid_generation = 0;
e6101a96 962 init_vmcb(svm);
99e3e30a 963 kvm_write_tsc(&svm->vcpu, 0);
a2fa3e9f 964
10ab25cd
JK		 965 err = fx_init(&svm->vcpu);
966 if (err)
967 goto free_page4;
968
ad312c7c 969 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 970 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 971 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 972
fb3f0f51 973 return &svm->vcpu;
36241b8c 974
10ab25cd
JK		 975free_page4:
976 __free_page(hsave_page);
b7af4043
TY		 977free_page3:
978 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
979free_page2:
980 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
981free_page1:
982 __free_page(page);
fb3f0f51
RR		 983uninit:
984 kvm_vcpu_uninit(&svm->vcpu);
985free_svm:
a4770347 986 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 987out:
988 return ERR_PTR(err);
6aa8b732
AK		 989}
990
991static void svm_free_vcpu(struct kvm_vcpu *vcpu)
992{
a2fa3e9f
GH		 993 struct vcpu_svm *svm = to_svm(vcpu);
994
fb3f0f51 995 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 996 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 997 __free_page(virt_to_page(svm->nested.hsave));
998 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 999 kvm_vcpu_uninit(vcpu);
a4770347 1000 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 1001}
1002
15ad7146 1003static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1004{
a2fa3e9f 1005 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 1006 int i;
0cc5064d 1007
0cc5064d 1008 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1009 svm->asid_generation = 0;
0cc5064d 1010 }
94dfbdb3 1011
82ca2d10
AK		 1012#ifdef CONFIG_X86_64
1013 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1014#endif
dacccfdd
AK		 1015 savesegment(fs, svm->host.fs);
1016 savesegment(gs, svm->host.gs);
1017 svm->host.ldt = kvm_read_ldt();
1018
94dfbdb3 1019 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1020 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1021}
1022
1023static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1024{
a2fa3e9f 1025 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1026 int i;
1027
e1beb1d3 1028 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1029 kvm_load_ldt(svm->host.ldt);
1030#ifdef CONFIG_X86_64
1031 loadsegment(fs, svm->host.fs);
1032 load_gs_index(svm->host.gs);
1033 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1034#else
1035 loadsegment(gs, svm->host.gs);
1036#endif
94dfbdb3 1037 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1038 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1039}
1040
6aa8b732
AK		 1041static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1042{
a2fa3e9f 1043 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 1044}
1045
1046static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1047{
a2fa3e9f 1048 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1049}
1050
6de4f3ad
AK		 1051static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1052{
1053 switch (reg) {
1054 case VCPU_EXREG_PDPTR:
1055 BUG_ON(!npt_enabled);
ff03a073 1056 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
6de4f3ad
AK		 1057 break;
1058 default:
1059 BUG();
1060 }
1061}
1062
f0b85051
AG		 1063static void svm_set_vintr(struct vcpu_svm *svm)
1064{
1065 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1066}
1067
1068static void svm_clear_vintr(struct vcpu_svm *svm)
1069{
1070 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1071}
1072
6aa8b732
AK		 1073static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1074{
a2fa3e9f 1075 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1076
1077 switch (seg) {
1078 case VCPU_SREG_CS: return &save->cs;
1079 case VCPU_SREG_DS: return &save->ds;
1080 case VCPU_SREG_ES: return &save->es;
1081 case VCPU_SREG_FS: return &save->fs;
1082 case VCPU_SREG_GS: return &save->gs;
1083 case VCPU_SREG_SS: return &save->ss;
1084 case VCPU_SREG_TR: return &save->tr;
1085 case VCPU_SREG_LDTR: return &save->ldtr;
1086 }
1087 BUG();
8b6d44c7 1088 return NULL;
6aa8b732
AK		 1089}
1090
1091static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1092{
1093 struct vmcb_seg *s = svm_seg(vcpu, seg);
1094
1095 return s->base;
1096}
1097
1098static void svm_get_segment(struct kvm_vcpu *vcpu,
1099 struct kvm_segment *var, int seg)
1100{
1101 struct vmcb_seg *s = svm_seg(vcpu, seg);
1102
1103 var->base = s->base;
1104 var->limit = s->limit;
1105 var->selector = s->selector;
1106 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1107 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1108 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1109 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1110 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1111 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1112 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1113 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1114
e0231715
JR		 1115 /*
1116 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1117 * for cross vendor migration purposes by "not present"
1118 */
1119 var->unusable = !var->present || (var->type == 0);
1120
1fbdc7a5
AP		 1121 switch (seg) {
1122 case VCPU_SREG_CS:
1123 /*
1124 * SVM always stores 0 for the 'G' bit in the CS selector in
1125 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1126 * Intel's VMENTRY has a check on the 'G' bit.
1127 */
25022acc 1128 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1129 break;
1130 case VCPU_SREG_TR:
1131 /*
1132 * Work around a bug where the busy flag in the tr selector
1133 * isn't exposed
1134 */
c0d09828 1135 var->type |= 0x2;
1fbdc7a5
AP		 1136 break;
1137 case VCPU_SREG_DS:
1138 case VCPU_SREG_ES:
1139 case VCPU_SREG_FS:
1140 case VCPU_SREG_GS:
1141 /*
1142 * The accessed bit must always be set in the segment
1143 * descriptor cache, although it can be cleared in the
1144 * descriptor, the cached bit always remains at 1. Since
1145 * Intel has a check on this, set it here to support
1146 * cross-vendor migration.
1147 */
1148 if (!var->unusable)
1149 var->type |= 0x1;
1150 break;
b586eb02 1151 case VCPU_SREG_SS:
e0231715
JR		 1152 /*
1153 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1154 * descriptor is left as 1, although the whole segment has
1155 * been made unusable. Clear it here to pass an Intel VMX
1156 * entry check when cross vendor migrating.
1157 */
1158 if (var->unusable)
1159 var->db = 0;
1160 break;
1fbdc7a5 1161 }
6aa8b732
AK		 1162}
1163
2e4d2653
IE		 1164static int svm_get_cpl(struct kvm_vcpu *vcpu)
1165{
1166 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1167
1168 return save->cpl;
1169}
1170
89a27f4d 1171static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1172{
a2fa3e9f
GH		 1173 struct vcpu_svm *svm = to_svm(vcpu);
1174
89a27f4d
GN		 1175 dt->size = svm->vmcb->save.idtr.limit;
1176 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1177}
1178
89a27f4d 1179static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1180{
a2fa3e9f
GH		 1181 struct vcpu_svm *svm = to_svm(vcpu);
1182
89a27f4d
GN		 1183 svm->vmcb->save.idtr.limit = dt->size;
1184 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1185}
1186
89a27f4d 1187static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1188{
a2fa3e9f
GH		 1189 struct vcpu_svm *svm = to_svm(vcpu);
1190
89a27f4d
GN		 1191 dt->size = svm->vmcb->save.gdtr.limit;
1192 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1193}
1194
89a27f4d 1195static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1196{
a2fa3e9f
GH		 1197 struct vcpu_svm *svm = to_svm(vcpu);
1198
89a27f4d
GN		 1199 svm->vmcb->save.gdtr.limit = dt->size;
1200 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1201}
1202
e8467fda
AK		 1203static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1204{
1205}
1206
25c4c276 1207static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1208{
1209}
1210
d225157b
AK		 1211static void update_cr0_intercept(struct vcpu_svm *svm)
1212{
66a562f7 1213 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1214 ulong gcr0 = svm->vcpu.arch.cr0;
1215 u64 *hcr0 = &svm->vmcb->save.cr0;
1216
1217 if (!svm->vcpu.fpu_active)
1218 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1219 else
1220 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1221 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1222
1223
1224 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1225 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1226 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
2030753d 1227 if (is_guest_mode(&svm->vcpu)) {
66a562f7
JR		 1228 struct vmcb *hsave = svm->nested.hsave;
1229
1230 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1231 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1232 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1233 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1234 }
d225157b
AK		 1235 } else {
1236 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1237 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
2030753d 1238 if (is_guest_mode(&svm->vcpu)) {
66a562f7
JR		 1239 struct vmcb *hsave = svm->nested.hsave;
1240
1241 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1242 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1243 }
d225157b
AK		 1244 }
1245}
1246
6aa8b732
AK		 1247static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1248{
a2fa3e9f
GH		 1249 struct vcpu_svm *svm = to_svm(vcpu);
1250
2030753d 1251 if (is_guest_mode(vcpu)) {
7f5d8b56
JR		 1252 /*
1253 * We are here because we run in nested mode, the host kvm
1254 * intercepts cr0 writes but the l1 hypervisor does not.
1255 * But the L1 hypervisor may intercept selective cr0 writes.
1256 * This needs to be checked here.
1257 */
1258 unsigned long old, new;
1259
1260 /* Remove bits that would trigger a real cr0 write intercept */
1261 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1262 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1263
1264 if (old == new) {
1265 /* cr0 write with ts and mp unchanged */
1266 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
cda00082
JR		 1267 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1268 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1269 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1270 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7f5d8b56 1271 return;
cda00082 1272 }
7f5d8b56
JR		 1273 }
1274 }
1275
05b3e0c2 1276#ifdef CONFIG_X86_64
f6801dff 1277 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1278 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1279 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1280 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1281 }
1282
d77c26fc 1283 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1284 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1285 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1286 }
1287 }
1288#endif
ad312c7c 1289 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1290
1291 if (!npt_enabled)
1292 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1293
1294 if (!vcpu->fpu_active)
334df50a 1295 cr0 |= X86_CR0_TS;
709ddebf
JR		 1296 /*
1297 * re-enable caching here because the QEMU bios
1298 * does not do it - this results in some delay at
1299 * reboot
1300 */
1301 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1302 svm->vmcb->save.cr0 = cr0;
d225157b 1303 update_cr0_intercept(svm);
6aa8b732
AK		 1304}
1305
1306static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1307{
6394b649 1308 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1309 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1310
1311 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1312 force_new_asid(vcpu);
6394b649 1313
ec077263
JR		 1314 vcpu->arch.cr4 = cr4;
1315 if (!npt_enabled)
1316 cr4 |= X86_CR4_PAE;
6394b649 1317 cr4 |= host_cr4_mce;
ec077263 1318 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1319}
1320
1321static void svm_set_segment(struct kvm_vcpu *vcpu,
1322 struct kvm_segment *var, int seg)
1323{
a2fa3e9f 1324 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1325 struct vmcb_seg *s = svm_seg(vcpu, seg);
1326
1327 s->base = var->base;
1328 s->limit = var->limit;
1329 s->selector = var->selector;
1330 if (var->unusable)
1331 s->attrib = 0;
1332 else {
1333 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1334 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1335 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1336 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1337 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1338 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1339 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1340 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1341 }
1342 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1343 svm->vmcb->save.cpl
1344 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1345 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1346
1347}
1348
44c11430 1349static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1350{
d0bfb940
JK		 1351 struct vcpu_svm *svm = to_svm(vcpu);
1352
d0bfb940
JK		 1353 svm->vmcb->control.intercept_exceptions &=
1354 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1355
6be7d306 1356 if (svm->nmi_singlestep)
44c11430
GN		 1357 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1358
d0bfb940
JK		 1359 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1360 if (vcpu->guest_debug &
1361 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1362 svm->vmcb->control.intercept_exceptions |=
1363 1 << DB_VECTOR;
1364 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1365 svm->vmcb->control.intercept_exceptions |=
1366 1 << BP_VECTOR;
1367 } else
1368 vcpu->guest_debug = 0;
44c11430
GN		 1369}
1370
355be0b9 1371static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1372{
44c11430
GN		 1373 struct vcpu_svm *svm = to_svm(vcpu);
1374
ae675ef0
JK		 1375 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1376 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1377 else
1378 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1379
355be0b9 1380 update_db_intercept(vcpu);
6aa8b732
AK		 1381}
1382
0fe1e009 1383static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1384{
0fe1e009
TH		 1385 if (sd->next_asid > sd->max_asid) {
1386 ++sd->asid_generation;
1387 sd->next_asid = 1;
a2fa3e9f 1388 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1389 }
1390
0fe1e009
TH		 1391 svm->asid_generation = sd->asid_generation;
1392 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1393}
1394
020df079 1395static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1396{
42dbaa5a 1397 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1398
020df079 1399 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1400}
1401
851ba692 1402static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1403{
631bc487 1404 u64 fault_address = svm->vmcb->control.exit_info_2;
6aa8b732 1405 u32 error_code;
631bc487 1406 int r = 1;
6aa8b732 1407
631bc487
GN		 1408 switch (svm->apf_reason) {
1409 default:
1410 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1411
631bc487
GN		 1412 trace_kvm_page_fault(fault_address, error_code);
1413 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1414 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1415 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1416 break;
1417 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1418 svm->apf_reason = 0;
1419 local_irq_disable();
1420 kvm_async_pf_task_wait(fault_address);
1421 local_irq_enable();
1422 break;
1423 case KVM_PV_REASON_PAGE_READY:
1424 svm->apf_reason = 0;
1425 local_irq_disable();
1426 kvm_async_pf_task_wake(fault_address);
1427 local_irq_enable();
1428 break;
1429 }
1430 return r;
6aa8b732
AK		 1431}
1432
851ba692 1433static int db_interception(struct vcpu_svm *svm)
d0bfb940 1434{
851ba692
AK		 1435 struct kvm_run *kvm_run = svm->vcpu.run;
1436
d0bfb940 1437 if (!(svm->vcpu.guest_debug &
44c11430 1438 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1439 !svm->nmi_singlestep) {
d0bfb940
JK		 1440 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1441 return 1;
1442 }
44c11430 1443
6be7d306
JK		 1444 if (svm->nmi_singlestep) {
1445 svm->nmi_singlestep = false;
44c11430
GN		 1446 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1447 svm->vmcb->save.rflags &=
1448 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1449 update_db_intercept(&svm->vcpu);
1450 }
1451
1452 if (svm->vcpu.guest_debug &
e0231715 1453 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1454 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1455 kvm_run->debug.arch.pc =
1456 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1457 kvm_run->debug.arch.exception = DB_VECTOR;
1458 return 0;
1459 }
1460
1461 return 1;
d0bfb940
JK		 1462}
1463
851ba692 1464static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1465{
851ba692
AK		 1466 struct kvm_run *kvm_run = svm->vcpu.run;
1467
d0bfb940
JK		 1468 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1469 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1470 kvm_run->debug.arch.exception = BP_VECTOR;
1471 return 0;
1472}
1473
851ba692 1474static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1475{
1476 int er;
1477
851ba692 1478 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1479 if (er != EMULATE_DONE)
7ee5d940 1480 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1481 return 1;
1482}
1483
6b52d186 1484static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1485{
6b52d186 1486 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1487 u32 excp;
1488
2030753d 1489 if (is_guest_mode(vcpu)) {
66a562f7
JR		 1490 u32 h_excp, n_excp;
1491
1492 h_excp = svm->nested.hsave->control.intercept_exceptions;
1493 n_excp = svm->nested.intercept_exceptions;
1494 h_excp &= ~(1 << NM_VECTOR);
1495 excp = h_excp | n_excp;
1496 } else {
1497 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1498 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1499 }
1500
1501 svm->vmcb->control.intercept_exceptions = excp;
1502
e756fc62 1503 svm->vcpu.fpu_active = 1;
d225157b 1504 update_cr0_intercept(svm);
6b52d186 1505}
a2fa3e9f 1506
6b52d186
AK		 1507static int nm_interception(struct vcpu_svm *svm)
1508{
1509 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1510 return 1;
7807fa6c
AL		 1511}
1512
67ec6607
JR		 1513static bool is_erratum_383(void)
1514{
1515 int err, i;
1516 u64 value;
1517
1518 if (!erratum_383_found)
1519 return false;
1520
1521 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1522 if (err)
1523 return false;
1524
1525 /* Bit 62 may or may not be set for this mce */
1526 value &= ~(1ULL << 62);
1527
1528 if (value != 0xb600000000010015ULL)
1529 return false;
1530
1531 /* Clear MCi_STATUS registers */
1532 for (i = 0; i < 6; ++i)
1533 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1534
1535 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1536 if (!err) {
1537 u32 low, high;
1538
1539 value &= ~(1ULL << 2);
1540 low = lower_32_bits(value);
1541 high = upper_32_bits(value);
1542
1543 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1544 }
1545
1546 /* Flush tlb to evict multi-match entries */
1547 __flush_tlb_all();
1548
1549 return true;
1550}
1551
fe5913e4 1552static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1553{
67ec6607
JR		 1554 if (is_erratum_383()) {
1555 /*
1556 * Erratum 383 triggered. Guest state is corrupt so kill the
1557 * guest.
1558 */
1559 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1560
a8eeb04a 1561 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1562
1563 return;
1564 }
1565
53371b50
JR		 1566 /*
1567 * On an #MC intercept the MCE handler is not called automatically in
1568 * the host. So do it by hand here.
1569 */
1570 asm volatile (
1571 "int $0x12\n");
1572 /* not sure if we ever come back to this point */
1573
fe5913e4
JR		 1574 return;
1575}
1576
1577static int mc_interception(struct vcpu_svm *svm)
1578{
53371b50
JR		 1579 return 1;
1580}
1581
851ba692 1582static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1583{
851ba692
AK		 1584 struct kvm_run *kvm_run = svm->vcpu.run;
1585
46fe4ddd
JR		 1586 /*
1587 * VMCB is undefined after a SHUTDOWN intercept
1588 * so reinitialize it.
1589 */
a2fa3e9f 1590 clear_page(svm->vmcb);
e6101a96 1591 init_vmcb(svm);
46fe4ddd
JR		 1592
1593 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1594 return 0;
1595}
1596
851ba692 1597static int io_interception(struct vcpu_svm *svm)
6aa8b732 1598{
cf8f70bf 1599 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1600 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1601 int size, in, string;
039576c0 1602 unsigned port;
6aa8b732 1603
e756fc62 1604 ++svm->vcpu.stat.io_exits;
e70669ab 1605 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1606 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1607 if (string || in)
6d77dbfc 1608 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1609
039576c0
AK		 1610 port = io_info >> 16;
1611 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1612 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1613 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1614
1615 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1616}
1617
851ba692 1618static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1619{
1620 return 1;
1621}
1622
851ba692 1623static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1624{
1625 ++svm->vcpu.stat.irq_exits;
1626 return 1;
1627}
1628
851ba692 1629static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1630{
1631 return 1;
1632}
1633
851ba692 1634static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1635{
5fdbf976 1636 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1637 skip_emulated_instruction(&svm->vcpu);
1638 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1639}
1640
851ba692 1641static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1642{
5fdbf976 1643 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1644 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1645 kvm_emulate_hypercall(&svm->vcpu);
1646 return 1;
02e235bc
AK		 1647}
1648
5bd2edc3
JR		 1649static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1650{
1651 struct vcpu_svm *svm = to_svm(vcpu);
1652
1653 return svm->nested.nested_cr3;
1654}
1655
1656static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1657 unsigned long root)
1658{
1659 struct vcpu_svm *svm = to_svm(vcpu);
1660
1661 svm->vmcb->control.nested_cr3 = root;
1662 force_new_asid(vcpu);
1663}
1664
6389ee94
AK		 1665static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1666 struct x86_exception *fault)
5bd2edc3
JR		 1667{
1668 struct vcpu_svm *svm = to_svm(vcpu);
1669
1670 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1671 svm->vmcb->control.exit_code_hi = 0;
6389ee94
AK		 1672 svm->vmcb->control.exit_info_1 = fault->error_code;
1673 svm->vmcb->control.exit_info_2 = fault->address;
5bd2edc3
JR		 1674
1675 nested_svm_vmexit(svm);
1676}
1677
4b16184c
JR		 1678static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1679{
1680 int r;
1681
1682 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1683
1684 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1685 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1686 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1687 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1688 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1689
1690 return r;
1691}
1692
1693static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1694{
1695 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1696}
1697
c0725420
AG		 1698static int nested_svm_check_permissions(struct vcpu_svm *svm)
1699{
f6801dff 1700 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1701 || !is_paging(&svm->vcpu)) {
1702 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1703 return 1;
1704 }
1705
1706 if (svm->vmcb->save.cpl) {
1707 kvm_inject_gp(&svm->vcpu, 0);
1708 return 1;
1709 }
1710
1711 return 0;
1712}
1713
cf74a78b
AG		 1714static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1715 bool has_error_code, u32 error_code)
1716{
b8e88bc8
JR		 1717 int vmexit;
1718
2030753d 1719 if (!is_guest_mode(&svm->vcpu))
0295ad7d 1720 return 0;
cf74a78b 1721
0295ad7d
JR		 1722 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1723 svm->vmcb->control.exit_code_hi = 0;
1724 svm->vmcb->control.exit_info_1 = error_code;
1725 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1726
b8e88bc8
JR		 1727 vmexit = nested_svm_intercept(svm);
1728 if (vmexit == NESTED_EXIT_DONE)
1729 svm->nested.exit_required = true;
1730
1731 return vmexit;
cf74a78b
AG		 1732}
1733
8fe54654
JR		 1734/* This function returns true if it is save to enable the irq window */
1735static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1736{
2030753d 1737 if (!is_guest_mode(&svm->vcpu))
8fe54654 1738 return true;
cf74a78b 1739
26666957 1740 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1741 return true;
cf74a78b 1742
26666957 1743 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1744 return false;
cf74a78b 1745
a0a07cd2
GN		 1746 /*
1747 * if vmexit was already requested (by intercepted exception
1748 * for instance) do not overwrite it with "external interrupt"
1749 * vmexit.
1750 */
1751 if (svm->nested.exit_required)
1752 return false;
1753
197717d5
JR		 1754 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1755 svm->vmcb->control.exit_info_1 = 0;
1756 svm->vmcb->control.exit_info_2 = 0;
26666957 1757
cd3ff653
JR		 1758 if (svm->nested.intercept & 1ULL) {
1759 /*
1760 * The #vmexit can't be emulated here directly because this
1761 * code path runs with irqs and preemtion disabled. A
1762 * #vmexit emulation might sleep. Only signal request for
1763 * the #vmexit here.
1764 */
1765 svm->nested.exit_required = true;
236649de 1766 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1767 return false;
cf74a78b
AG		 1768 }
1769
8fe54654 1770 return true;
cf74a78b
AG		 1771}
1772
887f500c
JR		 1773/* This function returns true if it is save to enable the nmi window */
1774static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1775{
2030753d 1776 if (!is_guest_mode(&svm->vcpu))
887f500c
JR		 1777 return true;
1778
1779 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1780 return true;
1781
1782 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1783 svm->nested.exit_required = true;
1784
1785 return false;
cf74a78b
AG		 1786}
1787
7597f129 1788static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1789{
1790 struct page *page;
1791
6c3bd3d7
JR		 1792 might_sleep();
1793
34f80cfa 1794 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1795 if (is_error_page(page))
1796 goto error;
1797
7597f129
JR		 1798 *_page = page;
1799
1800 return kmap(page);
34f80cfa
JR		 1801
1802error:
1803 kvm_release_page_clean(page);
1804 kvm_inject_gp(&svm->vcpu, 0);
1805
1806 return NULL;
1807}
1808
7597f129 1809static void nested_svm_unmap(struct page *page)
34f80cfa 1810{
7597f129 1811 kunmap(page);
34f80cfa
JR		 1812 kvm_release_page_dirty(page);
1813}
34f80cfa 1814
ce2ac085
JR		 1815static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1816{
1817 unsigned port;
1818 u8 val, bit;
1819 u64 gpa;
34f80cfa 1820
ce2ac085
JR		 1821 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1822 return NESTED_EXIT_HOST;
34f80cfa 1823
ce2ac085
JR		 1824 port = svm->vmcb->control.exit_info_1 >> 16;
1825 gpa = svm->nested.vmcb_iopm + (port / 8);
1826 bit = port % 8;
1827 val = 0;
1828
1829 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1830 val &= (1 << bit);
1831
1832 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1833}
1834
d2477826 1835static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1836{
0d6b3537
JR		 1837 u32 offset, msr, value;
1838 int write, mask;
4c2161ae 1839
3d62d9aa 1840 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1841 return NESTED_EXIT_HOST;
3d62d9aa 1842
0d6b3537
JR		 1843 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1844 offset = svm_msrpm_offset(msr);
1845 write = svm->vmcb->control.exit_info_1 & 1;
1846 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1847
0d6b3537
JR		 1848 if (offset == MSR_INVALID)
1849 return NESTED_EXIT_DONE;
4c2161ae 1850
0d6b3537
JR		 1851 /* Offset is in 32 bit units but need in 8 bit units */
1852 offset *= 4;
4c2161ae 1853
0d6b3537
JR		 1854 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1855 return NESTED_EXIT_DONE;
3d62d9aa 1856
0d6b3537 1857 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1858}
1859
410e4d57 1860static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1861{
cf74a78b 1862 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1863
410e4d57
JR		 1864 switch (exit_code) {
1865 case SVM_EXIT_INTR:
1866 case SVM_EXIT_NMI:
ff47a49b 1867 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1868 return NESTED_EXIT_HOST;
410e4d57 1869 case SVM_EXIT_NPF:
e0231715 1870 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1871 if (npt_enabled)
1872 return NESTED_EXIT_HOST;
1873 break;
410e4d57 1874 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
631bc487
GN		 1875 /* When we're shadowing, trap PFs, but not async PF */
1876 if (!npt_enabled && svm->apf_reason == 0)
410e4d57
JR		 1877 return NESTED_EXIT_HOST;
1878 break;
66a562f7
JR		 1879 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1880 nm_interception(svm);
1881 break;
410e4d57
JR		 1882 default:
1883 break;
cf74a78b
AG		 1884 }
1885
410e4d57
JR		 1886 return NESTED_EXIT_CONTINUE;
1887}
1888
1889/*
1890 * If this function returns true, this #vmexit was already handled
1891 */
b8e88bc8 1892static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1893{
1894 u32 exit_code = svm->vmcb->control.exit_code;
1895 int vmexit = NESTED_EXIT_HOST;
1896
cf74a78b 1897 switch (exit_code) {
9c4e40b9 1898 case SVM_EXIT_MSR:
3d62d9aa 1899 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1900 break;
ce2ac085
JR		 1901 case SVM_EXIT_IOIO:
1902 vmexit = nested_svm_intercept_ioio(svm);
1903 break;
cf74a78b
AG		 1904 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1905 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1906 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1907 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1908 break;
1909 }
1910 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1911 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1912 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1913 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1914 break;
1915 }
1916 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1917 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1918 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1919 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1920 break;
1921 }
1922 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1923 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1924 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1925 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1926 break;
1927 }
1928 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1929 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1930 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1931 vmexit = NESTED_EXIT_DONE;
631bc487
GN		 1932 /* async page fault always cause vmexit */
1933 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1934 svm->apf_reason != 0)
1935 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1936 break;
1937 }
228070b1
JR		 1938 case SVM_EXIT_ERR: {
1939 vmexit = NESTED_EXIT_DONE;
1940 break;
1941 }
cf74a78b
AG		 1942 default: {
1943 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1944 if (svm->nested.intercept & exit_bits)
410e4d57 1945 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1946 }
1947 }
1948
b8e88bc8
JR		 1949 return vmexit;
1950}
1951
1952static int nested_svm_exit_handled(struct vcpu_svm *svm)
1953{
1954 int vmexit;
1955
1956 vmexit = nested_svm_intercept(svm);
1957
1958 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1959 nested_svm_vmexit(svm);
9c4e40b9
JR		 1960
1961 return vmexit;
cf74a78b
AG		 1962}
1963
0460a979
JR		 1964static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1965{
1966 struct vmcb_control_area *dst = &dst_vmcb->control;
1967 struct vmcb_control_area *from = &from_vmcb->control;
1968
1969 dst->intercept_cr_read = from->intercept_cr_read;
1970 dst->intercept_cr_write = from->intercept_cr_write;
1971 dst->intercept_dr_read = from->intercept_dr_read;
1972 dst->intercept_dr_write = from->intercept_dr_write;
1973 dst->intercept_exceptions = from->intercept_exceptions;
1974 dst->intercept = from->intercept;
1975 dst->iopm_base_pa = from->iopm_base_pa;
1976 dst->msrpm_base_pa = from->msrpm_base_pa;
1977 dst->tsc_offset = from->tsc_offset;
1978 dst->asid = from->asid;
1979 dst->tlb_ctl = from->tlb_ctl;
1980 dst->int_ctl = from->int_ctl;
1981 dst->int_vector = from->int_vector;
1982 dst->int_state = from->int_state;
1983 dst->exit_code = from->exit_code;
1984 dst->exit_code_hi = from->exit_code_hi;
1985 dst->exit_info_1 = from->exit_info_1;
1986 dst->exit_info_2 = from->exit_info_2;
1987 dst->exit_int_info = from->exit_int_info;
1988 dst->exit_int_info_err = from->exit_int_info_err;
1989 dst->nested_ctl = from->nested_ctl;
1990 dst->event_inj = from->event_inj;
1991 dst->event_inj_err = from->event_inj_err;
1992 dst->nested_cr3 = from->nested_cr3;
1993 dst->lbr_ctl = from->lbr_ctl;
1994}
1995
34f80cfa 1996static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1997{
34f80cfa 1998 struct vmcb *nested_vmcb;
e6aa9abd 1999 struct vmcb *hsave = svm->nested.hsave;
33740e40 2000 struct vmcb *vmcb = svm->vmcb;
7597f129 2001 struct page *page;
cf74a78b 2002
17897f36
JR		 2003 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2004 vmcb->control.exit_info_1,
2005 vmcb->control.exit_info_2,
2006 vmcb->control.exit_int_info,
2007 vmcb->control.exit_int_info_err);
2008
7597f129 2009 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 2010 if (!nested_vmcb)
2011 return 1;
2012
2030753d
JR		 2013 /* Exit Guest-Mode */
2014 leave_guest_mode(&svm->vcpu);
06fc7772
JR		 2015 svm->nested.vmcb = 0;
2016
cf74a78b 2017 /* Give the current vmcb to the guest */
33740e40
JR		 2018 disable_gif(svm);
2019
2020 nested_vmcb->save.es = vmcb->save.es;
2021 nested_vmcb->save.cs = vmcb->save.cs;
2022 nested_vmcb->save.ss = vmcb->save.ss;
2023 nested_vmcb->save.ds = vmcb->save.ds;
2024 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2025 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 2026 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 2027 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 2028 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 2029 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 2030 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 2031 nested_vmcb->save.rflags = vmcb->save.rflags;
2032 nested_vmcb->save.rip = vmcb->save.rip;
2033 nested_vmcb->save.rsp = vmcb->save.rsp;
2034 nested_vmcb->save.rax = vmcb->save.rax;
2035 nested_vmcb->save.dr7 = vmcb->save.dr7;
2036 nested_vmcb->save.dr6 = vmcb->save.dr6;
2037 nested_vmcb->save.cpl = vmcb->save.cpl;
2038
2039 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2040 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2041 nested_vmcb->control.int_state = vmcb->control.int_state;
2042 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2043 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2044 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2045 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2046 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2047 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 2048 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 2049
2050 /*
2051 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2052 * to make sure that we do not lose injected events. So check event_inj
2053 * here and copy it to exit_int_info if it is valid.
2054 * Exit_int_info and event_inj can't be both valid because the case
2055 * below only happens on a VMRUN instruction intercept which has
2056 * no valid exit_int_info set.
2057 */
2058 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2059 struct vmcb_control_area *nc = &nested_vmcb->control;
2060
2061 nc->exit_int_info = vmcb->control.event_inj;
2062 nc->exit_int_info_err = vmcb->control.event_inj_err;
2063 }
2064
33740e40
JR		 2065 nested_vmcb->control.tlb_ctl = 0;
2066 nested_vmcb->control.event_inj = 0;
2067 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 2068
2069 /* We always set V_INTR_MASKING and remember the old value in hflags */
2070 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2071 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2072
cf74a78b 2073 /* Restore the original control entries */
0460a979 2074 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 2075
219b65dc
AG		 2076 kvm_clear_exception_queue(&svm->vcpu);
2077 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b 2078
4b16184c
JR		 2079 svm->nested.nested_cr3 = 0;
2080
cf74a78b
AG		 2081 /* Restore selected save entries */
2082 svm->vmcb->save.es = hsave->save.es;
2083 svm->vmcb->save.cs = hsave->save.cs;
2084 svm->vmcb->save.ss = hsave->save.ss;
2085 svm->vmcb->save.ds = hsave->save.ds;
2086 svm->vmcb->save.gdtr = hsave->save.gdtr;
2087 svm->vmcb->save.idtr = hsave->save.idtr;
2088 svm->vmcb->save.rflags = hsave->save.rflags;
2089 svm_set_efer(&svm->vcpu, hsave->save.efer);
2090 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2091 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2092 if (npt_enabled) {
2093 svm->vmcb->save.cr3 = hsave->save.cr3;
2094 svm->vcpu.arch.cr3 = hsave->save.cr3;
2095 } else {
2390218b 2096 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 2097 }
2098 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2099 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2100 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2101 svm->vmcb->save.dr7 = 0;
2102 svm->vmcb->save.cpl = 0;
2103 svm->vmcb->control.exit_int_info = 0;
2104
7597f129 2105 nested_svm_unmap(page);
cf74a78b 2106
4b16184c 2107 nested_svm_uninit_mmu_context(&svm->vcpu);
cf74a78b
AG		 2108 kvm_mmu_reset_context(&svm->vcpu);
2109 kvm_mmu_load(&svm->vcpu);
2110
2111 return 0;
2112}
3d6368ef 2113
9738b2c9 2114static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 2115{
323c3d80
JR		 2116 /*
2117 * This function merges the msr permission bitmaps of kvm and the
2118 * nested vmcb. It is omptimized in that it only merges the parts where
2119 * the kvm msr permission bitmap may contain zero bits
2120 */
3d6368ef 2121 int i;
9738b2c9 2122
323c3d80
JR		 2123 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2124 return true;
9738b2c9 2125
323c3d80
JR		 2126 for (i = 0; i < MSRPM_OFFSETS; i++) {
2127 u32 value, p;
2128 u64 offset;
9738b2c9 2129
323c3d80
JR		 2130 if (msrpm_offsets[i] == 0xffffffff)
2131 break;
3d6368ef 2132
0d6b3537
JR		 2133 p = msrpm_offsets[i];
2134 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2135
2136 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2137 return false;
2138
2139 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2140 }
3d6368ef 2141
323c3d80 2142 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2143
2144 return true;
3d6368ef
AG		 2145}
2146
52c65a30
JR		 2147static bool nested_vmcb_checks(struct vmcb *vmcb)
2148{
2149 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2150 return false;
2151
dbe77584
JR		 2152 if (vmcb->control.asid == 0)
2153 return false;
2154
4b16184c
JR		 2155 if (vmcb->control.nested_ctl && !npt_enabled)
2156 return false;
2157
52c65a30
JR		 2158 return true;
2159}
2160
9738b2c9 2161static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2162{
9738b2c9 2163 struct vmcb *nested_vmcb;
e6aa9abd 2164 struct vmcb *hsave = svm->nested.hsave;
defbba56 2165 struct vmcb *vmcb = svm->vmcb;
7597f129 2166 struct page *page;
06fc7772 2167 u64 vmcb_gpa;
3d6368ef 2168
06fc7772 2169 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2170
7597f129 2171 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2172 if (!nested_vmcb)
2173 return false;
2174
52c65a30
JR		 2175 if (!nested_vmcb_checks(nested_vmcb)) {
2176 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2177 nested_vmcb->control.exit_code_hi = 0;
2178 nested_vmcb->control.exit_info_1 = 0;
2179 nested_vmcb->control.exit_info_2 = 0;
2180
2181 nested_svm_unmap(page);
2182
2183 return false;
2184 }
2185
b75f4eb3 2186 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
0ac406de
JR		 2187 nested_vmcb->save.rip,
2188 nested_vmcb->control.int_ctl,
2189 nested_vmcb->control.event_inj,
2190 nested_vmcb->control.nested_ctl);
2191
2e554e8d
JR		 2192 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2193 nested_vmcb->control.intercept_cr_write,
2194 nested_vmcb->control.intercept_exceptions,
2195 nested_vmcb->control.intercept);
2196
3d6368ef 2197 /* Clear internal status */
219b65dc
AG		 2198 kvm_clear_exception_queue(&svm->vcpu);
2199 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2200
e0231715
JR		 2201 /*
2202 * Save the old vmcb, so we don't need to pick what we save, but can
2203 * restore everything when a VMEXIT occurs
2204 */
defbba56
JR		 2205 hsave->save.es = vmcb->save.es;
2206 hsave->save.cs = vmcb->save.cs;
2207 hsave->save.ss = vmcb->save.ss;
2208 hsave->save.ds = vmcb->save.ds;
2209 hsave->save.gdtr = vmcb->save.gdtr;
2210 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2211 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2212 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2213 hsave->save.cr4 = svm->vcpu.arch.cr4;
2214 hsave->save.rflags = vmcb->save.rflags;
b75f4eb3 2215 hsave->save.rip = kvm_rip_read(&svm->vcpu);
defbba56
JR		 2216 hsave->save.rsp = vmcb->save.rsp;
2217 hsave->save.rax = vmcb->save.rax;
2218 if (npt_enabled)
2219 hsave->save.cr3 = vmcb->save.cr3;
2220 else
2221 hsave->save.cr3 = svm->vcpu.arch.cr3;
2222
0460a979 2223 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2224
2225 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2226 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2227 else
2228 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2229
4b16184c
JR		 2230 if (nested_vmcb->control.nested_ctl) {
2231 kvm_mmu_unload(&svm->vcpu);
2232 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2233 nested_svm_init_mmu_context(&svm->vcpu);
2234 }
2235
3d6368ef
AG		 2236 /* Load the nested guest state */
2237 svm->vmcb->save.es = nested_vmcb->save.es;
2238 svm->vmcb->save.cs = nested_vmcb->save.cs;
2239 svm->vmcb->save.ss = nested_vmcb->save.ss;
2240 svm->vmcb->save.ds = nested_vmcb->save.ds;
2241 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2242 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2243 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2244 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2245 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2246 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2247 if (npt_enabled) {
2248 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2249 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2250 } else
2390218b 2251 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2252
2253 /* Guest paging mode is active - reset mmu */
2254 kvm_mmu_reset_context(&svm->vcpu);
2255
defbba56 2256 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2257 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2258 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2259 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2260
3d6368ef
AG		 2261 /* In case we don't even reach vcpu_run, the fields are not updated */
2262 svm->vmcb->save.rax = nested_vmcb->save.rax;
2263 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2264 svm->vmcb->save.rip = nested_vmcb->save.rip;
2265 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2266 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2267 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2268
f7138538 2269 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2270 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2271
aad42c64
JR		 2272 /* cache intercepts */
2273 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2274 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2275 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2276 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2277 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2278 svm->nested.intercept = nested_vmcb->control.intercept;
2279
3d6368ef 2280 force_new_asid(&svm->vcpu);
3d6368ef 2281 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2282 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2283 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2284 else
2285 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2286
88ab24ad
JR		 2287 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2288 /* We only want the cr8 intercept bits of the guest */
2289 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2290 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2291 }
2292
0d945bd9
JR		 2293 /* We don't want to see VMMCALLs from a nested guest */
2294 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2295
88ab24ad 2296 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2297 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2298 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2299 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2300 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2301 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2302
7597f129 2303 nested_svm_unmap(page);
9738b2c9 2304
2030753d
JR		 2305 /* Enter Guest-Mode */
2306 enter_guest_mode(&svm->vcpu);
2307
384c6368
JR		 2308 /*
2309 * Merge guest and host intercepts - must be called with vcpu in
2310 * guest-mode to take affect here
2311 */
2312 recalc_intercepts(svm);
2313
06fc7772 2314 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2315
2af9194d 2316 enable_gif(svm);
3d6368ef 2317
9738b2c9 2318 return true;
3d6368ef
AG		 2319}
2320
9966bf68 2321static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2322{
2323 to_vmcb->save.fs = from_vmcb->save.fs;
2324 to_vmcb->save.gs = from_vmcb->save.gs;
2325 to_vmcb->save.tr = from_vmcb->save.tr;
2326 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2327 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2328 to_vmcb->save.star = from_vmcb->save.star;
2329 to_vmcb->save.lstar = from_vmcb->save.lstar;
2330 to_vmcb->save.cstar = from_vmcb->save.cstar;
2331 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2332 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2333 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2334 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2335}
2336
851ba692 2337static int vmload_interception(struct vcpu_svm *svm)
5542675b 2338{
9966bf68 2339 struct vmcb *nested_vmcb;
7597f129 2340 struct page *page;
9966bf68 2341
5542675b
AG		 2342 if (nested_svm_check_permissions(svm))
2343 return 1;
2344
2345 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2346 skip_emulated_instruction(&svm->vcpu);
2347
7597f129 2348 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2349 if (!nested_vmcb)
2350 return 1;
2351
2352 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2353 nested_svm_unmap(page);
5542675b
AG		 2354
2355 return 1;
2356}
2357
851ba692 2358static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2359{
9966bf68 2360 struct vmcb *nested_vmcb;
7597f129 2361 struct page *page;
9966bf68 2362
5542675b
AG		 2363 if (nested_svm_check_permissions(svm))
2364 return 1;
2365
2366 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2367 skip_emulated_instruction(&svm->vcpu);
2368
7597f129 2369 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2370 if (!nested_vmcb)
2371 return 1;
2372
2373 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2374 nested_svm_unmap(page);
5542675b
AG		 2375
2376 return 1;
2377}
2378
851ba692 2379static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2380{
3d6368ef
AG		 2381 if (nested_svm_check_permissions(svm))
2382 return 1;
2383
b75f4eb3
RJ		 2384 /* Save rip after vmrun instruction */
2385 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3d6368ef 2386
9738b2c9 2387 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2388 return 1;
2389
9738b2c9 2390 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2391 goto failed;
2392
2393 return 1;
2394
2395failed:
2396
2397 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2398 svm->vmcb->control.exit_code_hi = 0;
2399 svm->vmcb->control.exit_info_1 = 0;
2400 svm->vmcb->control.exit_info_2 = 0;
2401
2402 nested_svm_vmexit(svm);
3d6368ef
AG		 2403
2404 return 1;
2405}
2406
851ba692 2407static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2408{
2409 if (nested_svm_check_permissions(svm))
2410 return 1;
2411
2412 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2413 skip_emulated_instruction(&svm->vcpu);
3842d135 2414 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
1371d904 2415
2af9194d 2416 enable_gif(svm);
1371d904
AG		 2417
2418 return 1;
2419}
2420
851ba692 2421static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2422{
2423 if (nested_svm_check_permissions(svm))
2424 return 1;
2425
2426 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2427 skip_emulated_instruction(&svm->vcpu);
2428
2af9194d 2429 disable_gif(svm);
1371d904
AG		 2430
2431 /* After a CLGI no interrupts should come */
2432 svm_clear_vintr(svm);
2433 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2434
2435 return 1;
2436}
2437
851ba692 2438static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2439{
2440 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2441
ec1ff790
JR		 2442 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2443 vcpu->arch.regs[VCPU_REGS_RAX]);
2444
ff092385
AG		 2445 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2446 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2447
2448 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2449 skip_emulated_instruction(&svm->vcpu);
2450 return 1;
2451}
2452
532a46b9
JR		 2453static int skinit_interception(struct vcpu_svm *svm)
2454{
2455 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2456
2457 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2458 return 1;
2459}
2460
851ba692 2461static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2462{
7ee5d940 2463 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2464 return 1;
2465}
2466
851ba692 2467static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2468{
37817f29 2469 u16 tss_selector;
64a7ec06
GN		 2470 int reason;
2471 int int_type = svm->vmcb->control.exit_int_info &
2472 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2473 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2474 uint32_t type =
2475 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2476 uint32_t idt_v =
2477 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2478 bool has_error_code = false;
2479 u32 error_code = 0;
37817f29
IE		 2480
2481 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2482
37817f29
IE		 2483 if (svm->vmcb->control.exit_info_2 &
2484 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2485 reason = TASK_SWITCH_IRET;
2486 else if (svm->vmcb->control.exit_info_2 &
2487 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2488 reason = TASK_SWITCH_JMP;
fe8e7f83 2489 else if (idt_v)
64a7ec06
GN		 2490 reason = TASK_SWITCH_GATE;
2491 else
2492 reason = TASK_SWITCH_CALL;
2493
fe8e7f83
GN		 2494 if (reason == TASK_SWITCH_GATE) {
2495 switch (type) {
2496 case SVM_EXITINTINFO_TYPE_NMI:
2497 svm->vcpu.arch.nmi_injected = false;
2498 break;
2499 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2500 if (svm->vmcb->control.exit_info_2 &
2501 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2502 has_error_code = true;
2503 error_code =
2504 (u32)svm->vmcb->control.exit_info_2;
2505 }
fe8e7f83
GN		 2506 kvm_clear_exception_queue(&svm->vcpu);
2507 break;
2508 case SVM_EXITINTINFO_TYPE_INTR:
2509 kvm_clear_interrupt_queue(&svm->vcpu);
2510 break;
2511 default:
2512 break;
2513 }
2514 }
64a7ec06 2515
8317c298
GN		 2516 if (reason != TASK_SWITCH_GATE ||
2517 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2518 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2519 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2520 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2521
acb54517
GN		 2522 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2523 has_error_code, error_code) == EMULATE_FAIL) {
2524 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2525 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2526 svm->vcpu.run->internal.ndata = 0;
2527 return 0;
2528 }
2529 return 1;
6aa8b732
AK		 2530}
2531
851ba692 2532static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2533{
5fdbf976 2534 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2535 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2536 return 1;
6aa8b732
AK		 2537}
2538
851ba692 2539static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2540{
2541 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2542 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2543 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2544 return 1;
2545}
2546
851ba692 2547static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2548{
6d77dbfc 2549 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2550}
2551
851ba692 2552static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2553{
6d77dbfc 2554 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2555}
2556
cda00082
JR		 2557static int cr0_write_interception(struct vcpu_svm *svm)
2558{
2559 struct kvm_vcpu *vcpu = &svm->vcpu;
2560 int r;
2561
2562 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2563
2564 if (svm->nested.vmexit_rip) {
2565 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2566 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2567 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2568 svm->nested.vmexit_rip = 0;
2569 }
2570
2571 return r == EMULATE_DONE;
2572}
2573
851ba692 2574static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2575{
851ba692
AK		 2576 struct kvm_run *kvm_run = svm->vcpu.run;
2577
0a5fff19
GN		 2578 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2579 /* instruction emulation calls kvm_set_cr8() */
851ba692 2580 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2581 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2582 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2583 return 1;
95ba8273 2584 }
0a5fff19
GN		 2585 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2586 return 1;
1d075434
JR		 2587 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2588 return 0;
2589}
2590
6aa8b732
AK		 2591static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2592{
a2fa3e9f
GH		 2593 struct vcpu_svm *svm = to_svm(vcpu);
2594
6aa8b732 2595 switch (ecx) {
af24a4e4 2596 case MSR_IA32_TSC: {
20824f30 2597 u64 tsc_offset;
6aa8b732 2598
2030753d 2599 if (is_guest_mode(vcpu))
20824f30
JR		 2600 tsc_offset = svm->nested.hsave->control.tsc_offset;
2601 else
2602 tsc_offset = svm->vmcb->control.tsc_offset;
2603
2604 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2605 break;
2606 }
8c06585d 2607 case MSR_STAR:
a2fa3e9f 2608 *data = svm->vmcb->save.star;
6aa8b732 2609 break;
0e859cac 2610#ifdef CONFIG_X86_64
6aa8b732 2611 case MSR_LSTAR:
a2fa3e9f 2612 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2613 break;
2614 case MSR_CSTAR:
a2fa3e9f 2615 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2616 break;
2617 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2618 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2619 break;
2620 case MSR_SYSCALL_MASK:
a2fa3e9f 2621 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2622 break;
2623#endif
2624 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2625 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2626 break;
2627 case MSR_IA32_SYSENTER_EIP:
017cb99e 2628 *data = svm->sysenter_eip;
6aa8b732
AK		 2629 break;
2630 case MSR_IA32_SYSENTER_ESP:
017cb99e 2631 *data = svm->sysenter_esp;
6aa8b732 2632 break;
e0231715
JR		 2633 /*
2634 * Nobody will change the following 5 values in the VMCB so we can
2635 * safely return them on rdmsr. They will always be 0 until LBRV is
2636 * implemented.
2637 */
a2938c80
JR		 2638 case MSR_IA32_DEBUGCTLMSR:
2639 *data = svm->vmcb->save.dbgctl;
2640 break;
2641 case MSR_IA32_LASTBRANCHFROMIP:
2642 *data = svm->vmcb->save.br_from;
2643 break;
2644 case MSR_IA32_LASTBRANCHTOIP:
2645 *data = svm->vmcb->save.br_to;
2646 break;
2647 case MSR_IA32_LASTINTFROMIP:
2648 *data = svm->vmcb->save.last_excp_from;
2649 break;
2650 case MSR_IA32_LASTINTTOIP:
2651 *data = svm->vmcb->save.last_excp_to;
2652 break;
b286d5d8 2653 case MSR_VM_HSAVE_PA:
e6aa9abd 2654 *data = svm->nested.hsave_msr;
b286d5d8 2655 break;
eb6f302e 2656 case MSR_VM_CR:
4a810181 2657 *data = svm->nested.vm_cr_msr;
eb6f302e 2658 break;
c8a73f18
AG		 2659 case MSR_IA32_UCODE_REV:
2660 *data = 0x01000065;
2661 break;
6aa8b732 2662 default:
3bab1f5d 2663 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2664 }
2665 return 0;
2666}
2667
851ba692 2668static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2669{
ad312c7c 2670 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2671 u64 data;
2672
59200273
AK		 2673 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2674 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2675 kvm_inject_gp(&svm->vcpu, 0);
59200273 2676 } else {
229456fc 2677 trace_kvm_msr_read(ecx, data);
af9ca2d7 2678
5fdbf976 2679 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2680 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2681 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2682 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2683 }
2684 return 1;
2685}
2686
4a810181
JR		 2687static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2688{
2689 struct vcpu_svm *svm = to_svm(vcpu);
2690 int svm_dis, chg_mask;
2691
2692 if (data & ~SVM_VM_CR_VALID_MASK)
2693 return 1;
2694
2695 chg_mask = SVM_VM_CR_VALID_MASK;
2696
2697 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2698 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2699
2700 svm->nested.vm_cr_msr &= ~chg_mask;
2701 svm->nested.vm_cr_msr |= (data & chg_mask);
2702
2703 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2704
2705 /* check for svm_disable while efer.svme is set */
2706 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2707 return 1;
2708
2709 return 0;
2710}
2711
6aa8b732
AK		 2712static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2713{
a2fa3e9f
GH		 2714 struct vcpu_svm *svm = to_svm(vcpu);
2715
6aa8b732 2716 switch (ecx) {
f4e1b3c8 2717 case MSR_IA32_TSC:
99e3e30a 2718 kvm_write_tsc(vcpu, data);
6aa8b732 2719 break;
8c06585d 2720 case MSR_STAR:
a2fa3e9f 2721 svm->vmcb->save.star = data;
6aa8b732 2722 break;
49b14f24 2723#ifdef CONFIG_X86_64
6aa8b732 2724 case MSR_LSTAR:
a2fa3e9f 2725 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2726 break;
2727 case MSR_CSTAR:
a2fa3e9f 2728 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2729 break;
2730 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2731 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2732 break;
2733 case MSR_SYSCALL_MASK:
a2fa3e9f 2734 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2735 break;
2736#endif
2737 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2738 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2739 break;
2740 case MSR_IA32_SYSENTER_EIP:
017cb99e 2741 svm->sysenter_eip = data;
a2fa3e9f 2742 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2743 break;
2744 case MSR_IA32_SYSENTER_ESP:
017cb99e 2745 svm->sysenter_esp = data;
a2fa3e9f 2746 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2747 break;
a2938c80 2748 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2749 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
24e09cbf 2750 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2751 __func__, data);
24e09cbf
JR		 2752 break;
2753 }
2754 if (data & DEBUGCTL_RESERVED_BITS)
2755 return 1;
2756
2757 svm->vmcb->save.dbgctl = data;
2758 if (data & (1ULL<<0))
2759 svm_enable_lbrv(svm);
2760 else
2761 svm_disable_lbrv(svm);
a2938c80 2762 break;
b286d5d8 2763 case MSR_VM_HSAVE_PA:
e6aa9abd 2764 svm->nested.hsave_msr = data;
62b9abaa 2765 break;
3c5d0a44 2766 case MSR_VM_CR:
4a810181 2767 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2768 case MSR_VM_IGNNE:
3c5d0a44
AG		 2769 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2770 break;
6aa8b732 2771 default:
3bab1f5d 2772 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2773 }
2774 return 0;
2775}
2776
851ba692 2777static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2778{
ad312c7c 2779 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2780 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2781 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2782
af9ca2d7 2783
5fdbf976 2784 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2785 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2786 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2787 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2788 } else {
2789 trace_kvm_msr_write(ecx, data);
e756fc62 2790 skip_emulated_instruction(&svm->vcpu);
59200273 2791 }
6aa8b732
AK		 2792 return 1;
2793}
2794
851ba692 2795static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2796{
e756fc62 2797 if (svm->vmcb->control.exit_info_1)
851ba692 2798 return wrmsr_interception(svm);
6aa8b732 2799 else
851ba692 2800 return rdmsr_interception(svm);
6aa8b732
AK		 2801}
2802
851ba692 2803static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2804{
851ba692
AK		 2805 struct kvm_run *kvm_run = svm->vcpu.run;
2806
3842d135 2807 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2808 svm_clear_vintr(svm);
85f455f7 2809 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2810 /*
2811 * If the user space waits to inject interrupts, exit as soon as
2812 * possible
2813 */
8061823a
GN		 2814 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2815 kvm_run->request_interrupt_window &&
2816 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2817 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2818 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2819 return 0;
2820 }
2821
2822 return 1;
2823}
2824
565d0998
ML		 2825static int pause_interception(struct vcpu_svm *svm)
2826{
2827 kvm_vcpu_on_spin(&(svm->vcpu));
2828 return 1;
2829}
2830
851ba692 2831static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2832 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2833 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2834 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2835 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2836 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
cda00082 2837 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
e0231715
JR		 2838 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2839 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2840 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2841 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2842 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2843 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2844 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2845 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2846 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2847 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2848 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2849 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2850 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2851 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2852 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2853 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2854 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2855 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2856 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2857 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2858 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2859 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2860 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2861 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2862 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2863 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2864 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2865 [SVM_EXIT_SMI] = nop_on_interception,
2866 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2867 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2868 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2869 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2870 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2871 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2872 [SVM_EXIT_HLT] = halt_interception,
a7052897 2873 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2874 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2875 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2876 [SVM_EXIT_MSR] = msr_interception,
2877 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2878 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2879 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2880 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2881 [SVM_EXIT_VMLOAD] = vmload_interception,
2882 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2883 [SVM_EXIT_STGI] = stgi_interception,
2884 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2885 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2886 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2887 [SVM_EXIT_MONITOR] = invalid_op_interception,
2888 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2889 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2890};
2891
3f10c846
JR		 2892void dump_vmcb(struct kvm_vcpu *vcpu)
2893{
2894 struct vcpu_svm *svm = to_svm(vcpu);
2895 struct vmcb_control_area *control = &svm->vmcb->control;
2896 struct vmcb_save_area *save = &svm->vmcb->save;
2897
2898 pr_err("VMCB Control Area:\n");
2899 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2900 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2901 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2902 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2903 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2904 pr_err("intercepts: %016llx\n", control->intercept);
2905 pr_err("pause filter count: %d\n", control->pause_filter_count);
2906 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2907 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2908 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2909 pr_err("asid: %d\n", control->asid);
2910 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2911 pr_err("int_ctl: %08x\n", control->int_ctl);
2912 pr_err("int_vector: %08x\n", control->int_vector);
2913 pr_err("int_state: %08x\n", control->int_state);
2914 pr_err("exit_code: %08x\n", control->exit_code);
2915 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2916 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2917 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2918 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2919 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2920 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2921 pr_err("event_inj: %08x\n", control->event_inj);
2922 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2923 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2924 pr_err("next_rip: %016llx\n", control->next_rip);
2925 pr_err("VMCB State Save Area:\n");
2926 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2927 save->es.selector, save->es.attrib,
2928 save->es.limit, save->es.base);
2929 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2930 save->cs.selector, save->cs.attrib,
2931 save->cs.limit, save->cs.base);
2932 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2933 save->ss.selector, save->ss.attrib,
2934 save->ss.limit, save->ss.base);
2935 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2936 save->ds.selector, save->ds.attrib,
2937 save->ds.limit, save->ds.base);
2938 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2939 save->fs.selector, save->fs.attrib,
2940 save->fs.limit, save->fs.base);
2941 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2942 save->gs.selector, save->gs.attrib,
2943 save->gs.limit, save->gs.base);
2944 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2945 save->gdtr.selector, save->gdtr.attrib,
2946 save->gdtr.limit, save->gdtr.base);
2947 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2948 save->ldtr.selector, save->ldtr.attrib,
2949 save->ldtr.limit, save->ldtr.base);
2950 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2951 save->idtr.selector, save->idtr.attrib,
2952 save->idtr.limit, save->idtr.base);
2953 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2954 save->tr.selector, save->tr.attrib,
2955 save->tr.limit, save->tr.base);
2956 pr_err("cpl: %d efer: %016llx\n",
2957 save->cpl, save->efer);
2958 pr_err("cr0: %016llx cr2: %016llx\n",
2959 save->cr0, save->cr2);
2960 pr_err("cr3: %016llx cr4: %016llx\n",
2961 save->cr3, save->cr4);
2962 pr_err("dr6: %016llx dr7: %016llx\n",
2963 save->dr6, save->dr7);
2964 pr_err("rip: %016llx rflags: %016llx\n",
2965 save->rip, save->rflags);
2966 pr_err("rsp: %016llx rax: %016llx\n",
2967 save->rsp, save->rax);
2968 pr_err("star: %016llx lstar: %016llx\n",
2969 save->star, save->lstar);
2970 pr_err("cstar: %016llx sfmask: %016llx\n",
2971 save->cstar, save->sfmask);
2972 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2973 save->kernel_gs_base, save->sysenter_cs);
2974 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2975 save->sysenter_esp, save->sysenter_eip);
2976 pr_err("gpat: %016llx dbgctl: %016llx\n",
2977 save->g_pat, save->dbgctl);
2978 pr_err("br_from: %016llx br_to: %016llx\n",
2979 save->br_from, save->br_to);
2980 pr_err("excp_from: %016llx excp_to: %016llx\n",
2981 save->last_excp_from, save->last_excp_to);
2982
2983}
2984
586f9607
AK		 2985static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2986{
2987 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2988
2989 *info1 = control->exit_info_1;
2990 *info2 = control->exit_info_2;
2991}
2992
851ba692 2993static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2994{
04d2cc77 2995 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2996 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2997 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2998
aa17911e 2999 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
af9ca2d7 3000
2be4fc7a
JR		 3001 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
3002 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3003 if (npt_enabled)
3004 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 3005
cd3ff653
JR		 3006 if (unlikely(svm->nested.exit_required)) {
3007 nested_svm_vmexit(svm);
3008 svm->nested.exit_required = false;
3009
3010 return 1;
3011 }
3012
2030753d 3013 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3014 int vmexit;
3015
d8cabddf
JR		 3016 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3017 svm->vmcb->control.exit_info_1,
3018 svm->vmcb->control.exit_info_2,
3019 svm->vmcb->control.exit_int_info,
3020 svm->vmcb->control.exit_int_info_err);
3021
410e4d57
JR		 3022 vmexit = nested_svm_exit_special(svm);
3023
3024 if (vmexit == NESTED_EXIT_CONTINUE)
3025 vmexit = nested_svm_exit_handled(svm);
3026
3027 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3028 return 1;
cf74a78b
AG		 3029 }
3030
a5c3832d
JR		 3031 svm_complete_interrupts(svm);
3032
04d2cc77
AK		 3033 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3034 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3035 kvm_run->fail_entry.hardware_entry_failure_reason
3036 = svm->vmcb->control.exit_code;
3f10c846
JR		 3037 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3038 dump_vmcb(vcpu);
04d2cc77
AK		 3039 return 0;
3040 }
3041
a2fa3e9f 3042 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3043 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3044 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3045 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6aa8b732
AK		 3046 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3047 "exit_code 0x%x\n",
b8688d51 3048 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3049 exit_code);
3050
9d8f549d 3051 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3052 || !svm_exit_handlers[exit_code]) {
6aa8b732 3053 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 3054 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 3055 return 0;
3056 }
3057
851ba692 3058 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3059}
3060
3061static void reload_tss(struct kvm_vcpu *vcpu)
3062{
3063 int cpu = raw_smp_processor_id();
3064
0fe1e009
TH		 3065 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3066 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3067 load_TR_desc();
3068}
3069
e756fc62 3070static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 3071{
3072 int cpu = raw_smp_processor_id();
3073
0fe1e009 3074 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 3075
a2fa3e9f 3076 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 3077 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3078 if (svm->asid_generation != sd->asid_generation)
3079 new_asid(svm, sd);
6aa8b732
AK		 3080}
3081
95ba8273
GN		 3082static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3083{
3084 struct vcpu_svm *svm = to_svm(vcpu);
3085
3086 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3087 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 3088 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 3089 ++vcpu->stat.nmi_injections;
3090}
6aa8b732 3091
85f455f7 3092static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 3093{
3094 struct vmcb_control_area *control;
3095
e756fc62 3096 control = &svm->vmcb->control;
85f455f7 3097 control->int_vector = irq;
6aa8b732
AK		 3098 control->int_ctl &= ~V_INTR_PRIO_MASK;
3099 control->int_ctl |= V_IRQ_MASK |
3100 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3101}
3102
66fd3f7f 3103static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3104{
3105 struct vcpu_svm *svm = to_svm(vcpu);
3106
2af9194d 3107 BUG_ON(!(gif_set(svm)));
cf74a78b 3108
9fb2d2b4
GN		 3109 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3110 ++vcpu->stat.irq_injections;
3111
219b65dc
AG		 3112 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3113 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3114}
3115
95ba8273 3116static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3117{
3118 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3119
2030753d 3120 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3121 return;
3122
95ba8273 3123 if (irr == -1)
aaacfc9a
JR		 3124 return;
3125
95ba8273
GN		 3126 if (tpr >= irr)
3127 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3128}
aaacfc9a 3129
95ba8273
GN		 3130static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3131{
3132 struct vcpu_svm *svm = to_svm(vcpu);
3133 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 3134 int ret;
3135 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3136 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3137 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3138
3139 return ret;
aaacfc9a
JR		 3140}
3141
3cfc3092
JK		 3142static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3143{
3144 struct vcpu_svm *svm = to_svm(vcpu);
3145
3146 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3147}
3148
3149static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3150{
3151 struct vcpu_svm *svm = to_svm(vcpu);
3152
3153 if (masked) {
3154 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3155 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3156 } else {
3157 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3158 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3159 }
3160}
3161
78646121
GN		 3162static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3163{
3164 struct vcpu_svm *svm = to_svm(vcpu);
3165 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3166 int ret;
3167
3168 if (!gif_set(svm) ||
3169 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3170 return 0;
3171
3172 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3173
2030753d 3174 if (is_guest_mode(vcpu))
7fcdb510
JR		 3175 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3176
3177 return ret;
78646121
GN		 3178}
3179
9222be18 3180static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3181{
219b65dc 3182 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3183
e0231715
JR		 3184 /*
3185 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3186 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3187 * get that intercept, this function will be called again though and
3188 * we'll get the vintr intercept.
3189 */
8fe54654 3190 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3191 svm_set_vintr(svm);
3192 svm_inject_irq(svm, 0x0);
3193 }
85f455f7
ED		 3194}
3195
95ba8273 3196static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3197{
04d2cc77 3198 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3199
44c11430
GN		 3200 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3201 == HF_NMI_MASK)
3202 return; /* IRET will cause a vm exit */
3203
e0231715
JR		 3204 /*
3205 * Something prevents NMI from been injected. Single step over possible
3206 * problem (IRET or exception injection or interrupt shadow)
3207 */
6be7d306 3208 svm->nmi_singlestep = true;
44c11430
GN		 3209 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3210 update_db_intercept(vcpu);
c1150d8c
DL		 3211}
3212
cbc94022
IE		 3213static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3214{
3215 return 0;
3216}
3217
d9e368d6
AK		 3218static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3219{
3220 force_new_asid(vcpu);
3221}
3222
04d2cc77
AK		 3223static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3224{
3225}
3226
d7bf8221
JR		 3227static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3228{
3229 struct vcpu_svm *svm = to_svm(vcpu);
3230
2030753d 3231 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3232 return;
3233
d7bf8221
JR		 3234 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3235 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3236 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3237 }
3238}
3239
649d6864
JR		 3240static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3241{
3242 struct vcpu_svm *svm = to_svm(vcpu);
3243 u64 cr8;
3244
2030753d 3245 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
88ab24ad
JR		 3246 return;
3247
649d6864
JR		 3248 cr8 = kvm_get_cr8(vcpu);
3249 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3250 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3251}
3252
9222be18
GN		 3253static void svm_complete_interrupts(struct vcpu_svm *svm)
3254{
3255 u8 vector;
3256 int type;
3257 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3258 unsigned int3_injected = svm->int3_injected;
3259
3260 svm->int3_injected = 0;
9222be18 3261
3842d135 3262 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
44c11430 3263 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3264 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3265 }
44c11430 3266
9222be18
GN		 3267 svm->vcpu.arch.nmi_injected = false;
3268 kvm_clear_exception_queue(&svm->vcpu);
3269 kvm_clear_interrupt_queue(&svm->vcpu);
3270
3271 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3272 return;
3273
3842d135
AK		 3274 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3275
9222be18
GN		 3276 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3277 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3278
3279 switch (type) {
3280 case SVM_EXITINTINFO_TYPE_NMI:
3281 svm->vcpu.arch.nmi_injected = true;
3282 break;
3283 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3284 /*
3285 * In case of software exceptions, do not reinject the vector,
3286 * but re-execute the instruction instead. Rewind RIP first
3287 * if we emulated INT3 before.
3288 */
3289 if (kvm_exception_is_soft(vector)) {
3290 if (vector == BP_VECTOR && int3_injected &&
3291 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3292 kvm_rip_write(&svm->vcpu,
3293 kvm_rip_read(&svm->vcpu) -
3294 int3_injected);
9222be18 3295 break;
66b7138f 3296 }
9222be18
GN		 3297 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3298 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3299 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3300
3301 } else
ce7ddec4 3302 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3303 break;
3304 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3305 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3306 break;
3307 default:
3308 break;
3309 }
3310}
3311
b463a6f7
AK		 3312static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3313{
3314 struct vcpu_svm *svm = to_svm(vcpu);
3315 struct vmcb_control_area *control = &svm->vmcb->control;
3316
3317 control->exit_int_info = control->event_inj;
3318 control->exit_int_info_err = control->event_inj_err;
3319 control->event_inj = 0;
3320 svm_complete_interrupts(svm);
3321}
3322
80e31d4f
AK		 3323#ifdef CONFIG_X86_64
3324#define R "r"
3325#else
3326#define R "e"
3327#endif
3328
851ba692 3329static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3330{
a2fa3e9f 3331 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3332
2041a06a
JR		 3333 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3334 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3335 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3336
cd3ff653
JR		 3337 /*
3338 * A vmexit emulation is required before the vcpu can be executed
3339 * again.
3340 */
3341 if (unlikely(svm->nested.exit_required))
3342 return;
3343
e756fc62 3344 pre_svm_run(svm);
6aa8b732 3345
649d6864
JR		 3346 sync_lapic_to_cr8(vcpu);
3347
cda0ffdd 3348 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3349
04d2cc77
AK		 3350 clgi();
3351
3352 local_irq_enable();
36241b8c 3353
6aa8b732 3354 asm volatile (
80e31d4f
AK		 3355 "push %%"R"bp; \n\t"
3356 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3357 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3358 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3359 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3360 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3361 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3362#ifdef CONFIG_X86_64
fb3f0f51
RR		 3363 "mov %c[r8](%[svm]), %%r8 \n\t"
3364 "mov %c[r9](%[svm]), %%r9 \n\t"
3365 "mov %c[r10](%[svm]), %%r10 \n\t"
3366 "mov %c[r11](%[svm]), %%r11 \n\t"
3367 "mov %c[r12](%[svm]), %%r12 \n\t"
3368 "mov %c[r13](%[svm]), %%r13 \n\t"
3369 "mov %c[r14](%[svm]), %%r14 \n\t"
3370 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3371#endif
3372
6aa8b732 3373 /* Enter guest mode */
80e31d4f
AK		 3374 "push %%"R"ax \n\t"
3375 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3376 __ex(SVM_VMLOAD) "\n\t"
3377 __ex(SVM_VMRUN) "\n\t"
3378 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3379 "pop %%"R"ax \n\t"
6aa8b732
AK		 3380
3381 /* Save guest registers, load host registers */
80e31d4f
AK		 3382 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3383 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3384 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3385 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3386 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3387 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3388#ifdef CONFIG_X86_64
fb3f0f51
RR		 3389 "mov %%r8, %c[r8](%[svm]) \n\t"
3390 "mov %%r9, %c[r9](%[svm]) \n\t"
3391 "mov %%r10, %c[r10](%[svm]) \n\t"
3392 "mov %%r11, %c[r11](%[svm]) \n\t"
3393 "mov %%r12, %c[r12](%[svm]) \n\t"
3394 "mov %%r13, %c[r13](%[svm]) \n\t"
3395 "mov %%r14, %c[r14](%[svm]) \n\t"
3396 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3397#endif
80e31d4f 3398 "pop %%"R"bp"
6aa8b732 3399 :
fb3f0f51 3400 : [svm]"a"(svm),
6aa8b732 3401 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3402 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3403 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3404 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3405 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3406 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3407 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3408#ifdef CONFIG_X86_64
ad312c7c
ZX		 3409 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3410 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3411 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3412 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3413 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3414 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3415 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3416 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3417#endif
54a08c04 3418 : "cc", "memory"
80e31d4f 3419 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3420#ifdef CONFIG_X86_64
54a08c04
LV		 3421 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3422#endif
3423 );
6aa8b732 3424
82ca2d10
AK		 3425#ifdef CONFIG_X86_64
3426 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3427#else
dacccfdd 3428 loadsegment(fs, svm->host.fs);
9581d442 3429#endif
6aa8b732
AK		 3430
3431 reload_tss(vcpu);
3432
56ba47dd
AK		 3433 local_irq_disable();
3434
3435 stgi();
3436
13c34e07
AK		 3437 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3438 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3439 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3440 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3441
d7bf8221
JR		 3442 sync_cr8_to_lapic(vcpu);
3443
a2fa3e9f 3444 svm->next_rip = 0;
9222be18 3445
631bc487
GN		 3446 /* if exit due to PF check for async PF */
3447 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3448 svm->apf_reason = kvm_read_and_reset_pf_reason();
3449
6de4f3ad
AK		 3450 if (npt_enabled) {
3451 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3452 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3453 }
fe5913e4
JR		 3454
3455 /*
3456 * We need to handle MC intercepts here before the vcpu has a chance to
3457 * change the physical cpu
3458 */
3459 if (unlikely(svm->vmcb->control.exit_code ==
3460 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3461 svm_handle_mce(svm);
6aa8b732
AK		 3462}
3463
80e31d4f
AK		 3464#undef R
3465
6aa8b732
AK		 3466static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3467{
a2fa3e9f
GH		 3468 struct vcpu_svm *svm = to_svm(vcpu);
3469
3470 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3471 force_new_asid(vcpu);
3472}
3473
1c97f0a0
JR		 3474static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3475{
3476 struct vcpu_svm *svm = to_svm(vcpu);
3477
3478 svm->vmcb->control.nested_cr3 = root;
3479
3480 /* Also sync guest cr3 here in case we live migrate */
3481 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3482
3483 force_new_asid(vcpu);
3484}
3485
6aa8b732
AK		 3486static int is_disabled(void)
3487{
6031a61c
JR		 3488 u64 vm_cr;
3489
3490 rdmsrl(MSR_VM_CR, vm_cr);
3491 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3492 return 1;
3493
6aa8b732
AK		 3494 return 0;
3495}
3496
102d8325
IM		 3497static void
3498svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3499{
3500 /*
3501 * Patch in the VMMCALL instruction:
3502 */
3503 hypercall[0] = 0x0f;
3504 hypercall[1] = 0x01;
3505 hypercall[2] = 0xd9;
102d8325
IM		 3506}
3507
002c7f7c
YS		 3508static void svm_check_processor_compat(void *rtn)
3509{
3510 *(int *)rtn = 0;
3511}
3512
774ead3a
AK		 3513static bool svm_cpu_has_accelerated_tpr(void)
3514{
3515 return false;
3516}
3517
4b12f0de 3518static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3519{
3520 return 0;
3521}
3522
0e851880
SY		 3523static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3524{
3525}
3526
d4330ef2
JR		 3527static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3528{
c2c63a49 3529 switch (func) {
24d1b15f
JR		 3530 case 0x00000001:
3531 /* Mask out xsave bit as long as it is not supported by SVM */
3532 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3533 break;
4c62a2dc
JR		 3534 case 0x80000001:
3535 if (nested)
3536 entry->ecx |= (1 << 2); /* Set SVM bit */
3537 break;
c2c63a49
JR		 3538 case 0x8000000A:
3539 entry->eax = 1; /* SVM revision 1 */
3540 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3541 ASID emulation to nested SVM */
3542 entry->ecx = 0; /* Reserved */
7a190667
JR		 3543 entry->edx = 0; /* Per default do not support any
3544 additional features */
3545
3546 /* Support next_rip if host supports it */
2a6b20b8 3547 if (boot_cpu_has(X86_FEATURE_NRIPS))
7a190667 3548 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49 3549
3d4aeaad
JR		 3550 /* Support NPT for the guest if enabled */
3551 if (npt_enabled)
3552 entry->edx |= SVM_FEATURE_NPT;
3553
c2c63a49
JR		 3554 break;
3555 }
d4330ef2
JR		 3556}
3557
229456fc 3558static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3559 { SVM_EXIT_READ_CR0, "read_cr0" },
3560 { SVM_EXIT_READ_CR3, "read_cr3" },
3561 { SVM_EXIT_READ_CR4, "read_cr4" },
3562 { SVM_EXIT_READ_CR8, "read_cr8" },
3563 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3564 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3565 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3566 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3567 { SVM_EXIT_READ_DR0, "read_dr0" },
3568 { SVM_EXIT_READ_DR1, "read_dr1" },
3569 { SVM_EXIT_READ_DR2, "read_dr2" },
3570 { SVM_EXIT_READ_DR3, "read_dr3" },
3571 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3572 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3573 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3574 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3575 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3576 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3577 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3578 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3579 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3580 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3581 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3582 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3583 { SVM_EXIT_INTR, "interrupt" },
3584 { SVM_EXIT_NMI, "nmi" },
3585 { SVM_EXIT_SMI, "smi" },
3586 { SVM_EXIT_INIT, "init" },
3587 { SVM_EXIT_VINTR, "vintr" },
3588 { SVM_EXIT_CPUID, "cpuid" },
3589 { SVM_EXIT_INVD, "invd" },
3590 { SVM_EXIT_HLT, "hlt" },
3591 { SVM_EXIT_INVLPG, "invlpg" },
3592 { SVM_EXIT_INVLPGA, "invlpga" },
3593 { SVM_EXIT_IOIO, "io" },
3594 { SVM_EXIT_MSR, "msr" },
3595 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3596 { SVM_EXIT_SHUTDOWN, "shutdown" },
3597 { SVM_EXIT_VMRUN, "vmrun" },
3598 { SVM_EXIT_VMMCALL, "hypercall" },
3599 { SVM_EXIT_VMLOAD, "vmload" },
3600 { SVM_EXIT_VMSAVE, "vmsave" },
3601 { SVM_EXIT_STGI, "stgi" },
3602 { SVM_EXIT_CLGI, "clgi" },
3603 { SVM_EXIT_SKINIT, "skinit" },
3604 { SVM_EXIT_WBINVD, "wbinvd" },
3605 { SVM_EXIT_MONITOR, "monitor" },
3606 { SVM_EXIT_MWAIT, "mwait" },
3607 { SVM_EXIT_NPF, "npf" },
3608 { -1, NULL }
3609};
3610
17cc3935 3611static int svm_get_lpage_level(void)
344f414f 3612{
17cc3935 3613 return PT_PDPE_LEVEL;
344f414f
JR		 3614}
3615
4e47c7a6
SY		 3616static bool svm_rdtscp_supported(void)
3617{
3618 return false;
3619}
3620
f5f48ee1
SY		 3621static bool svm_has_wbinvd_exit(void)
3622{
3623 return true;
3624}
3625
02daab21
AK		 3626static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3627{
3628 struct vcpu_svm *svm = to_svm(vcpu);
3629
02daab21 3630 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2030753d 3631 if (is_guest_mode(vcpu))
66a562f7
JR		 3632 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3633 update_cr0_intercept(svm);
02daab21
AK		 3634}
3635
cbdd1bea 3636static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3637 .cpu_has_kvm_support = has_svm,
3638 .disabled_by_bios = is_disabled,
3639 .hardware_setup = svm_hardware_setup,
3640 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3641 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3642 .hardware_enable = svm_hardware_enable,
3643 .hardware_disable = svm_hardware_disable,
774ead3a 3644 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3645
3646 .vcpu_create = svm_create_vcpu,
3647 .vcpu_free = svm_free_vcpu,
04d2cc77 3648 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3649
04d2cc77 3650 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3651 .vcpu_load = svm_vcpu_load,
3652 .vcpu_put = svm_vcpu_put,
3653
3654 .set_guest_debug = svm_guest_debug,
3655 .get_msr = svm_get_msr,
3656 .set_msr = svm_set_msr,
3657 .get_segment_base = svm_get_segment_base,
3658 .get_segment = svm_get_segment,
3659 .set_segment = svm_set_segment,
2e4d2653 3660 .get_cpl = svm_get_cpl,
1747fb71 3661 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3662 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3663 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3664 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3665 .set_cr3 = svm_set_cr3,
3666 .set_cr4 = svm_set_cr4,
3667 .set_efer = svm_set_efer,
3668 .get_idt = svm_get_idt,
3669 .set_idt = svm_set_idt,
3670 .get_gdt = svm_get_gdt,
3671 .set_gdt = svm_set_gdt,
020df079 3672 .set_dr7 = svm_set_dr7,
6de4f3ad 3673 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3674 .get_rflags = svm_get_rflags,
3675 .set_rflags = svm_set_rflags,
6b52d186 3676 .fpu_activate = svm_fpu_activate,
02daab21 3677 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3678
6aa8b732 3679 .tlb_flush = svm_flush_tlb,
6aa8b732 3680
6aa8b732 3681 .run = svm_vcpu_run,
04d2cc77 3682 .handle_exit = handle_exit,
6aa8b732 3683 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3684 .set_interrupt_shadow = svm_set_interrupt_shadow,
3685 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3686 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3687 .set_irq = svm_set_irq,
95ba8273 3688 .set_nmi = svm_inject_nmi,
298101da 3689 .queue_exception = svm_queue_exception,
b463a6f7 3690 .cancel_injection = svm_cancel_injection,
78646121 3691 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3692 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3693 .get_nmi_mask = svm_get_nmi_mask,
3694 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3695 .enable_nmi_window = enable_nmi_window,
3696 .enable_irq_window = enable_irq_window,
3697 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3698
3699 .set_tss_addr = svm_set_tss_addr,
67253af5 3700 .get_tdp_level = get_npt_level,
4b12f0de 3701 .get_mt_mask = svm_get_mt_mask,
229456fc 3702
586f9607 3703 .get_exit_info = svm_get_exit_info,
229456fc 3704 .exit_reasons_str = svm_exit_reasons_str,
586f9607 3705
17cc3935 3706 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3707
3708 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3709
3710 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3711
3712 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3713
3714 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a
ZA		 3715
3716 .write_tsc_offset = svm_write_tsc_offset,
e48672fa 3717 .adjust_tsc_offset = svm_adjust_tsc_offset,
1c97f0a0
JR		 3718
3719 .set_tdp_cr3 = set_tdp_cr3,
6aa8b732
AK		 3720};
3721
3722static int __init svm_init(void)
3723{
cb498ea2 3724 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3725 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3726}
3727
3728static void __exit svm_exit(void)
3729{
cb498ea2 3730 kvm_exit();
6aa8b732
AK		 3731}
3732
3733module_init(svm_init)
3734module_exit(svm_exit)
Linux kernel - Deliverables
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