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KVM: SVM: Move msrpm offset calculation to seperate function
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
66b7138f 50#define SVM_FEATURE_NRIP (1 << 3)
565d0998 51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
aad42c64 82
cd3ff653
JR		 83 /* A VMEXIT is required but not yet emulated */
84 bool exit_required;
85
aad42c64
JR		 86 /* cache for intercepts of the guest */
87 u16 intercept_cr_read;
88 u16 intercept_cr_write;
89 u16 intercept_dr_read;
90 u16 intercept_dr_write;
91 u32 intercept_exceptions;
92 u64 intercept;
93
e6aa9abd
JR		 94};
95
6c8166a7
AK		 96struct vcpu_svm {
97 struct kvm_vcpu vcpu;
98 struct vmcb *vmcb;
99 unsigned long vmcb_pa;
100 struct svm_cpu_data *svm_data;
101 uint64_t asid_generation;
102 uint64_t sysenter_esp;
103 uint64_t sysenter_eip;
104
105 u64 next_rip;
106
107 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
108 u64 host_gs_base;
6c8166a7
AK		 109
110 u32 *msrpm;
6c8166a7 111
e6aa9abd 112 struct nested_state nested;
6be7d306
JK		 113
114 bool nmi_singlestep;
66b7138f
JK		 115
116 unsigned int3_injected;
117 unsigned long int3_rip;
6c8166a7
AK		 118};
119
455716fa
JR		 120#define MSR_INVALID 0xffffffffU
121
709ddebf
JR		 122/* enable NPT for AMD64 and X86 with PAE */
123#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
124static bool npt_enabled = true;
125#else
e0231715 126static bool npt_enabled;
709ddebf 127#endif
6c7dac72
JR		 128static int npt = 1;
129
130module_param(npt, int, S_IRUGO);
e3da3acd 131
4b6e4dca 132static int nested = 1;
236de055
AG		 133module_param(nested, int, S_IRUGO);
134
44874f84 135static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 136static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 137
410e4d57 138static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 139static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 140static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 141static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
142 bool has_error_code, u32 error_code);
143
a2fa3e9f
GH		 144static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
145{
fb3f0f51 146 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 147}
148
3d6368ef
AG		 149static inline bool is_nested(struct vcpu_svm *svm)
150{
e6aa9abd 151 return svm->nested.vmcb;
3d6368ef
AG		 152}
153
2af9194d
JR		 154static inline void enable_gif(struct vcpu_svm *svm)
155{
156 svm->vcpu.arch.hflags |= HF_GIF_MASK;
157}
158
159static inline void disable_gif(struct vcpu_svm *svm)
160{
161 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
162}
163
164static inline bool gif_set(struct vcpu_svm *svm)
165{
166 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
167}
168
4866d5e3 169static unsigned long iopm_base;
6aa8b732
AK		 170
171struct kvm_ldttss_desc {
172 u16 limit0;
173 u16 base0;
e0231715
JR		 174 unsigned base1:8, type:5, dpl:2, p:1;
175 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 176 u32 base3;
177 u32 zero1;
178} __attribute__((packed));
179
180struct svm_cpu_data {
181 int cpu;
182
5008fdf5
AK		 183 u64 asid_generation;
184 u32 max_asid;
185 u32 next_asid;
6aa8b732
AK		 186 struct kvm_ldttss_desc *tss_desc;
187
188 struct page *save_area;
189};
190
191static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 192static uint32_t svm_features;
6aa8b732
AK		 193
194struct svm_init_data {
195 int cpu;
196 int r;
197};
198
199static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
200
9d8f549d 201#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 202#define MSRS_RANGE_SIZE 2048
203#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
204
455716fa
JR		 205static u32 svm_msrpm_offset(u32 msr)
206{
207 u32 offset;
208 int i;
209
210 for (i = 0; i < NUM_MSR_MAPS; i++) {
211 if (msr < msrpm_ranges[i] ||
212 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
213 continue;
214
215 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
216 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
217
218 /* Now we have the u8 offset - but need the u32 offset */
219 return offset / 4;
220 }
221
222 /* MSR not in any range */
223 return MSR_INVALID;
224}
225
6aa8b732
AK		 226#define MAX_INST_SIZE 15
227
80b7706e
JR		 228static inline u32 svm_has(u32 feat)
229{
230 return svm_features & feat;
231}
232
6aa8b732
AK		 233static inline void clgi(void)
234{
4ecac3fd 235 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 236}
237
238static inline void stgi(void)
239{
4ecac3fd 240 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 241}
242
243static inline void invlpga(unsigned long addr, u32 asid)
244{
e0231715 245 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 246}
247
6aa8b732
AK		 248static inline void force_new_asid(struct kvm_vcpu *vcpu)
249{
a2fa3e9f 250 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 251}
252
253static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
254{
255 force_new_asid(vcpu);
256}
257
258static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
259{
709ddebf 260 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 261 efer &= ~EFER_LME;
6aa8b732 262
9962d032 263 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 264 vcpu->arch.efer = efer;
6aa8b732
AK		 265}
266
6aa8b732
AK		 267static int is_external_interrupt(u32 info)
268{
269 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
270 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
271}
272
2809f5d2
GC		 273static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
274{
275 struct vcpu_svm *svm = to_svm(vcpu);
276 u32 ret = 0;
277
278 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 279 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 280 return ret & mask;
281}
282
283static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
284{
285 struct vcpu_svm *svm = to_svm(vcpu);
286
287 if (mask == 0)
288 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
289 else
290 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
291
292}
293
6aa8b732
AK		 294static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
295{
a2fa3e9f
GH		 296 struct vcpu_svm *svm = to_svm(vcpu);
297
298 if (!svm->next_rip) {
851ba692 299 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 300 EMULATE_DONE)
301 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 302 return;
303 }
5fdbf976
MT		 304 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
305 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
306 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 307
5fdbf976 308 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 309 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 310}
311
116a4752
JK		 312static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
313 bool has_error_code, u32 error_code)
314{
315 struct vcpu_svm *svm = to_svm(vcpu);
316
e0231715
JR		 317 /*
318 * If we are within a nested VM we'd better #VMEXIT and let the guest
319 * handle the exception
320 */
116a4752
JK		 321 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
322 return;
323
66b7138f
JK		 324 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
325 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
326
327 /*
328 * For guest debugging where we have to reinject #BP if some
329 * INT3 is guest-owned:
330 * Emulate nRIP by moving RIP forward. Will fail if injection
331 * raises a fault that is not intercepted. Still better than
332 * failing in all cases.
333 */
334 skip_emulated_instruction(&svm->vcpu);
335 rip = kvm_rip_read(&svm->vcpu);
336 svm->int3_rip = rip + svm->vmcb->save.cs.base;
337 svm->int3_injected = rip - old_rip;
338 }
339
116a4752
JK		 340 svm->vmcb->control.event_inj = nr
341 | SVM_EVTINJ_VALID
342 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
343 | SVM_EVTINJ_TYPE_EXEPT;
344 svm->vmcb->control.event_inj_err = error_code;
345}
346
6aa8b732
AK		 347static int has_svm(void)
348{
63d1142f 349 const char *msg;
6aa8b732 350
63d1142f 351 if (!cpu_has_svm(&msg)) {
ff81ff10 352 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 353 return 0;
354 }
355
6aa8b732
AK		 356 return 1;
357}
358
359static void svm_hardware_disable(void *garbage)
360{
2c8dceeb 361 cpu_svm_disable();
6aa8b732
AK		 362}
363
10474ae8 364static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 365{
366
0fe1e009 367 struct svm_cpu_data *sd;
6aa8b732 368 uint64_t efer;
89a27f4d 369 struct desc_ptr gdt_descr;
6aa8b732
AK		 370 struct desc_struct *gdt;
371 int me = raw_smp_processor_id();
372
10474ae8
AG		 373 rdmsrl(MSR_EFER, efer);
374 if (efer & EFER_SVME)
375 return -EBUSY;
376
6aa8b732 377 if (!has_svm()) {
e6732a5a
ZA		 378 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
379 me);
10474ae8 380 return -EINVAL;
6aa8b732 381 }
0fe1e009 382 sd = per_cpu(svm_data, me);
6aa8b732 383
0fe1e009 384 if (!sd) {
e6732a5a 385 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 386 me);
10474ae8 387 return -EINVAL;
6aa8b732
AK		 388 }
389
0fe1e009
TH		 390 sd->asid_generation = 1;
391 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
392 sd->next_asid = sd->max_asid + 1;
6aa8b732 393
d6ab1ed4 394 native_store_gdt(&gdt_descr);
89a27f4d 395 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 396 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 397
9962d032 398 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 399
d0316554 400 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 401
402 return 0;
6aa8b732
AK		 403}
404
0da1db75
JR		 405static void svm_cpu_uninit(int cpu)
406{
0fe1e009 407 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 408
0fe1e009 409 if (!sd)
0da1db75
JR		 410 return;
411
412 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 413 __free_page(sd->save_area);
414 kfree(sd);
0da1db75
JR		 415}
416
6aa8b732
AK		 417static int svm_cpu_init(int cpu)
418{
0fe1e009 419 struct svm_cpu_data *sd;
6aa8b732
AK		 420 int r;
421
0fe1e009
TH		 422 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
423 if (!sd)
6aa8b732 424 return -ENOMEM;
0fe1e009
TH		 425 sd->cpu = cpu;
426 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 427 r = -ENOMEM;
0fe1e009 428 if (!sd->save_area)
6aa8b732
AK		 429 goto err_1;
430
0fe1e009 431 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 432
433 return 0;
434
435err_1:
0fe1e009 436 kfree(sd);
6aa8b732
AK		 437 return r;
438
439}
440
bfc733a7
RR		 441static void set_msr_interception(u32 *msrpm, unsigned msr,
442 int read, int write)
6aa8b732 443{
455716fa
JR		 444 u8 bit_read, bit_write;
445 unsigned long tmp;
446 u32 offset;
6aa8b732 447
455716fa
JR		 448 offset = svm_msrpm_offset(msr);
449 bit_read = 2 * (msr & 0x0f);
450 bit_write = 2 * (msr & 0x0f) + 1;
451 tmp = msrpm[offset];
452
453 BUG_ON(offset == MSR_INVALID);
454
455 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
456 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
457
458 msrpm[offset] = tmp;
6aa8b732
AK		 459}
460
f65c229c
JR		 461static void svm_vcpu_init_msrpm(u32 *msrpm)
462{
463 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
464
465#ifdef CONFIG_X86_64
466 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
467 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
468 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
469 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
470 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
471 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
472#endif
473 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
474 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 475}
476
24e09cbf
JR		 477static void svm_enable_lbrv(struct vcpu_svm *svm)
478{
479 u32 *msrpm = svm->msrpm;
480
481 svm->vmcb->control.lbr_ctl = 1;
482 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
483 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
484 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
485 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
486}
487
488static void svm_disable_lbrv(struct vcpu_svm *svm)
489{
490 u32 *msrpm = svm->msrpm;
491
492 svm->vmcb->control.lbr_ctl = 0;
493 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
494 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
495 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
496 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
497}
498
6aa8b732
AK		 499static __init int svm_hardware_setup(void)
500{
501 int cpu;
502 struct page *iopm_pages;
f65c229c 503 void *iopm_va;
6aa8b732
AK		 504 int r;
505
6aa8b732
AK		 506 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
507
508 if (!iopm_pages)
509 return -ENOMEM;
c8681339
AL		 510
511 iopm_va = page_address(iopm_pages);
512 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 513 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
514
50a37eb4
JR		 515 if (boot_cpu_has(X86_FEATURE_NX))
516 kvm_enable_efer_bits(EFER_NX);
517
1b2fd70c
AG		 518 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
519 kvm_enable_efer_bits(EFER_FFXSR);
520
236de055
AG		 521 if (nested) {
522 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
523 kvm_enable_efer_bits(EFER_SVME);
524 }
525
3230bb47 526 for_each_possible_cpu(cpu) {
6aa8b732
AK		 527 r = svm_cpu_init(cpu);
528 if (r)
f65c229c 529 goto err;
6aa8b732 530 }
33bd6a0b
JR		 531
532 svm_features = cpuid_edx(SVM_CPUID_FUNC);
533
e3da3acd
JR		 534 if (!svm_has(SVM_FEATURE_NPT))
535 npt_enabled = false;
536
6c7dac72
JR		 537 if (npt_enabled && !npt) {
538 printk(KERN_INFO "kvm: Nested Paging disabled\n");
539 npt_enabled = false;
540 }
541
18552672 542 if (npt_enabled) {
e3da3acd 543 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 544 kvm_enable_tdp();
5f4cb662
JR		 545 } else
546 kvm_disable_tdp();
e3da3acd 547
6aa8b732
AK		 548 return 0;
549
f65c229c 550err:
6aa8b732
AK		 551 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
552 iopm_base = 0;
553 return r;
554}
555
556static __exit void svm_hardware_unsetup(void)
557{
0da1db75
JR		 558 int cpu;
559
3230bb47 560 for_each_possible_cpu(cpu)
0da1db75
JR		 561 svm_cpu_uninit(cpu);
562
6aa8b732 563 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 564 iopm_base = 0;
6aa8b732
AK		 565}
566
567static void init_seg(struct vmcb_seg *seg)
568{
569 seg->selector = 0;
570 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 571 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 572 seg->limit = 0xffff;
573 seg->base = 0;
574}
575
576static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
577{
578 seg->selector = 0;
579 seg->attrib = SVM_SELECTOR_P_MASK | type;
580 seg->limit = 0xffff;
581 seg->base = 0;
582}
583
e6101a96 584static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 585{
e6101a96
JR		 586 struct vmcb_control_area *control = &svm->vmcb->control;
587 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 588
bff78274
AK		 589 svm->vcpu.fpu_active = 1;
590
e0231715 591 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 592 INTERCEPT_CR3_MASK |
649d6864 593 INTERCEPT_CR4_MASK;
6aa8b732 594
e0231715 595 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 596 INTERCEPT_CR3_MASK |
80a8119c
AK		 597 INTERCEPT_CR4_MASK |
598 INTERCEPT_CR8_MASK;
6aa8b732 599
e0231715 600 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 601 INTERCEPT_DR1_MASK |
602 INTERCEPT_DR2_MASK |
727f5a23
JK		 603 INTERCEPT_DR3_MASK |
604 INTERCEPT_DR4_MASK |
605 INTERCEPT_DR5_MASK |
606 INTERCEPT_DR6_MASK |
607 INTERCEPT_DR7_MASK;
6aa8b732 608
e0231715 609 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 610 INTERCEPT_DR1_MASK |
611 INTERCEPT_DR2_MASK |
612 INTERCEPT_DR3_MASK |
727f5a23 613 INTERCEPT_DR4_MASK |
6aa8b732 614 INTERCEPT_DR5_MASK |
727f5a23 615 INTERCEPT_DR6_MASK |
6aa8b732
AK		 616 INTERCEPT_DR7_MASK;
617
7aa81cc0 618 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 619 (1 << UD_VECTOR) |
620 (1 << MC_VECTOR);
6aa8b732
AK		 621
622
e0231715 623 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 624 (1ULL << INTERCEPT_NMI) |
0152527b 625 (1ULL << INTERCEPT_SMI) |
d225157b 626 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 627 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 628 (1ULL << INTERCEPT_INVD) |
6aa8b732 629 (1ULL << INTERCEPT_HLT) |
a7052897 630 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 631 (1ULL << INTERCEPT_INVLPGA) |
632 (1ULL << INTERCEPT_IOIO_PROT) |
633 (1ULL << INTERCEPT_MSR_PROT) |
634 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 635 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 636 (1ULL << INTERCEPT_VMRUN) |
637 (1ULL << INTERCEPT_VMMCALL) |
638 (1ULL << INTERCEPT_VMLOAD) |
639 (1ULL << INTERCEPT_VMSAVE) |
640 (1ULL << INTERCEPT_STGI) |
641 (1ULL << INTERCEPT_CLGI) |
916ce236 642 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 643 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 644 (1ULL << INTERCEPT_MONITOR) |
645 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 646
647 control->iopm_base_pa = iopm_base;
f65c229c 648 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 649 control->tsc_offset = 0;
6aa8b732
AK		 650 control->int_ctl = V_INTR_MASKING_MASK;
651
652 init_seg(&save->es);
653 init_seg(&save->ss);
654 init_seg(&save->ds);
655 init_seg(&save->fs);
656 init_seg(&save->gs);
657
658 save->cs.selector = 0xf000;
659 /* Executable/Readable Code Segment */
660 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
661 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
662 save->cs.limit = 0xffff;
d92899a0
AK		 663 /*
664 * cs.base should really be 0xffff0000, but vmx can't handle that, so
665 * be consistent with it.
666 *
667 * Replace when we have real mode working for vmx.
668 */
669 save->cs.base = 0xf0000;
6aa8b732
AK		 670
671 save->gdtr.limit = 0xffff;
672 save->idtr.limit = 0xffff;
673
674 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
675 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
676
9962d032 677 save->efer = EFER_SVME;
d77c26fc 678 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 679 save->dr7 = 0x400;
680 save->rflags = 2;
681 save->rip = 0x0000fff0;
5fdbf976 682 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 683
e0231715
JR		 684 /*
685 * This is the guest-visible cr0 value.
18fa000a 686 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 687 */
18fa000a
EH		 688 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
689 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
690
66aee91a 691 save->cr4 = X86_CR4_PAE;
6aa8b732 692 /* rdx = ?? */
709ddebf
JR		 693
694 if (npt_enabled) {
695 /* Setup VMCB for Nested Paging */
696 control->nested_ctl = 1;
a7052897
MT		 697 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
698 (1ULL << INTERCEPT_INVLPG));
709ddebf 699 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 700 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
701 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 702 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 703 save->cr3 = 0;
704 save->cr4 = 0;
705 }
a79d2f18 706 force_new_asid(&svm->vcpu);
1371d904 707
e6aa9abd 708 svm->nested.vmcb = 0;
2af9194d
JR		 709 svm->vcpu.arch.hflags = 0;
710
565d0998
ML		 711 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
712 control->pause_filter_count = 3000;
713 control->intercept |= (1ULL << INTERCEPT_PAUSE);
714 }
715
2af9194d 716 enable_gif(svm);
6aa8b732
AK		 717}
718
e00c8cf2 719static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 720{
721 struct vcpu_svm *svm = to_svm(vcpu);
722
e6101a96 723 init_vmcb(svm);
70433389 724
c5af89b6 725 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 726 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 727 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
728 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 729 }
5fdbf976
MT		 730 vcpu->arch.regs_avail = ~0;
731 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 732
733 return 0;
04d2cc77
AK		 734}
735
fb3f0f51 736static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 737{
a2fa3e9f 738 struct vcpu_svm *svm;
6aa8b732 739 struct page *page;
f65c229c 740 struct page *msrpm_pages;
b286d5d8 741 struct page *hsave_page;
3d6368ef 742 struct page *nested_msrpm_pages;
fb3f0f51 743 int err;
6aa8b732 744
c16f862d 745 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 746 if (!svm) {
747 err = -ENOMEM;
748 goto out;
749 }
750
751 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
752 if (err)
753 goto free_svm;
754
b7af4043 755 err = -ENOMEM;
6aa8b732 756 page = alloc_page(GFP_KERNEL);
b7af4043 757 if (!page)
fb3f0f51 758 goto uninit;
6aa8b732 759
f65c229c
JR		 760 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
761 if (!msrpm_pages)
b7af4043 762 goto free_page1;
3d6368ef
AG		 763
764 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
765 if (!nested_msrpm_pages)
b7af4043 766 goto free_page2;
f65c229c 767
b286d5d8
AG		 768 hsave_page = alloc_page(GFP_KERNEL);
769 if (!hsave_page)
b7af4043
TY		 770 goto free_page3;
771
e6aa9abd 772 svm->nested.hsave = page_address(hsave_page);
b286d5d8 773
b7af4043
TY		 774 svm->msrpm = page_address(msrpm_pages);
775 svm_vcpu_init_msrpm(svm->msrpm);
776
e6aa9abd 777 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 778
a2fa3e9f
GH		 779 svm->vmcb = page_address(page);
780 clear_page(svm->vmcb);
781 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
782 svm->asid_generation = 0;
e6101a96 783 init_vmcb(svm);
a2fa3e9f 784
fb3f0f51 785 fx_init(&svm->vcpu);
ad312c7c 786 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 787 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 788 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 789
fb3f0f51 790 return &svm->vcpu;
36241b8c 791
b7af4043
TY		 792free_page3:
793 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
794free_page2:
795 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
796free_page1:
797 __free_page(page);
fb3f0f51
RR		 798uninit:
799 kvm_vcpu_uninit(&svm->vcpu);
800free_svm:
a4770347 801 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 802out:
803 return ERR_PTR(err);
6aa8b732
AK		 804}
805
806static void svm_free_vcpu(struct kvm_vcpu *vcpu)
807{
a2fa3e9f
GH		 808 struct vcpu_svm *svm = to_svm(vcpu);
809
fb3f0f51 810 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 811 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 812 __free_page(virt_to_page(svm->nested.hsave));
813 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 814 kvm_vcpu_uninit(vcpu);
a4770347 815 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 816}
817
15ad7146 818static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 819{
a2fa3e9f 820 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 821 int i;
0cc5064d 822
0cc5064d 823 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 824 u64 delta;
0cc5064d 825
953899b6
JR		 826 if (check_tsc_unstable()) {
827 /*
828 * Make sure that the guest sees a monotonically
829 * increasing TSC.
830 */
831 delta = vcpu->arch.host_tsc - native_read_tsc();
832 svm->vmcb->control.tsc_offset += delta;
833 if (is_nested(svm))
834 svm->nested.hsave->control.tsc_offset += delta;
835 }
0cc5064d 836 vcpu->cpu = cpu;
2f599714 837 kvm_migrate_timers(vcpu);
4b656b12 838 svm->asid_generation = 0;
0cc5064d 839 }
94dfbdb3
AL		 840
841 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 842 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 843}
844
845static void svm_vcpu_put(struct kvm_vcpu *vcpu)
846{
a2fa3e9f 847 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 848 int i;
849
e1beb1d3 850 ++vcpu->stat.host_state_reload;
94dfbdb3 851 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 852 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 853
e935d48e 854 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 855}
856
6aa8b732
AK		 857static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
858{
a2fa3e9f 859 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 860}
861
862static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
863{
a2fa3e9f 864 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 865}
866
6de4f3ad
AK		 867static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
868{
869 switch (reg) {
870 case VCPU_EXREG_PDPTR:
871 BUG_ON(!npt_enabled);
872 load_pdptrs(vcpu, vcpu->arch.cr3);
873 break;
874 default:
875 BUG();
876 }
877}
878
f0b85051
AG		 879static void svm_set_vintr(struct vcpu_svm *svm)
880{
881 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
882}
883
884static void svm_clear_vintr(struct vcpu_svm *svm)
885{
886 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
887}
888
6aa8b732
AK		 889static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
890{
a2fa3e9f 891 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 892
893 switch (seg) {
894 case VCPU_SREG_CS: return &save->cs;
895 case VCPU_SREG_DS: return &save->ds;
896 case VCPU_SREG_ES: return &save->es;
897 case VCPU_SREG_FS: return &save->fs;
898 case VCPU_SREG_GS: return &save->gs;
899 case VCPU_SREG_SS: return &save->ss;
900 case VCPU_SREG_TR: return &save->tr;
901 case VCPU_SREG_LDTR: return &save->ldtr;
902 }
903 BUG();
8b6d44c7 904 return NULL;
6aa8b732
AK		 905}
906
907static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
908{
909 struct vmcb_seg *s = svm_seg(vcpu, seg);
910
911 return s->base;
912}
913
914static void svm_get_segment(struct kvm_vcpu *vcpu,
915 struct kvm_segment *var, int seg)
916{
917 struct vmcb_seg *s = svm_seg(vcpu, seg);
918
919 var->base = s->base;
920 var->limit = s->limit;
921 var->selector = s->selector;
922 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
923 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
924 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
925 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
926 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
927 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
928 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
929 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 930
e0231715
JR		 931 /*
932 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 933 * for cross vendor migration purposes by "not present"
934 */
935 var->unusable = !var->present || (var->type == 0);
936
1fbdc7a5
AP		 937 switch (seg) {
938 case VCPU_SREG_CS:
939 /*
940 * SVM always stores 0 for the 'G' bit in the CS selector in
941 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
942 * Intel's VMENTRY has a check on the 'G' bit.
943 */
25022acc 944 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 945 break;
946 case VCPU_SREG_TR:
947 /*
948 * Work around a bug where the busy flag in the tr selector
949 * isn't exposed
950 */
c0d09828 951 var->type |= 0x2;
1fbdc7a5
AP		 952 break;
953 case VCPU_SREG_DS:
954 case VCPU_SREG_ES:
955 case VCPU_SREG_FS:
956 case VCPU_SREG_GS:
957 /*
958 * The accessed bit must always be set in the segment
959 * descriptor cache, although it can be cleared in the
960 * descriptor, the cached bit always remains at 1. Since
961 * Intel has a check on this, set it here to support
962 * cross-vendor migration.
963 */
964 if (!var->unusable)
965 var->type |= 0x1;
966 break;
b586eb02 967 case VCPU_SREG_SS:
e0231715
JR		 968 /*
969 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 970 * descriptor is left as 1, although the whole segment has
971 * been made unusable. Clear it here to pass an Intel VMX
972 * entry check when cross vendor migrating.
973 */
974 if (var->unusable)
975 var->db = 0;
976 break;
1fbdc7a5 977 }
6aa8b732
AK		 978}
979
2e4d2653
IE		 980static int svm_get_cpl(struct kvm_vcpu *vcpu)
981{
982 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
983
984 return save->cpl;
985}
986
89a27f4d 987static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 988{
a2fa3e9f
GH		 989 struct vcpu_svm *svm = to_svm(vcpu);
990
89a27f4d
GN		 991 dt->size = svm->vmcb->save.idtr.limit;
992 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 993}
994
89a27f4d 995static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 996{
a2fa3e9f
GH		 997 struct vcpu_svm *svm = to_svm(vcpu);
998
89a27f4d
GN		 999 svm->vmcb->save.idtr.limit = dt->size;
1000 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1001}
1002
89a27f4d 1003static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1004{
a2fa3e9f
GH		 1005 struct vcpu_svm *svm = to_svm(vcpu);
1006
89a27f4d
GN		 1007 dt->size = svm->vmcb->save.gdtr.limit;
1008 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1009}
1010
89a27f4d 1011static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1012{
a2fa3e9f
GH		 1013 struct vcpu_svm *svm = to_svm(vcpu);
1014
89a27f4d
GN		 1015 svm->vmcb->save.gdtr.limit = dt->size;
1016 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1017}
1018
e8467fda
AK		 1019static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1020{
1021}
1022
25c4c276 1023static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1024{
1025}
1026
d225157b
AK		 1027static void update_cr0_intercept(struct vcpu_svm *svm)
1028{
66a562f7 1029 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1030 ulong gcr0 = svm->vcpu.arch.cr0;
1031 u64 *hcr0 = &svm->vmcb->save.cr0;
1032
1033 if (!svm->vcpu.fpu_active)
1034 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1035 else
1036 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1037 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1038
1039
1040 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1041 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1042 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1043 if (is_nested(svm)) {
1044 struct vmcb *hsave = svm->nested.hsave;
1045
1046 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1047 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1048 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1049 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1050 }
d225157b
AK		 1051 } else {
1052 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1053 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1054 if (is_nested(svm)) {
1055 struct vmcb *hsave = svm->nested.hsave;
1056
1057 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1058 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1059 }
d225157b
AK		 1060 }
1061}
1062
6aa8b732
AK		 1063static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1064{
a2fa3e9f
GH		 1065 struct vcpu_svm *svm = to_svm(vcpu);
1066
7f5d8b56
JR		 1067 if (is_nested(svm)) {
1068 /*
1069 * We are here because we run in nested mode, the host kvm
1070 * intercepts cr0 writes but the l1 hypervisor does not.
1071 * But the L1 hypervisor may intercept selective cr0 writes.
1072 * This needs to be checked here.
1073 */
1074 unsigned long old, new;
1075
1076 /* Remove bits that would trigger a real cr0 write intercept */
1077 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1078 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1079
1080 if (old == new) {
1081 /* cr0 write with ts and mp unchanged */
1082 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1083 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1084 return;
1085 }
1086 }
1087
05b3e0c2 1088#ifdef CONFIG_X86_64
f6801dff 1089 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1090 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1091 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1092 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1093 }
1094
d77c26fc 1095 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1096 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1097 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1098 }
1099 }
1100#endif
ad312c7c 1101 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1102
1103 if (!npt_enabled)
1104 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1105
1106 if (!vcpu->fpu_active)
334df50a 1107 cr0 |= X86_CR0_TS;
709ddebf
JR		 1108 /*
1109 * re-enable caching here because the QEMU bios
1110 * does not do it - this results in some delay at
1111 * reboot
1112 */
1113 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1114 svm->vmcb->save.cr0 = cr0;
d225157b 1115 update_cr0_intercept(svm);
6aa8b732
AK		 1116}
1117
1118static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1119{
6394b649 1120 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1121 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1122
1123 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1124 force_new_asid(vcpu);
6394b649 1125
ec077263
JR		 1126 vcpu->arch.cr4 = cr4;
1127 if (!npt_enabled)
1128 cr4 |= X86_CR4_PAE;
6394b649 1129 cr4 |= host_cr4_mce;
ec077263 1130 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1131}
1132
1133static void svm_set_segment(struct kvm_vcpu *vcpu,
1134 struct kvm_segment *var, int seg)
1135{
a2fa3e9f 1136 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1137 struct vmcb_seg *s = svm_seg(vcpu, seg);
1138
1139 s->base = var->base;
1140 s->limit = var->limit;
1141 s->selector = var->selector;
1142 if (var->unusable)
1143 s->attrib = 0;
1144 else {
1145 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1146 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1147 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1148 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1149 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1150 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1151 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1152 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1153 }
1154 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1155 svm->vmcb->save.cpl
1156 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1157 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1158
1159}
1160
44c11430 1161static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1162{
d0bfb940
JK		 1163 struct vcpu_svm *svm = to_svm(vcpu);
1164
d0bfb940
JK		 1165 svm->vmcb->control.intercept_exceptions &=
1166 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1167
6be7d306 1168 if (svm->nmi_singlestep)
44c11430
GN		 1169 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1170
d0bfb940
JK		 1171 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1172 if (vcpu->guest_debug &
1173 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1174 svm->vmcb->control.intercept_exceptions |=
1175 1 << DB_VECTOR;
1176 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1177 svm->vmcb->control.intercept_exceptions |=
1178 1 << BP_VECTOR;
1179 } else
1180 vcpu->guest_debug = 0;
44c11430
GN		 1181}
1182
355be0b9 1183static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1184{
44c11430
GN		 1185 struct vcpu_svm *svm = to_svm(vcpu);
1186
ae675ef0
JK		 1187 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1188 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1189 else
1190 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1191
355be0b9 1192 update_db_intercept(vcpu);
6aa8b732
AK		 1193}
1194
1195static void load_host_msrs(struct kvm_vcpu *vcpu)
1196{
94dfbdb3 1197#ifdef CONFIG_X86_64
a2fa3e9f 1198 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1199#endif
6aa8b732
AK		 1200}
1201
1202static void save_host_msrs(struct kvm_vcpu *vcpu)
1203{
94dfbdb3 1204#ifdef CONFIG_X86_64
a2fa3e9f 1205 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1206#endif
6aa8b732
AK		 1207}
1208
0fe1e009 1209static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1210{
0fe1e009
TH		 1211 if (sd->next_asid > sd->max_asid) {
1212 ++sd->asid_generation;
1213 sd->next_asid = 1;
a2fa3e9f 1214 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1215 }
1216
0fe1e009
TH		 1217 svm->asid_generation = sd->asid_generation;
1218 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1219}
1220
c76de350 1221static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1222{
42dbaa5a 1223 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1224
1225 switch (dr) {
1226 case 0 ... 3:
c76de350 1227 *dest = vcpu->arch.db[dr];
42dbaa5a 1228 break;
c76de350
JK		 1229 case 4:
1230 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1231 return EMULATE_FAIL; /* will re-inject UD */
1232 /* fall through */
42dbaa5a
JK		 1233 case 6:
1234 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1235 *dest = vcpu->arch.dr6;
42dbaa5a 1236 else
c76de350 1237 *dest = svm->vmcb->save.dr6;
42dbaa5a 1238 break;
c76de350
JK		 1239 case 5:
1240 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1241 return EMULATE_FAIL; /* will re-inject UD */
1242 /* fall through */
42dbaa5a
JK		 1243 case 7:
1244 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1245 *dest = vcpu->arch.dr7;
42dbaa5a 1246 else
c76de350 1247 *dest = svm->vmcb->save.dr7;
42dbaa5a 1248 break;
42dbaa5a
JK		 1249 }
1250
c76de350 1251 return EMULATE_DONE;
6aa8b732
AK		 1252}
1253
c76de350 1254static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1255{
a2fa3e9f
GH		 1256 struct vcpu_svm *svm = to_svm(vcpu);
1257
6aa8b732
AK		 1258 switch (dr) {
1259 case 0 ... 3:
42dbaa5a
JK		 1260 vcpu->arch.db[dr] = value;
1261 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1262 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1263 break;
1264 case 4:
1265 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1266 return EMULATE_FAIL; /* will re-inject UD */
1267 /* fall through */
42dbaa5a 1268 case 6:
42dbaa5a 1269 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1270 break;
1271 case 5:
1272 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1273 return EMULATE_FAIL; /* will re-inject UD */
1274 /* fall through */
42dbaa5a 1275 case 7:
42dbaa5a
JK		 1276 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1277 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1278 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1279 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1280 }
c76de350 1281 break;
6aa8b732 1282 }
c76de350
JK		 1283
1284 return EMULATE_DONE;
6aa8b732
AK		 1285}
1286
851ba692 1287static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1288{
6aa8b732
AK		 1289 u64 fault_address;
1290 u32 error_code;
6aa8b732 1291
a2fa3e9f
GH		 1292 fault_address = svm->vmcb->control.exit_info_2;
1293 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1294
229456fc 1295 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1296 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1297 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1298 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1299}
1300
851ba692 1301static int db_interception(struct vcpu_svm *svm)
d0bfb940 1302{
851ba692
AK		 1303 struct kvm_run *kvm_run = svm->vcpu.run;
1304
d0bfb940 1305 if (!(svm->vcpu.guest_debug &
44c11430 1306 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1307 !svm->nmi_singlestep) {
d0bfb940
JK		 1308 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1309 return 1;
1310 }
44c11430 1311
6be7d306
JK		 1312 if (svm->nmi_singlestep) {
1313 svm->nmi_singlestep = false;
44c11430
GN		 1314 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1315 svm->vmcb->save.rflags &=
1316 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1317 update_db_intercept(&svm->vcpu);
1318 }
1319
1320 if (svm->vcpu.guest_debug &
e0231715 1321 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1322 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1323 kvm_run->debug.arch.pc =
1324 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1325 kvm_run->debug.arch.exception = DB_VECTOR;
1326 return 0;
1327 }
1328
1329 return 1;
d0bfb940
JK		 1330}
1331
851ba692 1332static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1333{
851ba692
AK		 1334 struct kvm_run *kvm_run = svm->vcpu.run;
1335
d0bfb940
JK		 1336 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1337 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1338 kvm_run->debug.arch.exception = BP_VECTOR;
1339 return 0;
1340}
1341
851ba692 1342static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1343{
1344 int er;
1345
851ba692 1346 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1347 if (er != EMULATE_DONE)
7ee5d940 1348 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1349 return 1;
1350}
1351
6b52d186 1352static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1353{
6b52d186 1354 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1355 u32 excp;
1356
1357 if (is_nested(svm)) {
1358 u32 h_excp, n_excp;
1359
1360 h_excp = svm->nested.hsave->control.intercept_exceptions;
1361 n_excp = svm->nested.intercept_exceptions;
1362 h_excp &= ~(1 << NM_VECTOR);
1363 excp = h_excp | n_excp;
1364 } else {
1365 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1366 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1367 }
1368
1369 svm->vmcb->control.intercept_exceptions = excp;
1370
e756fc62 1371 svm->vcpu.fpu_active = 1;
d225157b 1372 update_cr0_intercept(svm);
6b52d186 1373}
a2fa3e9f 1374
6b52d186
AK		 1375static int nm_interception(struct vcpu_svm *svm)
1376{
1377 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1378 return 1;
7807fa6c
AL		 1379}
1380
851ba692 1381static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1382{
1383 /*
1384 * On an #MC intercept the MCE handler is not called automatically in
1385 * the host. So do it by hand here.
1386 */
1387 asm volatile (
1388 "int $0x12\n");
1389 /* not sure if we ever come back to this point */
1390
1391 return 1;
1392}
1393
851ba692 1394static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1395{
851ba692
AK		 1396 struct kvm_run *kvm_run = svm->vcpu.run;
1397
46fe4ddd
JR		 1398 /*
1399 * VMCB is undefined after a SHUTDOWN intercept
1400 * so reinitialize it.
1401 */
a2fa3e9f 1402 clear_page(svm->vmcb);
e6101a96 1403 init_vmcb(svm);
46fe4ddd
JR		 1404
1405 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1406 return 0;
1407}
1408
851ba692 1409static int io_interception(struct vcpu_svm *svm)
6aa8b732 1410{
d77c26fc 1411 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1412 int size, in, string;
039576c0 1413 unsigned port;
6aa8b732 1414
e756fc62 1415 ++svm->vcpu.stat.io_exits;
6aa8b732 1416
a2fa3e9f 1417 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1418
e70669ab
LV		 1419 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1420
1421 if (string) {
3427318f 1422 if (emulate_instruction(&svm->vcpu,
851ba692 1423 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1424 return 0;
1425 return 1;
1426 }
1427
039576c0
AK		 1428 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1429 port = io_info >> 16;
1430 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1431
e93f36bc 1432 skip_emulated_instruction(&svm->vcpu);
851ba692 1433 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1434}
1435
851ba692 1436static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1437{
1438 return 1;
1439}
1440
851ba692 1441static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1442{
1443 ++svm->vcpu.stat.irq_exits;
1444 return 1;
1445}
1446
851ba692 1447static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1448{
1449 return 1;
1450}
1451
851ba692 1452static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1453{
5fdbf976 1454 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1455 skip_emulated_instruction(&svm->vcpu);
1456 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1457}
1458
851ba692 1459static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1460{
5fdbf976 1461 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1462 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1463 kvm_emulate_hypercall(&svm->vcpu);
1464 return 1;
02e235bc
AK		 1465}
1466
c0725420
AG		 1467static int nested_svm_check_permissions(struct vcpu_svm *svm)
1468{
f6801dff 1469 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1470 || !is_paging(&svm->vcpu)) {
1471 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1472 return 1;
1473 }
1474
1475 if (svm->vmcb->save.cpl) {
1476 kvm_inject_gp(&svm->vcpu, 0);
1477 return 1;
1478 }
1479
1480 return 0;
1481}
1482
cf74a78b
AG		 1483static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1484 bool has_error_code, u32 error_code)
1485{
b8e88bc8
JR		 1486 int vmexit;
1487
0295ad7d
JR		 1488 if (!is_nested(svm))
1489 return 0;
cf74a78b 1490
0295ad7d
JR		 1491 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1492 svm->vmcb->control.exit_code_hi = 0;
1493 svm->vmcb->control.exit_info_1 = error_code;
1494 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1495
b8e88bc8
JR		 1496 vmexit = nested_svm_intercept(svm);
1497 if (vmexit == NESTED_EXIT_DONE)
1498 svm->nested.exit_required = true;
1499
1500 return vmexit;
cf74a78b
AG		 1501}
1502
8fe54654
JR		 1503/* This function returns true if it is save to enable the irq window */
1504static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1505{
26666957 1506 if (!is_nested(svm))
8fe54654 1507 return true;
cf74a78b 1508
26666957 1509 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1510 return true;
cf74a78b 1511
26666957 1512 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1513 return false;
cf74a78b 1514
197717d5
JR		 1515 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1516 svm->vmcb->control.exit_info_1 = 0;
1517 svm->vmcb->control.exit_info_2 = 0;
26666957 1518
cd3ff653
JR		 1519 if (svm->nested.intercept & 1ULL) {
1520 /*
1521 * The #vmexit can't be emulated here directly because this
1522 * code path runs with irqs and preemtion disabled. A
1523 * #vmexit emulation might sleep. Only signal request for
1524 * the #vmexit here.
1525 */
1526 svm->nested.exit_required = true;
236649de 1527 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1528 return false;
cf74a78b
AG		 1529 }
1530
8fe54654 1531 return true;
cf74a78b
AG		 1532}
1533
887f500c
JR		 1534/* This function returns true if it is save to enable the nmi window */
1535static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1536{
1537 if (!is_nested(svm))
1538 return true;
1539
1540 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1541 return true;
1542
1543 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1544 svm->nested.exit_required = true;
1545
1546 return false;
1547}
1548
7597f129 1549static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1550{
1551 struct page *page;
1552
6c3bd3d7
JR		 1553 might_sleep();
1554
34f80cfa 1555 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1556 if (is_error_page(page))
1557 goto error;
1558
7597f129
JR		 1559 *_page = page;
1560
1561 return kmap(page);
34f80cfa
JR		 1562
1563error:
1564 kvm_release_page_clean(page);
1565 kvm_inject_gp(&svm->vcpu, 0);
1566
1567 return NULL;
1568}
1569
7597f129 1570static void nested_svm_unmap(struct page *page)
34f80cfa 1571{
7597f129 1572 kunmap(page);
34f80cfa
JR		 1573 kvm_release_page_dirty(page);
1574}
1575
d2477826 1576static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1577{
4c2161ae 1578 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa 1579 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3d62d9aa 1580 u32 t0, t1;
d2477826 1581 int ret;
4c7da8cb 1582 u8 val;
4c2161ae 1583
3d62d9aa 1584 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1585 return NESTED_EXIT_HOST;
3d62d9aa 1586
4c2161ae
JR		 1587 switch (msr) {
1588 case 0 ... 0x1fff:
1589 t0 = (msr * 2) % 8;
1590 t1 = msr / 8;
1591 break;
1592 case 0xc0000000 ... 0xc0001fff:
1593 t0 = (8192 + msr - 0xc0000000) * 2;
1594 t1 = (t0 / 8);
1595 t0 %= 8;
1596 break;
1597 case 0xc0010000 ... 0xc0011fff:
1598 t0 = (16384 + msr - 0xc0010000) * 2;
1599 t1 = (t0 / 8);
1600 t0 %= 8;
1601 break;
1602 default:
d2477826 1603 ret = NESTED_EXIT_DONE;
3d62d9aa 1604 goto out;
4c2161ae 1605 }
4c2161ae 1606
4c7da8cb 1607 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
d2477826 1608 ret = val & ((1 << param) << t0) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3d62d9aa
JR		 1609
1610out:
3d62d9aa 1611 return ret;
4c2161ae
JR		 1612}
1613
410e4d57 1614static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1615{
cf74a78b 1616 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1617
410e4d57
JR		 1618 switch (exit_code) {
1619 case SVM_EXIT_INTR:
1620 case SVM_EXIT_NMI:
1621 return NESTED_EXIT_HOST;
410e4d57 1622 case SVM_EXIT_NPF:
e0231715 1623 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1624 if (npt_enabled)
1625 return NESTED_EXIT_HOST;
1626 break;
410e4d57 1627 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1628 /* When we're shadowing, trap PFs */
410e4d57
JR		 1629 if (!npt_enabled)
1630 return NESTED_EXIT_HOST;
1631 break;
66a562f7
JR		 1632 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1633 nm_interception(svm);
1634 break;
410e4d57
JR		 1635 default:
1636 break;
cf74a78b
AG		 1637 }
1638
410e4d57
JR		 1639 return NESTED_EXIT_CONTINUE;
1640}
1641
1642/*
1643 * If this function returns true, this #vmexit was already handled
1644 */
b8e88bc8 1645static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1646{
1647 u32 exit_code = svm->vmcb->control.exit_code;
1648 int vmexit = NESTED_EXIT_HOST;
1649
cf74a78b 1650 switch (exit_code) {
9c4e40b9 1651 case SVM_EXIT_MSR:
3d62d9aa 1652 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1653 break;
cf74a78b
AG		 1654 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1655 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1656 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1657 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1658 break;
1659 }
1660 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1661 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1662 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1663 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1664 break;
1665 }
1666 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1667 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1668 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1669 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1670 break;
1671 }
1672 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1673 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1674 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1675 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1676 break;
1677 }
1678 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1679 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1680 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1681 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1682 break;
1683 }
1684 default: {
1685 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1686 if (svm->nested.intercept & exit_bits)
410e4d57 1687 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1688 }
1689 }
1690
b8e88bc8
JR		 1691 return vmexit;
1692}
1693
1694static int nested_svm_exit_handled(struct vcpu_svm *svm)
1695{
1696 int vmexit;
1697
1698 vmexit = nested_svm_intercept(svm);
1699
1700 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1701 nested_svm_vmexit(svm);
9c4e40b9
JR		 1702
1703 return vmexit;
cf74a78b
AG		 1704}
1705
0460a979
JR		 1706static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1707{
1708 struct vmcb_control_area *dst = &dst_vmcb->control;
1709 struct vmcb_control_area *from = &from_vmcb->control;
1710
1711 dst->intercept_cr_read = from->intercept_cr_read;
1712 dst->intercept_cr_write = from->intercept_cr_write;
1713 dst->intercept_dr_read = from->intercept_dr_read;
1714 dst->intercept_dr_write = from->intercept_dr_write;
1715 dst->intercept_exceptions = from->intercept_exceptions;
1716 dst->intercept = from->intercept;
1717 dst->iopm_base_pa = from->iopm_base_pa;
1718 dst->msrpm_base_pa = from->msrpm_base_pa;
1719 dst->tsc_offset = from->tsc_offset;
1720 dst->asid = from->asid;
1721 dst->tlb_ctl = from->tlb_ctl;
1722 dst->int_ctl = from->int_ctl;
1723 dst->int_vector = from->int_vector;
1724 dst->int_state = from->int_state;
1725 dst->exit_code = from->exit_code;
1726 dst->exit_code_hi = from->exit_code_hi;
1727 dst->exit_info_1 = from->exit_info_1;
1728 dst->exit_info_2 = from->exit_info_2;
1729 dst->exit_int_info = from->exit_int_info;
1730 dst->exit_int_info_err = from->exit_int_info_err;
1731 dst->nested_ctl = from->nested_ctl;
1732 dst->event_inj = from->event_inj;
1733 dst->event_inj_err = from->event_inj_err;
1734 dst->nested_cr3 = from->nested_cr3;
1735 dst->lbr_ctl = from->lbr_ctl;
1736}
1737
34f80cfa 1738static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1739{
34f80cfa 1740 struct vmcb *nested_vmcb;
e6aa9abd 1741 struct vmcb *hsave = svm->nested.hsave;
33740e40 1742 struct vmcb *vmcb = svm->vmcb;
7597f129 1743 struct page *page;
cf74a78b 1744
17897f36
JR		 1745 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1746 vmcb->control.exit_info_1,
1747 vmcb->control.exit_info_2,
1748 vmcb->control.exit_int_info,
1749 vmcb->control.exit_int_info_err);
1750
7597f129 1751 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1752 if (!nested_vmcb)
1753 return 1;
1754
06fc7772
JR		 1755 /* Exit nested SVM mode */
1756 svm->nested.vmcb = 0;
1757
cf74a78b 1758 /* Give the current vmcb to the guest */
33740e40
JR		 1759 disable_gif(svm);
1760
1761 nested_vmcb->save.es = vmcb->save.es;
1762 nested_vmcb->save.cs = vmcb->save.cs;
1763 nested_vmcb->save.ss = vmcb->save.ss;
1764 nested_vmcb->save.ds = vmcb->save.ds;
1765 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1766 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1767 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1768 if (npt_enabled)
1769 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1770 else
1771 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1772 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1773 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1774 nested_vmcb->save.rflags = vmcb->save.rflags;
1775 nested_vmcb->save.rip = vmcb->save.rip;
1776 nested_vmcb->save.rsp = vmcb->save.rsp;
1777 nested_vmcb->save.rax = vmcb->save.rax;
1778 nested_vmcb->save.dr7 = vmcb->save.dr7;
1779 nested_vmcb->save.dr6 = vmcb->save.dr6;
1780 nested_vmcb->save.cpl = vmcb->save.cpl;
1781
1782 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1783 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1784 nested_vmcb->control.int_state = vmcb->control.int_state;
1785 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1786 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1787 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1788 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1789 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1790 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1791
1792 /*
1793 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1794 * to make sure that we do not lose injected events. So check event_inj
1795 * here and copy it to exit_int_info if it is valid.
1796 * Exit_int_info and event_inj can't be both valid because the case
1797 * below only happens on a VMRUN instruction intercept which has
1798 * no valid exit_int_info set.
1799 */
1800 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1801 struct vmcb_control_area *nc = &nested_vmcb->control;
1802
1803 nc->exit_int_info = vmcb->control.event_inj;
1804 nc->exit_int_info_err = vmcb->control.event_inj_err;
1805 }
1806
33740e40
JR		 1807 nested_vmcb->control.tlb_ctl = 0;
1808 nested_vmcb->control.event_inj = 0;
1809 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1810
1811 /* We always set V_INTR_MASKING and remember the old value in hflags */
1812 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1813 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1814
cf74a78b 1815 /* Restore the original control entries */
0460a979 1816 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1817
219b65dc
AG		 1818 kvm_clear_exception_queue(&svm->vcpu);
1819 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1820
1821 /* Restore selected save entries */
1822 svm->vmcb->save.es = hsave->save.es;
1823 svm->vmcb->save.cs = hsave->save.cs;
1824 svm->vmcb->save.ss = hsave->save.ss;
1825 svm->vmcb->save.ds = hsave->save.ds;
1826 svm->vmcb->save.gdtr = hsave->save.gdtr;
1827 svm->vmcb->save.idtr = hsave->save.idtr;
1828 svm->vmcb->save.rflags = hsave->save.rflags;
1829 svm_set_efer(&svm->vcpu, hsave->save.efer);
1830 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1831 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1832 if (npt_enabled) {
1833 svm->vmcb->save.cr3 = hsave->save.cr3;
1834 svm->vcpu.arch.cr3 = hsave->save.cr3;
1835 } else {
1836 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1837 }
1838 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1839 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1840 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1841 svm->vmcb->save.dr7 = 0;
1842 svm->vmcb->save.cpl = 0;
1843 svm->vmcb->control.exit_int_info = 0;
1844
7597f129 1845 nested_svm_unmap(page);
cf74a78b
AG		 1846
1847 kvm_mmu_reset_context(&svm->vcpu);
1848 kvm_mmu_load(&svm->vcpu);
1849
1850 return 0;
1851}
3d6368ef 1852
9738b2c9 1853static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1854{
9738b2c9 1855 u32 *nested_msrpm;
7597f129 1856 struct page *page;
3d6368ef 1857 int i;
9738b2c9 1858
7597f129 1859 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
9738b2c9
JR		 1860 if (!nested_msrpm)
1861 return false;
1862
e0231715 1863 for (i = 0; i < PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1864 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1865
e6aa9abd 1866 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1867
7597f129 1868 nested_svm_unmap(page);
9738b2c9
JR		 1869
1870 return true;
3d6368ef
AG		 1871}
1872
9738b2c9 1873static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1874{
9738b2c9 1875 struct vmcb *nested_vmcb;
e6aa9abd 1876 struct vmcb *hsave = svm->nested.hsave;
defbba56 1877 struct vmcb *vmcb = svm->vmcb;
7597f129 1878 struct page *page;
06fc7772
JR		 1879 u64 vmcb_gpa;
1880
1881 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1882
7597f129 1883 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1884 if (!nested_vmcb)
1885 return false;
1886
ecf1405d 1887 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1888 nested_vmcb->save.rip,
1889 nested_vmcb->control.int_ctl,
1890 nested_vmcb->control.event_inj,
1891 nested_vmcb->control.nested_ctl);
1892
2e554e8d
JR		 1893 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1894 nested_vmcb->control.intercept_cr_write,
1895 nested_vmcb->control.intercept_exceptions,
1896 nested_vmcb->control.intercept);
1897
3d6368ef 1898 /* Clear internal status */
219b65dc
AG		 1899 kvm_clear_exception_queue(&svm->vcpu);
1900 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 1901
e0231715
JR		 1902 /*
1903 * Save the old vmcb, so we don't need to pick what we save, but can
1904 * restore everything when a VMEXIT occurs
1905 */
defbba56
JR		 1906 hsave->save.es = vmcb->save.es;
1907 hsave->save.cs = vmcb->save.cs;
1908 hsave->save.ss = vmcb->save.ss;
1909 hsave->save.ds = vmcb->save.ds;
1910 hsave->save.gdtr = vmcb->save.gdtr;
1911 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1912 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1913 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1914 hsave->save.cr4 = svm->vcpu.arch.cr4;
1915 hsave->save.rflags = vmcb->save.rflags;
1916 hsave->save.rip = svm->next_rip;
1917 hsave->save.rsp = vmcb->save.rsp;
1918 hsave->save.rax = vmcb->save.rax;
1919 if (npt_enabled)
1920 hsave->save.cr3 = vmcb->save.cr3;
1921 else
1922 hsave->save.cr3 = svm->vcpu.arch.cr3;
1923
0460a979 1924 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1925
1926 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1927 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1928 else
1929 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1930
1931 /* Load the nested guest state */
1932 svm->vmcb->save.es = nested_vmcb->save.es;
1933 svm->vmcb->save.cs = nested_vmcb->save.cs;
1934 svm->vmcb->save.ss = nested_vmcb->save.ss;
1935 svm->vmcb->save.ds = nested_vmcb->save.ds;
1936 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1937 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1938 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1939 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1940 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1941 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1942 if (npt_enabled) {
1943 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1944 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 1945 } else
3d6368ef 1946 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 1947
1948 /* Guest paging mode is active - reset mmu */
1949 kvm_mmu_reset_context(&svm->vcpu);
1950
defbba56 1951 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1952 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1953 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1954 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 1955
3d6368ef
AG		 1956 /* In case we don't even reach vcpu_run, the fields are not updated */
1957 svm->vmcb->save.rax = nested_vmcb->save.rax;
1958 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1959 svm->vmcb->save.rip = nested_vmcb->save.rip;
1960 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1961 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1962 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1963
e6aa9abd 1964 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1965
aad42c64
JR		 1966 /* cache intercepts */
1967 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1968 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1969 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1970 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1971 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1972 svm->nested.intercept = nested_vmcb->control.intercept;
1973
3d6368ef 1974 force_new_asid(&svm->vcpu);
3d6368ef 1975 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1976 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1977 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1978 else
1979 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1980
88ab24ad
JR		 1981 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1982 /* We only want the cr8 intercept bits of the guest */
1983 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1984 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1985 }
1986
e0231715
JR		 1987 /*
1988 * We don't want a nested guest to be more powerful than the guest, so
1989 * all intercepts are ORed
1990 */
88ab24ad
JR		 1991 svm->vmcb->control.intercept_cr_read |=
1992 nested_vmcb->control.intercept_cr_read;
1993 svm->vmcb->control.intercept_cr_write |=
1994 nested_vmcb->control.intercept_cr_write;
1995 svm->vmcb->control.intercept_dr_read |=
1996 nested_vmcb->control.intercept_dr_read;
1997 svm->vmcb->control.intercept_dr_write |=
1998 nested_vmcb->control.intercept_dr_write;
1999 svm->vmcb->control.intercept_exceptions |=
2000 nested_vmcb->control.intercept_exceptions;
2001
2002 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2003
2004 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2005 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2006 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2007 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2008 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2009 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2010
7597f129 2011 nested_svm_unmap(page);
9738b2c9 2012
06fc7772
JR		 2013 /* nested_vmcb is our indicator if nested SVM is activated */
2014 svm->nested.vmcb = vmcb_gpa;
2015
2af9194d 2016 enable_gif(svm);
3d6368ef 2017
9738b2c9 2018 return true;
3d6368ef
AG		 2019}
2020
9966bf68 2021static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2022{
2023 to_vmcb->save.fs = from_vmcb->save.fs;
2024 to_vmcb->save.gs = from_vmcb->save.gs;
2025 to_vmcb->save.tr = from_vmcb->save.tr;
2026 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2027 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2028 to_vmcb->save.star = from_vmcb->save.star;
2029 to_vmcb->save.lstar = from_vmcb->save.lstar;
2030 to_vmcb->save.cstar = from_vmcb->save.cstar;
2031 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2032 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2033 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2034 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2035}
2036
851ba692 2037static int vmload_interception(struct vcpu_svm *svm)
5542675b 2038{
9966bf68 2039 struct vmcb *nested_vmcb;
7597f129 2040 struct page *page;
9966bf68 2041
5542675b
AG		 2042 if (nested_svm_check_permissions(svm))
2043 return 1;
2044
2045 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2046 skip_emulated_instruction(&svm->vcpu);
2047
7597f129 2048 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2049 if (!nested_vmcb)
2050 return 1;
2051
2052 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2053 nested_svm_unmap(page);
5542675b
AG		 2054
2055 return 1;
2056}
2057
851ba692 2058static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2059{
9966bf68 2060 struct vmcb *nested_vmcb;
7597f129 2061 struct page *page;
9966bf68 2062
5542675b
AG		 2063 if (nested_svm_check_permissions(svm))
2064 return 1;
2065
2066 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2067 skip_emulated_instruction(&svm->vcpu);
2068
7597f129 2069 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2070 if (!nested_vmcb)
2071 return 1;
2072
2073 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2074 nested_svm_unmap(page);
5542675b
AG		 2075
2076 return 1;
2077}
2078
851ba692 2079static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2080{
3d6368ef
AG		 2081 if (nested_svm_check_permissions(svm))
2082 return 1;
2083
2084 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2085 skip_emulated_instruction(&svm->vcpu);
2086
9738b2c9 2087 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2088 return 1;
2089
9738b2c9 2090 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2091 goto failed;
2092
2093 return 1;
2094
2095failed:
2096
2097 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2098 svm->vmcb->control.exit_code_hi = 0;
2099 svm->vmcb->control.exit_info_1 = 0;
2100 svm->vmcb->control.exit_info_2 = 0;
2101
2102 nested_svm_vmexit(svm);
3d6368ef
AG		 2103
2104 return 1;
2105}
2106
851ba692 2107static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2108{
2109 if (nested_svm_check_permissions(svm))
2110 return 1;
2111
2112 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2113 skip_emulated_instruction(&svm->vcpu);
2114
2af9194d 2115 enable_gif(svm);
1371d904
AG		 2116
2117 return 1;
2118}
2119
851ba692 2120static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2121{
2122 if (nested_svm_check_permissions(svm))
2123 return 1;
2124
2125 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2126 skip_emulated_instruction(&svm->vcpu);
2127
2af9194d 2128 disable_gif(svm);
1371d904
AG		 2129
2130 /* After a CLGI no interrupts should come */
2131 svm_clear_vintr(svm);
2132 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2133
2134 return 1;
2135}
2136
851ba692 2137static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2138{
2139 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2140
ec1ff790
JR		 2141 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2142 vcpu->arch.regs[VCPU_REGS_RAX]);
2143
ff092385
AG		 2144 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2145 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2146
2147 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2148 skip_emulated_instruction(&svm->vcpu);
2149 return 1;
2150}
2151
532a46b9
JR		 2152static int skinit_interception(struct vcpu_svm *svm)
2153{
2154 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2155
2156 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2157 return 1;
2158}
2159
851ba692 2160static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2161{
7ee5d940 2162 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2163 return 1;
2164}
2165
851ba692 2166static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2167{
37817f29 2168 u16 tss_selector;
64a7ec06
GN		 2169 int reason;
2170 int int_type = svm->vmcb->control.exit_int_info &
2171 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2172 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2173 uint32_t type =
2174 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2175 uint32_t idt_v =
2176 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2177
2178 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2179
37817f29
IE		 2180 if (svm->vmcb->control.exit_info_2 &
2181 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2182 reason = TASK_SWITCH_IRET;
2183 else if (svm->vmcb->control.exit_info_2 &
2184 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2185 reason = TASK_SWITCH_JMP;
fe8e7f83 2186 else if (idt_v)
64a7ec06
GN		 2187 reason = TASK_SWITCH_GATE;
2188 else
2189 reason = TASK_SWITCH_CALL;
2190
fe8e7f83
GN		 2191 if (reason == TASK_SWITCH_GATE) {
2192 switch (type) {
2193 case SVM_EXITINTINFO_TYPE_NMI:
2194 svm->vcpu.arch.nmi_injected = false;
2195 break;
2196 case SVM_EXITINTINFO_TYPE_EXEPT:
2197 kvm_clear_exception_queue(&svm->vcpu);
2198 break;
2199 case SVM_EXITINTINFO_TYPE_INTR:
2200 kvm_clear_interrupt_queue(&svm->vcpu);
2201 break;
2202 default:
2203 break;
2204 }
2205 }
64a7ec06 2206
8317c298
GN		 2207 if (reason != TASK_SWITCH_GATE ||
2208 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2209 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2210 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2211 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2212
2213 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2214}
2215
851ba692 2216static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2217{
5fdbf976 2218 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2219 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2220 return 1;
6aa8b732
AK		 2221}
2222
851ba692 2223static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2224{
2225 ++svm->vcpu.stat.nmi_window_exits;
2226 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2227 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2228 return 1;
2229}
2230
851ba692 2231static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2232{
851ba692 2233 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2234 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2235 return 1;
2236}
2237
851ba692 2238static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2239{
851ba692 2240 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2241 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2242 return 1;
2243}
2244
851ba692 2245static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2246{
851ba692
AK		 2247 struct kvm_run *kvm_run = svm->vcpu.run;
2248
0a5fff19
GN		 2249 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2250 /* instruction emulation calls kvm_set_cr8() */
851ba692 2251 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2252 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2253 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2254 return 1;
95ba8273 2255 }
0a5fff19
GN		 2256 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2257 return 1;
1d075434
JR		 2258 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2259 return 0;
2260}
2261
6aa8b732
AK		 2262static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2263{
a2fa3e9f
GH		 2264 struct vcpu_svm *svm = to_svm(vcpu);
2265
6aa8b732 2266 switch (ecx) {
af24a4e4 2267 case MSR_IA32_TSC: {
20824f30 2268 u64 tsc_offset;
6aa8b732 2269
20824f30
JR		 2270 if (is_nested(svm))
2271 tsc_offset = svm->nested.hsave->control.tsc_offset;
2272 else
2273 tsc_offset = svm->vmcb->control.tsc_offset;
2274
2275 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2276 break;
2277 }
0e859cac 2278 case MSR_K6_STAR:
a2fa3e9f 2279 *data = svm->vmcb->save.star;
6aa8b732 2280 break;
0e859cac 2281#ifdef CONFIG_X86_64
6aa8b732 2282 case MSR_LSTAR:
a2fa3e9f 2283 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2284 break;
2285 case MSR_CSTAR:
a2fa3e9f 2286 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2287 break;
2288 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2289 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2290 break;
2291 case MSR_SYSCALL_MASK:
a2fa3e9f 2292 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2293 break;
2294#endif
2295 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2296 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2297 break;
2298 case MSR_IA32_SYSENTER_EIP:
017cb99e 2299 *data = svm->sysenter_eip;
6aa8b732
AK		 2300 break;
2301 case MSR_IA32_SYSENTER_ESP:
017cb99e 2302 *data = svm->sysenter_esp;
6aa8b732 2303 break;
e0231715
JR		 2304 /*
2305 * Nobody will change the following 5 values in the VMCB so we can
2306 * safely return them on rdmsr. They will always be 0 until LBRV is
2307 * implemented.
2308 */
a2938c80
JR		 2309 case MSR_IA32_DEBUGCTLMSR:
2310 *data = svm->vmcb->save.dbgctl;
2311 break;
2312 case MSR_IA32_LASTBRANCHFROMIP:
2313 *data = svm->vmcb->save.br_from;
2314 break;
2315 case MSR_IA32_LASTBRANCHTOIP:
2316 *data = svm->vmcb->save.br_to;
2317 break;
2318 case MSR_IA32_LASTINTFROMIP:
2319 *data = svm->vmcb->save.last_excp_from;
2320 break;
2321 case MSR_IA32_LASTINTTOIP:
2322 *data = svm->vmcb->save.last_excp_to;
2323 break;
b286d5d8 2324 case MSR_VM_HSAVE_PA:
e6aa9abd 2325 *data = svm->nested.hsave_msr;
b286d5d8 2326 break;
eb6f302e 2327 case MSR_VM_CR:
4a810181 2328 *data = svm->nested.vm_cr_msr;
eb6f302e 2329 break;
c8a73f18
AG		 2330 case MSR_IA32_UCODE_REV:
2331 *data = 0x01000065;
2332 break;
6aa8b732 2333 default:
3bab1f5d 2334 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2335 }
2336 return 0;
2337}
2338
851ba692 2339static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2340{
ad312c7c 2341 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2342 u64 data;
2343
59200273
AK		 2344 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2345 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2346 kvm_inject_gp(&svm->vcpu, 0);
59200273 2347 } else {
229456fc 2348 trace_kvm_msr_read(ecx, data);
af9ca2d7 2349
5fdbf976 2350 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2351 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2352 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2353 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2354 }
2355 return 1;
2356}
2357
4a810181
JR		 2358static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2359{
2360 struct vcpu_svm *svm = to_svm(vcpu);
2361 int svm_dis, chg_mask;
2362
2363 if (data & ~SVM_VM_CR_VALID_MASK)
2364 return 1;
2365
2366 chg_mask = SVM_VM_CR_VALID_MASK;
2367
2368 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2369 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2370
2371 svm->nested.vm_cr_msr &= ~chg_mask;
2372 svm->nested.vm_cr_msr |= (data & chg_mask);
2373
2374 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2375
2376 /* check for svm_disable while efer.svme is set */
2377 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2378 return 1;
2379
2380 return 0;
2381}
2382
6aa8b732
AK		 2383static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2384{
a2fa3e9f
GH		 2385 struct vcpu_svm *svm = to_svm(vcpu);
2386
6aa8b732 2387 switch (ecx) {
af24a4e4 2388 case MSR_IA32_TSC: {
20824f30
JR		 2389 u64 tsc_offset = data - native_read_tsc();
2390 u64 g_tsc_offset = 0;
2391
2392 if (is_nested(svm)) {
2393 g_tsc_offset = svm->vmcb->control.tsc_offset -
2394 svm->nested.hsave->control.tsc_offset;
2395 svm->nested.hsave->control.tsc_offset = tsc_offset;
2396 }
2397
2398 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2399
6aa8b732
AK		 2400 break;
2401 }
0e859cac 2402 case MSR_K6_STAR:
a2fa3e9f 2403 svm->vmcb->save.star = data;
6aa8b732 2404 break;
49b14f24 2405#ifdef CONFIG_X86_64
6aa8b732 2406 case MSR_LSTAR:
a2fa3e9f 2407 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2408 break;
2409 case MSR_CSTAR:
a2fa3e9f 2410 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2411 break;
2412 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2413 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2414 break;
2415 case MSR_SYSCALL_MASK:
a2fa3e9f 2416 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2417 break;
2418#endif
2419 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2420 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2421 break;
2422 case MSR_IA32_SYSENTER_EIP:
017cb99e 2423 svm->sysenter_eip = data;
a2fa3e9f 2424 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2425 break;
2426 case MSR_IA32_SYSENTER_ESP:
017cb99e 2427 svm->sysenter_esp = data;
a2fa3e9f 2428 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2429 break;
a2938c80 2430 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2431 if (!svm_has(SVM_FEATURE_LBRV)) {
2432 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2433 __func__, data);
24e09cbf
JR		 2434 break;
2435 }
2436 if (data & DEBUGCTL_RESERVED_BITS)
2437 return 1;
2438
2439 svm->vmcb->save.dbgctl = data;
2440 if (data & (1ULL<<0))
2441 svm_enable_lbrv(svm);
2442 else
2443 svm_disable_lbrv(svm);
a2938c80 2444 break;
b286d5d8 2445 case MSR_VM_HSAVE_PA:
e6aa9abd 2446 svm->nested.hsave_msr = data;
62b9abaa 2447 break;
3c5d0a44 2448 case MSR_VM_CR:
4a810181 2449 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2450 case MSR_VM_IGNNE:
3c5d0a44
AG		 2451 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2452 break;
6aa8b732 2453 default:
3bab1f5d 2454 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2455 }
2456 return 0;
2457}
2458
851ba692 2459static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2460{
ad312c7c 2461 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2462 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2463 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2464
af9ca2d7 2465
5fdbf976 2466 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2467 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2468 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2469 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2470 } else {
2471 trace_kvm_msr_write(ecx, data);
e756fc62 2472 skip_emulated_instruction(&svm->vcpu);
59200273 2473 }
6aa8b732
AK		 2474 return 1;
2475}
2476
851ba692 2477static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2478{
e756fc62 2479 if (svm->vmcb->control.exit_info_1)
851ba692 2480 return wrmsr_interception(svm);
6aa8b732 2481 else
851ba692 2482 return rdmsr_interception(svm);
6aa8b732
AK		 2483}
2484
851ba692 2485static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2486{
851ba692
AK		 2487 struct kvm_run *kvm_run = svm->vcpu.run;
2488
f0b85051 2489 svm_clear_vintr(svm);
85f455f7 2490 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2491 /*
2492 * If the user space waits to inject interrupts, exit as soon as
2493 * possible
2494 */
8061823a
GN		 2495 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2496 kvm_run->request_interrupt_window &&
2497 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2498 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2499 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2500 return 0;
2501 }
2502
2503 return 1;
2504}
2505
565d0998
ML		 2506static int pause_interception(struct vcpu_svm *svm)
2507{
2508 kvm_vcpu_on_spin(&(svm->vcpu));
2509 return 1;
2510}
2511
851ba692 2512static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2513 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2514 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2515 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2516 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2517 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2518 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2519 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2520 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2521 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2522 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2523 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2524 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2525 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2526 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2527 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2528 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2529 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2530 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2531 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2532 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2533 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2534 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2535 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2536 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2537 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2538 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2539 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2540 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2541 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2542 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2543 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2544 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2545 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2546 [SVM_EXIT_SMI] = nop_on_interception,
2547 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2548 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2549 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2550 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2551 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2552 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2553 [SVM_EXIT_HLT] = halt_interception,
a7052897 2554 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2555 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2556 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2557 [SVM_EXIT_MSR] = msr_interception,
2558 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2559 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2560 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2561 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2562 [SVM_EXIT_VMLOAD] = vmload_interception,
2563 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2564 [SVM_EXIT_STGI] = stgi_interception,
2565 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2566 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2567 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2568 [SVM_EXIT_MONITOR] = invalid_op_interception,
2569 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2570 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2571};
2572
851ba692 2573static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2574{
04d2cc77 2575 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2576 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2577 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2578
229456fc 2579 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2580
cd3ff653
JR		 2581 if (unlikely(svm->nested.exit_required)) {
2582 nested_svm_vmexit(svm);
2583 svm->nested.exit_required = false;
2584
2585 return 1;
2586 }
2587
cf74a78b 2588 if (is_nested(svm)) {
410e4d57
JR		 2589 int vmexit;
2590
d8cabddf
JR		 2591 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2592 svm->vmcb->control.exit_info_1,
2593 svm->vmcb->control.exit_info_2,
2594 svm->vmcb->control.exit_int_info,
2595 svm->vmcb->control.exit_int_info_err);
2596
410e4d57
JR		 2597 vmexit = nested_svm_exit_special(svm);
2598
2599 if (vmexit == NESTED_EXIT_CONTINUE)
2600 vmexit = nested_svm_exit_handled(svm);
2601
2602 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2603 return 1;
cf74a78b
AG		 2604 }
2605
a5c3832d
JR		 2606 svm_complete_interrupts(svm);
2607
888f9f3e 2608 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2609 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2610 if (npt_enabled)
709ddebf 2611 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2612
2613 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2614 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2615 kvm_run->fail_entry.hardware_entry_failure_reason
2616 = svm->vmcb->control.exit_code;
2617 return 0;
2618 }
2619
a2fa3e9f 2620 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2621 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2622 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2623 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2624 "exit_code 0x%x\n",
b8688d51 2625 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2626 exit_code);
2627
9d8f549d 2628 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2629 || !svm_exit_handlers[exit_code]) {
6aa8b732 2630 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2631 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2632 return 0;
2633 }
2634
851ba692 2635 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2636}
2637
2638static void reload_tss(struct kvm_vcpu *vcpu)
2639{
2640 int cpu = raw_smp_processor_id();
2641
0fe1e009
TH		 2642 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2643 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2644 load_TR_desc();
2645}
2646
e756fc62 2647static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2648{
2649 int cpu = raw_smp_processor_id();
2650
0fe1e009 2651 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2652
a2fa3e9f 2653 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2654 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2655 if (svm->asid_generation != sd->asid_generation)
2656 new_asid(svm, sd);
6aa8b732
AK		 2657}
2658
95ba8273
GN		 2659static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2660{
2661 struct vcpu_svm *svm = to_svm(vcpu);
2662
2663 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2664 vcpu->arch.hflags |= HF_NMI_MASK;
2665 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2666 ++vcpu->stat.nmi_injections;
2667}
6aa8b732 2668
85f455f7 2669static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2670{
2671 struct vmcb_control_area *control;
2672
229456fc 2673 trace_kvm_inj_virq(irq);
af9ca2d7 2674
fa89a817 2675 ++svm->vcpu.stat.irq_injections;
e756fc62 2676 control = &svm->vmcb->control;
85f455f7 2677 control->int_vector = irq;
6aa8b732
AK		 2678 control->int_ctl &= ~V_INTR_PRIO_MASK;
2679 control->int_ctl |= V_IRQ_MASK |
2680 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2681}
2682
66fd3f7f 2683static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2684{
2685 struct vcpu_svm *svm = to_svm(vcpu);
2686
2af9194d 2687 BUG_ON(!(gif_set(svm)));
cf74a78b 2688
219b65dc
AG		 2689 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2690 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2691}
2692
95ba8273 2693static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2694{
2695 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2696
88ab24ad
JR		 2697 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2698 return;
2699
95ba8273 2700 if (irr == -1)
aaacfc9a
JR		 2701 return;
2702
95ba8273
GN		 2703 if (tpr >= irr)
2704 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2705}
aaacfc9a 2706
95ba8273
GN		 2707static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2708{
2709 struct vcpu_svm *svm = to_svm(vcpu);
2710 struct vmcb *vmcb = svm->vmcb;
2711 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2712 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2713}
2714
3cfc3092
JK		 2715static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2716{
2717 struct vcpu_svm *svm = to_svm(vcpu);
2718
2719 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2720}
2721
2722static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2723{
2724 struct vcpu_svm *svm = to_svm(vcpu);
2725
2726 if (masked) {
2727 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2728 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2729 } else {
2730 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2731 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2732 }
2733}
2734
78646121
GN		 2735static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2736{
2737 struct vcpu_svm *svm = to_svm(vcpu);
2738 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2739 int ret;
2740
2741 if (!gif_set(svm) ||
2742 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2743 return 0;
2744
2745 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2746
2747 if (is_nested(svm))
2748 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2749
2750 return ret;
78646121
GN		 2751}
2752
9222be18 2753static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2754{
219b65dc 2755 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2756
e0231715
JR		 2757 /*
2758 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2759 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2760 * get that intercept, this function will be called again though and
2761 * we'll get the vintr intercept.
2762 */
8fe54654 2763 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2764 svm_set_vintr(svm);
2765 svm_inject_irq(svm, 0x0);
2766 }
85f455f7
ED		 2767}
2768
95ba8273 2769static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2770{
04d2cc77 2771 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2772
44c11430
GN		 2773 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2774 == HF_NMI_MASK)
2775 return; /* IRET will cause a vm exit */
2776
e0231715
JR		 2777 /*
2778 * Something prevents NMI from been injected. Single step over possible
2779 * problem (IRET or exception injection or interrupt shadow)
2780 */
887f500c
JR		 2781 if (gif_set(svm) && nested_svm_nmi(svm)) {
2782 svm->nmi_singlestep = true;
2783 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2784 update_db_intercept(vcpu);
2785 }
c1150d8c
DL		 2786}
2787
cbc94022
IE		 2788static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2789{
2790 return 0;
2791}
2792
d9e368d6
AK		 2793static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2794{
2795 force_new_asid(vcpu);
2796}
2797
04d2cc77
AK		 2798static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2799{
2800}
2801
d7bf8221
JR		 2802static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2803{
2804 struct vcpu_svm *svm = to_svm(vcpu);
2805
88ab24ad
JR		 2806 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2807 return;
2808
d7bf8221
JR		 2809 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2810 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2811 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2812 }
2813}
2814
649d6864
JR		 2815static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2816{
2817 struct vcpu_svm *svm = to_svm(vcpu);
2818 u64 cr8;
2819
88ab24ad
JR		 2820 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2821 return;
2822
649d6864
JR		 2823 cr8 = kvm_get_cr8(vcpu);
2824 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2825 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2826}
2827
9222be18
GN		 2828static void svm_complete_interrupts(struct vcpu_svm *svm)
2829{
2830 u8 vector;
2831 int type;
2832 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2833 unsigned int3_injected = svm->int3_injected;
2834
2835 svm->int3_injected = 0;
9222be18 2836
44c11430
GN		 2837 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2838 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2839
9222be18
GN		 2840 svm->vcpu.arch.nmi_injected = false;
2841 kvm_clear_exception_queue(&svm->vcpu);
2842 kvm_clear_interrupt_queue(&svm->vcpu);
2843
2844 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2845 return;
2846
2847 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2848 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2849
2850 switch (type) {
2851 case SVM_EXITINTINFO_TYPE_NMI:
2852 svm->vcpu.arch.nmi_injected = true;
2853 break;
2854 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2855 if (is_nested(svm))
2856 break;
66b7138f
JK		 2857 /*
2858 * In case of software exceptions, do not reinject the vector,
2859 * but re-execute the instruction instead. Rewind RIP first
2860 * if we emulated INT3 before.
2861 */
2862 if (kvm_exception_is_soft(vector)) {
2863 if (vector == BP_VECTOR && int3_injected &&
2864 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2865 kvm_rip_write(&svm->vcpu,
2866 kvm_rip_read(&svm->vcpu) -
2867 int3_injected);
9222be18 2868 break;
66b7138f 2869 }
9222be18
GN		 2870 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2871 u32 err = svm->vmcb->control.exit_int_info_err;
2872 kvm_queue_exception_e(&svm->vcpu, vector, err);
2873
2874 } else
2875 kvm_queue_exception(&svm->vcpu, vector);
2876 break;
2877 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2878 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2879 break;
2880 default:
2881 break;
2882 }
2883}
2884
80e31d4f
AK		 2885#ifdef CONFIG_X86_64
2886#define R "r"
2887#else
2888#define R "e"
2889#endif
2890
851ba692 2891static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2892{
a2fa3e9f 2893 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2894 u16 fs_selector;
2895 u16 gs_selector;
2896 u16 ldt_selector;
d9e368d6 2897
cd3ff653
JR		 2898 /*
2899 * A vmexit emulation is required before the vcpu can be executed
2900 * again.
2901 */
2902 if (unlikely(svm->nested.exit_required))
2903 return;
2904
5fdbf976
MT		 2905 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2906 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2907 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2908
e756fc62 2909 pre_svm_run(svm);
6aa8b732 2910
649d6864
JR		 2911 sync_lapic_to_cr8(vcpu);
2912
6aa8b732 2913 save_host_msrs(vcpu);
d6e88aec
AK		 2914 fs_selector = kvm_read_fs();
2915 gs_selector = kvm_read_gs();
2916 ldt_selector = kvm_read_ldt();
cda0ffdd 2917 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2918 /* required for live migration with NPT */
2919 if (npt_enabled)
2920 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2921
04d2cc77
AK		 2922 clgi();
2923
2924 local_irq_enable();
36241b8c 2925
6aa8b732 2926 asm volatile (
80e31d4f
AK		 2927 "push %%"R"bp; \n\t"
2928 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2929 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2930 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2931 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2932 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2933 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2934#ifdef CONFIG_X86_64
fb3f0f51
RR		 2935 "mov %c[r8](%[svm]), %%r8 \n\t"
2936 "mov %c[r9](%[svm]), %%r9 \n\t"
2937 "mov %c[r10](%[svm]), %%r10 \n\t"
2938 "mov %c[r11](%[svm]), %%r11 \n\t"
2939 "mov %c[r12](%[svm]), %%r12 \n\t"
2940 "mov %c[r13](%[svm]), %%r13 \n\t"
2941 "mov %c[r14](%[svm]), %%r14 \n\t"
2942 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2943#endif
2944
6aa8b732 2945 /* Enter guest mode */
80e31d4f
AK		 2946 "push %%"R"ax \n\t"
2947 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2948 __ex(SVM_VMLOAD) "\n\t"
2949 __ex(SVM_VMRUN) "\n\t"
2950 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2951 "pop %%"R"ax \n\t"
6aa8b732
AK		 2952
2953 /* Save guest registers, load host registers */
80e31d4f
AK		 2954 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2955 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2956 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2957 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2958 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2959 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2960#ifdef CONFIG_X86_64
fb3f0f51
RR		 2961 "mov %%r8, %c[r8](%[svm]) \n\t"
2962 "mov %%r9, %c[r9](%[svm]) \n\t"
2963 "mov %%r10, %c[r10](%[svm]) \n\t"
2964 "mov %%r11, %c[r11](%[svm]) \n\t"
2965 "mov %%r12, %c[r12](%[svm]) \n\t"
2966 "mov %%r13, %c[r13](%[svm]) \n\t"
2967 "mov %%r14, %c[r14](%[svm]) \n\t"
2968 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2969#endif
80e31d4f 2970 "pop %%"R"bp"
6aa8b732 2971 :
fb3f0f51 2972 : [svm]"a"(svm),
6aa8b732 2973 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2974 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2975 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2976 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2977 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2978 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2979 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2980#ifdef CONFIG_X86_64
ad312c7c
ZX		 2981 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2982 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2983 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2984 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2985 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2986 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2987 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2988 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2989#endif
54a08c04 2990 : "cc", "memory"
80e31d4f 2991 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2992#ifdef CONFIG_X86_64
54a08c04
LV		 2993 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2994#endif
2995 );
6aa8b732 2996
ad312c7c 2997 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2998 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2999 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3000 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3001
d6e88aec
AK		 3002 kvm_load_fs(fs_selector);
3003 kvm_load_gs(gs_selector);
3004 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3005 load_host_msrs(vcpu);
3006
3007 reload_tss(vcpu);
3008
56ba47dd
AK		 3009 local_irq_disable();
3010
3011 stgi();
3012
d7bf8221
JR		 3013 sync_cr8_to_lapic(vcpu);
3014
a2fa3e9f 3015 svm->next_rip = 0;
9222be18 3016
6de4f3ad
AK		 3017 if (npt_enabled) {
3018 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3019 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3020 }
6aa8b732
AK		 3021}
3022
80e31d4f
AK		 3023#undef R
3024
6aa8b732
AK		 3025static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3026{
a2fa3e9f
GH		 3027 struct vcpu_svm *svm = to_svm(vcpu);
3028
709ddebf
JR		 3029 if (npt_enabled) {
3030 svm->vmcb->control.nested_cr3 = root;
3031 force_new_asid(vcpu);
3032 return;
3033 }
3034
a2fa3e9f 3035 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3036 force_new_asid(vcpu);
3037}
3038
6aa8b732
AK		 3039static int is_disabled(void)
3040{
6031a61c
JR		 3041 u64 vm_cr;
3042
3043 rdmsrl(MSR_VM_CR, vm_cr);
3044 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3045 return 1;
3046
6aa8b732
AK		 3047 return 0;
3048}
3049
102d8325
IM		 3050static void
3051svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3052{
3053 /*
3054 * Patch in the VMMCALL instruction:
3055 */
3056 hypercall[0] = 0x0f;
3057 hypercall[1] = 0x01;
3058 hypercall[2] = 0xd9;
102d8325
IM		 3059}
3060
002c7f7c
YS		 3061static void svm_check_processor_compat(void *rtn)
3062{
3063 *(int *)rtn = 0;
3064}
3065
774ead3a
AK		 3066static bool svm_cpu_has_accelerated_tpr(void)
3067{
3068 return false;
3069}
3070
67253af5
SY		 3071static int get_npt_level(void)
3072{
3073#ifdef CONFIG_X86_64
3074 return PT64_ROOT_LEVEL;
3075#else
3076 return PT32E_ROOT_LEVEL;
3077#endif
3078}
3079
4b12f0de 3080static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3081{
3082 return 0;
3083}
3084
0e851880
SY		 3085static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3086{
3087}
3088
229456fc 3089static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3090 { SVM_EXIT_READ_CR0, "read_cr0" },
3091 { SVM_EXIT_READ_CR3, "read_cr3" },
3092 { SVM_EXIT_READ_CR4, "read_cr4" },
3093 { SVM_EXIT_READ_CR8, "read_cr8" },
3094 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3095 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3096 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3097 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3098 { SVM_EXIT_READ_DR0, "read_dr0" },
3099 { SVM_EXIT_READ_DR1, "read_dr1" },
3100 { SVM_EXIT_READ_DR2, "read_dr2" },
3101 { SVM_EXIT_READ_DR3, "read_dr3" },
3102 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3103 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3104 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3105 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3106 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3107 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3108 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3109 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3110 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3111 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3112 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3113 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3114 { SVM_EXIT_INTR, "interrupt" },
3115 { SVM_EXIT_NMI, "nmi" },
3116 { SVM_EXIT_SMI, "smi" },
3117 { SVM_EXIT_INIT, "init" },
3118 { SVM_EXIT_VINTR, "vintr" },
3119 { SVM_EXIT_CPUID, "cpuid" },
3120 { SVM_EXIT_INVD, "invd" },
3121 { SVM_EXIT_HLT, "hlt" },
3122 { SVM_EXIT_INVLPG, "invlpg" },
3123 { SVM_EXIT_INVLPGA, "invlpga" },
3124 { SVM_EXIT_IOIO, "io" },
3125 { SVM_EXIT_MSR, "msr" },
3126 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3127 { SVM_EXIT_SHUTDOWN, "shutdown" },
3128 { SVM_EXIT_VMRUN, "vmrun" },
3129 { SVM_EXIT_VMMCALL, "hypercall" },
3130 { SVM_EXIT_VMLOAD, "vmload" },
3131 { SVM_EXIT_VMSAVE, "vmsave" },
3132 { SVM_EXIT_STGI, "stgi" },
3133 { SVM_EXIT_CLGI, "clgi" },
3134 { SVM_EXIT_SKINIT, "skinit" },
3135 { SVM_EXIT_WBINVD, "wbinvd" },
3136 { SVM_EXIT_MONITOR, "monitor" },
3137 { SVM_EXIT_MWAIT, "mwait" },
3138 { SVM_EXIT_NPF, "npf" },
3139 { -1, NULL }
3140};
3141
17cc3935 3142static int svm_get_lpage_level(void)
344f414f 3143{
17cc3935 3144 return PT_PDPE_LEVEL;
344f414f
JR		 3145}
3146
4e47c7a6
SY		 3147static bool svm_rdtscp_supported(void)
3148{
3149 return false;
3150}
3151
02daab21
AK		 3152static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3153{
3154 struct vcpu_svm *svm = to_svm(vcpu);
3155
02daab21 3156 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3157 if (is_nested(svm))
3158 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3159 update_cr0_intercept(svm);
02daab21
AK		 3160}
3161
cbdd1bea 3162static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3163 .cpu_has_kvm_support = has_svm,
3164 .disabled_by_bios = is_disabled,
3165 .hardware_setup = svm_hardware_setup,
3166 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3167 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3168 .hardware_enable = svm_hardware_enable,
3169 .hardware_disable = svm_hardware_disable,
774ead3a 3170 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3171
3172 .vcpu_create = svm_create_vcpu,
3173 .vcpu_free = svm_free_vcpu,
04d2cc77 3174 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3175
04d2cc77 3176 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3177 .vcpu_load = svm_vcpu_load,
3178 .vcpu_put = svm_vcpu_put,
3179
3180 .set_guest_debug = svm_guest_debug,
3181 .get_msr = svm_get_msr,
3182 .set_msr = svm_set_msr,
3183 .get_segment_base = svm_get_segment_base,
3184 .get_segment = svm_get_segment,
3185 .set_segment = svm_set_segment,
2e4d2653 3186 .get_cpl = svm_get_cpl,
1747fb71 3187 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3188 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3189 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3190 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3191 .set_cr3 = svm_set_cr3,
3192 .set_cr4 = svm_set_cr4,
3193 .set_efer = svm_set_efer,
3194 .get_idt = svm_get_idt,
3195 .set_idt = svm_set_idt,
3196 .get_gdt = svm_get_gdt,
3197 .set_gdt = svm_set_gdt,
3198 .get_dr = svm_get_dr,
3199 .set_dr = svm_set_dr,
6de4f3ad 3200 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3201 .get_rflags = svm_get_rflags,
3202 .set_rflags = svm_set_rflags,
6b52d186 3203 .fpu_activate = svm_fpu_activate,
02daab21 3204 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3205
6aa8b732 3206 .tlb_flush = svm_flush_tlb,
6aa8b732 3207
6aa8b732 3208 .run = svm_vcpu_run,
04d2cc77 3209 .handle_exit = handle_exit,
6aa8b732 3210 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3211 .set_interrupt_shadow = svm_set_interrupt_shadow,
3212 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3213 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3214 .set_irq = svm_set_irq,
95ba8273 3215 .set_nmi = svm_inject_nmi,
298101da 3216 .queue_exception = svm_queue_exception,
78646121 3217 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3218 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3219 .get_nmi_mask = svm_get_nmi_mask,
3220 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3221 .enable_nmi_window = enable_nmi_window,
3222 .enable_irq_window = enable_irq_window,
3223 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3224
3225 .set_tss_addr = svm_set_tss_addr,
67253af5 3226 .get_tdp_level = get_npt_level,
4b12f0de 3227 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3228
3229 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3230 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3231
3232 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3233
3234 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3235};
3236
3237static int __init svm_init(void)
3238{
cb498ea2 3239 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3240 THIS_MODULE);
6aa8b732
AK		 3241}
3242
3243static void __exit svm_exit(void)
3244{
cb498ea2 3245 kvm_exit();
6aa8b732
AK		 3246}
3247
3248module_init(svm_init)
3249module_exit(svm_exit)
Linux kernel - Deliverables
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