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KVM: SVM: Initialize fpu_active in init_vmcb()
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
565d0998 49#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 50
410e4d57
JR		 51#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
24e09cbf
JR		 55#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
6c8166a7
AK		 57static const u32 host_save_user_msrs[] = {
58#ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61#endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63};
64
65#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67struct kvm_vcpu;
68
e6aa9abd
JR		 69struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
aad42c64 79
cd3ff653
JR		 80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
aad42c64
JR		 83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
e6aa9abd
JR		 91};
92
6c8166a7
AK		 93struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
6c8166a7
AK		 106
107 u32 *msrpm;
6c8166a7 108
e6aa9abd 109 struct nested_state nested;
6be7d306
JK		 110
111 bool nmi_singlestep;
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116static bool npt_enabled = true;
117#else
e3da3acd 118static bool npt_enabled = false;
709ddebf 119#endif
6c7dac72
JR		 120static int npt = 1;
121
122module_param(npt, int, S_IRUGO);
e3da3acd 123
4b6e4dca 124static int nested = 1;
236de055
AG		 125module_param(nested, int, S_IRUGO);
126
44874f84 127static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 128static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 129
410e4d57 130static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 131static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 132static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
a2fa3e9f
GH		 135static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136{
fb3f0f51 137 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 138}
139
3d6368ef
AG		 140static inline bool is_nested(struct vcpu_svm *svm)
141{
e6aa9abd 142 return svm->nested.vmcb;
3d6368ef
AG		 143}
144
2af9194d
JR		 145static inline void enable_gif(struct vcpu_svm *svm)
146{
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148}
149
150static inline void disable_gif(struct vcpu_svm *svm)
151{
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153}
154
155static inline bool gif_set(struct vcpu_svm *svm)
156{
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158}
159
4866d5e3 160static unsigned long iopm_base;
6aa8b732
AK		 161
162struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169} __attribute__((packed));
170
171struct svm_cpu_data {
172 int cpu;
173
5008fdf5
AK		 174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
6aa8b732
AK		 177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180};
181
182static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 183static uint32_t svm_features;
6aa8b732
AK		 184
185struct svm_init_data {
186 int cpu;
187 int r;
188};
189
190static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
9d8f549d 192#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 193#define MSRS_RANGE_SIZE 2048
194#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196#define MAX_INST_SIZE 15
197
80b7706e
JR		 198static inline u32 svm_has(u32 feat)
199{
200 return svm_features & feat;
201}
202
6aa8b732
AK		 203static inline void clgi(void)
204{
4ecac3fd 205 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 206}
207
208static inline void stgi(void)
209{
4ecac3fd 210 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 211}
212
213static inline void invlpga(unsigned long addr, u32 asid)
214{
4ecac3fd 215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 216}
217
6aa8b732
AK		 218static inline void force_new_asid(struct kvm_vcpu *vcpu)
219{
a2fa3e9f 220 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 221}
222
223static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224{
225 force_new_asid(vcpu);
226}
227
228static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229{
709ddebf 230 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 231 efer &= ~EFER_LME;
6aa8b732 232
9962d032 233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 234 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 235}
236
298101da
AK		 237static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239{
240 struct vcpu_svm *svm = to_svm(vcpu);
241
cf74a78b
AG		 242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
298101da
AK		 247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252}
253
6aa8b732
AK		 254static int is_external_interrupt(u32 info)
255{
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258}
259
2809f5d2
GC		 260static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261{
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268}
269
270static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271{
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279}
280
6aa8b732
AK		 281static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282{
a2fa3e9f
GH		 283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
851ba692 286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 289 return;
290 }
5fdbf976
MT		 291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 294
5fdbf976 295 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 296 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 297}
298
299static int has_svm(void)
300{
63d1142f 301 const char *msg;
6aa8b732 302
63d1142f 303 if (!cpu_has_svm(&msg)) {
ff81ff10 304 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 305 return 0;
306 }
307
6aa8b732
AK		 308 return 1;
309}
310
311static void svm_hardware_disable(void *garbage)
312{
2c8dceeb 313 cpu_svm_disable();
6aa8b732
AK		 314}
315
10474ae8 316static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 317{
318
0fe1e009 319 struct svm_cpu_data *sd;
6aa8b732 320 uint64_t efer;
b792c344 321 struct descriptor_table gdt_descr;
6aa8b732
AK		 322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
10474ae8
AG		 325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
6aa8b732 329 if (!has_svm()) {
e6732a5a
ZA		 330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
10474ae8 332 return -EINVAL;
6aa8b732 333 }
0fe1e009 334 sd = per_cpu(svm_data, me);
6aa8b732 335
0fe1e009 336 if (!sd) {
e6732a5a 337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 338 me);
10474ae8 339 return -EINVAL;
6aa8b732
AK		 340 }
341
0fe1e009
TH		 342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
6aa8b732 345
b792c344
AM		 346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
0fe1e009 348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 349
9962d032 350 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 351
d0316554 352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 353
354 return 0;
6aa8b732
AK		 355}
356
0da1db75
JR		 357static void svm_cpu_uninit(int cpu)
358{
0fe1e009 359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 360
0fe1e009 361 if (!sd)
0da1db75
JR		 362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 365 __free_page(sd->save_area);
366 kfree(sd);
0da1db75
JR		 367}
368
6aa8b732
AK		 369static int svm_cpu_init(int cpu)
370{
0fe1e009 371 struct svm_cpu_data *sd;
6aa8b732
AK		 372 int r;
373
0fe1e009
TH		 374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
6aa8b732 376 return -ENOMEM;
0fe1e009
TH		 377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 379 r = -ENOMEM;
0fe1e009 380 if (!sd->save_area)
6aa8b732
AK		 381 goto err_1;
382
0fe1e009 383 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 384
385 return 0;
386
387err_1:
0fe1e009 388 kfree(sd);
6aa8b732
AK		 389 return r;
390
391}
392
bfc733a7
RR		 393static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
6aa8b732
AK		 395{
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
bfc733a7 409 return;
6aa8b732
AK		 410 }
411 }
bfc733a7 412 BUG();
6aa8b732
AK		 413}
414
f65c229c
JR		 415static void svm_vcpu_init_msrpm(u32 *msrpm)
416{
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419#ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426#endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 429}
430
24e09cbf
JR		 431static void svm_enable_lbrv(struct vcpu_svm *svm)
432{
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440}
441
442static void svm_disable_lbrv(struct vcpu_svm *svm)
443{
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451}
452
6aa8b732
AK		 453static __init int svm_hardware_setup(void)
454{
455 int cpu;
456 struct page *iopm_pages;
f65c229c 457 void *iopm_va;
6aa8b732
AK		 458 int r;
459
6aa8b732
AK		 460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
c8681339
AL		 464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
50a37eb4
JR		 469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
1b2fd70c
AG		 472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
236de055
AG		 475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
3230bb47 480 for_each_possible_cpu(cpu) {
6aa8b732
AK		 481 r = svm_cpu_init(cpu);
482 if (r)
f65c229c 483 goto err;
6aa8b732 484 }
33bd6a0b
JR		 485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
e3da3acd
JR		 488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
6c7dac72
JR		 491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
18552672 496 if (npt_enabled) {
e3da3acd 497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 498 kvm_enable_tdp();
5f4cb662
JR		 499 } else
500 kvm_disable_tdp();
e3da3acd 501
6aa8b732
AK		 502 return 0;
503
f65c229c 504err:
6aa8b732
AK		 505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508}
509
510static __exit void svm_hardware_unsetup(void)
511{
0da1db75
JR		 512 int cpu;
513
3230bb47 514 for_each_possible_cpu(cpu)
0da1db75
JR		 515 svm_cpu_uninit(cpu);
516
6aa8b732 517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 518 iopm_base = 0;
6aa8b732
AK		 519}
520
521static void init_seg(struct vmcb_seg *seg)
522{
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528}
529
530static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531{
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536}
537
e6101a96 538static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 539{
e6101a96
JR		 540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 542
bff78274
AK		 543 svm->vcpu.fpu_active = 1;
544
6aa8b732
AK		 545 control->intercept_cr_read = INTERCEPT_CR0_MASK |
546 INTERCEPT_CR3_MASK |
649d6864 547 INTERCEPT_CR4_MASK;
6aa8b732
AK		 548
549 control->intercept_cr_write = INTERCEPT_CR0_MASK |
550 INTERCEPT_CR3_MASK |
80a8119c
AK		 551 INTERCEPT_CR4_MASK |
552 INTERCEPT_CR8_MASK;
6aa8b732
AK		 553
554 control->intercept_dr_read = INTERCEPT_DR0_MASK |
555 INTERCEPT_DR1_MASK |
556 INTERCEPT_DR2_MASK |
557 INTERCEPT_DR3_MASK;
558
559 control->intercept_dr_write = INTERCEPT_DR0_MASK |
560 INTERCEPT_DR1_MASK |
561 INTERCEPT_DR2_MASK |
562 INTERCEPT_DR3_MASK |
563 INTERCEPT_DR5_MASK |
564 INTERCEPT_DR7_MASK;
565
7aa81cc0 566 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 567 (1 << UD_VECTOR) |
568 (1 << MC_VECTOR);
6aa8b732
AK		 569
570
571 control->intercept = (1ULL << INTERCEPT_INTR) |
572 (1ULL << INTERCEPT_NMI) |
0152527b 573 (1ULL << INTERCEPT_SMI) |
6aa8b732 574 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 575 (1ULL << INTERCEPT_INVD) |
6aa8b732 576 (1ULL << INTERCEPT_HLT) |
a7052897 577 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 578 (1ULL << INTERCEPT_INVLPGA) |
579 (1ULL << INTERCEPT_IOIO_PROT) |
580 (1ULL << INTERCEPT_MSR_PROT) |
581 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 582 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 583 (1ULL << INTERCEPT_VMRUN) |
584 (1ULL << INTERCEPT_VMMCALL) |
585 (1ULL << INTERCEPT_VMLOAD) |
586 (1ULL << INTERCEPT_VMSAVE) |
587 (1ULL << INTERCEPT_STGI) |
588 (1ULL << INTERCEPT_CLGI) |
916ce236 589 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 590 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 591 (1ULL << INTERCEPT_MONITOR) |
592 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 593
594 control->iopm_base_pa = iopm_base;
f65c229c 595 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 596 control->tsc_offset = 0;
6aa8b732
AK		 597 control->int_ctl = V_INTR_MASKING_MASK;
598
599 init_seg(&save->es);
600 init_seg(&save->ss);
601 init_seg(&save->ds);
602 init_seg(&save->fs);
603 init_seg(&save->gs);
604
605 save->cs.selector = 0xf000;
606 /* Executable/Readable Code Segment */
607 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
608 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
609 save->cs.limit = 0xffff;
d92899a0
AK		 610 /*
611 * cs.base should really be 0xffff0000, but vmx can't handle that, so
612 * be consistent with it.
613 *
614 * Replace when we have real mode working for vmx.
615 */
616 save->cs.base = 0xf0000;
6aa8b732
AK		 617
618 save->gdtr.limit = 0xffff;
619 save->idtr.limit = 0xffff;
620
621 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
622 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
623
9962d032 624 save->efer = EFER_SVME;
d77c26fc 625 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 626 save->dr7 = 0x400;
627 save->rflags = 2;
628 save->rip = 0x0000fff0;
5fdbf976 629 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 630
18fa000a
EH		 631 /* This is the guest-visible cr0 value.
632 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 633 */
18fa000a
EH		 634 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
635 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
636
66aee91a 637 save->cr4 = X86_CR4_PAE;
6aa8b732 638 /* rdx = ?? */
709ddebf
JR		 639
640 if (npt_enabled) {
641 /* Setup VMCB for Nested Paging */
642 control->nested_ctl = 1;
a7052897
MT		 643 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
644 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 645 control->intercept_exceptions &= ~(1 << PF_VECTOR);
646 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
647 INTERCEPT_CR3_MASK);
648 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
649 INTERCEPT_CR3_MASK);
650 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 651 save->cr3 = 0;
652 save->cr4 = 0;
653 }
a79d2f18 654 force_new_asid(&svm->vcpu);
1371d904 655
e6aa9abd 656 svm->nested.vmcb = 0;
2af9194d
JR		 657 svm->vcpu.arch.hflags = 0;
658
565d0998
ML		 659 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
660 control->pause_filter_count = 3000;
661 control->intercept |= (1ULL << INTERCEPT_PAUSE);
662 }
663
2af9194d 664 enable_gif(svm);
6aa8b732
AK		 665}
666
e00c8cf2 667static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 668{
669 struct vcpu_svm *svm = to_svm(vcpu);
670
e6101a96 671 init_vmcb(svm);
70433389 672
c5af89b6 673 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 674 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 675 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
676 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 677 }
5fdbf976
MT		 678 vcpu->arch.regs_avail = ~0;
679 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 680
681 return 0;
04d2cc77
AK		 682}
683
fb3f0f51 684static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 685{
a2fa3e9f 686 struct vcpu_svm *svm;
6aa8b732 687 struct page *page;
f65c229c 688 struct page *msrpm_pages;
b286d5d8 689 struct page *hsave_page;
3d6368ef 690 struct page *nested_msrpm_pages;
fb3f0f51 691 int err;
6aa8b732 692
c16f862d 693 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 694 if (!svm) {
695 err = -ENOMEM;
696 goto out;
697 }
698
699 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
700 if (err)
701 goto free_svm;
702
6aa8b732 703 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 704 if (!page) {
705 err = -ENOMEM;
706 goto uninit;
707 }
6aa8b732 708
f65c229c
JR		 709 err = -ENOMEM;
710 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
711 if (!msrpm_pages)
712 goto uninit;
3d6368ef
AG		 713
714 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
715 if (!nested_msrpm_pages)
716 goto uninit;
717
f65c229c
JR		 718 svm->msrpm = page_address(msrpm_pages);
719 svm_vcpu_init_msrpm(svm->msrpm);
720
b286d5d8
AG		 721 hsave_page = alloc_page(GFP_KERNEL);
722 if (!hsave_page)
723 goto uninit;
e6aa9abd 724 svm->nested.hsave = page_address(hsave_page);
b286d5d8 725
e6aa9abd 726 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 727
a2fa3e9f
GH		 728 svm->vmcb = page_address(page);
729 clear_page(svm->vmcb);
730 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
731 svm->asid_generation = 0;
e6101a96 732 init_vmcb(svm);
a2fa3e9f 733
fb3f0f51 734 fx_init(&svm->vcpu);
ad312c7c 735 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 736 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 737 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 738
fb3f0f51 739 return &svm->vcpu;
36241b8c 740
fb3f0f51
RR		 741uninit:
742 kvm_vcpu_uninit(&svm->vcpu);
743free_svm:
a4770347 744 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 745out:
746 return ERR_PTR(err);
6aa8b732
AK		 747}
748
749static void svm_free_vcpu(struct kvm_vcpu *vcpu)
750{
a2fa3e9f
GH		 751 struct vcpu_svm *svm = to_svm(vcpu);
752
fb3f0f51 753 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 754 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 755 __free_page(virt_to_page(svm->nested.hsave));
756 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 757 kvm_vcpu_uninit(vcpu);
a4770347 758 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 759}
760
15ad7146 761static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 762{
a2fa3e9f 763 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 764 int i;
0cc5064d 765
0cc5064d 766 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 767 u64 delta;
0cc5064d 768
953899b6
JR		 769 if (check_tsc_unstable()) {
770 /*
771 * Make sure that the guest sees a monotonically
772 * increasing TSC.
773 */
774 delta = vcpu->arch.host_tsc - native_read_tsc();
775 svm->vmcb->control.tsc_offset += delta;
776 if (is_nested(svm))
777 svm->nested.hsave->control.tsc_offset += delta;
778 }
0cc5064d 779 vcpu->cpu = cpu;
2f599714 780 kvm_migrate_timers(vcpu);
4b656b12 781 svm->asid_generation = 0;
0cc5064d 782 }
94dfbdb3
AL		 783
784 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 785 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 786}
787
788static void svm_vcpu_put(struct kvm_vcpu *vcpu)
789{
a2fa3e9f 790 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 791 int i;
792
e1beb1d3 793 ++vcpu->stat.host_state_reload;
94dfbdb3 794 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 795 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 796
e935d48e 797 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 798}
799
6aa8b732
AK		 800static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
801{
a2fa3e9f 802 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 803}
804
805static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
806{
a2fa3e9f 807 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 808}
809
6de4f3ad
AK		 810static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
811{
812 switch (reg) {
813 case VCPU_EXREG_PDPTR:
814 BUG_ON(!npt_enabled);
815 load_pdptrs(vcpu, vcpu->arch.cr3);
816 break;
817 default:
818 BUG();
819 }
820}
821
f0b85051
AG		 822static void svm_set_vintr(struct vcpu_svm *svm)
823{
824 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
825}
826
827static void svm_clear_vintr(struct vcpu_svm *svm)
828{
829 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
830}
831
6aa8b732
AK		 832static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
833{
a2fa3e9f 834 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 835
836 switch (seg) {
837 case VCPU_SREG_CS: return &save->cs;
838 case VCPU_SREG_DS: return &save->ds;
839 case VCPU_SREG_ES: return &save->es;
840 case VCPU_SREG_FS: return &save->fs;
841 case VCPU_SREG_GS: return &save->gs;
842 case VCPU_SREG_SS: return &save->ss;
843 case VCPU_SREG_TR: return &save->tr;
844 case VCPU_SREG_LDTR: return &save->ldtr;
845 }
846 BUG();
8b6d44c7 847 return NULL;
6aa8b732
AK		 848}
849
850static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
851{
852 struct vmcb_seg *s = svm_seg(vcpu, seg);
853
854 return s->base;
855}
856
857static void svm_get_segment(struct kvm_vcpu *vcpu,
858 struct kvm_segment *var, int seg)
859{
860 struct vmcb_seg *s = svm_seg(vcpu, seg);
861
862 var->base = s->base;
863 var->limit = s->limit;
864 var->selector = s->selector;
865 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
866 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
867 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
868 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
869 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
870 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
871 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
872 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 873
19bca6ab
AP		 874 /* AMD's VMCB does not have an explicit unusable field, so emulate it
875 * for cross vendor migration purposes by "not present"
876 */
877 var->unusable = !var->present || (var->type == 0);
878
1fbdc7a5
AP		 879 switch (seg) {
880 case VCPU_SREG_CS:
881 /*
882 * SVM always stores 0 for the 'G' bit in the CS selector in
883 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
884 * Intel's VMENTRY has a check on the 'G' bit.
885 */
25022acc 886 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 887 break;
888 case VCPU_SREG_TR:
889 /*
890 * Work around a bug where the busy flag in the tr selector
891 * isn't exposed
892 */
c0d09828 893 var->type |= 0x2;
1fbdc7a5
AP		 894 break;
895 case VCPU_SREG_DS:
896 case VCPU_SREG_ES:
897 case VCPU_SREG_FS:
898 case VCPU_SREG_GS:
899 /*
900 * The accessed bit must always be set in the segment
901 * descriptor cache, although it can be cleared in the
902 * descriptor, the cached bit always remains at 1. Since
903 * Intel has a check on this, set it here to support
904 * cross-vendor migration.
905 */
906 if (!var->unusable)
907 var->type |= 0x1;
908 break;
b586eb02
AP		 909 case VCPU_SREG_SS:
910 /* On AMD CPUs sometimes the DB bit in the segment
911 * descriptor is left as 1, although the whole segment has
912 * been made unusable. Clear it here to pass an Intel VMX
913 * entry check when cross vendor migrating.
914 */
915 if (var->unusable)
916 var->db = 0;
917 break;
1fbdc7a5 918 }
6aa8b732
AK		 919}
920
2e4d2653
IE		 921static int svm_get_cpl(struct kvm_vcpu *vcpu)
922{
923 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
924
925 return save->cpl;
926}
927
6aa8b732
AK		 928static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
929{
a2fa3e9f
GH		 930 struct vcpu_svm *svm = to_svm(vcpu);
931
932 dt->limit = svm->vmcb->save.idtr.limit;
933 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 934}
935
936static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
937{
a2fa3e9f
GH		 938 struct vcpu_svm *svm = to_svm(vcpu);
939
940 svm->vmcb->save.idtr.limit = dt->limit;
941 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 942}
943
944static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
945{
a2fa3e9f
GH		 946 struct vcpu_svm *svm = to_svm(vcpu);
947
948 dt->limit = svm->vmcb->save.gdtr.limit;
949 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 950}
951
952static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
953{
a2fa3e9f
GH		 954 struct vcpu_svm *svm = to_svm(vcpu);
955
956 svm->vmcb->save.gdtr.limit = dt->limit;
957 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 958}
959
e8467fda
AK		 960static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
961{
962}
963
25c4c276 964static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 965{
966}
967
6aa8b732
AK		 968static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
969{
a2fa3e9f
GH		 970 struct vcpu_svm *svm = to_svm(vcpu);
971
05b3e0c2 972#ifdef CONFIG_X86_64
ad312c7c 973 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 974 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 975 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 976 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 977 }
978
d77c26fc 979 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 980 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 981 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 982 }
983 }
984#endif
709ddebf
JR		 985 if (npt_enabled)
986 goto set;
987
ad312c7c 988 vcpu->arch.cr0 = cr0;
707d92fa 989 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 990
991 if (!vcpu->fpu_active)
334df50a 992 cr0 |= X86_CR0_TS;
709ddebf
JR		 993set:
994 /*
995 * re-enable caching here because the QEMU bios
996 * does not do it - this results in some delay at
997 * reboot
998 */
999 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1000 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 1001}
1002
1003static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1004{
6394b649 1005 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1006 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1007
1008 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1009 force_new_asid(vcpu);
6394b649 1010
ec077263
JR		 1011 vcpu->arch.cr4 = cr4;
1012 if (!npt_enabled)
1013 cr4 |= X86_CR4_PAE;
6394b649 1014 cr4 |= host_cr4_mce;
ec077263 1015 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1016}
1017
1018static void svm_set_segment(struct kvm_vcpu *vcpu,
1019 struct kvm_segment *var, int seg)
1020{
a2fa3e9f 1021 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1022 struct vmcb_seg *s = svm_seg(vcpu, seg);
1023
1024 s->base = var->base;
1025 s->limit = var->limit;
1026 s->selector = var->selector;
1027 if (var->unusable)
1028 s->attrib = 0;
1029 else {
1030 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1031 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1032 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1033 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1034 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1035 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1036 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1037 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1038 }
1039 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1040 svm->vmcb->save.cpl
1041 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1042 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1043
1044}
1045
44c11430 1046static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1047{
d0bfb940
JK		 1048 struct vcpu_svm *svm = to_svm(vcpu);
1049
d0bfb940
JK		 1050 svm->vmcb->control.intercept_exceptions &=
1051 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1052
6be7d306 1053 if (svm->nmi_singlestep)
44c11430
GN		 1054 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1055
d0bfb940
JK		 1056 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1057 if (vcpu->guest_debug &
1058 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1059 svm->vmcb->control.intercept_exceptions |=
1060 1 << DB_VECTOR;
1061 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1062 svm->vmcb->control.intercept_exceptions |=
1063 1 << BP_VECTOR;
1064 } else
1065 vcpu->guest_debug = 0;
44c11430
GN		 1066}
1067
355be0b9 1068static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1069{
44c11430
GN		 1070 struct vcpu_svm *svm = to_svm(vcpu);
1071
ae675ef0
JK		 1072 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1073 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1074 else
1075 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1076
355be0b9 1077 update_db_intercept(vcpu);
6aa8b732
AK		 1078}
1079
1080static void load_host_msrs(struct kvm_vcpu *vcpu)
1081{
94dfbdb3 1082#ifdef CONFIG_X86_64
a2fa3e9f 1083 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1084#endif
6aa8b732
AK		 1085}
1086
1087static void save_host_msrs(struct kvm_vcpu *vcpu)
1088{
94dfbdb3 1089#ifdef CONFIG_X86_64
a2fa3e9f 1090 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1091#endif
6aa8b732
AK		 1092}
1093
0fe1e009 1094static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1095{
0fe1e009
TH		 1096 if (sd->next_asid > sd->max_asid) {
1097 ++sd->asid_generation;
1098 sd->next_asid = 1;
a2fa3e9f 1099 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1100 }
1101
0fe1e009
TH		 1102 svm->asid_generation = sd->asid_generation;
1103 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1104}
1105
6aa8b732
AK		 1106static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1107{
42dbaa5a
JK		 1108 struct vcpu_svm *svm = to_svm(vcpu);
1109 unsigned long val;
1110
1111 switch (dr) {
1112 case 0 ... 3:
1113 val = vcpu->arch.db[dr];
1114 break;
1115 case 6:
1116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117 val = vcpu->arch.dr6;
1118 else
1119 val = svm->vmcb->save.dr6;
1120 break;
1121 case 7:
1122 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1123 val = vcpu->arch.dr7;
1124 else
1125 val = svm->vmcb->save.dr7;
1126 break;
1127 default:
1128 val = 0;
1129 }
1130
af9ca2d7 1131 return val;
6aa8b732
AK		 1132}
1133
1134static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1135 int *exception)
1136{
a2fa3e9f
GH		 1137 struct vcpu_svm *svm = to_svm(vcpu);
1138
42dbaa5a 1139 *exception = 0;
6aa8b732
AK		 1140
1141 switch (dr) {
1142 case 0 ... 3:
42dbaa5a
JK		 1143 vcpu->arch.db[dr] = value;
1144 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1145 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1146 return;
1147 case 4 ... 5:
42dbaa5a 1148 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1149 *exception = UD_VECTOR;
42dbaa5a
JK		 1150 return;
1151 case 6:
1152 if (value & 0xffffffff00000000ULL) {
1153 *exception = GP_VECTOR;
6aa8b732
AK		 1154 return;
1155 }
42dbaa5a
JK		 1156 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1157 return;
1158 case 7:
1159 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1160 *exception = GP_VECTOR;
1161 return;
1162 }
42dbaa5a
JK		 1163 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1164 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1165 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1166 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1167 }
6aa8b732 1168 return;
6aa8b732 1169 default:
42dbaa5a 1170 /* FIXME: Possible case? */
6aa8b732 1171 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1172 __func__, dr);
6aa8b732
AK		 1173 *exception = UD_VECTOR;
1174 return;
1175 }
1176}
1177
851ba692 1178static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1179{
6aa8b732
AK		 1180 u64 fault_address;
1181 u32 error_code;
6aa8b732 1182
a2fa3e9f
GH		 1183 fault_address = svm->vmcb->control.exit_info_2;
1184 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1185
229456fc 1186 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1187 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1188 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1189 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1190}
1191
851ba692 1192static int db_interception(struct vcpu_svm *svm)
d0bfb940 1193{
851ba692
AK		 1194 struct kvm_run *kvm_run = svm->vcpu.run;
1195
d0bfb940 1196 if (!(svm->vcpu.guest_debug &
44c11430 1197 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1198 !svm->nmi_singlestep) {
d0bfb940
JK		 1199 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1200 return 1;
1201 }
44c11430 1202
6be7d306
JK		 1203 if (svm->nmi_singlestep) {
1204 svm->nmi_singlestep = false;
44c11430
GN		 1205 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1206 svm->vmcb->save.rflags &=
1207 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1208 update_db_intercept(&svm->vcpu);
1209 }
1210
1211 if (svm->vcpu.guest_debug &
1212 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1213 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1214 kvm_run->debug.arch.pc =
1215 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1216 kvm_run->debug.arch.exception = DB_VECTOR;
1217 return 0;
1218 }
1219
1220 return 1;
d0bfb940
JK		 1221}
1222
851ba692 1223static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1224{
851ba692
AK		 1225 struct kvm_run *kvm_run = svm->vcpu.run;
1226
d0bfb940
JK		 1227 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1228 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1229 kvm_run->debug.arch.exception = BP_VECTOR;
1230 return 0;
1231}
1232
851ba692 1233static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1234{
1235 int er;
1236
851ba692 1237 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1238 if (er != EMULATE_DONE)
7ee5d940 1239 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1240 return 1;
1241}
1242
851ba692 1243static int nm_interception(struct vcpu_svm *svm)
7807fa6c 1244{
a2fa3e9f 1245 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
4d4ec087 1246 if (!kvm_read_cr0_bits(&svm->vcpu, X86_CR0_TS))
a2fa3e9f 1247 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
02daab21
AK		 1248 else
1249 svm->vmcb->save.cr0 |= X86_CR0_TS;
e756fc62 1250 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1251
1252 return 1;
7807fa6c
AL		 1253}
1254
851ba692 1255static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1256{
1257 /*
1258 * On an #MC intercept the MCE handler is not called automatically in
1259 * the host. So do it by hand here.
1260 */
1261 asm volatile (
1262 "int $0x12\n");
1263 /* not sure if we ever come back to this point */
1264
1265 return 1;
1266}
1267
851ba692 1268static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1269{
851ba692
AK		 1270 struct kvm_run *kvm_run = svm->vcpu.run;
1271
46fe4ddd
JR		 1272 /*
1273 * VMCB is undefined after a SHUTDOWN intercept
1274 * so reinitialize it.
1275 */
a2fa3e9f 1276 clear_page(svm->vmcb);
e6101a96 1277 init_vmcb(svm);
46fe4ddd
JR		 1278
1279 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1280 return 0;
1281}
1282
851ba692 1283static int io_interception(struct vcpu_svm *svm)
6aa8b732 1284{
d77c26fc 1285 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1286 int size, in, string;
039576c0 1287 unsigned port;
6aa8b732 1288
e756fc62 1289 ++svm->vcpu.stat.io_exits;
6aa8b732 1290
a2fa3e9f 1291 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1292
e70669ab
LV		 1293 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1294
1295 if (string) {
3427318f 1296 if (emulate_instruction(&svm->vcpu,
851ba692 1297 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1298 return 0;
1299 return 1;
1300 }
1301
039576c0
AK		 1302 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1303 port = io_info >> 16;
1304 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1305
e93f36bc 1306 skip_emulated_instruction(&svm->vcpu);
851ba692 1307 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1308}
1309
851ba692 1310static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1311{
1312 return 1;
1313}
1314
851ba692 1315static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1316{
1317 ++svm->vcpu.stat.irq_exits;
1318 return 1;
1319}
1320
851ba692 1321static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1322{
1323 return 1;
1324}
1325
851ba692 1326static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1327{
5fdbf976 1328 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1329 skip_emulated_instruction(&svm->vcpu);
1330 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1331}
1332
851ba692 1333static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1334{
5fdbf976 1335 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1336 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1337 kvm_emulate_hypercall(&svm->vcpu);
1338 return 1;
02e235bc
AK		 1339}
1340
c0725420
AG		 1341static int nested_svm_check_permissions(struct vcpu_svm *svm)
1342{
1343 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1344 || !is_paging(&svm->vcpu)) {
1345 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1346 return 1;
1347 }
1348
1349 if (svm->vmcb->save.cpl) {
1350 kvm_inject_gp(&svm->vcpu, 0);
1351 return 1;
1352 }
1353
1354 return 0;
1355}
1356
cf74a78b
AG		 1357static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1358 bool has_error_code, u32 error_code)
1359{
0295ad7d
JR		 1360 if (!is_nested(svm))
1361 return 0;
cf74a78b 1362
0295ad7d
JR		 1363 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1364 svm->vmcb->control.exit_code_hi = 0;
1365 svm->vmcb->control.exit_info_1 = error_code;
1366 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1367
410e4d57 1368 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1369}
1370
1371static inline int nested_svm_intr(struct vcpu_svm *svm)
1372{
26666957
JR		 1373 if (!is_nested(svm))
1374 return 0;
cf74a78b 1375
26666957
JR		 1376 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1377 return 0;
cf74a78b 1378
26666957
JR		 1379 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1380 return 0;
cf74a78b 1381
26666957
JR		 1382 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1383
cd3ff653
JR		 1384 if (svm->nested.intercept & 1ULL) {
1385 /*
1386 * The #vmexit can't be emulated here directly because this
1387 * code path runs with irqs and preemtion disabled. A
1388 * #vmexit emulation might sleep. Only signal request for
1389 * the #vmexit here.
1390 */
1391 svm->nested.exit_required = true;
236649de 1392 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1393 return 1;
cf74a78b
AG		 1394 }
1395
1396 return 0;
1397}
1398
34f80cfa
JR		 1399static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1400{
1401 struct page *page;
1402
34f80cfa 1403 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1404 if (is_error_page(page))
1405 goto error;
1406
1407 return kmap_atomic(page, idx);
1408
1409error:
1410 kvm_release_page_clean(page);
1411 kvm_inject_gp(&svm->vcpu, 0);
1412
1413 return NULL;
1414}
1415
1416static void nested_svm_unmap(void *addr, enum km_type idx)
1417{
1418 struct page *page;
1419
1420 if (!addr)
1421 return;
1422
1423 page = kmap_atomic_to_page(addr);
1424
1425 kunmap_atomic(addr, idx);
1426 kvm_release_page_dirty(page);
1427}
1428
3d62d9aa 1429static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1430{
4c2161ae 1431 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1432 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1433 bool ret = false;
1434 u32 t0, t1;
1435 u8 *msrpm;
4c2161ae 1436
3d62d9aa
JR		 1437 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1438 return false;
1439
1440 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1441
1442 if (!msrpm)
1443 goto out;
4c2161ae
JR		 1444
1445 switch (msr) {
1446 case 0 ... 0x1fff:
1447 t0 = (msr * 2) % 8;
1448 t1 = msr / 8;
1449 break;
1450 case 0xc0000000 ... 0xc0001fff:
1451 t0 = (8192 + msr - 0xc0000000) * 2;
1452 t1 = (t0 / 8);
1453 t0 %= 8;
1454 break;
1455 case 0xc0010000 ... 0xc0011fff:
1456 t0 = (16384 + msr - 0xc0010000) * 2;
1457 t1 = (t0 / 8);
1458 t0 %= 8;
1459 break;
1460 default:
3d62d9aa
JR		 1461 ret = true;
1462 goto out;
4c2161ae 1463 }
4c2161ae 1464
3d62d9aa
JR		 1465 ret = msrpm[t1] & ((1 << param) << t0);
1466
1467out:
1468 nested_svm_unmap(msrpm, KM_USER0);
1469
1470 return ret;
4c2161ae
JR		 1471}
1472
410e4d57 1473static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1474{
cf74a78b 1475 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1476
410e4d57
JR		 1477 switch (exit_code) {
1478 case SVM_EXIT_INTR:
1479 case SVM_EXIT_NMI:
1480 return NESTED_EXIT_HOST;
cf74a78b 1481 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1482 case SVM_EXIT_NPF:
1483 if (npt_enabled)
1484 return NESTED_EXIT_HOST;
1485 break;
1486 /* When we're shadowing, trap PFs */
1487 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1488 if (!npt_enabled)
1489 return NESTED_EXIT_HOST;
1490 break;
1491 default:
1492 break;
cf74a78b
AG		 1493 }
1494
410e4d57
JR		 1495 return NESTED_EXIT_CONTINUE;
1496}
1497
1498/*
1499 * If this function returns true, this #vmexit was already handled
1500 */
1501static int nested_svm_exit_handled(struct vcpu_svm *svm)
1502{
1503 u32 exit_code = svm->vmcb->control.exit_code;
1504 int vmexit = NESTED_EXIT_HOST;
1505
cf74a78b 1506 switch (exit_code) {
9c4e40b9 1507 case SVM_EXIT_MSR:
3d62d9aa 1508 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1509 break;
cf74a78b
AG		 1510 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1511 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1512 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1513 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1514 break;
1515 }
1516 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1517 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1518 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1519 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1520 break;
1521 }
1522 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1523 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1524 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1525 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1526 break;
1527 }
1528 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1529 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1530 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1531 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1532 break;
1533 }
1534 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1535 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1536 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1537 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1538 break;
1539 }
1540 default: {
1541 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1542 if (svm->nested.intercept & exit_bits)
410e4d57 1543 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1544 }
1545 }
1546
410e4d57 1547 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1548 nested_svm_vmexit(svm);
1549 }
1550
1551 return vmexit;
cf74a78b
AG		 1552}
1553
0460a979
JR		 1554static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1555{
1556 struct vmcb_control_area *dst = &dst_vmcb->control;
1557 struct vmcb_control_area *from = &from_vmcb->control;
1558
1559 dst->intercept_cr_read = from->intercept_cr_read;
1560 dst->intercept_cr_write = from->intercept_cr_write;
1561 dst->intercept_dr_read = from->intercept_dr_read;
1562 dst->intercept_dr_write = from->intercept_dr_write;
1563 dst->intercept_exceptions = from->intercept_exceptions;
1564 dst->intercept = from->intercept;
1565 dst->iopm_base_pa = from->iopm_base_pa;
1566 dst->msrpm_base_pa = from->msrpm_base_pa;
1567 dst->tsc_offset = from->tsc_offset;
1568 dst->asid = from->asid;
1569 dst->tlb_ctl = from->tlb_ctl;
1570 dst->int_ctl = from->int_ctl;
1571 dst->int_vector = from->int_vector;
1572 dst->int_state = from->int_state;
1573 dst->exit_code = from->exit_code;
1574 dst->exit_code_hi = from->exit_code_hi;
1575 dst->exit_info_1 = from->exit_info_1;
1576 dst->exit_info_2 = from->exit_info_2;
1577 dst->exit_int_info = from->exit_int_info;
1578 dst->exit_int_info_err = from->exit_int_info_err;
1579 dst->nested_ctl = from->nested_ctl;
1580 dst->event_inj = from->event_inj;
1581 dst->event_inj_err = from->event_inj_err;
1582 dst->nested_cr3 = from->nested_cr3;
1583 dst->lbr_ctl = from->lbr_ctl;
1584}
1585
34f80cfa 1586static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1587{
34f80cfa 1588 struct vmcb *nested_vmcb;
e6aa9abd 1589 struct vmcb *hsave = svm->nested.hsave;
33740e40 1590 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1591
17897f36
JR		 1592 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1593 vmcb->control.exit_info_1,
1594 vmcb->control.exit_info_2,
1595 vmcb->control.exit_int_info,
1596 vmcb->control.exit_int_info_err);
1597
34f80cfa
JR		 1598 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1599 if (!nested_vmcb)
1600 return 1;
1601
cf74a78b 1602 /* Give the current vmcb to the guest */
33740e40
JR		 1603 disable_gif(svm);
1604
1605 nested_vmcb->save.es = vmcb->save.es;
1606 nested_vmcb->save.cs = vmcb->save.cs;
1607 nested_vmcb->save.ss = vmcb->save.ss;
1608 nested_vmcb->save.ds = vmcb->save.ds;
1609 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1610 nested_vmcb->save.idtr = vmcb->save.idtr;
1611 if (npt_enabled)
1612 nested_vmcb->save.cr3 = vmcb->save.cr3;
1613 nested_vmcb->save.cr2 = vmcb->save.cr2;
1614 nested_vmcb->save.rflags = vmcb->save.rflags;
1615 nested_vmcb->save.rip = vmcb->save.rip;
1616 nested_vmcb->save.rsp = vmcb->save.rsp;
1617 nested_vmcb->save.rax = vmcb->save.rax;
1618 nested_vmcb->save.dr7 = vmcb->save.dr7;
1619 nested_vmcb->save.dr6 = vmcb->save.dr6;
1620 nested_vmcb->save.cpl = vmcb->save.cpl;
1621
1622 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1623 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1624 nested_vmcb->control.int_state = vmcb->control.int_state;
1625 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1626 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1627 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1628 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1629 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1630 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1631
1632 /*
1633 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1634 * to make sure that we do not lose injected events. So check event_inj
1635 * here and copy it to exit_int_info if it is valid.
1636 * Exit_int_info and event_inj can't be both valid because the case
1637 * below only happens on a VMRUN instruction intercept which has
1638 * no valid exit_int_info set.
1639 */
1640 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1641 struct vmcb_control_area *nc = &nested_vmcb->control;
1642
1643 nc->exit_int_info = vmcb->control.event_inj;
1644 nc->exit_int_info_err = vmcb->control.event_inj_err;
1645 }
1646
33740e40
JR		 1647 nested_vmcb->control.tlb_ctl = 0;
1648 nested_vmcb->control.event_inj = 0;
1649 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1650
1651 /* We always set V_INTR_MASKING and remember the old value in hflags */
1652 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1653 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1654
cf74a78b 1655 /* Restore the original control entries */
0460a979 1656 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1657
219b65dc
AG		 1658 kvm_clear_exception_queue(&svm->vcpu);
1659 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1660
1661 /* Restore selected save entries */
1662 svm->vmcb->save.es = hsave->save.es;
1663 svm->vmcb->save.cs = hsave->save.cs;
1664 svm->vmcb->save.ss = hsave->save.ss;
1665 svm->vmcb->save.ds = hsave->save.ds;
1666 svm->vmcb->save.gdtr = hsave->save.gdtr;
1667 svm->vmcb->save.idtr = hsave->save.idtr;
1668 svm->vmcb->save.rflags = hsave->save.rflags;
1669 svm_set_efer(&svm->vcpu, hsave->save.efer);
1670 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1671 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1672 if (npt_enabled) {
1673 svm->vmcb->save.cr3 = hsave->save.cr3;
1674 svm->vcpu.arch.cr3 = hsave->save.cr3;
1675 } else {
1676 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1677 }
1678 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1679 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1680 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1681 svm->vmcb->save.dr7 = 0;
1682 svm->vmcb->save.cpl = 0;
1683 svm->vmcb->control.exit_int_info = 0;
1684
cf74a78b 1685 /* Exit nested SVM mode */
e6aa9abd 1686 svm->nested.vmcb = 0;
cf74a78b 1687
34f80cfa 1688 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1689
1690 kvm_mmu_reset_context(&svm->vcpu);
1691 kvm_mmu_load(&svm->vcpu);
1692
1693 return 0;
1694}
3d6368ef 1695
9738b2c9 1696static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1697{
9738b2c9 1698 u32 *nested_msrpm;
3d6368ef 1699 int i;
9738b2c9
JR		 1700
1701 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1702 if (!nested_msrpm)
1703 return false;
1704
3d6368ef 1705 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1706 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1707
e6aa9abd 1708 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1709
9738b2c9
JR		 1710 nested_svm_unmap(nested_msrpm, KM_USER0);
1711
1712 return true;
3d6368ef
AG		 1713}
1714
9738b2c9 1715static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1716{
9738b2c9 1717 struct vmcb *nested_vmcb;
e6aa9abd 1718 struct vmcb *hsave = svm->nested.hsave;
defbba56 1719 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1720
9738b2c9
JR		 1721 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1722 if (!nested_vmcb)
1723 return false;
1724
3d6368ef 1725 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1726 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1727
0ac406de
JR		 1728 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1729 nested_vmcb->save.rip,
1730 nested_vmcb->control.int_ctl,
1731 nested_vmcb->control.event_inj,
1732 nested_vmcb->control.nested_ctl);
1733
3d6368ef 1734 /* Clear internal status */
219b65dc
AG		 1735 kvm_clear_exception_queue(&svm->vcpu);
1736 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1737
1738 /* Save the old vmcb, so we don't need to pick what we save, but
1739 can restore everything when a VMEXIT occurs */
defbba56
JR		 1740 hsave->save.es = vmcb->save.es;
1741 hsave->save.cs = vmcb->save.cs;
1742 hsave->save.ss = vmcb->save.ss;
1743 hsave->save.ds = vmcb->save.ds;
1744 hsave->save.gdtr = vmcb->save.gdtr;
1745 hsave->save.idtr = vmcb->save.idtr;
1746 hsave->save.efer = svm->vcpu.arch.shadow_efer;
4d4ec087 1747 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1748 hsave->save.cr4 = svm->vcpu.arch.cr4;
1749 hsave->save.rflags = vmcb->save.rflags;
1750 hsave->save.rip = svm->next_rip;
1751 hsave->save.rsp = vmcb->save.rsp;
1752 hsave->save.rax = vmcb->save.rax;
1753 if (npt_enabled)
1754 hsave->save.cr3 = vmcb->save.cr3;
1755 else
1756 hsave->save.cr3 = svm->vcpu.arch.cr3;
1757
0460a979 1758 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1759
1760 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1761 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1762 else
1763 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1764
1765 /* Load the nested guest state */
1766 svm->vmcb->save.es = nested_vmcb->save.es;
1767 svm->vmcb->save.cs = nested_vmcb->save.cs;
1768 svm->vmcb->save.ss = nested_vmcb->save.ss;
1769 svm->vmcb->save.ds = nested_vmcb->save.ds;
1770 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1771 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1772 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1773 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1774 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1775 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1776 if (npt_enabled) {
1777 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1778 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1779 } else {
1780 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1781 kvm_mmu_reset_context(&svm->vcpu);
1782 }
defbba56 1783 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1784 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1785 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1786 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1787 /* In case we don't even reach vcpu_run, the fields are not updated */
1788 svm->vmcb->save.rax = nested_vmcb->save.rax;
1789 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1790 svm->vmcb->save.rip = nested_vmcb->save.rip;
1791 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1792 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1793 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1794
1795 /* We don't want a nested guest to be more powerful than the guest,
1796 so all intercepts are ORed */
1797 svm->vmcb->control.intercept_cr_read |=
1798 nested_vmcb->control.intercept_cr_read;
1799 svm->vmcb->control.intercept_cr_write |=
1800 nested_vmcb->control.intercept_cr_write;
1801 svm->vmcb->control.intercept_dr_read |=
1802 nested_vmcb->control.intercept_dr_read;
1803 svm->vmcb->control.intercept_dr_write |=
1804 nested_vmcb->control.intercept_dr_write;
1805 svm->vmcb->control.intercept_exceptions |=
1806 nested_vmcb->control.intercept_exceptions;
1807
1808 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1809
e6aa9abd 1810 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1811
aad42c64
JR		 1812 /* cache intercepts */
1813 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1814 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1815 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1816 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1817 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1818 svm->nested.intercept = nested_vmcb->control.intercept;
1819
3d6368ef 1820 force_new_asid(&svm->vcpu);
3d6368ef 1821 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1822 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1823 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1824 else
1825 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1826
3d6368ef
AG		 1827 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1828 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1829 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1830 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1831 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1832
9738b2c9
JR		 1833 nested_svm_unmap(nested_vmcb, KM_USER0);
1834
2af9194d 1835 enable_gif(svm);
3d6368ef 1836
9738b2c9 1837 return true;
3d6368ef
AG		 1838}
1839
9966bf68 1840static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1841{
1842 to_vmcb->save.fs = from_vmcb->save.fs;
1843 to_vmcb->save.gs = from_vmcb->save.gs;
1844 to_vmcb->save.tr = from_vmcb->save.tr;
1845 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1846 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1847 to_vmcb->save.star = from_vmcb->save.star;
1848 to_vmcb->save.lstar = from_vmcb->save.lstar;
1849 to_vmcb->save.cstar = from_vmcb->save.cstar;
1850 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1851 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1852 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1853 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1854}
1855
851ba692 1856static int vmload_interception(struct vcpu_svm *svm)
5542675b 1857{
9966bf68
JR		 1858 struct vmcb *nested_vmcb;
1859
5542675b
AG		 1860 if (nested_svm_check_permissions(svm))
1861 return 1;
1862
1863 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1864 skip_emulated_instruction(&svm->vcpu);
1865
9966bf68
JR		 1866 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1867 if (!nested_vmcb)
1868 return 1;
1869
1870 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1871 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1872
1873 return 1;
1874}
1875
851ba692 1876static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1877{
9966bf68
JR		 1878 struct vmcb *nested_vmcb;
1879
5542675b
AG		 1880 if (nested_svm_check_permissions(svm))
1881 return 1;
1882
1883 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1884 skip_emulated_instruction(&svm->vcpu);
1885
9966bf68
JR		 1886 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1887 if (!nested_vmcb)
1888 return 1;
1889
1890 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1891 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1892
1893 return 1;
1894}
1895
851ba692 1896static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1897{
3d6368ef
AG		 1898 if (nested_svm_check_permissions(svm))
1899 return 1;
1900
1901 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1902 skip_emulated_instruction(&svm->vcpu);
1903
9738b2c9 1904 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1905 return 1;
1906
9738b2c9 1907 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1908 goto failed;
1909
1910 return 1;
1911
1912failed:
1913
1914 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1915 svm->vmcb->control.exit_code_hi = 0;
1916 svm->vmcb->control.exit_info_1 = 0;
1917 svm->vmcb->control.exit_info_2 = 0;
1918
1919 nested_svm_vmexit(svm);
3d6368ef
AG		 1920
1921 return 1;
1922}
1923
851ba692 1924static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1925{
1926 if (nested_svm_check_permissions(svm))
1927 return 1;
1928
1929 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1930 skip_emulated_instruction(&svm->vcpu);
1931
2af9194d 1932 enable_gif(svm);
1371d904
AG		 1933
1934 return 1;
1935}
1936
851ba692 1937static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1938{
1939 if (nested_svm_check_permissions(svm))
1940 return 1;
1941
1942 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1943 skip_emulated_instruction(&svm->vcpu);
1944
2af9194d 1945 disable_gif(svm);
1371d904
AG		 1946
1947 /* After a CLGI no interrupts should come */
1948 svm_clear_vintr(svm);
1949 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1950
1951 return 1;
1952}
1953
851ba692 1954static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1955{
1956 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 1957
ec1ff790
JR		 1958 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1959 vcpu->arch.regs[VCPU_REGS_RAX]);
1960
ff092385
AG		 1961 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1962 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1963
1964 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1965 skip_emulated_instruction(&svm->vcpu);
1966 return 1;
1967}
1968
532a46b9
JR		 1969static int skinit_interception(struct vcpu_svm *svm)
1970{
1971 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1972
1973 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1974 return 1;
1975}
1976
851ba692 1977static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1978{
7ee5d940 1979 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1980 return 1;
1981}
1982
851ba692 1983static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 1984{
37817f29 1985 u16 tss_selector;
64a7ec06
GN		 1986 int reason;
1987 int int_type = svm->vmcb->control.exit_int_info &
1988 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1989 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1990 uint32_t type =
1991 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1992 uint32_t idt_v =
1993 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1994
1995 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1996
37817f29
IE		 1997 if (svm->vmcb->control.exit_info_2 &
1998 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1999 reason = TASK_SWITCH_IRET;
2000 else if (svm->vmcb->control.exit_info_2 &
2001 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2002 reason = TASK_SWITCH_JMP;
fe8e7f83 2003 else if (idt_v)
64a7ec06
GN		 2004 reason = TASK_SWITCH_GATE;
2005 else
2006 reason = TASK_SWITCH_CALL;
2007
fe8e7f83
GN		 2008 if (reason == TASK_SWITCH_GATE) {
2009 switch (type) {
2010 case SVM_EXITINTINFO_TYPE_NMI:
2011 svm->vcpu.arch.nmi_injected = false;
2012 break;
2013 case SVM_EXITINTINFO_TYPE_EXEPT:
2014 kvm_clear_exception_queue(&svm->vcpu);
2015 break;
2016 case SVM_EXITINTINFO_TYPE_INTR:
2017 kvm_clear_interrupt_queue(&svm->vcpu);
2018 break;
2019 default:
2020 break;
2021 }
2022 }
64a7ec06 2023
8317c298
GN		 2024 if (reason != TASK_SWITCH_GATE ||
2025 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2026 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2027 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2028 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2029
2030 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2031}
2032
851ba692 2033static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2034{
5fdbf976 2035 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2036 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2037 return 1;
6aa8b732
AK		 2038}
2039
851ba692 2040static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2041{
2042 ++svm->vcpu.stat.nmi_window_exits;
2043 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2044 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2045 return 1;
2046}
2047
851ba692 2048static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2049{
851ba692 2050 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2051 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2052 return 1;
2053}
2054
851ba692 2055static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2056{
851ba692 2057 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2058 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2059 return 1;
2060}
2061
851ba692 2062static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2063{
851ba692
AK		 2064 struct kvm_run *kvm_run = svm->vcpu.run;
2065
0a5fff19
GN		 2066 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2067 /* instruction emulation calls kvm_set_cr8() */
851ba692 2068 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2069 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2070 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2071 return 1;
95ba8273 2072 }
0a5fff19
GN		 2073 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2074 return 1;
1d075434
JR		 2075 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2076 return 0;
2077}
2078
6aa8b732
AK		 2079static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2080{
a2fa3e9f
GH		 2081 struct vcpu_svm *svm = to_svm(vcpu);
2082
6aa8b732 2083 switch (ecx) {
af24a4e4 2084 case MSR_IA32_TSC: {
20824f30 2085 u64 tsc_offset;
6aa8b732 2086
20824f30
JR		 2087 if (is_nested(svm))
2088 tsc_offset = svm->nested.hsave->control.tsc_offset;
2089 else
2090 tsc_offset = svm->vmcb->control.tsc_offset;
2091
2092 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2093 break;
2094 }
0e859cac 2095 case MSR_K6_STAR:
a2fa3e9f 2096 *data = svm->vmcb->save.star;
6aa8b732 2097 break;
0e859cac 2098#ifdef CONFIG_X86_64
6aa8b732 2099 case MSR_LSTAR:
a2fa3e9f 2100 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2101 break;
2102 case MSR_CSTAR:
a2fa3e9f 2103 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2104 break;
2105 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2106 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2107 break;
2108 case MSR_SYSCALL_MASK:
a2fa3e9f 2109 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2110 break;
2111#endif
2112 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2113 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2114 break;
2115 case MSR_IA32_SYSENTER_EIP:
017cb99e 2116 *data = svm->sysenter_eip;
6aa8b732
AK		 2117 break;
2118 case MSR_IA32_SYSENTER_ESP:
017cb99e 2119 *data = svm->sysenter_esp;
6aa8b732 2120 break;
a2938c80
JR		 2121 /* Nobody will change the following 5 values in the VMCB so
2122 we can safely return them on rdmsr. They will always be 0
2123 until LBRV is implemented. */
2124 case MSR_IA32_DEBUGCTLMSR:
2125 *data = svm->vmcb->save.dbgctl;
2126 break;
2127 case MSR_IA32_LASTBRANCHFROMIP:
2128 *data = svm->vmcb->save.br_from;
2129 break;
2130 case MSR_IA32_LASTBRANCHTOIP:
2131 *data = svm->vmcb->save.br_to;
2132 break;
2133 case MSR_IA32_LASTINTFROMIP:
2134 *data = svm->vmcb->save.last_excp_from;
2135 break;
2136 case MSR_IA32_LASTINTTOIP:
2137 *data = svm->vmcb->save.last_excp_to;
2138 break;
b286d5d8 2139 case MSR_VM_HSAVE_PA:
e6aa9abd 2140 *data = svm->nested.hsave_msr;
b286d5d8 2141 break;
eb6f302e
JR		 2142 case MSR_VM_CR:
2143 *data = 0;
2144 break;
c8a73f18
AG		 2145 case MSR_IA32_UCODE_REV:
2146 *data = 0x01000065;
2147 break;
6aa8b732 2148 default:
3bab1f5d 2149 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2150 }
2151 return 0;
2152}
2153
851ba692 2154static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2155{
ad312c7c 2156 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2157 u64 data;
2158
e756fc62 2159 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2160 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2161 else {
229456fc 2162 trace_kvm_msr_read(ecx, data);
af9ca2d7 2163
5fdbf976 2164 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2165 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2166 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2167 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2168 }
2169 return 1;
2170}
2171
2172static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2173{
a2fa3e9f
GH		 2174 struct vcpu_svm *svm = to_svm(vcpu);
2175
6aa8b732 2176 switch (ecx) {
af24a4e4 2177 case MSR_IA32_TSC: {
20824f30
JR		 2178 u64 tsc_offset = data - native_read_tsc();
2179 u64 g_tsc_offset = 0;
2180
2181 if (is_nested(svm)) {
2182 g_tsc_offset = svm->vmcb->control.tsc_offset -
2183 svm->nested.hsave->control.tsc_offset;
2184 svm->nested.hsave->control.tsc_offset = tsc_offset;
2185 }
2186
2187 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2188
6aa8b732
AK		 2189 break;
2190 }
0e859cac 2191 case MSR_K6_STAR:
a2fa3e9f 2192 svm->vmcb->save.star = data;
6aa8b732 2193 break;
49b14f24 2194#ifdef CONFIG_X86_64
6aa8b732 2195 case MSR_LSTAR:
a2fa3e9f 2196 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2197 break;
2198 case MSR_CSTAR:
a2fa3e9f 2199 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2200 break;
2201 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2202 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2203 break;
2204 case MSR_SYSCALL_MASK:
a2fa3e9f 2205 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2206 break;
2207#endif
2208 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2209 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2210 break;
2211 case MSR_IA32_SYSENTER_EIP:
017cb99e 2212 svm->sysenter_eip = data;
a2fa3e9f 2213 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2214 break;
2215 case MSR_IA32_SYSENTER_ESP:
017cb99e 2216 svm->sysenter_esp = data;
a2fa3e9f 2217 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2218 break;
a2938c80 2219 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2220 if (!svm_has(SVM_FEATURE_LBRV)) {
2221 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2222 __func__, data);
24e09cbf
JR		 2223 break;
2224 }
2225 if (data & DEBUGCTL_RESERVED_BITS)
2226 return 1;
2227
2228 svm->vmcb->save.dbgctl = data;
2229 if (data & (1ULL<<0))
2230 svm_enable_lbrv(svm);
2231 else
2232 svm_disable_lbrv(svm);
a2938c80 2233 break;
b286d5d8 2234 case MSR_VM_HSAVE_PA:
e6aa9abd 2235 svm->nested.hsave_msr = data;
62b9abaa 2236 break;
3c5d0a44
AG		 2237 case MSR_VM_CR:
2238 case MSR_VM_IGNNE:
3c5d0a44
AG		 2239 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2240 break;
6aa8b732 2241 default:
3bab1f5d 2242 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2243 }
2244 return 0;
2245}
2246
851ba692 2247static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2248{
ad312c7c 2249 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2250 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2251 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2252
229456fc 2253 trace_kvm_msr_write(ecx, data);
af9ca2d7 2254
5fdbf976 2255 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2256 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2257 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2258 else
e756fc62 2259 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2260 return 1;
2261}
2262
851ba692 2263static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2264{
e756fc62 2265 if (svm->vmcb->control.exit_info_1)
851ba692 2266 return wrmsr_interception(svm);
6aa8b732 2267 else
851ba692 2268 return rdmsr_interception(svm);
6aa8b732
AK		 2269}
2270
851ba692 2271static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2272{
851ba692
AK		 2273 struct kvm_run *kvm_run = svm->vcpu.run;
2274
f0b85051 2275 svm_clear_vintr(svm);
85f455f7 2276 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2277 /*
2278 * If the user space waits to inject interrupts, exit as soon as
2279 * possible
2280 */
8061823a
GN		 2281 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2282 kvm_run->request_interrupt_window &&
2283 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2284 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2285 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2286 return 0;
2287 }
2288
2289 return 1;
2290}
2291
565d0998
ML		 2292static int pause_interception(struct vcpu_svm *svm)
2293{
2294 kvm_vcpu_on_spin(&(svm->vcpu));
2295 return 1;
2296}
2297
851ba692 2298static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2299 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2300 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2301 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2302 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2303 /* for now: */
2304 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2305 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2306 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2307 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2308 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2309 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2310 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2311 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2312 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2313 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2314 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2315 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2316 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2317 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2318 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2319 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2320 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2321 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2322 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2323 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2324 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2325 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2326 [SVM_EXIT_SMI] = nop_on_interception,
2327 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2328 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2329 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2330 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2331 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2332 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2333 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2334 [SVM_EXIT_HLT] = halt_interception,
a7052897 2335 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2336 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2337 [SVM_EXIT_IOIO] = io_interception,
2338 [SVM_EXIT_MSR] = msr_interception,
2339 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2340 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2341 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2342 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2343 [SVM_EXIT_VMLOAD] = vmload_interception,
2344 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2345 [SVM_EXIT_STGI] = stgi_interception,
2346 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2347 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2348 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2349 [SVM_EXIT_MONITOR] = invalid_op_interception,
2350 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2351 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2352};
2353
851ba692 2354static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2355{
04d2cc77 2356 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2357 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2358 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2359
229456fc 2360 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2361
cd3ff653
JR		 2362 if (unlikely(svm->nested.exit_required)) {
2363 nested_svm_vmexit(svm);
2364 svm->nested.exit_required = false;
2365
2366 return 1;
2367 }
2368
cf74a78b 2369 if (is_nested(svm)) {
410e4d57
JR		 2370 int vmexit;
2371
d8cabddf
JR		 2372 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2373 svm->vmcb->control.exit_info_1,
2374 svm->vmcb->control.exit_info_2,
2375 svm->vmcb->control.exit_int_info,
2376 svm->vmcb->control.exit_int_info_err);
2377
410e4d57
JR		 2378 vmexit = nested_svm_exit_special(svm);
2379
2380 if (vmexit == NESTED_EXIT_CONTINUE)
2381 vmexit = nested_svm_exit_handled(svm);
2382
2383 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2384 return 1;
cf74a78b
AG		 2385 }
2386
a5c3832d
JR		 2387 svm_complete_interrupts(svm);
2388
709ddebf
JR		 2389 if (npt_enabled) {
2390 int mmu_reload = 0;
4d4ec087
AK		 2391 if ((kvm_read_cr0_bits(vcpu, X86_CR0_PG) ^ svm->vmcb->save.cr0)
2392 & X86_CR0_PG) {
709ddebf
JR		 2393 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2394 mmu_reload = 1;
2395 }
2396 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2397 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2398 if (mmu_reload) {
2399 kvm_mmu_reset_context(vcpu);
2400 kvm_mmu_load(vcpu);
2401 }
2402 }
2403
04d2cc77
AK		 2404
2405 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2406 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2407 kvm_run->fail_entry.hardware_entry_failure_reason
2408 = svm->vmcb->control.exit_code;
2409 return 0;
2410 }
2411
a2fa3e9f 2412 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2413 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2414 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2415 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2416 "exit_code 0x%x\n",
b8688d51 2417 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2418 exit_code);
2419
9d8f549d 2420 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2421 || !svm_exit_handlers[exit_code]) {
6aa8b732 2422 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2423 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2424 return 0;
2425 }
2426
851ba692 2427 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2428}
2429
2430static void reload_tss(struct kvm_vcpu *vcpu)
2431{
2432 int cpu = raw_smp_processor_id();
2433
0fe1e009
TH		 2434 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2435 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2436 load_TR_desc();
2437}
2438
e756fc62 2439static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2440{
2441 int cpu = raw_smp_processor_id();
2442
0fe1e009 2443 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2444
a2fa3e9f 2445 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2446 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2447 if (svm->asid_generation != sd->asid_generation)
2448 new_asid(svm, sd);
6aa8b732
AK		 2449}
2450
95ba8273
GN		 2451static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2452{
2453 struct vcpu_svm *svm = to_svm(vcpu);
2454
2455 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2456 vcpu->arch.hflags |= HF_NMI_MASK;
2457 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2458 ++vcpu->stat.nmi_injections;
2459}
6aa8b732 2460
85f455f7 2461static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2462{
2463 struct vmcb_control_area *control;
2464
229456fc 2465 trace_kvm_inj_virq(irq);
af9ca2d7 2466
fa89a817 2467 ++svm->vcpu.stat.irq_injections;
e756fc62 2468 control = &svm->vmcb->control;
85f455f7 2469 control->int_vector = irq;
6aa8b732
AK		 2470 control->int_ctl &= ~V_INTR_PRIO_MASK;
2471 control->int_ctl |= V_IRQ_MASK |
2472 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2473}
2474
66fd3f7f 2475static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2476{
2477 struct vcpu_svm *svm = to_svm(vcpu);
2478
2af9194d 2479 BUG_ON(!(gif_set(svm)));
cf74a78b 2480
219b65dc
AG		 2481 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2482 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2483}
2484
95ba8273 2485static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2486{
2487 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2488
95ba8273 2489 if (irr == -1)
aaacfc9a
JR		 2490 return;
2491
95ba8273
GN		 2492 if (tpr >= irr)
2493 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2494}
aaacfc9a 2495
95ba8273
GN		 2496static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2497{
2498 struct vcpu_svm *svm = to_svm(vcpu);
2499 struct vmcb *vmcb = svm->vmcb;
2500 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2501 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2502}
2503
3cfc3092
JK		 2504static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2505{
2506 struct vcpu_svm *svm = to_svm(vcpu);
2507
2508 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2509}
2510
2511static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2512{
2513 struct vcpu_svm *svm = to_svm(vcpu);
2514
2515 if (masked) {
2516 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2517 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2518 } else {
2519 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2520 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2521 }
2522}
2523
78646121
GN		 2524static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2525{
2526 struct vcpu_svm *svm = to_svm(vcpu);
2527 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2528 int ret;
2529
2530 if (!gif_set(svm) ||
2531 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2532 return 0;
2533
2534 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2535
2536 if (is_nested(svm))
2537 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2538
2539 return ret;
78646121
GN		 2540}
2541
9222be18 2542static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2543{
219b65dc 2544 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2545
2546 nested_svm_intr(svm);
2547
2548 /* In case GIF=0 we can't rely on the CPU to tell us when
2549 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2550 * The next time we get that intercept, this function will be
2551 * called again though and we'll get the vintr intercept. */
2af9194d 2552 if (gif_set(svm)) {
219b65dc
AG		 2553 svm_set_vintr(svm);
2554 svm_inject_irq(svm, 0x0);
2555 }
85f455f7
ED		 2556}
2557
95ba8273 2558static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2559{
04d2cc77 2560 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2561
44c11430
GN		 2562 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2563 == HF_NMI_MASK)
2564 return; /* IRET will cause a vm exit */
2565
2566 /* Something prevents NMI from been injected. Single step over
2567 possible problem (IRET or exception injection or interrupt
2568 shadow) */
6be7d306 2569 svm->nmi_singlestep = true;
44c11430
GN		 2570 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2571 update_db_intercept(vcpu);
c1150d8c
DL		 2572}
2573
cbc94022
IE		 2574static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2575{
2576 return 0;
2577}
2578
d9e368d6
AK		 2579static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2580{
2581 force_new_asid(vcpu);
2582}
2583
04d2cc77
AK		 2584static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2585{
02daab21
AK		 2586 if (npt_enabled)
2587 vcpu->fpu_active = 1;
04d2cc77
AK		 2588}
2589
d7bf8221
JR		 2590static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2591{
2592 struct vcpu_svm *svm = to_svm(vcpu);
2593
2594 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2595 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2596 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2597 }
2598}
2599
649d6864
JR		 2600static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2601{
2602 struct vcpu_svm *svm = to_svm(vcpu);
2603 u64 cr8;
2604
649d6864
JR		 2605 cr8 = kvm_get_cr8(vcpu);
2606 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2607 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2608}
2609
9222be18
GN		 2610static void svm_complete_interrupts(struct vcpu_svm *svm)
2611{
2612 u8 vector;
2613 int type;
2614 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2615
44c11430
GN		 2616 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2617 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2618
9222be18
GN		 2619 svm->vcpu.arch.nmi_injected = false;
2620 kvm_clear_exception_queue(&svm->vcpu);
2621 kvm_clear_interrupt_queue(&svm->vcpu);
2622
2623 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2624 return;
2625
2626 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2627 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2628
2629 switch (type) {
2630 case SVM_EXITINTINFO_TYPE_NMI:
2631 svm->vcpu.arch.nmi_injected = true;
2632 break;
2633 case SVM_EXITINTINFO_TYPE_EXEPT:
2634 /* In case of software exception do not reinject an exception
2635 vector, but re-execute and instruction instead */
219b65dc
AG		 2636 if (is_nested(svm))
2637 break;
66fd3f7f 2638 if (kvm_exception_is_soft(vector))
9222be18
GN		 2639 break;
2640 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2641 u32 err = svm->vmcb->control.exit_int_info_err;
2642 kvm_queue_exception_e(&svm->vcpu, vector, err);
2643
2644 } else
2645 kvm_queue_exception(&svm->vcpu, vector);
2646 break;
2647 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2648 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2649 break;
2650 default:
2651 break;
2652 }
2653}
2654
80e31d4f
AK		 2655#ifdef CONFIG_X86_64
2656#define R "r"
2657#else
2658#define R "e"
2659#endif
2660
851ba692 2661static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2662{
a2fa3e9f 2663 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2664 u16 fs_selector;
2665 u16 gs_selector;
2666 u16 ldt_selector;
d9e368d6 2667
cd3ff653
JR		 2668 /*
2669 * A vmexit emulation is required before the vcpu can be executed
2670 * again.
2671 */
2672 if (unlikely(svm->nested.exit_required))
2673 return;
2674
5fdbf976
MT		 2675 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2676 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2677 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2678
e756fc62 2679 pre_svm_run(svm);
6aa8b732 2680
649d6864
JR		 2681 sync_lapic_to_cr8(vcpu);
2682
6aa8b732 2683 save_host_msrs(vcpu);
d6e88aec
AK		 2684 fs_selector = kvm_read_fs();
2685 gs_selector = kvm_read_gs();
2686 ldt_selector = kvm_read_ldt();
cda0ffdd 2687 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2688 /* required for live migration with NPT */
2689 if (npt_enabled)
2690 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2691
04d2cc77
AK		 2692 clgi();
2693
2694 local_irq_enable();
36241b8c 2695
6aa8b732 2696 asm volatile (
80e31d4f
AK		 2697 "push %%"R"bp; \n\t"
2698 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2699 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2700 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2701 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2702 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2703 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2704#ifdef CONFIG_X86_64
fb3f0f51
RR		 2705 "mov %c[r8](%[svm]), %%r8 \n\t"
2706 "mov %c[r9](%[svm]), %%r9 \n\t"
2707 "mov %c[r10](%[svm]), %%r10 \n\t"
2708 "mov %c[r11](%[svm]), %%r11 \n\t"
2709 "mov %c[r12](%[svm]), %%r12 \n\t"
2710 "mov %c[r13](%[svm]), %%r13 \n\t"
2711 "mov %c[r14](%[svm]), %%r14 \n\t"
2712 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2713#endif
2714
6aa8b732 2715 /* Enter guest mode */
80e31d4f
AK		 2716 "push %%"R"ax \n\t"
2717 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2718 __ex(SVM_VMLOAD) "\n\t"
2719 __ex(SVM_VMRUN) "\n\t"
2720 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2721 "pop %%"R"ax \n\t"
6aa8b732
AK		 2722
2723 /* Save guest registers, load host registers */
80e31d4f
AK		 2724 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2725 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2726 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2727 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2728 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2729 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2730#ifdef CONFIG_X86_64
fb3f0f51
RR		 2731 "mov %%r8, %c[r8](%[svm]) \n\t"
2732 "mov %%r9, %c[r9](%[svm]) \n\t"
2733 "mov %%r10, %c[r10](%[svm]) \n\t"
2734 "mov %%r11, %c[r11](%[svm]) \n\t"
2735 "mov %%r12, %c[r12](%[svm]) \n\t"
2736 "mov %%r13, %c[r13](%[svm]) \n\t"
2737 "mov %%r14, %c[r14](%[svm]) \n\t"
2738 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2739#endif
80e31d4f 2740 "pop %%"R"bp"
6aa8b732 2741 :
fb3f0f51 2742 : [svm]"a"(svm),
6aa8b732 2743 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2744 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2745 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2746 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2747 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2748 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2749 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2750#ifdef CONFIG_X86_64
ad312c7c
ZX		 2751 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2752 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2753 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2754 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2755 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2756 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2757 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2758 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2759#endif
54a08c04 2760 : "cc", "memory"
80e31d4f 2761 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2762#ifdef CONFIG_X86_64
54a08c04
LV		 2763 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2764#endif
2765 );
6aa8b732 2766
ad312c7c 2767 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2768 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2769 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2770 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2771
d6e88aec
AK		 2772 kvm_load_fs(fs_selector);
2773 kvm_load_gs(gs_selector);
2774 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2775 load_host_msrs(vcpu);
2776
2777 reload_tss(vcpu);
2778
56ba47dd
AK		 2779 local_irq_disable();
2780
2781 stgi();
2782
d7bf8221
JR		 2783 sync_cr8_to_lapic(vcpu);
2784
a2fa3e9f 2785 svm->next_rip = 0;
9222be18 2786
6de4f3ad
AK		 2787 if (npt_enabled) {
2788 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2789 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2790 }
6aa8b732
AK		 2791}
2792
80e31d4f
AK		 2793#undef R
2794
6aa8b732
AK		 2795static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2796{
a2fa3e9f
GH		 2797 struct vcpu_svm *svm = to_svm(vcpu);
2798
709ddebf
JR		 2799 if (npt_enabled) {
2800 svm->vmcb->control.nested_cr3 = root;
2801 force_new_asid(vcpu);
2802 return;
2803 }
2804
a2fa3e9f 2805 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2806 force_new_asid(vcpu);
2807}
2808
6aa8b732
AK		 2809static int is_disabled(void)
2810{
6031a61c
JR		 2811 u64 vm_cr;
2812
2813 rdmsrl(MSR_VM_CR, vm_cr);
2814 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2815 return 1;
2816
6aa8b732
AK		 2817 return 0;
2818}
2819
102d8325
IM		 2820static void
2821svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2822{
2823 /*
2824 * Patch in the VMMCALL instruction:
2825 */
2826 hypercall[0] = 0x0f;
2827 hypercall[1] = 0x01;
2828 hypercall[2] = 0xd9;
102d8325
IM		 2829}
2830
002c7f7c
YS		 2831static void svm_check_processor_compat(void *rtn)
2832{
2833 *(int *)rtn = 0;
2834}
2835
774ead3a
AK		 2836static bool svm_cpu_has_accelerated_tpr(void)
2837{
2838 return false;
2839}
2840
67253af5
SY		 2841static int get_npt_level(void)
2842{
2843#ifdef CONFIG_X86_64
2844 return PT64_ROOT_LEVEL;
2845#else
2846 return PT32E_ROOT_LEVEL;
2847#endif
2848}
2849
4b12f0de 2850static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2851{
2852 return 0;
2853}
2854
0e851880
SY		 2855static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2856{
2857}
2858
229456fc
MT		 2859static const struct trace_print_flags svm_exit_reasons_str[] = {
2860 { SVM_EXIT_READ_CR0, "read_cr0" },
2861 { SVM_EXIT_READ_CR3, "read_cr3" },
2862 { SVM_EXIT_READ_CR4, "read_cr4" },
2863 { SVM_EXIT_READ_CR8, "read_cr8" },
2864 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2865 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2866 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2867 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2868 { SVM_EXIT_READ_DR0, "read_dr0" },
2869 { SVM_EXIT_READ_DR1, "read_dr1" },
2870 { SVM_EXIT_READ_DR2, "read_dr2" },
2871 { SVM_EXIT_READ_DR3, "read_dr3" },
2872 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2873 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2874 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2875 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2876 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2877 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2878 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2879 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2880 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2881 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2882 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2883 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2884 { SVM_EXIT_INTR, "interrupt" },
2885 { SVM_EXIT_NMI, "nmi" },
2886 { SVM_EXIT_SMI, "smi" },
2887 { SVM_EXIT_INIT, "init" },
2888 { SVM_EXIT_VINTR, "vintr" },
2889 { SVM_EXIT_CPUID, "cpuid" },
2890 { SVM_EXIT_INVD, "invd" },
2891 { SVM_EXIT_HLT, "hlt" },
2892 { SVM_EXIT_INVLPG, "invlpg" },
2893 { SVM_EXIT_INVLPGA, "invlpga" },
2894 { SVM_EXIT_IOIO, "io" },
2895 { SVM_EXIT_MSR, "msr" },
2896 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2897 { SVM_EXIT_SHUTDOWN, "shutdown" },
2898 { SVM_EXIT_VMRUN, "vmrun" },
2899 { SVM_EXIT_VMMCALL, "hypercall" },
2900 { SVM_EXIT_VMLOAD, "vmload" },
2901 { SVM_EXIT_VMSAVE, "vmsave" },
2902 { SVM_EXIT_STGI, "stgi" },
2903 { SVM_EXIT_CLGI, "clgi" },
2904 { SVM_EXIT_SKINIT, "skinit" },
2905 { SVM_EXIT_WBINVD, "wbinvd" },
2906 { SVM_EXIT_MONITOR, "monitor" },
2907 { SVM_EXIT_MWAIT, "mwait" },
2908 { SVM_EXIT_NPF, "npf" },
2909 { -1, NULL }
2910};
2911
17cc3935 2912static int svm_get_lpage_level(void)
344f414f 2913{
17cc3935 2914 return PT_PDPE_LEVEL;
344f414f
JR		 2915}
2916
4e47c7a6
SY		 2917static bool svm_rdtscp_supported(void)
2918{
2919 return false;
2920}
2921
02daab21
AK		 2922static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2923{
2924 struct vcpu_svm *svm = to_svm(vcpu);
2925
2926 if (npt_enabled) {
2927 /* hack: npt requires active fpu at this time */
2928 vcpu->fpu_active = 1;
2929 return;
2930 }
2931
2932 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2933 svm->vmcb->save.cr0 |= X86_CR0_TS;
2934}
2935
cbdd1bea 2936static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2937 .cpu_has_kvm_support = has_svm,
2938 .disabled_by_bios = is_disabled,
2939 .hardware_setup = svm_hardware_setup,
2940 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2941 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2942 .hardware_enable = svm_hardware_enable,
2943 .hardware_disable = svm_hardware_disable,
774ead3a 2944 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2945
2946 .vcpu_create = svm_create_vcpu,
2947 .vcpu_free = svm_free_vcpu,
04d2cc77 2948 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2949
04d2cc77 2950 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2951 .vcpu_load = svm_vcpu_load,
2952 .vcpu_put = svm_vcpu_put,
2953
2954 .set_guest_debug = svm_guest_debug,
2955 .get_msr = svm_get_msr,
2956 .set_msr = svm_set_msr,
2957 .get_segment_base = svm_get_segment_base,
2958 .get_segment = svm_get_segment,
2959 .set_segment = svm_set_segment,
2e4d2653 2960 .get_cpl = svm_get_cpl,
1747fb71 2961 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 2962 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 2963 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2964 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2965 .set_cr3 = svm_set_cr3,
2966 .set_cr4 = svm_set_cr4,
2967 .set_efer = svm_set_efer,
2968 .get_idt = svm_get_idt,
2969 .set_idt = svm_set_idt,
2970 .get_gdt = svm_get_gdt,
2971 .set_gdt = svm_set_gdt,
2972 .get_dr = svm_get_dr,
2973 .set_dr = svm_set_dr,
6de4f3ad 2974 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2975 .get_rflags = svm_get_rflags,
2976 .set_rflags = svm_set_rflags,
02daab21 2977 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 2978
6aa8b732 2979 .tlb_flush = svm_flush_tlb,
6aa8b732 2980
6aa8b732 2981 .run = svm_vcpu_run,
04d2cc77 2982 .handle_exit = handle_exit,
6aa8b732 2983 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2984 .set_interrupt_shadow = svm_set_interrupt_shadow,
2985 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2986 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2987 .set_irq = svm_set_irq,
95ba8273 2988 .set_nmi = svm_inject_nmi,
298101da 2989 .queue_exception = svm_queue_exception,
78646121 2990 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 2991 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 2992 .get_nmi_mask = svm_get_nmi_mask,
2993 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 2994 .enable_nmi_window = enable_nmi_window,
2995 .enable_irq_window = enable_irq_window,
2996 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2997
2998 .set_tss_addr = svm_set_tss_addr,
67253af5 2999 .get_tdp_level = get_npt_level,
4b12f0de 3000 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3001
3002 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3003 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3004
3005 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3006
3007 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3008};
3009
3010static int __init svm_init(void)
3011{
cb498ea2 3012 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3013 THIS_MODULE);
6aa8b732
AK		 3014}
3015
3016static void __exit svm_exit(void)
3017{
cb498ea2 3018 kvm_exit();
6aa8b732
AK		 3019}
3020
3021module_init(svm_init)
3022module_exit(svm_exit)
Linux kernel - Deliverables
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