Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
6aa8b732 | 28 | |
e495606d | 29 | #include <asm/desc.h> |
6aa8b732 | 30 | |
63d1142f EH |
31 | #include <asm/virtext.h> |
32 | ||
4ecac3fd AK |
33 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
34 | ||
6aa8b732 AK |
35 | MODULE_AUTHOR("Qumranet"); |
36 | MODULE_LICENSE("GPL"); | |
37 | ||
38 | #define IOPM_ALLOC_ORDER 2 | |
39 | #define MSRPM_ALLOC_ORDER 1 | |
40 | ||
6aa8b732 AK |
41 | #define DR7_GD_MASK (1 << 13) |
42 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
43 | |
44 | #define SEG_TYPE_LDT 2 | |
45 | #define SEG_TYPE_BUSY_TSS16 3 | |
46 | ||
80b7706e JR |
47 | #define SVM_FEATURE_NPT (1 << 0) |
48 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 49 | #define SVM_FEATURE_SVML (1 << 2) |
80b7706e | 50 | |
24e09cbf JR |
51 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
52 | ||
c0725420 AG |
53 | /* Turn on to get debugging output*/ |
54 | /* #define NESTED_DEBUG */ | |
55 | ||
56 | #ifdef NESTED_DEBUG | |
57 | #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args) | |
58 | #else | |
59 | #define nsvm_printk(fmt, args...) do {} while(0) | |
60 | #endif | |
61 | ||
709ddebf JR |
62 | /* enable NPT for AMD64 and X86 with PAE */ |
63 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
64 | static bool npt_enabled = true; | |
65 | #else | |
e3da3acd | 66 | static bool npt_enabled = false; |
709ddebf | 67 | #endif |
6c7dac72 JR |
68 | static int npt = 1; |
69 | ||
70 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 71 | |
04d2cc77 | 72 | static void kvm_reput_irq(struct vcpu_svm *svm); |
44874f84 | 73 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
04d2cc77 | 74 | |
a2fa3e9f GH |
75 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
76 | { | |
fb3f0f51 | 77 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
78 | } |
79 | ||
4866d5e3 | 80 | static unsigned long iopm_base; |
6aa8b732 AK |
81 | |
82 | struct kvm_ldttss_desc { | |
83 | u16 limit0; | |
84 | u16 base0; | |
85 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
86 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
87 | u32 base3; | |
88 | u32 zero1; | |
89 | } __attribute__((packed)); | |
90 | ||
91 | struct svm_cpu_data { | |
92 | int cpu; | |
93 | ||
5008fdf5 AK |
94 | u64 asid_generation; |
95 | u32 max_asid; | |
96 | u32 next_asid; | |
6aa8b732 AK |
97 | struct kvm_ldttss_desc *tss_desc; |
98 | ||
99 | struct page *save_area; | |
100 | }; | |
101 | ||
102 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 103 | static uint32_t svm_features; |
6aa8b732 AK |
104 | |
105 | struct svm_init_data { | |
106 | int cpu; | |
107 | int r; | |
108 | }; | |
109 | ||
110 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
111 | ||
9d8f549d | 112 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
113 | #define MSRS_RANGE_SIZE 2048 |
114 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
115 | ||
116 | #define MAX_INST_SIZE 15 | |
117 | ||
80b7706e JR |
118 | static inline u32 svm_has(u32 feat) |
119 | { | |
120 | return svm_features & feat; | |
121 | } | |
122 | ||
6aa8b732 AK |
123 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
124 | { | |
ad312c7c ZX |
125 | int word_index = __ffs(vcpu->arch.irq_summary); |
126 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
127 | int irq = word_index * BITS_PER_LONG + bit_index; |
128 | ||
ad312c7c ZX |
129 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
130 | if (!vcpu->arch.irq_pending[word_index]) | |
131 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
132 | return irq; |
133 | } | |
134 | ||
135 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
136 | { | |
ad312c7c ZX |
137 | set_bit(irq, vcpu->arch.irq_pending); |
138 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
139 | } |
140 | ||
141 | static inline void clgi(void) | |
142 | { | |
4ecac3fd | 143 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
144 | } |
145 | ||
146 | static inline void stgi(void) | |
147 | { | |
4ecac3fd | 148 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
149 | } |
150 | ||
151 | static inline void invlpga(unsigned long addr, u32 asid) | |
152 | { | |
4ecac3fd | 153 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
154 | } |
155 | ||
156 | static inline unsigned long kvm_read_cr2(void) | |
157 | { | |
158 | unsigned long cr2; | |
159 | ||
160 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
161 | return cr2; | |
162 | } | |
163 | ||
164 | static inline void kvm_write_cr2(unsigned long val) | |
165 | { | |
166 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
167 | } | |
168 | ||
169 | static inline unsigned long read_dr6(void) | |
170 | { | |
171 | unsigned long dr6; | |
172 | ||
173 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
174 | return dr6; | |
175 | } | |
176 | ||
177 | static inline void write_dr6(unsigned long val) | |
178 | { | |
179 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
180 | } | |
181 | ||
182 | static inline unsigned long read_dr7(void) | |
183 | { | |
184 | unsigned long dr7; | |
185 | ||
186 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
187 | return dr7; | |
188 | } | |
189 | ||
190 | static inline void write_dr7(unsigned long val) | |
191 | { | |
192 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
193 | } | |
194 | ||
6aa8b732 AK |
195 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
196 | { | |
a2fa3e9f | 197 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
198 | } |
199 | ||
200 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
201 | { | |
202 | force_new_asid(vcpu); | |
203 | } | |
204 | ||
205 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
206 | { | |
709ddebf | 207 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 208 | efer &= ~EFER_LME; |
6aa8b732 | 209 | |
9962d032 | 210 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
ad312c7c | 211 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
212 | } |
213 | ||
298101da AK |
214 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
215 | bool has_error_code, u32 error_code) | |
216 | { | |
217 | struct vcpu_svm *svm = to_svm(vcpu); | |
218 | ||
219 | svm->vmcb->control.event_inj = nr | |
220 | | SVM_EVTINJ_VALID | |
221 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
222 | | SVM_EVTINJ_TYPE_EXEPT; | |
223 | svm->vmcb->control.event_inj_err = error_code; | |
224 | } | |
225 | ||
226 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
227 | { | |
228 | struct vcpu_svm *svm = to_svm(vcpu); | |
229 | ||
230 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
231 | } | |
232 | ||
6aa8b732 AK |
233 | static int is_external_interrupt(u32 info) |
234 | { | |
235 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
236 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
237 | } | |
238 | ||
239 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
240 | { | |
a2fa3e9f GH |
241 | struct vcpu_svm *svm = to_svm(vcpu); |
242 | ||
243 | if (!svm->next_rip) { | |
b8688d51 | 244 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
245 | return; |
246 | } | |
5fdbf976 MT |
247 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
248 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
249 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 250 | |
5fdbf976 | 251 | kvm_rip_write(vcpu, svm->next_rip); |
a2fa3e9f | 252 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 253 | |
ad312c7c | 254 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
255 | } |
256 | ||
257 | static int has_svm(void) | |
258 | { | |
63d1142f | 259 | const char *msg; |
6aa8b732 | 260 | |
63d1142f EH |
261 | if (!cpu_has_svm(&msg)) { |
262 | printk(KERN_INFO "has_svn: %s\n", msg); | |
6aa8b732 AK |
263 | return 0; |
264 | } | |
265 | ||
6aa8b732 AK |
266 | return 1; |
267 | } | |
268 | ||
269 | static void svm_hardware_disable(void *garbage) | |
270 | { | |
2c8dceeb | 271 | cpu_svm_disable(); |
6aa8b732 AK |
272 | } |
273 | ||
274 | static void svm_hardware_enable(void *garbage) | |
275 | { | |
276 | ||
277 | struct svm_cpu_data *svm_data; | |
278 | uint64_t efer; | |
6aa8b732 | 279 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
280 | struct desc_struct *gdt; |
281 | int me = raw_smp_processor_id(); | |
282 | ||
283 | if (!has_svm()) { | |
284 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
285 | return; | |
286 | } | |
287 | svm_data = per_cpu(svm_data, me); | |
288 | ||
289 | if (!svm_data) { | |
290 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
291 | me); | |
292 | return; | |
293 | } | |
294 | ||
295 | svm_data->asid_generation = 1; | |
296 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
297 | svm_data->next_asid = svm_data->max_asid + 1; | |
298 | ||
d77c26fc | 299 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
300 | gdt = (struct desc_struct *)gdt_descr.address; |
301 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
302 | ||
303 | rdmsrl(MSR_EFER, efer); | |
9962d032 | 304 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 AK |
305 | |
306 | wrmsrl(MSR_VM_HSAVE_PA, | |
307 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
308 | } | |
309 | ||
0da1db75 JR |
310 | static void svm_cpu_uninit(int cpu) |
311 | { | |
312 | struct svm_cpu_data *svm_data | |
313 | = per_cpu(svm_data, raw_smp_processor_id()); | |
314 | ||
315 | if (!svm_data) | |
316 | return; | |
317 | ||
318 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
319 | __free_page(svm_data->save_area); | |
320 | kfree(svm_data); | |
321 | } | |
322 | ||
6aa8b732 AK |
323 | static int svm_cpu_init(int cpu) |
324 | { | |
325 | struct svm_cpu_data *svm_data; | |
326 | int r; | |
327 | ||
328 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
329 | if (!svm_data) | |
330 | return -ENOMEM; | |
331 | svm_data->cpu = cpu; | |
332 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
333 | r = -ENOMEM; | |
334 | if (!svm_data->save_area) | |
335 | goto err_1; | |
336 | ||
337 | per_cpu(svm_data, cpu) = svm_data; | |
338 | ||
339 | return 0; | |
340 | ||
341 | err_1: | |
342 | kfree(svm_data); | |
343 | return r; | |
344 | ||
345 | } | |
346 | ||
bfc733a7 RR |
347 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
348 | int read, int write) | |
6aa8b732 AK |
349 | { |
350 | int i; | |
351 | ||
352 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
353 | if (msr >= msrpm_ranges[i] && | |
354 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
355 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
356 | msrpm_ranges[i]) * 2; | |
357 | ||
358 | u32 *base = msrpm + (msr_offset / 32); | |
359 | u32 msr_shift = msr_offset % 32; | |
360 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
361 | *base = (*base & ~(0x3 << msr_shift)) | | |
362 | (mask << msr_shift); | |
bfc733a7 | 363 | return; |
6aa8b732 AK |
364 | } |
365 | } | |
bfc733a7 | 366 | BUG(); |
6aa8b732 AK |
367 | } |
368 | ||
f65c229c JR |
369 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
370 | { | |
371 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
372 | ||
373 | #ifdef CONFIG_X86_64 | |
374 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
375 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
376 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
377 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
378 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
379 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
380 | #endif | |
381 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
382 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
383 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
384 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
385 | } | |
386 | ||
24e09cbf JR |
387 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
388 | { | |
389 | u32 *msrpm = svm->msrpm; | |
390 | ||
391 | svm->vmcb->control.lbr_ctl = 1; | |
392 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
393 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
394 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
395 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
396 | } | |
397 | ||
398 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
399 | { | |
400 | u32 *msrpm = svm->msrpm; | |
401 | ||
402 | svm->vmcb->control.lbr_ctl = 0; | |
403 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
404 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
405 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
406 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
407 | } | |
408 | ||
6aa8b732 AK |
409 | static __init int svm_hardware_setup(void) |
410 | { | |
411 | int cpu; | |
412 | struct page *iopm_pages; | |
f65c229c | 413 | void *iopm_va; |
6aa8b732 AK |
414 | int r; |
415 | ||
6aa8b732 AK |
416 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
417 | ||
418 | if (!iopm_pages) | |
419 | return -ENOMEM; | |
c8681339 AL |
420 | |
421 | iopm_va = page_address(iopm_pages); | |
422 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
423 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
424 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
425 | ||
50a37eb4 JR |
426 | if (boot_cpu_has(X86_FEATURE_NX)) |
427 | kvm_enable_efer_bits(EFER_NX); | |
428 | ||
6aa8b732 AK |
429 | for_each_online_cpu(cpu) { |
430 | r = svm_cpu_init(cpu); | |
431 | if (r) | |
f65c229c | 432 | goto err; |
6aa8b732 | 433 | } |
33bd6a0b JR |
434 | |
435 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
436 | ||
e3da3acd JR |
437 | if (!svm_has(SVM_FEATURE_NPT)) |
438 | npt_enabled = false; | |
439 | ||
6c7dac72 JR |
440 | if (npt_enabled && !npt) { |
441 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
442 | npt_enabled = false; | |
443 | } | |
444 | ||
18552672 | 445 | if (npt_enabled) { |
e3da3acd | 446 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 447 | kvm_enable_tdp(); |
5f4cb662 JR |
448 | } else |
449 | kvm_disable_tdp(); | |
e3da3acd | 450 | |
6aa8b732 AK |
451 | return 0; |
452 | ||
f65c229c | 453 | err: |
6aa8b732 AK |
454 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
455 | iopm_base = 0; | |
456 | return r; | |
457 | } | |
458 | ||
459 | static __exit void svm_hardware_unsetup(void) | |
460 | { | |
0da1db75 JR |
461 | int cpu; |
462 | ||
463 | for_each_online_cpu(cpu) | |
464 | svm_cpu_uninit(cpu); | |
465 | ||
6aa8b732 | 466 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 467 | iopm_base = 0; |
6aa8b732 AK |
468 | } |
469 | ||
470 | static void init_seg(struct vmcb_seg *seg) | |
471 | { | |
472 | seg->selector = 0; | |
473 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
474 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
475 | seg->limit = 0xffff; | |
476 | seg->base = 0; | |
477 | } | |
478 | ||
479 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
480 | { | |
481 | seg->selector = 0; | |
482 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
483 | seg->limit = 0xffff; | |
484 | seg->base = 0; | |
485 | } | |
486 | ||
e6101a96 | 487 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 488 | { |
e6101a96 JR |
489 | struct vmcb_control_area *control = &svm->vmcb->control; |
490 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
491 | |
492 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
493 | INTERCEPT_CR3_MASK | | |
649d6864 | 494 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
495 | |
496 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
497 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
498 | INTERCEPT_CR4_MASK | |
499 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
500 | |
501 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
502 | INTERCEPT_DR1_MASK | | |
503 | INTERCEPT_DR2_MASK | | |
504 | INTERCEPT_DR3_MASK; | |
505 | ||
506 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
507 | INTERCEPT_DR1_MASK | | |
508 | INTERCEPT_DR2_MASK | | |
509 | INTERCEPT_DR3_MASK | | |
510 | INTERCEPT_DR5_MASK | | |
511 | INTERCEPT_DR7_MASK; | |
512 | ||
7aa81cc0 | 513 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
514 | (1 << UD_VECTOR) | |
515 | (1 << MC_VECTOR); | |
6aa8b732 AK |
516 | |
517 | ||
518 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
519 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 520 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 521 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 522 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 523 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 524 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
525 | (1ULL << INTERCEPT_INVLPGA) | |
526 | (1ULL << INTERCEPT_IOIO_PROT) | | |
527 | (1ULL << INTERCEPT_MSR_PROT) | | |
528 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 529 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
530 | (1ULL << INTERCEPT_VMRUN) | |
531 | (1ULL << INTERCEPT_VMMCALL) | | |
532 | (1ULL << INTERCEPT_VMLOAD) | | |
533 | (1ULL << INTERCEPT_VMSAVE) | | |
534 | (1ULL << INTERCEPT_STGI) | | |
535 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 536 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 537 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
538 | (1ULL << INTERCEPT_MONITOR) | |
539 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
540 | |
541 | control->iopm_base_pa = iopm_base; | |
f65c229c | 542 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 543 | control->tsc_offset = 0; |
6aa8b732 AK |
544 | control->int_ctl = V_INTR_MASKING_MASK; |
545 | ||
546 | init_seg(&save->es); | |
547 | init_seg(&save->ss); | |
548 | init_seg(&save->ds); | |
549 | init_seg(&save->fs); | |
550 | init_seg(&save->gs); | |
551 | ||
552 | save->cs.selector = 0xf000; | |
553 | /* Executable/Readable Code Segment */ | |
554 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
555 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
556 | save->cs.limit = 0xffff; | |
d92899a0 AK |
557 | /* |
558 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
559 | * be consistent with it. | |
560 | * | |
561 | * Replace when we have real mode working for vmx. | |
562 | */ | |
563 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
564 | |
565 | save->gdtr.limit = 0xffff; | |
566 | save->idtr.limit = 0xffff; | |
567 | ||
568 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
569 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
570 | ||
9962d032 | 571 | save->efer = EFER_SVME; |
d77c26fc | 572 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
573 | save->dr7 = 0x400; |
574 | save->rflags = 2; | |
575 | save->rip = 0x0000fff0; | |
5fdbf976 | 576 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 AK |
577 | |
578 | /* | |
579 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
580 | * cache by default. the orderly way is to enable cache in bios. | |
581 | */ | |
707d92fa | 582 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 583 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 584 | /* rdx = ?? */ |
709ddebf JR |
585 | |
586 | if (npt_enabled) { | |
587 | /* Setup VMCB for Nested Paging */ | |
588 | control->nested_ctl = 1; | |
a7052897 MT |
589 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
590 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf JR |
591 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
592 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
593 | INTERCEPT_CR3_MASK); | |
594 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
595 | INTERCEPT_CR3_MASK); | |
596 | save->g_pat = 0x0007040600070406ULL; | |
597 | /* enable caching because the QEMU Bios doesn't enable it */ | |
598 | save->cr0 = X86_CR0_ET; | |
599 | save->cr3 = 0; | |
600 | save->cr4 = 0; | |
601 | } | |
a79d2f18 | 602 | force_new_asid(&svm->vcpu); |
6aa8b732 AK |
603 | } |
604 | ||
e00c8cf2 | 605 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
606 | { |
607 | struct vcpu_svm *svm = to_svm(vcpu); | |
608 | ||
e6101a96 | 609 | init_vmcb(svm); |
70433389 AK |
610 | |
611 | if (vcpu->vcpu_id != 0) { | |
5fdbf976 | 612 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
613 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
614 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 615 | } |
5fdbf976 MT |
616 | vcpu->arch.regs_avail = ~0; |
617 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
618 | |
619 | return 0; | |
04d2cc77 AK |
620 | } |
621 | ||
fb3f0f51 | 622 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 623 | { |
a2fa3e9f | 624 | struct vcpu_svm *svm; |
6aa8b732 | 625 | struct page *page; |
f65c229c | 626 | struct page *msrpm_pages; |
fb3f0f51 | 627 | int err; |
6aa8b732 | 628 | |
c16f862d | 629 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
630 | if (!svm) { |
631 | err = -ENOMEM; | |
632 | goto out; | |
633 | } | |
634 | ||
635 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
636 | if (err) | |
637 | goto free_svm; | |
638 | ||
6aa8b732 | 639 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
640 | if (!page) { |
641 | err = -ENOMEM; | |
642 | goto uninit; | |
643 | } | |
6aa8b732 | 644 | |
f65c229c JR |
645 | err = -ENOMEM; |
646 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
647 | if (!msrpm_pages) | |
648 | goto uninit; | |
649 | svm->msrpm = page_address(msrpm_pages); | |
650 | svm_vcpu_init_msrpm(svm->msrpm); | |
651 | ||
a2fa3e9f GH |
652 | svm->vmcb = page_address(page); |
653 | clear_page(svm->vmcb); | |
654 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
655 | svm->asid_generation = 0; | |
656 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 657 | init_vmcb(svm); |
a2fa3e9f | 658 | |
fb3f0f51 RR |
659 | fx_init(&svm->vcpu); |
660 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 661 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 662 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 663 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 664 | |
fb3f0f51 | 665 | return &svm->vcpu; |
36241b8c | 666 | |
fb3f0f51 RR |
667 | uninit: |
668 | kvm_vcpu_uninit(&svm->vcpu); | |
669 | free_svm: | |
a4770347 | 670 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
671 | out: |
672 | return ERR_PTR(err); | |
6aa8b732 AK |
673 | } |
674 | ||
675 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
676 | { | |
a2fa3e9f GH |
677 | struct vcpu_svm *svm = to_svm(vcpu); |
678 | ||
fb3f0f51 | 679 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 680 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 681 | kvm_vcpu_uninit(vcpu); |
a4770347 | 682 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
683 | } |
684 | ||
15ad7146 | 685 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 686 | { |
a2fa3e9f | 687 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 688 | int i; |
0cc5064d | 689 | |
0cc5064d AK |
690 | if (unlikely(cpu != vcpu->cpu)) { |
691 | u64 tsc_this, delta; | |
692 | ||
693 | /* | |
694 | * Make sure that the guest sees a monotonically | |
695 | * increasing TSC. | |
696 | */ | |
697 | rdtscll(tsc_this); | |
ad312c7c | 698 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 699 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 700 | vcpu->cpu = cpu; |
2f599714 | 701 | kvm_migrate_timers(vcpu); |
0cc5064d | 702 | } |
94dfbdb3 AL |
703 | |
704 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 705 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
706 | } |
707 | ||
708 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
709 | { | |
a2fa3e9f | 710 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
711 | int i; |
712 | ||
e1beb1d3 | 713 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 714 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 715 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 716 | |
ad312c7c | 717 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
718 | } |
719 | ||
6aa8b732 AK |
720 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
721 | { | |
a2fa3e9f | 722 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
723 | } |
724 | ||
725 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
726 | { | |
a2fa3e9f | 727 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
728 | } |
729 | ||
f0b85051 AG |
730 | static void svm_set_vintr(struct vcpu_svm *svm) |
731 | { | |
732 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
733 | } | |
734 | ||
735 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
736 | { | |
737 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
738 | } | |
739 | ||
6aa8b732 AK |
740 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
741 | { | |
a2fa3e9f | 742 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
743 | |
744 | switch (seg) { | |
745 | case VCPU_SREG_CS: return &save->cs; | |
746 | case VCPU_SREG_DS: return &save->ds; | |
747 | case VCPU_SREG_ES: return &save->es; | |
748 | case VCPU_SREG_FS: return &save->fs; | |
749 | case VCPU_SREG_GS: return &save->gs; | |
750 | case VCPU_SREG_SS: return &save->ss; | |
751 | case VCPU_SREG_TR: return &save->tr; | |
752 | case VCPU_SREG_LDTR: return &save->ldtr; | |
753 | } | |
754 | BUG(); | |
8b6d44c7 | 755 | return NULL; |
6aa8b732 AK |
756 | } |
757 | ||
758 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
759 | { | |
760 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
761 | ||
762 | return s->base; | |
763 | } | |
764 | ||
765 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
766 | struct kvm_segment *var, int seg) | |
767 | { | |
768 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
769 | ||
770 | var->base = s->base; | |
771 | var->limit = s->limit; | |
772 | var->selector = s->selector; | |
773 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
774 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
775 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
776 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
777 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
778 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
779 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
780 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc AS |
781 | |
782 | /* | |
783 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
784 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
785 | * Intel's VMENTRY has a check on the 'G' bit. | |
786 | */ | |
787 | if (seg == VCPU_SREG_CS) | |
788 | var->g = s->limit > 0xfffff; | |
789 | ||
c0d09828 AS |
790 | /* |
791 | * Work around a bug where the busy flag in the tr selector | |
792 | * isn't exposed | |
793 | */ | |
794 | if (seg == VCPU_SREG_TR) | |
795 | var->type |= 0x2; | |
796 | ||
6aa8b732 AK |
797 | var->unusable = !var->present; |
798 | } | |
799 | ||
2e4d2653 IE |
800 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
801 | { | |
802 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
803 | ||
804 | return save->cpl; | |
805 | } | |
806 | ||
6aa8b732 AK |
807 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
808 | { | |
a2fa3e9f GH |
809 | struct vcpu_svm *svm = to_svm(vcpu); |
810 | ||
811 | dt->limit = svm->vmcb->save.idtr.limit; | |
812 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
813 | } |
814 | ||
815 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
816 | { | |
a2fa3e9f GH |
817 | struct vcpu_svm *svm = to_svm(vcpu); |
818 | ||
819 | svm->vmcb->save.idtr.limit = dt->limit; | |
820 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
821 | } |
822 | ||
823 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
824 | { | |
a2fa3e9f GH |
825 | struct vcpu_svm *svm = to_svm(vcpu); |
826 | ||
827 | dt->limit = svm->vmcb->save.gdtr.limit; | |
828 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
829 | } |
830 | ||
831 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
832 | { | |
a2fa3e9f GH |
833 | struct vcpu_svm *svm = to_svm(vcpu); |
834 | ||
835 | svm->vmcb->save.gdtr.limit = dt->limit; | |
836 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
837 | } |
838 | ||
25c4c276 | 839 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
840 | { |
841 | } | |
842 | ||
6aa8b732 AK |
843 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
844 | { | |
a2fa3e9f GH |
845 | struct vcpu_svm *svm = to_svm(vcpu); |
846 | ||
05b3e0c2 | 847 | #ifdef CONFIG_X86_64 |
ad312c7c | 848 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 849 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 850 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 851 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
852 | } |
853 | ||
d77c26fc | 854 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 855 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 856 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
857 | } |
858 | } | |
859 | #endif | |
709ddebf JR |
860 | if (npt_enabled) |
861 | goto set; | |
862 | ||
ad312c7c | 863 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 864 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
865 | vcpu->fpu_active = 1; |
866 | } | |
867 | ||
ad312c7c | 868 | vcpu->arch.cr0 = cr0; |
707d92fa | 869 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
870 | if (!vcpu->fpu_active) { |
871 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 872 | cr0 |= X86_CR0_TS; |
6b390b63 | 873 | } |
709ddebf JR |
874 | set: |
875 | /* | |
876 | * re-enable caching here because the QEMU bios | |
877 | * does not do it - this results in some delay at | |
878 | * reboot | |
879 | */ | |
880 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 881 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
882 | } |
883 | ||
884 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
885 | { | |
6394b649 | 886 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
887 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
888 | ||
889 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
890 | force_new_asid(vcpu); | |
6394b649 | 891 | |
ec077263 JR |
892 | vcpu->arch.cr4 = cr4; |
893 | if (!npt_enabled) | |
894 | cr4 |= X86_CR4_PAE; | |
6394b649 | 895 | cr4 |= host_cr4_mce; |
ec077263 | 896 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
897 | } |
898 | ||
899 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
900 | struct kvm_segment *var, int seg) | |
901 | { | |
a2fa3e9f | 902 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
903 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
904 | ||
905 | s->base = var->base; | |
906 | s->limit = var->limit; | |
907 | s->selector = var->selector; | |
908 | if (var->unusable) | |
909 | s->attrib = 0; | |
910 | else { | |
911 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
912 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
913 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
914 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
915 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
916 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
917 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
918 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
919 | } | |
920 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
921 | svm->vmcb->save.cpl |
922 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
923 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
924 | ||
925 | } | |
926 | ||
6aa8b732 AK |
927 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) |
928 | { | |
929 | return -EOPNOTSUPP; | |
930 | } | |
931 | ||
2a8067f1 ED |
932 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
933 | { | |
934 | struct vcpu_svm *svm = to_svm(vcpu); | |
935 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
936 | ||
937 | if (is_external_interrupt(exit_int_info)) | |
938 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
939 | return -1; | |
940 | } | |
941 | ||
6aa8b732 AK |
942 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
943 | { | |
94dfbdb3 | 944 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 945 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 946 | #endif |
6aa8b732 AK |
947 | } |
948 | ||
949 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
950 | { | |
94dfbdb3 | 951 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 952 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 953 | #endif |
6aa8b732 AK |
954 | } |
955 | ||
e756fc62 | 956 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
957 | { |
958 | if (svm_data->next_asid > svm_data->max_asid) { | |
959 | ++svm_data->asid_generation; | |
960 | svm_data->next_asid = 1; | |
a2fa3e9f | 961 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
962 | } |
963 | ||
e756fc62 | 964 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
965 | svm->asid_generation = svm_data->asid_generation; |
966 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
967 | } |
968 | ||
6aa8b732 AK |
969 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
970 | { | |
af9ca2d7 JR |
971 | unsigned long val = to_svm(vcpu)->db_regs[dr]; |
972 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); | |
973 | return val; | |
6aa8b732 AK |
974 | } |
975 | ||
976 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
977 | int *exception) | |
978 | { | |
a2fa3e9f GH |
979 | struct vcpu_svm *svm = to_svm(vcpu); |
980 | ||
6aa8b732 AK |
981 | *exception = 0; |
982 | ||
a2fa3e9f GH |
983 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
984 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
985 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
986 | *exception = DB_VECTOR; |
987 | return; | |
988 | } | |
989 | ||
990 | switch (dr) { | |
991 | case 0 ... 3: | |
a2fa3e9f | 992 | svm->db_regs[dr] = value; |
6aa8b732 AK |
993 | return; |
994 | case 4 ... 5: | |
ad312c7c | 995 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
996 | *exception = UD_VECTOR; |
997 | return; | |
998 | } | |
999 | case 7: { | |
1000 | if (value & ~((1ULL << 32) - 1)) { | |
1001 | *exception = GP_VECTOR; | |
1002 | return; | |
1003 | } | |
a2fa3e9f | 1004 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
1005 | return; |
1006 | } | |
1007 | default: | |
1008 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 1009 | __func__, dr); |
6aa8b732 AK |
1010 | *exception = UD_VECTOR; |
1011 | return; | |
1012 | } | |
1013 | } | |
1014 | ||
e756fc62 | 1015 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1016 | { |
a2fa3e9f | 1017 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 1018 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
1019 | u64 fault_address; |
1020 | u32 error_code; | |
577bdc49 | 1021 | bool event_injection = false; |
6aa8b732 | 1022 | |
85f455f7 | 1023 | if (!irqchip_in_kernel(kvm) && |
577bdc49 AK |
1024 | is_external_interrupt(exit_int_info)) { |
1025 | event_injection = true; | |
e756fc62 | 1026 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
577bdc49 | 1027 | } |
6aa8b732 | 1028 | |
a2fa3e9f GH |
1029 | fault_address = svm->vmcb->control.exit_info_2; |
1030 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 JR |
1031 | |
1032 | if (!npt_enabled) | |
1033 | KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code, | |
1034 | (u32)fault_address, (u32)(fault_address >> 32), | |
1035 | handler); | |
d2ebb410 JR |
1036 | else |
1037 | KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code, | |
1038 | (u32)fault_address, (u32)(fault_address >> 32), | |
1039 | handler); | |
44874f84 JR |
1040 | /* |
1041 | * FIXME: Tis shouldn't be necessary here, but there is a flush | |
1042 | * missing in the MMU code. Until we find this bug, flush the | |
1043 | * complete TLB here on an NPF | |
1044 | */ | |
1045 | if (npt_enabled) | |
1046 | svm_flush_tlb(&svm->vcpu); | |
af9ca2d7 | 1047 | |
48d15039 | 1048 | if (!npt_enabled && event_injection) |
577bdc49 | 1049 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); |
3067714c | 1050 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1051 | } |
1052 | ||
7aa81cc0 AL |
1053 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1054 | { | |
1055 | int er; | |
1056 | ||
571008da | 1057 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1058 | if (er != EMULATE_DONE) |
7ee5d940 | 1059 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1060 | return 1; |
1061 | } | |
1062 | ||
e756fc62 | 1063 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1064 | { |
a2fa3e9f | 1065 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1066 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1067 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1068 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1069 | |
1070 | return 1; | |
7807fa6c AL |
1071 | } |
1072 | ||
53371b50 JR |
1073 | static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1074 | { | |
1075 | /* | |
1076 | * On an #MC intercept the MCE handler is not called automatically in | |
1077 | * the host. So do it by hand here. | |
1078 | */ | |
1079 | asm volatile ( | |
1080 | "int $0x12\n"); | |
1081 | /* not sure if we ever come back to this point */ | |
1082 | ||
1083 | return 1; | |
1084 | } | |
1085 | ||
e756fc62 | 1086 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1087 | { |
1088 | /* | |
1089 | * VMCB is undefined after a SHUTDOWN intercept | |
1090 | * so reinitialize it. | |
1091 | */ | |
a2fa3e9f | 1092 | clear_page(svm->vmcb); |
e6101a96 | 1093 | init_vmcb(svm); |
46fe4ddd JR |
1094 | |
1095 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1096 | return 0; | |
1097 | } | |
1098 | ||
e756fc62 | 1099 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1100 | { |
d77c26fc | 1101 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1102 | int size, down, in, string, rep; |
1103 | unsigned port; | |
6aa8b732 | 1104 | |
e756fc62 | 1105 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1106 | |
a2fa3e9f | 1107 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1108 | |
e70669ab LV |
1109 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1110 | ||
1111 | if (string) { | |
3427318f LV |
1112 | if (emulate_instruction(&svm->vcpu, |
1113 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1114 | return 0; |
1115 | return 1; | |
1116 | } | |
1117 | ||
039576c0 AK |
1118 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1119 | port = io_info >> 16; | |
1120 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1121 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1122 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1123 | |
e93f36bc | 1124 | skip_emulated_instruction(&svm->vcpu); |
3090dd73 | 1125 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1126 | } |
1127 | ||
c47f098d JR |
1128 | static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1129 | { | |
af9ca2d7 | 1130 | KVMTRACE_0D(NMI, &svm->vcpu, handler); |
c47f098d JR |
1131 | return 1; |
1132 | } | |
1133 | ||
a0698055 JR |
1134 | static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1135 | { | |
1136 | ++svm->vcpu.stat.irq_exits; | |
af9ca2d7 | 1137 | KVMTRACE_0D(INTR, &svm->vcpu, handler); |
a0698055 JR |
1138 | return 1; |
1139 | } | |
1140 | ||
e756fc62 | 1141 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1142 | { |
1143 | return 1; | |
1144 | } | |
1145 | ||
e756fc62 | 1146 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1147 | { |
5fdbf976 | 1148 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1149 | skip_emulated_instruction(&svm->vcpu); |
1150 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1151 | } |
1152 | ||
e756fc62 | 1153 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1154 | { |
5fdbf976 | 1155 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1156 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1157 | kvm_emulate_hypercall(&svm->vcpu); |
1158 | return 1; | |
02e235bc AK |
1159 | } |
1160 | ||
c0725420 AG |
1161 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1162 | { | |
1163 | if (!(svm->vcpu.arch.shadow_efer & EFER_SVME) | |
1164 | || !is_paging(&svm->vcpu)) { | |
1165 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1166 | return 1; | |
1167 | } | |
1168 | ||
1169 | if (svm->vmcb->save.cpl) { | |
1170 | kvm_inject_gp(&svm->vcpu, 0); | |
1171 | return 1; | |
1172 | } | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa) | |
1178 | { | |
1179 | struct page *page; | |
1180 | ||
1181 | down_read(¤t->mm->mmap_sem); | |
1182 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); | |
1183 | up_read(¤t->mm->mmap_sem); | |
1184 | ||
1185 | if (is_error_page(page)) { | |
1186 | printk(KERN_INFO "%s: could not find page at 0x%llx\n", | |
1187 | __func__, gpa); | |
1188 | kvm_release_page_clean(page); | |
1189 | kvm_inject_gp(&svm->vcpu, 0); | |
1190 | return NULL; | |
1191 | } | |
1192 | return page; | |
1193 | } | |
1194 | ||
1195 | static int nested_svm_do(struct vcpu_svm *svm, | |
1196 | u64 arg1_gpa, u64 arg2_gpa, void *opaque, | |
1197 | int (*handler)(struct vcpu_svm *svm, | |
1198 | void *arg1, | |
1199 | void *arg2, | |
1200 | void *opaque)) | |
1201 | { | |
1202 | struct page *arg1_page; | |
1203 | struct page *arg2_page = NULL; | |
1204 | void *arg1; | |
1205 | void *arg2 = NULL; | |
1206 | int retval; | |
1207 | ||
1208 | arg1_page = nested_svm_get_page(svm, arg1_gpa); | |
1209 | if(arg1_page == NULL) | |
1210 | return 1; | |
1211 | ||
1212 | if (arg2_gpa) { | |
1213 | arg2_page = nested_svm_get_page(svm, arg2_gpa); | |
1214 | if(arg2_page == NULL) { | |
1215 | kvm_release_page_clean(arg1_page); | |
1216 | return 1; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | arg1 = kmap_atomic(arg1_page, KM_USER0); | |
1221 | if (arg2_gpa) | |
1222 | arg2 = kmap_atomic(arg2_page, KM_USER1); | |
1223 | ||
1224 | retval = handler(svm, arg1, arg2, opaque); | |
1225 | ||
1226 | kunmap_atomic(arg1, KM_USER0); | |
1227 | if (arg2_gpa) | |
1228 | kunmap_atomic(arg2, KM_USER1); | |
1229 | ||
1230 | kvm_release_page_dirty(arg1_page); | |
1231 | if (arg2_gpa) | |
1232 | kvm_release_page_dirty(arg2_page); | |
1233 | ||
1234 | return retval; | |
1235 | } | |
1236 | ||
e756fc62 RR |
1237 | static int invalid_op_interception(struct vcpu_svm *svm, |
1238 | struct kvm_run *kvm_run) | |
6aa8b732 | 1239 | { |
7ee5d940 | 1240 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1241 | return 1; |
1242 | } | |
1243 | ||
e756fc62 RR |
1244 | static int task_switch_interception(struct vcpu_svm *svm, |
1245 | struct kvm_run *kvm_run) | |
6aa8b732 | 1246 | { |
37817f29 IE |
1247 | u16 tss_selector; |
1248 | ||
1249 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
1250 | if (svm->vmcb->control.exit_info_2 & | |
1251 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
1252 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1253 | TASK_SWITCH_IRET); | |
1254 | if (svm->vmcb->control.exit_info_2 & | |
1255 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1256 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1257 | TASK_SWITCH_JMP); | |
1258 | return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL); | |
6aa8b732 AK |
1259 | } |
1260 | ||
e756fc62 | 1261 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1262 | { |
5fdbf976 | 1263 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1264 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1265 | return 1; |
6aa8b732 AK |
1266 | } |
1267 | ||
a7052897 MT |
1268 | static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1269 | { | |
1270 | if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE) | |
1271 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); | |
1272 | return 1; | |
1273 | } | |
1274 | ||
e756fc62 RR |
1275 | static int emulate_on_interception(struct vcpu_svm *svm, |
1276 | struct kvm_run *kvm_run) | |
6aa8b732 | 1277 | { |
3427318f | 1278 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1279 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1280 | return 1; |
1281 | } | |
1282 | ||
1d075434 JR |
1283 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1284 | { | |
1285 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1286 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1287 | return 1; | |
1288 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1289 | return 0; | |
1290 | } | |
1291 | ||
6aa8b732 AK |
1292 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1293 | { | |
a2fa3e9f GH |
1294 | struct vcpu_svm *svm = to_svm(vcpu); |
1295 | ||
6aa8b732 | 1296 | switch (ecx) { |
6aa8b732 AK |
1297 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1298 | u64 tsc; | |
1299 | ||
1300 | rdtscll(tsc); | |
a2fa3e9f | 1301 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1302 | break; |
1303 | } | |
0e859cac | 1304 | case MSR_K6_STAR: |
a2fa3e9f | 1305 | *data = svm->vmcb->save.star; |
6aa8b732 | 1306 | break; |
0e859cac | 1307 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1308 | case MSR_LSTAR: |
a2fa3e9f | 1309 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1310 | break; |
1311 | case MSR_CSTAR: | |
a2fa3e9f | 1312 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1313 | break; |
1314 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1315 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1316 | break; |
1317 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1318 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1319 | break; |
1320 | #endif | |
1321 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1322 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1323 | break; |
1324 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1325 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1326 | break; |
1327 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1328 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1329 | break; |
a2938c80 JR |
1330 | /* Nobody will change the following 5 values in the VMCB so |
1331 | we can safely return them on rdmsr. They will always be 0 | |
1332 | until LBRV is implemented. */ | |
1333 | case MSR_IA32_DEBUGCTLMSR: | |
1334 | *data = svm->vmcb->save.dbgctl; | |
1335 | break; | |
1336 | case MSR_IA32_LASTBRANCHFROMIP: | |
1337 | *data = svm->vmcb->save.br_from; | |
1338 | break; | |
1339 | case MSR_IA32_LASTBRANCHTOIP: | |
1340 | *data = svm->vmcb->save.br_to; | |
1341 | break; | |
1342 | case MSR_IA32_LASTINTFROMIP: | |
1343 | *data = svm->vmcb->save.last_excp_from; | |
1344 | break; | |
1345 | case MSR_IA32_LASTINTTOIP: | |
1346 | *data = svm->vmcb->save.last_excp_to; | |
1347 | break; | |
6aa8b732 | 1348 | default: |
3bab1f5d | 1349 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1350 | } |
1351 | return 0; | |
1352 | } | |
1353 | ||
e756fc62 | 1354 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1355 | { |
ad312c7c | 1356 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1357 | u64 data; |
1358 | ||
e756fc62 | 1359 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1360 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1361 | else { |
af9ca2d7 JR |
1362 | KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data, |
1363 | (u32)(data >> 32), handler); | |
1364 | ||
5fdbf976 | 1365 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 1366 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 1367 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1368 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1369 | } |
1370 | return 1; | |
1371 | } | |
1372 | ||
1373 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1374 | { | |
a2fa3e9f GH |
1375 | struct vcpu_svm *svm = to_svm(vcpu); |
1376 | ||
6aa8b732 | 1377 | switch (ecx) { |
6aa8b732 AK |
1378 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1379 | u64 tsc; | |
1380 | ||
1381 | rdtscll(tsc); | |
a2fa3e9f | 1382 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1383 | break; |
1384 | } | |
0e859cac | 1385 | case MSR_K6_STAR: |
a2fa3e9f | 1386 | svm->vmcb->save.star = data; |
6aa8b732 | 1387 | break; |
49b14f24 | 1388 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1389 | case MSR_LSTAR: |
a2fa3e9f | 1390 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1391 | break; |
1392 | case MSR_CSTAR: | |
a2fa3e9f | 1393 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1394 | break; |
1395 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1396 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1397 | break; |
1398 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1399 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1400 | break; |
1401 | #endif | |
1402 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1403 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1404 | break; |
1405 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1406 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1407 | break; |
1408 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1409 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1410 | break; |
a2938c80 | 1411 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1412 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1413 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1414 | __func__, data); |
24e09cbf JR |
1415 | break; |
1416 | } | |
1417 | if (data & DEBUGCTL_RESERVED_BITS) | |
1418 | return 1; | |
1419 | ||
1420 | svm->vmcb->save.dbgctl = data; | |
1421 | if (data & (1ULL<<0)) | |
1422 | svm_enable_lbrv(svm); | |
1423 | else | |
1424 | svm_disable_lbrv(svm); | |
a2938c80 | 1425 | break; |
62b9abaa JR |
1426 | case MSR_K7_EVNTSEL0: |
1427 | case MSR_K7_EVNTSEL1: | |
1428 | case MSR_K7_EVNTSEL2: | |
1429 | case MSR_K7_EVNTSEL3: | |
14ae51b6 CL |
1430 | case MSR_K7_PERFCTR0: |
1431 | case MSR_K7_PERFCTR1: | |
1432 | case MSR_K7_PERFCTR2: | |
1433 | case MSR_K7_PERFCTR3: | |
62b9abaa | 1434 | /* |
14ae51b6 CL |
1435 | * Just discard all writes to the performance counters; this |
1436 | * should keep both older linux and windows 64-bit guests | |
1437 | * happy | |
62b9abaa | 1438 | */ |
14ae51b6 CL |
1439 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data); |
1440 | ||
62b9abaa | 1441 | break; |
6aa8b732 | 1442 | default: |
3bab1f5d | 1443 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1444 | } |
1445 | return 0; | |
1446 | } | |
1447 | ||
e756fc62 | 1448 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1449 | { |
ad312c7c | 1450 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 1451 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 1452 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 JR |
1453 | |
1454 | KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32), | |
1455 | handler); | |
1456 | ||
5fdbf976 | 1457 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 1458 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1459 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1460 | else |
e756fc62 | 1461 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1462 | return 1; |
1463 | } | |
1464 | ||
e756fc62 | 1465 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1466 | { |
e756fc62 RR |
1467 | if (svm->vmcb->control.exit_info_1) |
1468 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1469 | else |
e756fc62 | 1470 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1471 | } |
1472 | ||
e756fc62 | 1473 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1474 | struct kvm_run *kvm_run) |
1475 | { | |
af9ca2d7 JR |
1476 | KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler); |
1477 | ||
f0b85051 | 1478 | svm_clear_vintr(svm); |
85f455f7 | 1479 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
1480 | /* |
1481 | * If the user space waits to inject interrupts, exit as soon as | |
1482 | * possible | |
1483 | */ | |
1484 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1485 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1486 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1487 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | return 1; | |
1492 | } | |
1493 | ||
e756fc62 | 1494 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1495 | struct kvm_run *kvm_run) = { |
1496 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1497 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1498 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1499 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1500 | /* for now: */ |
1501 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1502 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1503 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1504 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1505 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1506 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1507 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1508 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1509 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1510 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1511 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1512 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1513 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1514 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1515 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1516 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1517 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 1518 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 1519 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 1520 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
1521 | [SVM_EXIT_SMI] = nop_on_interception, |
1522 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1523 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1524 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1525 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1526 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 | 1527 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 1528 | [SVM_EXIT_INVLPG] = invlpg_interception, |
6aa8b732 AK |
1529 | [SVM_EXIT_INVLPGA] = invalid_op_interception, |
1530 | [SVM_EXIT_IOIO] = io_interception, | |
1531 | [SVM_EXIT_MSR] = msr_interception, | |
1532 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1533 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1534 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1535 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1536 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1537 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1538 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1539 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1540 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1541 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1542 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1543 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1544 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1545 | }; |
1546 | ||
04d2cc77 | 1547 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1548 | { |
04d2cc77 | 1549 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1550 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1551 | |
af9ca2d7 JR |
1552 | KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip, |
1553 | (u32)((u64)svm->vmcb->save.rip >> 32), entryexit); | |
1554 | ||
709ddebf JR |
1555 | if (npt_enabled) { |
1556 | int mmu_reload = 0; | |
1557 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1558 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1559 | mmu_reload = 1; | |
1560 | } | |
1561 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1562 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1563 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1564 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1565 | kvm_inject_gp(vcpu, 0); | |
1566 | return 1; | |
1567 | } | |
1568 | } | |
1569 | if (mmu_reload) { | |
1570 | kvm_mmu_reset_context(vcpu); | |
1571 | kvm_mmu_load(vcpu); | |
1572 | } | |
1573 | } | |
1574 | ||
04d2cc77 AK |
1575 | kvm_reput_irq(svm); |
1576 | ||
1577 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1578 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1579 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1580 | = svm->vmcb->control.exit_code; | |
1581 | return 0; | |
1582 | } | |
1583 | ||
a2fa3e9f | 1584 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1585 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1586 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1587 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1588 | "exit_code 0x%x\n", | |
b8688d51 | 1589 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1590 | exit_code); |
1591 | ||
9d8f549d | 1592 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1593 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1594 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1595 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1596 | return 0; |
1597 | } | |
1598 | ||
e756fc62 | 1599 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1600 | } |
1601 | ||
1602 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1603 | { | |
1604 | int cpu = raw_smp_processor_id(); | |
1605 | ||
1606 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1607 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1608 | load_TR_desc(); |
1609 | } | |
1610 | ||
e756fc62 | 1611 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1612 | { |
1613 | int cpu = raw_smp_processor_id(); | |
1614 | ||
1615 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1616 | ||
a2fa3e9f | 1617 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1618 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1619 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1620 | new_asid(svm, svm_data); |
6aa8b732 AK |
1621 | } |
1622 | ||
1623 | ||
85f455f7 | 1624 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1625 | { |
1626 | struct vmcb_control_area *control; | |
1627 | ||
af9ca2d7 JR |
1628 | KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler); |
1629 | ||
fa89a817 | 1630 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 1631 | control = &svm->vmcb->control; |
85f455f7 | 1632 | control->int_vector = irq; |
6aa8b732 AK |
1633 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1634 | control->int_ctl |= V_IRQ_MASK | | |
1635 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1636 | } | |
1637 | ||
2a8067f1 ED |
1638 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1639 | { | |
1640 | struct vcpu_svm *svm = to_svm(vcpu); | |
1641 | ||
1642 | svm_inject_irq(svm, irq); | |
1643 | } | |
1644 | ||
aaacfc9a JR |
1645 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
1646 | { | |
1647 | struct vcpu_svm *svm = to_svm(vcpu); | |
1648 | struct vmcb *vmcb = svm->vmcb; | |
1649 | int max_irr, tpr; | |
1650 | ||
1651 | if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr) | |
1652 | return; | |
1653 | ||
1654 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1655 | ||
1656 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
1657 | if (max_irr == -1) | |
1658 | return; | |
1659 | ||
1660 | tpr = kvm_lapic_get_cr8(vcpu) << 4; | |
1661 | ||
1662 | if (tpr >= (max_irr & 0xf0)) | |
1663 | vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
1664 | } | |
1665 | ||
04d2cc77 | 1666 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1667 | { |
04d2cc77 | 1668 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1669 | struct vmcb *vmcb = svm->vmcb; |
1670 | int intr_vector = -1; | |
1671 | ||
1672 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1673 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1674 | intr_vector = vmcb->control.exit_int_info & | |
1675 | SVM_EVTINJ_VEC_MASK; | |
1676 | vmcb->control.exit_int_info = 0; | |
1677 | svm_inject_irq(svm, intr_vector); | |
aaacfc9a | 1678 | goto out; |
85f455f7 ED |
1679 | } |
1680 | ||
1681 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
aaacfc9a | 1682 | goto out; |
85f455f7 | 1683 | |
1b9778da | 1684 | if (!kvm_cpu_has_interrupt(vcpu)) |
aaacfc9a | 1685 | goto out; |
85f455f7 ED |
1686 | |
1687 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1688 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1689 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1690 | /* unable to deliver irq, set pending irq */ | |
f0b85051 | 1691 | svm_set_vintr(svm); |
85f455f7 | 1692 | svm_inject_irq(svm, 0x0); |
aaacfc9a | 1693 | goto out; |
85f455f7 ED |
1694 | } |
1695 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1696 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1697 | svm_inject_irq(svm, intr_vector); |
aaacfc9a JR |
1698 | out: |
1699 | update_cr8_intercept(vcpu); | |
85f455f7 ED |
1700 | } |
1701 | ||
1702 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1703 | { | |
e756fc62 | 1704 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1705 | |
7017fc3d ED |
1706 | if ((control->int_ctl & V_IRQ_MASK) |
1707 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1708 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1709 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1710 | } |
c1150d8c | 1711 | |
ad312c7c | 1712 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1713 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1714 | } | |
1715 | ||
85f455f7 ED |
1716 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1717 | { | |
1718 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1719 | int word_index = __ffs(vcpu->arch.irq_summary); |
1720 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1721 | int irq = word_index * BITS_PER_LONG + bit_index; |
1722 | ||
ad312c7c ZX |
1723 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1724 | if (!vcpu->arch.irq_pending[word_index]) | |
1725 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1726 | svm_inject_irq(svm, irq); |
1727 | } | |
1728 | ||
04d2cc77 | 1729 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1730 | struct kvm_run *kvm_run) |
1731 | { | |
04d2cc77 | 1732 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1733 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1734 | |
ad312c7c | 1735 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1736 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1737 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1738 | |
ad312c7c | 1739 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1740 | /* |
1741 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1742 | */ | |
85f455f7 | 1743 | svm_do_inject_vector(svm); |
c1150d8c DL |
1744 | |
1745 | /* | |
1746 | * Interrupts blocked. Wait for unblock. | |
1747 | */ | |
ad312c7c ZX |
1748 | if (!svm->vcpu.arch.interrupt_window_open && |
1749 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
f0b85051 AG |
1750 | svm_set_vintr(svm); |
1751 | else | |
1752 | svm_clear_vintr(svm); | |
c1150d8c DL |
1753 | } |
1754 | ||
cbc94022 IE |
1755 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1756 | { | |
1757 | return 0; | |
1758 | } | |
1759 | ||
6aa8b732 AK |
1760 | static void save_db_regs(unsigned long *db_regs) |
1761 | { | |
5aff458e AK |
1762 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1763 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1764 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1765 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1766 | } |
1767 | ||
1768 | static void load_db_regs(unsigned long *db_regs) | |
1769 | { | |
5aff458e AK |
1770 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1771 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1772 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1773 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1774 | } |
1775 | ||
d9e368d6 AK |
1776 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1777 | { | |
1778 | force_new_asid(vcpu); | |
1779 | } | |
1780 | ||
04d2cc77 AK |
1781 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1782 | { | |
1783 | } | |
1784 | ||
d7bf8221 JR |
1785 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
1786 | { | |
1787 | struct vcpu_svm *svm = to_svm(vcpu); | |
1788 | ||
1789 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
1790 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
1791 | kvm_lapic_set_tpr(vcpu, cr8); | |
1792 | } | |
1793 | } | |
1794 | ||
649d6864 JR |
1795 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
1796 | { | |
1797 | struct vcpu_svm *svm = to_svm(vcpu); | |
1798 | u64 cr8; | |
1799 | ||
1800 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1801 | return; | |
1802 | ||
1803 | cr8 = kvm_get_cr8(vcpu); | |
1804 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
1805 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
1806 | } | |
1807 | ||
80e31d4f AK |
1808 | #ifdef CONFIG_X86_64 |
1809 | #define R "r" | |
1810 | #else | |
1811 | #define R "e" | |
1812 | #endif | |
1813 | ||
04d2cc77 | 1814 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 1815 | { |
a2fa3e9f | 1816 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1817 | u16 fs_selector; |
1818 | u16 gs_selector; | |
1819 | u16 ldt_selector; | |
d9e368d6 | 1820 | |
5fdbf976 MT |
1821 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
1822 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
1823 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
1824 | ||
e756fc62 | 1825 | pre_svm_run(svm); |
6aa8b732 | 1826 | |
649d6864 JR |
1827 | sync_lapic_to_cr8(vcpu); |
1828 | ||
6aa8b732 | 1829 | save_host_msrs(vcpu); |
d6e88aec AK |
1830 | fs_selector = kvm_read_fs(); |
1831 | gs_selector = kvm_read_gs(); | |
1832 | ldt_selector = kvm_read_ldt(); | |
a2fa3e9f GH |
1833 | svm->host_cr2 = kvm_read_cr2(); |
1834 | svm->host_dr6 = read_dr6(); | |
1835 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1836 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1837 | /* required for live migration with NPT */ |
1838 | if (npt_enabled) | |
1839 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1840 | |
a2fa3e9f | 1841 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1842 | write_dr7(0); |
a2fa3e9f GH |
1843 | save_db_regs(svm->host_db_regs); |
1844 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1845 | } |
36241b8c | 1846 | |
04d2cc77 AK |
1847 | clgi(); |
1848 | ||
1849 | local_irq_enable(); | |
36241b8c | 1850 | |
6aa8b732 | 1851 | asm volatile ( |
80e31d4f AK |
1852 | "push %%"R"bp; \n\t" |
1853 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
1854 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
1855 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
1856 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
1857 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
1858 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 1859 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1860 | "mov %c[r8](%[svm]), %%r8 \n\t" |
1861 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1862 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1863 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1864 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1865 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1866 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1867 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
1868 | #endif |
1869 | ||
6aa8b732 | 1870 | /* Enter guest mode */ |
80e31d4f AK |
1871 | "push %%"R"ax \n\t" |
1872 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
1873 | __ex(SVM_VMLOAD) "\n\t" |
1874 | __ex(SVM_VMRUN) "\n\t" | |
1875 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 1876 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
1877 | |
1878 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
1879 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
1880 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
1881 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
1882 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
1883 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
1884 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 1885 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1886 | "mov %%r8, %c[r8](%[svm]) \n\t" |
1887 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1888 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1889 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1890 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1891 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1892 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1893 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1894 | #endif |
80e31d4f | 1895 | "pop %%"R"bp" |
6aa8b732 | 1896 | : |
fb3f0f51 | 1897 | : [svm]"a"(svm), |
6aa8b732 | 1898 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1899 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1900 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1901 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1902 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1903 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1904 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1905 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1906 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1907 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1908 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1909 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1910 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1911 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1912 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1913 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1914 | #endif |
54a08c04 | 1915 | : "cc", "memory" |
80e31d4f | 1916 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 1917 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
1918 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
1919 | #endif | |
1920 | ); | |
6aa8b732 | 1921 | |
a2fa3e9f GH |
1922 | if ((svm->vmcb->save.dr7 & 0xff)) |
1923 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1924 | |
ad312c7c | 1925 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
1926 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
1927 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
1928 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 1929 | |
a2fa3e9f GH |
1930 | write_dr6(svm->host_dr6); |
1931 | write_dr7(svm->host_dr7); | |
1932 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 | 1933 | |
d6e88aec AK |
1934 | kvm_load_fs(fs_selector); |
1935 | kvm_load_gs(gs_selector); | |
1936 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
1937 | load_host_msrs(vcpu); |
1938 | ||
1939 | reload_tss(vcpu); | |
1940 | ||
56ba47dd AK |
1941 | local_irq_disable(); |
1942 | ||
1943 | stgi(); | |
1944 | ||
d7bf8221 JR |
1945 | sync_cr8_to_lapic(vcpu); |
1946 | ||
a2fa3e9f | 1947 | svm->next_rip = 0; |
6aa8b732 AK |
1948 | } |
1949 | ||
80e31d4f AK |
1950 | #undef R |
1951 | ||
6aa8b732 AK |
1952 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1953 | { | |
a2fa3e9f GH |
1954 | struct vcpu_svm *svm = to_svm(vcpu); |
1955 | ||
709ddebf JR |
1956 | if (npt_enabled) { |
1957 | svm->vmcb->control.nested_cr3 = root; | |
1958 | force_new_asid(vcpu); | |
1959 | return; | |
1960 | } | |
1961 | ||
a2fa3e9f | 1962 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1963 | force_new_asid(vcpu); |
7807fa6c AL |
1964 | |
1965 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1966 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1967 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1968 | vcpu->fpu_active = 0; |
1969 | } | |
6aa8b732 AK |
1970 | } |
1971 | ||
6aa8b732 AK |
1972 | static int is_disabled(void) |
1973 | { | |
6031a61c JR |
1974 | u64 vm_cr; |
1975 | ||
1976 | rdmsrl(MSR_VM_CR, vm_cr); | |
1977 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1978 | return 1; | |
1979 | ||
6aa8b732 AK |
1980 | return 0; |
1981 | } | |
1982 | ||
102d8325 IM |
1983 | static void |
1984 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1985 | { | |
1986 | /* | |
1987 | * Patch in the VMMCALL instruction: | |
1988 | */ | |
1989 | hypercall[0] = 0x0f; | |
1990 | hypercall[1] = 0x01; | |
1991 | hypercall[2] = 0xd9; | |
102d8325 IM |
1992 | } |
1993 | ||
002c7f7c YS |
1994 | static void svm_check_processor_compat(void *rtn) |
1995 | { | |
1996 | *(int *)rtn = 0; | |
1997 | } | |
1998 | ||
774ead3a AK |
1999 | static bool svm_cpu_has_accelerated_tpr(void) |
2000 | { | |
2001 | return false; | |
2002 | } | |
2003 | ||
67253af5 SY |
2004 | static int get_npt_level(void) |
2005 | { | |
2006 | #ifdef CONFIG_X86_64 | |
2007 | return PT64_ROOT_LEVEL; | |
2008 | #else | |
2009 | return PT32E_ROOT_LEVEL; | |
2010 | #endif | |
2011 | } | |
2012 | ||
64d4d521 SY |
2013 | static int svm_get_mt_mask_shift(void) |
2014 | { | |
2015 | return 0; | |
2016 | } | |
2017 | ||
cbdd1bea | 2018 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
2019 | .cpu_has_kvm_support = has_svm, |
2020 | .disabled_by_bios = is_disabled, | |
2021 | .hardware_setup = svm_hardware_setup, | |
2022 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 2023 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
2024 | .hardware_enable = svm_hardware_enable, |
2025 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 2026 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
2027 | |
2028 | .vcpu_create = svm_create_vcpu, | |
2029 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 2030 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 2031 | |
04d2cc77 | 2032 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
2033 | .vcpu_load = svm_vcpu_load, |
2034 | .vcpu_put = svm_vcpu_put, | |
2035 | ||
2036 | .set_guest_debug = svm_guest_debug, | |
2037 | .get_msr = svm_get_msr, | |
2038 | .set_msr = svm_set_msr, | |
2039 | .get_segment_base = svm_get_segment_base, | |
2040 | .get_segment = svm_get_segment, | |
2041 | .set_segment = svm_set_segment, | |
2e4d2653 | 2042 | .get_cpl = svm_get_cpl, |
1747fb71 | 2043 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 2044 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 2045 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
2046 | .set_cr3 = svm_set_cr3, |
2047 | .set_cr4 = svm_set_cr4, | |
2048 | .set_efer = svm_set_efer, | |
2049 | .get_idt = svm_get_idt, | |
2050 | .set_idt = svm_set_idt, | |
2051 | .get_gdt = svm_get_gdt, | |
2052 | .set_gdt = svm_set_gdt, | |
2053 | .get_dr = svm_get_dr, | |
2054 | .set_dr = svm_set_dr, | |
6aa8b732 AK |
2055 | .get_rflags = svm_get_rflags, |
2056 | .set_rflags = svm_set_rflags, | |
2057 | ||
6aa8b732 | 2058 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 2059 | |
6aa8b732 | 2060 | .run = svm_vcpu_run, |
04d2cc77 | 2061 | .handle_exit = handle_exit, |
6aa8b732 | 2062 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 2063 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
2064 | .get_irq = svm_get_irq, |
2065 | .set_irq = svm_set_irq, | |
298101da AK |
2066 | .queue_exception = svm_queue_exception, |
2067 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
2068 | .inject_pending_irq = svm_intr_assist, |
2069 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
2070 | |
2071 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 2072 | .get_tdp_level = get_npt_level, |
64d4d521 | 2073 | .get_mt_mask_shift = svm_get_mt_mask_shift, |
6aa8b732 AK |
2074 | }; |
2075 | ||
2076 | static int __init svm_init(void) | |
2077 | { | |
cb498ea2 | 2078 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 2079 | THIS_MODULE); |
6aa8b732 AK |
2080 | } |
2081 | ||
2082 | static void __exit svm_exit(void) | |
2083 | { | |
cb498ea2 | 2084 | kvm_exit(); |
6aa8b732 AK |
2085 | } |
2086 | ||
2087 | module_init(svm_init) | |
2088 | module_exit(svm_exit) |