Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 7 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
631bc487 | 34 | #include <asm/kvm_para.h> |
6aa8b732 | 35 | |
63d1142f | 36 | #include <asm/virtext.h> |
229456fc | 37 | #include "trace.h" |
63d1142f | 38 | |
4ecac3fd AK |
39 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
40 | ||
6aa8b732 AK |
41 | MODULE_AUTHOR("Qumranet"); |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | #define IOPM_ALLOC_ORDER 2 | |
45 | #define MSRPM_ALLOC_ORDER 1 | |
46 | ||
6aa8b732 AK |
47 | #define SEG_TYPE_LDT 2 |
48 | #define SEG_TYPE_BUSY_TSS16 3 | |
49 | ||
6bc31bdc AP |
50 | #define SVM_FEATURE_NPT (1 << 0) |
51 | #define SVM_FEATURE_LBRV (1 << 1) | |
52 | #define SVM_FEATURE_SVML (1 << 2) | |
53 | #define SVM_FEATURE_NRIP (1 << 3) | |
54 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) | |
80b7706e | 55 | |
410e4d57 JR |
56 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
57 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
58 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
59 | ||
24e09cbf JR |
60 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
61 | ||
67ec6607 JR |
62 | static bool erratum_383_found __read_mostly; |
63 | ||
6c8166a7 AK |
64 | static const u32 host_save_user_msrs[] = { |
65 | #ifdef CONFIG_X86_64 | |
66 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
67 | MSR_FS_BASE, | |
68 | #endif | |
69 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
70 | }; | |
71 | ||
72 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
73 | ||
74 | struct kvm_vcpu; | |
75 | ||
e6aa9abd JR |
76 | struct nested_state { |
77 | struct vmcb *hsave; | |
78 | u64 hsave_msr; | |
4a810181 | 79 | u64 vm_cr_msr; |
e6aa9abd JR |
80 | u64 vmcb; |
81 | ||
82 | /* These are the merged vectors */ | |
83 | u32 *msrpm; | |
84 | ||
85 | /* gpa pointers to the real vectors */ | |
86 | u64 vmcb_msrpm; | |
ce2ac085 | 87 | u64 vmcb_iopm; |
aad42c64 | 88 | |
cd3ff653 JR |
89 | /* A VMEXIT is required but not yet emulated */ |
90 | bool exit_required; | |
91 | ||
cda00082 JR |
92 | /* |
93 | * If we vmexit during an instruction emulation we need this to restore | |
94 | * the l1 guest rip after the emulation | |
95 | */ | |
96 | unsigned long vmexit_rip; | |
97 | unsigned long vmexit_rsp; | |
98 | unsigned long vmexit_rax; | |
99 | ||
aad42c64 JR |
100 | /* cache for intercepts of the guest */ |
101 | u16 intercept_cr_read; | |
102 | u16 intercept_cr_write; | |
103 | u16 intercept_dr_read; | |
104 | u16 intercept_dr_write; | |
105 | u32 intercept_exceptions; | |
106 | u64 intercept; | |
107 | ||
5bd2edc3 JR |
108 | /* Nested Paging related state */ |
109 | u64 nested_cr3; | |
e6aa9abd JR |
110 | }; |
111 | ||
323c3d80 JR |
112 | #define MSRPM_OFFSETS 16 |
113 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
114 | ||
6c8166a7 AK |
115 | struct vcpu_svm { |
116 | struct kvm_vcpu vcpu; | |
117 | struct vmcb *vmcb; | |
118 | unsigned long vmcb_pa; | |
119 | struct svm_cpu_data *svm_data; | |
120 | uint64_t asid_generation; | |
121 | uint64_t sysenter_esp; | |
122 | uint64_t sysenter_eip; | |
123 | ||
124 | u64 next_rip; | |
125 | ||
126 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
afe9e66f | 127 | struct { |
dacccfdd AK |
128 | u16 fs; |
129 | u16 gs; | |
130 | u16 ldt; | |
afe9e66f AK |
131 | u64 gs_base; |
132 | } host; | |
6c8166a7 AK |
133 | |
134 | u32 *msrpm; | |
6c8166a7 | 135 | |
e6aa9abd | 136 | struct nested_state nested; |
6be7d306 JK |
137 | |
138 | bool nmi_singlestep; | |
66b7138f JK |
139 | |
140 | unsigned int3_injected; | |
141 | unsigned long int3_rip; | |
631bc487 | 142 | u32 apf_reason; |
6c8166a7 AK |
143 | }; |
144 | ||
455716fa JR |
145 | #define MSR_INVALID 0xffffffffU |
146 | ||
ac72a9b7 JR |
147 | static struct svm_direct_access_msrs { |
148 | u32 index; /* Index of the MSR */ | |
149 | bool always; /* True if intercept is always on */ | |
150 | } direct_access_msrs[] = { | |
8c06585d | 151 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
152 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
153 | #ifdef CONFIG_X86_64 | |
154 | { .index = MSR_GS_BASE, .always = true }, | |
155 | { .index = MSR_FS_BASE, .always = true }, | |
156 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
157 | { .index = MSR_LSTAR, .always = true }, | |
158 | { .index = MSR_CSTAR, .always = true }, | |
159 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
160 | #endif | |
161 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
162 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
163 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
164 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
165 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
166 | }; |
167 | ||
709ddebf JR |
168 | /* enable NPT for AMD64 and X86 with PAE */ |
169 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
170 | static bool npt_enabled = true; | |
171 | #else | |
e0231715 | 172 | static bool npt_enabled; |
709ddebf | 173 | #endif |
6c7dac72 JR |
174 | static int npt = 1; |
175 | ||
176 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 177 | |
4b6e4dca | 178 | static int nested = 1; |
236de055 AG |
179 | module_param(nested, int, S_IRUGO); |
180 | ||
44874f84 | 181 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 182 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 183 | |
410e4d57 | 184 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 185 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 186 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
187 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
188 | bool has_error_code, u32 error_code); | |
189 | ||
a2fa3e9f GH |
190 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
191 | { | |
fb3f0f51 | 192 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
193 | } |
194 | ||
3d6368ef AG |
195 | static inline bool is_nested(struct vcpu_svm *svm) |
196 | { | |
e6aa9abd | 197 | return svm->nested.vmcb; |
3d6368ef AG |
198 | } |
199 | ||
2af9194d JR |
200 | static inline void enable_gif(struct vcpu_svm *svm) |
201 | { | |
202 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
203 | } | |
204 | ||
205 | static inline void disable_gif(struct vcpu_svm *svm) | |
206 | { | |
207 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
208 | } | |
209 | ||
210 | static inline bool gif_set(struct vcpu_svm *svm) | |
211 | { | |
212 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
213 | } | |
214 | ||
4866d5e3 | 215 | static unsigned long iopm_base; |
6aa8b732 AK |
216 | |
217 | struct kvm_ldttss_desc { | |
218 | u16 limit0; | |
219 | u16 base0; | |
e0231715 JR |
220 | unsigned base1:8, type:5, dpl:2, p:1; |
221 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
222 | u32 base3; |
223 | u32 zero1; | |
224 | } __attribute__((packed)); | |
225 | ||
226 | struct svm_cpu_data { | |
227 | int cpu; | |
228 | ||
5008fdf5 AK |
229 | u64 asid_generation; |
230 | u32 max_asid; | |
231 | u32 next_asid; | |
6aa8b732 AK |
232 | struct kvm_ldttss_desc *tss_desc; |
233 | ||
234 | struct page *save_area; | |
235 | }; | |
236 | ||
237 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 238 | static uint32_t svm_features; |
6aa8b732 AK |
239 | |
240 | struct svm_init_data { | |
241 | int cpu; | |
242 | int r; | |
243 | }; | |
244 | ||
245 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
246 | ||
9d8f549d | 247 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
248 | #define MSRS_RANGE_SIZE 2048 |
249 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
250 | ||
455716fa JR |
251 | static u32 svm_msrpm_offset(u32 msr) |
252 | { | |
253 | u32 offset; | |
254 | int i; | |
255 | ||
256 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
257 | if (msr < msrpm_ranges[i] || | |
258 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
259 | continue; | |
260 | ||
261 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
262 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
263 | ||
264 | /* Now we have the u8 offset - but need the u32 offset */ | |
265 | return offset / 4; | |
266 | } | |
267 | ||
268 | /* MSR not in any range */ | |
269 | return MSR_INVALID; | |
270 | } | |
271 | ||
6aa8b732 AK |
272 | #define MAX_INST_SIZE 15 |
273 | ||
80b7706e JR |
274 | static inline u32 svm_has(u32 feat) |
275 | { | |
276 | return svm_features & feat; | |
277 | } | |
278 | ||
6aa8b732 AK |
279 | static inline void clgi(void) |
280 | { | |
4ecac3fd | 281 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
282 | } |
283 | ||
284 | static inline void stgi(void) | |
285 | { | |
4ecac3fd | 286 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
287 | } |
288 | ||
289 | static inline void invlpga(unsigned long addr, u32 asid) | |
290 | { | |
e0231715 | 291 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
292 | } |
293 | ||
6aa8b732 AK |
294 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
295 | { | |
a2fa3e9f | 296 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
297 | } |
298 | ||
299 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
300 | { | |
301 | force_new_asid(vcpu); | |
302 | } | |
303 | ||
4b16184c JR |
304 | static int get_npt_level(void) |
305 | { | |
306 | #ifdef CONFIG_X86_64 | |
307 | return PT64_ROOT_LEVEL; | |
308 | #else | |
309 | return PT32E_ROOT_LEVEL; | |
310 | #endif | |
311 | } | |
312 | ||
6aa8b732 AK |
313 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
314 | { | |
6dc696d4 | 315 | vcpu->arch.efer = efer; |
709ddebf | 316 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 317 | efer &= ~EFER_LME; |
6aa8b732 | 318 | |
9962d032 | 319 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
6aa8b732 AK |
320 | } |
321 | ||
6aa8b732 AK |
322 | static int is_external_interrupt(u32 info) |
323 | { | |
324 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
325 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
326 | } | |
327 | ||
2809f5d2 GC |
328 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
329 | { | |
330 | struct vcpu_svm *svm = to_svm(vcpu); | |
331 | u32 ret = 0; | |
332 | ||
333 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 334 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
335 | return ret & mask; |
336 | } | |
337 | ||
338 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
339 | { | |
340 | struct vcpu_svm *svm = to_svm(vcpu); | |
341 | ||
342 | if (mask == 0) | |
343 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
344 | else | |
345 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
346 | ||
347 | } | |
348 | ||
6aa8b732 AK |
349 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
350 | { | |
a2fa3e9f GH |
351 | struct vcpu_svm *svm = to_svm(vcpu); |
352 | ||
6bc31bdc AP |
353 | if (svm->vmcb->control.next_rip != 0) |
354 | svm->next_rip = svm->vmcb->control.next_rip; | |
355 | ||
a2fa3e9f | 356 | if (!svm->next_rip) { |
851ba692 | 357 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
358 | EMULATE_DONE) |
359 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
360 | return; |
361 | } | |
5fdbf976 MT |
362 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
363 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
364 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 365 | |
5fdbf976 | 366 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 367 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
368 | } |
369 | ||
116a4752 | 370 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
371 | bool has_error_code, u32 error_code, |
372 | bool reinject) | |
116a4752 JK |
373 | { |
374 | struct vcpu_svm *svm = to_svm(vcpu); | |
375 | ||
e0231715 JR |
376 | /* |
377 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
378 | * handle the exception | |
379 | */ | |
ce7ddec4 JR |
380 | if (!reinject && |
381 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
382 | return; |
383 | ||
66b7138f JK |
384 | if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) { |
385 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); | |
386 | ||
387 | /* | |
388 | * For guest debugging where we have to reinject #BP if some | |
389 | * INT3 is guest-owned: | |
390 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
391 | * raises a fault that is not intercepted. Still better than | |
392 | * failing in all cases. | |
393 | */ | |
394 | skip_emulated_instruction(&svm->vcpu); | |
395 | rip = kvm_rip_read(&svm->vcpu); | |
396 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
397 | svm->int3_injected = rip - old_rip; | |
398 | } | |
399 | ||
116a4752 JK |
400 | svm->vmcb->control.event_inj = nr |
401 | | SVM_EVTINJ_VALID | |
402 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
403 | | SVM_EVTINJ_TYPE_EXEPT; | |
404 | svm->vmcb->control.event_inj_err = error_code; | |
405 | } | |
406 | ||
67ec6607 JR |
407 | static void svm_init_erratum_383(void) |
408 | { | |
409 | u32 low, high; | |
410 | int err; | |
411 | u64 val; | |
412 | ||
1be85a6d | 413 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
414 | return; |
415 | ||
416 | /* Use _safe variants to not break nested virtualization */ | |
417 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
418 | if (err) | |
419 | return; | |
420 | ||
421 | val |= (1ULL << 47); | |
422 | ||
423 | low = lower_32_bits(val); | |
424 | high = upper_32_bits(val); | |
425 | ||
426 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
427 | ||
428 | erratum_383_found = true; | |
429 | } | |
430 | ||
6aa8b732 AK |
431 | static int has_svm(void) |
432 | { | |
63d1142f | 433 | const char *msg; |
6aa8b732 | 434 | |
63d1142f | 435 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 436 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
437 | return 0; |
438 | } | |
439 | ||
6aa8b732 AK |
440 | return 1; |
441 | } | |
442 | ||
443 | static void svm_hardware_disable(void *garbage) | |
444 | { | |
2c8dceeb | 445 | cpu_svm_disable(); |
6aa8b732 AK |
446 | } |
447 | ||
10474ae8 | 448 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
449 | { |
450 | ||
0fe1e009 | 451 | struct svm_cpu_data *sd; |
6aa8b732 | 452 | uint64_t efer; |
89a27f4d | 453 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
454 | struct desc_struct *gdt; |
455 | int me = raw_smp_processor_id(); | |
456 | ||
10474ae8 AG |
457 | rdmsrl(MSR_EFER, efer); |
458 | if (efer & EFER_SVME) | |
459 | return -EBUSY; | |
460 | ||
6aa8b732 | 461 | if (!has_svm()) { |
e6732a5a ZA |
462 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
463 | me); | |
10474ae8 | 464 | return -EINVAL; |
6aa8b732 | 465 | } |
0fe1e009 | 466 | sd = per_cpu(svm_data, me); |
6aa8b732 | 467 | |
0fe1e009 | 468 | if (!sd) { |
e6732a5a | 469 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 470 | me); |
10474ae8 | 471 | return -EINVAL; |
6aa8b732 AK |
472 | } |
473 | ||
0fe1e009 TH |
474 | sd->asid_generation = 1; |
475 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
476 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 477 | |
d6ab1ed4 | 478 | native_store_gdt(&gdt_descr); |
89a27f4d | 479 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 480 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 481 | |
9962d032 | 482 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 483 | |
d0316554 | 484 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 485 | |
67ec6607 JR |
486 | svm_init_erratum_383(); |
487 | ||
10474ae8 | 488 | return 0; |
6aa8b732 AK |
489 | } |
490 | ||
0da1db75 JR |
491 | static void svm_cpu_uninit(int cpu) |
492 | { | |
0fe1e009 | 493 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 494 | |
0fe1e009 | 495 | if (!sd) |
0da1db75 JR |
496 | return; |
497 | ||
498 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
499 | __free_page(sd->save_area); |
500 | kfree(sd); | |
0da1db75 JR |
501 | } |
502 | ||
6aa8b732 AK |
503 | static int svm_cpu_init(int cpu) |
504 | { | |
0fe1e009 | 505 | struct svm_cpu_data *sd; |
6aa8b732 AK |
506 | int r; |
507 | ||
0fe1e009 TH |
508 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
509 | if (!sd) | |
6aa8b732 | 510 | return -ENOMEM; |
0fe1e009 TH |
511 | sd->cpu = cpu; |
512 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 513 | r = -ENOMEM; |
0fe1e009 | 514 | if (!sd->save_area) |
6aa8b732 AK |
515 | goto err_1; |
516 | ||
0fe1e009 | 517 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
518 | |
519 | return 0; | |
520 | ||
521 | err_1: | |
0fe1e009 | 522 | kfree(sd); |
6aa8b732 AK |
523 | return r; |
524 | ||
525 | } | |
526 | ||
ac72a9b7 JR |
527 | static bool valid_msr_intercept(u32 index) |
528 | { | |
529 | int i; | |
530 | ||
531 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
532 | if (direct_access_msrs[i].index == index) | |
533 | return true; | |
534 | ||
535 | return false; | |
536 | } | |
537 | ||
bfc733a7 RR |
538 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
539 | int read, int write) | |
6aa8b732 | 540 | { |
455716fa JR |
541 | u8 bit_read, bit_write; |
542 | unsigned long tmp; | |
543 | u32 offset; | |
6aa8b732 | 544 | |
ac72a9b7 JR |
545 | /* |
546 | * If this warning triggers extend the direct_access_msrs list at the | |
547 | * beginning of the file | |
548 | */ | |
549 | WARN_ON(!valid_msr_intercept(msr)); | |
550 | ||
455716fa JR |
551 | offset = svm_msrpm_offset(msr); |
552 | bit_read = 2 * (msr & 0x0f); | |
553 | bit_write = 2 * (msr & 0x0f) + 1; | |
554 | tmp = msrpm[offset]; | |
555 | ||
556 | BUG_ON(offset == MSR_INVALID); | |
557 | ||
558 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
559 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
560 | ||
561 | msrpm[offset] = tmp; | |
6aa8b732 AK |
562 | } |
563 | ||
f65c229c | 564 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
565 | { |
566 | int i; | |
567 | ||
f65c229c JR |
568 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
569 | ||
ac72a9b7 JR |
570 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
571 | if (!direct_access_msrs[i].always) | |
572 | continue; | |
573 | ||
574 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
575 | } | |
f65c229c JR |
576 | } |
577 | ||
323c3d80 JR |
578 | static void add_msr_offset(u32 offset) |
579 | { | |
580 | int i; | |
581 | ||
582 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
583 | ||
584 | /* Offset already in list? */ | |
585 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 586 | return; |
323c3d80 JR |
587 | |
588 | /* Slot used by another offset? */ | |
589 | if (msrpm_offsets[i] != MSR_INVALID) | |
590 | continue; | |
591 | ||
592 | /* Add offset to list */ | |
593 | msrpm_offsets[i] = offset; | |
594 | ||
595 | return; | |
6aa8b732 | 596 | } |
323c3d80 JR |
597 | |
598 | /* | |
599 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
600 | * increase MSRPM_OFFSETS in this case. | |
601 | */ | |
bfc733a7 | 602 | BUG(); |
6aa8b732 AK |
603 | } |
604 | ||
323c3d80 | 605 | static void init_msrpm_offsets(void) |
f65c229c | 606 | { |
323c3d80 | 607 | int i; |
f65c229c | 608 | |
323c3d80 JR |
609 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
610 | ||
611 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
612 | u32 offset; | |
613 | ||
614 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
615 | BUG_ON(offset == MSR_INVALID); | |
616 | ||
617 | add_msr_offset(offset); | |
618 | } | |
f65c229c JR |
619 | } |
620 | ||
24e09cbf JR |
621 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
622 | { | |
623 | u32 *msrpm = svm->msrpm; | |
624 | ||
625 | svm->vmcb->control.lbr_ctl = 1; | |
626 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
627 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
628 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
629 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
630 | } | |
631 | ||
632 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
633 | { | |
634 | u32 *msrpm = svm->msrpm; | |
635 | ||
636 | svm->vmcb->control.lbr_ctl = 0; | |
637 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
638 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
639 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
640 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
641 | } | |
642 | ||
6aa8b732 AK |
643 | static __init int svm_hardware_setup(void) |
644 | { | |
645 | int cpu; | |
646 | struct page *iopm_pages; | |
f65c229c | 647 | void *iopm_va; |
6aa8b732 AK |
648 | int r; |
649 | ||
6aa8b732 AK |
650 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
651 | ||
652 | if (!iopm_pages) | |
653 | return -ENOMEM; | |
c8681339 AL |
654 | |
655 | iopm_va = page_address(iopm_pages); | |
656 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
657 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
658 | ||
323c3d80 JR |
659 | init_msrpm_offsets(); |
660 | ||
50a37eb4 JR |
661 | if (boot_cpu_has(X86_FEATURE_NX)) |
662 | kvm_enable_efer_bits(EFER_NX); | |
663 | ||
1b2fd70c AG |
664 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
665 | kvm_enable_efer_bits(EFER_FFXSR); | |
666 | ||
236de055 AG |
667 | if (nested) { |
668 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 669 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
670 | } |
671 | ||
3230bb47 | 672 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
673 | r = svm_cpu_init(cpu); |
674 | if (r) | |
f65c229c | 675 | goto err; |
6aa8b732 | 676 | } |
33bd6a0b JR |
677 | |
678 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
679 | ||
e3da3acd JR |
680 | if (!svm_has(SVM_FEATURE_NPT)) |
681 | npt_enabled = false; | |
682 | ||
6c7dac72 JR |
683 | if (npt_enabled && !npt) { |
684 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
685 | npt_enabled = false; | |
686 | } | |
687 | ||
18552672 | 688 | if (npt_enabled) { |
e3da3acd | 689 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 690 | kvm_enable_tdp(); |
5f4cb662 JR |
691 | } else |
692 | kvm_disable_tdp(); | |
e3da3acd | 693 | |
6aa8b732 AK |
694 | return 0; |
695 | ||
f65c229c | 696 | err: |
6aa8b732 AK |
697 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
698 | iopm_base = 0; | |
699 | return r; | |
700 | } | |
701 | ||
702 | static __exit void svm_hardware_unsetup(void) | |
703 | { | |
0da1db75 JR |
704 | int cpu; |
705 | ||
3230bb47 | 706 | for_each_possible_cpu(cpu) |
0da1db75 JR |
707 | svm_cpu_uninit(cpu); |
708 | ||
6aa8b732 | 709 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 710 | iopm_base = 0; |
6aa8b732 AK |
711 | } |
712 | ||
713 | static void init_seg(struct vmcb_seg *seg) | |
714 | { | |
715 | seg->selector = 0; | |
716 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 717 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
718 | seg->limit = 0xffff; |
719 | seg->base = 0; | |
720 | } | |
721 | ||
722 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
723 | { | |
724 | seg->selector = 0; | |
725 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
726 | seg->limit = 0xffff; | |
727 | seg->base = 0; | |
728 | } | |
729 | ||
f4e1b3c8 ZA |
730 | static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
731 | { | |
732 | struct vcpu_svm *svm = to_svm(vcpu); | |
733 | u64 g_tsc_offset = 0; | |
734 | ||
735 | if (is_nested(svm)) { | |
736 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
737 | svm->nested.hsave->control.tsc_offset; | |
738 | svm->nested.hsave->control.tsc_offset = offset; | |
739 | } | |
740 | ||
741 | svm->vmcb->control.tsc_offset = offset + g_tsc_offset; | |
742 | } | |
743 | ||
e48672fa ZA |
744 | static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
745 | { | |
746 | struct vcpu_svm *svm = to_svm(vcpu); | |
747 | ||
748 | svm->vmcb->control.tsc_offset += adjustment; | |
749 | if (is_nested(svm)) | |
750 | svm->nested.hsave->control.tsc_offset += adjustment; | |
751 | } | |
752 | ||
e6101a96 | 753 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 754 | { |
e6101a96 JR |
755 | struct vmcb_control_area *control = &svm->vmcb->control; |
756 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 757 | |
bff78274 AK |
758 | svm->vcpu.fpu_active = 1; |
759 | ||
e0231715 | 760 | control->intercept_cr_read = INTERCEPT_CR0_MASK | |
6aa8b732 | 761 | INTERCEPT_CR3_MASK | |
649d6864 | 762 | INTERCEPT_CR4_MASK; |
6aa8b732 | 763 | |
e0231715 | 764 | control->intercept_cr_write = INTERCEPT_CR0_MASK | |
6aa8b732 | 765 | INTERCEPT_CR3_MASK | |
80a8119c AK |
766 | INTERCEPT_CR4_MASK | |
767 | INTERCEPT_CR8_MASK; | |
6aa8b732 | 768 | |
e0231715 | 769 | control->intercept_dr_read = INTERCEPT_DR0_MASK | |
6aa8b732 AK |
770 | INTERCEPT_DR1_MASK | |
771 | INTERCEPT_DR2_MASK | | |
727f5a23 JK |
772 | INTERCEPT_DR3_MASK | |
773 | INTERCEPT_DR4_MASK | | |
774 | INTERCEPT_DR5_MASK | | |
775 | INTERCEPT_DR6_MASK | | |
776 | INTERCEPT_DR7_MASK; | |
6aa8b732 | 777 | |
e0231715 | 778 | control->intercept_dr_write = INTERCEPT_DR0_MASK | |
6aa8b732 AK |
779 | INTERCEPT_DR1_MASK | |
780 | INTERCEPT_DR2_MASK | | |
781 | INTERCEPT_DR3_MASK | | |
727f5a23 | 782 | INTERCEPT_DR4_MASK | |
6aa8b732 | 783 | INTERCEPT_DR5_MASK | |
727f5a23 | 784 | INTERCEPT_DR6_MASK | |
6aa8b732 AK |
785 | INTERCEPT_DR7_MASK; |
786 | ||
7aa81cc0 | 787 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
788 | (1 << UD_VECTOR) | |
789 | (1 << MC_VECTOR); | |
6aa8b732 AK |
790 | |
791 | ||
e0231715 | 792 | control->intercept = (1ULL << INTERCEPT_INTR) | |
6aa8b732 | 793 | (1ULL << INTERCEPT_NMI) | |
0152527b | 794 | (1ULL << INTERCEPT_SMI) | |
d225157b | 795 | (1ULL << INTERCEPT_SELECTIVE_CR0) | |
6aa8b732 | 796 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 797 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 798 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 799 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
800 | (1ULL << INTERCEPT_INVLPGA) | |
801 | (1ULL << INTERCEPT_IOIO_PROT) | | |
802 | (1ULL << INTERCEPT_MSR_PROT) | | |
803 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 804 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
805 | (1ULL << INTERCEPT_VMRUN) | |
806 | (1ULL << INTERCEPT_VMMCALL) | | |
807 | (1ULL << INTERCEPT_VMLOAD) | | |
808 | (1ULL << INTERCEPT_VMSAVE) | | |
809 | (1ULL << INTERCEPT_STGI) | | |
810 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 811 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 812 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
813 | (1ULL << INTERCEPT_MONITOR) | |
814 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
815 | |
816 | control->iopm_base_pa = iopm_base; | |
f65c229c | 817 | control->msrpm_base_pa = __pa(svm->msrpm); |
6aa8b732 AK |
818 | control->int_ctl = V_INTR_MASKING_MASK; |
819 | ||
820 | init_seg(&save->es); | |
821 | init_seg(&save->ss); | |
822 | init_seg(&save->ds); | |
823 | init_seg(&save->fs); | |
824 | init_seg(&save->gs); | |
825 | ||
826 | save->cs.selector = 0xf000; | |
827 | /* Executable/Readable Code Segment */ | |
828 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
829 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
830 | save->cs.limit = 0xffff; | |
d92899a0 AK |
831 | /* |
832 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
833 | * be consistent with it. | |
834 | * | |
835 | * Replace when we have real mode working for vmx. | |
836 | */ | |
837 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
838 | |
839 | save->gdtr.limit = 0xffff; | |
840 | save->idtr.limit = 0xffff; | |
841 | ||
842 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
843 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
844 | ||
eaa48512 | 845 | svm_set_efer(&svm->vcpu, 0); |
d77c26fc | 846 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
847 | save->dr7 = 0x400; |
848 | save->rflags = 2; | |
849 | save->rip = 0x0000fff0; | |
5fdbf976 | 850 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 851 | |
e0231715 JR |
852 | /* |
853 | * This is the guest-visible cr0 value. | |
18fa000a | 854 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 855 | */ |
678041ad MT |
856 | svm->vcpu.arch.cr0 = 0; |
857 | (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET); | |
18fa000a | 858 | |
66aee91a | 859 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 860 | /* rdx = ?? */ |
709ddebf JR |
861 | |
862 | if (npt_enabled) { | |
863 | /* Setup VMCB for Nested Paging */ | |
864 | control->nested_ctl = 1; | |
a7052897 MT |
865 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
866 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf | 867 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
888f9f3e AK |
868 | control->intercept_cr_read &= ~INTERCEPT_CR3_MASK; |
869 | control->intercept_cr_write &= ~INTERCEPT_CR3_MASK; | |
709ddebf | 870 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
871 | save->cr3 = 0; |
872 | save->cr4 = 0; | |
873 | } | |
a79d2f18 | 874 | force_new_asid(&svm->vcpu); |
1371d904 | 875 | |
e6aa9abd | 876 | svm->nested.vmcb = 0; |
2af9194d JR |
877 | svm->vcpu.arch.hflags = 0; |
878 | ||
565d0998 ML |
879 | if (svm_has(SVM_FEATURE_PAUSE_FILTER)) { |
880 | control->pause_filter_count = 3000; | |
881 | control->intercept |= (1ULL << INTERCEPT_PAUSE); | |
882 | } | |
883 | ||
2af9194d | 884 | enable_gif(svm); |
6aa8b732 AK |
885 | } |
886 | ||
e00c8cf2 | 887 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
888 | { |
889 | struct vcpu_svm *svm = to_svm(vcpu); | |
890 | ||
e6101a96 | 891 | init_vmcb(svm); |
70433389 | 892 | |
c5af89b6 | 893 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 894 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
895 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
896 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 897 | } |
5fdbf976 MT |
898 | vcpu->arch.regs_avail = ~0; |
899 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
900 | |
901 | return 0; | |
04d2cc77 AK |
902 | } |
903 | ||
fb3f0f51 | 904 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 905 | { |
a2fa3e9f | 906 | struct vcpu_svm *svm; |
6aa8b732 | 907 | struct page *page; |
f65c229c | 908 | struct page *msrpm_pages; |
b286d5d8 | 909 | struct page *hsave_page; |
3d6368ef | 910 | struct page *nested_msrpm_pages; |
fb3f0f51 | 911 | int err; |
6aa8b732 | 912 | |
c16f862d | 913 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
914 | if (!svm) { |
915 | err = -ENOMEM; | |
916 | goto out; | |
917 | } | |
918 | ||
919 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
920 | if (err) | |
921 | goto free_svm; | |
922 | ||
b7af4043 | 923 | err = -ENOMEM; |
6aa8b732 | 924 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 925 | if (!page) |
fb3f0f51 | 926 | goto uninit; |
6aa8b732 | 927 | |
f65c229c JR |
928 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
929 | if (!msrpm_pages) | |
b7af4043 | 930 | goto free_page1; |
3d6368ef AG |
931 | |
932 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
933 | if (!nested_msrpm_pages) | |
b7af4043 | 934 | goto free_page2; |
f65c229c | 935 | |
b286d5d8 AG |
936 | hsave_page = alloc_page(GFP_KERNEL); |
937 | if (!hsave_page) | |
b7af4043 TY |
938 | goto free_page3; |
939 | ||
e6aa9abd | 940 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 941 | |
b7af4043 TY |
942 | svm->msrpm = page_address(msrpm_pages); |
943 | svm_vcpu_init_msrpm(svm->msrpm); | |
944 | ||
e6aa9abd | 945 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 946 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 947 | |
a2fa3e9f GH |
948 | svm->vmcb = page_address(page); |
949 | clear_page(svm->vmcb); | |
950 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
951 | svm->asid_generation = 0; | |
e6101a96 | 952 | init_vmcb(svm); |
99e3e30a | 953 | kvm_write_tsc(&svm->vcpu, 0); |
a2fa3e9f | 954 | |
10ab25cd JK |
955 | err = fx_init(&svm->vcpu); |
956 | if (err) | |
957 | goto free_page4; | |
958 | ||
ad312c7c | 959 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 960 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 961 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 962 | |
fb3f0f51 | 963 | return &svm->vcpu; |
36241b8c | 964 | |
10ab25cd JK |
965 | free_page4: |
966 | __free_page(hsave_page); | |
b7af4043 TY |
967 | free_page3: |
968 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
969 | free_page2: | |
970 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
971 | free_page1: | |
972 | __free_page(page); | |
fb3f0f51 RR |
973 | uninit: |
974 | kvm_vcpu_uninit(&svm->vcpu); | |
975 | free_svm: | |
a4770347 | 976 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
977 | out: |
978 | return ERR_PTR(err); | |
6aa8b732 AK |
979 | } |
980 | ||
981 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
982 | { | |
a2fa3e9f GH |
983 | struct vcpu_svm *svm = to_svm(vcpu); |
984 | ||
fb3f0f51 | 985 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 986 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
987 | __free_page(virt_to_page(svm->nested.hsave)); |
988 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 989 | kvm_vcpu_uninit(vcpu); |
a4770347 | 990 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
991 | } |
992 | ||
15ad7146 | 993 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 994 | { |
a2fa3e9f | 995 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 996 | int i; |
0cc5064d | 997 | |
0cc5064d | 998 | if (unlikely(cpu != vcpu->cpu)) { |
4b656b12 | 999 | svm->asid_generation = 0; |
0cc5064d | 1000 | } |
94dfbdb3 | 1001 | |
82ca2d10 AK |
1002 | #ifdef CONFIG_X86_64 |
1003 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); | |
1004 | #endif | |
dacccfdd AK |
1005 | savesegment(fs, svm->host.fs); |
1006 | savesegment(gs, svm->host.gs); | |
1007 | svm->host.ldt = kvm_read_ldt(); | |
1008 | ||
94dfbdb3 | 1009 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1010 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1011 | } |
1012 | ||
1013 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
1014 | { | |
a2fa3e9f | 1015 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
1016 | int i; |
1017 | ||
e1beb1d3 | 1018 | ++vcpu->stat.host_state_reload; |
dacccfdd AK |
1019 | kvm_load_ldt(svm->host.ldt); |
1020 | #ifdef CONFIG_X86_64 | |
1021 | loadsegment(fs, svm->host.fs); | |
1022 | load_gs_index(svm->host.gs); | |
1023 | wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs); | |
1024 | #else | |
1025 | loadsegment(gs, svm->host.gs); | |
1026 | #endif | |
94dfbdb3 | 1027 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 1028 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
1029 | } |
1030 | ||
6aa8b732 AK |
1031 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
1032 | { | |
a2fa3e9f | 1033 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
1034 | } |
1035 | ||
1036 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1037 | { | |
a2fa3e9f | 1038 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
1039 | } |
1040 | ||
6de4f3ad AK |
1041 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
1042 | { | |
1043 | switch (reg) { | |
1044 | case VCPU_EXREG_PDPTR: | |
1045 | BUG_ON(!npt_enabled); | |
ff03a073 | 1046 | load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3); |
6de4f3ad AK |
1047 | break; |
1048 | default: | |
1049 | BUG(); | |
1050 | } | |
1051 | } | |
1052 | ||
f0b85051 AG |
1053 | static void svm_set_vintr(struct vcpu_svm *svm) |
1054 | { | |
1055 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
1056 | } | |
1057 | ||
1058 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1059 | { | |
1060 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1061 | } | |
1062 | ||
6aa8b732 AK |
1063 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1064 | { | |
a2fa3e9f | 1065 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1066 | |
1067 | switch (seg) { | |
1068 | case VCPU_SREG_CS: return &save->cs; | |
1069 | case VCPU_SREG_DS: return &save->ds; | |
1070 | case VCPU_SREG_ES: return &save->es; | |
1071 | case VCPU_SREG_FS: return &save->fs; | |
1072 | case VCPU_SREG_GS: return &save->gs; | |
1073 | case VCPU_SREG_SS: return &save->ss; | |
1074 | case VCPU_SREG_TR: return &save->tr; | |
1075 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1076 | } | |
1077 | BUG(); | |
8b6d44c7 | 1078 | return NULL; |
6aa8b732 AK |
1079 | } |
1080 | ||
1081 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1082 | { | |
1083 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1084 | ||
1085 | return s->base; | |
1086 | } | |
1087 | ||
1088 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1089 | struct kvm_segment *var, int seg) | |
1090 | { | |
1091 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1092 | ||
1093 | var->base = s->base; | |
1094 | var->limit = s->limit; | |
1095 | var->selector = s->selector; | |
1096 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1097 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1098 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1099 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1100 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1101 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1102 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1103 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1104 | |
e0231715 JR |
1105 | /* |
1106 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1107 | * for cross vendor migration purposes by "not present" |
1108 | */ | |
1109 | var->unusable = !var->present || (var->type == 0); | |
1110 | ||
1fbdc7a5 AP |
1111 | switch (seg) { |
1112 | case VCPU_SREG_CS: | |
1113 | /* | |
1114 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1115 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1116 | * Intel's VMENTRY has a check on the 'G' bit. | |
1117 | */ | |
25022acc | 1118 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1119 | break; |
1120 | case VCPU_SREG_TR: | |
1121 | /* | |
1122 | * Work around a bug where the busy flag in the tr selector | |
1123 | * isn't exposed | |
1124 | */ | |
c0d09828 | 1125 | var->type |= 0x2; |
1fbdc7a5 AP |
1126 | break; |
1127 | case VCPU_SREG_DS: | |
1128 | case VCPU_SREG_ES: | |
1129 | case VCPU_SREG_FS: | |
1130 | case VCPU_SREG_GS: | |
1131 | /* | |
1132 | * The accessed bit must always be set in the segment | |
1133 | * descriptor cache, although it can be cleared in the | |
1134 | * descriptor, the cached bit always remains at 1. Since | |
1135 | * Intel has a check on this, set it here to support | |
1136 | * cross-vendor migration. | |
1137 | */ | |
1138 | if (!var->unusable) | |
1139 | var->type |= 0x1; | |
1140 | break; | |
b586eb02 | 1141 | case VCPU_SREG_SS: |
e0231715 JR |
1142 | /* |
1143 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1144 | * descriptor is left as 1, although the whole segment has |
1145 | * been made unusable. Clear it here to pass an Intel VMX | |
1146 | * entry check when cross vendor migrating. | |
1147 | */ | |
1148 | if (var->unusable) | |
1149 | var->db = 0; | |
1150 | break; | |
1fbdc7a5 | 1151 | } |
6aa8b732 AK |
1152 | } |
1153 | ||
2e4d2653 IE |
1154 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1155 | { | |
1156 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1157 | ||
1158 | return save->cpl; | |
1159 | } | |
1160 | ||
89a27f4d | 1161 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1162 | { |
a2fa3e9f GH |
1163 | struct vcpu_svm *svm = to_svm(vcpu); |
1164 | ||
89a27f4d GN |
1165 | dt->size = svm->vmcb->save.idtr.limit; |
1166 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1167 | } |
1168 | ||
89a27f4d | 1169 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1170 | { |
a2fa3e9f GH |
1171 | struct vcpu_svm *svm = to_svm(vcpu); |
1172 | ||
89a27f4d GN |
1173 | svm->vmcb->save.idtr.limit = dt->size; |
1174 | svm->vmcb->save.idtr.base = dt->address ; | |
6aa8b732 AK |
1175 | } |
1176 | ||
89a27f4d | 1177 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1178 | { |
a2fa3e9f GH |
1179 | struct vcpu_svm *svm = to_svm(vcpu); |
1180 | ||
89a27f4d GN |
1181 | dt->size = svm->vmcb->save.gdtr.limit; |
1182 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1183 | } |
1184 | ||
89a27f4d | 1185 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1186 | { |
a2fa3e9f GH |
1187 | struct vcpu_svm *svm = to_svm(vcpu); |
1188 | ||
89a27f4d GN |
1189 | svm->vmcb->save.gdtr.limit = dt->size; |
1190 | svm->vmcb->save.gdtr.base = dt->address ; | |
6aa8b732 AK |
1191 | } |
1192 | ||
e8467fda AK |
1193 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1194 | { | |
1195 | } | |
1196 | ||
25c4c276 | 1197 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1198 | { |
1199 | } | |
1200 | ||
d225157b AK |
1201 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1202 | { | |
66a562f7 | 1203 | struct vmcb *vmcb = svm->vmcb; |
d225157b AK |
1204 | ulong gcr0 = svm->vcpu.arch.cr0; |
1205 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1206 | ||
1207 | if (!svm->vcpu.fpu_active) | |
1208 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1209 | else | |
1210 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1211 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1212 | ||
1213 | ||
1214 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
66a562f7 JR |
1215 | vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; |
1216 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
1217 | if (is_nested(svm)) { | |
1218 | struct vmcb *hsave = svm->nested.hsave; | |
1219 | ||
1220 | hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; | |
1221 | hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
1222 | vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read; | |
1223 | vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write; | |
1224 | } | |
d225157b AK |
1225 | } else { |
1226 | svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
1227 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
66a562f7 JR |
1228 | if (is_nested(svm)) { |
1229 | struct vmcb *hsave = svm->nested.hsave; | |
1230 | ||
1231 | hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
1232 | hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
1233 | } | |
d225157b AK |
1234 | } |
1235 | } | |
1236 | ||
6aa8b732 AK |
1237 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1238 | { | |
a2fa3e9f GH |
1239 | struct vcpu_svm *svm = to_svm(vcpu); |
1240 | ||
7f5d8b56 JR |
1241 | if (is_nested(svm)) { |
1242 | /* | |
1243 | * We are here because we run in nested mode, the host kvm | |
1244 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1245 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1246 | * This needs to be checked here. | |
1247 | */ | |
1248 | unsigned long old, new; | |
1249 | ||
1250 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1251 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1252 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1253 | ||
1254 | if (old == new) { | |
1255 | /* cr0 write with ts and mp unchanged */ | |
1256 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
cda00082 JR |
1257 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) { |
1258 | svm->nested.vmexit_rip = kvm_rip_read(vcpu); | |
1259 | svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
1260 | svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
7f5d8b56 | 1261 | return; |
cda00082 | 1262 | } |
7f5d8b56 JR |
1263 | } |
1264 | } | |
1265 | ||
05b3e0c2 | 1266 | #ifdef CONFIG_X86_64 |
f6801dff | 1267 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1268 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1269 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1270 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1271 | } |
1272 | ||
d77c26fc | 1273 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1274 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1275 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1276 | } |
1277 | } | |
1278 | #endif | |
ad312c7c | 1279 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1280 | |
1281 | if (!npt_enabled) | |
1282 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1283 | |
1284 | if (!vcpu->fpu_active) | |
334df50a | 1285 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1286 | /* |
1287 | * re-enable caching here because the QEMU bios | |
1288 | * does not do it - this results in some delay at | |
1289 | * reboot | |
1290 | */ | |
1291 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1292 | svm->vmcb->save.cr0 = cr0; |
d225157b | 1293 | update_cr0_intercept(svm); |
6aa8b732 AK |
1294 | } |
1295 | ||
1296 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1297 | { | |
6394b649 | 1298 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1299 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1300 | ||
1301 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1302 | force_new_asid(vcpu); | |
6394b649 | 1303 | |
ec077263 JR |
1304 | vcpu->arch.cr4 = cr4; |
1305 | if (!npt_enabled) | |
1306 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1307 | cr4 |= host_cr4_mce; |
ec077263 | 1308 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1309 | } |
1310 | ||
1311 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1312 | struct kvm_segment *var, int seg) | |
1313 | { | |
a2fa3e9f | 1314 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1315 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1316 | ||
1317 | s->base = var->base; | |
1318 | s->limit = var->limit; | |
1319 | s->selector = var->selector; | |
1320 | if (var->unusable) | |
1321 | s->attrib = 0; | |
1322 | else { | |
1323 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1324 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1325 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1326 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1327 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1328 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1329 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1330 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1331 | } | |
1332 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1333 | svm->vmcb->save.cpl |
1334 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1335 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1336 | ||
1337 | } | |
1338 | ||
44c11430 | 1339 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1340 | { |
d0bfb940 JK |
1341 | struct vcpu_svm *svm = to_svm(vcpu); |
1342 | ||
d0bfb940 JK |
1343 | svm->vmcb->control.intercept_exceptions &= |
1344 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 | 1345 | |
6be7d306 | 1346 | if (svm->nmi_singlestep) |
44c11430 GN |
1347 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); |
1348 | ||
d0bfb940 JK |
1349 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1350 | if (vcpu->guest_debug & | |
1351 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1352 | svm->vmcb->control.intercept_exceptions |= | |
1353 | 1 << DB_VECTOR; | |
1354 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1355 | svm->vmcb->control.intercept_exceptions |= | |
1356 | 1 << BP_VECTOR; | |
1357 | } else | |
1358 | vcpu->guest_debug = 0; | |
44c11430 GN |
1359 | } |
1360 | ||
355be0b9 | 1361 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1362 | { |
44c11430 GN |
1363 | struct vcpu_svm *svm = to_svm(vcpu); |
1364 | ||
ae675ef0 JK |
1365 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1366 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1367 | else | |
1368 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1369 | ||
355be0b9 | 1370 | update_db_intercept(vcpu); |
6aa8b732 AK |
1371 | } |
1372 | ||
0fe1e009 | 1373 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1374 | { |
0fe1e009 TH |
1375 | if (sd->next_asid > sd->max_asid) { |
1376 | ++sd->asid_generation; | |
1377 | sd->next_asid = 1; | |
a2fa3e9f | 1378 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1379 | } |
1380 | ||
0fe1e009 TH |
1381 | svm->asid_generation = sd->asid_generation; |
1382 | svm->vmcb->control.asid = sd->next_asid++; | |
6aa8b732 AK |
1383 | } |
1384 | ||
020df079 | 1385 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1386 | { |
42dbaa5a | 1387 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1388 | |
020df079 | 1389 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
1390 | } |
1391 | ||
851ba692 | 1392 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1393 | { |
631bc487 | 1394 | u64 fault_address = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1395 | u32 error_code; |
631bc487 | 1396 | int r = 1; |
6aa8b732 | 1397 | |
631bc487 GN |
1398 | switch (svm->apf_reason) { |
1399 | default: | |
1400 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1401 | |
631bc487 GN |
1402 | trace_kvm_page_fault(fault_address, error_code); |
1403 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) | |
1404 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
1405 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); | |
1406 | break; | |
1407 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
1408 | svm->apf_reason = 0; | |
1409 | local_irq_disable(); | |
1410 | kvm_async_pf_task_wait(fault_address); | |
1411 | local_irq_enable(); | |
1412 | break; | |
1413 | case KVM_PV_REASON_PAGE_READY: | |
1414 | svm->apf_reason = 0; | |
1415 | local_irq_disable(); | |
1416 | kvm_async_pf_task_wake(fault_address); | |
1417 | local_irq_enable(); | |
1418 | break; | |
1419 | } | |
1420 | return r; | |
6aa8b732 AK |
1421 | } |
1422 | ||
851ba692 | 1423 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1424 | { |
851ba692 AK |
1425 | struct kvm_run *kvm_run = svm->vcpu.run; |
1426 | ||
d0bfb940 | 1427 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1428 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1429 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1430 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1431 | return 1; | |
1432 | } | |
44c11430 | 1433 | |
6be7d306 JK |
1434 | if (svm->nmi_singlestep) { |
1435 | svm->nmi_singlestep = false; | |
44c11430 GN |
1436 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1437 | svm->vmcb->save.rflags &= | |
1438 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1439 | update_db_intercept(&svm->vcpu); | |
1440 | } | |
1441 | ||
1442 | if (svm->vcpu.guest_debug & | |
e0231715 | 1443 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1444 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1445 | kvm_run->debug.arch.pc = | |
1446 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1447 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | return 1; | |
d0bfb940 JK |
1452 | } |
1453 | ||
851ba692 | 1454 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1455 | { |
851ba692 AK |
1456 | struct kvm_run *kvm_run = svm->vcpu.run; |
1457 | ||
d0bfb940 JK |
1458 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1459 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1460 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1461 | return 0; | |
1462 | } | |
1463 | ||
851ba692 | 1464 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1465 | { |
1466 | int er; | |
1467 | ||
851ba692 | 1468 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1469 | if (er != EMULATE_DONE) |
7ee5d940 | 1470 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1471 | return 1; |
1472 | } | |
1473 | ||
6b52d186 | 1474 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1475 | { |
6b52d186 | 1476 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 JR |
1477 | u32 excp; |
1478 | ||
1479 | if (is_nested(svm)) { | |
1480 | u32 h_excp, n_excp; | |
1481 | ||
1482 | h_excp = svm->nested.hsave->control.intercept_exceptions; | |
1483 | n_excp = svm->nested.intercept_exceptions; | |
1484 | h_excp &= ~(1 << NM_VECTOR); | |
1485 | excp = h_excp | n_excp; | |
1486 | } else { | |
1487 | excp = svm->vmcb->control.intercept_exceptions; | |
e0231715 | 1488 | excp &= ~(1 << NM_VECTOR); |
66a562f7 JR |
1489 | } |
1490 | ||
1491 | svm->vmcb->control.intercept_exceptions = excp; | |
1492 | ||
e756fc62 | 1493 | svm->vcpu.fpu_active = 1; |
d225157b | 1494 | update_cr0_intercept(svm); |
6b52d186 | 1495 | } |
a2fa3e9f | 1496 | |
6b52d186 AK |
1497 | static int nm_interception(struct vcpu_svm *svm) |
1498 | { | |
1499 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1500 | return 1; |
7807fa6c AL |
1501 | } |
1502 | ||
67ec6607 JR |
1503 | static bool is_erratum_383(void) |
1504 | { | |
1505 | int err, i; | |
1506 | u64 value; | |
1507 | ||
1508 | if (!erratum_383_found) | |
1509 | return false; | |
1510 | ||
1511 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1512 | if (err) | |
1513 | return false; | |
1514 | ||
1515 | /* Bit 62 may or may not be set for this mce */ | |
1516 | value &= ~(1ULL << 62); | |
1517 | ||
1518 | if (value != 0xb600000000010015ULL) | |
1519 | return false; | |
1520 | ||
1521 | /* Clear MCi_STATUS registers */ | |
1522 | for (i = 0; i < 6; ++i) | |
1523 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1524 | ||
1525 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1526 | if (!err) { | |
1527 | u32 low, high; | |
1528 | ||
1529 | value &= ~(1ULL << 2); | |
1530 | low = lower_32_bits(value); | |
1531 | high = upper_32_bits(value); | |
1532 | ||
1533 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1534 | } | |
1535 | ||
1536 | /* Flush tlb to evict multi-match entries */ | |
1537 | __flush_tlb_all(); | |
1538 | ||
1539 | return true; | |
1540 | } | |
1541 | ||
fe5913e4 | 1542 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1543 | { |
67ec6607 JR |
1544 | if (is_erratum_383()) { |
1545 | /* | |
1546 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1547 | * guest. | |
1548 | */ | |
1549 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1550 | ||
a8eeb04a | 1551 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1552 | |
1553 | return; | |
1554 | } | |
1555 | ||
53371b50 JR |
1556 | /* |
1557 | * On an #MC intercept the MCE handler is not called automatically in | |
1558 | * the host. So do it by hand here. | |
1559 | */ | |
1560 | asm volatile ( | |
1561 | "int $0x12\n"); | |
1562 | /* not sure if we ever come back to this point */ | |
1563 | ||
fe5913e4 JR |
1564 | return; |
1565 | } | |
1566 | ||
1567 | static int mc_interception(struct vcpu_svm *svm) | |
1568 | { | |
53371b50 JR |
1569 | return 1; |
1570 | } | |
1571 | ||
851ba692 | 1572 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1573 | { |
851ba692 AK |
1574 | struct kvm_run *kvm_run = svm->vcpu.run; |
1575 | ||
46fe4ddd JR |
1576 | /* |
1577 | * VMCB is undefined after a SHUTDOWN intercept | |
1578 | * so reinitialize it. | |
1579 | */ | |
a2fa3e9f | 1580 | clear_page(svm->vmcb); |
e6101a96 | 1581 | init_vmcb(svm); |
46fe4ddd JR |
1582 | |
1583 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1584 | return 0; | |
1585 | } | |
1586 | ||
851ba692 | 1587 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1588 | { |
cf8f70bf | 1589 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1590 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1591 | int size, in, string; |
039576c0 | 1592 | unsigned port; |
6aa8b732 | 1593 | |
e756fc62 | 1594 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1595 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1596 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1597 | if (string || in) |
6d77dbfc | 1598 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; |
cf8f70bf | 1599 | |
039576c0 AK |
1600 | port = io_info >> 16; |
1601 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1602 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1603 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1604 | |
1605 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1606 | } |
1607 | ||
851ba692 | 1608 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1609 | { |
1610 | return 1; | |
1611 | } | |
1612 | ||
851ba692 | 1613 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1614 | { |
1615 | ++svm->vcpu.stat.irq_exits; | |
1616 | return 1; | |
1617 | } | |
1618 | ||
851ba692 | 1619 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1620 | { |
1621 | return 1; | |
1622 | } | |
1623 | ||
851ba692 | 1624 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1625 | { |
5fdbf976 | 1626 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1627 | skip_emulated_instruction(&svm->vcpu); |
1628 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1629 | } |
1630 | ||
851ba692 | 1631 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1632 | { |
5fdbf976 | 1633 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1634 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1635 | kvm_emulate_hypercall(&svm->vcpu); |
1636 | return 1; | |
02e235bc AK |
1637 | } |
1638 | ||
5bd2edc3 JR |
1639 | static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu) |
1640 | { | |
1641 | struct vcpu_svm *svm = to_svm(vcpu); | |
1642 | ||
1643 | return svm->nested.nested_cr3; | |
1644 | } | |
1645 | ||
1646 | static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu, | |
1647 | unsigned long root) | |
1648 | { | |
1649 | struct vcpu_svm *svm = to_svm(vcpu); | |
1650 | ||
1651 | svm->vmcb->control.nested_cr3 = root; | |
1652 | force_new_asid(vcpu); | |
1653 | } | |
1654 | ||
1655 | static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu) | |
1656 | { | |
1657 | struct vcpu_svm *svm = to_svm(vcpu); | |
1658 | ||
1659 | svm->vmcb->control.exit_code = SVM_EXIT_NPF; | |
1660 | svm->vmcb->control.exit_code_hi = 0; | |
1661 | svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code; | |
1662 | svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address; | |
1663 | ||
1664 | nested_svm_vmexit(svm); | |
1665 | } | |
1666 | ||
4b16184c JR |
1667 | static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu) |
1668 | { | |
1669 | int r; | |
1670 | ||
1671 | r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu); | |
1672 | ||
1673 | vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3; | |
1674 | vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3; | |
1675 | vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit; | |
1676 | vcpu->arch.mmu.shadow_root_level = get_npt_level(); | |
1677 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
1678 | ||
1679 | return r; | |
1680 | } | |
1681 | ||
1682 | static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
1683 | { | |
1684 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
1685 | } | |
1686 | ||
c0725420 AG |
1687 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1688 | { | |
f6801dff | 1689 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1690 | || !is_paging(&svm->vcpu)) { |
1691 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1692 | return 1; | |
1693 | } | |
1694 | ||
1695 | if (svm->vmcb->save.cpl) { | |
1696 | kvm_inject_gp(&svm->vcpu, 0); | |
1697 | return 1; | |
1698 | } | |
1699 | ||
1700 | return 0; | |
1701 | } | |
1702 | ||
cf74a78b AG |
1703 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1704 | bool has_error_code, u32 error_code) | |
1705 | { | |
b8e88bc8 JR |
1706 | int vmexit; |
1707 | ||
0295ad7d JR |
1708 | if (!is_nested(svm)) |
1709 | return 0; | |
cf74a78b | 1710 | |
0295ad7d JR |
1711 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1712 | svm->vmcb->control.exit_code_hi = 0; | |
1713 | svm->vmcb->control.exit_info_1 = error_code; | |
1714 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1715 | ||
b8e88bc8 JR |
1716 | vmexit = nested_svm_intercept(svm); |
1717 | if (vmexit == NESTED_EXIT_DONE) | |
1718 | svm->nested.exit_required = true; | |
1719 | ||
1720 | return vmexit; | |
cf74a78b AG |
1721 | } |
1722 | ||
8fe54654 JR |
1723 | /* This function returns true if it is save to enable the irq window */ |
1724 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1725 | { |
26666957 | 1726 | if (!is_nested(svm)) |
8fe54654 | 1727 | return true; |
cf74a78b | 1728 | |
26666957 | 1729 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1730 | return true; |
cf74a78b | 1731 | |
26666957 | 1732 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1733 | return false; |
cf74a78b | 1734 | |
a0a07cd2 GN |
1735 | /* |
1736 | * if vmexit was already requested (by intercepted exception | |
1737 | * for instance) do not overwrite it with "external interrupt" | |
1738 | * vmexit. | |
1739 | */ | |
1740 | if (svm->nested.exit_required) | |
1741 | return false; | |
1742 | ||
197717d5 JR |
1743 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1744 | svm->vmcb->control.exit_info_1 = 0; | |
1745 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1746 | |
cd3ff653 JR |
1747 | if (svm->nested.intercept & 1ULL) { |
1748 | /* | |
1749 | * The #vmexit can't be emulated here directly because this | |
1750 | * code path runs with irqs and preemtion disabled. A | |
1751 | * #vmexit emulation might sleep. Only signal request for | |
1752 | * the #vmexit here. | |
1753 | */ | |
1754 | svm->nested.exit_required = true; | |
236649de | 1755 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1756 | return false; |
cf74a78b AG |
1757 | } |
1758 | ||
8fe54654 | 1759 | return true; |
cf74a78b AG |
1760 | } |
1761 | ||
887f500c JR |
1762 | /* This function returns true if it is save to enable the nmi window */ |
1763 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1764 | { | |
1765 | if (!is_nested(svm)) | |
1766 | return true; | |
1767 | ||
1768 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1769 | return true; | |
1770 | ||
1771 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1772 | svm->nested.exit_required = true; | |
1773 | ||
1774 | return false; | |
cf74a78b AG |
1775 | } |
1776 | ||
7597f129 | 1777 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1778 | { |
1779 | struct page *page; | |
1780 | ||
6c3bd3d7 JR |
1781 | might_sleep(); |
1782 | ||
34f80cfa | 1783 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1784 | if (is_error_page(page)) |
1785 | goto error; | |
1786 | ||
7597f129 JR |
1787 | *_page = page; |
1788 | ||
1789 | return kmap(page); | |
34f80cfa JR |
1790 | |
1791 | error: | |
1792 | kvm_release_page_clean(page); | |
1793 | kvm_inject_gp(&svm->vcpu, 0); | |
1794 | ||
1795 | return NULL; | |
1796 | } | |
1797 | ||
7597f129 | 1798 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1799 | { |
7597f129 | 1800 | kunmap(page); |
34f80cfa JR |
1801 | kvm_release_page_dirty(page); |
1802 | } | |
34f80cfa | 1803 | |
ce2ac085 JR |
1804 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1805 | { | |
1806 | unsigned port; | |
1807 | u8 val, bit; | |
1808 | u64 gpa; | |
34f80cfa | 1809 | |
ce2ac085 JR |
1810 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1811 | return NESTED_EXIT_HOST; | |
34f80cfa | 1812 | |
ce2ac085 JR |
1813 | port = svm->vmcb->control.exit_info_1 >> 16; |
1814 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1815 | bit = port % 8; | |
1816 | val = 0; | |
1817 | ||
1818 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1819 | val &= (1 << bit); | |
1820 | ||
1821 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1822 | } |
1823 | ||
d2477826 | 1824 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1825 | { |
0d6b3537 JR |
1826 | u32 offset, msr, value; |
1827 | int write, mask; | |
4c2161ae | 1828 | |
3d62d9aa | 1829 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1830 | return NESTED_EXIT_HOST; |
3d62d9aa | 1831 | |
0d6b3537 JR |
1832 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1833 | offset = svm_msrpm_offset(msr); | |
1834 | write = svm->vmcb->control.exit_info_1 & 1; | |
1835 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1836 | |
0d6b3537 JR |
1837 | if (offset == MSR_INVALID) |
1838 | return NESTED_EXIT_DONE; | |
4c2161ae | 1839 | |
0d6b3537 JR |
1840 | /* Offset is in 32 bit units but need in 8 bit units */ |
1841 | offset *= 4; | |
4c2161ae | 1842 | |
0d6b3537 JR |
1843 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1844 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1845 | |
0d6b3537 | 1846 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1847 | } |
1848 | ||
410e4d57 | 1849 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1850 | { |
cf74a78b | 1851 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1852 | |
410e4d57 JR |
1853 | switch (exit_code) { |
1854 | case SVM_EXIT_INTR: | |
1855 | case SVM_EXIT_NMI: | |
ff47a49b | 1856 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1857 | return NESTED_EXIT_HOST; |
410e4d57 | 1858 | case SVM_EXIT_NPF: |
e0231715 | 1859 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1860 | if (npt_enabled) |
1861 | return NESTED_EXIT_HOST; | |
1862 | break; | |
410e4d57 | 1863 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
631bc487 GN |
1864 | /* When we're shadowing, trap PFs, but not async PF */ |
1865 | if (!npt_enabled && svm->apf_reason == 0) | |
410e4d57 JR |
1866 | return NESTED_EXIT_HOST; |
1867 | break; | |
66a562f7 JR |
1868 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1869 | nm_interception(svm); | |
1870 | break; | |
410e4d57 JR |
1871 | default: |
1872 | break; | |
cf74a78b AG |
1873 | } |
1874 | ||
410e4d57 JR |
1875 | return NESTED_EXIT_CONTINUE; |
1876 | } | |
1877 | ||
1878 | /* | |
1879 | * If this function returns true, this #vmexit was already handled | |
1880 | */ | |
b8e88bc8 | 1881 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
1882 | { |
1883 | u32 exit_code = svm->vmcb->control.exit_code; | |
1884 | int vmexit = NESTED_EXIT_HOST; | |
1885 | ||
cf74a78b | 1886 | switch (exit_code) { |
9c4e40b9 | 1887 | case SVM_EXIT_MSR: |
3d62d9aa | 1888 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1889 | break; |
ce2ac085 JR |
1890 | case SVM_EXIT_IOIO: |
1891 | vmexit = nested_svm_intercept_ioio(svm); | |
1892 | break; | |
cf74a78b AG |
1893 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { |
1894 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
aad42c64 | 1895 | if (svm->nested.intercept_cr_read & cr_bits) |
410e4d57 | 1896 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1897 | break; |
1898 | } | |
1899 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1900 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
aad42c64 | 1901 | if (svm->nested.intercept_cr_write & cr_bits) |
410e4d57 | 1902 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1903 | break; |
1904 | } | |
1905 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1906 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
aad42c64 | 1907 | if (svm->nested.intercept_dr_read & dr_bits) |
410e4d57 | 1908 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1909 | break; |
1910 | } | |
1911 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1912 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
aad42c64 | 1913 | if (svm->nested.intercept_dr_write & dr_bits) |
410e4d57 | 1914 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1915 | break; |
1916 | } | |
1917 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1918 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1919 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1920 | vmexit = NESTED_EXIT_DONE; |
631bc487 GN |
1921 | /* async page fault always cause vmexit */ |
1922 | else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) && | |
1923 | svm->apf_reason != 0) | |
1924 | vmexit = NESTED_EXIT_DONE; | |
cf74a78b AG |
1925 | break; |
1926 | } | |
228070b1 JR |
1927 | case SVM_EXIT_ERR: { |
1928 | vmexit = NESTED_EXIT_DONE; | |
1929 | break; | |
1930 | } | |
cf74a78b AG |
1931 | default: { |
1932 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 1933 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1934 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1935 | } |
1936 | } | |
1937 | ||
b8e88bc8 JR |
1938 | return vmexit; |
1939 | } | |
1940 | ||
1941 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1942 | { | |
1943 | int vmexit; | |
1944 | ||
1945 | vmexit = nested_svm_intercept(svm); | |
1946 | ||
1947 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 1948 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
1949 | |
1950 | return vmexit; | |
cf74a78b AG |
1951 | } |
1952 | ||
0460a979 JR |
1953 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1954 | { | |
1955 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1956 | struct vmcb_control_area *from = &from_vmcb->control; | |
1957 | ||
1958 | dst->intercept_cr_read = from->intercept_cr_read; | |
1959 | dst->intercept_cr_write = from->intercept_cr_write; | |
1960 | dst->intercept_dr_read = from->intercept_dr_read; | |
1961 | dst->intercept_dr_write = from->intercept_dr_write; | |
1962 | dst->intercept_exceptions = from->intercept_exceptions; | |
1963 | dst->intercept = from->intercept; | |
1964 | dst->iopm_base_pa = from->iopm_base_pa; | |
1965 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1966 | dst->tsc_offset = from->tsc_offset; | |
1967 | dst->asid = from->asid; | |
1968 | dst->tlb_ctl = from->tlb_ctl; | |
1969 | dst->int_ctl = from->int_ctl; | |
1970 | dst->int_vector = from->int_vector; | |
1971 | dst->int_state = from->int_state; | |
1972 | dst->exit_code = from->exit_code; | |
1973 | dst->exit_code_hi = from->exit_code_hi; | |
1974 | dst->exit_info_1 = from->exit_info_1; | |
1975 | dst->exit_info_2 = from->exit_info_2; | |
1976 | dst->exit_int_info = from->exit_int_info; | |
1977 | dst->exit_int_info_err = from->exit_int_info_err; | |
1978 | dst->nested_ctl = from->nested_ctl; | |
1979 | dst->event_inj = from->event_inj; | |
1980 | dst->event_inj_err = from->event_inj_err; | |
1981 | dst->nested_cr3 = from->nested_cr3; | |
1982 | dst->lbr_ctl = from->lbr_ctl; | |
1983 | } | |
1984 | ||
34f80cfa | 1985 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 1986 | { |
34f80cfa | 1987 | struct vmcb *nested_vmcb; |
e6aa9abd | 1988 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 1989 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 1990 | struct page *page; |
cf74a78b | 1991 | |
17897f36 JR |
1992 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
1993 | vmcb->control.exit_info_1, | |
1994 | vmcb->control.exit_info_2, | |
1995 | vmcb->control.exit_int_info, | |
1996 | vmcb->control.exit_int_info_err); | |
1997 | ||
7597f129 | 1998 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
1999 | if (!nested_vmcb) |
2000 | return 1; | |
2001 | ||
06fc7772 JR |
2002 | /* Exit nested SVM mode */ |
2003 | svm->nested.vmcb = 0; | |
2004 | ||
cf74a78b | 2005 | /* Give the current vmcb to the guest */ |
33740e40 JR |
2006 | disable_gif(svm); |
2007 | ||
2008 | nested_vmcb->save.es = vmcb->save.es; | |
2009 | nested_vmcb->save.cs = vmcb->save.cs; | |
2010 | nested_vmcb->save.ss = vmcb->save.ss; | |
2011 | nested_vmcb->save.ds = vmcb->save.ds; | |
2012 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
2013 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
3f6a9d16 | 2014 | nested_vmcb->save.efer = svm->vcpu.arch.efer; |
cdbbdc12 | 2015 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
2be4fc7a | 2016 | nested_vmcb->save.cr3 = svm->vcpu.arch.cr3; |
33740e40 | 2017 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 2018 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
33740e40 JR |
2019 | nested_vmcb->save.rflags = vmcb->save.rflags; |
2020 | nested_vmcb->save.rip = vmcb->save.rip; | |
2021 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
2022 | nested_vmcb->save.rax = vmcb->save.rax; | |
2023 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
2024 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
2025 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
2026 | ||
2027 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
2028 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
2029 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
2030 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
2031 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
2032 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
2033 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
2034 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
2035 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
7a190667 | 2036 | nested_vmcb->control.next_rip = vmcb->control.next_rip; |
8d23c466 AG |
2037 | |
2038 | /* | |
2039 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
2040 | * to make sure that we do not lose injected events. So check event_inj | |
2041 | * here and copy it to exit_int_info if it is valid. | |
2042 | * Exit_int_info and event_inj can't be both valid because the case | |
2043 | * below only happens on a VMRUN instruction intercept which has | |
2044 | * no valid exit_int_info set. | |
2045 | */ | |
2046 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
2047 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
2048 | ||
2049 | nc->exit_int_info = vmcb->control.event_inj; | |
2050 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
2051 | } | |
2052 | ||
33740e40 JR |
2053 | nested_vmcb->control.tlb_ctl = 0; |
2054 | nested_vmcb->control.event_inj = 0; | |
2055 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
2056 | |
2057 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
2058 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
2059 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
2060 | ||
cf74a78b | 2061 | /* Restore the original control entries */ |
0460a979 | 2062 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 2063 | |
219b65dc AG |
2064 | kvm_clear_exception_queue(&svm->vcpu); |
2065 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b | 2066 | |
4b16184c JR |
2067 | svm->nested.nested_cr3 = 0; |
2068 | ||
cf74a78b AG |
2069 | /* Restore selected save entries */ |
2070 | svm->vmcb->save.es = hsave->save.es; | |
2071 | svm->vmcb->save.cs = hsave->save.cs; | |
2072 | svm->vmcb->save.ss = hsave->save.ss; | |
2073 | svm->vmcb->save.ds = hsave->save.ds; | |
2074 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
2075 | svm->vmcb->save.idtr = hsave->save.idtr; | |
2076 | svm->vmcb->save.rflags = hsave->save.rflags; | |
2077 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
2078 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
2079 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
2080 | if (npt_enabled) { | |
2081 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
2082 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
2083 | } else { | |
2390218b | 2084 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
2085 | } |
2086 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
2087 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
2088 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
2089 | svm->vmcb->save.dr7 = 0; | |
2090 | svm->vmcb->save.cpl = 0; | |
2091 | svm->vmcb->control.exit_int_info = 0; | |
2092 | ||
7597f129 | 2093 | nested_svm_unmap(page); |
cf74a78b | 2094 | |
4b16184c | 2095 | nested_svm_uninit_mmu_context(&svm->vcpu); |
cf74a78b AG |
2096 | kvm_mmu_reset_context(&svm->vcpu); |
2097 | kvm_mmu_load(&svm->vcpu); | |
2098 | ||
2099 | return 0; | |
2100 | } | |
3d6368ef | 2101 | |
9738b2c9 | 2102 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 2103 | { |
323c3d80 JR |
2104 | /* |
2105 | * This function merges the msr permission bitmaps of kvm and the | |
2106 | * nested vmcb. It is omptimized in that it only merges the parts where | |
2107 | * the kvm msr permission bitmap may contain zero bits | |
2108 | */ | |
3d6368ef | 2109 | int i; |
9738b2c9 | 2110 | |
323c3d80 JR |
2111 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
2112 | return true; | |
9738b2c9 | 2113 | |
323c3d80 JR |
2114 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
2115 | u32 value, p; | |
2116 | u64 offset; | |
9738b2c9 | 2117 | |
323c3d80 JR |
2118 | if (msrpm_offsets[i] == 0xffffffff) |
2119 | break; | |
3d6368ef | 2120 | |
0d6b3537 JR |
2121 | p = msrpm_offsets[i]; |
2122 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2123 | |
2124 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2125 | return false; | |
2126 | ||
2127 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2128 | } | |
3d6368ef | 2129 | |
323c3d80 | 2130 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2131 | |
2132 | return true; | |
3d6368ef AG |
2133 | } |
2134 | ||
52c65a30 JR |
2135 | static bool nested_vmcb_checks(struct vmcb *vmcb) |
2136 | { | |
2137 | if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0) | |
2138 | return false; | |
2139 | ||
dbe77584 JR |
2140 | if (vmcb->control.asid == 0) |
2141 | return false; | |
2142 | ||
4b16184c JR |
2143 | if (vmcb->control.nested_ctl && !npt_enabled) |
2144 | return false; | |
2145 | ||
52c65a30 JR |
2146 | return true; |
2147 | } | |
2148 | ||
9738b2c9 | 2149 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2150 | { |
9738b2c9 | 2151 | struct vmcb *nested_vmcb; |
e6aa9abd | 2152 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2153 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2154 | struct page *page; |
06fc7772 | 2155 | u64 vmcb_gpa; |
3d6368ef | 2156 | |
06fc7772 | 2157 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2158 | |
7597f129 | 2159 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2160 | if (!nested_vmcb) |
2161 | return false; | |
2162 | ||
52c65a30 JR |
2163 | if (!nested_vmcb_checks(nested_vmcb)) { |
2164 | nested_vmcb->control.exit_code = SVM_EXIT_ERR; | |
2165 | nested_vmcb->control.exit_code_hi = 0; | |
2166 | nested_vmcb->control.exit_info_1 = 0; | |
2167 | nested_vmcb->control.exit_info_2 = 0; | |
2168 | ||
2169 | nested_svm_unmap(page); | |
2170 | ||
2171 | return false; | |
2172 | } | |
2173 | ||
b75f4eb3 | 2174 | trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa, |
0ac406de JR |
2175 | nested_vmcb->save.rip, |
2176 | nested_vmcb->control.int_ctl, | |
2177 | nested_vmcb->control.event_inj, | |
2178 | nested_vmcb->control.nested_ctl); | |
2179 | ||
2e554e8d JR |
2180 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read, |
2181 | nested_vmcb->control.intercept_cr_write, | |
2182 | nested_vmcb->control.intercept_exceptions, | |
2183 | nested_vmcb->control.intercept); | |
2184 | ||
3d6368ef | 2185 | /* Clear internal status */ |
219b65dc AG |
2186 | kvm_clear_exception_queue(&svm->vcpu); |
2187 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2188 | |
e0231715 JR |
2189 | /* |
2190 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2191 | * restore everything when a VMEXIT occurs | |
2192 | */ | |
defbba56 JR |
2193 | hsave->save.es = vmcb->save.es; |
2194 | hsave->save.cs = vmcb->save.cs; | |
2195 | hsave->save.ss = vmcb->save.ss; | |
2196 | hsave->save.ds = vmcb->save.ds; | |
2197 | hsave->save.gdtr = vmcb->save.gdtr; | |
2198 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2199 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2200 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
2201 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
2202 | hsave->save.rflags = vmcb->save.rflags; | |
b75f4eb3 | 2203 | hsave->save.rip = kvm_rip_read(&svm->vcpu); |
defbba56 JR |
2204 | hsave->save.rsp = vmcb->save.rsp; |
2205 | hsave->save.rax = vmcb->save.rax; | |
2206 | if (npt_enabled) | |
2207 | hsave->save.cr3 = vmcb->save.cr3; | |
2208 | else | |
2209 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
2210 | ||
0460a979 | 2211 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
2212 | |
2213 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2214 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2215 | else | |
2216 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2217 | ||
4b16184c JR |
2218 | if (nested_vmcb->control.nested_ctl) { |
2219 | kvm_mmu_unload(&svm->vcpu); | |
2220 | svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3; | |
2221 | nested_svm_init_mmu_context(&svm->vcpu); | |
2222 | } | |
2223 | ||
3d6368ef AG |
2224 | /* Load the nested guest state */ |
2225 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2226 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2227 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2228 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2229 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2230 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2231 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2232 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2233 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2234 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2235 | if (npt_enabled) { | |
2236 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2237 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2238 | } else |
2390218b | 2239 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2240 | |
2241 | /* Guest paging mode is active - reset mmu */ | |
2242 | kvm_mmu_reset_context(&svm->vcpu); | |
2243 | ||
defbba56 | 2244 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2245 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2246 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2247 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2248 | |
3d6368ef AG |
2249 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2250 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2251 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2252 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2253 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2254 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2255 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2256 | ||
f7138538 | 2257 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2258 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2259 | |
aad42c64 JR |
2260 | /* cache intercepts */ |
2261 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
2262 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
2263 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
2264 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
2265 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
2266 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2267 | ||
3d6368ef | 2268 | force_new_asid(&svm->vcpu); |
3d6368ef | 2269 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2270 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2271 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2272 | else | |
2273 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2274 | ||
88ab24ad JR |
2275 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2276 | /* We only want the cr8 intercept bits of the guest */ | |
2277 | svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK; | |
2278 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
2279 | } | |
2280 | ||
0d945bd9 JR |
2281 | /* We don't want to see VMMCALLs from a nested guest */ |
2282 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL); | |
2283 | ||
e0231715 JR |
2284 | /* |
2285 | * We don't want a nested guest to be more powerful than the guest, so | |
2286 | * all intercepts are ORed | |
2287 | */ | |
88ab24ad JR |
2288 | svm->vmcb->control.intercept_cr_read |= |
2289 | nested_vmcb->control.intercept_cr_read; | |
2290 | svm->vmcb->control.intercept_cr_write |= | |
2291 | nested_vmcb->control.intercept_cr_write; | |
2292 | svm->vmcb->control.intercept_dr_read |= | |
2293 | nested_vmcb->control.intercept_dr_read; | |
2294 | svm->vmcb->control.intercept_dr_write |= | |
2295 | nested_vmcb->control.intercept_dr_write; | |
2296 | svm->vmcb->control.intercept_exceptions |= | |
2297 | nested_vmcb->control.intercept_exceptions; | |
2298 | ||
2299 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
2300 | ||
2301 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; | |
3d6368ef AG |
2302 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2303 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2304 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2305 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2306 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2307 | ||
7597f129 | 2308 | nested_svm_unmap(page); |
9738b2c9 | 2309 | |
06fc7772 JR |
2310 | /* nested_vmcb is our indicator if nested SVM is activated */ |
2311 | svm->nested.vmcb = vmcb_gpa; | |
9738b2c9 | 2312 | |
2af9194d | 2313 | enable_gif(svm); |
3d6368ef | 2314 | |
9738b2c9 | 2315 | return true; |
3d6368ef AG |
2316 | } |
2317 | ||
9966bf68 | 2318 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2319 | { |
2320 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2321 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2322 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2323 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2324 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2325 | to_vmcb->save.star = from_vmcb->save.star; | |
2326 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2327 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2328 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2329 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2330 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2331 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2332 | } |
2333 | ||
851ba692 | 2334 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2335 | { |
9966bf68 | 2336 | struct vmcb *nested_vmcb; |
7597f129 | 2337 | struct page *page; |
9966bf68 | 2338 | |
5542675b AG |
2339 | if (nested_svm_check_permissions(svm)) |
2340 | return 1; | |
2341 | ||
2342 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2343 | skip_emulated_instruction(&svm->vcpu); | |
2344 | ||
7597f129 | 2345 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2346 | if (!nested_vmcb) |
2347 | return 1; | |
2348 | ||
2349 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2350 | nested_svm_unmap(page); |
5542675b AG |
2351 | |
2352 | return 1; | |
2353 | } | |
2354 | ||
851ba692 | 2355 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2356 | { |
9966bf68 | 2357 | struct vmcb *nested_vmcb; |
7597f129 | 2358 | struct page *page; |
9966bf68 | 2359 | |
5542675b AG |
2360 | if (nested_svm_check_permissions(svm)) |
2361 | return 1; | |
2362 | ||
2363 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2364 | skip_emulated_instruction(&svm->vcpu); | |
2365 | ||
7597f129 | 2366 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2367 | if (!nested_vmcb) |
2368 | return 1; | |
2369 | ||
2370 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2371 | nested_svm_unmap(page); |
5542675b AG |
2372 | |
2373 | return 1; | |
2374 | } | |
2375 | ||
851ba692 | 2376 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2377 | { |
3d6368ef AG |
2378 | if (nested_svm_check_permissions(svm)) |
2379 | return 1; | |
2380 | ||
b75f4eb3 RJ |
2381 | /* Save rip after vmrun instruction */ |
2382 | kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3); | |
3d6368ef | 2383 | |
9738b2c9 | 2384 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2385 | return 1; |
2386 | ||
9738b2c9 | 2387 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2388 | goto failed; |
2389 | ||
2390 | return 1; | |
2391 | ||
2392 | failed: | |
2393 | ||
2394 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2395 | svm->vmcb->control.exit_code_hi = 0; | |
2396 | svm->vmcb->control.exit_info_1 = 0; | |
2397 | svm->vmcb->control.exit_info_2 = 0; | |
2398 | ||
2399 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2400 | |
2401 | return 1; | |
2402 | } | |
2403 | ||
851ba692 | 2404 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2405 | { |
2406 | if (nested_svm_check_permissions(svm)) | |
2407 | return 1; | |
2408 | ||
2409 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2410 | skip_emulated_instruction(&svm->vcpu); | |
3842d135 | 2411 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
1371d904 | 2412 | |
2af9194d | 2413 | enable_gif(svm); |
1371d904 AG |
2414 | |
2415 | return 1; | |
2416 | } | |
2417 | ||
851ba692 | 2418 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2419 | { |
2420 | if (nested_svm_check_permissions(svm)) | |
2421 | return 1; | |
2422 | ||
2423 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2424 | skip_emulated_instruction(&svm->vcpu); | |
2425 | ||
2af9194d | 2426 | disable_gif(svm); |
1371d904 AG |
2427 | |
2428 | /* After a CLGI no interrupts should come */ | |
2429 | svm_clear_vintr(svm); | |
2430 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2431 | ||
2432 | return 1; | |
2433 | } | |
2434 | ||
851ba692 | 2435 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2436 | { |
2437 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2438 | |
ec1ff790 JR |
2439 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2440 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2441 | ||
ff092385 AG |
2442 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2443 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2444 | ||
2445 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2446 | skip_emulated_instruction(&svm->vcpu); | |
2447 | return 1; | |
2448 | } | |
2449 | ||
532a46b9 JR |
2450 | static int skinit_interception(struct vcpu_svm *svm) |
2451 | { | |
2452 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2453 | ||
2454 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2455 | return 1; | |
2456 | } | |
2457 | ||
851ba692 | 2458 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2459 | { |
7ee5d940 | 2460 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2461 | return 1; |
2462 | } | |
2463 | ||
851ba692 | 2464 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2465 | { |
37817f29 | 2466 | u16 tss_selector; |
64a7ec06 GN |
2467 | int reason; |
2468 | int int_type = svm->vmcb->control.exit_int_info & | |
2469 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2470 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2471 | uint32_t type = |
2472 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2473 | uint32_t idt_v = | |
2474 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2475 | bool has_error_code = false; |
2476 | u32 error_code = 0; | |
37817f29 IE |
2477 | |
2478 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2479 | |
37817f29 IE |
2480 | if (svm->vmcb->control.exit_info_2 & |
2481 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2482 | reason = TASK_SWITCH_IRET; |
2483 | else if (svm->vmcb->control.exit_info_2 & | |
2484 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2485 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2486 | else if (idt_v) |
64a7ec06 GN |
2487 | reason = TASK_SWITCH_GATE; |
2488 | else | |
2489 | reason = TASK_SWITCH_CALL; | |
2490 | ||
fe8e7f83 GN |
2491 | if (reason == TASK_SWITCH_GATE) { |
2492 | switch (type) { | |
2493 | case SVM_EXITINTINFO_TYPE_NMI: | |
2494 | svm->vcpu.arch.nmi_injected = false; | |
2495 | break; | |
2496 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2497 | if (svm->vmcb->control.exit_info_2 & |
2498 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2499 | has_error_code = true; | |
2500 | error_code = | |
2501 | (u32)svm->vmcb->control.exit_info_2; | |
2502 | } | |
fe8e7f83 GN |
2503 | kvm_clear_exception_queue(&svm->vcpu); |
2504 | break; | |
2505 | case SVM_EXITINTINFO_TYPE_INTR: | |
2506 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2507 | break; | |
2508 | default: | |
2509 | break; | |
2510 | } | |
2511 | } | |
64a7ec06 | 2512 | |
8317c298 GN |
2513 | if (reason != TASK_SWITCH_GATE || |
2514 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2515 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2516 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2517 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2518 | |
acb54517 GN |
2519 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2520 | has_error_code, error_code) == EMULATE_FAIL) { | |
2521 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2522 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2523 | svm->vcpu.run->internal.ndata = 0; | |
2524 | return 0; | |
2525 | } | |
2526 | return 1; | |
6aa8b732 AK |
2527 | } |
2528 | ||
851ba692 | 2529 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2530 | { |
5fdbf976 | 2531 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2532 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2533 | return 1; |
6aa8b732 AK |
2534 | } |
2535 | ||
851ba692 | 2536 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2537 | { |
2538 | ++svm->vcpu.stat.nmi_window_exits; | |
061e2fd1 | 2539 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); |
44c11430 | 2540 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2541 | return 1; |
2542 | } | |
2543 | ||
851ba692 | 2544 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2545 | { |
6d77dbfc | 2546 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
a7052897 MT |
2547 | } |
2548 | ||
851ba692 | 2549 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2550 | { |
6d77dbfc | 2551 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
6aa8b732 AK |
2552 | } |
2553 | ||
cda00082 JR |
2554 | static int cr0_write_interception(struct vcpu_svm *svm) |
2555 | { | |
2556 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
2557 | int r; | |
2558 | ||
2559 | r = emulate_instruction(&svm->vcpu, 0, 0, 0); | |
2560 | ||
2561 | if (svm->nested.vmexit_rip) { | |
2562 | kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip); | |
2563 | kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp); | |
2564 | kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax); | |
2565 | svm->nested.vmexit_rip = 0; | |
2566 | } | |
2567 | ||
2568 | return r == EMULATE_DONE; | |
2569 | } | |
2570 | ||
851ba692 | 2571 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2572 | { |
851ba692 AK |
2573 | struct kvm_run *kvm_run = svm->vcpu.run; |
2574 | ||
0a5fff19 GN |
2575 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2576 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2577 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 GN |
2578 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
2579 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1d075434 | 2580 | return 1; |
95ba8273 | 2581 | } |
0a5fff19 GN |
2582 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2583 | return 1; | |
1d075434 JR |
2584 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2585 | return 0; | |
2586 | } | |
2587 | ||
6aa8b732 AK |
2588 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2589 | { | |
a2fa3e9f GH |
2590 | struct vcpu_svm *svm = to_svm(vcpu); |
2591 | ||
6aa8b732 | 2592 | switch (ecx) { |
af24a4e4 | 2593 | case MSR_IA32_TSC: { |
20824f30 | 2594 | u64 tsc_offset; |
6aa8b732 | 2595 | |
20824f30 JR |
2596 | if (is_nested(svm)) |
2597 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2598 | else | |
2599 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2600 | ||
2601 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2602 | break; |
2603 | } | |
8c06585d | 2604 | case MSR_STAR: |
a2fa3e9f | 2605 | *data = svm->vmcb->save.star; |
6aa8b732 | 2606 | break; |
0e859cac | 2607 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2608 | case MSR_LSTAR: |
a2fa3e9f | 2609 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2610 | break; |
2611 | case MSR_CSTAR: | |
a2fa3e9f | 2612 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2613 | break; |
2614 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2615 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2616 | break; |
2617 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2618 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2619 | break; |
2620 | #endif | |
2621 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2622 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2623 | break; |
2624 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2625 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2626 | break; |
2627 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2628 | *data = svm->sysenter_esp; |
6aa8b732 | 2629 | break; |
e0231715 JR |
2630 | /* |
2631 | * Nobody will change the following 5 values in the VMCB so we can | |
2632 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2633 | * implemented. | |
2634 | */ | |
a2938c80 JR |
2635 | case MSR_IA32_DEBUGCTLMSR: |
2636 | *data = svm->vmcb->save.dbgctl; | |
2637 | break; | |
2638 | case MSR_IA32_LASTBRANCHFROMIP: | |
2639 | *data = svm->vmcb->save.br_from; | |
2640 | break; | |
2641 | case MSR_IA32_LASTBRANCHTOIP: | |
2642 | *data = svm->vmcb->save.br_to; | |
2643 | break; | |
2644 | case MSR_IA32_LASTINTFROMIP: | |
2645 | *data = svm->vmcb->save.last_excp_from; | |
2646 | break; | |
2647 | case MSR_IA32_LASTINTTOIP: | |
2648 | *data = svm->vmcb->save.last_excp_to; | |
2649 | break; | |
b286d5d8 | 2650 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2651 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2652 | break; |
eb6f302e | 2653 | case MSR_VM_CR: |
4a810181 | 2654 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2655 | break; |
c8a73f18 AG |
2656 | case MSR_IA32_UCODE_REV: |
2657 | *data = 0x01000065; | |
2658 | break; | |
6aa8b732 | 2659 | default: |
3bab1f5d | 2660 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2661 | } |
2662 | return 0; | |
2663 | } | |
2664 | ||
851ba692 | 2665 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2666 | { |
ad312c7c | 2667 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2668 | u64 data; |
2669 | ||
59200273 AK |
2670 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2671 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2672 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2673 | } else { |
229456fc | 2674 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2675 | |
5fdbf976 | 2676 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2677 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2678 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2679 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2680 | } |
2681 | return 1; | |
2682 | } | |
2683 | ||
4a810181 JR |
2684 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2685 | { | |
2686 | struct vcpu_svm *svm = to_svm(vcpu); | |
2687 | int svm_dis, chg_mask; | |
2688 | ||
2689 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2690 | return 1; | |
2691 | ||
2692 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2693 | ||
2694 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2695 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2696 | ||
2697 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2698 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2699 | ||
2700 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2701 | ||
2702 | /* check for svm_disable while efer.svme is set */ | |
2703 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2704 | return 1; | |
2705 | ||
2706 | return 0; | |
2707 | } | |
2708 | ||
6aa8b732 AK |
2709 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2710 | { | |
a2fa3e9f GH |
2711 | struct vcpu_svm *svm = to_svm(vcpu); |
2712 | ||
6aa8b732 | 2713 | switch (ecx) { |
f4e1b3c8 | 2714 | case MSR_IA32_TSC: |
99e3e30a | 2715 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2716 | break; |
8c06585d | 2717 | case MSR_STAR: |
a2fa3e9f | 2718 | svm->vmcb->save.star = data; |
6aa8b732 | 2719 | break; |
49b14f24 | 2720 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2721 | case MSR_LSTAR: |
a2fa3e9f | 2722 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2723 | break; |
2724 | case MSR_CSTAR: | |
a2fa3e9f | 2725 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2726 | break; |
2727 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2728 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2729 | break; |
2730 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2731 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2732 | break; |
2733 | #endif | |
2734 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2735 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2736 | break; |
2737 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2738 | svm->sysenter_eip = data; |
a2fa3e9f | 2739 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2740 | break; |
2741 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2742 | svm->sysenter_esp = data; |
a2fa3e9f | 2743 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2744 | break; |
a2938c80 | 2745 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
2746 | if (!svm_has(SVM_FEATURE_LBRV)) { |
2747 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 2748 | __func__, data); |
24e09cbf JR |
2749 | break; |
2750 | } | |
2751 | if (data & DEBUGCTL_RESERVED_BITS) | |
2752 | return 1; | |
2753 | ||
2754 | svm->vmcb->save.dbgctl = data; | |
2755 | if (data & (1ULL<<0)) | |
2756 | svm_enable_lbrv(svm); | |
2757 | else | |
2758 | svm_disable_lbrv(svm); | |
a2938c80 | 2759 | break; |
b286d5d8 | 2760 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2761 | svm->nested.hsave_msr = data; |
62b9abaa | 2762 | break; |
3c5d0a44 | 2763 | case MSR_VM_CR: |
4a810181 | 2764 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2765 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2766 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2767 | break; | |
6aa8b732 | 2768 | default: |
3bab1f5d | 2769 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2770 | } |
2771 | return 0; | |
2772 | } | |
2773 | ||
851ba692 | 2774 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2775 | { |
ad312c7c | 2776 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2777 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2778 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2779 | |
af9ca2d7 | 2780 | |
5fdbf976 | 2781 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2782 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2783 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2784 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2785 | } else { |
2786 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2787 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2788 | } |
6aa8b732 AK |
2789 | return 1; |
2790 | } | |
2791 | ||
851ba692 | 2792 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2793 | { |
e756fc62 | 2794 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2795 | return wrmsr_interception(svm); |
6aa8b732 | 2796 | else |
851ba692 | 2797 | return rdmsr_interception(svm); |
6aa8b732 AK |
2798 | } |
2799 | ||
851ba692 | 2800 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2801 | { |
851ba692 AK |
2802 | struct kvm_run *kvm_run = svm->vcpu.run; |
2803 | ||
3842d135 | 2804 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
f0b85051 | 2805 | svm_clear_vintr(svm); |
85f455f7 | 2806 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2807 | /* |
2808 | * If the user space waits to inject interrupts, exit as soon as | |
2809 | * possible | |
2810 | */ | |
8061823a GN |
2811 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2812 | kvm_run->request_interrupt_window && | |
2813 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2814 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2815 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2816 | return 0; | |
2817 | } | |
2818 | ||
2819 | return 1; | |
2820 | } | |
2821 | ||
565d0998 ML |
2822 | static int pause_interception(struct vcpu_svm *svm) |
2823 | { | |
2824 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2825 | return 1; | |
2826 | } | |
2827 | ||
851ba692 | 2828 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
e0231715 JR |
2829 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2830 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2831 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
2832 | [SVM_EXIT_READ_CR8] = emulate_on_interception, | |
d225157b | 2833 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
cda00082 | 2834 | [SVM_EXIT_WRITE_CR0] = cr0_write_interception, |
e0231715 JR |
2835 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, |
2836 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
2837 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, | |
2838 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
6aa8b732 AK |
2839 | [SVM_EXIT_READ_DR1] = emulate_on_interception, |
2840 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2841 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
727f5a23 JK |
2842 | [SVM_EXIT_READ_DR4] = emulate_on_interception, |
2843 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2844 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2845 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
6aa8b732 AK |
2846 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, |
2847 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2848 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2849 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
727f5a23 | 2850 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, |
6aa8b732 | 2851 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, |
727f5a23 | 2852 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, |
6aa8b732 | 2853 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, |
d0bfb940 JK |
2854 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2855 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2856 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
2857 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
2858 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
2859 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
2860 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 2861 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2862 | [SVM_EXIT_SMI] = nop_on_interception, |
2863 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2864 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 2865 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 2866 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2867 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 2868 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 2869 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2870 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2871 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 2872 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
2873 | [SVM_EXIT_MSR] = msr_interception, |
2874 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2875 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2876 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2877 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2878 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2879 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2880 | [SVM_EXIT_STGI] = stgi_interception, |
2881 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 2882 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 2883 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2884 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2885 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2886 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2887 | }; |
2888 | ||
3f10c846 JR |
2889 | void dump_vmcb(struct kvm_vcpu *vcpu) |
2890 | { | |
2891 | struct vcpu_svm *svm = to_svm(vcpu); | |
2892 | struct vmcb_control_area *control = &svm->vmcb->control; | |
2893 | struct vmcb_save_area *save = &svm->vmcb->save; | |
2894 | ||
2895 | pr_err("VMCB Control Area:\n"); | |
2896 | pr_err("cr_read: %04x\n", control->intercept_cr_read); | |
2897 | pr_err("cr_write: %04x\n", control->intercept_cr_write); | |
2898 | pr_err("dr_read: %04x\n", control->intercept_dr_read); | |
2899 | pr_err("dr_write: %04x\n", control->intercept_dr_write); | |
2900 | pr_err("exceptions: %08x\n", control->intercept_exceptions); | |
2901 | pr_err("intercepts: %016llx\n", control->intercept); | |
2902 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
2903 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
2904 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
2905 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
2906 | pr_err("asid: %d\n", control->asid); | |
2907 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
2908 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
2909 | pr_err("int_vector: %08x\n", control->int_vector); | |
2910 | pr_err("int_state: %08x\n", control->int_state); | |
2911 | pr_err("exit_code: %08x\n", control->exit_code); | |
2912 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
2913 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
2914 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
2915 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
2916 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
2917 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
2918 | pr_err("event_inj: %08x\n", control->event_inj); | |
2919 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
2920 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
2921 | pr_err("next_rip: %016llx\n", control->next_rip); | |
2922 | pr_err("VMCB State Save Area:\n"); | |
2923 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
2924 | save->es.selector, save->es.attrib, | |
2925 | save->es.limit, save->es.base); | |
2926 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2927 | save->cs.selector, save->cs.attrib, | |
2928 | save->cs.limit, save->cs.base); | |
2929 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
2930 | save->ss.selector, save->ss.attrib, | |
2931 | save->ss.limit, save->ss.base); | |
2932 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
2933 | save->ds.selector, save->ds.attrib, | |
2934 | save->ds.limit, save->ds.base); | |
2935 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2936 | save->fs.selector, save->fs.attrib, | |
2937 | save->fs.limit, save->fs.base); | |
2938 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2939 | save->gs.selector, save->gs.attrib, | |
2940 | save->gs.limit, save->gs.base); | |
2941 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2942 | save->gdtr.selector, save->gdtr.attrib, | |
2943 | save->gdtr.limit, save->gdtr.base); | |
2944 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2945 | save->ldtr.selector, save->ldtr.attrib, | |
2946 | save->ldtr.limit, save->ldtr.base); | |
2947 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2948 | save->idtr.selector, save->idtr.attrib, | |
2949 | save->idtr.limit, save->idtr.base); | |
2950 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2951 | save->tr.selector, save->tr.attrib, | |
2952 | save->tr.limit, save->tr.base); | |
2953 | pr_err("cpl: %d efer: %016llx\n", | |
2954 | save->cpl, save->efer); | |
2955 | pr_err("cr0: %016llx cr2: %016llx\n", | |
2956 | save->cr0, save->cr2); | |
2957 | pr_err("cr3: %016llx cr4: %016llx\n", | |
2958 | save->cr3, save->cr4); | |
2959 | pr_err("dr6: %016llx dr7: %016llx\n", | |
2960 | save->dr6, save->dr7); | |
2961 | pr_err("rip: %016llx rflags: %016llx\n", | |
2962 | save->rip, save->rflags); | |
2963 | pr_err("rsp: %016llx rax: %016llx\n", | |
2964 | save->rsp, save->rax); | |
2965 | pr_err("star: %016llx lstar: %016llx\n", | |
2966 | save->star, save->lstar); | |
2967 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
2968 | save->cstar, save->sfmask); | |
2969 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
2970 | save->kernel_gs_base, save->sysenter_cs); | |
2971 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
2972 | save->sysenter_esp, save->sysenter_eip); | |
2973 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
2974 | save->g_pat, save->dbgctl); | |
2975 | pr_err("br_from: %016llx br_to: %016llx\n", | |
2976 | save->br_from, save->br_to); | |
2977 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
2978 | save->last_excp_from, save->last_excp_to); | |
2979 | ||
2980 | } | |
2981 | ||
851ba692 | 2982 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 2983 | { |
04d2cc77 | 2984 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 2985 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 2986 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2987 | |
5bfd8b54 | 2988 | trace_kvm_exit(exit_code, vcpu); |
af9ca2d7 | 2989 | |
2be4fc7a JR |
2990 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) |
2991 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
2992 | if (npt_enabled) | |
2993 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 2994 | |
cd3ff653 JR |
2995 | if (unlikely(svm->nested.exit_required)) { |
2996 | nested_svm_vmexit(svm); | |
2997 | svm->nested.exit_required = false; | |
2998 | ||
2999 | return 1; | |
3000 | } | |
3001 | ||
cf74a78b | 3002 | if (is_nested(svm)) { |
410e4d57 JR |
3003 | int vmexit; |
3004 | ||
d8cabddf JR |
3005 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
3006 | svm->vmcb->control.exit_info_1, | |
3007 | svm->vmcb->control.exit_info_2, | |
3008 | svm->vmcb->control.exit_int_info, | |
3009 | svm->vmcb->control.exit_int_info_err); | |
3010 | ||
410e4d57 JR |
3011 | vmexit = nested_svm_exit_special(svm); |
3012 | ||
3013 | if (vmexit == NESTED_EXIT_CONTINUE) | |
3014 | vmexit = nested_svm_exit_handled(svm); | |
3015 | ||
3016 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 3017 | return 1; |
cf74a78b AG |
3018 | } |
3019 | ||
a5c3832d JR |
3020 | svm_complete_interrupts(svm); |
3021 | ||
04d2cc77 AK |
3022 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
3023 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3024 | kvm_run->fail_entry.hardware_entry_failure_reason | |
3025 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
3026 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
3027 | dump_vmcb(vcpu); | |
04d2cc77 AK |
3028 | return 0; |
3029 | } | |
3030 | ||
a2fa3e9f | 3031 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 3032 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
55c5e464 JR |
3033 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH && |
3034 | exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI) | |
6aa8b732 AK |
3035 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
3036 | "exit_code 0x%x\n", | |
b8688d51 | 3037 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
3038 | exit_code); |
3039 | ||
9d8f549d | 3040 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 3041 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 3042 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 3043 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
3044 | return 0; |
3045 | } | |
3046 | ||
851ba692 | 3047 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
3048 | } |
3049 | ||
3050 | static void reload_tss(struct kvm_vcpu *vcpu) | |
3051 | { | |
3052 | int cpu = raw_smp_processor_id(); | |
3053 | ||
0fe1e009 TH |
3054 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
3055 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
3056 | load_TR_desc(); |
3057 | } | |
3058 | ||
e756fc62 | 3059 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
3060 | { |
3061 | int cpu = raw_smp_processor_id(); | |
3062 | ||
0fe1e009 | 3063 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 3064 | |
a2fa3e9f | 3065 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 | 3066 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
3067 | if (svm->asid_generation != sd->asid_generation) |
3068 | new_asid(svm, sd); | |
6aa8b732 AK |
3069 | } |
3070 | ||
95ba8273 GN |
3071 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
3072 | { | |
3073 | struct vcpu_svm *svm = to_svm(vcpu); | |
3074 | ||
3075 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
3076 | vcpu->arch.hflags |= HF_NMI_MASK; | |
061e2fd1 | 3077 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); |
95ba8273 GN |
3078 | ++vcpu->stat.nmi_injections; |
3079 | } | |
6aa8b732 | 3080 | |
85f455f7 | 3081 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
3082 | { |
3083 | struct vmcb_control_area *control; | |
3084 | ||
e756fc62 | 3085 | control = &svm->vmcb->control; |
85f455f7 | 3086 | control->int_vector = irq; |
6aa8b732 AK |
3087 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
3088 | control->int_ctl |= V_IRQ_MASK | | |
3089 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
3090 | } | |
3091 | ||
66fd3f7f | 3092 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
3093 | { |
3094 | struct vcpu_svm *svm = to_svm(vcpu); | |
3095 | ||
2af9194d | 3096 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 3097 | |
9fb2d2b4 GN |
3098 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
3099 | ++vcpu->stat.irq_injections; | |
3100 | ||
219b65dc AG |
3101 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
3102 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
3103 | } |
3104 | ||
95ba8273 | 3105 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
3106 | { |
3107 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 3108 | |
88ab24ad JR |
3109 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
3110 | return; | |
3111 | ||
95ba8273 | 3112 | if (irr == -1) |
aaacfc9a JR |
3113 | return; |
3114 | ||
95ba8273 GN |
3115 | if (tpr >= irr) |
3116 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
3117 | } | |
aaacfc9a | 3118 | |
95ba8273 GN |
3119 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
3120 | { | |
3121 | struct vcpu_svm *svm = to_svm(vcpu); | |
3122 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
3123 | int ret; |
3124 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
3125 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3126 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
3127 | ||
3128 | return ret; | |
aaacfc9a JR |
3129 | } |
3130 | ||
3cfc3092 JK |
3131 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
3132 | { | |
3133 | struct vcpu_svm *svm = to_svm(vcpu); | |
3134 | ||
3135 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
3136 | } | |
3137 | ||
3138 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
3139 | { | |
3140 | struct vcpu_svm *svm = to_svm(vcpu); | |
3141 | ||
3142 | if (masked) { | |
3143 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
061e2fd1 | 3144 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); |
3cfc3092 JK |
3145 | } else { |
3146 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
061e2fd1 | 3147 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); |
3cfc3092 JK |
3148 | } |
3149 | } | |
3150 | ||
78646121 GN |
3151 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
3152 | { | |
3153 | struct vcpu_svm *svm = to_svm(vcpu); | |
3154 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
3155 | int ret; |
3156 | ||
3157 | if (!gif_set(svm) || | |
3158 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
3159 | return 0; | |
3160 | ||
3161 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3162 | ||
3163 | if (is_nested(svm)) | |
3164 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
3165 | ||
3166 | return ret; | |
78646121 GN |
3167 | } |
3168 | ||
9222be18 | 3169 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3170 | { |
219b65dc | 3171 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3172 | |
e0231715 JR |
3173 | /* |
3174 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3175 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3176 | * get that intercept, this function will be called again though and | |
3177 | * we'll get the vintr intercept. | |
3178 | */ | |
8fe54654 | 3179 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3180 | svm_set_vintr(svm); |
3181 | svm_inject_irq(svm, 0x0); | |
3182 | } | |
85f455f7 ED |
3183 | } |
3184 | ||
95ba8273 | 3185 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3186 | { |
04d2cc77 | 3187 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3188 | |
44c11430 GN |
3189 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3190 | == HF_NMI_MASK) | |
3191 | return; /* IRET will cause a vm exit */ | |
3192 | ||
e0231715 JR |
3193 | /* |
3194 | * Something prevents NMI from been injected. Single step over possible | |
3195 | * problem (IRET or exception injection or interrupt shadow) | |
3196 | */ | |
6be7d306 | 3197 | svm->nmi_singlestep = true; |
44c11430 GN |
3198 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3199 | update_db_intercept(vcpu); | |
c1150d8c DL |
3200 | } |
3201 | ||
cbc94022 IE |
3202 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3203 | { | |
3204 | return 0; | |
3205 | } | |
3206 | ||
d9e368d6 AK |
3207 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3208 | { | |
3209 | force_new_asid(vcpu); | |
3210 | } | |
3211 | ||
04d2cc77 AK |
3212 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3213 | { | |
3214 | } | |
3215 | ||
d7bf8221 JR |
3216 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3217 | { | |
3218 | struct vcpu_svm *svm = to_svm(vcpu); | |
3219 | ||
88ab24ad JR |
3220 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
3221 | return; | |
3222 | ||
d7bf8221 JR |
3223 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { |
3224 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
615d5193 | 3225 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3226 | } |
3227 | } | |
3228 | ||
649d6864 JR |
3229 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3230 | { | |
3231 | struct vcpu_svm *svm = to_svm(vcpu); | |
3232 | u64 cr8; | |
3233 | ||
88ab24ad JR |
3234 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
3235 | return; | |
3236 | ||
649d6864 JR |
3237 | cr8 = kvm_get_cr8(vcpu); |
3238 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3239 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3240 | } | |
3241 | ||
9222be18 GN |
3242 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3243 | { | |
3244 | u8 vector; | |
3245 | int type; | |
3246 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3247 | unsigned int3_injected = svm->int3_injected; |
3248 | ||
3249 | svm->int3_injected = 0; | |
9222be18 | 3250 | |
3842d135 | 3251 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) { |
44c11430 | 3252 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); |
3842d135 AK |
3253 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3254 | } | |
44c11430 | 3255 | |
9222be18 GN |
3256 | svm->vcpu.arch.nmi_injected = false; |
3257 | kvm_clear_exception_queue(&svm->vcpu); | |
3258 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3259 | ||
3260 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3261 | return; | |
3262 | ||
3842d135 AK |
3263 | kvm_make_request(KVM_REQ_EVENT, &svm->vcpu); |
3264 | ||
9222be18 GN |
3265 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; |
3266 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3267 | ||
3268 | switch (type) { | |
3269 | case SVM_EXITINTINFO_TYPE_NMI: | |
3270 | svm->vcpu.arch.nmi_injected = true; | |
3271 | break; | |
3272 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3273 | /* |
3274 | * In case of software exceptions, do not reinject the vector, | |
3275 | * but re-execute the instruction instead. Rewind RIP first | |
3276 | * if we emulated INT3 before. | |
3277 | */ | |
3278 | if (kvm_exception_is_soft(vector)) { | |
3279 | if (vector == BP_VECTOR && int3_injected && | |
3280 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3281 | kvm_rip_write(&svm->vcpu, | |
3282 | kvm_rip_read(&svm->vcpu) - | |
3283 | int3_injected); | |
9222be18 | 3284 | break; |
66b7138f | 3285 | } |
9222be18 GN |
3286 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3287 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3288 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3289 | |
3290 | } else | |
ce7ddec4 | 3291 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3292 | break; |
3293 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3294 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3295 | break; |
3296 | default: | |
3297 | break; | |
3298 | } | |
3299 | } | |
3300 | ||
b463a6f7 AK |
3301 | static void svm_cancel_injection(struct kvm_vcpu *vcpu) |
3302 | { | |
3303 | struct vcpu_svm *svm = to_svm(vcpu); | |
3304 | struct vmcb_control_area *control = &svm->vmcb->control; | |
3305 | ||
3306 | control->exit_int_info = control->event_inj; | |
3307 | control->exit_int_info_err = control->event_inj_err; | |
3308 | control->event_inj = 0; | |
3309 | svm_complete_interrupts(svm); | |
3310 | } | |
3311 | ||
80e31d4f AK |
3312 | #ifdef CONFIG_X86_64 |
3313 | #define R "r" | |
3314 | #else | |
3315 | #define R "e" | |
3316 | #endif | |
3317 | ||
851ba692 | 3318 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3319 | { |
a2fa3e9f | 3320 | struct vcpu_svm *svm = to_svm(vcpu); |
d9e368d6 | 3321 | |
2041a06a JR |
3322 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3323 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3324 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3325 | ||
cd3ff653 JR |
3326 | /* |
3327 | * A vmexit emulation is required before the vcpu can be executed | |
3328 | * again. | |
3329 | */ | |
3330 | if (unlikely(svm->nested.exit_required)) | |
3331 | return; | |
3332 | ||
e756fc62 | 3333 | pre_svm_run(svm); |
6aa8b732 | 3334 | |
649d6864 JR |
3335 | sync_lapic_to_cr8(vcpu); |
3336 | ||
cda0ffdd | 3337 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 3338 | |
04d2cc77 AK |
3339 | clgi(); |
3340 | ||
3341 | local_irq_enable(); | |
36241b8c | 3342 | |
6aa8b732 | 3343 | asm volatile ( |
80e31d4f AK |
3344 | "push %%"R"bp; \n\t" |
3345 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3346 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3347 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3348 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3349 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3350 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3351 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3352 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3353 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3354 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3355 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3356 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3357 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3358 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3359 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3360 | #endif |
3361 | ||
6aa8b732 | 3362 | /* Enter guest mode */ |
80e31d4f AK |
3363 | "push %%"R"ax \n\t" |
3364 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3365 | __ex(SVM_VMLOAD) "\n\t" |
3366 | __ex(SVM_VMRUN) "\n\t" | |
3367 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3368 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3369 | |
3370 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3371 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3372 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3373 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3374 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3375 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3376 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3377 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3378 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3379 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3380 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3381 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3382 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3383 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3384 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3385 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3386 | #endif |
80e31d4f | 3387 | "pop %%"R"bp" |
6aa8b732 | 3388 | : |
fb3f0f51 | 3389 | : [svm]"a"(svm), |
6aa8b732 | 3390 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3391 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3392 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3393 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3394 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3395 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3396 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3397 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3398 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3399 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3400 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3401 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3402 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3403 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3404 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3405 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3406 | #endif |
54a08c04 | 3407 | : "cc", "memory" |
80e31d4f | 3408 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3409 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3410 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3411 | #endif | |
3412 | ); | |
6aa8b732 | 3413 | |
82ca2d10 AK |
3414 | #ifdef CONFIG_X86_64 |
3415 | wrmsrl(MSR_GS_BASE, svm->host.gs_base); | |
3416 | #else | |
dacccfdd | 3417 | loadsegment(fs, svm->host.fs); |
9581d442 | 3418 | #endif |
6aa8b732 AK |
3419 | |
3420 | reload_tss(vcpu); | |
3421 | ||
56ba47dd AK |
3422 | local_irq_disable(); |
3423 | ||
3424 | stgi(); | |
3425 | ||
13c34e07 AK |
3426 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
3427 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
3428 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3429 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
3430 | ||
d7bf8221 JR |
3431 | sync_cr8_to_lapic(vcpu); |
3432 | ||
a2fa3e9f | 3433 | svm->next_rip = 0; |
9222be18 | 3434 | |
631bc487 GN |
3435 | /* if exit due to PF check for async PF */ |
3436 | if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) | |
3437 | svm->apf_reason = kvm_read_and_reset_pf_reason(); | |
3438 | ||
6de4f3ad AK |
3439 | if (npt_enabled) { |
3440 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3441 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3442 | } | |
fe5913e4 JR |
3443 | |
3444 | /* | |
3445 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3446 | * change the physical cpu | |
3447 | */ | |
3448 | if (unlikely(svm->vmcb->control.exit_code == | |
3449 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3450 | svm_handle_mce(svm); | |
6aa8b732 AK |
3451 | } |
3452 | ||
80e31d4f AK |
3453 | #undef R |
3454 | ||
6aa8b732 AK |
3455 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3456 | { | |
a2fa3e9f GH |
3457 | struct vcpu_svm *svm = to_svm(vcpu); |
3458 | ||
3459 | svm->vmcb->save.cr3 = root; | |
6aa8b732 AK |
3460 | force_new_asid(vcpu); |
3461 | } | |
3462 | ||
1c97f0a0 JR |
3463 | static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3464 | { | |
3465 | struct vcpu_svm *svm = to_svm(vcpu); | |
3466 | ||
3467 | svm->vmcb->control.nested_cr3 = root; | |
3468 | ||
3469 | /* Also sync guest cr3 here in case we live migrate */ | |
3470 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
3471 | ||
3472 | force_new_asid(vcpu); | |
3473 | } | |
3474 | ||
6aa8b732 AK |
3475 | static int is_disabled(void) |
3476 | { | |
6031a61c JR |
3477 | u64 vm_cr; |
3478 | ||
3479 | rdmsrl(MSR_VM_CR, vm_cr); | |
3480 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3481 | return 1; | |
3482 | ||
6aa8b732 AK |
3483 | return 0; |
3484 | } | |
3485 | ||
102d8325 IM |
3486 | static void |
3487 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3488 | { | |
3489 | /* | |
3490 | * Patch in the VMMCALL instruction: | |
3491 | */ | |
3492 | hypercall[0] = 0x0f; | |
3493 | hypercall[1] = 0x01; | |
3494 | hypercall[2] = 0xd9; | |
102d8325 IM |
3495 | } |
3496 | ||
002c7f7c YS |
3497 | static void svm_check_processor_compat(void *rtn) |
3498 | { | |
3499 | *(int *)rtn = 0; | |
3500 | } | |
3501 | ||
774ead3a AK |
3502 | static bool svm_cpu_has_accelerated_tpr(void) |
3503 | { | |
3504 | return false; | |
3505 | } | |
3506 | ||
4b12f0de | 3507 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3508 | { |
3509 | return 0; | |
3510 | } | |
3511 | ||
0e851880 SY |
3512 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3513 | { | |
3514 | } | |
3515 | ||
d4330ef2 JR |
3516 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3517 | { | |
c2c63a49 | 3518 | switch (func) { |
24d1b15f JR |
3519 | case 0x00000001: |
3520 | /* Mask out xsave bit as long as it is not supported by SVM */ | |
3521 | entry->ecx &= ~(bit(X86_FEATURE_XSAVE)); | |
3522 | break; | |
4c62a2dc JR |
3523 | case 0x80000001: |
3524 | if (nested) | |
3525 | entry->ecx |= (1 << 2); /* Set SVM bit */ | |
3526 | break; | |
c2c63a49 JR |
3527 | case 0x8000000A: |
3528 | entry->eax = 1; /* SVM revision 1 */ | |
3529 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3530 | ASID emulation to nested SVM */ | |
3531 | entry->ecx = 0; /* Reserved */ | |
7a190667 JR |
3532 | entry->edx = 0; /* Per default do not support any |
3533 | additional features */ | |
3534 | ||
3535 | /* Support next_rip if host supports it */ | |
3536 | if (svm_has(SVM_FEATURE_NRIP)) | |
3537 | entry->edx |= SVM_FEATURE_NRIP; | |
c2c63a49 | 3538 | |
3d4aeaad JR |
3539 | /* Support NPT for the guest if enabled */ |
3540 | if (npt_enabled) | |
3541 | entry->edx |= SVM_FEATURE_NPT; | |
3542 | ||
c2c63a49 JR |
3543 | break; |
3544 | } | |
d4330ef2 JR |
3545 | } |
3546 | ||
229456fc | 3547 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3548 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3549 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3550 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3551 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3552 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3553 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3554 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3555 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3556 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3557 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3558 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3559 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3560 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3561 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3562 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3563 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3564 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3565 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3566 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3567 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3568 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3569 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3570 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3571 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3572 | { SVM_EXIT_INTR, "interrupt" }, | |
3573 | { SVM_EXIT_NMI, "nmi" }, | |
3574 | { SVM_EXIT_SMI, "smi" }, | |
3575 | { SVM_EXIT_INIT, "init" }, | |
3576 | { SVM_EXIT_VINTR, "vintr" }, | |
3577 | { SVM_EXIT_CPUID, "cpuid" }, | |
3578 | { SVM_EXIT_INVD, "invd" }, | |
3579 | { SVM_EXIT_HLT, "hlt" }, | |
3580 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3581 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3582 | { SVM_EXIT_IOIO, "io" }, | |
3583 | { SVM_EXIT_MSR, "msr" }, | |
3584 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3585 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3586 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3587 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3588 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3589 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3590 | { SVM_EXIT_STGI, "stgi" }, | |
3591 | { SVM_EXIT_CLGI, "clgi" }, | |
3592 | { SVM_EXIT_SKINIT, "skinit" }, | |
3593 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3594 | { SVM_EXIT_MONITOR, "monitor" }, | |
3595 | { SVM_EXIT_MWAIT, "mwait" }, | |
3596 | { SVM_EXIT_NPF, "npf" }, | |
3597 | { -1, NULL } | |
3598 | }; | |
3599 | ||
17cc3935 | 3600 | static int svm_get_lpage_level(void) |
344f414f | 3601 | { |
17cc3935 | 3602 | return PT_PDPE_LEVEL; |
344f414f JR |
3603 | } |
3604 | ||
4e47c7a6 SY |
3605 | static bool svm_rdtscp_supported(void) |
3606 | { | |
3607 | return false; | |
3608 | } | |
3609 | ||
f5f48ee1 SY |
3610 | static bool svm_has_wbinvd_exit(void) |
3611 | { | |
3612 | return true; | |
3613 | } | |
3614 | ||
02daab21 AK |
3615 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3616 | { | |
3617 | struct vcpu_svm *svm = to_svm(vcpu); | |
3618 | ||
02daab21 | 3619 | svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; |
66a562f7 JR |
3620 | if (is_nested(svm)) |
3621 | svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR; | |
3622 | update_cr0_intercept(svm); | |
02daab21 AK |
3623 | } |
3624 | ||
cbdd1bea | 3625 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
3626 | .cpu_has_kvm_support = has_svm, |
3627 | .disabled_by_bios = is_disabled, | |
3628 | .hardware_setup = svm_hardware_setup, | |
3629 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 3630 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
3631 | .hardware_enable = svm_hardware_enable, |
3632 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 3633 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
3634 | |
3635 | .vcpu_create = svm_create_vcpu, | |
3636 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 3637 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 3638 | |
04d2cc77 | 3639 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
3640 | .vcpu_load = svm_vcpu_load, |
3641 | .vcpu_put = svm_vcpu_put, | |
3642 | ||
3643 | .set_guest_debug = svm_guest_debug, | |
3644 | .get_msr = svm_get_msr, | |
3645 | .set_msr = svm_set_msr, | |
3646 | .get_segment_base = svm_get_segment_base, | |
3647 | .get_segment = svm_get_segment, | |
3648 | .set_segment = svm_set_segment, | |
2e4d2653 | 3649 | .get_cpl = svm_get_cpl, |
1747fb71 | 3650 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 3651 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 3652 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 3653 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
3654 | .set_cr3 = svm_set_cr3, |
3655 | .set_cr4 = svm_set_cr4, | |
3656 | .set_efer = svm_set_efer, | |
3657 | .get_idt = svm_get_idt, | |
3658 | .set_idt = svm_set_idt, | |
3659 | .get_gdt = svm_get_gdt, | |
3660 | .set_gdt = svm_set_gdt, | |
020df079 | 3661 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 3662 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3663 | .get_rflags = svm_get_rflags, |
3664 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3665 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3666 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3667 | |
6aa8b732 | 3668 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3669 | |
6aa8b732 | 3670 | .run = svm_vcpu_run, |
04d2cc77 | 3671 | .handle_exit = handle_exit, |
6aa8b732 | 3672 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3673 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3674 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3675 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3676 | .set_irq = svm_set_irq, |
95ba8273 | 3677 | .set_nmi = svm_inject_nmi, |
298101da | 3678 | .queue_exception = svm_queue_exception, |
b463a6f7 | 3679 | .cancel_injection = svm_cancel_injection, |
78646121 | 3680 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3681 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3682 | .get_nmi_mask = svm_get_nmi_mask, |
3683 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3684 | .enable_nmi_window = enable_nmi_window, |
3685 | .enable_irq_window = enable_irq_window, | |
3686 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3687 | |
3688 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3689 | .get_tdp_level = get_npt_level, |
4b12f0de | 3690 | .get_mt_mask = svm_get_mt_mask, |
229456fc MT |
3691 | |
3692 | .exit_reasons_str = svm_exit_reasons_str, | |
17cc3935 | 3693 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3694 | |
3695 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3696 | |
3697 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
3698 | |
3699 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
3700 | |
3701 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
99e3e30a ZA |
3702 | |
3703 | .write_tsc_offset = svm_write_tsc_offset, | |
e48672fa | 3704 | .adjust_tsc_offset = svm_adjust_tsc_offset, |
1c97f0a0 JR |
3705 | |
3706 | .set_tdp_cr3 = set_tdp_cr3, | |
6aa8b732 AK |
3707 | }; |
3708 | ||
3709 | static int __init svm_init(void) | |
3710 | { | |
cb498ea2 | 3711 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 3712 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
3713 | } |
3714 | ||
3715 | static void __exit svm_exit(void) | |
3716 | { | |
cb498ea2 | 3717 | kvm_exit(); |
6aa8b732 AK |
3718 | } |
3719 | ||
3720 | module_init(svm_init) | |
3721 | module_exit(svm_exit) |