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KVM: SVM: Clean up and enhance mov dr emulation
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
565d0998 49#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 50
410e4d57
JR		 51#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
24e09cbf
JR		 55#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
6c8166a7
AK		 57static const u32 host_save_user_msrs[] = {
58#ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61#endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63};
64
65#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67struct kvm_vcpu;
68
e6aa9abd
JR		 69struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
aad42c64 79
cd3ff653
JR		 80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
aad42c64
JR		 83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
e6aa9abd
JR		 91};
92
6c8166a7
AK		 93struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
6c8166a7
AK		 106
107 u32 *msrpm;
6c8166a7 108
e6aa9abd 109 struct nested_state nested;
6be7d306
JK		 110
111 bool nmi_singlestep;
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116static bool npt_enabled = true;
117#else
e3da3acd 118static bool npt_enabled = false;
709ddebf 119#endif
6c7dac72
JR		 120static int npt = 1;
121
122module_param(npt, int, S_IRUGO);
e3da3acd 123
4b6e4dca 124static int nested = 1;
236de055
AG		 125module_param(nested, int, S_IRUGO);
126
44874f84 127static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 128static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 129
410e4d57 130static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 131static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 132static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
a2fa3e9f
GH		 135static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136{
fb3f0f51 137 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 138}
139
3d6368ef
AG		 140static inline bool is_nested(struct vcpu_svm *svm)
141{
e6aa9abd 142 return svm->nested.vmcb;
3d6368ef
AG		 143}
144
2af9194d
JR		 145static inline void enable_gif(struct vcpu_svm *svm)
146{
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148}
149
150static inline void disable_gif(struct vcpu_svm *svm)
151{
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153}
154
155static inline bool gif_set(struct vcpu_svm *svm)
156{
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158}
159
4866d5e3 160static unsigned long iopm_base;
6aa8b732
AK		 161
162struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169} __attribute__((packed));
170
171struct svm_cpu_data {
172 int cpu;
173
5008fdf5
AK		 174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
6aa8b732
AK		 177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180};
181
182static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 183static uint32_t svm_features;
6aa8b732
AK		 184
185struct svm_init_data {
186 int cpu;
187 int r;
188};
189
190static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
9d8f549d 192#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 193#define MSRS_RANGE_SIZE 2048
194#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196#define MAX_INST_SIZE 15
197
80b7706e
JR		 198static inline u32 svm_has(u32 feat)
199{
200 return svm_features & feat;
201}
202
6aa8b732
AK		 203static inline void clgi(void)
204{
4ecac3fd 205 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 206}
207
208static inline void stgi(void)
209{
4ecac3fd 210 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 211}
212
213static inline void invlpga(unsigned long addr, u32 asid)
214{
4ecac3fd 215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 216}
217
6aa8b732
AK		 218static inline void force_new_asid(struct kvm_vcpu *vcpu)
219{
a2fa3e9f 220 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 221}
222
223static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224{
225 force_new_asid(vcpu);
226}
227
228static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229{
709ddebf 230 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 231 efer &= ~EFER_LME;
6aa8b732 232
9962d032 233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 234 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 235}
236
298101da
AK		 237static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239{
240 struct vcpu_svm *svm = to_svm(vcpu);
241
cf74a78b
AG		 242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
298101da
AK		 247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252}
253
6aa8b732
AK		 254static int is_external_interrupt(u32 info)
255{
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258}
259
2809f5d2
GC		 260static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261{
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268}
269
270static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271{
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279}
280
6aa8b732
AK		 281static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282{
a2fa3e9f
GH		 283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
851ba692 286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 289 return;
290 }
5fdbf976
MT		 291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 294
5fdbf976 295 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 296 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 297}
298
299static int has_svm(void)
300{
63d1142f 301 const char *msg;
6aa8b732 302
63d1142f 303 if (!cpu_has_svm(&msg)) {
ff81ff10 304 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 305 return 0;
306 }
307
6aa8b732
AK		 308 return 1;
309}
310
311static void svm_hardware_disable(void *garbage)
312{
2c8dceeb 313 cpu_svm_disable();
6aa8b732
AK		 314}
315
10474ae8 316static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 317{
318
0fe1e009 319 struct svm_cpu_data *sd;
6aa8b732 320 uint64_t efer;
b792c344 321 struct descriptor_table gdt_descr;
6aa8b732
AK		 322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
10474ae8
AG		 325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
6aa8b732 329 if (!has_svm()) {
e6732a5a
ZA		 330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
10474ae8 332 return -EINVAL;
6aa8b732 333 }
0fe1e009 334 sd = per_cpu(svm_data, me);
6aa8b732 335
0fe1e009 336 if (!sd) {
e6732a5a 337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 338 me);
10474ae8 339 return -EINVAL;
6aa8b732
AK		 340 }
341
0fe1e009
TH		 342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
6aa8b732 345
b792c344
AM		 346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
0fe1e009 348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 349
9962d032 350 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 351
d0316554 352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 353
354 return 0;
6aa8b732
AK		 355}
356
0da1db75
JR		 357static void svm_cpu_uninit(int cpu)
358{
0fe1e009 359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 360
0fe1e009 361 if (!sd)
0da1db75
JR		 362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 365 __free_page(sd->save_area);
366 kfree(sd);
0da1db75
JR		 367}
368
6aa8b732
AK		 369static int svm_cpu_init(int cpu)
370{
0fe1e009 371 struct svm_cpu_data *sd;
6aa8b732
AK		 372 int r;
373
0fe1e009
TH		 374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
6aa8b732 376 return -ENOMEM;
0fe1e009
TH		 377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 379 r = -ENOMEM;
0fe1e009 380 if (!sd->save_area)
6aa8b732
AK		 381 goto err_1;
382
0fe1e009 383 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 384
385 return 0;
386
387err_1:
0fe1e009 388 kfree(sd);
6aa8b732
AK		 389 return r;
390
391}
392
bfc733a7
RR		 393static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
6aa8b732
AK		 395{
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
bfc733a7 409 return;
6aa8b732
AK		 410 }
411 }
bfc733a7 412 BUG();
6aa8b732
AK		 413}
414
f65c229c
JR		 415static void svm_vcpu_init_msrpm(u32 *msrpm)
416{
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419#ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426#endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 429}
430
24e09cbf
JR		 431static void svm_enable_lbrv(struct vcpu_svm *svm)
432{
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440}
441
442static void svm_disable_lbrv(struct vcpu_svm *svm)
443{
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451}
452
6aa8b732
AK		 453static __init int svm_hardware_setup(void)
454{
455 int cpu;
456 struct page *iopm_pages;
f65c229c 457 void *iopm_va;
6aa8b732
AK		 458 int r;
459
6aa8b732
AK		 460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
c8681339
AL		 464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
50a37eb4
JR		 469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
1b2fd70c
AG		 472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
236de055
AG		 475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
3230bb47 480 for_each_possible_cpu(cpu) {
6aa8b732
AK		 481 r = svm_cpu_init(cpu);
482 if (r)
f65c229c 483 goto err;
6aa8b732 484 }
33bd6a0b
JR		 485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
e3da3acd
JR		 488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
6c7dac72
JR		 491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
18552672 496 if (npt_enabled) {
e3da3acd 497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 498 kvm_enable_tdp();
5f4cb662
JR		 499 } else
500 kvm_disable_tdp();
e3da3acd 501
6aa8b732
AK		 502 return 0;
503
f65c229c 504err:
6aa8b732
AK		 505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508}
509
510static __exit void svm_hardware_unsetup(void)
511{
0da1db75
JR		 512 int cpu;
513
3230bb47 514 for_each_possible_cpu(cpu)
0da1db75
JR		 515 svm_cpu_uninit(cpu);
516
6aa8b732 517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 518 iopm_base = 0;
6aa8b732
AK		 519}
520
521static void init_seg(struct vmcb_seg *seg)
522{
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528}
529
530static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531{
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536}
537
e6101a96 538static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 539{
e6101a96
JR		 540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 542
bff78274
AK		 543 svm->vcpu.fpu_active = 1;
544
6aa8b732
AK		 545 control->intercept_cr_read = INTERCEPT_CR0_MASK |
546 INTERCEPT_CR3_MASK |
649d6864 547 INTERCEPT_CR4_MASK;
6aa8b732
AK		 548
549 control->intercept_cr_write = INTERCEPT_CR0_MASK |
550 INTERCEPT_CR3_MASK |
80a8119c
AK		 551 INTERCEPT_CR4_MASK |
552 INTERCEPT_CR8_MASK;
6aa8b732
AK		 553
554 control->intercept_dr_read = INTERCEPT_DR0_MASK |
555 INTERCEPT_DR1_MASK |
556 INTERCEPT_DR2_MASK |
557 INTERCEPT_DR3_MASK;
558
559 control->intercept_dr_write = INTERCEPT_DR0_MASK |
560 INTERCEPT_DR1_MASK |
561 INTERCEPT_DR2_MASK |
562 INTERCEPT_DR3_MASK |
563 INTERCEPT_DR5_MASK |
564 INTERCEPT_DR7_MASK;
565
7aa81cc0 566 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 567 (1 << UD_VECTOR) |
568 (1 << MC_VECTOR);
6aa8b732
AK		 569
570
571 control->intercept = (1ULL << INTERCEPT_INTR) |
572 (1ULL << INTERCEPT_NMI) |
0152527b 573 (1ULL << INTERCEPT_SMI) |
d225157b 574 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 575 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 576 (1ULL << INTERCEPT_INVD) |
6aa8b732 577 (1ULL << INTERCEPT_HLT) |
a7052897 578 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 579 (1ULL << INTERCEPT_INVLPGA) |
580 (1ULL << INTERCEPT_IOIO_PROT) |
581 (1ULL << INTERCEPT_MSR_PROT) |
582 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 583 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 584 (1ULL << INTERCEPT_VMRUN) |
585 (1ULL << INTERCEPT_VMMCALL) |
586 (1ULL << INTERCEPT_VMLOAD) |
587 (1ULL << INTERCEPT_VMSAVE) |
588 (1ULL << INTERCEPT_STGI) |
589 (1ULL << INTERCEPT_CLGI) |
916ce236 590 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 591 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 592 (1ULL << INTERCEPT_MONITOR) |
593 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 594
595 control->iopm_base_pa = iopm_base;
f65c229c 596 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 597 control->tsc_offset = 0;
6aa8b732
AK		 598 control->int_ctl = V_INTR_MASKING_MASK;
599
600 init_seg(&save->es);
601 init_seg(&save->ss);
602 init_seg(&save->ds);
603 init_seg(&save->fs);
604 init_seg(&save->gs);
605
606 save->cs.selector = 0xf000;
607 /* Executable/Readable Code Segment */
608 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
609 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
610 save->cs.limit = 0xffff;
d92899a0
AK		 611 /*
612 * cs.base should really be 0xffff0000, but vmx can't handle that, so
613 * be consistent with it.
614 *
615 * Replace when we have real mode working for vmx.
616 */
617 save->cs.base = 0xf0000;
6aa8b732
AK		 618
619 save->gdtr.limit = 0xffff;
620 save->idtr.limit = 0xffff;
621
622 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
623 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
624
9962d032 625 save->efer = EFER_SVME;
d77c26fc 626 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 627 save->dr7 = 0x400;
628 save->rflags = 2;
629 save->rip = 0x0000fff0;
5fdbf976 630 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 631
18fa000a
EH		 632 /* This is the guest-visible cr0 value.
633 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 634 */
18fa000a
EH		 635 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
636 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
637
66aee91a 638 save->cr4 = X86_CR4_PAE;
6aa8b732 639 /* rdx = ?? */
709ddebf
JR		 640
641 if (npt_enabled) {
642 /* Setup VMCB for Nested Paging */
643 control->nested_ctl = 1;
a7052897
MT		 644 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
645 (1ULL << INTERCEPT_INVLPG));
709ddebf 646 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 647 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
648 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 649 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 650 save->cr3 = 0;
651 save->cr4 = 0;
652 }
a79d2f18 653 force_new_asid(&svm->vcpu);
1371d904 654
e6aa9abd 655 svm->nested.vmcb = 0;
2af9194d
JR		 656 svm->vcpu.arch.hflags = 0;
657
565d0998
ML		 658 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
659 control->pause_filter_count = 3000;
660 control->intercept |= (1ULL << INTERCEPT_PAUSE);
661 }
662
2af9194d 663 enable_gif(svm);
6aa8b732
AK		 664}
665
e00c8cf2 666static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 667{
668 struct vcpu_svm *svm = to_svm(vcpu);
669
e6101a96 670 init_vmcb(svm);
70433389 671
c5af89b6 672 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 673 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 674 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
675 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 676 }
5fdbf976
MT		 677 vcpu->arch.regs_avail = ~0;
678 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 679
680 return 0;
04d2cc77
AK		 681}
682
fb3f0f51 683static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 684{
a2fa3e9f 685 struct vcpu_svm *svm;
6aa8b732 686 struct page *page;
f65c229c 687 struct page *msrpm_pages;
b286d5d8 688 struct page *hsave_page;
3d6368ef 689 struct page *nested_msrpm_pages;
fb3f0f51 690 int err;
6aa8b732 691
c16f862d 692 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 693 if (!svm) {
694 err = -ENOMEM;
695 goto out;
696 }
697
698 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
699 if (err)
700 goto free_svm;
701
6aa8b732 702 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 703 if (!page) {
704 err = -ENOMEM;
705 goto uninit;
706 }
6aa8b732 707
f65c229c
JR		 708 err = -ENOMEM;
709 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
710 if (!msrpm_pages)
711 goto uninit;
3d6368ef
AG		 712
713 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
714 if (!nested_msrpm_pages)
715 goto uninit;
716
f65c229c
JR		 717 svm->msrpm = page_address(msrpm_pages);
718 svm_vcpu_init_msrpm(svm->msrpm);
719
b286d5d8
AG		 720 hsave_page = alloc_page(GFP_KERNEL);
721 if (!hsave_page)
722 goto uninit;
e6aa9abd 723 svm->nested.hsave = page_address(hsave_page);
b286d5d8 724
e6aa9abd 725 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 726
a2fa3e9f
GH		 727 svm->vmcb = page_address(page);
728 clear_page(svm->vmcb);
729 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
730 svm->asid_generation = 0;
e6101a96 731 init_vmcb(svm);
a2fa3e9f 732
fb3f0f51 733 fx_init(&svm->vcpu);
ad312c7c 734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 735 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 737
fb3f0f51 738 return &svm->vcpu;
36241b8c 739
fb3f0f51
RR		 740uninit:
741 kvm_vcpu_uninit(&svm->vcpu);
742free_svm:
a4770347 743 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 744out:
745 return ERR_PTR(err);
6aa8b732
AK		 746}
747
748static void svm_free_vcpu(struct kvm_vcpu *vcpu)
749{
a2fa3e9f
GH		 750 struct vcpu_svm *svm = to_svm(vcpu);
751
fb3f0f51 752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 756 kvm_vcpu_uninit(vcpu);
a4770347 757 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 758}
759
15ad7146 760static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 761{
a2fa3e9f 762 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 763 int i;
0cc5064d 764
0cc5064d 765 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 766 u64 delta;
0cc5064d 767
953899b6
JR		 768 if (check_tsc_unstable()) {
769 /*
770 * Make sure that the guest sees a monotonically
771 * increasing TSC.
772 */
773 delta = vcpu->arch.host_tsc - native_read_tsc();
774 svm->vmcb->control.tsc_offset += delta;
775 if (is_nested(svm))
776 svm->nested.hsave->control.tsc_offset += delta;
777 }
0cc5064d 778 vcpu->cpu = cpu;
2f599714 779 kvm_migrate_timers(vcpu);
4b656b12 780 svm->asid_generation = 0;
0cc5064d 781 }
94dfbdb3
AL		 782
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 784 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 785}
786
787static void svm_vcpu_put(struct kvm_vcpu *vcpu)
788{
a2fa3e9f 789 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 790 int i;
791
e1beb1d3 792 ++vcpu->stat.host_state_reload;
94dfbdb3 793 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 794 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 795
e935d48e 796 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 797}
798
6aa8b732
AK		 799static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
800{
a2fa3e9f 801 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 802}
803
804static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
805{
a2fa3e9f 806 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 807}
808
6de4f3ad
AK		 809static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
810{
811 switch (reg) {
812 case VCPU_EXREG_PDPTR:
813 BUG_ON(!npt_enabled);
814 load_pdptrs(vcpu, vcpu->arch.cr3);
815 break;
816 default:
817 BUG();
818 }
819}
820
f0b85051
AG		 821static void svm_set_vintr(struct vcpu_svm *svm)
822{
823 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
824}
825
826static void svm_clear_vintr(struct vcpu_svm *svm)
827{
828 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
829}
830
6aa8b732
AK		 831static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
832{
a2fa3e9f 833 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 834
835 switch (seg) {
836 case VCPU_SREG_CS: return &save->cs;
837 case VCPU_SREG_DS: return &save->ds;
838 case VCPU_SREG_ES: return &save->es;
839 case VCPU_SREG_FS: return &save->fs;
840 case VCPU_SREG_GS: return &save->gs;
841 case VCPU_SREG_SS: return &save->ss;
842 case VCPU_SREG_TR: return &save->tr;
843 case VCPU_SREG_LDTR: return &save->ldtr;
844 }
845 BUG();
8b6d44c7 846 return NULL;
6aa8b732
AK		 847}
848
849static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
850{
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
852
853 return s->base;
854}
855
856static void svm_get_segment(struct kvm_vcpu *vcpu,
857 struct kvm_segment *var, int seg)
858{
859 struct vmcb_seg *s = svm_seg(vcpu, seg);
860
861 var->base = s->base;
862 var->limit = s->limit;
863 var->selector = s->selector;
864 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
865 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
866 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
867 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
868 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
869 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
870 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
871 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 872
19bca6ab
AP		 873 /* AMD's VMCB does not have an explicit unusable field, so emulate it
874 * for cross vendor migration purposes by "not present"
875 */
876 var->unusable = !var->present || (var->type == 0);
877
1fbdc7a5
AP		 878 switch (seg) {
879 case VCPU_SREG_CS:
880 /*
881 * SVM always stores 0 for the 'G' bit in the CS selector in
882 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
883 * Intel's VMENTRY has a check on the 'G' bit.
884 */
25022acc 885 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 886 break;
887 case VCPU_SREG_TR:
888 /*
889 * Work around a bug where the busy flag in the tr selector
890 * isn't exposed
891 */
c0d09828 892 var->type |= 0x2;
1fbdc7a5
AP		 893 break;
894 case VCPU_SREG_DS:
895 case VCPU_SREG_ES:
896 case VCPU_SREG_FS:
897 case VCPU_SREG_GS:
898 /*
899 * The accessed bit must always be set in the segment
900 * descriptor cache, although it can be cleared in the
901 * descriptor, the cached bit always remains at 1. Since
902 * Intel has a check on this, set it here to support
903 * cross-vendor migration.
904 */
905 if (!var->unusable)
906 var->type |= 0x1;
907 break;
b586eb02
AP		 908 case VCPU_SREG_SS:
909 /* On AMD CPUs sometimes the DB bit in the segment
910 * descriptor is left as 1, although the whole segment has
911 * been made unusable. Clear it here to pass an Intel VMX
912 * entry check when cross vendor migrating.
913 */
914 if (var->unusable)
915 var->db = 0;
916 break;
1fbdc7a5 917 }
6aa8b732
AK		 918}
919
2e4d2653
IE		 920static int svm_get_cpl(struct kvm_vcpu *vcpu)
921{
922 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
923
924 return save->cpl;
925}
926
6aa8b732
AK		 927static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928{
a2fa3e9f
GH		 929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 dt->limit = svm->vmcb->save.idtr.limit;
932 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 933}
934
935static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936{
a2fa3e9f
GH		 937 struct vcpu_svm *svm = to_svm(vcpu);
938
939 svm->vmcb->save.idtr.limit = dt->limit;
940 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 941}
942
943static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944{
a2fa3e9f
GH		 945 struct vcpu_svm *svm = to_svm(vcpu);
946
947 dt->limit = svm->vmcb->save.gdtr.limit;
948 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 949}
950
951static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
952{
a2fa3e9f
GH		 953 struct vcpu_svm *svm = to_svm(vcpu);
954
955 svm->vmcb->save.gdtr.limit = dt->limit;
956 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 957}
958
e8467fda
AK		 959static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
960{
961}
962
25c4c276 963static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 964{
965}
966
d225157b
AK		 967static void update_cr0_intercept(struct vcpu_svm *svm)
968{
969 ulong gcr0 = svm->vcpu.arch.cr0;
970 u64 *hcr0 = &svm->vmcb->save.cr0;
971
972 if (!svm->vcpu.fpu_active)
973 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
974 else
975 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
976 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
977
978
979 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
980 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
981 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
982 } else {
983 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
984 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
985 }
986}
987
6aa8b732
AK		 988static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
989{
a2fa3e9f
GH		 990 struct vcpu_svm *svm = to_svm(vcpu);
991
05b3e0c2 992#ifdef CONFIG_X86_64
ad312c7c 993 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 994 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 995 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 996 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 997 }
998
d77c26fc 999 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 1000 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 1001 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1002 }
1003 }
1004#endif
ad312c7c 1005 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1006
1007 if (!npt_enabled)
1008 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1009
1010 if (!vcpu->fpu_active)
334df50a 1011 cr0 |= X86_CR0_TS;
709ddebf
JR		 1012 /*
1013 * re-enable caching here because the QEMU bios
1014 * does not do it - this results in some delay at
1015 * reboot
1016 */
1017 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1018 svm->vmcb->save.cr0 = cr0;
d225157b 1019 update_cr0_intercept(svm);
6aa8b732
AK		 1020}
1021
1022static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1023{
6394b649 1024 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1025 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1026
1027 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1028 force_new_asid(vcpu);
6394b649 1029
ec077263
JR		 1030 vcpu->arch.cr4 = cr4;
1031 if (!npt_enabled)
1032 cr4 |= X86_CR4_PAE;
6394b649 1033 cr4 |= host_cr4_mce;
ec077263 1034 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1035}
1036
1037static void svm_set_segment(struct kvm_vcpu *vcpu,
1038 struct kvm_segment *var, int seg)
1039{
a2fa3e9f 1040 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1041 struct vmcb_seg *s = svm_seg(vcpu, seg);
1042
1043 s->base = var->base;
1044 s->limit = var->limit;
1045 s->selector = var->selector;
1046 if (var->unusable)
1047 s->attrib = 0;
1048 else {
1049 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1050 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1051 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1052 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1053 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1054 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1055 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1056 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1057 }
1058 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1059 svm->vmcb->save.cpl
1060 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1061 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1062
1063}
1064
44c11430 1065static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1066{
d0bfb940
JK		 1067 struct vcpu_svm *svm = to_svm(vcpu);
1068
d0bfb940
JK		 1069 svm->vmcb->control.intercept_exceptions &=
1070 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1071
6be7d306 1072 if (svm->nmi_singlestep)
44c11430
GN		 1073 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1074
d0bfb940
JK		 1075 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1076 if (vcpu->guest_debug &
1077 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1078 svm->vmcb->control.intercept_exceptions |=
1079 1 << DB_VECTOR;
1080 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1081 svm->vmcb->control.intercept_exceptions |=
1082 1 << BP_VECTOR;
1083 } else
1084 vcpu->guest_debug = 0;
44c11430
GN		 1085}
1086
355be0b9 1087static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1088{
44c11430
GN		 1089 struct vcpu_svm *svm = to_svm(vcpu);
1090
ae675ef0
JK		 1091 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1092 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1093 else
1094 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1095
355be0b9 1096 update_db_intercept(vcpu);
6aa8b732
AK		 1097}
1098
1099static void load_host_msrs(struct kvm_vcpu *vcpu)
1100{
94dfbdb3 1101#ifdef CONFIG_X86_64
a2fa3e9f 1102 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1103#endif
6aa8b732
AK		 1104}
1105
1106static void save_host_msrs(struct kvm_vcpu *vcpu)
1107{
94dfbdb3 1108#ifdef CONFIG_X86_64
a2fa3e9f 1109 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1110#endif
6aa8b732
AK		 1111}
1112
0fe1e009 1113static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1114{
0fe1e009
TH		 1115 if (sd->next_asid > sd->max_asid) {
1116 ++sd->asid_generation;
1117 sd->next_asid = 1;
a2fa3e9f 1118 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1119 }
1120
0fe1e009
TH		 1121 svm->asid_generation = sd->asid_generation;
1122 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1123}
1124
c76de350 1125static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1126{
42dbaa5a 1127 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1128
1129 switch (dr) {
1130 case 0 ... 3:
c76de350 1131 *dest = vcpu->arch.db[dr];
42dbaa5a 1132 break;
c76de350
JK		 1133 case 4:
1134 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1135 return EMULATE_FAIL; /* will re-inject UD */
1136 /* fall through */
42dbaa5a
JK		 1137 case 6:
1138 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1139 *dest = vcpu->arch.dr6;
42dbaa5a 1140 else
c76de350 1141 *dest = svm->vmcb->save.dr6;
42dbaa5a 1142 break;
c76de350
JK		 1143 case 5:
1144 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1145 return EMULATE_FAIL; /* will re-inject UD */
1146 /* fall through */
42dbaa5a
JK		 1147 case 7:
1148 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1149 *dest = vcpu->arch.dr7;
42dbaa5a 1150 else
c76de350 1151 *dest = svm->vmcb->save.dr7;
42dbaa5a 1152 break;
42dbaa5a
JK		 1153 }
1154
c76de350 1155 return EMULATE_DONE;
6aa8b732
AK		 1156}
1157
c76de350 1158static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1159{
a2fa3e9f
GH		 1160 struct vcpu_svm *svm = to_svm(vcpu);
1161
6aa8b732
AK		 1162 switch (dr) {
1163 case 0 ... 3:
42dbaa5a
JK		 1164 vcpu->arch.db[dr] = value;
1165 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1166 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1167 break;
1168 case 4:
1169 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1170 return EMULATE_FAIL; /* will re-inject UD */
1171 /* fall through */
42dbaa5a 1172 case 6:
42dbaa5a 1173 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1174 break;
1175 case 5:
1176 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1177 return EMULATE_FAIL; /* will re-inject UD */
1178 /* fall through */
42dbaa5a 1179 case 7:
42dbaa5a
JK		 1180 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1181 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1182 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1183 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1184 }
c76de350 1185 break;
6aa8b732 1186 }
c76de350
JK		 1187
1188 return EMULATE_DONE;
6aa8b732
AK		 1189}
1190
851ba692 1191static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1192{
6aa8b732
AK		 1193 u64 fault_address;
1194 u32 error_code;
6aa8b732 1195
a2fa3e9f
GH		 1196 fault_address = svm->vmcb->control.exit_info_2;
1197 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1198
229456fc 1199 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1200 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1201 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1202 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1203}
1204
851ba692 1205static int db_interception(struct vcpu_svm *svm)
d0bfb940 1206{
851ba692
AK		 1207 struct kvm_run *kvm_run = svm->vcpu.run;
1208
d0bfb940 1209 if (!(svm->vcpu.guest_debug &
44c11430 1210 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1211 !svm->nmi_singlestep) {
d0bfb940
JK		 1212 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1213 return 1;
1214 }
44c11430 1215
6be7d306
JK		 1216 if (svm->nmi_singlestep) {
1217 svm->nmi_singlestep = false;
44c11430
GN		 1218 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1219 svm->vmcb->save.rflags &=
1220 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1221 update_db_intercept(&svm->vcpu);
1222 }
1223
1224 if (svm->vcpu.guest_debug &
1225 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1226 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1227 kvm_run->debug.arch.pc =
1228 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1229 kvm_run->debug.arch.exception = DB_VECTOR;
1230 return 0;
1231 }
1232
1233 return 1;
d0bfb940
JK		 1234}
1235
851ba692 1236static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1237{
851ba692
AK		 1238 struct kvm_run *kvm_run = svm->vcpu.run;
1239
d0bfb940
JK		 1240 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1241 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1242 kvm_run->debug.arch.exception = BP_VECTOR;
1243 return 0;
1244}
1245
851ba692 1246static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1247{
1248 int er;
1249
851ba692 1250 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1251 if (er != EMULATE_DONE)
7ee5d940 1252 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1253 return 1;
1254}
1255
851ba692 1256static int nm_interception(struct vcpu_svm *svm)
7807fa6c 1257{
a2fa3e9f 1258 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
e756fc62 1259 svm->vcpu.fpu_active = 1;
d225157b 1260 update_cr0_intercept(svm);
a2fa3e9f
GH		 1261
1262 return 1;
7807fa6c
AL		 1263}
1264
851ba692 1265static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1266{
1267 /*
1268 * On an #MC intercept the MCE handler is not called automatically in
1269 * the host. So do it by hand here.
1270 */
1271 asm volatile (
1272 "int $0x12\n");
1273 /* not sure if we ever come back to this point */
1274
1275 return 1;
1276}
1277
851ba692 1278static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1279{
851ba692
AK		 1280 struct kvm_run *kvm_run = svm->vcpu.run;
1281
46fe4ddd
JR		 1282 /*
1283 * VMCB is undefined after a SHUTDOWN intercept
1284 * so reinitialize it.
1285 */
a2fa3e9f 1286 clear_page(svm->vmcb);
e6101a96 1287 init_vmcb(svm);
46fe4ddd
JR		 1288
1289 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1290 return 0;
1291}
1292
851ba692 1293static int io_interception(struct vcpu_svm *svm)
6aa8b732 1294{
d77c26fc 1295 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1296 int size, in, string;
039576c0 1297 unsigned port;
6aa8b732 1298
e756fc62 1299 ++svm->vcpu.stat.io_exits;
6aa8b732 1300
a2fa3e9f 1301 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1302
e70669ab
LV		 1303 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1304
1305 if (string) {
3427318f 1306 if (emulate_instruction(&svm->vcpu,
851ba692 1307 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1308 return 0;
1309 return 1;
1310 }
1311
039576c0
AK		 1312 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1313 port = io_info >> 16;
1314 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1315
e93f36bc 1316 skip_emulated_instruction(&svm->vcpu);
851ba692 1317 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1318}
1319
851ba692 1320static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1321{
1322 return 1;
1323}
1324
851ba692 1325static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1326{
1327 ++svm->vcpu.stat.irq_exits;
1328 return 1;
1329}
1330
851ba692 1331static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1332{
1333 return 1;
1334}
1335
851ba692 1336static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1337{
5fdbf976 1338 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1339 skip_emulated_instruction(&svm->vcpu);
1340 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1341}
1342
851ba692 1343static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1344{
5fdbf976 1345 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1346 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1347 kvm_emulate_hypercall(&svm->vcpu);
1348 return 1;
02e235bc
AK		 1349}
1350
c0725420
AG		 1351static int nested_svm_check_permissions(struct vcpu_svm *svm)
1352{
1353 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1354 || !is_paging(&svm->vcpu)) {
1355 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1356 return 1;
1357 }
1358
1359 if (svm->vmcb->save.cpl) {
1360 kvm_inject_gp(&svm->vcpu, 0);
1361 return 1;
1362 }
1363
1364 return 0;
1365}
1366
cf74a78b
AG		 1367static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1368 bool has_error_code, u32 error_code)
1369{
0295ad7d
JR		 1370 if (!is_nested(svm))
1371 return 0;
cf74a78b 1372
0295ad7d
JR		 1373 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1374 svm->vmcb->control.exit_code_hi = 0;
1375 svm->vmcb->control.exit_info_1 = error_code;
1376 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1377
410e4d57 1378 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1379}
1380
1381static inline int nested_svm_intr(struct vcpu_svm *svm)
1382{
26666957
JR		 1383 if (!is_nested(svm))
1384 return 0;
cf74a78b 1385
26666957
JR		 1386 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1387 return 0;
cf74a78b 1388
26666957
JR		 1389 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1390 return 0;
cf74a78b 1391
26666957
JR		 1392 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1393
cd3ff653
JR		 1394 if (svm->nested.intercept & 1ULL) {
1395 /*
1396 * The #vmexit can't be emulated here directly because this
1397 * code path runs with irqs and preemtion disabled. A
1398 * #vmexit emulation might sleep. Only signal request for
1399 * the #vmexit here.
1400 */
1401 svm->nested.exit_required = true;
236649de 1402 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1403 return 1;
cf74a78b
AG		 1404 }
1405
1406 return 0;
1407}
1408
34f80cfa
JR		 1409static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1410{
1411 struct page *page;
1412
34f80cfa 1413 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1414 if (is_error_page(page))
1415 goto error;
1416
1417 return kmap_atomic(page, idx);
1418
1419error:
1420 kvm_release_page_clean(page);
1421 kvm_inject_gp(&svm->vcpu, 0);
1422
1423 return NULL;
1424}
1425
1426static void nested_svm_unmap(void *addr, enum km_type idx)
1427{
1428 struct page *page;
1429
1430 if (!addr)
1431 return;
1432
1433 page = kmap_atomic_to_page(addr);
1434
1435 kunmap_atomic(addr, idx);
1436 kvm_release_page_dirty(page);
1437}
1438
3d62d9aa 1439static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1440{
4c2161ae 1441 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1442 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1443 bool ret = false;
1444 u32 t0, t1;
1445 u8 *msrpm;
4c2161ae 1446
3d62d9aa
JR		 1447 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1448 return false;
1449
1450 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1451
1452 if (!msrpm)
1453 goto out;
4c2161ae
JR		 1454
1455 switch (msr) {
1456 case 0 ... 0x1fff:
1457 t0 = (msr * 2) % 8;
1458 t1 = msr / 8;
1459 break;
1460 case 0xc0000000 ... 0xc0001fff:
1461 t0 = (8192 + msr - 0xc0000000) * 2;
1462 t1 = (t0 / 8);
1463 t0 %= 8;
1464 break;
1465 case 0xc0010000 ... 0xc0011fff:
1466 t0 = (16384 + msr - 0xc0010000) * 2;
1467 t1 = (t0 / 8);
1468 t0 %= 8;
1469 break;
1470 default:
3d62d9aa
JR		 1471 ret = true;
1472 goto out;
4c2161ae 1473 }
4c2161ae 1474
3d62d9aa
JR		 1475 ret = msrpm[t1] & ((1 << param) << t0);
1476
1477out:
1478 nested_svm_unmap(msrpm, KM_USER0);
1479
1480 return ret;
4c2161ae
JR		 1481}
1482
410e4d57 1483static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1484{
cf74a78b 1485 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1486
410e4d57
JR		 1487 switch (exit_code) {
1488 case SVM_EXIT_INTR:
1489 case SVM_EXIT_NMI:
1490 return NESTED_EXIT_HOST;
cf74a78b 1491 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1492 case SVM_EXIT_NPF:
1493 if (npt_enabled)
1494 return NESTED_EXIT_HOST;
1495 break;
1496 /* When we're shadowing, trap PFs */
1497 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1498 if (!npt_enabled)
1499 return NESTED_EXIT_HOST;
1500 break;
1501 default:
1502 break;
cf74a78b
AG		 1503 }
1504
410e4d57
JR		 1505 return NESTED_EXIT_CONTINUE;
1506}
1507
1508/*
1509 * If this function returns true, this #vmexit was already handled
1510 */
1511static int nested_svm_exit_handled(struct vcpu_svm *svm)
1512{
1513 u32 exit_code = svm->vmcb->control.exit_code;
1514 int vmexit = NESTED_EXIT_HOST;
1515
cf74a78b 1516 switch (exit_code) {
9c4e40b9 1517 case SVM_EXIT_MSR:
3d62d9aa 1518 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1519 break;
cf74a78b
AG		 1520 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1521 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1522 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1523 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1524 break;
1525 }
1526 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1527 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1528 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1529 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1530 break;
1531 }
1532 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1533 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1534 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1535 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1536 break;
1537 }
1538 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1539 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1540 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1541 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1542 break;
1543 }
1544 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1545 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1546 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1547 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1548 break;
1549 }
1550 default: {
1551 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1552 if (svm->nested.intercept & exit_bits)
410e4d57 1553 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1554 }
1555 }
1556
410e4d57 1557 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1558 nested_svm_vmexit(svm);
1559 }
1560
1561 return vmexit;
cf74a78b
AG		 1562}
1563
0460a979
JR		 1564static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1565{
1566 struct vmcb_control_area *dst = &dst_vmcb->control;
1567 struct vmcb_control_area *from = &from_vmcb->control;
1568
1569 dst->intercept_cr_read = from->intercept_cr_read;
1570 dst->intercept_cr_write = from->intercept_cr_write;
1571 dst->intercept_dr_read = from->intercept_dr_read;
1572 dst->intercept_dr_write = from->intercept_dr_write;
1573 dst->intercept_exceptions = from->intercept_exceptions;
1574 dst->intercept = from->intercept;
1575 dst->iopm_base_pa = from->iopm_base_pa;
1576 dst->msrpm_base_pa = from->msrpm_base_pa;
1577 dst->tsc_offset = from->tsc_offset;
1578 dst->asid = from->asid;
1579 dst->tlb_ctl = from->tlb_ctl;
1580 dst->int_ctl = from->int_ctl;
1581 dst->int_vector = from->int_vector;
1582 dst->int_state = from->int_state;
1583 dst->exit_code = from->exit_code;
1584 dst->exit_code_hi = from->exit_code_hi;
1585 dst->exit_info_1 = from->exit_info_1;
1586 dst->exit_info_2 = from->exit_info_2;
1587 dst->exit_int_info = from->exit_int_info;
1588 dst->exit_int_info_err = from->exit_int_info_err;
1589 dst->nested_ctl = from->nested_ctl;
1590 dst->event_inj = from->event_inj;
1591 dst->event_inj_err = from->event_inj_err;
1592 dst->nested_cr3 = from->nested_cr3;
1593 dst->lbr_ctl = from->lbr_ctl;
1594}
1595
34f80cfa 1596static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1597{
34f80cfa 1598 struct vmcb *nested_vmcb;
e6aa9abd 1599 struct vmcb *hsave = svm->nested.hsave;
33740e40 1600 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1601
17897f36
JR		 1602 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1603 vmcb->control.exit_info_1,
1604 vmcb->control.exit_info_2,
1605 vmcb->control.exit_int_info,
1606 vmcb->control.exit_int_info_err);
1607
34f80cfa
JR		 1608 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1609 if (!nested_vmcb)
1610 return 1;
1611
cf74a78b 1612 /* Give the current vmcb to the guest */
33740e40
JR		 1613 disable_gif(svm);
1614
1615 nested_vmcb->save.es = vmcb->save.es;
1616 nested_vmcb->save.cs = vmcb->save.cs;
1617 nested_vmcb->save.ss = vmcb->save.ss;
1618 nested_vmcb->save.ds = vmcb->save.ds;
1619 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1620 nested_vmcb->save.idtr = vmcb->save.idtr;
1621 if (npt_enabled)
1622 nested_vmcb->save.cr3 = vmcb->save.cr3;
1623 nested_vmcb->save.cr2 = vmcb->save.cr2;
1624 nested_vmcb->save.rflags = vmcb->save.rflags;
1625 nested_vmcb->save.rip = vmcb->save.rip;
1626 nested_vmcb->save.rsp = vmcb->save.rsp;
1627 nested_vmcb->save.rax = vmcb->save.rax;
1628 nested_vmcb->save.dr7 = vmcb->save.dr7;
1629 nested_vmcb->save.dr6 = vmcb->save.dr6;
1630 nested_vmcb->save.cpl = vmcb->save.cpl;
1631
1632 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1633 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1634 nested_vmcb->control.int_state = vmcb->control.int_state;
1635 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1636 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1637 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1638 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1639 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1640 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1641
1642 /*
1643 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1644 * to make sure that we do not lose injected events. So check event_inj
1645 * here and copy it to exit_int_info if it is valid.
1646 * Exit_int_info and event_inj can't be both valid because the case
1647 * below only happens on a VMRUN instruction intercept which has
1648 * no valid exit_int_info set.
1649 */
1650 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1651 struct vmcb_control_area *nc = &nested_vmcb->control;
1652
1653 nc->exit_int_info = vmcb->control.event_inj;
1654 nc->exit_int_info_err = vmcb->control.event_inj_err;
1655 }
1656
33740e40
JR		 1657 nested_vmcb->control.tlb_ctl = 0;
1658 nested_vmcb->control.event_inj = 0;
1659 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1660
1661 /* We always set V_INTR_MASKING and remember the old value in hflags */
1662 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1663 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1664
cf74a78b 1665 /* Restore the original control entries */
0460a979 1666 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1667
219b65dc
AG		 1668 kvm_clear_exception_queue(&svm->vcpu);
1669 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1670
1671 /* Restore selected save entries */
1672 svm->vmcb->save.es = hsave->save.es;
1673 svm->vmcb->save.cs = hsave->save.cs;
1674 svm->vmcb->save.ss = hsave->save.ss;
1675 svm->vmcb->save.ds = hsave->save.ds;
1676 svm->vmcb->save.gdtr = hsave->save.gdtr;
1677 svm->vmcb->save.idtr = hsave->save.idtr;
1678 svm->vmcb->save.rflags = hsave->save.rflags;
1679 svm_set_efer(&svm->vcpu, hsave->save.efer);
1680 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1681 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1682 if (npt_enabled) {
1683 svm->vmcb->save.cr3 = hsave->save.cr3;
1684 svm->vcpu.arch.cr3 = hsave->save.cr3;
1685 } else {
1686 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1687 }
1688 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1689 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1690 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1691 svm->vmcb->save.dr7 = 0;
1692 svm->vmcb->save.cpl = 0;
1693 svm->vmcb->control.exit_int_info = 0;
1694
cf74a78b 1695 /* Exit nested SVM mode */
e6aa9abd 1696 svm->nested.vmcb = 0;
cf74a78b 1697
34f80cfa 1698 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1699
1700 kvm_mmu_reset_context(&svm->vcpu);
1701 kvm_mmu_load(&svm->vcpu);
1702
1703 return 0;
1704}
3d6368ef 1705
9738b2c9 1706static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1707{
9738b2c9 1708 u32 *nested_msrpm;
3d6368ef 1709 int i;
9738b2c9
JR		 1710
1711 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1712 if (!nested_msrpm)
1713 return false;
1714
3d6368ef 1715 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1716 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1717
e6aa9abd 1718 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1719
9738b2c9
JR		 1720 nested_svm_unmap(nested_msrpm, KM_USER0);
1721
1722 return true;
3d6368ef
AG		 1723}
1724
9738b2c9 1725static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1726{
9738b2c9 1727 struct vmcb *nested_vmcb;
e6aa9abd 1728 struct vmcb *hsave = svm->nested.hsave;
defbba56 1729 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1730
9738b2c9
JR		 1731 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1732 if (!nested_vmcb)
1733 return false;
1734
3d6368ef 1735 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1736 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1737
0ac406de
JR		 1738 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1739 nested_vmcb->save.rip,
1740 nested_vmcb->control.int_ctl,
1741 nested_vmcb->control.event_inj,
1742 nested_vmcb->control.nested_ctl);
1743
3d6368ef 1744 /* Clear internal status */
219b65dc
AG		 1745 kvm_clear_exception_queue(&svm->vcpu);
1746 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1747
1748 /* Save the old vmcb, so we don't need to pick what we save, but
1749 can restore everything when a VMEXIT occurs */
defbba56
JR		 1750 hsave->save.es = vmcb->save.es;
1751 hsave->save.cs = vmcb->save.cs;
1752 hsave->save.ss = vmcb->save.ss;
1753 hsave->save.ds = vmcb->save.ds;
1754 hsave->save.gdtr = vmcb->save.gdtr;
1755 hsave->save.idtr = vmcb->save.idtr;
1756 hsave->save.efer = svm->vcpu.arch.shadow_efer;
4d4ec087 1757 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1758 hsave->save.cr4 = svm->vcpu.arch.cr4;
1759 hsave->save.rflags = vmcb->save.rflags;
1760 hsave->save.rip = svm->next_rip;
1761 hsave->save.rsp = vmcb->save.rsp;
1762 hsave->save.rax = vmcb->save.rax;
1763 if (npt_enabled)
1764 hsave->save.cr3 = vmcb->save.cr3;
1765 else
1766 hsave->save.cr3 = svm->vcpu.arch.cr3;
1767
0460a979 1768 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1769
1770 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1771 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1772 else
1773 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1774
1775 /* Load the nested guest state */
1776 svm->vmcb->save.es = nested_vmcb->save.es;
1777 svm->vmcb->save.cs = nested_vmcb->save.cs;
1778 svm->vmcb->save.ss = nested_vmcb->save.ss;
1779 svm->vmcb->save.ds = nested_vmcb->save.ds;
1780 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1781 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1782 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1783 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1784 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1785 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1786 if (npt_enabled) {
1787 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1788 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1789 } else {
1790 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1791 kvm_mmu_reset_context(&svm->vcpu);
1792 }
defbba56 1793 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1794 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1795 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1796 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1797 /* In case we don't even reach vcpu_run, the fields are not updated */
1798 svm->vmcb->save.rax = nested_vmcb->save.rax;
1799 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1800 svm->vmcb->save.rip = nested_vmcb->save.rip;
1801 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1802 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1803 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1804
1805 /* We don't want a nested guest to be more powerful than the guest,
1806 so all intercepts are ORed */
1807 svm->vmcb->control.intercept_cr_read |=
1808 nested_vmcb->control.intercept_cr_read;
1809 svm->vmcb->control.intercept_cr_write |=
1810 nested_vmcb->control.intercept_cr_write;
1811 svm->vmcb->control.intercept_dr_read |=
1812 nested_vmcb->control.intercept_dr_read;
1813 svm->vmcb->control.intercept_dr_write |=
1814 nested_vmcb->control.intercept_dr_write;
1815 svm->vmcb->control.intercept_exceptions |=
1816 nested_vmcb->control.intercept_exceptions;
1817
1818 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1819
e6aa9abd 1820 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1821
aad42c64
JR		 1822 /* cache intercepts */
1823 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1824 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1825 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1826 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1827 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1828 svm->nested.intercept = nested_vmcb->control.intercept;
1829
3d6368ef 1830 force_new_asid(&svm->vcpu);
3d6368ef 1831 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1832 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1833 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1834 else
1835 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1836
3d6368ef
AG		 1837 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1838 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1839 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1840 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1841 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1842
9738b2c9
JR		 1843 nested_svm_unmap(nested_vmcb, KM_USER0);
1844
2af9194d 1845 enable_gif(svm);
3d6368ef 1846
9738b2c9 1847 return true;
3d6368ef
AG		 1848}
1849
9966bf68 1850static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1851{
1852 to_vmcb->save.fs = from_vmcb->save.fs;
1853 to_vmcb->save.gs = from_vmcb->save.gs;
1854 to_vmcb->save.tr = from_vmcb->save.tr;
1855 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1856 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1857 to_vmcb->save.star = from_vmcb->save.star;
1858 to_vmcb->save.lstar = from_vmcb->save.lstar;
1859 to_vmcb->save.cstar = from_vmcb->save.cstar;
1860 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1861 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1862 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1863 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1864}
1865
851ba692 1866static int vmload_interception(struct vcpu_svm *svm)
5542675b 1867{
9966bf68
JR		 1868 struct vmcb *nested_vmcb;
1869
5542675b
AG		 1870 if (nested_svm_check_permissions(svm))
1871 return 1;
1872
1873 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1874 skip_emulated_instruction(&svm->vcpu);
1875
9966bf68
JR		 1876 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1877 if (!nested_vmcb)
1878 return 1;
1879
1880 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1881 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1882
1883 return 1;
1884}
1885
851ba692 1886static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1887{
9966bf68
JR		 1888 struct vmcb *nested_vmcb;
1889
5542675b
AG		 1890 if (nested_svm_check_permissions(svm))
1891 return 1;
1892
1893 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1894 skip_emulated_instruction(&svm->vcpu);
1895
9966bf68
JR		 1896 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1897 if (!nested_vmcb)
1898 return 1;
1899
1900 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1901 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1902
1903 return 1;
1904}
1905
851ba692 1906static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1907{
3d6368ef
AG		 1908 if (nested_svm_check_permissions(svm))
1909 return 1;
1910
1911 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1912 skip_emulated_instruction(&svm->vcpu);
1913
9738b2c9 1914 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1915 return 1;
1916
9738b2c9 1917 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1918 goto failed;
1919
1920 return 1;
1921
1922failed:
1923
1924 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1925 svm->vmcb->control.exit_code_hi = 0;
1926 svm->vmcb->control.exit_info_1 = 0;
1927 svm->vmcb->control.exit_info_2 = 0;
1928
1929 nested_svm_vmexit(svm);
3d6368ef
AG		 1930
1931 return 1;
1932}
1933
851ba692 1934static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1935{
1936 if (nested_svm_check_permissions(svm))
1937 return 1;
1938
1939 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1940 skip_emulated_instruction(&svm->vcpu);
1941
2af9194d 1942 enable_gif(svm);
1371d904
AG		 1943
1944 return 1;
1945}
1946
851ba692 1947static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1948{
1949 if (nested_svm_check_permissions(svm))
1950 return 1;
1951
1952 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1953 skip_emulated_instruction(&svm->vcpu);
1954
2af9194d 1955 disable_gif(svm);
1371d904
AG		 1956
1957 /* After a CLGI no interrupts should come */
1958 svm_clear_vintr(svm);
1959 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1960
1961 return 1;
1962}
1963
851ba692 1964static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1965{
1966 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 1967
ec1ff790
JR		 1968 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1969 vcpu->arch.regs[VCPU_REGS_RAX]);
1970
ff092385
AG		 1971 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1972 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1973
1974 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1975 skip_emulated_instruction(&svm->vcpu);
1976 return 1;
1977}
1978
532a46b9
JR		 1979static int skinit_interception(struct vcpu_svm *svm)
1980{
1981 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1982
1983 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1984 return 1;
1985}
1986
851ba692 1987static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1988{
7ee5d940 1989 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1990 return 1;
1991}
1992
851ba692 1993static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 1994{
37817f29 1995 u16 tss_selector;
64a7ec06
GN		 1996 int reason;
1997 int int_type = svm->vmcb->control.exit_int_info &
1998 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1999 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2000 uint32_t type =
2001 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2002 uint32_t idt_v =
2003 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2004
2005 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2006
37817f29
IE		 2007 if (svm->vmcb->control.exit_info_2 &
2008 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2009 reason = TASK_SWITCH_IRET;
2010 else if (svm->vmcb->control.exit_info_2 &
2011 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2012 reason = TASK_SWITCH_JMP;
fe8e7f83 2013 else if (idt_v)
64a7ec06
GN		 2014 reason = TASK_SWITCH_GATE;
2015 else
2016 reason = TASK_SWITCH_CALL;
2017
fe8e7f83
GN		 2018 if (reason == TASK_SWITCH_GATE) {
2019 switch (type) {
2020 case SVM_EXITINTINFO_TYPE_NMI:
2021 svm->vcpu.arch.nmi_injected = false;
2022 break;
2023 case SVM_EXITINTINFO_TYPE_EXEPT:
2024 kvm_clear_exception_queue(&svm->vcpu);
2025 break;
2026 case SVM_EXITINTINFO_TYPE_INTR:
2027 kvm_clear_interrupt_queue(&svm->vcpu);
2028 break;
2029 default:
2030 break;
2031 }
2032 }
64a7ec06 2033
8317c298
GN		 2034 if (reason != TASK_SWITCH_GATE ||
2035 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2036 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2037 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2038 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2039
2040 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2041}
2042
851ba692 2043static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2044{
5fdbf976 2045 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2046 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2047 return 1;
6aa8b732
AK		 2048}
2049
851ba692 2050static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2051{
2052 ++svm->vcpu.stat.nmi_window_exits;
2053 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2054 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2055 return 1;
2056}
2057
851ba692 2058static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2059{
851ba692 2060 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2061 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2062 return 1;
2063}
2064
851ba692 2065static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2066{
851ba692 2067 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2068 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2069 return 1;
2070}
2071
851ba692 2072static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2073{
851ba692
AK		 2074 struct kvm_run *kvm_run = svm->vcpu.run;
2075
0a5fff19
GN		 2076 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2077 /* instruction emulation calls kvm_set_cr8() */
851ba692 2078 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2079 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2080 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2081 return 1;
95ba8273 2082 }
0a5fff19
GN		 2083 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2084 return 1;
1d075434
JR		 2085 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2086 return 0;
2087}
2088
6aa8b732
AK		 2089static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2090{
a2fa3e9f
GH		 2091 struct vcpu_svm *svm = to_svm(vcpu);
2092
6aa8b732 2093 switch (ecx) {
af24a4e4 2094 case MSR_IA32_TSC: {
20824f30 2095 u64 tsc_offset;
6aa8b732 2096
20824f30
JR		 2097 if (is_nested(svm))
2098 tsc_offset = svm->nested.hsave->control.tsc_offset;
2099 else
2100 tsc_offset = svm->vmcb->control.tsc_offset;
2101
2102 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2103 break;
2104 }
0e859cac 2105 case MSR_K6_STAR:
a2fa3e9f 2106 *data = svm->vmcb->save.star;
6aa8b732 2107 break;
0e859cac 2108#ifdef CONFIG_X86_64
6aa8b732 2109 case MSR_LSTAR:
a2fa3e9f 2110 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2111 break;
2112 case MSR_CSTAR:
a2fa3e9f 2113 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2114 break;
2115 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2116 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2117 break;
2118 case MSR_SYSCALL_MASK:
a2fa3e9f 2119 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2120 break;
2121#endif
2122 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2123 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2124 break;
2125 case MSR_IA32_SYSENTER_EIP:
017cb99e 2126 *data = svm->sysenter_eip;
6aa8b732
AK		 2127 break;
2128 case MSR_IA32_SYSENTER_ESP:
017cb99e 2129 *data = svm->sysenter_esp;
6aa8b732 2130 break;
a2938c80
JR		 2131 /* Nobody will change the following 5 values in the VMCB so
2132 we can safely return them on rdmsr. They will always be 0
2133 until LBRV is implemented. */
2134 case MSR_IA32_DEBUGCTLMSR:
2135 *data = svm->vmcb->save.dbgctl;
2136 break;
2137 case MSR_IA32_LASTBRANCHFROMIP:
2138 *data = svm->vmcb->save.br_from;
2139 break;
2140 case MSR_IA32_LASTBRANCHTOIP:
2141 *data = svm->vmcb->save.br_to;
2142 break;
2143 case MSR_IA32_LASTINTFROMIP:
2144 *data = svm->vmcb->save.last_excp_from;
2145 break;
2146 case MSR_IA32_LASTINTTOIP:
2147 *data = svm->vmcb->save.last_excp_to;
2148 break;
b286d5d8 2149 case MSR_VM_HSAVE_PA:
e6aa9abd 2150 *data = svm->nested.hsave_msr;
b286d5d8 2151 break;
eb6f302e
JR		 2152 case MSR_VM_CR:
2153 *data = 0;
2154 break;
c8a73f18
AG		 2155 case MSR_IA32_UCODE_REV:
2156 *data = 0x01000065;
2157 break;
6aa8b732 2158 default:
3bab1f5d 2159 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2160 }
2161 return 0;
2162}
2163
851ba692 2164static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2165{
ad312c7c 2166 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2167 u64 data;
2168
e756fc62 2169 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2170 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2171 else {
229456fc 2172 trace_kvm_msr_read(ecx, data);
af9ca2d7 2173
5fdbf976 2174 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2175 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2176 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2177 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2178 }
2179 return 1;
2180}
2181
2182static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2183{
a2fa3e9f
GH		 2184 struct vcpu_svm *svm = to_svm(vcpu);
2185
6aa8b732 2186 switch (ecx) {
af24a4e4 2187 case MSR_IA32_TSC: {
20824f30
JR		 2188 u64 tsc_offset = data - native_read_tsc();
2189 u64 g_tsc_offset = 0;
2190
2191 if (is_nested(svm)) {
2192 g_tsc_offset = svm->vmcb->control.tsc_offset -
2193 svm->nested.hsave->control.tsc_offset;
2194 svm->nested.hsave->control.tsc_offset = tsc_offset;
2195 }
2196
2197 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2198
6aa8b732
AK		 2199 break;
2200 }
0e859cac 2201 case MSR_K6_STAR:
a2fa3e9f 2202 svm->vmcb->save.star = data;
6aa8b732 2203 break;
49b14f24 2204#ifdef CONFIG_X86_64
6aa8b732 2205 case MSR_LSTAR:
a2fa3e9f 2206 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2207 break;
2208 case MSR_CSTAR:
a2fa3e9f 2209 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2210 break;
2211 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2212 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2213 break;
2214 case MSR_SYSCALL_MASK:
a2fa3e9f 2215 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2216 break;
2217#endif
2218 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2219 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2220 break;
2221 case MSR_IA32_SYSENTER_EIP:
017cb99e 2222 svm->sysenter_eip = data;
a2fa3e9f 2223 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2224 break;
2225 case MSR_IA32_SYSENTER_ESP:
017cb99e 2226 svm->sysenter_esp = data;
a2fa3e9f 2227 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2228 break;
a2938c80 2229 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2230 if (!svm_has(SVM_FEATURE_LBRV)) {
2231 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2232 __func__, data);
24e09cbf
JR		 2233 break;
2234 }
2235 if (data & DEBUGCTL_RESERVED_BITS)
2236 return 1;
2237
2238 svm->vmcb->save.dbgctl = data;
2239 if (data & (1ULL<<0))
2240 svm_enable_lbrv(svm);
2241 else
2242 svm_disable_lbrv(svm);
a2938c80 2243 break;
b286d5d8 2244 case MSR_VM_HSAVE_PA:
e6aa9abd 2245 svm->nested.hsave_msr = data;
62b9abaa 2246 break;
3c5d0a44
AG		 2247 case MSR_VM_CR:
2248 case MSR_VM_IGNNE:
3c5d0a44
AG		 2249 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2250 break;
6aa8b732 2251 default:
3bab1f5d 2252 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2253 }
2254 return 0;
2255}
2256
851ba692 2257static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2258{
ad312c7c 2259 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2260 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2261 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2262
229456fc 2263 trace_kvm_msr_write(ecx, data);
af9ca2d7 2264
5fdbf976 2265 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2266 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2267 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2268 else
e756fc62 2269 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2270 return 1;
2271}
2272
851ba692 2273static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2274{
e756fc62 2275 if (svm->vmcb->control.exit_info_1)
851ba692 2276 return wrmsr_interception(svm);
6aa8b732 2277 else
851ba692 2278 return rdmsr_interception(svm);
6aa8b732
AK		 2279}
2280
851ba692 2281static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2282{
851ba692
AK		 2283 struct kvm_run *kvm_run = svm->vcpu.run;
2284
f0b85051 2285 svm_clear_vintr(svm);
85f455f7 2286 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2287 /*
2288 * If the user space waits to inject interrupts, exit as soon as
2289 * possible
2290 */
8061823a
GN		 2291 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2292 kvm_run->request_interrupt_window &&
2293 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2294 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2295 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2296 return 0;
2297 }
2298
2299 return 1;
2300}
2301
565d0998
ML		 2302static int pause_interception(struct vcpu_svm *svm)
2303{
2304 kvm_vcpu_on_spin(&(svm->vcpu));
2305 return 1;
2306}
2307
851ba692 2308static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2309 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2310 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2311 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2312 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2313 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2314 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2315 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2316 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2317 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2318 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2319 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2320 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2321 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2322 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2323 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2324 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2325 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2326 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2327 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2328 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2329 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2330 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2331 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2332 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2333 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2334 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2335 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2336 [SVM_EXIT_SMI] = nop_on_interception,
2337 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2338 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2339 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2340 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2341 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2342 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2343 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2344 [SVM_EXIT_HLT] = halt_interception,
a7052897 2345 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2346 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2347 [SVM_EXIT_IOIO] = io_interception,
2348 [SVM_EXIT_MSR] = msr_interception,
2349 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2350 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2351 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2352 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2353 [SVM_EXIT_VMLOAD] = vmload_interception,
2354 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2355 [SVM_EXIT_STGI] = stgi_interception,
2356 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2357 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2358 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2359 [SVM_EXIT_MONITOR] = invalid_op_interception,
2360 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2361 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2362};
2363
851ba692 2364static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2365{
04d2cc77 2366 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2367 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2368 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2369
229456fc 2370 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2371
cd3ff653
JR		 2372 if (unlikely(svm->nested.exit_required)) {
2373 nested_svm_vmexit(svm);
2374 svm->nested.exit_required = false;
2375
2376 return 1;
2377 }
2378
cf74a78b 2379 if (is_nested(svm)) {
410e4d57
JR		 2380 int vmexit;
2381
d8cabddf
JR		 2382 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2383 svm->vmcb->control.exit_info_1,
2384 svm->vmcb->control.exit_info_2,
2385 svm->vmcb->control.exit_int_info,
2386 svm->vmcb->control.exit_int_info_err);
2387
410e4d57
JR		 2388 vmexit = nested_svm_exit_special(svm);
2389
2390 if (vmexit == NESTED_EXIT_CONTINUE)
2391 vmexit = nested_svm_exit_handled(svm);
2392
2393 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2394 return 1;
cf74a78b
AG		 2395 }
2396
a5c3832d
JR		 2397 svm_complete_interrupts(svm);
2398
888f9f3e 2399 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2400 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2401 if (npt_enabled)
709ddebf 2402 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2403
2404 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2405 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2406 kvm_run->fail_entry.hardware_entry_failure_reason
2407 = svm->vmcb->control.exit_code;
2408 return 0;
2409 }
2410
a2fa3e9f 2411 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2412 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2413 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2414 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2415 "exit_code 0x%x\n",
b8688d51 2416 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2417 exit_code);
2418
9d8f549d 2419 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2420 || !svm_exit_handlers[exit_code]) {
6aa8b732 2421 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2422 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2423 return 0;
2424 }
2425
851ba692 2426 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2427}
2428
2429static void reload_tss(struct kvm_vcpu *vcpu)
2430{
2431 int cpu = raw_smp_processor_id();
2432
0fe1e009
TH		 2433 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2434 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2435 load_TR_desc();
2436}
2437
e756fc62 2438static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2439{
2440 int cpu = raw_smp_processor_id();
2441
0fe1e009 2442 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2443
a2fa3e9f 2444 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2445 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2446 if (svm->asid_generation != sd->asid_generation)
2447 new_asid(svm, sd);
6aa8b732
AK		 2448}
2449
95ba8273
GN		 2450static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2451{
2452 struct vcpu_svm *svm = to_svm(vcpu);
2453
2454 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2455 vcpu->arch.hflags |= HF_NMI_MASK;
2456 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2457 ++vcpu->stat.nmi_injections;
2458}
6aa8b732 2459
85f455f7 2460static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2461{
2462 struct vmcb_control_area *control;
2463
229456fc 2464 trace_kvm_inj_virq(irq);
af9ca2d7 2465
fa89a817 2466 ++svm->vcpu.stat.irq_injections;
e756fc62 2467 control = &svm->vmcb->control;
85f455f7 2468 control->int_vector = irq;
6aa8b732
AK		 2469 control->int_ctl &= ~V_INTR_PRIO_MASK;
2470 control->int_ctl |= V_IRQ_MASK |
2471 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2472}
2473
66fd3f7f 2474static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2475{
2476 struct vcpu_svm *svm = to_svm(vcpu);
2477
2af9194d 2478 BUG_ON(!(gif_set(svm)));
cf74a78b 2479
219b65dc
AG		 2480 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2481 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2482}
2483
95ba8273 2484static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2485{
2486 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2487
95ba8273 2488 if (irr == -1)
aaacfc9a
JR		 2489 return;
2490
95ba8273
GN		 2491 if (tpr >= irr)
2492 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2493}
aaacfc9a 2494
95ba8273
GN		 2495static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2496{
2497 struct vcpu_svm *svm = to_svm(vcpu);
2498 struct vmcb *vmcb = svm->vmcb;
2499 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2500 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2501}
2502
3cfc3092
JK		 2503static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2504{
2505 struct vcpu_svm *svm = to_svm(vcpu);
2506
2507 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2508}
2509
2510static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2511{
2512 struct vcpu_svm *svm = to_svm(vcpu);
2513
2514 if (masked) {
2515 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2516 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2517 } else {
2518 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2519 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2520 }
2521}
2522
78646121
GN		 2523static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2524{
2525 struct vcpu_svm *svm = to_svm(vcpu);
2526 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2527 int ret;
2528
2529 if (!gif_set(svm) ||
2530 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2531 return 0;
2532
2533 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2534
2535 if (is_nested(svm))
2536 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2537
2538 return ret;
78646121
GN		 2539}
2540
9222be18 2541static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2542{
219b65dc 2543 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2544
2545 nested_svm_intr(svm);
2546
2547 /* In case GIF=0 we can't rely on the CPU to tell us when
2548 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2549 * The next time we get that intercept, this function will be
2550 * called again though and we'll get the vintr intercept. */
2af9194d 2551 if (gif_set(svm)) {
219b65dc
AG		 2552 svm_set_vintr(svm);
2553 svm_inject_irq(svm, 0x0);
2554 }
85f455f7
ED		 2555}
2556
95ba8273 2557static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2558{
04d2cc77 2559 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2560
44c11430
GN		 2561 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2562 == HF_NMI_MASK)
2563 return; /* IRET will cause a vm exit */
2564
2565 /* Something prevents NMI from been injected. Single step over
2566 possible problem (IRET or exception injection or interrupt
2567 shadow) */
6be7d306 2568 svm->nmi_singlestep = true;
44c11430
GN		 2569 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2570 update_db_intercept(vcpu);
c1150d8c
DL		 2571}
2572
cbc94022
IE		 2573static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2574{
2575 return 0;
2576}
2577
d9e368d6
AK		 2578static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2579{
2580 force_new_asid(vcpu);
2581}
2582
04d2cc77
AK		 2583static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2584{
2585}
2586
d7bf8221
JR		 2587static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2588{
2589 struct vcpu_svm *svm = to_svm(vcpu);
2590
2591 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2592 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2593 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2594 }
2595}
2596
649d6864
JR		 2597static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2598{
2599 struct vcpu_svm *svm = to_svm(vcpu);
2600 u64 cr8;
2601
649d6864
JR		 2602 cr8 = kvm_get_cr8(vcpu);
2603 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2604 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2605}
2606
9222be18
GN		 2607static void svm_complete_interrupts(struct vcpu_svm *svm)
2608{
2609 u8 vector;
2610 int type;
2611 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2612
44c11430
GN		 2613 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2614 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2615
9222be18
GN		 2616 svm->vcpu.arch.nmi_injected = false;
2617 kvm_clear_exception_queue(&svm->vcpu);
2618 kvm_clear_interrupt_queue(&svm->vcpu);
2619
2620 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2621 return;
2622
2623 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2624 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2625
2626 switch (type) {
2627 case SVM_EXITINTINFO_TYPE_NMI:
2628 svm->vcpu.arch.nmi_injected = true;
2629 break;
2630 case SVM_EXITINTINFO_TYPE_EXEPT:
2631 /* In case of software exception do not reinject an exception
2632 vector, but re-execute and instruction instead */
219b65dc
AG		 2633 if (is_nested(svm))
2634 break;
66fd3f7f 2635 if (kvm_exception_is_soft(vector))
9222be18
GN		 2636 break;
2637 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2638 u32 err = svm->vmcb->control.exit_int_info_err;
2639 kvm_queue_exception_e(&svm->vcpu, vector, err);
2640
2641 } else
2642 kvm_queue_exception(&svm->vcpu, vector);
2643 break;
2644 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2645 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2646 break;
2647 default:
2648 break;
2649 }
2650}
2651
80e31d4f
AK		 2652#ifdef CONFIG_X86_64
2653#define R "r"
2654#else
2655#define R "e"
2656#endif
2657
851ba692 2658static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2659{
a2fa3e9f 2660 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2661 u16 fs_selector;
2662 u16 gs_selector;
2663 u16 ldt_selector;
d9e368d6 2664
cd3ff653
JR		 2665 /*
2666 * A vmexit emulation is required before the vcpu can be executed
2667 * again.
2668 */
2669 if (unlikely(svm->nested.exit_required))
2670 return;
2671
5fdbf976
MT		 2672 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2673 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2674 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2675
e756fc62 2676 pre_svm_run(svm);
6aa8b732 2677
649d6864
JR		 2678 sync_lapic_to_cr8(vcpu);
2679
6aa8b732 2680 save_host_msrs(vcpu);
d6e88aec
AK		 2681 fs_selector = kvm_read_fs();
2682 gs_selector = kvm_read_gs();
2683 ldt_selector = kvm_read_ldt();
cda0ffdd 2684 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2685 /* required for live migration with NPT */
2686 if (npt_enabled)
2687 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2688
04d2cc77
AK		 2689 clgi();
2690
2691 local_irq_enable();
36241b8c 2692
6aa8b732 2693 asm volatile (
80e31d4f
AK		 2694 "push %%"R"bp; \n\t"
2695 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2696 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2697 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2698 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2699 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2700 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2701#ifdef CONFIG_X86_64
fb3f0f51
RR		 2702 "mov %c[r8](%[svm]), %%r8 \n\t"
2703 "mov %c[r9](%[svm]), %%r9 \n\t"
2704 "mov %c[r10](%[svm]), %%r10 \n\t"
2705 "mov %c[r11](%[svm]), %%r11 \n\t"
2706 "mov %c[r12](%[svm]), %%r12 \n\t"
2707 "mov %c[r13](%[svm]), %%r13 \n\t"
2708 "mov %c[r14](%[svm]), %%r14 \n\t"
2709 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2710#endif
2711
6aa8b732 2712 /* Enter guest mode */
80e31d4f
AK		 2713 "push %%"R"ax \n\t"
2714 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2715 __ex(SVM_VMLOAD) "\n\t"
2716 __ex(SVM_VMRUN) "\n\t"
2717 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2718 "pop %%"R"ax \n\t"
6aa8b732
AK		 2719
2720 /* Save guest registers, load host registers */
80e31d4f
AK		 2721 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2722 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2723 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2724 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2725 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2726 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2727#ifdef CONFIG_X86_64
fb3f0f51
RR		 2728 "mov %%r8, %c[r8](%[svm]) \n\t"
2729 "mov %%r9, %c[r9](%[svm]) \n\t"
2730 "mov %%r10, %c[r10](%[svm]) \n\t"
2731 "mov %%r11, %c[r11](%[svm]) \n\t"
2732 "mov %%r12, %c[r12](%[svm]) \n\t"
2733 "mov %%r13, %c[r13](%[svm]) \n\t"
2734 "mov %%r14, %c[r14](%[svm]) \n\t"
2735 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2736#endif
80e31d4f 2737 "pop %%"R"bp"
6aa8b732 2738 :
fb3f0f51 2739 : [svm]"a"(svm),
6aa8b732 2740 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2741 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2742 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2743 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2744 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2745 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2746 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2747#ifdef CONFIG_X86_64
ad312c7c
ZX		 2748 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2749 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2750 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2751 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2752 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2753 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2754 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2755 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2756#endif
54a08c04 2757 : "cc", "memory"
80e31d4f 2758 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2759#ifdef CONFIG_X86_64
54a08c04
LV		 2760 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2761#endif
2762 );
6aa8b732 2763
ad312c7c 2764 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2765 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2766 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2767 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2768
d6e88aec
AK		 2769 kvm_load_fs(fs_selector);
2770 kvm_load_gs(gs_selector);
2771 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2772 load_host_msrs(vcpu);
2773
2774 reload_tss(vcpu);
2775
56ba47dd
AK		 2776 local_irq_disable();
2777
2778 stgi();
2779
d7bf8221
JR		 2780 sync_cr8_to_lapic(vcpu);
2781
a2fa3e9f 2782 svm->next_rip = 0;
9222be18 2783
6de4f3ad
AK		 2784 if (npt_enabled) {
2785 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2786 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2787 }
6aa8b732
AK		 2788}
2789
80e31d4f
AK		 2790#undef R
2791
6aa8b732
AK		 2792static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2793{
a2fa3e9f
GH		 2794 struct vcpu_svm *svm = to_svm(vcpu);
2795
709ddebf
JR		 2796 if (npt_enabled) {
2797 svm->vmcb->control.nested_cr3 = root;
2798 force_new_asid(vcpu);
2799 return;
2800 }
2801
a2fa3e9f 2802 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2803 force_new_asid(vcpu);
2804}
2805
6aa8b732
AK		 2806static int is_disabled(void)
2807{
6031a61c
JR		 2808 u64 vm_cr;
2809
2810 rdmsrl(MSR_VM_CR, vm_cr);
2811 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2812 return 1;
2813
6aa8b732
AK		 2814 return 0;
2815}
2816
102d8325
IM		 2817static void
2818svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2819{
2820 /*
2821 * Patch in the VMMCALL instruction:
2822 */
2823 hypercall[0] = 0x0f;
2824 hypercall[1] = 0x01;
2825 hypercall[2] = 0xd9;
102d8325
IM		 2826}
2827
002c7f7c
YS		 2828static void svm_check_processor_compat(void *rtn)
2829{
2830 *(int *)rtn = 0;
2831}
2832
774ead3a
AK		 2833static bool svm_cpu_has_accelerated_tpr(void)
2834{
2835 return false;
2836}
2837
67253af5
SY		 2838static int get_npt_level(void)
2839{
2840#ifdef CONFIG_X86_64
2841 return PT64_ROOT_LEVEL;
2842#else
2843 return PT32E_ROOT_LEVEL;
2844#endif
2845}
2846
4b12f0de 2847static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2848{
2849 return 0;
2850}
2851
0e851880
SY		 2852static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2853{
2854}
2855
229456fc
MT		 2856static const struct trace_print_flags svm_exit_reasons_str[] = {
2857 { SVM_EXIT_READ_CR0, "read_cr0" },
2858 { SVM_EXIT_READ_CR3, "read_cr3" },
2859 { SVM_EXIT_READ_CR4, "read_cr4" },
2860 { SVM_EXIT_READ_CR8, "read_cr8" },
2861 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2862 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2863 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2864 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2865 { SVM_EXIT_READ_DR0, "read_dr0" },
2866 { SVM_EXIT_READ_DR1, "read_dr1" },
2867 { SVM_EXIT_READ_DR2, "read_dr2" },
2868 { SVM_EXIT_READ_DR3, "read_dr3" },
2869 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2870 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2871 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2872 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2873 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2874 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2875 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2876 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2877 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2878 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2879 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2880 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2881 { SVM_EXIT_INTR, "interrupt" },
2882 { SVM_EXIT_NMI, "nmi" },
2883 { SVM_EXIT_SMI, "smi" },
2884 { SVM_EXIT_INIT, "init" },
2885 { SVM_EXIT_VINTR, "vintr" },
2886 { SVM_EXIT_CPUID, "cpuid" },
2887 { SVM_EXIT_INVD, "invd" },
2888 { SVM_EXIT_HLT, "hlt" },
2889 { SVM_EXIT_INVLPG, "invlpg" },
2890 { SVM_EXIT_INVLPGA, "invlpga" },
2891 { SVM_EXIT_IOIO, "io" },
2892 { SVM_EXIT_MSR, "msr" },
2893 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2894 { SVM_EXIT_SHUTDOWN, "shutdown" },
2895 { SVM_EXIT_VMRUN, "vmrun" },
2896 { SVM_EXIT_VMMCALL, "hypercall" },
2897 { SVM_EXIT_VMLOAD, "vmload" },
2898 { SVM_EXIT_VMSAVE, "vmsave" },
2899 { SVM_EXIT_STGI, "stgi" },
2900 { SVM_EXIT_CLGI, "clgi" },
2901 { SVM_EXIT_SKINIT, "skinit" },
2902 { SVM_EXIT_WBINVD, "wbinvd" },
2903 { SVM_EXIT_MONITOR, "monitor" },
2904 { SVM_EXIT_MWAIT, "mwait" },
2905 { SVM_EXIT_NPF, "npf" },
2906 { -1, NULL }
2907};
2908
17cc3935 2909static int svm_get_lpage_level(void)
344f414f 2910{
17cc3935 2911 return PT_PDPE_LEVEL;
344f414f
JR		 2912}
2913
4e47c7a6
SY		 2914static bool svm_rdtscp_supported(void)
2915{
2916 return false;
2917}
2918
02daab21
AK		 2919static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2920{
2921 struct vcpu_svm *svm = to_svm(vcpu);
2922
d225157b 2923 update_cr0_intercept(svm);
02daab21 2924 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
02daab21
AK		 2925}
2926
cbdd1bea 2927static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2928 .cpu_has_kvm_support = has_svm,
2929 .disabled_by_bios = is_disabled,
2930 .hardware_setup = svm_hardware_setup,
2931 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2932 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2933 .hardware_enable = svm_hardware_enable,
2934 .hardware_disable = svm_hardware_disable,
774ead3a 2935 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2936
2937 .vcpu_create = svm_create_vcpu,
2938 .vcpu_free = svm_free_vcpu,
04d2cc77 2939 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2940
04d2cc77 2941 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2942 .vcpu_load = svm_vcpu_load,
2943 .vcpu_put = svm_vcpu_put,
2944
2945 .set_guest_debug = svm_guest_debug,
2946 .get_msr = svm_get_msr,
2947 .set_msr = svm_set_msr,
2948 .get_segment_base = svm_get_segment_base,
2949 .get_segment = svm_get_segment,
2950 .set_segment = svm_set_segment,
2e4d2653 2951 .get_cpl = svm_get_cpl,
1747fb71 2952 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 2953 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 2954 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2955 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2956 .set_cr3 = svm_set_cr3,
2957 .set_cr4 = svm_set_cr4,
2958 .set_efer = svm_set_efer,
2959 .get_idt = svm_get_idt,
2960 .set_idt = svm_set_idt,
2961 .get_gdt = svm_get_gdt,
2962 .set_gdt = svm_set_gdt,
2963 .get_dr = svm_get_dr,
2964 .set_dr = svm_set_dr,
6de4f3ad 2965 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2966 .get_rflags = svm_get_rflags,
2967 .set_rflags = svm_set_rflags,
02daab21 2968 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 2969
6aa8b732 2970 .tlb_flush = svm_flush_tlb,
6aa8b732 2971
6aa8b732 2972 .run = svm_vcpu_run,
04d2cc77 2973 .handle_exit = handle_exit,
6aa8b732 2974 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2975 .set_interrupt_shadow = svm_set_interrupt_shadow,
2976 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2977 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2978 .set_irq = svm_set_irq,
95ba8273 2979 .set_nmi = svm_inject_nmi,
298101da 2980 .queue_exception = svm_queue_exception,
78646121 2981 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 2982 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 2983 .get_nmi_mask = svm_get_nmi_mask,
2984 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 2985 .enable_nmi_window = enable_nmi_window,
2986 .enable_irq_window = enable_irq_window,
2987 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2988
2989 .set_tss_addr = svm_set_tss_addr,
67253af5 2990 .get_tdp_level = get_npt_level,
4b12f0de 2991 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2992
2993 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 2994 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 2995
2996 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 2997
2998 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 2999};
3000
3001static int __init svm_init(void)
3002{
cb498ea2 3003 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3004 THIS_MODULE);
6aa8b732
AK		 3005}
3006
3007static void __exit svm_exit(void)
3008{
cb498ea2 3009 kvm_exit();
6aa8b732
AK		 3010}
3011
3012module_init(svm_init)
3013module_exit(svm_exit)
Linux kernel - Deliverables
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