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KVM: MMU: s/shadow_pte/spte/
[deliverable/linux.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
6aa8b732 28
e495606d 29#include <asm/desc.h>
6aa8b732 30
63d1142f
EH		 31#include <asm/virtext.h>
32
4ecac3fd
AK		 33#define __ex(x) __kvm_handle_fault_on_reboot(x)
34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
38#define IOPM_ALLOC_ORDER 2
39#define MSRPM_ALLOC_ORDER 1
40
6aa8b732
AK		 41#define SEG_TYPE_LDT 2
42#define SEG_TYPE_BUSY_TSS16 3
43
80b7706e
JR		 44#define SVM_FEATURE_NPT (1 << 0)
45#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 46#define SVM_FEATURE_SVML (1 << 2)
80b7706e 47
24e09cbf
JR		 48#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
49
c0725420
AG		 50/* Turn on to get debugging output*/
51/* #define NESTED_DEBUG */
52
53#ifdef NESTED_DEBUG
54#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
55#else
56#define nsvm_printk(fmt, args...) do {} while(0)
57#endif
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
71struct vcpu_svm {
72 struct kvm_vcpu vcpu;
73 struct vmcb *vmcb;
74 unsigned long vmcb_pa;
75 struct svm_cpu_data *svm_data;
76 uint64_t asid_generation;
77 uint64_t sysenter_esp;
78 uint64_t sysenter_eip;
79
80 u64 next_rip;
81
82 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
83 u64 host_gs_base;
84 unsigned long host_cr2;
85
86 u32 *msrpm;
87 struct vmcb *hsave;
88 u64 hsave_msr;
89
90 u64 nested_vmcb;
91
92 /* These are the merged vectors */
93 u32 *nested_msrpm;
94
95 /* gpa pointers to the real vectors */
96 u64 nested_vmcb_msrpm;
97};
98
709ddebf
JR		 99/* enable NPT for AMD64 and X86 with PAE */
100#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
101static bool npt_enabled = true;
102#else
e3da3acd 103static bool npt_enabled = false;
709ddebf 104#endif
6c7dac72
JR		 105static int npt = 1;
106
107module_param(npt, int, S_IRUGO);
e3da3acd 108
236de055
AG		 109static int nested = 0;
110module_param(nested, int, S_IRUGO);
111
44874f84 112static void svm_flush_tlb(struct kvm_vcpu *vcpu);
04d2cc77 113
cf74a78b
AG		 114static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
115static int nested_svm_vmexit(struct vcpu_svm *svm);
116static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
117 void *arg2, void *opaque);
118static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
119 bool has_error_code, u32 error_code);
120
a2fa3e9f
GH		 121static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
122{
fb3f0f51 123 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 124}
125
3d6368ef
AG		 126static inline bool is_nested(struct vcpu_svm *svm)
127{
128 return svm->nested_vmcb;
129}
130
4866d5e3 131static unsigned long iopm_base;
6aa8b732
AK		 132
133struct kvm_ldttss_desc {
134 u16 limit0;
135 u16 base0;
136 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
137 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
138 u32 base3;
139 u32 zero1;
140} __attribute__((packed));
141
142struct svm_cpu_data {
143 int cpu;
144
5008fdf5
AK		 145 u64 asid_generation;
146 u32 max_asid;
147 u32 next_asid;
6aa8b732
AK		 148 struct kvm_ldttss_desc *tss_desc;
149
150 struct page *save_area;
151};
152
153static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 154static uint32_t svm_features;
6aa8b732
AK		 155
156struct svm_init_data {
157 int cpu;
158 int r;
159};
160
161static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
162
9d8f549d 163#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 164#define MSRS_RANGE_SIZE 2048
165#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
166
167#define MAX_INST_SIZE 15
168
80b7706e
JR		 169static inline u32 svm_has(u32 feat)
170{
171 return svm_features & feat;
172}
173
6aa8b732
AK		 174static inline void clgi(void)
175{
4ecac3fd 176 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 177}
178
179static inline void stgi(void)
180{
4ecac3fd 181 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 182}
183
184static inline void invlpga(unsigned long addr, u32 asid)
185{
4ecac3fd 186 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 187}
188
189static inline unsigned long kvm_read_cr2(void)
190{
191 unsigned long cr2;
192
193 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
194 return cr2;
195}
196
197static inline void kvm_write_cr2(unsigned long val)
198{
199 asm volatile ("mov %0, %%cr2" :: "r" (val));
200}
201
6aa8b732
AK		 202static inline void force_new_asid(struct kvm_vcpu *vcpu)
203{
a2fa3e9f 204 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 205}
206
207static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
208{
209 force_new_asid(vcpu);
210}
211
212static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
213{
709ddebf 214 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 215 efer &= ~EFER_LME;
6aa8b732 216
9962d032 217 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 218 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 219}
220
298101da
AK		 221static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
222 bool has_error_code, u32 error_code)
223{
224 struct vcpu_svm *svm = to_svm(vcpu);
225
cf74a78b
AG		 226 /* If we are within a nested VM we'd better #VMEXIT and let the
227 guest handle the exception */
228 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
229 return;
230
298101da
AK		 231 svm->vmcb->control.event_inj = nr
232 | SVM_EVTINJ_VALID
233 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
234 | SVM_EVTINJ_TYPE_EXEPT;
235 svm->vmcb->control.event_inj_err = error_code;
236}
237
6aa8b732
AK		 238static int is_external_interrupt(u32 info)
239{
240 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
241 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
242}
243
2809f5d2
GC		 244static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
245{
246 struct vcpu_svm *svm = to_svm(vcpu);
247 u32 ret = 0;
248
249 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
250 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
251 return ret & mask;
252}
253
254static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
255{
256 struct vcpu_svm *svm = to_svm(vcpu);
257
258 if (mask == 0)
259 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
260 else
261 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
262
263}
264
6aa8b732
AK		 265static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
266{
a2fa3e9f
GH		 267 struct vcpu_svm *svm = to_svm(vcpu);
268
269 if (!svm->next_rip) {
f629cf84
GN		 270 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
271 EMULATE_DONE)
272 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 273 return;
274 }
5fdbf976
MT		 275 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
276 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
277 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 278
5fdbf976 279 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 280 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 281}
282
283static int has_svm(void)
284{
63d1142f 285 const char *msg;
6aa8b732 286
63d1142f 287 if (!cpu_has_svm(&msg)) {
ff81ff10 288 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 289 return 0;
290 }
291
6aa8b732
AK		 292 return 1;
293}
294
295static void svm_hardware_disable(void *garbage)
296{
2c8dceeb 297 cpu_svm_disable();
6aa8b732
AK		 298}
299
300static void svm_hardware_enable(void *garbage)
301{
302
303 struct svm_cpu_data *svm_data;
304 uint64_t efer;
6aa8b732 305 struct desc_ptr gdt_descr;
6aa8b732
AK		 306 struct desc_struct *gdt;
307 int me = raw_smp_processor_id();
308
309 if (!has_svm()) {
310 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
311 return;
312 }
313 svm_data = per_cpu(svm_data, me);
314
315 if (!svm_data) {
316 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
317 me);
318 return;
319 }
320
321 svm_data->asid_generation = 1;
322 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
323 svm_data->next_asid = svm_data->max_asid + 1;
324
d77c26fc 325 asm volatile ("sgdt %0" : "=m"(gdt_descr));
6aa8b732
AK		 326 gdt = (struct desc_struct *)gdt_descr.address;
327 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
328
329 rdmsrl(MSR_EFER, efer);
9962d032 330 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 331
332 wrmsrl(MSR_VM_HSAVE_PA,
333 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
334}
335
0da1db75
JR		 336static void svm_cpu_uninit(int cpu)
337{
338 struct svm_cpu_data *svm_data
339 = per_cpu(svm_data, raw_smp_processor_id());
340
341 if (!svm_data)
342 return;
343
344 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
345 __free_page(svm_data->save_area);
346 kfree(svm_data);
347}
348
6aa8b732
AK		 349static int svm_cpu_init(int cpu)
350{
351 struct svm_cpu_data *svm_data;
352 int r;
353
354 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
355 if (!svm_data)
356 return -ENOMEM;
357 svm_data->cpu = cpu;
358 svm_data->save_area = alloc_page(GFP_KERNEL);
359 r = -ENOMEM;
360 if (!svm_data->save_area)
361 goto err_1;
362
363 per_cpu(svm_data, cpu) = svm_data;
364
365 return 0;
366
367err_1:
368 kfree(svm_data);
369 return r;
370
371}
372
bfc733a7
RR		 373static void set_msr_interception(u32 *msrpm, unsigned msr,
374 int read, int write)
6aa8b732
AK		 375{
376 int i;
377
378 for (i = 0; i < NUM_MSR_MAPS; i++) {
379 if (msr >= msrpm_ranges[i] &&
380 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
381 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
382 msrpm_ranges[i]) * 2;
383
384 u32 *base = msrpm + (msr_offset / 32);
385 u32 msr_shift = msr_offset % 32;
386 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
387 *base = (*base & ~(0x3 << msr_shift)) |
388 (mask << msr_shift);
bfc733a7 389 return;
6aa8b732
AK		 390 }
391 }
bfc733a7 392 BUG();
6aa8b732
AK		 393}
394
f65c229c
JR		 395static void svm_vcpu_init_msrpm(u32 *msrpm)
396{
397 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
398
399#ifdef CONFIG_X86_64
400 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
401 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
402 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
403 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
404 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
405 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
406#endif
407 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
408 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 409}
410
24e09cbf
JR		 411static void svm_enable_lbrv(struct vcpu_svm *svm)
412{
413 u32 *msrpm = svm->msrpm;
414
415 svm->vmcb->control.lbr_ctl = 1;
416 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
417 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
418 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
419 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
420}
421
422static void svm_disable_lbrv(struct vcpu_svm *svm)
423{
424 u32 *msrpm = svm->msrpm;
425
426 svm->vmcb->control.lbr_ctl = 0;
427 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
428 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
429 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
430 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
431}
432
6aa8b732
AK		 433static __init int svm_hardware_setup(void)
434{
435 int cpu;
436 struct page *iopm_pages;
f65c229c 437 void *iopm_va;
6aa8b732
AK		 438 int r;
439
6aa8b732
AK		 440 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
441
442 if (!iopm_pages)
443 return -ENOMEM;
c8681339
AL		 444
445 iopm_va = page_address(iopm_pages);
446 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 447 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
448
50a37eb4
JR		 449 if (boot_cpu_has(X86_FEATURE_NX))
450 kvm_enable_efer_bits(EFER_NX);
451
1b2fd70c
AG		 452 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
453 kvm_enable_efer_bits(EFER_FFXSR);
454
236de055
AG		 455 if (nested) {
456 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
457 kvm_enable_efer_bits(EFER_SVME);
458 }
459
6aa8b732
AK		 460 for_each_online_cpu(cpu) {
461 r = svm_cpu_init(cpu);
462 if (r)
f65c229c 463 goto err;
6aa8b732 464 }
33bd6a0b
JR		 465
466 svm_features = cpuid_edx(SVM_CPUID_FUNC);
467
e3da3acd
JR		 468 if (!svm_has(SVM_FEATURE_NPT))
469 npt_enabled = false;
470
6c7dac72
JR		 471 if (npt_enabled && !npt) {
472 printk(KERN_INFO "kvm: Nested Paging disabled\n");
473 npt_enabled = false;
474 }
475
18552672 476 if (npt_enabled) {
e3da3acd 477 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 478 kvm_enable_tdp();
5f4cb662
JR		 479 } else
480 kvm_disable_tdp();
e3da3acd 481
6aa8b732
AK		 482 return 0;
483
f65c229c 484err:
6aa8b732
AK		 485 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
486 iopm_base = 0;
487 return r;
488}
489
490static __exit void svm_hardware_unsetup(void)
491{
0da1db75
JR		 492 int cpu;
493
494 for_each_online_cpu(cpu)
495 svm_cpu_uninit(cpu);
496
6aa8b732 497 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 498 iopm_base = 0;
6aa8b732
AK		 499}
500
501static void init_seg(struct vmcb_seg *seg)
502{
503 seg->selector = 0;
504 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
505 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
506 seg->limit = 0xffff;
507 seg->base = 0;
508}
509
510static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
511{
512 seg->selector = 0;
513 seg->attrib = SVM_SELECTOR_P_MASK | type;
514 seg->limit = 0xffff;
515 seg->base = 0;
516}
517
e6101a96 518static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 519{
e6101a96
JR		 520 struct vmcb_control_area *control = &svm->vmcb->control;
521 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 522
523 control->intercept_cr_read = INTERCEPT_CR0_MASK |
524 INTERCEPT_CR3_MASK |
649d6864 525 INTERCEPT_CR4_MASK;
6aa8b732
AK		 526
527 control->intercept_cr_write = INTERCEPT_CR0_MASK |
528 INTERCEPT_CR3_MASK |
80a8119c
AK		 529 INTERCEPT_CR4_MASK |
530 INTERCEPT_CR8_MASK;
6aa8b732
AK		 531
532 control->intercept_dr_read = INTERCEPT_DR0_MASK |
533 INTERCEPT_DR1_MASK |
534 INTERCEPT_DR2_MASK |
535 INTERCEPT_DR3_MASK;
536
537 control->intercept_dr_write = INTERCEPT_DR0_MASK |
538 INTERCEPT_DR1_MASK |
539 INTERCEPT_DR2_MASK |
540 INTERCEPT_DR3_MASK |
541 INTERCEPT_DR5_MASK |
542 INTERCEPT_DR7_MASK;
543
7aa81cc0 544 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 545 (1 << UD_VECTOR) |
546 (1 << MC_VECTOR);
6aa8b732
AK		 547
548
549 control->intercept = (1ULL << INTERCEPT_INTR) |
550 (1ULL << INTERCEPT_NMI) |
0152527b 551 (1ULL << INTERCEPT_SMI) |
6aa8b732 552 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 553 (1ULL << INTERCEPT_INVD) |
6aa8b732 554 (1ULL << INTERCEPT_HLT) |
a7052897 555 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 556 (1ULL << INTERCEPT_INVLPGA) |
557 (1ULL << INTERCEPT_IOIO_PROT) |
558 (1ULL << INTERCEPT_MSR_PROT) |
559 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 560 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 561 (1ULL << INTERCEPT_VMRUN) |
562 (1ULL << INTERCEPT_VMMCALL) |
563 (1ULL << INTERCEPT_VMLOAD) |
564 (1ULL << INTERCEPT_VMSAVE) |
565 (1ULL << INTERCEPT_STGI) |
566 (1ULL << INTERCEPT_CLGI) |
916ce236 567 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 568 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 569 (1ULL << INTERCEPT_MONITOR) |
570 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 571
572 control->iopm_base_pa = iopm_base;
f65c229c 573 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 574 control->tsc_offset = 0;
6aa8b732
AK		 575 control->int_ctl = V_INTR_MASKING_MASK;
576
577 init_seg(&save->es);
578 init_seg(&save->ss);
579 init_seg(&save->ds);
580 init_seg(&save->fs);
581 init_seg(&save->gs);
582
583 save->cs.selector = 0xf000;
584 /* Executable/Readable Code Segment */
585 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
586 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
587 save->cs.limit = 0xffff;
d92899a0
AK		 588 /*
589 * cs.base should really be 0xffff0000, but vmx can't handle that, so
590 * be consistent with it.
591 *
592 * Replace when we have real mode working for vmx.
593 */
594 save->cs.base = 0xf0000;
6aa8b732
AK		 595
596 save->gdtr.limit = 0xffff;
597 save->idtr.limit = 0xffff;
598
599 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
600 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
601
9962d032 602 save->efer = EFER_SVME;
d77c26fc 603 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 604 save->dr7 = 0x400;
605 save->rflags = 2;
606 save->rip = 0x0000fff0;
5fdbf976 607 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 608
609 /*
610 * cr0 val on cpu init should be 0x60000010, we enable cpu
611 * cache by default. the orderly way is to enable cache in bios.
612 */
707d92fa 613 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 614 save->cr4 = X86_CR4_PAE;
6aa8b732 615 /* rdx = ?? */
709ddebf
JR		 616
617 if (npt_enabled) {
618 /* Setup VMCB for Nested Paging */
619 control->nested_ctl = 1;
a7052897
MT		 620 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
621 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 622 control->intercept_exceptions &= ~(1 << PF_VECTOR);
623 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
624 INTERCEPT_CR3_MASK);
625 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
626 INTERCEPT_CR3_MASK);
627 save->g_pat = 0x0007040600070406ULL;
628 /* enable caching because the QEMU Bios doesn't enable it */
629 save->cr0 = X86_CR0_ET;
630 save->cr3 = 0;
631 save->cr4 = 0;
632 }
a79d2f18 633 force_new_asid(&svm->vcpu);
1371d904 634
3d6368ef 635 svm->nested_vmcb = 0;
1371d904 636 svm->vcpu.arch.hflags = HF_GIF_MASK;
6aa8b732
AK		 637}
638
e00c8cf2 639static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 640{
641 struct vcpu_svm *svm = to_svm(vcpu);
642
e6101a96 643 init_vmcb(svm);
70433389
AK		 644
645 if (vcpu->vcpu_id != 0) {
5fdbf976 646 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 647 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
648 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 649 }
5fdbf976
MT		 650 vcpu->arch.regs_avail = ~0;
651 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 652
653 return 0;
04d2cc77
AK		 654}
655
fb3f0f51 656static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 657{
a2fa3e9f 658 struct vcpu_svm *svm;
6aa8b732 659 struct page *page;
f65c229c 660 struct page *msrpm_pages;
b286d5d8 661 struct page *hsave_page;
3d6368ef 662 struct page *nested_msrpm_pages;
fb3f0f51 663 int err;
6aa8b732 664
c16f862d 665 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 666 if (!svm) {
667 err = -ENOMEM;
668 goto out;
669 }
670
671 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
672 if (err)
673 goto free_svm;
674
6aa8b732 675 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 676 if (!page) {
677 err = -ENOMEM;
678 goto uninit;
679 }
6aa8b732 680
f65c229c
JR		 681 err = -ENOMEM;
682 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
683 if (!msrpm_pages)
684 goto uninit;
3d6368ef
AG		 685
686 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
687 if (!nested_msrpm_pages)
688 goto uninit;
689
f65c229c
JR		 690 svm->msrpm = page_address(msrpm_pages);
691 svm_vcpu_init_msrpm(svm->msrpm);
692
b286d5d8
AG		 693 hsave_page = alloc_page(GFP_KERNEL);
694 if (!hsave_page)
695 goto uninit;
696 svm->hsave = page_address(hsave_page);
697
3d6368ef
AG		 698 svm->nested_msrpm = page_address(nested_msrpm_pages);
699
a2fa3e9f
GH		 700 svm->vmcb = page_address(page);
701 clear_page(svm->vmcb);
702 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
703 svm->asid_generation = 0;
e6101a96 704 init_vmcb(svm);
a2fa3e9f 705
fb3f0f51
RR		 706 fx_init(&svm->vcpu);
707 svm->vcpu.fpu_active = 1;
ad312c7c 708 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
fb3f0f51 709 if (svm->vcpu.vcpu_id == 0)
ad312c7c 710 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 711
fb3f0f51 712 return &svm->vcpu;
36241b8c 713
fb3f0f51
RR		 714uninit:
715 kvm_vcpu_uninit(&svm->vcpu);
716free_svm:
a4770347 717 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 718out:
719 return ERR_PTR(err);
6aa8b732
AK		 720}
721
722static void svm_free_vcpu(struct kvm_vcpu *vcpu)
723{
a2fa3e9f
GH		 724 struct vcpu_svm *svm = to_svm(vcpu);
725
fb3f0f51 726 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 727 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
b286d5d8 728 __free_page(virt_to_page(svm->hsave));
3d6368ef 729 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 730 kvm_vcpu_uninit(vcpu);
a4770347 731 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 732}
733
15ad7146 734static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 735{
a2fa3e9f 736 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 737 int i;
0cc5064d 738
0cc5064d
AK		 739 if (unlikely(cpu != vcpu->cpu)) {
740 u64 tsc_this, delta;
741
742 /*
743 * Make sure that the guest sees a monotonically
744 * increasing TSC.
745 */
746 rdtscll(tsc_this);
ad312c7c 747 delta = vcpu->arch.host_tsc - tsc_this;
a2fa3e9f 748 svm->vmcb->control.tsc_offset += delta;
0cc5064d 749 vcpu->cpu = cpu;
2f599714 750 kvm_migrate_timers(vcpu);
4b656b12 751 svm->asid_generation = 0;
0cc5064d 752 }
94dfbdb3
AL		 753
754 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 755 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 756}
757
758static void svm_vcpu_put(struct kvm_vcpu *vcpu)
759{
a2fa3e9f 760 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 761 int i;
762
e1beb1d3 763 ++vcpu->stat.host_state_reload;
94dfbdb3 764 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 765 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 766
ad312c7c 767 rdtscll(vcpu->arch.host_tsc);
6aa8b732
AK		 768}
769
6aa8b732
AK		 770static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
771{
a2fa3e9f 772 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 773}
774
775static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
776{
a2fa3e9f 777 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 778}
779
6de4f3ad
AK		 780static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
781{
782 switch (reg) {
783 case VCPU_EXREG_PDPTR:
784 BUG_ON(!npt_enabled);
785 load_pdptrs(vcpu, vcpu->arch.cr3);
786 break;
787 default:
788 BUG();
789 }
790}
791
f0b85051
AG		 792static void svm_set_vintr(struct vcpu_svm *svm)
793{
794 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
795}
796
797static void svm_clear_vintr(struct vcpu_svm *svm)
798{
799 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
800}
801
6aa8b732
AK		 802static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
803{
a2fa3e9f 804 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 805
806 switch (seg) {
807 case VCPU_SREG_CS: return &save->cs;
808 case VCPU_SREG_DS: return &save->ds;
809 case VCPU_SREG_ES: return &save->es;
810 case VCPU_SREG_FS: return &save->fs;
811 case VCPU_SREG_GS: return &save->gs;
812 case VCPU_SREG_SS: return &save->ss;
813 case VCPU_SREG_TR: return &save->tr;
814 case VCPU_SREG_LDTR: return &save->ldtr;
815 }
816 BUG();
8b6d44c7 817 return NULL;
6aa8b732
AK		 818}
819
820static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
821{
822 struct vmcb_seg *s = svm_seg(vcpu, seg);
823
824 return s->base;
825}
826
827static void svm_get_segment(struct kvm_vcpu *vcpu,
828 struct kvm_segment *var, int seg)
829{
830 struct vmcb_seg *s = svm_seg(vcpu, seg);
831
832 var->base = s->base;
833 var->limit = s->limit;
834 var->selector = s->selector;
835 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
836 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
837 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
838 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
839 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
840 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
841 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
842 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 843
19bca6ab
AP		 844 /* AMD's VMCB does not have an explicit unusable field, so emulate it
845 * for cross vendor migration purposes by "not present"
846 */
847 var->unusable = !var->present || (var->type == 0);
848
1fbdc7a5
AP		 849 switch (seg) {
850 case VCPU_SREG_CS:
851 /*
852 * SVM always stores 0 for the 'G' bit in the CS selector in
853 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
854 * Intel's VMENTRY has a check on the 'G' bit.
855 */
25022acc 856 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 857 break;
858 case VCPU_SREG_TR:
859 /*
860 * Work around a bug where the busy flag in the tr selector
861 * isn't exposed
862 */
c0d09828 863 var->type |= 0x2;
1fbdc7a5
AP		 864 break;
865 case VCPU_SREG_DS:
866 case VCPU_SREG_ES:
867 case VCPU_SREG_FS:
868 case VCPU_SREG_GS:
869 /*
870 * The accessed bit must always be set in the segment
871 * descriptor cache, although it can be cleared in the
872 * descriptor, the cached bit always remains at 1. Since
873 * Intel has a check on this, set it here to support
874 * cross-vendor migration.
875 */
876 if (!var->unusable)
877 var->type |= 0x1;
878 break;
b586eb02
AP		 879 case VCPU_SREG_SS:
880 /* On AMD CPUs sometimes the DB bit in the segment
881 * descriptor is left as 1, although the whole segment has
882 * been made unusable. Clear it here to pass an Intel VMX
883 * entry check when cross vendor migrating.
884 */
885 if (var->unusable)
886 var->db = 0;
887 break;
1fbdc7a5 888 }
6aa8b732
AK		 889}
890
2e4d2653
IE		 891static int svm_get_cpl(struct kvm_vcpu *vcpu)
892{
893 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
894
895 return save->cpl;
896}
897
6aa8b732
AK		 898static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
899{
a2fa3e9f
GH		 900 struct vcpu_svm *svm = to_svm(vcpu);
901
902 dt->limit = svm->vmcb->save.idtr.limit;
903 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 904}
905
906static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
907{
a2fa3e9f
GH		 908 struct vcpu_svm *svm = to_svm(vcpu);
909
910 svm->vmcb->save.idtr.limit = dt->limit;
911 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 912}
913
914static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
915{
a2fa3e9f
GH		 916 struct vcpu_svm *svm = to_svm(vcpu);
917
918 dt->limit = svm->vmcb->save.gdtr.limit;
919 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 920}
921
922static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
923{
a2fa3e9f
GH		 924 struct vcpu_svm *svm = to_svm(vcpu);
925
926 svm->vmcb->save.gdtr.limit = dt->limit;
927 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 928}
929
25c4c276 930static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 931{
932}
933
6aa8b732
AK		 934static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
935{
a2fa3e9f
GH		 936 struct vcpu_svm *svm = to_svm(vcpu);
937
05b3e0c2 938#ifdef CONFIG_X86_64
ad312c7c 939 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 940 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 941 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 942 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 943 }
944
d77c26fc 945 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 946 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 947 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 948 }
949 }
950#endif
709ddebf
JR		 951 if (npt_enabled)
952 goto set;
953
ad312c7c 954 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 955 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 956 vcpu->fpu_active = 1;
957 }
958
ad312c7c 959 vcpu->arch.cr0 = cr0;
707d92fa 960 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 961 if (!vcpu->fpu_active) {
962 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 963 cr0 |= X86_CR0_TS;
6b390b63 964 }
709ddebf
JR		 965set:
966 /*
967 * re-enable caching here because the QEMU bios
968 * does not do it - this results in some delay at
969 * reboot
970 */
971 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 972 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 973}
974
975static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
976{
6394b649 977 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 978 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
979
980 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
981 force_new_asid(vcpu);
6394b649 982
ec077263
JR		 983 vcpu->arch.cr4 = cr4;
984 if (!npt_enabled)
985 cr4 |= X86_CR4_PAE;
6394b649 986 cr4 |= host_cr4_mce;
ec077263 987 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 988}
989
990static void svm_set_segment(struct kvm_vcpu *vcpu,
991 struct kvm_segment *var, int seg)
992{
a2fa3e9f 993 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 994 struct vmcb_seg *s = svm_seg(vcpu, seg);
995
996 s->base = var->base;
997 s->limit = var->limit;
998 s->selector = var->selector;
999 if (var->unusable)
1000 s->attrib = 0;
1001 else {
1002 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1003 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1004 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1005 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1006 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1007 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1008 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1009 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1010 }
1011 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1012 svm->vmcb->save.cpl
1013 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1014 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1015
1016}
1017
44c11430 1018static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1019{
d0bfb940
JK		 1020 struct vcpu_svm *svm = to_svm(vcpu);
1021
d0bfb940
JK		 1022 svm->vmcb->control.intercept_exceptions &=
1023 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1024
1025 if (vcpu->arch.singlestep)
1026 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1027
d0bfb940
JK		 1028 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1029 if (vcpu->guest_debug &
1030 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1031 svm->vmcb->control.intercept_exceptions |=
1032 1 << DB_VECTOR;
1033 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1034 svm->vmcb->control.intercept_exceptions |=
1035 1 << BP_VECTOR;
1036 } else
1037 vcpu->guest_debug = 0;
44c11430
GN		 1038}
1039
1040static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1041{
1042 int old_debug = vcpu->guest_debug;
1043 struct vcpu_svm *svm = to_svm(vcpu);
1044
1045 vcpu->guest_debug = dbg->control;
1046
1047 update_db_intercept(vcpu);
d0bfb940 1048
ae675ef0
JK		 1049 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1050 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1051 else
1052 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1053
d0bfb940
JK		 1054 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1055 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1056 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1057 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1058
1059 return 0;
6aa8b732
AK		 1060}
1061
1062static void load_host_msrs(struct kvm_vcpu *vcpu)
1063{
94dfbdb3 1064#ifdef CONFIG_X86_64
a2fa3e9f 1065 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1066#endif
6aa8b732
AK		 1067}
1068
1069static void save_host_msrs(struct kvm_vcpu *vcpu)
1070{
94dfbdb3 1071#ifdef CONFIG_X86_64
a2fa3e9f 1072 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1073#endif
6aa8b732
AK		 1074}
1075
e756fc62 1076static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1077{
1078 if (svm_data->next_asid > svm_data->max_asid) {
1079 ++svm_data->asid_generation;
1080 svm_data->next_asid = 1;
a2fa3e9f 1081 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1082 }
1083
a2fa3e9f
GH		 1084 svm->asid_generation = svm_data->asid_generation;
1085 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1086}
1087
6aa8b732
AK		 1088static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1089{
42dbaa5a
JK		 1090 struct vcpu_svm *svm = to_svm(vcpu);
1091 unsigned long val;
1092
1093 switch (dr) {
1094 case 0 ... 3:
1095 val = vcpu->arch.db[dr];
1096 break;
1097 case 6:
1098 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1099 val = vcpu->arch.dr6;
1100 else
1101 val = svm->vmcb->save.dr6;
1102 break;
1103 case 7:
1104 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1105 val = vcpu->arch.dr7;
1106 else
1107 val = svm->vmcb->save.dr7;
1108 break;
1109 default:
1110 val = 0;
1111 }
1112
af9ca2d7
JR		 1113 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1114 return val;
6aa8b732
AK		 1115}
1116
1117static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1118 int *exception)
1119{
a2fa3e9f
GH		 1120 struct vcpu_svm *svm = to_svm(vcpu);
1121
42dbaa5a 1122 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
6aa8b732 1123
42dbaa5a 1124 *exception = 0;
6aa8b732
AK		 1125
1126 switch (dr) {
1127 case 0 ... 3:
42dbaa5a
JK		 1128 vcpu->arch.db[dr] = value;
1129 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1130 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1131 return;
1132 case 4 ... 5:
42dbaa5a 1133 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1134 *exception = UD_VECTOR;
42dbaa5a
JK		 1135 return;
1136 case 6:
1137 if (value & 0xffffffff00000000ULL) {
1138 *exception = GP_VECTOR;
6aa8b732
AK		 1139 return;
1140 }
42dbaa5a
JK		 1141 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1142 return;
1143 case 7:
1144 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1145 *exception = GP_VECTOR;
1146 return;
1147 }
42dbaa5a
JK		 1148 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1149 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1150 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1151 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1152 }
6aa8b732 1153 return;
6aa8b732 1154 default:
42dbaa5a 1155 /* FIXME: Possible case? */
6aa8b732 1156 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1157 __func__, dr);
6aa8b732
AK		 1158 *exception = UD_VECTOR;
1159 return;
1160 }
1161}
1162
e756fc62 1163static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1164{
6aa8b732
AK		 1165 u64 fault_address;
1166 u32 error_code;
6aa8b732 1167
a2fa3e9f
GH		 1168 fault_address = svm->vmcb->control.exit_info_2;
1169 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7
JR		 1170
1171 if (!npt_enabled)
1172 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1173 (u32)fault_address, (u32)(fault_address >> 32),
1174 handler);
d2ebb410
JR		 1175 else
1176 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1177 (u32)fault_address, (u32)(fault_address >> 32),
1178 handler);
44874f84
JR		 1179 /*
1180 * FIXME: Tis shouldn't be necessary here, but there is a flush
1181 * missing in the MMU code. Until we find this bug, flush the
1182 * complete TLB here on an NPF
1183 */
1184 if (npt_enabled)
1185 svm_flush_tlb(&svm->vcpu);
9222be18 1186 else {
3298b75c 1187 if (kvm_event_needs_reinjection(&svm->vcpu))
9222be18
GN		 1188 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1189 }
3067714c 1190 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1191}
1192
d0bfb940
JK		 1193static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1194{
1195 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1196 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1197 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1198 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1199 return 1;
1200 }
44c11430
GN		 1201
1202 if (svm->vcpu.arch.singlestep) {
1203 svm->vcpu.arch.singlestep = false;
1204 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1205 svm->vmcb->save.rflags &=
1206 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1207 update_db_intercept(&svm->vcpu);
1208 }
1209
1210 if (svm->vcpu.guest_debug &
1211 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1212 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1213 kvm_run->debug.arch.pc =
1214 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1215 kvm_run->debug.arch.exception = DB_VECTOR;
1216 return 0;
1217 }
1218
1219 return 1;
d0bfb940
JK		 1220}
1221
1222static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1223{
1224 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1225 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1226 kvm_run->debug.arch.exception = BP_VECTOR;
1227 return 0;
1228}
1229
7aa81cc0
AL		 1230static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1231{
1232 int er;
1233
571008da 1234 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1235 if (er != EMULATE_DONE)
7ee5d940 1236 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1237 return 1;
1238}
1239
e756fc62 1240static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
7807fa6c 1241{
a2fa3e9f 1242 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1243 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1244 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1245 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1246
1247 return 1;
7807fa6c
AL		 1248}
1249
53371b50
JR		 1250static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1251{
1252 /*
1253 * On an #MC intercept the MCE handler is not called automatically in
1254 * the host. So do it by hand here.
1255 */
1256 asm volatile (
1257 "int $0x12\n");
1258 /* not sure if we ever come back to this point */
1259
1260 return 1;
1261}
1262
e756fc62 1263static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
46fe4ddd
JR		 1264{
1265 /*
1266 * VMCB is undefined after a SHUTDOWN intercept
1267 * so reinitialize it.
1268 */
a2fa3e9f 1269 clear_page(svm->vmcb);
e6101a96 1270 init_vmcb(svm);
46fe4ddd
JR		 1271
1272 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1273 return 0;
1274}
1275
e756fc62 1276static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1277{
d77c26fc 1278 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1279 int size, in, string;
039576c0 1280 unsigned port;
6aa8b732 1281
e756fc62 1282 ++svm->vcpu.stat.io_exits;
6aa8b732 1283
a2fa3e9f 1284 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1285
e70669ab
LV		 1286 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1287
1288 if (string) {
3427318f
LV		 1289 if (emulate_instruction(&svm->vcpu,
1290 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1291 return 0;
1292 return 1;
1293 }
1294
039576c0
AK		 1295 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1296 port = io_info >> 16;
1297 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1298
e93f36bc 1299 skip_emulated_instruction(&svm->vcpu);
3090dd73 1300 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1301}
1302
c47f098d
JR		 1303static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1304{
af9ca2d7 1305 KVMTRACE_0D(NMI, &svm->vcpu, handler);
c47f098d
JR		 1306 return 1;
1307}
1308
a0698055
JR		 1309static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1310{
1311 ++svm->vcpu.stat.irq_exits;
af9ca2d7 1312 KVMTRACE_0D(INTR, &svm->vcpu, handler);
a0698055
JR		 1313 return 1;
1314}
1315
e756fc62 1316static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732
AK		 1317{
1318 return 1;
1319}
1320
e756fc62 1321static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1322{
5fdbf976 1323 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1324 skip_emulated_instruction(&svm->vcpu);
1325 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1326}
1327
e756fc62 1328static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
02e235bc 1329{
5fdbf976 1330 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1331 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1332 kvm_emulate_hypercall(&svm->vcpu);
1333 return 1;
02e235bc
AK		 1334}
1335
c0725420
AG		 1336static int nested_svm_check_permissions(struct vcpu_svm *svm)
1337{
1338 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1339 || !is_paging(&svm->vcpu)) {
1340 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1341 return 1;
1342 }
1343
1344 if (svm->vmcb->save.cpl) {
1345 kvm_inject_gp(&svm->vcpu, 0);
1346 return 1;
1347 }
1348
1349 return 0;
1350}
1351
cf74a78b
AG		 1352static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1353 bool has_error_code, u32 error_code)
1354{
1355 if (is_nested(svm)) {
1356 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1357 svm->vmcb->control.exit_code_hi = 0;
1358 svm->vmcb->control.exit_info_1 = error_code;
1359 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1360 if (nested_svm_exit_handled(svm, false)) {
1361 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1362
1363 nested_svm_vmexit(svm);
1364 return 1;
1365 }
1366 }
1367
1368 return 0;
1369}
1370
1371static inline int nested_svm_intr(struct vcpu_svm *svm)
1372{
1373 if (is_nested(svm)) {
1374 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1375 return 0;
1376
1377 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1378 return 0;
1379
1380 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1381
1382 if (nested_svm_exit_handled(svm, false)) {
1383 nsvm_printk("VMexit -> INTR\n");
1384 nested_svm_vmexit(svm);
1385 return 1;
1386 }
1387 }
1388
1389 return 0;
1390}
1391
c0725420
AG		 1392static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1393{
1394 struct page *page;
1395
1396 down_read(&current->mm->mmap_sem);
1397 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1398 up_read(&current->mm->mmap_sem);
1399
1400 if (is_error_page(page)) {
1401 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1402 __func__, gpa);
1403 kvm_release_page_clean(page);
1404 kvm_inject_gp(&svm->vcpu, 0);
1405 return NULL;
1406 }
1407 return page;
1408}
1409
1410static int nested_svm_do(struct vcpu_svm *svm,
1411 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1412 int (*handler)(struct vcpu_svm *svm,
1413 void *arg1,
1414 void *arg2,
1415 void *opaque))
1416{
1417 struct page *arg1_page;
1418 struct page *arg2_page = NULL;
1419 void *arg1;
1420 void *arg2 = NULL;
1421 int retval;
1422
1423 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1424 if(arg1_page == NULL)
1425 return 1;
1426
1427 if (arg2_gpa) {
1428 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1429 if(arg2_page == NULL) {
1430 kvm_release_page_clean(arg1_page);
1431 return 1;
1432 }
1433 }
1434
1435 arg1 = kmap_atomic(arg1_page, KM_USER0);
1436 if (arg2_gpa)
1437 arg2 = kmap_atomic(arg2_page, KM_USER1);
1438
1439 retval = handler(svm, arg1, arg2, opaque);
1440
1441 kunmap_atomic(arg1, KM_USER0);
1442 if (arg2_gpa)
1443 kunmap_atomic(arg2, KM_USER1);
1444
1445 kvm_release_page_dirty(arg1_page);
1446 if (arg2_gpa)
1447 kvm_release_page_dirty(arg2_page);
1448
1449 return retval;
1450}
1451
cf74a78b
AG		 1452static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1453 void *arg1,
1454 void *arg2,
1455 void *opaque)
1456{
1457 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1458 bool kvm_overrides = *(bool *)opaque;
1459 u32 exit_code = svm->vmcb->control.exit_code;
1460
1461 if (kvm_overrides) {
1462 switch (exit_code) {
1463 case SVM_EXIT_INTR:
1464 case SVM_EXIT_NMI:
1465 return 0;
1466 /* For now we are always handling NPFs when using them */
1467 case SVM_EXIT_NPF:
1468 if (npt_enabled)
1469 return 0;
1470 break;
1471 /* When we're shadowing, trap PFs */
1472 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1473 if (!npt_enabled)
1474 return 0;
1475 break;
1476 default:
1477 break;
1478 }
1479 }
1480
1481 switch (exit_code) {
1482 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1483 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1484 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1485 return 1;
1486 break;
1487 }
1488 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1489 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1490 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1491 return 1;
1492 break;
1493 }
1494 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1495 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1496 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1497 return 1;
1498 break;
1499 }
1500 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1501 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1502 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1503 return 1;
1504 break;
1505 }
1506 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1507 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1508 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1509 return 1;
1510 break;
1511 }
1512 default: {
1513 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1514 nsvm_printk("exit code: 0x%x\n", exit_code);
1515 if (nested_vmcb->control.intercept & exit_bits)
1516 return 1;
1517 }
1518 }
1519
1520 return 0;
1521}
1522
1523static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1524 void *arg1, void *arg2,
1525 void *opaque)
1526{
1527 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1528 u8 *msrpm = (u8 *)arg2;
1529 u32 t0, t1;
1530 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1531 u32 param = svm->vmcb->control.exit_info_1 & 1;
1532
1533 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1534 return 0;
1535
1536 switch(msr) {
1537 case 0 ... 0x1fff:
1538 t0 = (msr * 2) % 8;
1539 t1 = msr / 8;
1540 break;
1541 case 0xc0000000 ... 0xc0001fff:
1542 t0 = (8192 + msr - 0xc0000000) * 2;
1543 t1 = (t0 / 8);
1544 t0 %= 8;
1545 break;
1546 case 0xc0010000 ... 0xc0011fff:
1547 t0 = (16384 + msr - 0xc0010000) * 2;
1548 t1 = (t0 / 8);
1549 t0 %= 8;
1550 break;
1551 default:
1552 return 1;
1553 break;
1554 }
1555 if (msrpm[t1] & ((1 << param) << t0))
1556 return 1;
1557
1558 return 0;
1559}
1560
1561static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1562{
1563 bool k = kvm_override;
1564
1565 switch (svm->vmcb->control.exit_code) {
1566 case SVM_EXIT_MSR:
1567 return nested_svm_do(svm, svm->nested_vmcb,
1568 svm->nested_vmcb_msrpm, NULL,
1569 nested_svm_exit_handled_msr);
1570 default: break;
1571 }
1572
1573 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1574 nested_svm_exit_handled_real);
1575}
1576
1577static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1578 void *arg2, void *opaque)
1579{
1580 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1581 struct vmcb *hsave = svm->hsave;
1582 u64 nested_save[] = { nested_vmcb->save.cr0,
1583 nested_vmcb->save.cr3,
1584 nested_vmcb->save.cr4,
1585 nested_vmcb->save.efer,
1586 nested_vmcb->control.intercept_cr_read,
1587 nested_vmcb->control.intercept_cr_write,
1588 nested_vmcb->control.intercept_dr_read,
1589 nested_vmcb->control.intercept_dr_write,
1590 nested_vmcb->control.intercept_exceptions,
1591 nested_vmcb->control.intercept,
1592 nested_vmcb->control.msrpm_base_pa,
1593 nested_vmcb->control.iopm_base_pa,
1594 nested_vmcb->control.tsc_offset };
1595
1596 /* Give the current vmcb to the guest */
1597 memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1598 nested_vmcb->save.cr0 = nested_save[0];
1599 if (!npt_enabled)
1600 nested_vmcb->save.cr3 = nested_save[1];
1601 nested_vmcb->save.cr4 = nested_save[2];
1602 nested_vmcb->save.efer = nested_save[3];
1603 nested_vmcb->control.intercept_cr_read = nested_save[4];
1604 nested_vmcb->control.intercept_cr_write = nested_save[5];
1605 nested_vmcb->control.intercept_dr_read = nested_save[6];
1606 nested_vmcb->control.intercept_dr_write = nested_save[7];
1607 nested_vmcb->control.intercept_exceptions = nested_save[8];
1608 nested_vmcb->control.intercept = nested_save[9];
1609 nested_vmcb->control.msrpm_base_pa = nested_save[10];
1610 nested_vmcb->control.iopm_base_pa = nested_save[11];
1611 nested_vmcb->control.tsc_offset = nested_save[12];
1612
1613 /* We always set V_INTR_MASKING and remember the old value in hflags */
1614 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1615 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1616
1617 if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1618 (nested_vmcb->control.int_vector)) {
1619 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1620 nested_vmcb->control.int_vector);
1621 }
1622
1623 /* Restore the original control entries */
1624 svm->vmcb->control = hsave->control;
1625
1626 /* Kill any pending exceptions */
1627 if (svm->vcpu.arch.exception.pending == true)
1628 nsvm_printk("WARNING: Pending Exception\n");
1629 svm->vcpu.arch.exception.pending = false;
1630
1631 /* Restore selected save entries */
1632 svm->vmcb->save.es = hsave->save.es;
1633 svm->vmcb->save.cs = hsave->save.cs;
1634 svm->vmcb->save.ss = hsave->save.ss;
1635 svm->vmcb->save.ds = hsave->save.ds;
1636 svm->vmcb->save.gdtr = hsave->save.gdtr;
1637 svm->vmcb->save.idtr = hsave->save.idtr;
1638 svm->vmcb->save.rflags = hsave->save.rflags;
1639 svm_set_efer(&svm->vcpu, hsave->save.efer);
1640 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1641 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1642 if (npt_enabled) {
1643 svm->vmcb->save.cr3 = hsave->save.cr3;
1644 svm->vcpu.arch.cr3 = hsave->save.cr3;
1645 } else {
1646 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1647 }
1648 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1649 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1650 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1651 svm->vmcb->save.dr7 = 0;
1652 svm->vmcb->save.cpl = 0;
1653 svm->vmcb->control.exit_int_info = 0;
1654
1655 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1656 /* Exit nested SVM mode */
1657 svm->nested_vmcb = 0;
1658
1659 return 0;
1660}
1661
1662static int nested_svm_vmexit(struct vcpu_svm *svm)
1663{
1664 nsvm_printk("VMexit\n");
1665 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1666 NULL, nested_svm_vmexit_real))
1667 return 1;
1668
1669 kvm_mmu_reset_context(&svm->vcpu);
1670 kvm_mmu_load(&svm->vcpu);
1671
1672 return 0;
1673}
3d6368ef
AG		 1674
1675static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1676 void *arg2, void *opaque)
1677{
1678 int i;
1679 u32 *nested_msrpm = (u32*)arg1;
1680 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1681 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1682 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1683
1684 return 0;
1685}
1686
1687static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1688 void *arg2, void *opaque)
1689{
1690 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1691 struct vmcb *hsave = svm->hsave;
1692
1693 /* nested_vmcb is our indicator if nested SVM is activated */
1694 svm->nested_vmcb = svm->vmcb->save.rax;
1695
1696 /* Clear internal status */
1697 svm->vcpu.arch.exception.pending = false;
1698
1699 /* Save the old vmcb, so we don't need to pick what we save, but
1700 can restore everything when a VMEXIT occurs */
1701 memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1702 /* We need to remember the original CR3 in the SPT case */
1703 if (!npt_enabled)
1704 hsave->save.cr3 = svm->vcpu.arch.cr3;
1705 hsave->save.cr4 = svm->vcpu.arch.cr4;
1706 hsave->save.rip = svm->next_rip;
1707
1708 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1709 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1710 else
1711 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1712
1713 /* Load the nested guest state */
1714 svm->vmcb->save.es = nested_vmcb->save.es;
1715 svm->vmcb->save.cs = nested_vmcb->save.cs;
1716 svm->vmcb->save.ss = nested_vmcb->save.ss;
1717 svm->vmcb->save.ds = nested_vmcb->save.ds;
1718 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1719 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1720 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1721 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1722 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1723 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1724 if (npt_enabled) {
1725 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1726 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1727 } else {
1728 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1729 kvm_mmu_reset_context(&svm->vcpu);
1730 }
1731 svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1732 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1733 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1734 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1735 /* In case we don't even reach vcpu_run, the fields are not updated */
1736 svm->vmcb->save.rax = nested_vmcb->save.rax;
1737 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1738 svm->vmcb->save.rip = nested_vmcb->save.rip;
1739 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1740 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1741 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1742
1743 /* We don't want a nested guest to be more powerful than the guest,
1744 so all intercepts are ORed */
1745 svm->vmcb->control.intercept_cr_read |=
1746 nested_vmcb->control.intercept_cr_read;
1747 svm->vmcb->control.intercept_cr_write |=
1748 nested_vmcb->control.intercept_cr_write;
1749 svm->vmcb->control.intercept_dr_read |=
1750 nested_vmcb->control.intercept_dr_read;
1751 svm->vmcb->control.intercept_dr_write |=
1752 nested_vmcb->control.intercept_dr_write;
1753 svm->vmcb->control.intercept_exceptions |=
1754 nested_vmcb->control.intercept_exceptions;
1755
1756 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1757
1758 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1759
1760 force_new_asid(&svm->vcpu);
1761 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1762 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1763 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1764 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1765 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1766 nested_vmcb->control.int_ctl);
1767 }
1768 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1769 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1770 else
1771 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1772
1773 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1774 nested_vmcb->control.exit_int_info,
1775 nested_vmcb->control.int_state);
1776
1777 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1778 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1779 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1780 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1781 nsvm_printk("Injecting Event: 0x%x\n",
1782 nested_vmcb->control.event_inj);
1783 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1784 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1785
1786 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1787
1788 return 0;
1789}
1790
5542675b
AG		 1791static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1792{
1793 to_vmcb->save.fs = from_vmcb->save.fs;
1794 to_vmcb->save.gs = from_vmcb->save.gs;
1795 to_vmcb->save.tr = from_vmcb->save.tr;
1796 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1797 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1798 to_vmcb->save.star = from_vmcb->save.star;
1799 to_vmcb->save.lstar = from_vmcb->save.lstar;
1800 to_vmcb->save.cstar = from_vmcb->save.cstar;
1801 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1802 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1803 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1804 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1805
1806 return 1;
1807}
1808
1809static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1810 void *arg2, void *opaque)
1811{
1812 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1813}
1814
1815static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1816 void *arg2, void *opaque)
1817{
1818 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1819}
1820
1821static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1822{
1823 if (nested_svm_check_permissions(svm))
1824 return 1;
1825
1826 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1827 skip_emulated_instruction(&svm->vcpu);
1828
1829 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1830
1831 return 1;
1832}
1833
1834static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1835{
1836 if (nested_svm_check_permissions(svm))
1837 return 1;
1838
1839 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1840 skip_emulated_instruction(&svm->vcpu);
1841
1842 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1843
1844 return 1;
1845}
1846
3d6368ef
AG		 1847static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1848{
1849 nsvm_printk("VMrun\n");
1850 if (nested_svm_check_permissions(svm))
1851 return 1;
1852
1853 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1854 skip_emulated_instruction(&svm->vcpu);
1855
1856 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1857 NULL, nested_svm_vmrun))
1858 return 1;
1859
1860 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1861 NULL, nested_svm_vmrun_msrpm))
1862 return 1;
1863
1864 return 1;
1865}
1866
1371d904
AG		 1867static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1868{
1869 if (nested_svm_check_permissions(svm))
1870 return 1;
1871
1872 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1873 skip_emulated_instruction(&svm->vcpu);
1874
1875 svm->vcpu.arch.hflags |= HF_GIF_MASK;
1876
1877 return 1;
1878}
1879
1880static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1881{
1882 if (nested_svm_check_permissions(svm))
1883 return 1;
1884
1885 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1886 skip_emulated_instruction(&svm->vcpu);
1887
1888 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1889
1890 /* After a CLGI no interrupts should come */
1891 svm_clear_vintr(svm);
1892 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1893
1894 return 1;
1895}
1896
e756fc62
RR		 1897static int invalid_op_interception(struct vcpu_svm *svm,
1898 struct kvm_run *kvm_run)
6aa8b732 1899{
7ee5d940 1900 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1901 return 1;
1902}
1903
e756fc62
RR		 1904static int task_switch_interception(struct vcpu_svm *svm,
1905 struct kvm_run *kvm_run)
6aa8b732 1906{
37817f29 1907 u16 tss_selector;
64a7ec06
GN		 1908 int reason;
1909 int int_type = svm->vmcb->control.exit_int_info &
1910 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1911 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1912 uint32_t type =
1913 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1914 uint32_t idt_v =
1915 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1916
1917 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1918
37817f29
IE		 1919 if (svm->vmcb->control.exit_info_2 &
1920 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1921 reason = TASK_SWITCH_IRET;
1922 else if (svm->vmcb->control.exit_info_2 &
1923 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1924 reason = TASK_SWITCH_JMP;
fe8e7f83 1925 else if (idt_v)
64a7ec06
GN		 1926 reason = TASK_SWITCH_GATE;
1927 else
1928 reason = TASK_SWITCH_CALL;
1929
fe8e7f83
GN		 1930 if (reason == TASK_SWITCH_GATE) {
1931 switch (type) {
1932 case SVM_EXITINTINFO_TYPE_NMI:
1933 svm->vcpu.arch.nmi_injected = false;
1934 break;
1935 case SVM_EXITINTINFO_TYPE_EXEPT:
1936 kvm_clear_exception_queue(&svm->vcpu);
1937 break;
1938 case SVM_EXITINTINFO_TYPE_INTR:
1939 kvm_clear_interrupt_queue(&svm->vcpu);
1940 break;
1941 default:
1942 break;
1943 }
1944 }
64a7ec06 1945
8317c298
GN		 1946 if (reason != TASK_SWITCH_GATE ||
1947 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1948 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 1949 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1950 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 1951
1952 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 1953}
1954
e756fc62 1955static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 1956{
5fdbf976 1957 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 1958 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 1959 return 1;
6aa8b732
AK		 1960}
1961
95ba8273
GN		 1962static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1963{
1964 ++svm->vcpu.stat.nmi_window_exits;
1965 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 1966 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 1967 return 1;
1968}
1969
a7052897
MT		 1970static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1971{
1972 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1973 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1974 return 1;
1975}
1976
e756fc62
RR		 1977static int emulate_on_interception(struct vcpu_svm *svm,
1978 struct kvm_run *kvm_run)
6aa8b732 1979{
3427318f 1980 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
b8688d51 1981 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 1982 return 1;
1983}
1984
1d075434
JR		 1985static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1986{
0a5fff19
GN		 1987 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1988 /* instruction emulation calls kvm_set_cr8() */
1d075434 1989 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
95ba8273
GN		 1990 if (irqchip_in_kernel(svm->vcpu.kvm)) {
1991 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 1992 return 1;
95ba8273 1993 }
0a5fff19
GN		 1994 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1995 return 1;
1d075434
JR		 1996 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1997 return 0;
1998}
1999
6aa8b732
AK		 2000static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2001{
a2fa3e9f
GH		 2002 struct vcpu_svm *svm = to_svm(vcpu);
2003
6aa8b732 2004 switch (ecx) {
af24a4e4 2005 case MSR_IA32_TSC: {
6aa8b732
AK		 2006 u64 tsc;
2007
2008 rdtscll(tsc);
a2fa3e9f 2009 *data = svm->vmcb->control.tsc_offset + tsc;
6aa8b732
AK		 2010 break;
2011 }
0e859cac 2012 case MSR_K6_STAR:
a2fa3e9f 2013 *data = svm->vmcb->save.star;
6aa8b732 2014 break;
0e859cac 2015#ifdef CONFIG_X86_64
6aa8b732 2016 case MSR_LSTAR:
a2fa3e9f 2017 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2018 break;
2019 case MSR_CSTAR:
a2fa3e9f 2020 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2021 break;
2022 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2023 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2024 break;
2025 case MSR_SYSCALL_MASK:
a2fa3e9f 2026 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2027 break;
2028#endif
2029 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2030 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2031 break;
2032 case MSR_IA32_SYSENTER_EIP:
017cb99e 2033 *data = svm->sysenter_eip;
6aa8b732
AK		 2034 break;
2035 case MSR_IA32_SYSENTER_ESP:
017cb99e 2036 *data = svm->sysenter_esp;
6aa8b732 2037 break;
a2938c80
JR		 2038 /* Nobody will change the following 5 values in the VMCB so
2039 we can safely return them on rdmsr. They will always be 0
2040 until LBRV is implemented. */
2041 case MSR_IA32_DEBUGCTLMSR:
2042 *data = svm->vmcb->save.dbgctl;
2043 break;
2044 case MSR_IA32_LASTBRANCHFROMIP:
2045 *data = svm->vmcb->save.br_from;
2046 break;
2047 case MSR_IA32_LASTBRANCHTOIP:
2048 *data = svm->vmcb->save.br_to;
2049 break;
2050 case MSR_IA32_LASTINTFROMIP:
2051 *data = svm->vmcb->save.last_excp_from;
2052 break;
2053 case MSR_IA32_LASTINTTOIP:
2054 *data = svm->vmcb->save.last_excp_to;
2055 break;
b286d5d8
AG		 2056 case MSR_VM_HSAVE_PA:
2057 *data = svm->hsave_msr;
2058 break;
eb6f302e
JR		 2059 case MSR_VM_CR:
2060 *data = 0;
2061 break;
c8a73f18
AG		 2062 case MSR_IA32_UCODE_REV:
2063 *data = 0x01000065;
2064 break;
6aa8b732 2065 default:
3bab1f5d 2066 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2067 }
2068 return 0;
2069}
2070
e756fc62 2071static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2072{
ad312c7c 2073 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2074 u64 data;
2075
e756fc62 2076 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2077 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2078 else {
af9ca2d7
JR		 2079 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2080 (u32)(data >> 32), handler);
2081
5fdbf976 2082 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2083 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2084 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2085 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2086 }
2087 return 1;
2088}
2089
2090static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2091{
a2fa3e9f
GH		 2092 struct vcpu_svm *svm = to_svm(vcpu);
2093
6aa8b732 2094 switch (ecx) {
af24a4e4 2095 case MSR_IA32_TSC: {
6aa8b732
AK		 2096 u64 tsc;
2097
2098 rdtscll(tsc);
a2fa3e9f 2099 svm->vmcb->control.tsc_offset = data - tsc;
6aa8b732
AK		 2100 break;
2101 }
0e859cac 2102 case MSR_K6_STAR:
a2fa3e9f 2103 svm->vmcb->save.star = data;
6aa8b732 2104 break;
49b14f24 2105#ifdef CONFIG_X86_64
6aa8b732 2106 case MSR_LSTAR:
a2fa3e9f 2107 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2108 break;
2109 case MSR_CSTAR:
a2fa3e9f 2110 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2111 break;
2112 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2113 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2114 break;
2115 case MSR_SYSCALL_MASK:
a2fa3e9f 2116 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2117 break;
2118#endif
2119 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2120 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2121 break;
2122 case MSR_IA32_SYSENTER_EIP:
017cb99e 2123 svm->sysenter_eip = data;
a2fa3e9f 2124 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2125 break;
2126 case MSR_IA32_SYSENTER_ESP:
017cb99e 2127 svm->sysenter_esp = data;
a2fa3e9f 2128 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2129 break;
a2938c80 2130 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2131 if (!svm_has(SVM_FEATURE_LBRV)) {
2132 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2133 __func__, data);
24e09cbf
JR		 2134 break;
2135 }
2136 if (data & DEBUGCTL_RESERVED_BITS)
2137 return 1;
2138
2139 svm->vmcb->save.dbgctl = data;
2140 if (data & (1ULL<<0))
2141 svm_enable_lbrv(svm);
2142 else
2143 svm_disable_lbrv(svm);
a2938c80 2144 break;
62b9abaa
JR		 2145 case MSR_K7_EVNTSEL0:
2146 case MSR_K7_EVNTSEL1:
2147 case MSR_K7_EVNTSEL2:
2148 case MSR_K7_EVNTSEL3:
14ae51b6
CL		 2149 case MSR_K7_PERFCTR0:
2150 case MSR_K7_PERFCTR1:
2151 case MSR_K7_PERFCTR2:
2152 case MSR_K7_PERFCTR3:
62b9abaa 2153 /*
14ae51b6
CL		 2154 * Just discard all writes to the performance counters; this
2155 * should keep both older linux and windows 64-bit guests
2156 * happy
62b9abaa 2157 */
14ae51b6
CL		 2158 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2159
b286d5d8
AG		 2160 break;
2161 case MSR_VM_HSAVE_PA:
2162 svm->hsave_msr = data;
62b9abaa 2163 break;
6aa8b732 2164 default:
3bab1f5d 2165 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2166 }
2167 return 0;
2168}
2169
e756fc62 2170static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2171{
ad312c7c 2172 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2173 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2174 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7
JR		 2175
2176 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2177 handler);
2178
5fdbf976 2179 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2180 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2181 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2182 else
e756fc62 2183 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2184 return 1;
2185}
2186
e756fc62 2187static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
6aa8b732 2188{
e756fc62
RR		 2189 if (svm->vmcb->control.exit_info_1)
2190 return wrmsr_interception(svm, kvm_run);
6aa8b732 2191 else
e756fc62 2192 return rdmsr_interception(svm, kvm_run);
6aa8b732
AK		 2193}
2194
e756fc62 2195static int interrupt_window_interception(struct vcpu_svm *svm,
c1150d8c
DL		 2196 struct kvm_run *kvm_run)
2197{
af9ca2d7
JR		 2198 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2199
f0b85051 2200 svm_clear_vintr(svm);
85f455f7 2201 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2202 /*
2203 * If the user space waits to inject interrupts, exit as soon as
2204 * possible
2205 */
8061823a
GN		 2206 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2207 kvm_run->request_interrupt_window &&
2208 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2209 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2210 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2211 return 0;
2212 }
2213
2214 return 1;
2215}
2216
e756fc62 2217static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
6aa8b732
AK		 2218 struct kvm_run *kvm_run) = {
2219 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2220 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2221 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2222 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2223 /* for now: */
2224 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2225 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2226 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2227 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2228 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2229 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2230 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2231 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2232 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2233 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2234 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2235 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2236 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2237 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2238 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2239 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2240 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2241 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2242 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2243 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2244 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2245 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2246 [SVM_EXIT_SMI] = nop_on_interception,
2247 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2248 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2249 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2250 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2251 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2252 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2253 [SVM_EXIT_HLT] = halt_interception,
a7052897 2254 [SVM_EXIT_INVLPG] = invlpg_interception,
6aa8b732
AK		 2255 [SVM_EXIT_INVLPGA] = invalid_op_interception,
2256 [SVM_EXIT_IOIO] = io_interception,
2257 [SVM_EXIT_MSR] = msr_interception,
2258 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2259 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2260 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2261 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2262 [SVM_EXIT_VMLOAD] = vmload_interception,
2263 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2264 [SVM_EXIT_STGI] = stgi_interception,
2265 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2266 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2267 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2268 [SVM_EXIT_MONITOR] = invalid_op_interception,
2269 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2270 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2271};
2272
04d2cc77 2273static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
6aa8b732 2274{
04d2cc77 2275 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 2276 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2277
af9ca2d7
JR		 2278 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2279 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2280
cf74a78b
AG		 2281 if (is_nested(svm)) {
2282 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2283 exit_code, svm->vmcb->control.exit_info_1,
2284 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2285 if (nested_svm_exit_handled(svm, true)) {
2286 nested_svm_vmexit(svm);
2287 nsvm_printk("-> #VMEXIT\n");
2288 return 1;
2289 }
2290 }
2291
709ddebf
JR		 2292 if (npt_enabled) {
2293 int mmu_reload = 0;
2294 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2295 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2296 mmu_reload = 1;
2297 }
2298 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2299 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2300 if (mmu_reload) {
2301 kvm_mmu_reset_context(vcpu);
2302 kvm_mmu_load(vcpu);
2303 }
2304 }
2305
04d2cc77
AK		 2306
2307 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2308 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2309 kvm_run->fail_entry.hardware_entry_failure_reason
2310 = svm->vmcb->control.exit_code;
2311 return 0;
2312 }
2313
a2fa3e9f 2314 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2315 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2316 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2317 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2318 "exit_code 0x%x\n",
b8688d51 2319 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2320 exit_code);
2321
9d8f549d 2322 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2323 || !svm_exit_handlers[exit_code]) {
6aa8b732 2324 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2325 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2326 return 0;
2327 }
2328
e756fc62 2329 return svm_exit_handlers[exit_code](svm, kvm_run);
6aa8b732
AK		 2330}
2331
2332static void reload_tss(struct kvm_vcpu *vcpu)
2333{
2334 int cpu = raw_smp_processor_id();
2335
2336 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2337 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2338 load_TR_desc();
2339}
2340
e756fc62 2341static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2342{
2343 int cpu = raw_smp_processor_id();
2344
2345 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2346
a2fa3e9f 2347 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2348 /* FIXME: handle wraparound of asid_generation */
2349 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2350 new_asid(svm, svm_data);
6aa8b732
AK		 2351}
2352
95ba8273
GN		 2353static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2354{
2355 struct vcpu_svm *svm = to_svm(vcpu);
2356
2357 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2358 vcpu->arch.hflags |= HF_NMI_MASK;
2359 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2360 ++vcpu->stat.nmi_injections;
2361}
6aa8b732 2362
85f455f7 2363static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2364{
2365 struct vmcb_control_area *control;
2366
af9ca2d7
JR		 2367 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2368
fa89a817 2369 ++svm->vcpu.stat.irq_injections;
e756fc62 2370 control = &svm->vmcb->control;
85f455f7 2371 control->int_vector = irq;
6aa8b732
AK		 2372 control->int_ctl &= ~V_INTR_PRIO_MASK;
2373 control->int_ctl |= V_IRQ_MASK |
2374 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2375}
2376
95ba8273 2377static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
9222be18 2378{
95ba8273
GN		 2379 struct vcpu_svm *svm = to_svm(vcpu);
2380
9222be18
GN		 2381 svm->vmcb->control.event_inj = nr |
2382 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2383}
2384
66fd3f7f 2385static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2386{
2387 struct vcpu_svm *svm = to_svm(vcpu);
2388
cf74a78b
AG		 2389 nested_svm_intr(svm);
2390
66fd3f7f 2391 svm_queue_irq(vcpu, vcpu->arch.interrupt.nr);
2a8067f1
ED		 2392}
2393
95ba8273 2394static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2395{
2396 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2397
95ba8273 2398 if (irr == -1)
aaacfc9a
JR		 2399 return;
2400
95ba8273
GN		 2401 if (tpr >= irr)
2402 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2403}
aaacfc9a 2404
95ba8273
GN		 2405static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2406{
2407 struct vcpu_svm *svm = to_svm(vcpu);
2408 struct vmcb *vmcb = svm->vmcb;
2409 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2410 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2411}
2412
78646121
GN		 2413static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2414{
2415 struct vcpu_svm *svm = to_svm(vcpu);
2416 struct vmcb *vmcb = svm->vmcb;
2417 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2418 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2419 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2420}
2421
9222be18 2422static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2423{
9222be18
GN		 2424 svm_set_vintr(to_svm(vcpu));
2425 svm_inject_irq(to_svm(vcpu), 0x0);
85f455f7
ED		 2426}
2427
95ba8273 2428static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2429{
04d2cc77 2430 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2431
44c11430
GN		 2432 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2433 == HF_NMI_MASK)
2434 return; /* IRET will cause a vm exit */
2435
2436 /* Something prevents NMI from been injected. Single step over
2437 possible problem (IRET or exception injection or interrupt
2438 shadow) */
2439 vcpu->arch.singlestep = true;
2440 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2441 update_db_intercept(vcpu);
c1150d8c
DL		 2442}
2443
cbc94022
IE		 2444static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2445{
2446 return 0;
2447}
2448
d9e368d6
AK		 2449static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2450{
2451 force_new_asid(vcpu);
2452}
2453
04d2cc77
AK		 2454static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2455{
2456}
2457
d7bf8221
JR		 2458static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2459{
2460 struct vcpu_svm *svm = to_svm(vcpu);
2461
2462 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2463 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2464 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2465 }
2466}
2467
649d6864
JR		 2468static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2469{
2470 struct vcpu_svm *svm = to_svm(vcpu);
2471 u64 cr8;
2472
649d6864
JR		 2473 cr8 = kvm_get_cr8(vcpu);
2474 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2475 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2476}
2477
9222be18
GN		 2478static void svm_complete_interrupts(struct vcpu_svm *svm)
2479{
2480 u8 vector;
2481 int type;
2482 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2483
44c11430
GN		 2484 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2485 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2486
9222be18
GN		 2487 svm->vcpu.arch.nmi_injected = false;
2488 kvm_clear_exception_queue(&svm->vcpu);
2489 kvm_clear_interrupt_queue(&svm->vcpu);
2490
2491 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2492 return;
2493
2494 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2495 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2496
2497 switch (type) {
2498 case SVM_EXITINTINFO_TYPE_NMI:
2499 svm->vcpu.arch.nmi_injected = true;
2500 break;
2501 case SVM_EXITINTINFO_TYPE_EXEPT:
2502 /* In case of software exception do not reinject an exception
2503 vector, but re-execute and instruction instead */
66fd3f7f 2504 if (kvm_exception_is_soft(vector))
9222be18
GN		 2505 break;
2506 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2507 u32 err = svm->vmcb->control.exit_int_info_err;
2508 kvm_queue_exception_e(&svm->vcpu, vector, err);
2509
2510 } else
2511 kvm_queue_exception(&svm->vcpu, vector);
2512 break;
2513 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2514 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2515 break;
2516 default:
2517 break;
2518 }
2519}
2520
80e31d4f
AK		 2521#ifdef CONFIG_X86_64
2522#define R "r"
2523#else
2524#define R "e"
2525#endif
2526
04d2cc77 2527static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2528{
a2fa3e9f 2529 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2530 u16 fs_selector;
2531 u16 gs_selector;
2532 u16 ldt_selector;
d9e368d6 2533
5fdbf976
MT		 2534 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2535 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2536 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2537
e756fc62 2538 pre_svm_run(svm);
6aa8b732 2539
649d6864
JR		 2540 sync_lapic_to_cr8(vcpu);
2541
6aa8b732 2542 save_host_msrs(vcpu);
d6e88aec
AK		 2543 fs_selector = kvm_read_fs();
2544 gs_selector = kvm_read_gs();
2545 ldt_selector = kvm_read_ldt();
a2fa3e9f 2546 svm->host_cr2 = kvm_read_cr2();
3d6368ef
AG		 2547 if (!is_nested(svm))
2548 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2549 /* required for live migration with NPT */
2550 if (npt_enabled)
2551 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2552
04d2cc77
AK		 2553 clgi();
2554
2555 local_irq_enable();
36241b8c 2556
6aa8b732 2557 asm volatile (
80e31d4f
AK		 2558 "push %%"R"bp; \n\t"
2559 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2560 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2561 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2562 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2563 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2564 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2565#ifdef CONFIG_X86_64
fb3f0f51
RR		 2566 "mov %c[r8](%[svm]), %%r8 \n\t"
2567 "mov %c[r9](%[svm]), %%r9 \n\t"
2568 "mov %c[r10](%[svm]), %%r10 \n\t"
2569 "mov %c[r11](%[svm]), %%r11 \n\t"
2570 "mov %c[r12](%[svm]), %%r12 \n\t"
2571 "mov %c[r13](%[svm]), %%r13 \n\t"
2572 "mov %c[r14](%[svm]), %%r14 \n\t"
2573 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2574#endif
2575
6aa8b732 2576 /* Enter guest mode */
80e31d4f
AK		 2577 "push %%"R"ax \n\t"
2578 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2579 __ex(SVM_VMLOAD) "\n\t"
2580 __ex(SVM_VMRUN) "\n\t"
2581 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2582 "pop %%"R"ax \n\t"
6aa8b732
AK		 2583
2584 /* Save guest registers, load host registers */
80e31d4f
AK		 2585 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2586 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2587 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2588 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2589 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2590 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2591#ifdef CONFIG_X86_64
fb3f0f51
RR		 2592 "mov %%r8, %c[r8](%[svm]) \n\t"
2593 "mov %%r9, %c[r9](%[svm]) \n\t"
2594 "mov %%r10, %c[r10](%[svm]) \n\t"
2595 "mov %%r11, %c[r11](%[svm]) \n\t"
2596 "mov %%r12, %c[r12](%[svm]) \n\t"
2597 "mov %%r13, %c[r13](%[svm]) \n\t"
2598 "mov %%r14, %c[r14](%[svm]) \n\t"
2599 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2600#endif
80e31d4f 2601 "pop %%"R"bp"
6aa8b732 2602 :
fb3f0f51 2603 : [svm]"a"(svm),
6aa8b732 2604 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2605 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2606 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2607 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2608 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2609 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2610 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2611#ifdef CONFIG_X86_64
ad312c7c
ZX		 2612 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2613 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2614 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2615 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2616 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2617 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2618 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2619 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2620#endif
54a08c04 2621 : "cc", "memory"
80e31d4f 2622 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2623#ifdef CONFIG_X86_64
54a08c04
LV		 2624 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2625#endif
2626 );
6aa8b732 2627
ad312c7c 2628 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2629 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2630 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2631 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2632
a2fa3e9f 2633 kvm_write_cr2(svm->host_cr2);
6aa8b732 2634
d6e88aec
AK		 2635 kvm_load_fs(fs_selector);
2636 kvm_load_gs(gs_selector);
2637 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2638 load_host_msrs(vcpu);
2639
2640 reload_tss(vcpu);
2641
56ba47dd
AK		 2642 local_irq_disable();
2643
2644 stgi();
2645
d7bf8221
JR		 2646 sync_cr8_to_lapic(vcpu);
2647
a2fa3e9f 2648 svm->next_rip = 0;
9222be18 2649
6de4f3ad
AK		 2650 if (npt_enabled) {
2651 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2652 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2653 }
2654
9222be18 2655 svm_complete_interrupts(svm);
6aa8b732
AK		 2656}
2657
80e31d4f
AK		 2658#undef R
2659
6aa8b732
AK		 2660static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2661{
a2fa3e9f
GH		 2662 struct vcpu_svm *svm = to_svm(vcpu);
2663
709ddebf
JR		 2664 if (npt_enabled) {
2665 svm->vmcb->control.nested_cr3 = root;
2666 force_new_asid(vcpu);
2667 return;
2668 }
2669
a2fa3e9f 2670 svm->vmcb->save.cr3 = root;
6aa8b732 2671 force_new_asid(vcpu);
7807fa6c
AL		 2672
2673 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2674 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2675 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2676 vcpu->fpu_active = 0;
2677 }
6aa8b732
AK		 2678}
2679
6aa8b732
AK		 2680static int is_disabled(void)
2681{
6031a61c
JR		 2682 u64 vm_cr;
2683
2684 rdmsrl(MSR_VM_CR, vm_cr);
2685 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2686 return 1;
2687
6aa8b732
AK		 2688 return 0;
2689}
2690
102d8325
IM		 2691static void
2692svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2693{
2694 /*
2695 * Patch in the VMMCALL instruction:
2696 */
2697 hypercall[0] = 0x0f;
2698 hypercall[1] = 0x01;
2699 hypercall[2] = 0xd9;
102d8325
IM		 2700}
2701
002c7f7c
YS		 2702static void svm_check_processor_compat(void *rtn)
2703{
2704 *(int *)rtn = 0;
2705}
2706
774ead3a
AK		 2707static bool svm_cpu_has_accelerated_tpr(void)
2708{
2709 return false;
2710}
2711
67253af5
SY		 2712static int get_npt_level(void)
2713{
2714#ifdef CONFIG_X86_64
2715 return PT64_ROOT_LEVEL;
2716#else
2717 return PT32E_ROOT_LEVEL;
2718#endif
2719}
2720
4b12f0de 2721static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2722{
2723 return 0;
2724}
2725
cbdd1bea 2726static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2727 .cpu_has_kvm_support = has_svm,
2728 .disabled_by_bios = is_disabled,
2729 .hardware_setup = svm_hardware_setup,
2730 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2731 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2732 .hardware_enable = svm_hardware_enable,
2733 .hardware_disable = svm_hardware_disable,
774ead3a 2734 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2735
2736 .vcpu_create = svm_create_vcpu,
2737 .vcpu_free = svm_free_vcpu,
04d2cc77 2738 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2739
04d2cc77 2740 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2741 .vcpu_load = svm_vcpu_load,
2742 .vcpu_put = svm_vcpu_put,
2743
2744 .set_guest_debug = svm_guest_debug,
2745 .get_msr = svm_get_msr,
2746 .set_msr = svm_set_msr,
2747 .get_segment_base = svm_get_segment_base,
2748 .get_segment = svm_get_segment,
2749 .set_segment = svm_set_segment,
2e4d2653 2750 .get_cpl = svm_get_cpl,
1747fb71 2751 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2752 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2753 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2754 .set_cr3 = svm_set_cr3,
2755 .set_cr4 = svm_set_cr4,
2756 .set_efer = svm_set_efer,
2757 .get_idt = svm_get_idt,
2758 .set_idt = svm_set_idt,
2759 .get_gdt = svm_get_gdt,
2760 .set_gdt = svm_set_gdt,
2761 .get_dr = svm_get_dr,
2762 .set_dr = svm_set_dr,
6de4f3ad 2763 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2764 .get_rflags = svm_get_rflags,
2765 .set_rflags = svm_set_rflags,
2766
6aa8b732 2767 .tlb_flush = svm_flush_tlb,
6aa8b732 2768
6aa8b732 2769 .run = svm_vcpu_run,
04d2cc77 2770 .handle_exit = handle_exit,
6aa8b732 2771 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2772 .set_interrupt_shadow = svm_set_interrupt_shadow,
2773 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2774 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2775 .set_irq = svm_set_irq,
95ba8273 2776 .set_nmi = svm_inject_nmi,
298101da 2777 .queue_exception = svm_queue_exception,
78646121 2778 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2779 .nmi_allowed = svm_nmi_allowed,
2780 .enable_nmi_window = enable_nmi_window,
2781 .enable_irq_window = enable_irq_window,
2782 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2783
2784 .set_tss_addr = svm_set_tss_addr,
67253af5 2785 .get_tdp_level = get_npt_level,
4b12f0de 2786 .get_mt_mask = svm_get_mt_mask,
6aa8b732
AK		 2787};
2788
2789static int __init svm_init(void)
2790{
cb498ea2 2791 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2792 THIS_MODULE);
6aa8b732
AK		 2793}
2794
2795static void __exit svm_exit(void)
2796{
cb498ea2 2797 kvm_exit();
6aa8b732
AK		 2798}
2799
2800module_init(svm_init)
2801module_exit(svm_exit)
Linux kernel - Deliverables
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