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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
2961e876
GN		 421 u32 vm_entry_controls_shadow;
422 u32 vm_exit_controls_shadow;
d462b819
NHE		 423 /*
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
427 */
428 struct loaded_vmcs vmcs01;
429 struct loaded_vmcs *loaded_vmcs;
430 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 431 struct msr_autoload {
432 unsigned nr;
433 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
434 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
435 } msr_autoload;
a2fa3e9f
GH		 436 struct {
437 int loaded;
438 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 439#ifdef CONFIG_X86_64
440 u16 ds_sel, es_sel;
441#endif
152d3f2f
LV		 442 int gs_ldt_reload_needed;
443 int fs_reload_needed;
d77c26fc 444 } host_state;
9c8cba37 445 struct {
7ffd92c5 446 int vm86_active;
78ac8b47 447 ulong save_rflags;
f5f7b2fe
AK		 448 struct kvm_segment segs[8];
449 } rmode;
450 struct {
451 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 452 struct kvm_save_segment {
453 u16 selector;
454 unsigned long base;
455 u32 limit;
456 u32 ar;
f5f7b2fe 457 } seg[8];
2fb92db1 458 } segment_cache;
2384d2b3 459 int vpid;
04fa4d32 460 bool emulation_required;
3b86cd99
JK		 461
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked;
464 ktime_t entry_time;
465 s64 vnmi_blocked_time;
a0861c02 466 u32 exit_reason;
4e47c7a6
SY		 467
468 bool rdtscp_enabled;
ec378aee 469
01e439be
YZ		 470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc;
472
ec378aee
NHE		 473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested;
a2fa3e9f
GH		 475};
476
2fb92db1
AK		 477enum segment_cache_field {
478 SEG_FIELD_SEL = 0,
479 SEG_FIELD_BASE = 1,
480 SEG_FIELD_LIMIT = 2,
481 SEG_FIELD_AR = 3,
482
483 SEG_FIELD_NR = 4
484};
485
a2fa3e9f
GH		 486static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
487{
fb3f0f51 488 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 489}
490
22bd0358
NHE		 491#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
495
4607c2d7
AG		 496
497static const unsigned long shadow_read_only_fields[] = {
498 /*
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
509 */
510 VM_EXIT_REASON,
511 VM_EXIT_INTR_INFO,
512 VM_EXIT_INSTRUCTION_LEN,
513 IDT_VECTORING_INFO_FIELD,
514 IDT_VECTORING_ERROR_CODE,
515 VM_EXIT_INTR_ERROR_CODE,
516 EXIT_QUALIFICATION,
517 GUEST_LINEAR_ADDRESS,
518 GUEST_PHYSICAL_ADDRESS
519};
520static const int max_shadow_read_only_fields =
521 ARRAY_SIZE(shadow_read_only_fields);
522
523static const unsigned long shadow_read_write_fields[] = {
524 GUEST_RIP,
525 GUEST_RSP,
526 GUEST_CR0,
527 GUEST_CR3,
528 GUEST_CR4,
529 GUEST_INTERRUPTIBILITY_INFO,
530 GUEST_RFLAGS,
531 GUEST_CS_SELECTOR,
532 GUEST_CS_AR_BYTES,
533 GUEST_CS_LIMIT,
534 GUEST_CS_BASE,
535 GUEST_ES_BASE,
536 CR0_GUEST_HOST_MASK,
537 CR0_READ_SHADOW,
538 CR4_READ_SHADOW,
539 TSC_OFFSET,
540 EXCEPTION_BITMAP,
541 CPU_BASED_VM_EXEC_CONTROL,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 VM_ENTRY_INTR_INFO_FIELD,
544 VM_ENTRY_INSTRUCTION_LEN,
545 VM_ENTRY_EXCEPTION_ERROR_CODE,
546 HOST_FS_BASE,
547 HOST_GS_BASE,
548 HOST_FS_SELECTOR,
549 HOST_GS_SELECTOR
550};
551static const int max_shadow_read_write_fields =
552 ARRAY_SIZE(shadow_read_write_fields);
553
772e0318 554static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 555 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
556 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
557 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
558 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
559 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
560 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
561 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
562 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
563 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
564 FIELD(HOST_ES_SELECTOR, host_es_selector),
565 FIELD(HOST_CS_SELECTOR, host_cs_selector),
566 FIELD(HOST_SS_SELECTOR, host_ss_selector),
567 FIELD(HOST_DS_SELECTOR, host_ds_selector),
568 FIELD(HOST_FS_SELECTOR, host_fs_selector),
569 FIELD(HOST_GS_SELECTOR, host_gs_selector),
570 FIELD(HOST_TR_SELECTOR, host_tr_selector),
571 FIELD64(IO_BITMAP_A, io_bitmap_a),
572 FIELD64(IO_BITMAP_B, io_bitmap_b),
573 FIELD64(MSR_BITMAP, msr_bitmap),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
577 FIELD64(TSC_OFFSET, tsc_offset),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
579 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
580 FIELD64(EPT_POINTER, ept_pointer),
581 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
582 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
583 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
584 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
585 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
587 FIELD64(GUEST_PDPTR0, guest_pdptr0),
588 FIELD64(GUEST_PDPTR1, guest_pdptr1),
589 FIELD64(GUEST_PDPTR2, guest_pdptr2),
590 FIELD64(GUEST_PDPTR3, guest_pdptr3),
591 FIELD64(HOST_IA32_PAT, host_ia32_pat),
592 FIELD64(HOST_IA32_EFER, host_ia32_efer),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
596 FIELD(EXCEPTION_BITMAP, exception_bitmap),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
599 FIELD(CR3_TARGET_COUNT, cr3_target_count),
600 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
601 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
603 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
608 FIELD(TPR_THRESHOLD, tpr_threshold),
609 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
610 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
611 FIELD(VM_EXIT_REASON, vm_exit_reason),
612 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
613 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
614 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
615 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
616 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
617 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
618 FIELD(GUEST_ES_LIMIT, guest_es_limit),
619 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
620 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
621 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
622 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
623 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
624 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
625 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
626 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
627 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
628 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
629 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
630 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
631 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
632 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
633 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
634 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
635 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
637 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
638 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
639 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 640 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 641 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
642 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
643 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
644 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
645 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
646 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
647 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
648 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
649 FIELD(EXIT_QUALIFICATION, exit_qualification),
650 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
651 FIELD(GUEST_CR0, guest_cr0),
652 FIELD(GUEST_CR3, guest_cr3),
653 FIELD(GUEST_CR4, guest_cr4),
654 FIELD(GUEST_ES_BASE, guest_es_base),
655 FIELD(GUEST_CS_BASE, guest_cs_base),
656 FIELD(GUEST_SS_BASE, guest_ss_base),
657 FIELD(GUEST_DS_BASE, guest_ds_base),
658 FIELD(GUEST_FS_BASE, guest_fs_base),
659 FIELD(GUEST_GS_BASE, guest_gs_base),
660 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
661 FIELD(GUEST_TR_BASE, guest_tr_base),
662 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
663 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
664 FIELD(GUEST_DR7, guest_dr7),
665 FIELD(GUEST_RSP, guest_rsp),
666 FIELD(GUEST_RIP, guest_rip),
667 FIELD(GUEST_RFLAGS, guest_rflags),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
669 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
670 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
671 FIELD(HOST_CR0, host_cr0),
672 FIELD(HOST_CR3, host_cr3),
673 FIELD(HOST_CR4, host_cr4),
674 FIELD(HOST_FS_BASE, host_fs_base),
675 FIELD(HOST_GS_BASE, host_gs_base),
676 FIELD(HOST_TR_BASE, host_tr_base),
677 FIELD(HOST_GDTR_BASE, host_gdtr_base),
678 FIELD(HOST_IDTR_BASE, host_idtr_base),
679 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
680 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
681 FIELD(HOST_RSP, host_rsp),
682 FIELD(HOST_RIP, host_rip),
683};
684static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
685
686static inline short vmcs_field_to_offset(unsigned long field)
687{
688 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
689 return -1;
690 return vmcs_field_to_offset_table[field];
691}
692
a9d30f33
NHE		 693static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
694{
695 return to_vmx(vcpu)->nested.current_vmcs12;
696}
697
698static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
699{
700 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 701 if (is_error_page(page))
a9d30f33 702 return NULL;
32cad84f 703
a9d30f33
NHE		 704 return page;
705}
706
707static void nested_release_page(struct page *page)
708{
709 kvm_release_page_dirty(page);
710}
711
712static void nested_release_page_clean(struct page *page)
713{
714 kvm_release_page_clean(page);
715}
716
bfd0a56b 717static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 718static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 719static void kvm_cpu_vmxon(u64 addr);
720static void kvm_cpu_vmxoff(void);
776e58ea 721static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 722static void vmx_set_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724static void vmx_get_segment(struct kvm_vcpu *vcpu,
725 struct kvm_segment *var, int seg);
d99e4152
GN		 726static bool guest_state_valid(struct kvm_vcpu *vcpu);
727static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 728static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 729static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 730static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 731
6aa8b732
AK		 732static DEFINE_PER_CPU(struct vmcs *, vmxarea);
733static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 734/*
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
737 */
738static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 739static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 740
3e7c73e9
AK		 741static unsigned long *vmx_io_bitmap_a;
742static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 743static unsigned long *vmx_msr_bitmap_legacy;
744static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 745static unsigned long *vmx_msr_bitmap_legacy_x2apic;
746static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 747static unsigned long *vmx_vmread_bitmap;
748static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 749
110312c8 750static bool cpu_has_load_ia32_efer;
8bf00a52 751static bool cpu_has_load_perf_global_ctrl;
110312c8 752
2384d2b3
SY		 753static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
754static DEFINE_SPINLOCK(vmx_vpid_lock);
755
1c3d14fe 756static struct vmcs_config {
6aa8b732
AK		 757 int size;
758 int order;
759 u32 revision_id;
1c3d14fe
YS		 760 u32 pin_based_exec_ctrl;
761 u32 cpu_based_exec_ctrl;
f78e0e2e 762 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 763 u32 vmexit_ctrl;
764 u32 vmentry_ctrl;
765} vmcs_config;
6aa8b732 766
efff9e53 767static struct vmx_capability {
d56f546d
SY		 768 u32 ept;
769 u32 vpid;
770} vmx_capability;
771
6aa8b732
AK		 772#define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 }
779
772e0318 780static const struct kvm_vmx_segment_field {
6aa8b732
AK		 781 unsigned selector;
782 unsigned base;
783 unsigned limit;
784 unsigned ar_bytes;
785} kvm_vmx_segment_fields[] = {
786 VMX_SEGMENT_FIELD(CS),
787 VMX_SEGMENT_FIELD(DS),
788 VMX_SEGMENT_FIELD(ES),
789 VMX_SEGMENT_FIELD(FS),
790 VMX_SEGMENT_FIELD(GS),
791 VMX_SEGMENT_FIELD(SS),
792 VMX_SEGMENT_FIELD(TR),
793 VMX_SEGMENT_FIELD(LDTR),
794};
795
26bb0981
AK		 796static u64 host_efer;
797
6de4f3ad
AK		 798static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
799
4d56c8a7 800/*
8c06585d 801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 802 * away by decrementing the array size.
803 */
6aa8b732 804static const u32 vmx_msr_index[] = {
05b3e0c2 805#ifdef CONFIG_X86_64
44ea2b17 806 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 807#endif
8c06585d 808 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 809};
9d8f549d 810#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 811
31299944 812static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 813{
814 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
815 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 816 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 817}
818
31299944 819static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 820{
821 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
822 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 823 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 824}
825
31299944 826static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 831}
832
31299944 833static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
836 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
837}
838
31299944 839static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
843 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
844}
845
31299944 846static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 847{
04547156 848 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 852{
04547156 853 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 854}
855
31299944 856static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 857{
04547156 858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 859}
860
31299944 861static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 862{
04547156
SY		 863 return vmcs_config.cpu_based_exec_ctrl &
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 865}
866
774ead3a 867static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 868{
04547156
SY		 869 return vmcs_config.cpu_based_2nd_exec_ctrl &
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
871}
872
8d14695f
YZ		 873static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
874{
875 return vmcs_config.cpu_based_2nd_exec_ctrl &
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
877}
878
83d4c286
YZ		 879static inline bool cpu_has_vmx_apic_register_virt(void)
880{
881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_APIC_REGISTER_VIRT;
883}
884
c7c9c56c
YZ		 885static inline bool cpu_has_vmx_virtual_intr_delivery(void)
886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
889}
890
01e439be
YZ		 891static inline bool cpu_has_vmx_posted_intr(void)
892{
893 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
894}
895
896static inline bool cpu_has_vmx_apicv(void)
897{
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
901}
902
04547156
SY		 903static inline bool cpu_has_vmx_flexpriority(void)
904{
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 907}
908
e799794e
MT		 909static inline bool cpu_has_vmx_ept_execute_only(void)
910{
31299944 911 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 912}
913
914static inline bool cpu_has_vmx_eptp_uncacheable(void)
915{
31299944 916 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 917}
918
919static inline bool cpu_has_vmx_eptp_writeback(void)
920{
31299944 921 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 922}
923
924static inline bool cpu_has_vmx_ept_2m_page(void)
925{
31299944 926 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 927}
928
878403b7
SY		 929static inline bool cpu_has_vmx_ept_1g_page(void)
930{
31299944 931 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 932}
933
4bc9b982
SY		 934static inline bool cpu_has_vmx_ept_4levels(void)
935{
936 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
937}
938
83c3a331
XH		 939static inline bool cpu_has_vmx_ept_ad_bits(void)
940{
941 return vmx_capability.ept & VMX_EPT_AD_BIT;
942}
943
31299944 944static inline bool cpu_has_vmx_invept_context(void)
d56f546d 945{
31299944 946 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 947}
948
31299944 949static inline bool cpu_has_vmx_invept_global(void)
d56f546d 950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 952}
953
518c8aee
GJ		 954static inline bool cpu_has_vmx_invvpid_single(void)
955{
956 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
957}
958
b9d762fa
GJ		 959static inline bool cpu_has_vmx_invvpid_global(void)
960{
961 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
962}
963
31299944 964static inline bool cpu_has_vmx_ept(void)
d56f546d 965{
04547156
SY		 966 return vmcs_config.cpu_based_2nd_exec_ctrl &
967 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 968}
969
31299944 970static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 971{
972 return vmcs_config.cpu_based_2nd_exec_ctrl &
973 SECONDARY_EXEC_UNRESTRICTED_GUEST;
974}
975
31299944 976static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 977{
978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
980}
981
31299944 982static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 983{
6d3e435e 984 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 985}
986
31299944 987static inline bool cpu_has_vmx_vpid(void)
2384d2b3 988{
04547156
SY		 989 return vmcs_config.cpu_based_2nd_exec_ctrl &
990 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 991}
992
31299944 993static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 994{
995 return vmcs_config.cpu_based_2nd_exec_ctrl &
996 SECONDARY_EXEC_RDTSCP;
997}
998
ad756a16
MJ		 999static inline bool cpu_has_vmx_invpcid(void)
1000{
1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_ENABLE_INVPCID;
1003}
1004
31299944 1005static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1006{
1007 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008}
1009
f5f48ee1
SY		 1010static inline bool cpu_has_vmx_wbinvd_exit(void)
1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_WBINVD_EXITING;
1014}
1015
abc4fc58
AG		 1016static inline bool cpu_has_vmx_shadow_vmcs(void)
1017{
1018 u64 vmx_msr;
1019 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022 return false;
1023
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_SHADOW_VMCS;
1026}
1027
04547156
SY		 1028static inline bool report_flexpriority(void)
1029{
1030 return flexpriority_enabled;
1031}
1032
fe3ef05c
NHE		 1033static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1034{
1035 return vmcs12->cpu_based_vm_exec_control & bit;
1036}
1037
1038static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1039{
1040 return (vmcs12->cpu_based_vm_exec_control &
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1042 (vmcs12->secondary_vm_exec_control & bit);
1043}
1044
f5c4368f 1045static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
155a97a3
NHE		 1050static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051{
1052 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053}
1054
644d711a
NHE		 1055static inline bool is_exception(u32 intr_info)
1056{
1057 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059}
1060
533558bc
JK		 1061static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1062 u32 exit_intr_info,
1063 unsigned long exit_qualification);
7c177938
NHE		 1064static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1065 struct vmcs12 *vmcs12,
1066 u32 reason, unsigned long qualification);
1067
8b9cf98c 1068static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1069{
1070 int i;
1071
a2fa3e9f 1072 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1073 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1074 return i;
1075 return -1;
1076}
1077
2384d2b3
SY		 1078static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1079{
1080 struct {
1081 u64 vpid : 16;
1082 u64 rsvd : 48;
1083 u64 gva;
1084 } operand = { vpid, 0, gva };
1085
4ecac3fd 1086 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1087 /* CF==1 or ZF==1 --> rc = -1 */
1088 "; ja 1f ; ud2 ; 1:"
1089 : : "a"(&operand), "c"(ext) : "cc", "memory");
1090}
1091
1439442c
SY		 1092static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1093{
1094 struct {
1095 u64 eptp, gpa;
1096 } operand = {eptp, gpa};
1097
4ecac3fd 1098 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1099 /* CF==1 or ZF==1 --> rc = -1 */
1100 "; ja 1f ; ud2 ; 1:\n"
1101 : : "a" (&operand), "c" (ext) : "cc", "memory");
1102}
1103
26bb0981 1104static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1105{
1106 int i;
1107
8b9cf98c 1108 i = __find_msr_index(vmx, msr);
a75beee6 1109 if (i >= 0)
a2fa3e9f 1110 return &vmx->guest_msrs[i];
8b6d44c7 1111 return NULL;
7725f0ba
AK		 1112}
1113
6aa8b732
AK		 1114static void vmcs_clear(struct vmcs *vmcs)
1115{
1116 u64 phys_addr = __pa(vmcs);
1117 u8 error;
1118
4ecac3fd 1119 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1120 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1121 : "cc", "memory");
1122 if (error)
1123 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1124 vmcs, phys_addr);
1125}
1126
d462b819
NHE		 1127static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1128{
1129 vmcs_clear(loaded_vmcs->vmcs);
1130 loaded_vmcs->cpu = -1;
1131 loaded_vmcs->launched = 0;
1132}
1133
7725b894
DX		 1134static void vmcs_load(struct vmcs *vmcs)
1135{
1136 u64 phys_addr = __pa(vmcs);
1137 u8 error;
1138
1139 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1140 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1141 : "cc", "memory");
1142 if (error)
2844d849 1143 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1144 vmcs, phys_addr);
1145}
1146
8f536b76
ZY		 1147#ifdef CONFIG_KEXEC
1148/*
1149 * This bitmap is used to indicate whether the vmclear
1150 * operation is enabled on all cpus. All disabled by
1151 * default.
1152 */
1153static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1154
1155static inline void crash_enable_local_vmclear(int cpu)
1156{
1157 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1158}
1159
1160static inline void crash_disable_local_vmclear(int cpu)
1161{
1162 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1163}
1164
1165static inline int crash_local_vmclear_enabled(int cpu)
1166{
1167 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1168}
1169
1170static void crash_vmclear_local_loaded_vmcss(void)
1171{
1172 int cpu = raw_smp_processor_id();
1173 struct loaded_vmcs *v;
1174
1175 if (!crash_local_vmclear_enabled(cpu))
1176 return;
1177
1178 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1179 loaded_vmcss_on_cpu_link)
1180 vmcs_clear(v->vmcs);
1181}
1182#else
1183static inline void crash_enable_local_vmclear(int cpu) { }
1184static inline void crash_disable_local_vmclear(int cpu) { }
1185#endif /* CONFIG_KEXEC */
1186
d462b819 1187static void __loaded_vmcs_clear(void *arg)
6aa8b732 1188{
d462b819 1189 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1190 int cpu = raw_smp_processor_id();
6aa8b732 1191
d462b819
NHE		 1192 if (loaded_vmcs->cpu != cpu)
1193 return; /* vcpu migration can race with cpu offline */
1194 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1195 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1196 crash_disable_local_vmclear(cpu);
d462b819 1197 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1198
1199 /*
1200 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1201 * is before setting loaded_vmcs->vcpu to -1 which is done in
1202 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1203 * then adds the vmcs into percpu list before it is deleted.
1204 */
1205 smp_wmb();
1206
d462b819 1207 loaded_vmcs_init(loaded_vmcs);
8f536b76 1208 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1209}
1210
d462b819 1211static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1212{
e6c7d321
XG		 1213 int cpu = loaded_vmcs->cpu;
1214
1215 if (cpu != -1)
1216 smp_call_function_single(cpu,
1217 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1218}
1219
1760dd49 1220static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1221{
1222 if (vmx->vpid == 0)
1223 return;
1224
518c8aee
GJ		 1225 if (cpu_has_vmx_invvpid_single())
1226 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1227}
1228
b9d762fa
GJ		 1229static inline void vpid_sync_vcpu_global(void)
1230{
1231 if (cpu_has_vmx_invvpid_global())
1232 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1233}
1234
1235static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1236{
1237 if (cpu_has_vmx_invvpid_single())
1760dd49 1238 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1239 else
1240 vpid_sync_vcpu_global();
1241}
1242
1439442c
SY		 1243static inline void ept_sync_global(void)
1244{
1245 if (cpu_has_vmx_invept_global())
1246 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1247}
1248
1249static inline void ept_sync_context(u64 eptp)
1250{
089d034e 1251 if (enable_ept) {
1439442c
SY		 1252 if (cpu_has_vmx_invept_context())
1253 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1254 else
1255 ept_sync_global();
1256 }
1257}
1258
96304217 1259static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1260{
5e520e62 1261 unsigned long value;
6aa8b732 1262
5e520e62
AK		 1263 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1264 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1265 return value;
1266}
1267
96304217 1268static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1269{
1270 return vmcs_readl(field);
1271}
1272
96304217 1273static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1274{
1275 return vmcs_readl(field);
1276}
1277
96304217 1278static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1279{
05b3e0c2 1280#ifdef CONFIG_X86_64
6aa8b732
AK		 1281 return vmcs_readl(field);
1282#else
1283 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1284#endif
1285}
1286
e52de1b8
AK		 1287static noinline void vmwrite_error(unsigned long field, unsigned long value)
1288{
1289 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1290 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1291 dump_stack();
1292}
1293
6aa8b732
AK		 1294static void vmcs_writel(unsigned long field, unsigned long value)
1295{
1296 u8 error;
1297
4ecac3fd 1298 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1299 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1300 if (unlikely(error))
1301 vmwrite_error(field, value);
6aa8b732
AK		 1302}
1303
1304static void vmcs_write16(unsigned long field, u16 value)
1305{
1306 vmcs_writel(field, value);
1307}
1308
1309static void vmcs_write32(unsigned long field, u32 value)
1310{
1311 vmcs_writel(field, value);
1312}
1313
1314static void vmcs_write64(unsigned long field, u64 value)
1315{
6aa8b732 1316 vmcs_writel(field, value);
7682f2d0 1317#ifndef CONFIG_X86_64
6aa8b732
AK		 1318 asm volatile ("");
1319 vmcs_writel(field+1, value >> 32);
1320#endif
1321}
1322
2ab455cc
AL		 1323static void vmcs_clear_bits(unsigned long field, u32 mask)
1324{
1325 vmcs_writel(field, vmcs_readl(field) & ~mask);
1326}
1327
1328static void vmcs_set_bits(unsigned long field, u32 mask)
1329{
1330 vmcs_writel(field, vmcs_readl(field) | mask);
1331}
1332
2961e876
GN		 1333static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1334{
1335 vmcs_write32(VM_ENTRY_CONTROLS, val);
1336 vmx->vm_entry_controls_shadow = val;
1337}
1338
1339static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1340{
1341 if (vmx->vm_entry_controls_shadow != val)
1342 vm_entry_controls_init(vmx, val);
1343}
1344
1345static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1346{
1347 return vmx->vm_entry_controls_shadow;
1348}
1349
1350
1351static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1352{
1353 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1354}
1355
1356static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1357{
1358 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1359}
1360
1361static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1362{
1363 vmcs_write32(VM_EXIT_CONTROLS, val);
1364 vmx->vm_exit_controls_shadow = val;
1365}
1366
1367static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1368{
1369 if (vmx->vm_exit_controls_shadow != val)
1370 vm_exit_controls_init(vmx, val);
1371}
1372
1373static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1374{
1375 return vmx->vm_exit_controls_shadow;
1376}
1377
1378
1379static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1380{
1381 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1382}
1383
1384static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1385{
1386 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1387}
1388
2fb92db1
AK		 1389static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1390{
1391 vmx->segment_cache.bitmask = 0;
1392}
1393
1394static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1395 unsigned field)
1396{
1397 bool ret;
1398 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1399
1400 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1401 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1402 vmx->segment_cache.bitmask = 0;
1403 }
1404 ret = vmx->segment_cache.bitmask & mask;
1405 vmx->segment_cache.bitmask |= mask;
1406 return ret;
1407}
1408
1409static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1410{
1411 u16 *p = &vmx->segment_cache.seg[seg].selector;
1412
1413 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1414 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1415 return *p;
1416}
1417
1418static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1419{
1420 ulong *p = &vmx->segment_cache.seg[seg].base;
1421
1422 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1423 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1424 return *p;
1425}
1426
1427static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1428{
1429 u32 *p = &vmx->segment_cache.seg[seg].limit;
1430
1431 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1432 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1433 return *p;
1434}
1435
1436static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1437{
1438 u32 *p = &vmx->segment_cache.seg[seg].ar;
1439
1440 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1441 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1442 return *p;
1443}
1444
abd3f2d6
AK		 1445static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1446{
1447 u32 eb;
1448
fd7373cc
JK		 1449 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1450 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1451 if ((vcpu->guest_debug &
1452 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1453 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1454 eb |= 1u << BP_VECTOR;
7ffd92c5 1455 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1456 eb = ~0;
089d034e 1457 if (enable_ept)
1439442c 1458 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1459 if (vcpu->fpu_active)
1460 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1461
1462 /* When we are running a nested L2 guest and L1 specified for it a
1463 * certain exception bitmap, we must trap the same exceptions and pass
1464 * them to L1. When running L2, we will only handle the exceptions
1465 * specified above if L1 did not want them.
1466 */
1467 if (is_guest_mode(vcpu))
1468 eb |= get_vmcs12(vcpu)->exception_bitmap;
1469
abd3f2d6
AK		 1470 vmcs_write32(EXCEPTION_BITMAP, eb);
1471}
1472
2961e876
GN		 1473static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1474 unsigned long entry, unsigned long exit)
8bf00a52 1475{
2961e876
GN		 1476 vm_entry_controls_clearbit(vmx, entry);
1477 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1478}
1479
61d2ef2c
AK		 1480static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1481{
1482 unsigned i;
1483 struct msr_autoload *m = &vmx->msr_autoload;
1484
8bf00a52
GN		 1485 switch (msr) {
1486 case MSR_EFER:
1487 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1488 clear_atomic_switch_msr_special(vmx,
1489 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1490 VM_EXIT_LOAD_IA32_EFER);
1491 return;
1492 }
1493 break;
1494 case MSR_CORE_PERF_GLOBAL_CTRL:
1495 if (cpu_has_load_perf_global_ctrl) {
2961e876 1496 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1497 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1498 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1499 return;
1500 }
1501 break;
110312c8
AK		 1502 }
1503
61d2ef2c
AK		 1504 for (i = 0; i < m->nr; ++i)
1505 if (m->guest[i].index == msr)
1506 break;
1507
1508 if (i == m->nr)
1509 return;
1510 --m->nr;
1511 m->guest[i] = m->guest[m->nr];
1512 m->host[i] = m->host[m->nr];
1513 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1514 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1515}
1516
2961e876
GN		 1517static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1518 unsigned long entry, unsigned long exit,
1519 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1520 u64 guest_val, u64 host_val)
8bf00a52
GN		 1521{
1522 vmcs_write64(guest_val_vmcs, guest_val);
1523 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1524 vm_entry_controls_setbit(vmx, entry);
1525 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1526}
1527
61d2ef2c
AK		 1528static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1529 u64 guest_val, u64 host_val)
1530{
1531 unsigned i;
1532 struct msr_autoload *m = &vmx->msr_autoload;
1533
8bf00a52
GN		 1534 switch (msr) {
1535 case MSR_EFER:
1536 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1537 add_atomic_switch_msr_special(vmx,
1538 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1539 VM_EXIT_LOAD_IA32_EFER,
1540 GUEST_IA32_EFER,
1541 HOST_IA32_EFER,
1542 guest_val, host_val);
1543 return;
1544 }
1545 break;
1546 case MSR_CORE_PERF_GLOBAL_CTRL:
1547 if (cpu_has_load_perf_global_ctrl) {
2961e876 1548 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1549 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1550 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1551 GUEST_IA32_PERF_GLOBAL_CTRL,
1552 HOST_IA32_PERF_GLOBAL_CTRL,
1553 guest_val, host_val);
1554 return;
1555 }
1556 break;
110312c8
AK		 1557 }
1558
61d2ef2c
AK		 1559 for (i = 0; i < m->nr; ++i)
1560 if (m->guest[i].index == msr)
1561 break;
1562
e7fc6f93 1563 if (i == NR_AUTOLOAD_MSRS) {
60266204 1564 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1565 "Can't add msr %x\n", msr);
1566 return;
1567 } else if (i == m->nr) {
61d2ef2c
AK		 1568 ++m->nr;
1569 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1570 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1571 }
1572
1573 m->guest[i].index = msr;
1574 m->guest[i].value = guest_val;
1575 m->host[i].index = msr;
1576 m->host[i].value = host_val;
1577}
1578
33ed6329
AK		 1579static void reload_tss(void)
1580{
33ed6329
AK		 1581 /*
1582 * VT restores TR but not its size. Useless.
1583 */
d359192f 1584 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1585 struct desc_struct *descs;
33ed6329 1586
d359192f 1587 descs = (void *)gdt->address;
33ed6329
AK		 1588 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1589 load_TR_desc();
33ed6329
AK		 1590}
1591
92c0d900 1592static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1593{
3a34a881 1594 u64 guest_efer;
51c6cf66
AK		 1595 u64 ignore_bits;
1596
f6801dff 1597 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1598
51c6cf66 1599 /*
0fa06071 1600 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1601 * outside long mode
1602 */
1603 ignore_bits = EFER_NX | EFER_SCE;
1604#ifdef CONFIG_X86_64
1605 ignore_bits |= EFER_LMA | EFER_LME;
1606 /* SCE is meaningful only in long mode on Intel */
1607 if (guest_efer & EFER_LMA)
1608 ignore_bits &= ~(u64)EFER_SCE;
1609#endif
51c6cf66
AK		 1610 guest_efer &= ~ignore_bits;
1611 guest_efer |= host_efer & ignore_bits;
26bb0981 1612 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1613 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1614
1615 clear_atomic_switch_msr(vmx, MSR_EFER);
1616 /* On ept, can't emulate nx, and must switch nx atomically */
1617 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1618 guest_efer = vmx->vcpu.arch.efer;
1619 if (!(guest_efer & EFER_LMA))
1620 guest_efer &= ~EFER_LME;
1621 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1622 return false;
1623 }
1624
26bb0981 1625 return true;
51c6cf66
AK		 1626}
1627
2d49ec72
GN		 1628static unsigned long segment_base(u16 selector)
1629{
d359192f 1630 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1631 struct desc_struct *d;
1632 unsigned long table_base;
1633 unsigned long v;
1634
1635 if (!(selector & ~3))
1636 return 0;
1637
d359192f 1638 table_base = gdt->address;
2d49ec72
GN		 1639
1640 if (selector & 4) { /* from ldt */
1641 u16 ldt_selector = kvm_read_ldt();
1642
1643 if (!(ldt_selector & ~3))
1644 return 0;
1645
1646 table_base = segment_base(ldt_selector);
1647 }
1648 d = (struct desc_struct *)(table_base + (selector & ~7));
1649 v = get_desc_base(d);
1650#ifdef CONFIG_X86_64
1651 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1652 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1653#endif
1654 return v;
1655}
1656
1657static inline unsigned long kvm_read_tr_base(void)
1658{
1659 u16 tr;
1660 asm("str %0" : "=g"(tr));
1661 return segment_base(tr);
1662}
1663
04d2cc77 1664static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1665{
04d2cc77 1666 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1667 int i;
04d2cc77 1668
a2fa3e9f 1669 if (vmx->host_state.loaded)
33ed6329
AK		 1670 return;
1671
a2fa3e9f 1672 vmx->host_state.loaded = 1;
33ed6329
AK		 1673 /*
1674 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1675 * allow segment selectors with cpl > 0 or ti == 1.
1676 */
d6e88aec 1677 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1678 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1679 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1680 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1681 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1682 vmx->host_state.fs_reload_needed = 0;
1683 } else {
33ed6329 1684 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1685 vmx->host_state.fs_reload_needed = 1;
33ed6329 1686 }
9581d442 1687 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1688 if (!(vmx->host_state.gs_sel & 7))
1689 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1690 else {
1691 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1692 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1693 }
1694
b2da15ac
AK		 1695#ifdef CONFIG_X86_64
1696 savesegment(ds, vmx->host_state.ds_sel);
1697 savesegment(es, vmx->host_state.es_sel);
1698#endif
1699
33ed6329
AK		 1700#ifdef CONFIG_X86_64
1701 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1702 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1703#else
a2fa3e9f
GH		 1704 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1705 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1706#endif
707c0874
AK		 1707
1708#ifdef CONFIG_X86_64
c8770e7b
AK		 1709 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1710 if (is_long_mode(&vmx->vcpu))
44ea2b17 1711 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1712#endif
26bb0981
AK		 1713 for (i = 0; i < vmx->save_nmsrs; ++i)
1714 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1715 vmx->guest_msrs[i].data,
1716 vmx->guest_msrs[i].mask);
33ed6329
AK		 1717}
1718
a9b21b62 1719static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1720{
a2fa3e9f 1721 if (!vmx->host_state.loaded)
33ed6329
AK		 1722 return;
1723
e1beb1d3 1724 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1725 vmx->host_state.loaded = 0;
c8770e7b
AK		 1726#ifdef CONFIG_X86_64
1727 if (is_long_mode(&vmx->vcpu))
1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1729#endif
152d3f2f 1730 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1731 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1732#ifdef CONFIG_X86_64
9581d442 1733 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1734#else
1735 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1736#endif
33ed6329 1737 }
0a77fe4c
AK		 1738 if (vmx->host_state.fs_reload_needed)
1739 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1740#ifdef CONFIG_X86_64
1741 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1742 loadsegment(ds, vmx->host_state.ds_sel);
1743 loadsegment(es, vmx->host_state.es_sel);
1744 }
b2da15ac 1745#endif
152d3f2f 1746 reload_tss();
44ea2b17 1747#ifdef CONFIG_X86_64
c8770e7b 1748 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1749#endif
b1a74bf8
SS		 1750 /*
1751 * If the FPU is not active (through the host task or
1752 * the guest vcpu), then restore the cr0.TS bit.
1753 */
1754 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1755 stts();
3444d7da 1756 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1757}
1758
a9b21b62
AK		 1759static void vmx_load_host_state(struct vcpu_vmx *vmx)
1760{
1761 preempt_disable();
1762 __vmx_load_host_state(vmx);
1763 preempt_enable();
1764}
1765
6aa8b732
AK		 1766/*
1767 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1768 * vcpu mutex is already taken.
1769 */
15ad7146 1770static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1771{
a2fa3e9f 1772 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1773 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1774
4610c9cc
DX		 1775 if (!vmm_exclusive)
1776 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1777 else if (vmx->loaded_vmcs->cpu != cpu)
1778 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1779
d462b819
NHE		 1780 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1781 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1782 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1783 }
1784
d462b819 1785 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1786 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1787 unsigned long sysenter_esp;
1788
a8eeb04a 1789 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1790 local_irq_disable();
8f536b76 1791 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1792
1793 /*
1794 * Read loaded_vmcs->cpu should be before fetching
1795 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1796 * See the comments in __loaded_vmcs_clear().
1797 */
1798 smp_rmb();
1799
d462b819
NHE		 1800 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1801 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1802 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1803 local_irq_enable();
1804
6aa8b732
AK		 1805 /*
1806 * Linux uses per-cpu TSS and GDT, so set these when switching
1807 * processors.
1808 */
d6e88aec 1809 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1810 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1811
1812 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1813 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1814 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1815 }
6aa8b732
AK		 1816}
1817
1818static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1819{
a9b21b62 1820 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1821 if (!vmm_exclusive) {
d462b819
NHE		 1822 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1823 vcpu->cpu = -1;
4610c9cc
DX		 1824 kvm_cpu_vmxoff();
1825 }
6aa8b732
AK		 1826}
1827
5fd86fcf
AK		 1828static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1829{
81231c69
AK		 1830 ulong cr0;
1831
5fd86fcf
AK		 1832 if (vcpu->fpu_active)
1833 return;
1834 vcpu->fpu_active = 1;
81231c69
AK		 1835 cr0 = vmcs_readl(GUEST_CR0);
1836 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1837 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1838 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1839 update_exception_bitmap(vcpu);
edcafe3c 1840 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1841 if (is_guest_mode(vcpu))
1842 vcpu->arch.cr0_guest_owned_bits &=
1843 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1844 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1845}
1846
edcafe3c
AK		 1847static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1848
fe3ef05c
NHE		 1849/*
1850 * Return the cr0 value that a nested guest would read. This is a combination
1851 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1852 * its hypervisor (cr0_read_shadow).
1853 */
1854static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1855{
1856 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1857 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1858}
1859static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1860{
1861 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1862 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1863}
1864
5fd86fcf
AK		 1865static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1866{
36cf24e0
NHE		 1867 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1868 * set this *before* calling this function.
1869 */
edcafe3c 1870 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1871 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1872 update_exception_bitmap(vcpu);
edcafe3c
AK		 1873 vcpu->arch.cr0_guest_owned_bits = 0;
1874 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1875 if (is_guest_mode(vcpu)) {
1876 /*
1877 * L1's specified read shadow might not contain the TS bit,
1878 * so now that we turned on shadowing of this bit, we need to
1879 * set this bit of the shadow. Like in nested_vmx_run we need
1880 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1881 * up-to-date here because we just decached cr0.TS (and we'll
1882 * only update vmcs12->guest_cr0 on nested exit).
1883 */
1884 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1885 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1886 (vcpu->arch.cr0 & X86_CR0_TS);
1887 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1888 } else
1889 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1890}
1891
6aa8b732
AK		 1892static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1893{
78ac8b47 1894 unsigned long rflags, save_rflags;
345dcaa8 1895
6de12732
AK		 1896 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1897 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1898 rflags = vmcs_readl(GUEST_RFLAGS);
1899 if (to_vmx(vcpu)->rmode.vm86_active) {
1900 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1901 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1902 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1903 }
1904 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1905 }
6de12732 1906 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1907}
1908
1909static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1910{
6de12732
AK		 1911 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1912 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1913 if (to_vmx(vcpu)->rmode.vm86_active) {
1914 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1915 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1916 }
6aa8b732
AK		 1917 vmcs_writel(GUEST_RFLAGS, rflags);
1918}
1919
2809f5d2
GC		 1920static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1921{
1922 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1923 int ret = 0;
1924
1925 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1926 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1927 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1928 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1929
1930 return ret & mask;
1931}
1932
1933static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1934{
1935 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1936 u32 interruptibility = interruptibility_old;
1937
1938 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1939
48005f64 1940 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1941 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1942 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1943 interruptibility |= GUEST_INTR_STATE_STI;
1944
1945 if ((interruptibility != interruptibility_old))
1946 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1947}
1948
6aa8b732
AK		 1949static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1950{
1951 unsigned long rip;
6aa8b732 1952
5fdbf976 1953 rip = kvm_rip_read(vcpu);
6aa8b732 1954 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1955 kvm_rip_write(vcpu, rip);
6aa8b732 1956
2809f5d2
GC		 1957 /* skipping an emulated instruction also counts */
1958 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1959}
1960
0b6ac343
NHE		 1961/*
1962 * KVM wants to inject page-faults which it got to the guest. This function
1963 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1964 */
e011c663 1965static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1966{
1967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1968
e011c663 1969 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1970 return 0;
1971
533558bc
JK		 1972 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1973 vmcs_read32(VM_EXIT_INTR_INFO),
1974 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1975 return 1;
1976}
1977
298101da 1978static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1979 bool has_error_code, u32 error_code,
1980 bool reinject)
298101da 1981{
77ab6db0 1982 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1983 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1984
e011c663
GN		 1985 if (!reinject && is_guest_mode(vcpu) &&
1986 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1987 return;
1988
8ab2d2e2 1989 if (has_error_code) {
77ab6db0 1990 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1991 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1992 }
77ab6db0 1993
7ffd92c5 1994 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1995 int inc_eip = 0;
1996 if (kvm_exception_is_soft(nr))
1997 inc_eip = vcpu->arch.event_exit_inst_len;
1998 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1999 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2000 return;
2001 }
2002
66fd3f7f
GN		 2003 if (kvm_exception_is_soft(nr)) {
2004 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2005 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2006 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2007 } else
2008 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2009
2010 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2011}
2012
4e47c7a6
SY		 2013static bool vmx_rdtscp_supported(void)
2014{
2015 return cpu_has_vmx_rdtscp();
2016}
2017
ad756a16
MJ		 2018static bool vmx_invpcid_supported(void)
2019{
2020 return cpu_has_vmx_invpcid() && enable_ept;
2021}
2022
a75beee6
ED		 2023/*
2024 * Swap MSR entry in host/guest MSR entry array.
2025 */
8b9cf98c 2026static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2027{
26bb0981 2028 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2029
2030 tmp = vmx->guest_msrs[to];
2031 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2032 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2033}
2034
8d14695f
YZ		 2035static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2036{
2037 unsigned long *msr_bitmap;
2038
2039 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2040 if (is_long_mode(vcpu))
2041 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2042 else
2043 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2044 } else {
2045 if (is_long_mode(vcpu))
2046 msr_bitmap = vmx_msr_bitmap_longmode;
2047 else
2048 msr_bitmap = vmx_msr_bitmap_legacy;
2049 }
2050
2051 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2052}
2053
e38aea3e
AK		 2054/*
2055 * Set up the vmcs to automatically save and restore system
2056 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2057 * mode, as fiddling with msrs is very expensive.
2058 */
8b9cf98c 2059static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2060{
26bb0981 2061 int save_nmsrs, index;
e38aea3e 2062
a75beee6
ED		 2063 save_nmsrs = 0;
2064#ifdef CONFIG_X86_64
8b9cf98c 2065 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2066 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2067 if (index >= 0)
8b9cf98c
RR		 2068 move_msr_up(vmx, index, save_nmsrs++);
2069 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2070 if (index >= 0)
8b9cf98c
RR		 2071 move_msr_up(vmx, index, save_nmsrs++);
2072 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2073 if (index >= 0)
8b9cf98c 2074 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2075 index = __find_msr_index(vmx, MSR_TSC_AUX);
2076 if (index >= 0 && vmx->rdtscp_enabled)
2077 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2078 /*
8c06585d 2079 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2080 * if efer.sce is enabled.
2081 */
8c06585d 2082 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2083 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2084 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2085 }
2086#endif
92c0d900
AK		 2087 index = __find_msr_index(vmx, MSR_EFER);
2088 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2089 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2090
26bb0981 2091 vmx->save_nmsrs = save_nmsrs;
5897297b 2092
8d14695f
YZ		 2093 if (cpu_has_vmx_msr_bitmap())
2094 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2095}
2096
6aa8b732
AK		 2097/*
2098 * reads and returns guest's timestamp counter "register"
2099 * guest_tsc = host_tsc + tsc_offset -- 21.3
2100 */
2101static u64 guest_read_tsc(void)
2102{
2103 u64 host_tsc, tsc_offset;
2104
2105 rdtscll(host_tsc);
2106 tsc_offset = vmcs_read64(TSC_OFFSET);
2107 return host_tsc + tsc_offset;
2108}
2109
d5c1785d
NHE		 2110/*
2111 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2112 * counter, even if a nested guest (L2) is currently running.
2113 */
886b470c 2114u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2115{
886b470c 2116 u64 tsc_offset;
d5c1785d 2117
d5c1785d
NHE		 2118 tsc_offset = is_guest_mode(vcpu) ?
2119 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2120 vmcs_read64(TSC_OFFSET);
2121 return host_tsc + tsc_offset;
2122}
2123
4051b188 2124/*
cc578287
ZA		 2125 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2126 * software catchup for faster rates on slower CPUs.
4051b188 2127 */
cc578287 2128static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2129{
cc578287
ZA		 2130 if (!scale)
2131 return;
2132
2133 if (user_tsc_khz > tsc_khz) {
2134 vcpu->arch.tsc_catchup = 1;
2135 vcpu->arch.tsc_always_catchup = 1;
2136 } else
2137 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2138}
2139
ba904635
WA		 2140static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2141{
2142 return vmcs_read64(TSC_OFFSET);
2143}
2144
6aa8b732 2145/*
99e3e30a 2146 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2147 */
99e3e30a 2148static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2149{
27fc51b2 2150 if (is_guest_mode(vcpu)) {
7991825b 2151 /*
27fc51b2
NHE		 2152 * We're here if L1 chose not to trap WRMSR to TSC. According
2153 * to the spec, this should set L1's TSC; The offset that L1
2154 * set for L2 remains unchanged, and still needs to be added
2155 * to the newly set TSC to get L2's TSC.
7991825b 2156 */
27fc51b2
NHE		 2157 struct vmcs12 *vmcs12;
2158 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2159 /* recalculate vmcs02.TSC_OFFSET: */
2160 vmcs12 = get_vmcs12(vcpu);
2161 vmcs_write64(TSC_OFFSET, offset +
2162 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2163 vmcs12->tsc_offset : 0));
2164 } else {
489223ed
YY		 2165 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2166 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2167 vmcs_write64(TSC_OFFSET, offset);
2168 }
6aa8b732
AK		 2169}
2170
f1e2b260 2171static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2172{
2173 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2174
e48672fa 2175 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2176 if (is_guest_mode(vcpu)) {
2177 /* Even when running L2, the adjustment needs to apply to L1 */
2178 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2179 } else
2180 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2181 offset + adjustment);
e48672fa
ZA		 2182}
2183
857e4099
JR		 2184static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2185{
2186 return target_tsc - native_read_tsc();
2187}
2188
801d3424
NHE		 2189static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2190{
2191 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2192 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2193}
2194
2195/*
2196 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2197 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2198 * all guests if the "nested" module option is off, and can also be disabled
2199 * for a single guest by disabling its VMX cpuid bit.
2200 */
2201static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2202{
2203 return nested && guest_cpuid_has_vmx(vcpu);
2204}
2205
b87a51ae
NHE		 2206/*
2207 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2208 * returned for the various VMX controls MSRs when nested VMX is enabled.
2209 * The same values should also be used to verify that vmcs12 control fields are
2210 * valid during nested entry from L1 to L2.
2211 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2212 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2213 * bit in the high half is on if the corresponding bit in the control field
2214 * may be on. See also vmx_control_verify().
2215 * TODO: allow these variables to be modified (downgraded) by module options
2216 * or other means.
2217 */
2218static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2219static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2220static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2221static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2222static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2223static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2224static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2225static __init void nested_vmx_setup_ctls_msrs(void)
2226{
2227 /*
2228 * Note that as a general rule, the high half of the MSRs (bits in
2229 * the control fields which may be 1) should be initialized by the
2230 * intersection of the underlying hardware's MSR (i.e., features which
2231 * can be supported) and the list of features we want to expose -
2232 * because they are known to be properly supported in our code.
2233 * Also, usually, the low half of the MSRs (bits which must be 1) can
2234 * be set to 0, meaning that L1 may turn off any of these bits. The
2235 * reason is that if one of these bits is necessary, it will appear
2236 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2237 * fields of vmcs01 and vmcs02, will turn these bits off - and
2238 * nested_vmx_exit_handled() will not pass related exits to L1.
2239 * These rules have exceptions below.
2240 */
2241
2242 /* pin-based controls */
eabeaacc
JK		 2243 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2244 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2245 /*
2246 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2247 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2248 */
eabeaacc
JK		 2249 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2250 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2251 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2252 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2253 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2254
33fb20c3
JK		 2255 /*
2256 * Exit controls
2257 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2258 * 17 must be 1.
2259 */
c0dfee58
ACL		 2260 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2261 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2262 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2263 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2264 nested_vmx_exit_ctls_high &=
b87a51ae 2265#ifdef CONFIG_X86_64
c0dfee58 2266 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2267#endif
7854cbca
ACL		 2268 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2269 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2270 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2271 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2272 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2273 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2274 }
8049d651 2275 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2276 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2277
2278 /* entry controls */
2279 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2280 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2281 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2282 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2283 nested_vmx_entry_ctls_high &=
57435349
JK		 2284#ifdef CONFIG_X86_64
2285 VM_ENTRY_IA32E_MODE |
2286#endif
2287 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2288 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2289 VM_ENTRY_LOAD_IA32_EFER);
57435349 2290
b87a51ae
NHE		 2291 /* cpu-based controls */
2292 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2293 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2294 nested_vmx_procbased_ctls_low = 0;
2295 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2296 CPU_BASED_VIRTUAL_INTR_PENDING |
2297 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2298 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2299 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2300 CPU_BASED_CR3_STORE_EXITING |
2301#ifdef CONFIG_X86_64
2302 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2303#endif
2304 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2305 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2306 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2307 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2309 /*
2310 * We can allow some features even when not supported by the
2311 * hardware. For example, L1 can specify an MSR bitmap - and we
2312 * can use it to avoid exits to L1 - even when L0 runs L2
2313 * without MSR bitmaps.
2314 */
2315 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2316
2317 /* secondary cpu-based controls */
2318 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2319 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2320 nested_vmx_secondary_ctls_low = 0;
2321 nested_vmx_secondary_ctls_high &=
d6851fbe 2322 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2323 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2324 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2325
afa61f75
NHE		 2326 if (enable_ept) {
2327 /* nested EPT: emulate EPT also to L1 */
2328 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2329 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2330 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2331 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2332 nested_vmx_ept_caps &= vmx_capability.ept;
2333 /*
2334 * Since invept is completely emulated we support both global
2335 * and context invalidation independent of what host cpu
2336 * supports
2337 */
2338 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2339 VMX_EPT_EXTENT_CONTEXT_BIT;
2340 } else
2341 nested_vmx_ept_caps = 0;
2342
c18911a2
JK		 2343 /* miscellaneous data */
2344 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2345 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2346 VMX_MISC_SAVE_EFER_LMA;
6dfacadd 2347 nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
c18911a2 2348 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2349}
2350
2351static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2352{
2353 /*
2354 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2355 */
2356 return ((control & high) | low) == control;
2357}
2358
2359static inline u64 vmx_control_msr(u32 low, u32 high)
2360{
2361 return low | ((u64)high << 32);
2362}
2363
cae50139 2364/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2365static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2366{
b87a51ae 2367 switch (msr_index) {
b87a51ae
NHE		 2368 case MSR_IA32_VMX_BASIC:
2369 /*
2370 * This MSR reports some information about VMX support. We
2371 * should return information about the VMX we emulate for the
2372 * guest, and the VMCS structure we give it - not about the
2373 * VMX support of the underlying hardware.
2374 */
2375 *pdata = VMCS12_REVISION |
2376 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2377 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2378 break;
2379 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2380 case MSR_IA32_VMX_PINBASED_CTLS:
2381 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2382 nested_vmx_pinbased_ctls_high);
2383 break;
2384 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2385 case MSR_IA32_VMX_PROCBASED_CTLS:
2386 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2387 nested_vmx_procbased_ctls_high);
2388 break;
2389 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2390 case MSR_IA32_VMX_EXIT_CTLS:
2391 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2392 nested_vmx_exit_ctls_high);
2393 break;
2394 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2395 case MSR_IA32_VMX_ENTRY_CTLS:
2396 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2397 nested_vmx_entry_ctls_high);
2398 break;
2399 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2400 *pdata = vmx_control_msr(nested_vmx_misc_low,
2401 nested_vmx_misc_high);
b87a51ae
NHE		 2402 break;
2403 /*
2404 * These MSRs specify bits which the guest must keep fixed (on or off)
2405 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2406 * We picked the standard core2 setting.
2407 */
2408#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2409#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2410 case MSR_IA32_VMX_CR0_FIXED0:
2411 *pdata = VMXON_CR0_ALWAYSON;
2412 break;
2413 case MSR_IA32_VMX_CR0_FIXED1:
2414 *pdata = -1ULL;
2415 break;
2416 case MSR_IA32_VMX_CR4_FIXED0:
2417 *pdata = VMXON_CR4_ALWAYSON;
2418 break;
2419 case MSR_IA32_VMX_CR4_FIXED1:
2420 *pdata = -1ULL;
2421 break;
2422 case MSR_IA32_VMX_VMCS_ENUM:
2423 *pdata = 0x1f;
2424 break;
2425 case MSR_IA32_VMX_PROCBASED_CTLS2:
2426 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2427 nested_vmx_secondary_ctls_high);
2428 break;
2429 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2430 /* Currently, no nested vpid support */
2431 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2432 break;
2433 default:
b87a51ae 2434 return 1;
b3897a49
NHE		 2435 }
2436
b87a51ae
NHE		 2437 return 0;
2438}
2439
6aa8b732
AK		 2440/*
2441 * Reads an msr value (of 'msr_index') into 'pdata'.
2442 * Returns 0 on success, non-0 otherwise.
2443 * Assumes vcpu_load() was already called.
2444 */
2445static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2446{
2447 u64 data;
26bb0981 2448 struct shared_msr_entry *msr;
6aa8b732
AK		 2449
2450 if (!pdata) {
2451 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2452 return -EINVAL;
2453 }
2454
2455 switch (msr_index) {
05b3e0c2 2456#ifdef CONFIG_X86_64
6aa8b732
AK		 2457 case MSR_FS_BASE:
2458 data = vmcs_readl(GUEST_FS_BASE);
2459 break;
2460 case MSR_GS_BASE:
2461 data = vmcs_readl(GUEST_GS_BASE);
2462 break;
44ea2b17
AK		 2463 case MSR_KERNEL_GS_BASE:
2464 vmx_load_host_state(to_vmx(vcpu));
2465 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2466 break;
26bb0981 2467#endif
6aa8b732 2468 case MSR_EFER:
3bab1f5d 2469 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2470 case MSR_IA32_TSC:
6aa8b732
AK		 2471 data = guest_read_tsc();
2472 break;
2473 case MSR_IA32_SYSENTER_CS:
2474 data = vmcs_read32(GUEST_SYSENTER_CS);
2475 break;
2476 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2477 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2478 break;
2479 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2480 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2481 break;
cae50139
JK		 2482 case MSR_IA32_FEATURE_CONTROL:
2483 if (!nested_vmx_allowed(vcpu))
2484 return 1;
2485 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2486 break;
2487 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2488 if (!nested_vmx_allowed(vcpu))
2489 return 1;
2490 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2491 case MSR_TSC_AUX:
2492 if (!to_vmx(vcpu)->rdtscp_enabled)
2493 return 1;
2494 /* Otherwise falls through */
6aa8b732 2495 default:
8b9cf98c 2496 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2497 if (msr) {
2498 data = msr->data;
2499 break;
6aa8b732 2500 }
3bab1f5d 2501 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2502 }
2503
2504 *pdata = data;
2505 return 0;
2506}
2507
cae50139
JK		 2508static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2509
6aa8b732
AK		 2510/*
2511 * Writes msr value into into the appropriate "register".
2512 * Returns 0 on success, non-0 otherwise.
2513 * Assumes vcpu_load() was already called.
2514 */
8fe8ab46 2515static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2516{
a2fa3e9f 2517 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2518 struct shared_msr_entry *msr;
2cc51560 2519 int ret = 0;
8fe8ab46
WA		 2520 u32 msr_index = msr_info->index;
2521 u64 data = msr_info->data;
2cc51560 2522
6aa8b732 2523 switch (msr_index) {
3bab1f5d 2524 case MSR_EFER:
8fe8ab46 2525 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2526 break;
16175a79 2527#ifdef CONFIG_X86_64
6aa8b732 2528 case MSR_FS_BASE:
2fb92db1 2529 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2530 vmcs_writel(GUEST_FS_BASE, data);
2531 break;
2532 case MSR_GS_BASE:
2fb92db1 2533 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2534 vmcs_writel(GUEST_GS_BASE, data);
2535 break;
44ea2b17
AK		 2536 case MSR_KERNEL_GS_BASE:
2537 vmx_load_host_state(vmx);
2538 vmx->msr_guest_kernel_gs_base = data;
2539 break;
6aa8b732
AK		 2540#endif
2541 case MSR_IA32_SYSENTER_CS:
2542 vmcs_write32(GUEST_SYSENTER_CS, data);
2543 break;
2544 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2545 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2546 break;
2547 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2548 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2549 break;
af24a4e4 2550 case MSR_IA32_TSC:
8fe8ab46 2551 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2552 break;
468d472f
SY		 2553 case MSR_IA32_CR_PAT:
2554 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2555 vmcs_write64(GUEST_IA32_PAT, data);
2556 vcpu->arch.pat = data;
2557 break;
2558 }
8fe8ab46 2559 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2560 break;
ba904635
WA		 2561 case MSR_IA32_TSC_ADJUST:
2562 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2563 break;
cae50139
JK		 2564 case MSR_IA32_FEATURE_CONTROL:
2565 if (!nested_vmx_allowed(vcpu) ||
2566 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2567 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2568 return 1;
2569 vmx->nested.msr_ia32_feature_control = data;
2570 if (msr_info->host_initiated && data == 0)
2571 vmx_leave_nested(vcpu);
2572 break;
2573 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2574 return 1; /* they are read-only */
4e47c7a6
SY		 2575 case MSR_TSC_AUX:
2576 if (!vmx->rdtscp_enabled)
2577 return 1;
2578 /* Check reserved bit, higher 32 bits should be zero */
2579 if ((data >> 32) != 0)
2580 return 1;
2581 /* Otherwise falls through */
6aa8b732 2582 default:
8b9cf98c 2583 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2584 if (msr) {
2585 msr->data = data;
2225fd56
AK		 2586 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2587 preempt_disable();
9ee73970
AK		 2588 kvm_set_shared_msr(msr->index, msr->data,
2589 msr->mask);
2225fd56
AK		 2590 preempt_enable();
2591 }
3bab1f5d 2592 break;
6aa8b732 2593 }
8fe8ab46 2594 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2595 }
2596
2cc51560 2597 return ret;
6aa8b732
AK		 2598}
2599
5fdbf976 2600static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2601{
5fdbf976
MT		 2602 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2603 switch (reg) {
2604 case VCPU_REGS_RSP:
2605 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2606 break;
2607 case VCPU_REGS_RIP:
2608 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2609 break;
6de4f3ad
AK		 2610 case VCPU_EXREG_PDPTR:
2611 if (enable_ept)
2612 ept_save_pdptrs(vcpu);
2613 break;
5fdbf976
MT		 2614 default:
2615 break;
2616 }
6aa8b732
AK		 2617}
2618
6aa8b732
AK		 2619static __init int cpu_has_kvm_support(void)
2620{
6210e37b 2621 return cpu_has_vmx();
6aa8b732
AK		 2622}
2623
2624static __init int vmx_disabled_by_bios(void)
2625{
2626 u64 msr;
2627
2628 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2629 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2630 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2631 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2632 && tboot_enabled())
2633 return 1;
23f3e991 2634 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2635 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2636 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2637 && !tboot_enabled()) {
2638 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2639 "activate TXT before enabling KVM\n");
cafd6659 2640 return 1;
f9335afe 2641 }
23f3e991
JC		 2642 /* launched w/o TXT and VMX disabled */
2643 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2644 && !tboot_enabled())
2645 return 1;
cafd6659
SW		 2646 }
2647
2648 return 0;
6aa8b732
AK		 2649}
2650
7725b894
DX		 2651static void kvm_cpu_vmxon(u64 addr)
2652{
2653 asm volatile (ASM_VMX_VMXON_RAX
2654 : : "a"(&addr), "m"(addr)
2655 : "memory", "cc");
2656}
2657
10474ae8 2658static int hardware_enable(void *garbage)
6aa8b732
AK		 2659{
2660 int cpu = raw_smp_processor_id();
2661 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2662 u64 old, test_bits;
6aa8b732 2663
10474ae8
AG		 2664 if (read_cr4() & X86_CR4_VMXE)
2665 return -EBUSY;
2666
d462b819 2667 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2668
2669 /*
2670 * Now we can enable the vmclear operation in kdump
2671 * since the loaded_vmcss_on_cpu list on this cpu
2672 * has been initialized.
2673 *
2674 * Though the cpu is not in VMX operation now, there
2675 * is no problem to enable the vmclear operation
2676 * for the loaded_vmcss_on_cpu list is empty!
2677 */
2678 crash_enable_local_vmclear(cpu);
2679
6aa8b732 2680 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2681
2682 test_bits = FEATURE_CONTROL_LOCKED;
2683 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2684 if (tboot_enabled())
2685 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2686
2687 if ((old & test_bits) != test_bits) {
6aa8b732 2688 /* enable and lock */
cafd6659
SW		 2689 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2690 }
66aee91a 2691 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2692
4610c9cc
DX		 2693 if (vmm_exclusive) {
2694 kvm_cpu_vmxon(phys_addr);
2695 ept_sync_global();
2696 }
10474ae8 2697
357d1226 2698 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2699
10474ae8 2700 return 0;
6aa8b732
AK		 2701}
2702
d462b819 2703static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2704{
2705 int cpu = raw_smp_processor_id();
d462b819 2706 struct loaded_vmcs *v, *n;
543e4243 2707
d462b819
NHE		 2708 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2709 loaded_vmcss_on_cpu_link)
2710 __loaded_vmcs_clear(v);
543e4243
AK		 2711}
2712
710ff4a8
EH		 2713
2714/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2715 * tricks.
2716 */
2717static void kvm_cpu_vmxoff(void)
6aa8b732 2718{
4ecac3fd 2719 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2720}
2721
710ff4a8
EH		 2722static void hardware_disable(void *garbage)
2723{
4610c9cc 2724 if (vmm_exclusive) {
d462b819 2725 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2726 kvm_cpu_vmxoff();
2727 }
7725b894 2728 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2729}
2730
1c3d14fe 2731static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2732 u32 msr, u32 *result)
1c3d14fe
YS		 2733{
2734 u32 vmx_msr_low, vmx_msr_high;
2735 u32 ctl = ctl_min | ctl_opt;
2736
2737 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2738
2739 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2740 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2741
2742 /* Ensure minimum (required) set of control bits are supported. */
2743 if (ctl_min & ~ctl)
002c7f7c 2744 return -EIO;
1c3d14fe
YS		 2745
2746 *result = ctl;
2747 return 0;
2748}
2749
110312c8
AK		 2750static __init bool allow_1_setting(u32 msr, u32 ctl)
2751{
2752 u32 vmx_msr_low, vmx_msr_high;
2753
2754 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2755 return vmx_msr_high & ctl;
2756}
2757
002c7f7c 2758static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2759{
2760 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2761 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2762 u32 _pin_based_exec_control = 0;
2763 u32 _cpu_based_exec_control = 0;
f78e0e2e 2764 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2765 u32 _vmexit_control = 0;
2766 u32 _vmentry_control = 0;
2767
10166744 2768 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2769#ifdef CONFIG_X86_64
2770 CPU_BASED_CR8_LOAD_EXITING |
2771 CPU_BASED_CR8_STORE_EXITING |
2772#endif
d56f546d
SY		 2773 CPU_BASED_CR3_LOAD_EXITING |
2774 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2775 CPU_BASED_USE_IO_BITMAPS |
2776 CPU_BASED_MOV_DR_EXITING |
a7052897 2777 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2778 CPU_BASED_MWAIT_EXITING |
2779 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2780 CPU_BASED_INVLPG_EXITING |
2781 CPU_BASED_RDPMC_EXITING;
443381a8 2782
f78e0e2e 2783 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2784 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2785 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2786 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2787 &_cpu_based_exec_control) < 0)
002c7f7c 2788 return -EIO;
6e5d865c
YS		 2789#ifdef CONFIG_X86_64
2790 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2791 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2792 ~CPU_BASED_CR8_STORE_EXITING;
2793#endif
f78e0e2e 2794 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2795 min2 = 0;
2796 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2797 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2798 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2799 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2800 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2801 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2802 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2803 SECONDARY_EXEC_RDTSCP |
83d4c286 2804 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2805 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2806 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2807 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2808 if (adjust_vmx_controls(min2, opt2,
2809 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2810 &_cpu_based_2nd_exec_control) < 0)
2811 return -EIO;
2812 }
2813#ifndef CONFIG_X86_64
2814 if (!(_cpu_based_2nd_exec_control &
2815 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2816 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2817#endif
83d4c286
YZ		 2818
2819 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2820 _cpu_based_2nd_exec_control &= ~(
8d14695f 2821 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2822 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2823 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2824
d56f546d 2825 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2826 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2827 enabled */
5fff7d27
GN		 2828 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2829 CPU_BASED_CR3_STORE_EXITING |
2830 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2831 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2832 vmx_capability.ept, vmx_capability.vpid);
2833 }
1c3d14fe
YS		 2834
2835 min = 0;
2836#ifdef CONFIG_X86_64
2837 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2838#endif
a547c6db
YZ		 2839 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2840 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2841 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2842 &_vmexit_control) < 0)
002c7f7c 2843 return -EIO;
1c3d14fe 2844
01e439be
YZ		 2845 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2846 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2847 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2848 &_pin_based_exec_control) < 0)
2849 return -EIO;
2850
2851 if (!(_cpu_based_2nd_exec_control &
2852 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2853 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2854 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2855
468d472f
SY		 2856 min = 0;
2857 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2858 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2859 &_vmentry_control) < 0)
002c7f7c 2860 return -EIO;
6aa8b732 2861
c68876fd 2862 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2863
2864 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2865 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2866 return -EIO;
1c3d14fe
YS		 2867
2868#ifdef CONFIG_X86_64
2869 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2870 if (vmx_msr_high & (1u<<16))
002c7f7c 2871 return -EIO;
1c3d14fe
YS		 2872#endif
2873
2874 /* Require Write-Back (WB) memory type for VMCS accesses. */
2875 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2876 return -EIO;
1c3d14fe 2877
002c7f7c
YS		 2878 vmcs_conf->size = vmx_msr_high & 0x1fff;
2879 vmcs_conf->order = get_order(vmcs_config.size);
2880 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2881
002c7f7c
YS		 2882 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2883 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2884 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2885 vmcs_conf->vmexit_ctrl = _vmexit_control;
2886 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2887
110312c8
AK		 2888 cpu_has_load_ia32_efer =
2889 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2890 VM_ENTRY_LOAD_IA32_EFER)
2891 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2892 VM_EXIT_LOAD_IA32_EFER);
2893
8bf00a52
GN		 2894 cpu_has_load_perf_global_ctrl =
2895 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2896 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2897 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2898 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2899
2900 /*
2901 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2902 * but due to arrata below it can't be used. Workaround is to use
2903 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2904 *
2905 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2906 *
2907 * AAK155 (model 26)
2908 * AAP115 (model 30)
2909 * AAT100 (model 37)
2910 * BC86,AAY89,BD102 (model 44)
2911 * BA97 (model 46)
2912 *
2913 */
2914 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2915 switch (boot_cpu_data.x86_model) {
2916 case 26:
2917 case 30:
2918 case 37:
2919 case 44:
2920 case 46:
2921 cpu_has_load_perf_global_ctrl = false;
2922 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2923 "does not work properly. Using workaround\n");
2924 break;
2925 default:
2926 break;
2927 }
2928 }
2929
1c3d14fe 2930 return 0;
c68876fd 2931}
6aa8b732
AK		 2932
2933static struct vmcs *alloc_vmcs_cpu(int cpu)
2934{
2935 int node = cpu_to_node(cpu);
2936 struct page *pages;
2937 struct vmcs *vmcs;
2938
6484eb3e 2939 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2940 if (!pages)
2941 return NULL;
2942 vmcs = page_address(pages);
1c3d14fe
YS		 2943 memset(vmcs, 0, vmcs_config.size);
2944 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2945 return vmcs;
2946}
2947
2948static struct vmcs *alloc_vmcs(void)
2949{
d3b2c338 2950 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2951}
2952
2953static void free_vmcs(struct vmcs *vmcs)
2954{
1c3d14fe 2955 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2956}
2957
d462b819
NHE		 2958/*
2959 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2960 */
2961static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2962{
2963 if (!loaded_vmcs->vmcs)
2964 return;
2965 loaded_vmcs_clear(loaded_vmcs);
2966 free_vmcs(loaded_vmcs->vmcs);
2967 loaded_vmcs->vmcs = NULL;
2968}
2969
39959588 2970static void free_kvm_area(void)
6aa8b732
AK		 2971{
2972 int cpu;
2973
3230bb47 2974 for_each_possible_cpu(cpu) {
6aa8b732 2975 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2976 per_cpu(vmxarea, cpu) = NULL;
2977 }
6aa8b732
AK		 2978}
2979
6aa8b732
AK		 2980static __init int alloc_kvm_area(void)
2981{
2982 int cpu;
2983
3230bb47 2984 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2985 struct vmcs *vmcs;
2986
2987 vmcs = alloc_vmcs_cpu(cpu);
2988 if (!vmcs) {
2989 free_kvm_area();
2990 return -ENOMEM;
2991 }
2992
2993 per_cpu(vmxarea, cpu) = vmcs;
2994 }
2995 return 0;
2996}
2997
2998static __init int hardware_setup(void)
2999{
002c7f7c
YS		 3000 if (setup_vmcs_config(&vmcs_config) < 0)
3001 return -EIO;
50a37eb4
JR		 3002
3003 if (boot_cpu_has(X86_FEATURE_NX))
3004 kvm_enable_efer_bits(EFER_NX);
3005
93ba03c2
SY		 3006 if (!cpu_has_vmx_vpid())
3007 enable_vpid = 0;
abc4fc58
AG		 3008 if (!cpu_has_vmx_shadow_vmcs())
3009 enable_shadow_vmcs = 0;
93ba03c2 3010
4bc9b982
SY		 3011 if (!cpu_has_vmx_ept() ||
3012 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3013 enable_ept = 0;
3a624e29 3014 enable_unrestricted_guest = 0;
83c3a331 3015 enable_ept_ad_bits = 0;
3a624e29
NK		 3016 }
3017
83c3a331
XH		 3018 if (!cpu_has_vmx_ept_ad_bits())
3019 enable_ept_ad_bits = 0;
3020
3a624e29
NK		 3021 if (!cpu_has_vmx_unrestricted_guest())
3022 enable_unrestricted_guest = 0;
93ba03c2
SY		 3023
3024 if (!cpu_has_vmx_flexpriority())
3025 flexpriority_enabled = 0;
3026
95ba8273
GN		 3027 if (!cpu_has_vmx_tpr_shadow())
3028 kvm_x86_ops->update_cr8_intercept = NULL;
3029
54dee993
MT		 3030 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3031 kvm_disable_largepages();
3032
4b8d54f9
ZE		 3033 if (!cpu_has_vmx_ple())
3034 ple_gap = 0;
3035
01e439be
YZ		 3036 if (!cpu_has_vmx_apicv())
3037 enable_apicv = 0;
c7c9c56c 3038
01e439be 3039 if (enable_apicv)
c7c9c56c 3040 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3041 else {
c7c9c56c 3042 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3043 kvm_x86_ops->deliver_posted_interrupt = NULL;
3044 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3045 }
83d4c286 3046
b87a51ae
NHE		 3047 if (nested)
3048 nested_vmx_setup_ctls_msrs();
3049
6aa8b732
AK		 3050 return alloc_kvm_area();
3051}
3052
3053static __exit void hardware_unsetup(void)
3054{
3055 free_kvm_area();
3056}
3057
14168786
GN		 3058static bool emulation_required(struct kvm_vcpu *vcpu)
3059{
3060 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3061}
3062
91b0aa2c 3063static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3064 struct kvm_segment *save)
6aa8b732 3065{
d99e4152
GN		 3066 if (!emulate_invalid_guest_state) {
3067 /*
3068 * CS and SS RPL should be equal during guest entry according
3069 * to VMX spec, but in reality it is not always so. Since vcpu
3070 * is in the middle of the transition from real mode to
3071 * protected mode it is safe to assume that RPL 0 is a good
3072 * default value.
3073 */
3074 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3075 save->selector &= ~SELECTOR_RPL_MASK;
3076 save->dpl = save->selector & SELECTOR_RPL_MASK;
3077 save->s = 1;
6aa8b732 3078 }
d99e4152 3079 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3080}
3081
3082static void enter_pmode(struct kvm_vcpu *vcpu)
3083{
3084 unsigned long flags;
a89a8fb9 3085 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3086
d99e4152
GN		 3087 /*
3088 * Update real mode segment cache. It may be not up-to-date if sement
3089 * register was written while vcpu was in a guest mode.
3090 */
3091 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3092 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3093 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3094 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3095 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3096 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3097
7ffd92c5 3098 vmx->rmode.vm86_active = 0;
6aa8b732 3099
2fb92db1
AK		 3100 vmx_segment_cache_clear(vmx);
3101
f5f7b2fe 3102 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3103
3104 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3105 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3106 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3107 vmcs_writel(GUEST_RFLAGS, flags);
3108
66aee91a
RR		 3109 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3110 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3111
3112 update_exception_bitmap(vcpu);
3113
91b0aa2c
GN		 3114 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3115 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3116 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3117 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3118 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3119 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3120
3121 /* CPL is always 0 when CPU enters protected mode */
3122 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3123 vmx->cpl = 0;
6aa8b732
AK		 3124}
3125
f5f7b2fe 3126static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3127{
772e0318 3128 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3129 struct kvm_segment var = *save;
3130
3131 var.dpl = 0x3;
3132 if (seg == VCPU_SREG_CS)
3133 var.type = 0x3;
3134
3135 if (!emulate_invalid_guest_state) {
3136 var.selector = var.base >> 4;
3137 var.base = var.base & 0xffff0;
3138 var.limit = 0xffff;
3139 var.g = 0;
3140 var.db = 0;
3141 var.present = 1;
3142 var.s = 1;
3143 var.l = 0;
3144 var.unusable = 0;
3145 var.type = 0x3;
3146 var.avl = 0;
3147 if (save->base & 0xf)
3148 printk_once(KERN_WARNING "kvm: segment base is not "
3149 "paragraph aligned when entering "
3150 "protected mode (seg=%d)", seg);
3151 }
6aa8b732 3152
d99e4152
GN		 3153 vmcs_write16(sf->selector, var.selector);
3154 vmcs_write32(sf->base, var.base);
3155 vmcs_write32(sf->limit, var.limit);
3156 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3157}
3158
3159static void enter_rmode(struct kvm_vcpu *vcpu)
3160{
3161 unsigned long flags;
a89a8fb9 3162 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3163
f5f7b2fe
AK		 3164 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3165 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3166 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3167 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3168 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3169 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3170 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3171
7ffd92c5 3172 vmx->rmode.vm86_active = 1;
6aa8b732 3173
776e58ea
GN		 3174 /*
3175 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3176 * vcpu. Warn the user that an update is overdue.
776e58ea 3177 */
4918c6ca 3178 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3179 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3180 "called before entering vcpu\n");
776e58ea 3181
2fb92db1
AK		 3182 vmx_segment_cache_clear(vmx);
3183
4918c6ca 3184 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3185 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3186 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3187
3188 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3189 vmx->rmode.save_rflags = flags;
6aa8b732 3190
053de044 3191 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3192
3193 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3194 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3195 update_exception_bitmap(vcpu);
3196
d99e4152
GN		 3197 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3198 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3199 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3200 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3201 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3202 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3203
8668a3c4 3204 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3205}
3206
401d10de
AS		 3207static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3208{
3209 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3210 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3211
3212 if (!msr)
3213 return;
401d10de 3214
44ea2b17
AK		 3215 /*
3216 * Force kernel_gs_base reloading before EFER changes, as control
3217 * of this msr depends on is_long_mode().
3218 */
3219 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3220 vcpu->arch.efer = efer;
401d10de 3221 if (efer & EFER_LMA) {
2961e876 3222 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3223 msr->data = efer;
3224 } else {
2961e876 3225 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3226
3227 msr->data = efer & ~EFER_LME;
3228 }
3229 setup_msrs(vmx);
3230}
3231
05b3e0c2 3232#ifdef CONFIG_X86_64
6aa8b732
AK		 3233
3234static void enter_lmode(struct kvm_vcpu *vcpu)
3235{
3236 u32 guest_tr_ar;
3237
2fb92db1
AK		 3238 vmx_segment_cache_clear(to_vmx(vcpu));
3239
6aa8b732
AK		 3240 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3241 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3242 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3243 __func__);
6aa8b732
AK		 3244 vmcs_write32(GUEST_TR_AR_BYTES,
3245 (guest_tr_ar & ~AR_TYPE_MASK)
3246 | AR_TYPE_BUSY_64_TSS);
3247 }
da38f438 3248 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3249}
3250
3251static void exit_lmode(struct kvm_vcpu *vcpu)
3252{
2961e876 3253 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3254 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3255}
3256
3257#endif
3258
2384d2b3
SY		 3259static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3260{
b9d762fa 3261 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3262 if (enable_ept) {
3263 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3264 return;
4e1096d2 3265 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3266 }
2384d2b3
SY		 3267}
3268
e8467fda
AK		 3269static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3270{
3271 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3272
3273 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3274 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3275}
3276
aff48baa
AK		 3277static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3278{
3279 if (enable_ept && is_paging(vcpu))
3280 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3281 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3282}
3283
25c4c276 3284static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3285{
fc78f519
AK		 3286 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3287
3288 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3289 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3290}
3291
1439442c
SY		 3292static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3293{
d0d538b9
GN		 3294 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3295
6de4f3ad
AK		 3296 if (!test_bit(VCPU_EXREG_PDPTR,
3297 (unsigned long *)&vcpu->arch.regs_dirty))
3298 return;
3299
1439442c 3300 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3301 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3302 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3303 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3304 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3305 }
3306}
3307
8f5d549f
AK		 3308static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3309{
d0d538b9
GN		 3310 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3311
8f5d549f 3312 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3313 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3314 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3315 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3316 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3317 }
6de4f3ad
AK		 3318
3319 __set_bit(VCPU_EXREG_PDPTR,
3320 (unsigned long *)&vcpu->arch.regs_avail);
3321 __set_bit(VCPU_EXREG_PDPTR,
3322 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3323}
3324
5e1746d6 3325static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3326
3327static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3328 unsigned long cr0,
3329 struct kvm_vcpu *vcpu)
3330{
5233dd51
MT		 3331 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3332 vmx_decache_cr3(vcpu);
1439442c
SY		 3333 if (!(cr0 & X86_CR0_PG)) {
3334 /* From paging/starting to nonpaging */
3335 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3336 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3337 (CPU_BASED_CR3_LOAD_EXITING |
3338 CPU_BASED_CR3_STORE_EXITING));
3339 vcpu->arch.cr0 = cr0;
fc78f519 3340 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3341 } else if (!is_paging(vcpu)) {
3342 /* From nonpaging to paging */
3343 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3344 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3345 ~(CPU_BASED_CR3_LOAD_EXITING |
3346 CPU_BASED_CR3_STORE_EXITING));
3347 vcpu->arch.cr0 = cr0;
fc78f519 3348 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3349 }
95eb84a7
SY		 3350
3351 if (!(cr0 & X86_CR0_WP))
3352 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3353}
3354
6aa8b732
AK		 3355static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3356{
7ffd92c5 3357 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3358 unsigned long hw_cr0;
3359
5037878e 3360 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3361 if (enable_unrestricted_guest)
5037878e 3362 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3363 else {
5037878e 3364 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3365
218e763f
GN		 3366 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3367 enter_pmode(vcpu);
6aa8b732 3368
218e763f
GN		 3369 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3370 enter_rmode(vcpu);
3371 }
6aa8b732 3372
05b3e0c2 3373#ifdef CONFIG_X86_64
f6801dff 3374 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3375 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3376 enter_lmode(vcpu);
707d92fa 3377 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3378 exit_lmode(vcpu);
3379 }
3380#endif
3381
089d034e 3382 if (enable_ept)
1439442c
SY		 3383 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3384
02daab21 3385 if (!vcpu->fpu_active)
81231c69 3386 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3387
6aa8b732 3388 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3389 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3390 vcpu->arch.cr0 = cr0;
14168786
GN		 3391
3392 /* depends on vcpu->arch.cr0 to be set to a new value */
3393 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3394}
3395
1439442c
SY		 3396static u64 construct_eptp(unsigned long root_hpa)
3397{
3398 u64 eptp;
3399
3400 /* TODO write the value reading from MSR */
3401 eptp = VMX_EPT_DEFAULT_MT |
3402 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3403 if (enable_ept_ad_bits)
3404 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3405 eptp |= (root_hpa & PAGE_MASK);
3406
3407 return eptp;
3408}
3409
6aa8b732
AK		 3410static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3411{
1439442c
SY		 3412 unsigned long guest_cr3;
3413 u64 eptp;
3414
3415 guest_cr3 = cr3;
089d034e 3416 if (enable_ept) {
1439442c
SY		 3417 eptp = construct_eptp(cr3);
3418 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3419 if (is_paging(vcpu) || is_guest_mode(vcpu))
3420 guest_cr3 = kvm_read_cr3(vcpu);
3421 else
3422 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3423 ept_load_pdptrs(vcpu);
1439442c
SY		 3424 }
3425
2384d2b3 3426 vmx_flush_tlb(vcpu);
1439442c 3427 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3428}
3429
5e1746d6 3430static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3431{
7ffd92c5 3432 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3433 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3434
5e1746d6
NHE		 3435 if (cr4 & X86_CR4_VMXE) {
3436 /*
3437 * To use VMXON (and later other VMX instructions), a guest
3438 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3439 * So basically the check on whether to allow nested VMX
3440 * is here.
3441 */
3442 if (!nested_vmx_allowed(vcpu))
3443 return 1;
1a0d74e6
JK		 3444 }
3445 if (to_vmx(vcpu)->nested.vmxon &&
3446 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3447 return 1;
3448
ad312c7c 3449 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3450 if (enable_ept) {
3451 if (!is_paging(vcpu)) {
3452 hw_cr4 &= ~X86_CR4_PAE;
3453 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3454 /*
3455 * SMEP is disabled if CPU is in non-paging mode in
3456 * hardware. However KVM always uses paging mode to
3457 * emulate guest non-paging mode with TDP.
3458 * To emulate this behavior, SMEP needs to be manually
3459 * disabled when guest switches to non-paging mode.
3460 */
3461 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3462 } else if (!(cr4 & X86_CR4_PAE)) {
3463 hw_cr4 &= ~X86_CR4_PAE;
3464 }
3465 }
1439442c
SY		 3466
3467 vmcs_writel(CR4_READ_SHADOW, cr4);
3468 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3469 return 0;
6aa8b732
AK		 3470}
3471
6aa8b732
AK		 3472static void vmx_get_segment(struct kvm_vcpu *vcpu,
3473 struct kvm_segment *var, int seg)
3474{
a9179499 3475 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3476 u32 ar;
3477
c6ad1153 3478 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3479 *var = vmx->rmode.segs[seg];
a9179499 3480 if (seg == VCPU_SREG_TR
2fb92db1 3481 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3482 return;
1390a28b
AK		 3483 var->base = vmx_read_guest_seg_base(vmx, seg);
3484 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3485 return;
a9179499 3486 }
2fb92db1
AK		 3487 var->base = vmx_read_guest_seg_base(vmx, seg);
3488 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3489 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3490 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3491 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3492 var->type = ar & 15;
3493 var->s = (ar >> 4) & 1;
3494 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3495 /*
3496 * Some userspaces do not preserve unusable property. Since usable
3497 * segment has to be present according to VMX spec we can use present
3498 * property to amend userspace bug by making unusable segment always
3499 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3500 * segment as unusable.
3501 */
3502 var->present = !var->unusable;
6aa8b732
AK		 3503 var->avl = (ar >> 12) & 1;
3504 var->l = (ar >> 13) & 1;
3505 var->db = (ar >> 14) & 1;
3506 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3507}
3508
a9179499
AK		 3509static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3510{
a9179499
AK		 3511 struct kvm_segment s;
3512
3513 if (to_vmx(vcpu)->rmode.vm86_active) {
3514 vmx_get_segment(vcpu, &s, seg);
3515 return s.base;
3516 }
2fb92db1 3517 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3518}
3519
b09408d0 3520static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3521{
b09408d0
MT		 3522 struct vcpu_vmx *vmx = to_vmx(vcpu);
3523
3eeb3288 3524 if (!is_protmode(vcpu))
2e4d2653
IE		 3525 return 0;
3526
f4c63e5d
AK		 3527 if (!is_long_mode(vcpu)
3528 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3529 return 3;
3530
69c73028
AK		 3531 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3532 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3533 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3534 }
d881e6f6
AK		 3535
3536 return vmx->cpl;
69c73028
AK		 3537}
3538
3539
653e3108 3540static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3541{
6aa8b732
AK		 3542 u32 ar;
3543
f0495f9b 3544 if (var->unusable || !var->present)
6aa8b732
AK		 3545 ar = 1 << 16;
3546 else {
3547 ar = var->type & 15;
3548 ar |= (var->s & 1) << 4;
3549 ar |= (var->dpl & 3) << 5;
3550 ar |= (var->present & 1) << 7;
3551 ar |= (var->avl & 1) << 12;
3552 ar |= (var->l & 1) << 13;
3553 ar |= (var->db & 1) << 14;
3554 ar |= (var->g & 1) << 15;
3555 }
653e3108
AK		 3556
3557 return ar;
3558}
3559
3560static void vmx_set_segment(struct kvm_vcpu *vcpu,
3561 struct kvm_segment *var, int seg)
3562{
7ffd92c5 3563 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3564 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3565
2fb92db1 3566 vmx_segment_cache_clear(vmx);
2f143240
GN		 3567 if (seg == VCPU_SREG_CS)
3568 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3569
1ecd50a9
GN		 3570 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3571 vmx->rmode.segs[seg] = *var;
3572 if (seg == VCPU_SREG_TR)
3573 vmcs_write16(sf->selector, var->selector);
3574 else if (var->s)
3575 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3576 goto out;
653e3108 3577 }
1ecd50a9 3578
653e3108
AK		 3579 vmcs_writel(sf->base, var->base);
3580 vmcs_write32(sf->limit, var->limit);
3581 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3582
3583 /*
3584 * Fix the "Accessed" bit in AR field of segment registers for older
3585 * qemu binaries.
3586 * IA32 arch specifies that at the time of processor reset the
3587 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3588 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3589 * state vmexit when "unrestricted guest" mode is turned on.
3590 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3591 * tree. Newer qemu binaries with that qemu fix would not need this
3592 * kvm hack.
3593 */
3594 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3595 var->type |= 0x1; /* Accessed */
3a624e29 3596
f924d66d 3597 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3598
3599out:
14168786 3600 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3601}
3602
6aa8b732
AK		 3603static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3604{
2fb92db1 3605 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3606
3607 *db = (ar >> 14) & 1;
3608 *l = (ar >> 13) & 1;
3609}
3610
89a27f4d 3611static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3612{
89a27f4d
GN		 3613 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3614 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3615}
3616
89a27f4d 3617static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3618{
89a27f4d
GN		 3619 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3620 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3621}
3622
89a27f4d 3623static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3624{
89a27f4d
GN		 3625 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3626 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3627}
3628
89a27f4d 3629static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3630{
89a27f4d
GN		 3631 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3632 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3633}
3634
648dfaa7
MG		 3635static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3636{
3637 struct kvm_segment var;
3638 u32 ar;
3639
3640 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3641 var.dpl = 0x3;
0647f4aa
GN		 3642 if (seg == VCPU_SREG_CS)
3643 var.type = 0x3;
648dfaa7
MG		 3644 ar = vmx_segment_access_rights(&var);
3645
3646 if (var.base != (var.selector << 4))
3647 return false;
89efbed0 3648 if (var.limit != 0xffff)
648dfaa7 3649 return false;
07f42f5f 3650 if (ar != 0xf3)
648dfaa7
MG		 3651 return false;
3652
3653 return true;
3654}
3655
3656static bool code_segment_valid(struct kvm_vcpu *vcpu)
3657{
3658 struct kvm_segment cs;
3659 unsigned int cs_rpl;
3660
3661 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3662 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3663
1872a3f4
AK		 3664 if (cs.unusable)
3665 return false;
648dfaa7
MG		 3666 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3667 return false;
3668 if (!cs.s)
3669 return false;
1872a3f4 3670 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3671 if (cs.dpl > cs_rpl)
3672 return false;
1872a3f4 3673 } else {
648dfaa7
MG		 3674 if (cs.dpl != cs_rpl)
3675 return false;
3676 }
3677 if (!cs.present)
3678 return false;
3679
3680 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3681 return true;
3682}
3683
3684static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3685{
3686 struct kvm_segment ss;
3687 unsigned int ss_rpl;
3688
3689 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3690 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3691
1872a3f4
AK		 3692 if (ss.unusable)
3693 return true;
3694 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3695 return false;
3696 if (!ss.s)
3697 return false;
3698 if (ss.dpl != ss_rpl) /* DPL != RPL */
3699 return false;
3700 if (!ss.present)
3701 return false;
3702
3703 return true;
3704}
3705
3706static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3707{
3708 struct kvm_segment var;
3709 unsigned int rpl;
3710
3711 vmx_get_segment(vcpu, &var, seg);
3712 rpl = var.selector & SELECTOR_RPL_MASK;
3713
1872a3f4
AK		 3714 if (var.unusable)
3715 return true;
648dfaa7
MG		 3716 if (!var.s)
3717 return false;
3718 if (!var.present)
3719 return false;
3720 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3721 if (var.dpl < rpl) /* DPL < RPL */
3722 return false;
3723 }
3724
3725 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3726 * rights flags
3727 */
3728 return true;
3729}
3730
3731static bool tr_valid(struct kvm_vcpu *vcpu)
3732{
3733 struct kvm_segment tr;
3734
3735 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3736
1872a3f4
AK		 3737 if (tr.unusable)
3738 return false;
648dfaa7
MG		 3739 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3740 return false;
1872a3f4 3741 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3742 return false;
3743 if (!tr.present)
3744 return false;
3745
3746 return true;
3747}
3748
3749static bool ldtr_valid(struct kvm_vcpu *vcpu)
3750{
3751 struct kvm_segment ldtr;
3752
3753 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3754
1872a3f4
AK		 3755 if (ldtr.unusable)
3756 return true;
648dfaa7
MG		 3757 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3758 return false;
3759 if (ldtr.type != 2)
3760 return false;
3761 if (!ldtr.present)
3762 return false;
3763
3764 return true;
3765}
3766
3767static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3768{
3769 struct kvm_segment cs, ss;
3770
3771 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3772 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3773
3774 return ((cs.selector & SELECTOR_RPL_MASK) ==
3775 (ss.selector & SELECTOR_RPL_MASK));
3776}
3777
3778/*
3779 * Check if guest state is valid. Returns true if valid, false if
3780 * not.
3781 * We assume that registers are always usable
3782 */
3783static bool guest_state_valid(struct kvm_vcpu *vcpu)
3784{
c5e97c80
GN		 3785 if (enable_unrestricted_guest)
3786 return true;
3787
648dfaa7 3788 /* real mode guest state checks */
f13882d8 3789 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3790 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3791 return false;
3792 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3793 return false;
3794 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3795 return false;
3796 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3797 return false;
3798 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3799 return false;
3800 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3801 return false;
3802 } else {
3803 /* protected mode guest state checks */
3804 if (!cs_ss_rpl_check(vcpu))
3805 return false;
3806 if (!code_segment_valid(vcpu))
3807 return false;
3808 if (!stack_segment_valid(vcpu))
3809 return false;
3810 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3811 return false;
3812 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3813 return false;
3814 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3815 return false;
3816 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3817 return false;
3818 if (!tr_valid(vcpu))
3819 return false;
3820 if (!ldtr_valid(vcpu))
3821 return false;
3822 }
3823 /* TODO:
3824 * - Add checks on RIP
3825 * - Add checks on RFLAGS
3826 */
3827
3828 return true;
3829}
3830
d77c26fc 3831static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3832{
40dcaa9f 3833 gfn_t fn;
195aefde 3834 u16 data = 0;
40dcaa9f 3835 int r, idx, ret = 0;
6aa8b732 3836
40dcaa9f 3837 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3838 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3839 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3840 if (r < 0)
10589a46 3841 goto out;
195aefde 3842 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3843 r = kvm_write_guest_page(kvm, fn++, &data,
3844 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3845 if (r < 0)
10589a46 3846 goto out;
195aefde
IE		 3847 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3848 if (r < 0)
10589a46 3849 goto out;
195aefde
IE		 3850 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3851 if (r < 0)
10589a46 3852 goto out;
195aefde 3853 data = ~0;
10589a46
MT		 3854 r = kvm_write_guest_page(kvm, fn, &data,
3855 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3856 sizeof(u8));
195aefde 3857 if (r < 0)
10589a46
MT		 3858 goto out;
3859
3860 ret = 1;
3861out:
40dcaa9f 3862 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3863 return ret;
6aa8b732
AK		 3864}
3865
b7ebfb05
SY		 3866static int init_rmode_identity_map(struct kvm *kvm)
3867{
40dcaa9f 3868 int i, idx, r, ret;
b7ebfb05
SY		 3869 pfn_t identity_map_pfn;
3870 u32 tmp;
3871
089d034e 3872 if (!enable_ept)
b7ebfb05
SY		 3873 return 1;
3874 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3875 printk(KERN_ERR "EPT: identity-mapping pagetable "
3876 "haven't been allocated!\n");
3877 return 0;
3878 }
3879 if (likely(kvm->arch.ept_identity_pagetable_done))
3880 return 1;
3881 ret = 0;
b927a3ce 3882 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3883 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3884 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3885 if (r < 0)
3886 goto out;
3887 /* Set up identity-mapping pagetable for EPT in real mode */
3888 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3889 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3890 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3891 r = kvm_write_guest_page(kvm, identity_map_pfn,
3892 &tmp, i * sizeof(tmp), sizeof(tmp));
3893 if (r < 0)
3894 goto out;
3895 }
3896 kvm->arch.ept_identity_pagetable_done = true;
3897 ret = 1;
3898out:
40dcaa9f 3899 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3900 return ret;
3901}
3902
6aa8b732
AK		 3903static void seg_setup(int seg)
3904{
772e0318 3905 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3906 unsigned int ar;
6aa8b732
AK		 3907
3908 vmcs_write16(sf->selector, 0);
3909 vmcs_writel(sf->base, 0);
3910 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3911 ar = 0x93;
3912 if (seg == VCPU_SREG_CS)
3913 ar |= 0x08; /* code segment */
3a624e29
NK		 3914
3915 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3916}
3917
f78e0e2e
SY		 3918static int alloc_apic_access_page(struct kvm *kvm)
3919{
4484141a 3920 struct page *page;
f78e0e2e
SY		 3921 struct kvm_userspace_memory_region kvm_userspace_mem;
3922 int r = 0;
3923
79fac95e 3924 mutex_lock(&kvm->slots_lock);
bfc6d222 3925 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3926 goto out;
3927 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3928 kvm_userspace_mem.flags = 0;
3929 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3930 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3931 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3932 if (r)
3933 goto out;
72dc67a6 3934
4484141a
XG		 3935 page = gfn_to_page(kvm, 0xfee00);
3936 if (is_error_page(page)) {
3937 r = -EFAULT;
3938 goto out;
3939 }
3940
3941 kvm->arch.apic_access_page = page;
f78e0e2e 3942out:
79fac95e 3943 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3944 return r;
3945}
3946
b7ebfb05
SY		 3947static int alloc_identity_pagetable(struct kvm *kvm)
3948{
4484141a 3949 struct page *page;
b7ebfb05
SY		 3950 struct kvm_userspace_memory_region kvm_userspace_mem;
3951 int r = 0;
3952
79fac95e 3953 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3954 if (kvm->arch.ept_identity_pagetable)
3955 goto out;
3956 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3957 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3958 kvm_userspace_mem.guest_phys_addr =
3959 kvm->arch.ept_identity_map_addr;
b7ebfb05 3960 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3961 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3962 if (r)
3963 goto out;
3964
4484141a
XG		 3965 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3966 if (is_error_page(page)) {
3967 r = -EFAULT;
3968 goto out;
3969 }
3970
3971 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3972out:
79fac95e 3973 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3974 return r;
3975}
3976
2384d2b3
SY		 3977static void allocate_vpid(struct vcpu_vmx *vmx)
3978{
3979 int vpid;
3980
3981 vmx->vpid = 0;
919818ab 3982 if (!enable_vpid)
2384d2b3
SY		 3983 return;
3984 spin_lock(&vmx_vpid_lock);
3985 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3986 if (vpid < VMX_NR_VPIDS) {
3987 vmx->vpid = vpid;
3988 __set_bit(vpid, vmx_vpid_bitmap);
3989 }
3990 spin_unlock(&vmx_vpid_lock);
3991}
3992
cdbecfc3
LJ		 3993static void free_vpid(struct vcpu_vmx *vmx)
3994{
3995 if (!enable_vpid)
3996 return;
3997 spin_lock(&vmx_vpid_lock);
3998 if (vmx->vpid != 0)
3999 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4000 spin_unlock(&vmx_vpid_lock);
4001}
4002
8d14695f
YZ		 4003#define MSR_TYPE_R 1
4004#define MSR_TYPE_W 2
4005static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4006 u32 msr, int type)
25c5f225 4007{
3e7c73e9 4008 int f = sizeof(unsigned long);
25c5f225
SY		 4009
4010 if (!cpu_has_vmx_msr_bitmap())
4011 return;
4012
4013 /*
4014 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4015 * have the write-low and read-high bitmap offsets the wrong way round.
4016 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4017 */
25c5f225 4018 if (msr <= 0x1fff) {
8d14695f
YZ		 4019 if (type & MSR_TYPE_R)
4020 /* read-low */
4021 __clear_bit(msr, msr_bitmap + 0x000 / f);
4022
4023 if (type & MSR_TYPE_W)
4024 /* write-low */
4025 __clear_bit(msr, msr_bitmap + 0x800 / f);
4026
25c5f225
SY		 4027 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4028 msr &= 0x1fff;
8d14695f
YZ		 4029 if (type & MSR_TYPE_R)
4030 /* read-high */
4031 __clear_bit(msr, msr_bitmap + 0x400 / f);
4032
4033 if (type & MSR_TYPE_W)
4034 /* write-high */
4035 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4036
4037 }
4038}
4039
4040static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4041 u32 msr, int type)
4042{
4043 int f = sizeof(unsigned long);
4044
4045 if (!cpu_has_vmx_msr_bitmap())
4046 return;
4047
4048 /*
4049 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4050 * have the write-low and read-high bitmap offsets the wrong way round.
4051 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4052 */
4053 if (msr <= 0x1fff) {
4054 if (type & MSR_TYPE_R)
4055 /* read-low */
4056 __set_bit(msr, msr_bitmap + 0x000 / f);
4057
4058 if (type & MSR_TYPE_W)
4059 /* write-low */
4060 __set_bit(msr, msr_bitmap + 0x800 / f);
4061
4062 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4063 msr &= 0x1fff;
4064 if (type & MSR_TYPE_R)
4065 /* read-high */
4066 __set_bit(msr, msr_bitmap + 0x400 / f);
4067
4068 if (type & MSR_TYPE_W)
4069 /* write-high */
4070 __set_bit(msr, msr_bitmap + 0xc00 / f);
4071
25c5f225 4072 }
25c5f225
SY		 4073}
4074
5897297b
AK		 4075static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4076{
4077 if (!longmode_only)
8d14695f
YZ		 4078 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4079 msr, MSR_TYPE_R | MSR_TYPE_W);
4080 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4081 msr, MSR_TYPE_R | MSR_TYPE_W);
4082}
4083
4084static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4085{
4086 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4087 msr, MSR_TYPE_R);
4088 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4089 msr, MSR_TYPE_R);
4090}
4091
4092static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4093{
4094 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4095 msr, MSR_TYPE_R);
4096 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4097 msr, MSR_TYPE_R);
4098}
4099
4100static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4101{
4102 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4103 msr, MSR_TYPE_W);
4104 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4105 msr, MSR_TYPE_W);
5897297b
AK		 4106}
4107
01e439be
YZ		 4108static int vmx_vm_has_apicv(struct kvm *kvm)
4109{
4110 return enable_apicv && irqchip_in_kernel(kvm);
4111}
4112
a20ed54d
YZ		 4113/*
4114 * Send interrupt to vcpu via posted interrupt way.
4115 * 1. If target vcpu is running(non-root mode), send posted interrupt
4116 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4117 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4118 * interrupt from PIR in next vmentry.
4119 */
4120static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4121{
4122 struct vcpu_vmx *vmx = to_vmx(vcpu);
4123 int r;
4124
4125 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4126 return;
4127
4128 r = pi_test_and_set_on(&vmx->pi_desc);
4129 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4130#ifdef CONFIG_SMP
a20ed54d
YZ		 4131 if (!r && (vcpu->mode == IN_GUEST_MODE))
4132 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4133 POSTED_INTR_VECTOR);
4134 else
6ffbbbba 4135#endif
a20ed54d
YZ		 4136 kvm_vcpu_kick(vcpu);
4137}
4138
4139static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4140{
4141 struct vcpu_vmx *vmx = to_vmx(vcpu);
4142
4143 if (!pi_test_and_clear_on(&vmx->pi_desc))
4144 return;
4145
4146 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4147}
4148
4149static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4150{
4151 return;
4152}
4153
a3a8ff8e
NHE		 4154/*
4155 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4156 * will not change in the lifetime of the guest.
4157 * Note that host-state that does change is set elsewhere. E.g., host-state
4158 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4159 */
a547c6db 4160static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4161{
4162 u32 low32, high32;
4163 unsigned long tmpl;
4164 struct desc_ptr dt;
4165
b1a74bf8 4166 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4167 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4168 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4169
4170 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4171#ifdef CONFIG_X86_64
4172 /*
4173 * Load null selectors, so we can avoid reloading them in
4174 * __vmx_load_host_state(), in case userspace uses the null selectors
4175 * too (the expected case).
4176 */
4177 vmcs_write16(HOST_DS_SELECTOR, 0);
4178 vmcs_write16(HOST_ES_SELECTOR, 0);
4179#else
a3a8ff8e
NHE		 4180 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4181 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4182#endif
a3a8ff8e
NHE		 4183 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4184 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4185
4186 native_store_idt(&dt);
4187 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4188 vmx->host_idt_base = dt.address;
a3a8ff8e 4189
83287ea4 4190 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4191
4192 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4193 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4194 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4195 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4196
4197 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4198 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4199 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4200 }
4201}
4202
bf8179a0
NHE		 4203static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4204{
4205 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4206 if (enable_ept)
4207 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4208 if (is_guest_mode(&vmx->vcpu))
4209 vmx->vcpu.arch.cr4_guest_owned_bits &=
4210 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4211 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4212}
4213
01e439be
YZ		 4214static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4215{
4216 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4217
4218 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4219 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4220 return pin_based_exec_ctrl;
4221}
4222
bf8179a0
NHE		 4223static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4224{
4225 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4226 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4227 exec_control &= ~CPU_BASED_TPR_SHADOW;
4228#ifdef CONFIG_X86_64
4229 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4230 CPU_BASED_CR8_LOAD_EXITING;
4231#endif
4232 }
4233 if (!enable_ept)
4234 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4235 CPU_BASED_CR3_LOAD_EXITING |
4236 CPU_BASED_INVLPG_EXITING;
4237 return exec_control;
4238}
4239
4240static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4241{
4242 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4243 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4244 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4245 if (vmx->vpid == 0)
4246 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4247 if (!enable_ept) {
4248 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4249 enable_unrestricted_guest = 0;
ad756a16
MJ		 4250 /* Enable INVPCID for non-ept guests may cause performance regression. */
4251 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4252 }
4253 if (!enable_unrestricted_guest)
4254 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4255 if (!ple_gap)
4256 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4257 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4258 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4259 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4260 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4261 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4262 (handle_vmptrld).
4263 We can NOT enable shadow_vmcs here because we don't have yet
4264 a current VMCS12
4265 */
4266 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4267 return exec_control;
4268}
4269
ce88decf
XG		 4270static void ept_set_mmio_spte_mask(void)
4271{
4272 /*
4273 * EPT Misconfigurations can be generated if the value of bits 2:0
4274 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4275 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4276 * spte.
4277 */
885032b9 4278 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4279}
4280
6aa8b732
AK		 4281/*
4282 * Sets up the vmcs for emulated real mode.
4283 */
8b9cf98c 4284static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4285{
2e4ce7f5 4286#ifdef CONFIG_X86_64
6aa8b732 4287 unsigned long a;
2e4ce7f5 4288#endif
6aa8b732 4289 int i;
6aa8b732 4290
6aa8b732 4291 /* I/O */
3e7c73e9
AK		 4292 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4293 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4294
4607c2d7
AG		 4295 if (enable_shadow_vmcs) {
4296 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4297 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4298 }
25c5f225 4299 if (cpu_has_vmx_msr_bitmap())
5897297b 4300 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4301
6aa8b732
AK		 4302 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4303
6aa8b732 4304 /* Control */
01e439be 4305 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4306
bf8179a0 4307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4308
83ff3b9d 4309 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4310 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4311 vmx_secondary_exec_control(vmx));
83ff3b9d 4312 }
f78e0e2e 4313
01e439be 4314 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4315 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4316 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4317 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4318 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4319
4320 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4321
4322 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4323 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4324 }
4325
4b8d54f9
ZE		 4326 if (ple_gap) {
4327 vmcs_write32(PLE_GAP, ple_gap);
4328 vmcs_write32(PLE_WINDOW, ple_window);
4329 }
4330
c3707958
XG		 4331 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4332 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4333 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4334
9581d442
AK		 4335 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4336 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4337 vmx_set_constant_host_state(vmx);
05b3e0c2 4338#ifdef CONFIG_X86_64
6aa8b732
AK		 4339 rdmsrl(MSR_FS_BASE, a);
4340 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4341 rdmsrl(MSR_GS_BASE, a);
4342 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4343#else
4344 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4345 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4346#endif
4347
2cc51560
ED		 4348 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4349 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4350 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4351 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4352 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4353
468d472f 4354 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4355 u32 msr_low, msr_high;
4356 u64 host_pat;
468d472f
SY		 4357 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4358 host_pat = msr_low | ((u64) msr_high << 32);
4359 /* Write the default value follow host pat */
4360 vmcs_write64(GUEST_IA32_PAT, host_pat);
4361 /* Keep arch.pat sync with GUEST_IA32_PAT */
4362 vmx->vcpu.arch.pat = host_pat;
4363 }
4364
6aa8b732
AK		 4365 for (i = 0; i < NR_VMX_MSR; ++i) {
4366 u32 index = vmx_msr_index[i];
4367 u32 data_low, data_high;
a2fa3e9f 4368 int j = vmx->nmsrs;
6aa8b732
AK		 4369
4370 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4371 continue;
432bd6cb
AK		 4372 if (wrmsr_safe(index, data_low, data_high) < 0)
4373 continue;
26bb0981
AK		 4374 vmx->guest_msrs[j].index = i;
4375 vmx->guest_msrs[j].data = 0;
d5696725 4376 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4377 ++vmx->nmsrs;
6aa8b732 4378 }
6aa8b732 4379
2961e876
GN		 4380
4381 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4382
4383 /* 22.2.1, 20.8.1 */
2961e876 4384 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4385
e00c8cf2 4386 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4387 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4388
4389 return 0;
4390}
4391
57f252f2 4392static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4393{
4394 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4395 struct msr_data apic_base_msr;
e00c8cf2 4396
7ffd92c5 4397 vmx->rmode.vm86_active = 0;
e00c8cf2 4398
3b86cd99
JK		 4399 vmx->soft_vnmi_blocked = 0;
4400
ad312c7c 4401 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4402 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4403 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4404 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4405 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4406 apic_base_msr.host_initiated = true;
4407 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4408
2fb92db1
AK		 4409 vmx_segment_cache_clear(vmx);
4410
5706be0d 4411 seg_setup(VCPU_SREG_CS);
66450a21 4412 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4413 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4414
4415 seg_setup(VCPU_SREG_DS);
4416 seg_setup(VCPU_SREG_ES);
4417 seg_setup(VCPU_SREG_FS);
4418 seg_setup(VCPU_SREG_GS);
4419 seg_setup(VCPU_SREG_SS);
4420
4421 vmcs_write16(GUEST_TR_SELECTOR, 0);
4422 vmcs_writel(GUEST_TR_BASE, 0);
4423 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4424 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4425
4426 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4427 vmcs_writel(GUEST_LDTR_BASE, 0);
4428 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4429 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4430
4431 vmcs_write32(GUEST_SYSENTER_CS, 0);
4432 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4433 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4434
4435 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4436 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4437
e00c8cf2
AK		 4438 vmcs_writel(GUEST_GDTR_BASE, 0);
4439 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4440
4441 vmcs_writel(GUEST_IDTR_BASE, 0);
4442 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4443
443381a8 4444 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4445 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4446 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4447
e00c8cf2
AK		 4448 /* Special registers */
4449 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4450
4451 setup_msrs(vmx);
4452
6aa8b732
AK		 4453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4454
f78e0e2e
SY		 4455 if (cpu_has_vmx_tpr_shadow()) {
4456 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4457 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4458 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4459 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4460 vmcs_write32(TPR_THRESHOLD, 0);
4461 }
4462
4463 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4464 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4465 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4466
01e439be
YZ		 4467 if (vmx_vm_has_apicv(vcpu->kvm))
4468 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4469
2384d2b3
SY		 4470 if (vmx->vpid != 0)
4471 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4472
fa40052c 4473 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4474 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4475 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4476 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4477 vmx_fpu_activate(&vmx->vcpu);
4478 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4479
b9d762fa 4480 vpid_sync_context(vmx);
6aa8b732
AK		 4481}
4482
b6f1250e
NHE		 4483/*
4484 * In nested virtualization, check if L1 asked to exit on external interrupts.
4485 * For most existing hypervisors, this will always return true.
4486 */
4487static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4488{
4489 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4490 PIN_BASED_EXT_INTR_MASK;
4491}
4492
ea8ceb83
JK		 4493static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4494{
4495 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4496 PIN_BASED_NMI_EXITING;
4497}
4498
730dca42 4499static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4500{
4501 u32 cpu_based_vm_exec_control;
730dca42
JK		 4502
4503 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4504 /*
4505 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4506 * inject to L1 now because L2 must run. The caller will have
4507 * to make L2 exit right after entry, so we can inject to L1
4508 * more promptly.
b6f1250e 4509 */
730dca42 4510 return -EBUSY;
3b86cd99
JK		 4511
4512 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4513 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4514 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4515 return 0;
3b86cd99
JK		 4516}
4517
03b28f81 4518static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4519{
4520 u32 cpu_based_vm_exec_control;
4521
03b28f81
JK		 4522 if (!cpu_has_virtual_nmis())
4523 return enable_irq_window(vcpu);
4524
4525 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4526 return enable_irq_window(vcpu);
3b86cd99
JK		 4527
4528 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4529 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4530 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4531 return 0;
3b86cd99
JK		 4532}
4533
66fd3f7f 4534static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4535{
9c8cba37 4536 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4537 uint32_t intr;
4538 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4539
229456fc 4540 trace_kvm_inj_virq(irq);
2714d1d3 4541
fa89a817 4542 ++vcpu->stat.irq_injections;
7ffd92c5 4543 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4544 int inc_eip = 0;
4545 if (vcpu->arch.interrupt.soft)
4546 inc_eip = vcpu->arch.event_exit_inst_len;
4547 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4548 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4549 return;
4550 }
66fd3f7f
GN		 4551 intr = irq | INTR_INFO_VALID_MASK;
4552 if (vcpu->arch.interrupt.soft) {
4553 intr |= INTR_TYPE_SOFT_INTR;
4554 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4555 vmx->vcpu.arch.event_exit_inst_len);
4556 } else
4557 intr |= INTR_TYPE_EXT_INTR;
4558 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4559}
4560
f08864b4
SY		 4561static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4562{
66a5a347
JK		 4563 struct vcpu_vmx *vmx = to_vmx(vcpu);
4564
0b6ac343
NHE		 4565 if (is_guest_mode(vcpu))
4566 return;
4567
3b86cd99
JK		 4568 if (!cpu_has_virtual_nmis()) {
4569 /*
4570 * Tracking the NMI-blocked state in software is built upon
4571 * finding the next open IRQ window. This, in turn, depends on
4572 * well-behaving guests: They have to keep IRQs disabled at
4573 * least as long as the NMI handler runs. Otherwise we may
4574 * cause NMI nesting, maybe breaking the guest. But as this is
4575 * highly unlikely, we can live with the residual risk.
4576 */
4577 vmx->soft_vnmi_blocked = 1;
4578 vmx->vnmi_blocked_time = 0;
4579 }
4580
487b391d 4581 ++vcpu->stat.nmi_injections;
9d58b931 4582 vmx->nmi_known_unmasked = false;
7ffd92c5 4583 if (vmx->rmode.vm86_active) {
71f9833b 4584 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4585 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4586 return;
4587 }
f08864b4
SY		 4588 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4589 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4590}
4591
3cfc3092
JK		 4592static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4593{
4594 if (!cpu_has_virtual_nmis())
4595 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4596 if (to_vmx(vcpu)->nmi_known_unmasked)
4597 return false;
c332c83a 4598 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4599}
4600
4601static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4602{
4603 struct vcpu_vmx *vmx = to_vmx(vcpu);
4604
4605 if (!cpu_has_virtual_nmis()) {
4606 if (vmx->soft_vnmi_blocked != masked) {
4607 vmx->soft_vnmi_blocked = masked;
4608 vmx->vnmi_blocked_time = 0;
4609 }
4610 } else {
9d58b931 4611 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4612 if (masked)
4613 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4614 GUEST_INTR_STATE_NMI);
4615 else
4616 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4617 GUEST_INTR_STATE_NMI);
4618 }
4619}
4620
2505dc9f
JK		 4621static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4622{
ea8ceb83 4623 if (is_guest_mode(vcpu)) {
ea8ceb83
JK		 4624 if (to_vmx(vcpu)->nested.nested_run_pending)
4625 return 0;
4626 if (nested_exit_on_nmi(vcpu)) {
533558bc
JK		 4627 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
4628 NMI_VECTOR | INTR_TYPE_NMI_INTR |
4629 INTR_INFO_VALID_MASK, 0);
ea8ceb83
JK		 4630 /*
4631 * The NMI-triggered VM exit counts as injection:
4632 * clear this one and block further NMIs.
4633 */
4634 vcpu->arch.nmi_pending = 0;
4635 vmx_set_nmi_mask(vcpu, true);
4636 return 0;
4637 }
4638 }
4639
2505dc9f
JK		 4640 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4641 return 0;
4642
4643 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4644 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4645 | GUEST_INTR_STATE_NMI));
4646}
4647
78646121
GN		 4648static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4649{
e8457c67 4650 if (is_guest_mode(vcpu)) {
e8457c67 4651 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4652 return 0;
e8457c67 4653 if (nested_exit_on_intr(vcpu)) {
533558bc
JK		 4654 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT,
4655 0, 0);
e8457c67
JK		 4656 /*
4657 * fall through to normal code, but now in L1, not L2
4658 */
4659 }
b6f1250e
NHE		 4660 }
4661
c4282df9
GN		 4662 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4663 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4664 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4665}
4666
cbc94022
IE		 4667static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4668{
4669 int ret;
4670 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4671 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4672 .guest_phys_addr = addr,
4673 .memory_size = PAGE_SIZE * 3,
4674 .flags = 0,
4675 };
4676
47ae31e2 4677 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4678 if (ret)
4679 return ret;
bfc6d222 4680 kvm->arch.tss_addr = addr;
93ea5388
GN		 4681 if (!init_rmode_tss(kvm))
4682 return -ENOMEM;
4683
cbc94022
IE		 4684 return 0;
4685}
4686
0ca1b4f4 4687static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4688{
77ab6db0 4689 switch (vec) {
77ab6db0 4690 case BP_VECTOR:
c573cd22
JK		 4691 /*
4692 * Update instruction length as we may reinject the exception
4693 * from user space while in guest debugging mode.
4694 */
4695 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4696 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4697 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4698 return false;
4699 /* fall through */
4700 case DB_VECTOR:
4701 if (vcpu->guest_debug &
4702 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4703 return false;
d0bfb940
JK		 4704 /* fall through */
4705 case DE_VECTOR:
77ab6db0
JK		 4706 case OF_VECTOR:
4707 case BR_VECTOR:
4708 case UD_VECTOR:
4709 case DF_VECTOR:
4710 case SS_VECTOR:
4711 case GP_VECTOR:
4712 case MF_VECTOR:
0ca1b4f4
GN		 4713 return true;
4714 break;
77ab6db0 4715 }
0ca1b4f4
GN		 4716 return false;
4717}
4718
4719static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4720 int vec, u32 err_code)
4721{
4722 /*
4723 * Instruction with address size override prefix opcode 0x67
4724 * Cause the #SS fault with 0 error code in VM86 mode.
4725 */
4726 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4727 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4728 if (vcpu->arch.halt_request) {
4729 vcpu->arch.halt_request = 0;
4730 return kvm_emulate_halt(vcpu);
4731 }
4732 return 1;
4733 }
4734 return 0;
4735 }
4736
4737 /*
4738 * Forward all other exceptions that are valid in real mode.
4739 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4740 * the required debugging infrastructure rework.
4741 */
4742 kvm_queue_exception(vcpu, vec);
4743 return 1;
6aa8b732
AK		 4744}
4745
a0861c02
AK		 4746/*
4747 * Trigger machine check on the host. We assume all the MSRs are already set up
4748 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4749 * We pass a fake environment to the machine check handler because we want
4750 * the guest to be always treated like user space, no matter what context
4751 * it used internally.
4752 */
4753static void kvm_machine_check(void)
4754{
4755#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4756 struct pt_regs regs = {
4757 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4758 .flags = X86_EFLAGS_IF,
4759 };
4760
4761 do_machine_check(&regs, 0);
4762#endif
4763}
4764
851ba692 4765static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4766{
4767 /* already handled by vcpu_run */
4768 return 1;
4769}
4770
851ba692 4771static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4772{
1155f76a 4773 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4774 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4775 u32 intr_info, ex_no, error_code;
42dbaa5a 4776 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4777 u32 vect_info;
4778 enum emulation_result er;
4779
1155f76a 4780 vect_info = vmx->idt_vectoring_info;
88786475 4781 intr_info = vmx->exit_intr_info;
6aa8b732 4782
a0861c02 4783 if (is_machine_check(intr_info))
851ba692 4784 return handle_machine_check(vcpu);
a0861c02 4785
e4a41889 4786 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4787 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4788
4789 if (is_no_device(intr_info)) {
5fd86fcf 4790 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4791 return 1;
4792 }
4793
7aa81cc0 4794 if (is_invalid_opcode(intr_info)) {
51d8b661 4795 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4796 if (er != EMULATE_DONE)
7ee5d940 4797 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4798 return 1;
4799 }
4800
6aa8b732 4801 error_code = 0;
2e11384c 4802 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4803 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4804
4805 /*
4806 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4807 * MMIO, it is better to report an internal error.
4808 * See the comments in vmx_handle_exit.
4809 */
4810 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4811 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4812 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4813 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4814 vcpu->run->internal.ndata = 2;
4815 vcpu->run->internal.data[0] = vect_info;
4816 vcpu->run->internal.data[1] = intr_info;
4817 return 0;
4818 }
4819
6aa8b732 4820 if (is_page_fault(intr_info)) {
1439442c 4821 /* EPT won't cause page fault directly */
cf3ace79 4822 BUG_ON(enable_ept);
6aa8b732 4823 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4824 trace_kvm_page_fault(cr2, error_code);
4825
3298b75c 4826 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4827 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4828 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4829 }
4830
d0bfb940 4831 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4832
4833 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4834 return handle_rmode_exception(vcpu, ex_no, error_code);
4835
42dbaa5a
JK		 4836 switch (ex_no) {
4837 case DB_VECTOR:
4838 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4839 if (!(vcpu->guest_debug &
4840 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4841 vcpu->arch.dr6 &= ~15;
4842 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4843 kvm_queue_exception(vcpu, DB_VECTOR);
4844 return 1;
4845 }
4846 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4847 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4848 /* fall through */
4849 case BP_VECTOR:
c573cd22
JK		 4850 /*
4851 * Update instruction length as we may reinject #BP from
4852 * user space while in guest debugging mode. Reading it for
4853 * #DB as well causes no harm, it is not used in that case.
4854 */
4855 vmx->vcpu.arch.event_exit_inst_len =
4856 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4857 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4858 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4859 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4860 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4861 break;
4862 default:
d0bfb940
JK		 4863 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4864 kvm_run->ex.exception = ex_no;
4865 kvm_run->ex.error_code = error_code;
42dbaa5a 4866 break;
6aa8b732 4867 }
6aa8b732
AK		 4868 return 0;
4869}
4870
851ba692 4871static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4872{
1165f5fe 4873 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4874 return 1;
4875}
4876
851ba692 4877static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4878{
851ba692 4879 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4880 return 0;
4881}
6aa8b732 4882
851ba692 4883static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4884{
bfdaab09 4885 unsigned long exit_qualification;
34c33d16 4886 int size, in, string;
039576c0 4887 unsigned port;
6aa8b732 4888
bfdaab09 4889 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4890 string = (exit_qualification & 16) != 0;
cf8f70bf 4891 in = (exit_qualification & 8) != 0;
e70669ab 4892
cf8f70bf 4893 ++vcpu->stat.io_exits;
e70669ab 4894
cf8f70bf 4895 if (string || in)
51d8b661 4896 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4897
cf8f70bf
GN		 4898 port = exit_qualification >> 16;
4899 size = (exit_qualification & 7) + 1;
e93f36bc 4900 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4901
4902 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4903}
4904
102d8325
IM		 4905static void
4906vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4907{
4908 /*
4909 * Patch in the VMCALL instruction:
4910 */
4911 hypercall[0] = 0x0f;
4912 hypercall[1] = 0x01;
4913 hypercall[2] = 0xc1;
102d8325
IM		 4914}
4915
92fbc7b1
JK		 4916static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4917{
4918 unsigned long always_on = VMXON_CR0_ALWAYSON;
4919
4920 if (nested_vmx_secondary_ctls_high &
4921 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4922 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4923 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4924 return (val & always_on) == always_on;
4925}
4926
0fa06071 4927/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4928static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4929{
eeadf9e7 4930 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4931 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4932 unsigned long orig_val = val;
4933
eeadf9e7
NHE		 4934 /*
4935 * We get here when L2 changed cr0 in a way that did not change
4936 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4937 * but did change L0 shadowed bits. So we first calculate the
4938 * effective cr0 value that L1 would like to write into the
4939 * hardware. It consists of the L2-owned bits from the new
4940 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4941 */
1a0d74e6
JK		 4942 val = (val & ~vmcs12->cr0_guest_host_mask) |
4943 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4944
92fbc7b1 4945 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4946 return 1;
1a0d74e6
JK		 4947
4948 if (kvm_set_cr0(vcpu, val))
4949 return 1;
4950 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4951 return 0;
1a0d74e6
JK		 4952 } else {
4953 if (to_vmx(vcpu)->nested.vmxon &&
4954 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4955 return 1;
eeadf9e7 4956 return kvm_set_cr0(vcpu, val);
1a0d74e6 4957 }
eeadf9e7
NHE		 4958}
4959
4960static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4961{
4962 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4963 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4964 unsigned long orig_val = val;
4965
4966 /* analogously to handle_set_cr0 */
4967 val = (val & ~vmcs12->cr4_guest_host_mask) |
4968 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4969 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4970 return 1;
1a0d74e6 4971 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4972 return 0;
4973 } else
4974 return kvm_set_cr4(vcpu, val);
4975}
4976
4977/* called to set cr0 as approriate for clts instruction exit. */
4978static void handle_clts(struct kvm_vcpu *vcpu)
4979{
4980 if (is_guest_mode(vcpu)) {
4981 /*
4982 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4983 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4984 * just pretend it's off (also in arch.cr0 for fpu_activate).
4985 */
4986 vmcs_writel(CR0_READ_SHADOW,
4987 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4988 vcpu->arch.cr0 &= ~X86_CR0_TS;
4989 } else
4990 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4991}
4992
851ba692 4993static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4994{
229456fc 4995 unsigned long exit_qualification, val;
6aa8b732
AK		 4996 int cr;
4997 int reg;
49a9b07e 4998 int err;
6aa8b732 4999
bfdaab09 5000 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5001 cr = exit_qualification & 15;
5002 reg = (exit_qualification >> 8) & 15;
5003 switch ((exit_qualification >> 4) & 3) {
5004 case 0: /* mov to cr */
229456fc
MT		 5005 val = kvm_register_read(vcpu, reg);
5006 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5007 switch (cr) {
5008 case 0:
eeadf9e7 5009 err = handle_set_cr0(vcpu, val);
db8fcefa 5010 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5011 return 1;
5012 case 3:
2390218b 5013 err = kvm_set_cr3(vcpu, val);
db8fcefa 5014 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5015 return 1;
5016 case 4:
eeadf9e7 5017 err = handle_set_cr4(vcpu, val);
db8fcefa 5018 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5019 return 1;
0a5fff19
GN		 5020 case 8: {
5021 u8 cr8_prev = kvm_get_cr8(vcpu);
5022 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5023 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5024 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5025 if (irqchip_in_kernel(vcpu->kvm))
5026 return 1;
5027 if (cr8_prev <= cr8)
5028 return 1;
851ba692 5029 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5030 return 0;
5031 }
4b8073e4 5032 }
6aa8b732 5033 break;
25c4c276 5034 case 2: /* clts */
eeadf9e7 5035 handle_clts(vcpu);
4d4ec087 5036 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5037 skip_emulated_instruction(vcpu);
6b52d186 5038 vmx_fpu_activate(vcpu);
25c4c276 5039 return 1;
6aa8b732
AK		 5040 case 1: /*mov from cr*/
5041 switch (cr) {
5042 case 3:
9f8fe504
AK		 5043 val = kvm_read_cr3(vcpu);
5044 kvm_register_write(vcpu, reg, val);
5045 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5046 skip_emulated_instruction(vcpu);
5047 return 1;
5048 case 8:
229456fc
MT		 5049 val = kvm_get_cr8(vcpu);
5050 kvm_register_write(vcpu, reg, val);
5051 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5052 skip_emulated_instruction(vcpu);
5053 return 1;
5054 }
5055 break;
5056 case 3: /* lmsw */
a1f83a74 5057 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5058 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5059 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5060
5061 skip_emulated_instruction(vcpu);
5062 return 1;
5063 default:
5064 break;
5065 }
851ba692 5066 vcpu->run->exit_reason = 0;
a737f256 5067 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5068 (int)(exit_qualification >> 4) & 3, cr);
5069 return 0;
5070}
5071
851ba692 5072static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5073{
bfdaab09 5074 unsigned long exit_qualification;
6aa8b732
AK		 5075 int dr, reg;
5076
f2483415 5077 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5078 if (!kvm_require_cpl(vcpu, 0))
5079 return 1;
42dbaa5a
JK		 5080 dr = vmcs_readl(GUEST_DR7);
5081 if (dr & DR7_GD) {
5082 /*
5083 * As the vm-exit takes precedence over the debug trap, we
5084 * need to emulate the latter, either for the host or the
5085 * guest debugging itself.
5086 */
5087 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5088 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5089 vcpu->run->debug.arch.dr7 = dr;
5090 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5091 vmcs_readl(GUEST_CS_BASE) +
5092 vmcs_readl(GUEST_RIP);
851ba692
AK		 5093 vcpu->run->debug.arch.exception = DB_VECTOR;
5094 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5095 return 0;
5096 } else {
5097 vcpu->arch.dr7 &= ~DR7_GD;
5098 vcpu->arch.dr6 |= DR6_BD;
5099 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5100 kvm_queue_exception(vcpu, DB_VECTOR);
5101 return 1;
5102 }
5103 }
5104
bfdaab09 5105 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5106 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5107 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5108 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5109 unsigned long val;
4c4d563b
JK		 5110
5111 if (kvm_get_dr(vcpu, dr, &val))
5112 return 1;
5113 kvm_register_write(vcpu, reg, val);
020df079 5114 } else
4c4d563b
JK		 5115 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5116 return 1;
5117
6aa8b732
AK		 5118 skip_emulated_instruction(vcpu);
5119 return 1;
5120}
5121
73aaf249
JK		 5122static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5123{
5124 return vcpu->arch.dr6;
5125}
5126
5127static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5128{
5129}
5130
020df079
GN		 5131static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5132{
5133 vmcs_writel(GUEST_DR7, val);
5134}
5135
851ba692 5136static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5137{
06465c5a
AK		 5138 kvm_emulate_cpuid(vcpu);
5139 return 1;
6aa8b732
AK		 5140}
5141
851ba692 5142static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5143{
ad312c7c 5144 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5145 u64 data;
5146
5147 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5148 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5149 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5150 return 1;
5151 }
5152
229456fc 5153 trace_kvm_msr_read(ecx, data);
2714d1d3 5154
6aa8b732 5155 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5156 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5157 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5158 skip_emulated_instruction(vcpu);
5159 return 1;
5160}
5161
851ba692 5162static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5163{
8fe8ab46 5164 struct msr_data msr;
ad312c7c
ZX		 5165 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5166 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5167 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5168
8fe8ab46
WA		 5169 msr.data = data;
5170 msr.index = ecx;
5171 msr.host_initiated = false;
5172 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5173 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5174 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5175 return 1;
5176 }
5177
59200273 5178 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5179 skip_emulated_instruction(vcpu);
5180 return 1;
5181}
5182
851ba692 5183static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5184{
3842d135 5185 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5186 return 1;
5187}
5188
851ba692 5189static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5190{
85f455f7
ED		 5191 u32 cpu_based_vm_exec_control;
5192
5193 /* clear pending irq */
5194 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5195 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5196 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5197
3842d135
AK		 5198 kvm_make_request(KVM_REQ_EVENT, vcpu);
5199
a26bf12a 5200 ++vcpu->stat.irq_window_exits;
2714d1d3 5201
c1150d8c
DL		 5202 /*
5203 * If the user space waits to inject interrupts, exit as soon as
5204 * possible
5205 */
8061823a 5206 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5207 vcpu->run->request_interrupt_window &&
8061823a 5208 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5209 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5210 return 0;
5211 }
6aa8b732
AK		 5212 return 1;
5213}
5214
851ba692 5215static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5216{
5217 skip_emulated_instruction(vcpu);
d3bef15f 5218 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5219}
5220
851ba692 5221static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5222{
510043da 5223 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5224 kvm_emulate_hypercall(vcpu);
5225 return 1;
c21415e8
IM		 5226}
5227
ec25d5e6
GN		 5228static int handle_invd(struct kvm_vcpu *vcpu)
5229{
51d8b661 5230 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5231}
5232
851ba692 5233static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5234{
f9c617f6 5235 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5236
5237 kvm_mmu_invlpg(vcpu, exit_qualification);
5238 skip_emulated_instruction(vcpu);
5239 return 1;
5240}
5241
fee84b07
AK		 5242static int handle_rdpmc(struct kvm_vcpu *vcpu)
5243{
5244 int err;
5245
5246 err = kvm_rdpmc(vcpu);
5247 kvm_complete_insn_gp(vcpu, err);
5248
5249 return 1;
5250}
5251
851ba692 5252static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5253{
5254 skip_emulated_instruction(vcpu);
f5f48ee1 5255 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5256 return 1;
5257}
5258
2acf923e
DC		 5259static int handle_xsetbv(struct kvm_vcpu *vcpu)
5260{
5261 u64 new_bv = kvm_read_edx_eax(vcpu);
5262 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5263
5264 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5265 skip_emulated_instruction(vcpu);
5266 return 1;
5267}
5268
851ba692 5269static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5270{
58fbbf26
KT		 5271 if (likely(fasteoi)) {
5272 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5273 int access_type, offset;
5274
5275 access_type = exit_qualification & APIC_ACCESS_TYPE;
5276 offset = exit_qualification & APIC_ACCESS_OFFSET;
5277 /*
5278 * Sane guest uses MOV to write EOI, with written value
5279 * not cared. So make a short-circuit here by avoiding
5280 * heavy instruction emulation.
5281 */
5282 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5283 (offset == APIC_EOI)) {
5284 kvm_lapic_set_eoi(vcpu);
5285 skip_emulated_instruction(vcpu);
5286 return 1;
5287 }
5288 }
51d8b661 5289 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5290}
5291
c7c9c56c
YZ		 5292static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5293{
5294 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5295 int vector = exit_qualification & 0xff;
5296
5297 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5298 kvm_apic_set_eoi_accelerated(vcpu, vector);
5299 return 1;
5300}
5301
83d4c286
YZ		 5302static int handle_apic_write(struct kvm_vcpu *vcpu)
5303{
5304 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5305 u32 offset = exit_qualification & 0xfff;
5306
5307 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5308 kvm_apic_write_nodecode(vcpu, offset);
5309 return 1;
5310}
5311
851ba692 5312static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5313{
60637aac 5314 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5315 unsigned long exit_qualification;
e269fb21
JK		 5316 bool has_error_code = false;
5317 u32 error_code = 0;
37817f29 5318 u16 tss_selector;
7f3d35fd 5319 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5320
5321 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5322 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5323 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5324
5325 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5326
5327 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5328 if (reason == TASK_SWITCH_GATE && idt_v) {
5329 switch (type) {
5330 case INTR_TYPE_NMI_INTR:
5331 vcpu->arch.nmi_injected = false;
654f06fc 5332 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5333 break;
5334 case INTR_TYPE_EXT_INTR:
66fd3f7f 5335 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5336 kvm_clear_interrupt_queue(vcpu);
5337 break;
5338 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5339 if (vmx->idt_vectoring_info &
5340 VECTORING_INFO_DELIVER_CODE_MASK) {
5341 has_error_code = true;
5342 error_code =
5343 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5344 }
5345 /* fall through */
64a7ec06
GN		 5346 case INTR_TYPE_SOFT_EXCEPTION:
5347 kvm_clear_exception_queue(vcpu);
5348 break;
5349 default:
5350 break;
5351 }
60637aac 5352 }
37817f29
IE		 5353 tss_selector = exit_qualification;
5354
64a7ec06
GN		 5355 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5356 type != INTR_TYPE_EXT_INTR &&
5357 type != INTR_TYPE_NMI_INTR))
5358 skip_emulated_instruction(vcpu);
5359
7f3d35fd
KW		 5360 if (kvm_task_switch(vcpu, tss_selector,
5361 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5362 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5363 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5364 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5365 vcpu->run->internal.ndata = 0;
42dbaa5a 5366 return 0;
acb54517 5367 }
42dbaa5a
JK		 5368
5369 /* clear all local breakpoint enable flags */
5370 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5371
5372 /*
5373 * TODO: What about debug traps on tss switch?
5374 * Are we supposed to inject them and update dr6?
5375 */
5376
5377 return 1;
37817f29
IE		 5378}
5379
851ba692 5380static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5381{
f9c617f6 5382 unsigned long exit_qualification;
1439442c 5383 gpa_t gpa;
4f5982a5 5384 u32 error_code;
1439442c 5385 int gla_validity;
1439442c 5386
f9c617f6 5387 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5388
1439442c
SY		 5389 gla_validity = (exit_qualification >> 7) & 0x3;
5390 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5391 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5392 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5393 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5394 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5395 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5396 (long unsigned int)exit_qualification);
851ba692
AK		 5397 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5398 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5399 return 0;
1439442c
SY		 5400 }
5401
0be9c7a8
GN		 5402 /*
5403 * EPT violation happened while executing iret from NMI,
5404 * "blocked by NMI" bit has to be set before next VM entry.
5405 * There are errata that may cause this bit to not be set:
5406 * AAK134, BY25.
5407 */
bcd1c294
GN		 5408 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5409 cpu_has_virtual_nmis() &&
5410 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5411 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5412
1439442c 5413 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5414 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5415
5416 /* It is a write fault? */
5417 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5418 /* It is a fetch fault? */
5419 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5420 /* ept page table is present? */
5421 error_code |= (exit_qualification >> 3) & 0x1;
5422
25d92081
YZ		 5423 vcpu->arch.exit_qualification = exit_qualification;
5424
4f5982a5 5425 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5426}
5427
68f89400
MT		 5428static u64 ept_rsvd_mask(u64 spte, int level)
5429{
5430 int i;
5431 u64 mask = 0;
5432
5433 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5434 mask |= (1ULL << i);
5435
5436 if (level > 2)
5437 /* bits 7:3 reserved */
5438 mask |= 0xf8;
5439 else if (level == 2) {
5440 if (spte & (1ULL << 7))
5441 /* 2MB ref, bits 20:12 reserved */
5442 mask |= 0x1ff000;
5443 else
5444 /* bits 6:3 reserved */
5445 mask |= 0x78;
5446 }
5447
5448 return mask;
5449}
5450
5451static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5452 int level)
5453{
5454 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5455
5456 /* 010b (write-only) */
5457 WARN_ON((spte & 0x7) == 0x2);
5458
5459 /* 110b (write/execute) */
5460 WARN_ON((spte & 0x7) == 0x6);
5461
5462 /* 100b (execute-only) and value not supported by logical processor */
5463 if (!cpu_has_vmx_ept_execute_only())
5464 WARN_ON((spte & 0x7) == 0x4);
5465
5466 /* not 000b */
5467 if ((spte & 0x7)) {
5468 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5469
5470 if (rsvd_bits != 0) {
5471 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5472 __func__, rsvd_bits);
5473 WARN_ON(1);
5474 }
5475
5476 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5477 u64 ept_mem_type = (spte & 0x38) >> 3;
5478
5479 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5480 ept_mem_type == 7) {
5481 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5482 __func__, ept_mem_type);
5483 WARN_ON(1);
5484 }
5485 }
5486 }
5487}
5488
851ba692 5489static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5490{
5491 u64 sptes[4];
ce88decf 5492 int nr_sptes, i, ret;
68f89400
MT		 5493 gpa_t gpa;
5494
5495 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5496
ce88decf 5497 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5498 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5499 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5500 EMULATE_DONE;
f8f55942
XG		 5501
5502 if (unlikely(ret == RET_MMIO_PF_INVALID))
5503 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5504
b37fbea6 5505 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5506 return 1;
5507
5508 /* It is the real ept misconfig */
68f89400
MT		 5509 printk(KERN_ERR "EPT: Misconfiguration.\n");
5510 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5511
5512 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5513
5514 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5515 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5516
851ba692
AK		 5517 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5518 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5519
5520 return 0;
5521}
5522
851ba692 5523static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5524{
5525 u32 cpu_based_vm_exec_control;
5526
5527 /* clear pending NMI */
5528 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5529 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5530 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5531 ++vcpu->stat.nmi_window_exits;
3842d135 5532 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5533
5534 return 1;
5535}
5536
80ced186 5537static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5538{
8b3079a5
AK		 5539 struct vcpu_vmx *vmx = to_vmx(vcpu);
5540 enum emulation_result err = EMULATE_DONE;
80ced186 5541 int ret = 1;
49e9d557
AK		 5542 u32 cpu_exec_ctrl;
5543 bool intr_window_requested;
b8405c18 5544 unsigned count = 130;
49e9d557
AK		 5545
5546 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5547 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5548
b8405c18 5549 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5550 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5551 return handle_interrupt_window(&vmx->vcpu);
5552
de87dcdd
AK		 5553 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5554 return 1;
5555
991eebf9 5556 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5557
ac0a48c3 5558 if (err == EMULATE_USER_EXIT) {
94452b9e 5559 ++vcpu->stat.mmio_exits;
80ced186
MG		 5560 ret = 0;
5561 goto out;
5562 }
1d5a4d9b 5563
de5f70e0
AK		 5564 if (err != EMULATE_DONE) {
5565 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5566 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5567 vcpu->run->internal.ndata = 0;
6d77dbfc 5568 return 0;
de5f70e0 5569 }
ea953ef0 5570
8d76c49e
GN		 5571 if (vcpu->arch.halt_request) {
5572 vcpu->arch.halt_request = 0;
5573 ret = kvm_emulate_halt(vcpu);
5574 goto out;
5575 }
5576
ea953ef0 5577 if (signal_pending(current))
80ced186 5578 goto out;
ea953ef0
MG		 5579 if (need_resched())
5580 schedule();
5581 }
5582
14168786 5583 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5584out:
5585 return ret;
ea953ef0
MG		 5586}
5587
4b8d54f9
ZE		 5588/*
5589 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5590 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5591 */
9fb41ba8 5592static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5593{
5594 skip_emulated_instruction(vcpu);
5595 kvm_vcpu_on_spin(vcpu);
5596
5597 return 1;
5598}
5599
59708670
SY		 5600static int handle_invalid_op(struct kvm_vcpu *vcpu)
5601{
5602 kvm_queue_exception(vcpu, UD_VECTOR);
5603 return 1;
5604}
5605
ff2f6fe9
NHE		 5606/*
5607 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5608 * We could reuse a single VMCS for all the L2 guests, but we also want the
5609 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5610 * allows keeping them loaded on the processor, and in the future will allow
5611 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5612 * every entry if they never change.
5613 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5614 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5615 *
5616 * The following functions allocate and free a vmcs02 in this pool.
5617 */
5618
5619/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5620static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5621{
5622 struct vmcs02_list *item;
5623 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5624 if (item->vmptr == vmx->nested.current_vmptr) {
5625 list_move(&item->list, &vmx->nested.vmcs02_pool);
5626 return &item->vmcs02;
5627 }
5628
5629 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5630 /* Recycle the least recently used VMCS. */
5631 item = list_entry(vmx->nested.vmcs02_pool.prev,
5632 struct vmcs02_list, list);
5633 item->vmptr = vmx->nested.current_vmptr;
5634 list_move(&item->list, &vmx->nested.vmcs02_pool);
5635 return &item->vmcs02;
5636 }
5637
5638 /* Create a new VMCS */
0fa24ce3 5639 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5640 if (!item)
5641 return NULL;
5642 item->vmcs02.vmcs = alloc_vmcs();
5643 if (!item->vmcs02.vmcs) {
5644 kfree(item);
5645 return NULL;
5646 }
5647 loaded_vmcs_init(&item->vmcs02);
5648 item->vmptr = vmx->nested.current_vmptr;
5649 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5650 vmx->nested.vmcs02_num++;
5651 return &item->vmcs02;
5652}
5653
5654/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5655static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5656{
5657 struct vmcs02_list *item;
5658 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5659 if (item->vmptr == vmptr) {
5660 free_loaded_vmcs(&item->vmcs02);
5661 list_del(&item->list);
5662 kfree(item);
5663 vmx->nested.vmcs02_num--;
5664 return;
5665 }
5666}
5667
5668/*
5669 * Free all VMCSs saved for this vcpu, except the one pointed by
5670 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5671 * currently used, if running L2), and vmcs01 when running L2.
5672 */
5673static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5674{
5675 struct vmcs02_list *item, *n;
5676 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5677 if (vmx->loaded_vmcs != &item->vmcs02)
5678 free_loaded_vmcs(&item->vmcs02);
5679 list_del(&item->list);
5680 kfree(item);
5681 }
5682 vmx->nested.vmcs02_num = 0;
5683
5684 if (vmx->loaded_vmcs != &vmx->vmcs01)
5685 free_loaded_vmcs(&vmx->vmcs01);
5686}
5687
0658fbaa
ACL		 5688/*
5689 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5690 * set the success or error code of an emulated VMX instruction, as specified
5691 * by Vol 2B, VMX Instruction Reference, "Conventions".
5692 */
5693static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5694{
5695 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5696 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5697 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5698}
5699
5700static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5701{
5702 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5703 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5704 X86_EFLAGS_SF | X86_EFLAGS_OF))
5705 | X86_EFLAGS_CF);
5706}
5707
145c28dd 5708static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5709 u32 vm_instruction_error)
5710{
5711 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5712 /*
5713 * failValid writes the error number to the current VMCS, which
5714 * can't be done there isn't a current VMCS.
5715 */
5716 nested_vmx_failInvalid(vcpu);
5717 return;
5718 }
5719 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5720 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5721 X86_EFLAGS_SF | X86_EFLAGS_OF))
5722 | X86_EFLAGS_ZF);
5723 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5724 /*
5725 * We don't need to force a shadow sync because
5726 * VM_INSTRUCTION_ERROR is not shadowed
5727 */
5728}
145c28dd 5729
ec378aee
NHE		 5730/*
5731 * Emulate the VMXON instruction.
5732 * Currently, we just remember that VMX is active, and do not save or even
5733 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5734 * do not currently need to store anything in that guest-allocated memory
5735 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5736 * argument is different from the VMXON pointer (which the spec says they do).
5737 */
5738static int handle_vmon(struct kvm_vcpu *vcpu)
5739{
5740 struct kvm_segment cs;
5741 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5742 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5743 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5744 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5745
5746 /* The Intel VMX Instruction Reference lists a bunch of bits that
5747 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5748 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5749 * Otherwise, we should fail with #UD. We test these now:
5750 */
5751 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5752 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5753 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5754 kvm_queue_exception(vcpu, UD_VECTOR);
5755 return 1;
5756 }
5757
5758 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5759 if (is_long_mode(vcpu) && !cs.l) {
5760 kvm_queue_exception(vcpu, UD_VECTOR);
5761 return 1;
5762 }
5763
5764 if (vmx_get_cpl(vcpu)) {
5765 kvm_inject_gp(vcpu, 0);
5766 return 1;
5767 }
145c28dd
AG		 5768 if (vmx->nested.vmxon) {
5769 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5770 skip_emulated_instruction(vcpu);
5771 return 1;
5772 }
b3897a49
NHE		 5773
5774 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5775 != VMXON_NEEDED_FEATURES) {
5776 kvm_inject_gp(vcpu, 0);
5777 return 1;
5778 }
5779
8de48833
AG		 5780 if (enable_shadow_vmcs) {
5781 shadow_vmcs = alloc_vmcs();
5782 if (!shadow_vmcs)
5783 return -ENOMEM;
5784 /* mark vmcs as shadow */
5785 shadow_vmcs->revision_id |= (1u << 31);
5786 /* init shadow vmcs */
5787 vmcs_clear(shadow_vmcs);
5788 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5789 }
ec378aee 5790
ff2f6fe9
NHE		 5791 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5792 vmx->nested.vmcs02_num = 0;
5793
ec378aee
NHE		 5794 vmx->nested.vmxon = true;
5795
5796 skip_emulated_instruction(vcpu);
a25eb114 5797 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5798 return 1;
5799}
5800
5801/*
5802 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5803 * for running VMX instructions (except VMXON, whose prerequisites are
5804 * slightly different). It also specifies what exception to inject otherwise.
5805 */
5806static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5807{
5808 struct kvm_segment cs;
5809 struct vcpu_vmx *vmx = to_vmx(vcpu);
5810
5811 if (!vmx->nested.vmxon) {
5812 kvm_queue_exception(vcpu, UD_VECTOR);
5813 return 0;
5814 }
5815
5816 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5817 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5818 (is_long_mode(vcpu) && !cs.l)) {
5819 kvm_queue_exception(vcpu, UD_VECTOR);
5820 return 0;
5821 }
5822
5823 if (vmx_get_cpl(vcpu)) {
5824 kvm_inject_gp(vcpu, 0);
5825 return 0;
5826 }
5827
5828 return 1;
5829}
5830
e7953d7f
AG		 5831static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5832{
8a1b9dd0 5833 u32 exec_control;
012f83cb
AG		 5834 if (enable_shadow_vmcs) {
5835 if (vmx->nested.current_vmcs12 != NULL) {
5836 /* copy to memory all shadowed fields in case
5837 they were modified */
5838 copy_shadow_to_vmcs12(vmx);
5839 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5840 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5841 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5842 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5843 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5844 }
5845 }
e7953d7f
AG		 5846 kunmap(vmx->nested.current_vmcs12_page);
5847 nested_release_page(vmx->nested.current_vmcs12_page);
5848}
5849
ec378aee
NHE		 5850/*
5851 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5852 * just stops using VMX.
5853 */
5854static void free_nested(struct vcpu_vmx *vmx)
5855{
5856 if (!vmx->nested.vmxon)
5857 return;
5858 vmx->nested.vmxon = false;
a9d30f33 5859 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5860 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5861 vmx->nested.current_vmptr = -1ull;
5862 vmx->nested.current_vmcs12 = NULL;
5863 }
e7953d7f
AG		 5864 if (enable_shadow_vmcs)
5865 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5866 /* Unpin physical memory we referred to in current vmcs02 */
5867 if (vmx->nested.apic_access_page) {
5868 nested_release_page(vmx->nested.apic_access_page);
5869 vmx->nested.apic_access_page = 0;
5870 }
ff2f6fe9
NHE		 5871
5872 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5873}
5874
5875/* Emulate the VMXOFF instruction */
5876static int handle_vmoff(struct kvm_vcpu *vcpu)
5877{
5878 if (!nested_vmx_check_permission(vcpu))
5879 return 1;
5880 free_nested(to_vmx(vcpu));
5881 skip_emulated_instruction(vcpu);
a25eb114 5882 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5883 return 1;
5884}
5885
064aea77
NHE		 5886/*
5887 * Decode the memory-address operand of a vmx instruction, as recorded on an
5888 * exit caused by such an instruction (run by a guest hypervisor).
5889 * On success, returns 0. When the operand is invalid, returns 1 and throws
5890 * #UD or #GP.
5891 */
5892static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5893 unsigned long exit_qualification,
5894 u32 vmx_instruction_info, gva_t *ret)
5895{
5896 /*
5897 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5898 * Execution", on an exit, vmx_instruction_info holds most of the
5899 * addressing components of the operand. Only the displacement part
5900 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5901 * For how an actual address is calculated from all these components,
5902 * refer to Vol. 1, "Operand Addressing".
5903 */
5904 int scaling = vmx_instruction_info & 3;
5905 int addr_size = (vmx_instruction_info >> 7) & 7;
5906 bool is_reg = vmx_instruction_info & (1u << 10);
5907 int seg_reg = (vmx_instruction_info >> 15) & 7;
5908 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5909 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5910 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5911 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5912
5913 if (is_reg) {
5914 kvm_queue_exception(vcpu, UD_VECTOR);
5915 return 1;
5916 }
5917
5918 /* Addr = segment_base + offset */
5919 /* offset = base + [index * scale] + displacement */
5920 *ret = vmx_get_segment_base(vcpu, seg_reg);
5921 if (base_is_valid)
5922 *ret += kvm_register_read(vcpu, base_reg);
5923 if (index_is_valid)
5924 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5925 *ret += exit_qualification; /* holds the displacement */
5926
5927 if (addr_size == 1) /* 32 bit */
5928 *ret &= 0xffffffff;
5929
5930 /*
5931 * TODO: throw #GP (and return 1) in various cases that the VM*
5932 * instructions require it - e.g., offset beyond segment limit,
5933 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5934 * address, and so on. Currently these are not checked.
5935 */
5936 return 0;
5937}
5938
27d6c865
NHE		 5939/* Emulate the VMCLEAR instruction */
5940static int handle_vmclear(struct kvm_vcpu *vcpu)
5941{
5942 struct vcpu_vmx *vmx = to_vmx(vcpu);
5943 gva_t gva;
5944 gpa_t vmptr;
5945 struct vmcs12 *vmcs12;
5946 struct page *page;
5947 struct x86_exception e;
5948
5949 if (!nested_vmx_check_permission(vcpu))
5950 return 1;
5951
5952 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5953 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5954 return 1;
5955
5956 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5957 sizeof(vmptr), &e)) {
5958 kvm_inject_page_fault(vcpu, &e);
5959 return 1;
5960 }
5961
5962 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5963 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5964 skip_emulated_instruction(vcpu);
5965 return 1;
5966 }
5967
5968 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5969 nested_release_vmcs12(vmx);
27d6c865
NHE		 5970 vmx->nested.current_vmptr = -1ull;
5971 vmx->nested.current_vmcs12 = NULL;
5972 }
5973
5974 page = nested_get_page(vcpu, vmptr);
5975 if (page == NULL) {
5976 /*
5977 * For accurate processor emulation, VMCLEAR beyond available
5978 * physical memory should do nothing at all. However, it is
5979 * possible that a nested vmx bug, not a guest hypervisor bug,
5980 * resulted in this case, so let's shut down before doing any
5981 * more damage:
5982 */
5983 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5984 return 1;
5985 }
5986 vmcs12 = kmap(page);
5987 vmcs12->launch_state = 0;
5988 kunmap(page);
5989 nested_release_page(page);
5990
5991 nested_free_vmcs02(vmx, vmptr);
5992
5993 skip_emulated_instruction(vcpu);
5994 nested_vmx_succeed(vcpu);
5995 return 1;
5996}
5997
cd232ad0
NHE		 5998static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5999
6000/* Emulate the VMLAUNCH instruction */
6001static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6002{
6003 return nested_vmx_run(vcpu, true);
6004}
6005
6006/* Emulate the VMRESUME instruction */
6007static int handle_vmresume(struct kvm_vcpu *vcpu)
6008{
6009
6010 return nested_vmx_run(vcpu, false);
6011}
6012
49f705c5
NHE		 6013enum vmcs_field_type {
6014 VMCS_FIELD_TYPE_U16 = 0,
6015 VMCS_FIELD_TYPE_U64 = 1,
6016 VMCS_FIELD_TYPE_U32 = 2,
6017 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6018};
6019
6020static inline int vmcs_field_type(unsigned long field)
6021{
6022 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6023 return VMCS_FIELD_TYPE_U32;
6024 return (field >> 13) & 0x3 ;
6025}
6026
6027static inline int vmcs_field_readonly(unsigned long field)
6028{
6029 return (((field >> 10) & 0x3) == 1);
6030}
6031
6032/*
6033 * Read a vmcs12 field. Since these can have varying lengths and we return
6034 * one type, we chose the biggest type (u64) and zero-extend the return value
6035 * to that size. Note that the caller, handle_vmread, might need to use only
6036 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6037 * 64-bit fields are to be returned).
6038 */
6039static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6040 unsigned long field, u64 *ret)
6041{
6042 short offset = vmcs_field_to_offset(field);
6043 char *p;
6044
6045 if (offset < 0)
6046 return 0;
6047
6048 p = ((char *)(get_vmcs12(vcpu))) + offset;
6049
6050 switch (vmcs_field_type(field)) {
6051 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6052 *ret = *((natural_width *)p);
6053 return 1;
6054 case VMCS_FIELD_TYPE_U16:
6055 *ret = *((u16 *)p);
6056 return 1;
6057 case VMCS_FIELD_TYPE_U32:
6058 *ret = *((u32 *)p);
6059 return 1;
6060 case VMCS_FIELD_TYPE_U64:
6061 *ret = *((u64 *)p);
6062 return 1;
6063 default:
6064 return 0; /* can never happen. */
6065 }
6066}
6067
20b97fea
AG		 6068
6069static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6070 unsigned long field, u64 field_value){
6071 short offset = vmcs_field_to_offset(field);
6072 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6073 if (offset < 0)
6074 return false;
6075
6076 switch (vmcs_field_type(field)) {
6077 case VMCS_FIELD_TYPE_U16:
6078 *(u16 *)p = field_value;
6079 return true;
6080 case VMCS_FIELD_TYPE_U32:
6081 *(u32 *)p = field_value;
6082 return true;
6083 case VMCS_FIELD_TYPE_U64:
6084 *(u64 *)p = field_value;
6085 return true;
6086 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6087 *(natural_width *)p = field_value;
6088 return true;
6089 default:
6090 return false; /* can never happen. */
6091 }
6092
6093}
6094
16f5b903
AG		 6095static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6096{
6097 int i;
6098 unsigned long field;
6099 u64 field_value;
6100 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6101 const unsigned long *fields = shadow_read_write_fields;
6102 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6103
6104 vmcs_load(shadow_vmcs);
6105
6106 for (i = 0; i < num_fields; i++) {
6107 field = fields[i];
6108 switch (vmcs_field_type(field)) {
6109 case VMCS_FIELD_TYPE_U16:
6110 field_value = vmcs_read16(field);
6111 break;
6112 case VMCS_FIELD_TYPE_U32:
6113 field_value = vmcs_read32(field);
6114 break;
6115 case VMCS_FIELD_TYPE_U64:
6116 field_value = vmcs_read64(field);
6117 break;
6118 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6119 field_value = vmcs_readl(field);
6120 break;
6121 }
6122 vmcs12_write_any(&vmx->vcpu, field, field_value);
6123 }
6124
6125 vmcs_clear(shadow_vmcs);
6126 vmcs_load(vmx->loaded_vmcs->vmcs);
6127}
6128
c3114420
AG		 6129static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6130{
c2bae893
MK		 6131 const unsigned long *fields[] = {
6132 shadow_read_write_fields,
6133 shadow_read_only_fields
c3114420 6134 };
c2bae893 6135 const int max_fields[] = {
c3114420
AG		 6136 max_shadow_read_write_fields,
6137 max_shadow_read_only_fields
6138 };
6139 int i, q;
6140 unsigned long field;
6141 u64 field_value = 0;
6142 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6143
6144 vmcs_load(shadow_vmcs);
6145
c2bae893 6146 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6147 for (i = 0; i < max_fields[q]; i++) {
6148 field = fields[q][i];
6149 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6150
6151 switch (vmcs_field_type(field)) {
6152 case VMCS_FIELD_TYPE_U16:
6153 vmcs_write16(field, (u16)field_value);
6154 break;
6155 case VMCS_FIELD_TYPE_U32:
6156 vmcs_write32(field, (u32)field_value);
6157 break;
6158 case VMCS_FIELD_TYPE_U64:
6159 vmcs_write64(field, (u64)field_value);
6160 break;
6161 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6162 vmcs_writel(field, (long)field_value);
6163 break;
6164 }
6165 }
6166 }
6167
6168 vmcs_clear(shadow_vmcs);
6169 vmcs_load(vmx->loaded_vmcs->vmcs);
6170}
6171
49f705c5
NHE		 6172/*
6173 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6174 * used before) all generate the same failure when it is missing.
6175 */
6176static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6177{
6178 struct vcpu_vmx *vmx = to_vmx(vcpu);
6179 if (vmx->nested.current_vmptr == -1ull) {
6180 nested_vmx_failInvalid(vcpu);
6181 skip_emulated_instruction(vcpu);
6182 return 0;
6183 }
6184 return 1;
6185}
6186
6187static int handle_vmread(struct kvm_vcpu *vcpu)
6188{
6189 unsigned long field;
6190 u64 field_value;
6191 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6192 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6193 gva_t gva = 0;
6194
6195 if (!nested_vmx_check_permission(vcpu) ||
6196 !nested_vmx_check_vmcs12(vcpu))
6197 return 1;
6198
6199 /* Decode instruction info and find the field to read */
6200 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6201 /* Read the field, zero-extended to a u64 field_value */
6202 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6203 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6204 skip_emulated_instruction(vcpu);
6205 return 1;
6206 }
6207 /*
6208 * Now copy part of this value to register or memory, as requested.
6209 * Note that the number of bits actually copied is 32 or 64 depending
6210 * on the guest's mode (32 or 64 bit), not on the given field's length.
6211 */
6212 if (vmx_instruction_info & (1u << 10)) {
6213 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6214 field_value);
6215 } else {
6216 if (get_vmx_mem_address(vcpu, exit_qualification,
6217 vmx_instruction_info, &gva))
6218 return 1;
6219 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6220 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6221 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6222 }
6223
6224 nested_vmx_succeed(vcpu);
6225 skip_emulated_instruction(vcpu);
6226 return 1;
6227}
6228
6229
6230static int handle_vmwrite(struct kvm_vcpu *vcpu)
6231{
6232 unsigned long field;
6233 gva_t gva;
6234 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6235 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6236 /* The value to write might be 32 or 64 bits, depending on L1's long
6237 * mode, and eventually we need to write that into a field of several
6238 * possible lengths. The code below first zero-extends the value to 64
6239 * bit (field_value), and then copies only the approriate number of
6240 * bits into the vmcs12 field.
6241 */
6242 u64 field_value = 0;
6243 struct x86_exception e;
6244
6245 if (!nested_vmx_check_permission(vcpu) ||
6246 !nested_vmx_check_vmcs12(vcpu))
6247 return 1;
6248
6249 if (vmx_instruction_info & (1u << 10))
6250 field_value = kvm_register_read(vcpu,
6251 (((vmx_instruction_info) >> 3) & 0xf));
6252 else {
6253 if (get_vmx_mem_address(vcpu, exit_qualification,
6254 vmx_instruction_info, &gva))
6255 return 1;
6256 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6257 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6258 kvm_inject_page_fault(vcpu, &e);
6259 return 1;
6260 }
6261 }
6262
6263
6264 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6265 if (vmcs_field_readonly(field)) {
6266 nested_vmx_failValid(vcpu,
6267 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6268 skip_emulated_instruction(vcpu);
6269 return 1;
6270 }
6271
20b97fea 6272 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6273 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6274 skip_emulated_instruction(vcpu);
6275 return 1;
6276 }
6277
6278 nested_vmx_succeed(vcpu);
6279 skip_emulated_instruction(vcpu);
6280 return 1;
6281}
6282
63846663
NHE		 6283/* Emulate the VMPTRLD instruction */
6284static int handle_vmptrld(struct kvm_vcpu *vcpu)
6285{
6286 struct vcpu_vmx *vmx = to_vmx(vcpu);
6287 gva_t gva;
6288 gpa_t vmptr;
6289 struct x86_exception e;
8a1b9dd0 6290 u32 exec_control;
63846663
NHE		 6291
6292 if (!nested_vmx_check_permission(vcpu))
6293 return 1;
6294
6295 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6296 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6297 return 1;
6298
6299 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6300 sizeof(vmptr), &e)) {
6301 kvm_inject_page_fault(vcpu, &e);
6302 return 1;
6303 }
6304
6305 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6306 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6307 skip_emulated_instruction(vcpu);
6308 return 1;
6309 }
6310
6311 if (vmx->nested.current_vmptr != vmptr) {
6312 struct vmcs12 *new_vmcs12;
6313 struct page *page;
6314 page = nested_get_page(vcpu, vmptr);
6315 if (page == NULL) {
6316 nested_vmx_failInvalid(vcpu);
6317 skip_emulated_instruction(vcpu);
6318 return 1;
6319 }
6320 new_vmcs12 = kmap(page);
6321 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6322 kunmap(page);
6323 nested_release_page_clean(page);
6324 nested_vmx_failValid(vcpu,
6325 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6326 skip_emulated_instruction(vcpu);
6327 return 1;
6328 }
e7953d7f
AG		 6329 if (vmx->nested.current_vmptr != -1ull)
6330 nested_release_vmcs12(vmx);
63846663
NHE		 6331
6332 vmx->nested.current_vmptr = vmptr;
6333 vmx->nested.current_vmcs12 = new_vmcs12;
6334 vmx->nested.current_vmcs12_page = page;
012f83cb 6335 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6336 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6337 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6338 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6339 vmcs_write64(VMCS_LINK_POINTER,
6340 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6341 vmx->nested.sync_shadow_vmcs = true;
6342 }
63846663
NHE		 6343 }
6344
6345 nested_vmx_succeed(vcpu);
6346 skip_emulated_instruction(vcpu);
6347 return 1;
6348}
6349
6a4d7550
NHE		 6350/* Emulate the VMPTRST instruction */
6351static int handle_vmptrst(struct kvm_vcpu *vcpu)
6352{
6353 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6354 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6355 gva_t vmcs_gva;
6356 struct x86_exception e;
6357
6358 if (!nested_vmx_check_permission(vcpu))
6359 return 1;
6360
6361 if (get_vmx_mem_address(vcpu, exit_qualification,
6362 vmx_instruction_info, &vmcs_gva))
6363 return 1;
6364 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6365 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6366 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6367 sizeof(u64), &e)) {
6368 kvm_inject_page_fault(vcpu, &e);
6369 return 1;
6370 }
6371 nested_vmx_succeed(vcpu);
6372 skip_emulated_instruction(vcpu);
6373 return 1;
6374}
6375
bfd0a56b
NHE		 6376/* Emulate the INVEPT instruction */
6377static int handle_invept(struct kvm_vcpu *vcpu)
6378{
6379 u32 vmx_instruction_info, types;
6380 unsigned long type;
6381 gva_t gva;
6382 struct x86_exception e;
6383 struct {
6384 u64 eptp, gpa;
6385 } operand;
6386 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6387
6388 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6389 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6390 kvm_queue_exception(vcpu, UD_VECTOR);
6391 return 1;
6392 }
6393
6394 if (!nested_vmx_check_permission(vcpu))
6395 return 1;
6396
6397 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6398 kvm_queue_exception(vcpu, UD_VECTOR);
6399 return 1;
6400 }
6401
6402 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6403 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6404
6405 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6406
6407 if (!(types & (1UL << type))) {
6408 nested_vmx_failValid(vcpu,
6409 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6410 return 1;
6411 }
6412
6413 /* According to the Intel VMX instruction reference, the memory
6414 * operand is read even if it isn't needed (e.g., for type==global)
6415 */
6416 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6417 vmx_instruction_info, &gva))
6418 return 1;
6419 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6420 sizeof(operand), &e)) {
6421 kvm_inject_page_fault(vcpu, &e);
6422 return 1;
6423 }
6424
6425 switch (type) {
6426 case VMX_EPT_EXTENT_CONTEXT:
6427 if ((operand.eptp & eptp_mask) !=
6428 (nested_ept_get_cr3(vcpu) & eptp_mask))
6429 break;
6430 case VMX_EPT_EXTENT_GLOBAL:
6431 kvm_mmu_sync_roots(vcpu);
6432 kvm_mmu_flush_tlb(vcpu);
6433 nested_vmx_succeed(vcpu);
6434 break;
6435 default:
6436 BUG_ON(1);
6437 break;
6438 }
6439
6440 skip_emulated_instruction(vcpu);
6441 return 1;
6442}
6443
6aa8b732
AK		 6444/*
6445 * The exit handlers return 1 if the exit was handled fully and guest execution
6446 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6447 * to be done to userspace and return 0.
6448 */
772e0318 6449static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6450 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6451 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6452 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6453 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6454 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6455 [EXIT_REASON_CR_ACCESS] = handle_cr,
6456 [EXIT_REASON_DR_ACCESS] = handle_dr,
6457 [EXIT_REASON_CPUID] = handle_cpuid,
6458 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6459 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6460 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6461 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6462 [EXIT_REASON_INVD] = handle_invd,
a7052897 6463 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6464 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6465 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6466 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6467 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6468 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6469 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6470 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6471 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6472 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6473 [EXIT_REASON_VMOFF] = handle_vmoff,
6474 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6475 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6476 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6477 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6478 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6479 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6480 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6481 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6482 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6483 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6484 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6485 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6486 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6487 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6488 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6489};
6490
6491static const int kvm_vmx_max_exit_handlers =
50a3485c 6492 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6493
908a7bdd
JK		 6494static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6495 struct vmcs12 *vmcs12)
6496{
6497 unsigned long exit_qualification;
6498 gpa_t bitmap, last_bitmap;
6499 unsigned int port;
6500 int size;
6501 u8 b;
6502
908a7bdd 6503 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6504 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6505
6506 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6507
6508 port = exit_qualification >> 16;
6509 size = (exit_qualification & 7) + 1;
6510
6511 last_bitmap = (gpa_t)-1;
6512 b = -1;
6513
6514 while (size > 0) {
6515 if (port < 0x8000)
6516 bitmap = vmcs12->io_bitmap_a;
6517 else if (port < 0x10000)
6518 bitmap = vmcs12->io_bitmap_b;
6519 else
6520 return 1;
6521 bitmap += (port & 0x7fff) / 8;
6522
6523 if (last_bitmap != bitmap)
6524 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6525 return 1;
6526 if (b & (1 << (port & 7)))
6527 return 1;
6528
6529 port++;
6530 size--;
6531 last_bitmap = bitmap;
6532 }
6533
6534 return 0;
6535}
6536
644d711a
NHE		 6537/*
6538 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6539 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6540 * disinterest in the current event (read or write a specific MSR) by using an
6541 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6542 */
6543static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6544 struct vmcs12 *vmcs12, u32 exit_reason)
6545{
6546 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6547 gpa_t bitmap;
6548
cbd29cb6 6549 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6550 return 1;
6551
6552 /*
6553 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6554 * for the four combinations of read/write and low/high MSR numbers.
6555 * First we need to figure out which of the four to use:
6556 */
6557 bitmap = vmcs12->msr_bitmap;
6558 if (exit_reason == EXIT_REASON_MSR_WRITE)
6559 bitmap += 2048;
6560 if (msr_index >= 0xc0000000) {
6561 msr_index -= 0xc0000000;
6562 bitmap += 1024;
6563 }
6564
6565 /* Then read the msr_index'th bit from this bitmap: */
6566 if (msr_index < 1024*8) {
6567 unsigned char b;
bd31a7f5
JK		 6568 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6569 return 1;
644d711a
NHE		 6570 return 1 & (b >> (msr_index & 7));
6571 } else
6572 return 1; /* let L1 handle the wrong parameter */
6573}
6574
6575/*
6576 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6577 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6578 * intercept (via guest_host_mask etc.) the current event.
6579 */
6580static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6581 struct vmcs12 *vmcs12)
6582{
6583 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6584 int cr = exit_qualification & 15;
6585 int reg = (exit_qualification >> 8) & 15;
6586 unsigned long val = kvm_register_read(vcpu, reg);
6587
6588 switch ((exit_qualification >> 4) & 3) {
6589 case 0: /* mov to cr */
6590 switch (cr) {
6591 case 0:
6592 if (vmcs12->cr0_guest_host_mask &
6593 (val ^ vmcs12->cr0_read_shadow))
6594 return 1;
6595 break;
6596 case 3:
6597 if ((vmcs12->cr3_target_count >= 1 &&
6598 vmcs12->cr3_target_value0 == val) ||
6599 (vmcs12->cr3_target_count >= 2 &&
6600 vmcs12->cr3_target_value1 == val) ||
6601 (vmcs12->cr3_target_count >= 3 &&
6602 vmcs12->cr3_target_value2 == val) ||
6603 (vmcs12->cr3_target_count >= 4 &&
6604 vmcs12->cr3_target_value3 == val))
6605 return 0;
6606 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6607 return 1;
6608 break;
6609 case 4:
6610 if (vmcs12->cr4_guest_host_mask &
6611 (vmcs12->cr4_read_shadow ^ val))
6612 return 1;
6613 break;
6614 case 8:
6615 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6616 return 1;
6617 break;
6618 }
6619 break;
6620 case 2: /* clts */
6621 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6622 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6623 return 1;
6624 break;
6625 case 1: /* mov from cr */
6626 switch (cr) {
6627 case 3:
6628 if (vmcs12->cpu_based_vm_exec_control &
6629 CPU_BASED_CR3_STORE_EXITING)
6630 return 1;
6631 break;
6632 case 8:
6633 if (vmcs12->cpu_based_vm_exec_control &
6634 CPU_BASED_CR8_STORE_EXITING)
6635 return 1;
6636 break;
6637 }
6638 break;
6639 case 3: /* lmsw */
6640 /*
6641 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6642 * cr0. Other attempted changes are ignored, with no exit.
6643 */
6644 if (vmcs12->cr0_guest_host_mask & 0xe &
6645 (val ^ vmcs12->cr0_read_shadow))
6646 return 1;
6647 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6648 !(vmcs12->cr0_read_shadow & 0x1) &&
6649 (val & 0x1))
6650 return 1;
6651 break;
6652 }
6653 return 0;
6654}
6655
6656/*
6657 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6658 * should handle it ourselves in L0 (and then continue L2). Only call this
6659 * when in is_guest_mode (L2).
6660 */
6661static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6662{
644d711a
NHE		 6663 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6664 struct vcpu_vmx *vmx = to_vmx(vcpu);
6665 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6666 u32 exit_reason = vmx->exit_reason;
644d711a 6667
542060ea
JK		 6668 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6669 vmcs_readl(EXIT_QUALIFICATION),
6670 vmx->idt_vectoring_info,
6671 intr_info,
6672 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6673 KVM_ISA_VMX);
6674
644d711a
NHE		 6675 if (vmx->nested.nested_run_pending)
6676 return 0;
6677
6678 if (unlikely(vmx->fail)) {
bd80158a
JK		 6679 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6680 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6681 return 1;
6682 }
6683
6684 switch (exit_reason) {
6685 case EXIT_REASON_EXCEPTION_NMI:
6686 if (!is_exception(intr_info))
6687 return 0;
6688 else if (is_page_fault(intr_info))
6689 return enable_ept;
e504c909 6690 else if (is_no_device(intr_info) &&
1b385cbd 6691 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6692 return 0;
644d711a
NHE		 6693 return vmcs12->exception_bitmap &
6694 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6695 case EXIT_REASON_EXTERNAL_INTERRUPT:
6696 return 0;
6697 case EXIT_REASON_TRIPLE_FAULT:
6698 return 1;
6699 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6700 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6701 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6702 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6703 case EXIT_REASON_TASK_SWITCH:
6704 return 1;
6705 case EXIT_REASON_CPUID:
6706 return 1;
6707 case EXIT_REASON_HLT:
6708 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6709 case EXIT_REASON_INVD:
6710 return 1;
6711 case EXIT_REASON_INVLPG:
6712 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6713 case EXIT_REASON_RDPMC:
6714 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6715 case EXIT_REASON_RDTSC:
6716 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6717 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6718 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6719 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6720 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6721 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6722 case EXIT_REASON_INVEPT:
644d711a
NHE		 6723 /*
6724 * VMX instructions trap unconditionally. This allows L1 to
6725 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6726 */
6727 return 1;
6728 case EXIT_REASON_CR_ACCESS:
6729 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6730 case EXIT_REASON_DR_ACCESS:
6731 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6732 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6733 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6734 case EXIT_REASON_MSR_READ:
6735 case EXIT_REASON_MSR_WRITE:
6736 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6737 case EXIT_REASON_INVALID_STATE:
6738 return 1;
6739 case EXIT_REASON_MWAIT_INSTRUCTION:
6740 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6741 case EXIT_REASON_MONITOR_INSTRUCTION:
6742 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6743 case EXIT_REASON_PAUSE_INSTRUCTION:
6744 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6745 nested_cpu_has2(vmcs12,
6746 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6747 case EXIT_REASON_MCE_DURING_VMENTRY:
6748 return 0;
6749 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6750 return 1;
6751 case EXIT_REASON_APIC_ACCESS:
6752 return nested_cpu_has2(vmcs12,
6753 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6754 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6755 /*
6756 * L0 always deals with the EPT violation. If nested EPT is
6757 * used, and the nested mmu code discovers that the address is
6758 * missing in the guest EPT table (EPT12), the EPT violation
6759 * will be injected with nested_ept_inject_page_fault()
6760 */
6761 return 0;
644d711a 6762 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6763 /*
6764 * L2 never uses directly L1's EPT, but rather L0's own EPT
6765 * table (shadow on EPT) or a merged EPT table that L0 built
6766 * (EPT on EPT). So any problems with the structure of the
6767 * table is L0's fault.
6768 */
644d711a 6769 return 0;
0238ea91
JK		 6770 case EXIT_REASON_PREEMPTION_TIMER:
6771 return vmcs12->pin_based_vm_exec_control &
6772 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6773 case EXIT_REASON_WBINVD:
6774 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6775 case EXIT_REASON_XSETBV:
6776 return 1;
6777 default:
6778 return 1;
6779 }
6780}
6781
586f9607
AK		 6782static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6783{
6784 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6785 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6786}
6787
7854cbca
ACL		 6788static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6789{
6790 u64 delta_tsc_l1;
6791 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6792
6793 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6794 PIN_BASED_VMX_PREEMPTION_TIMER))
6795 return;
6796 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6797 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6798 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6799 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6800 - vcpu->arch.last_guest_tsc;
6801 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6802 if (preempt_val_l2 <= preempt_val_l1)
6803 preempt_val_l2 = 0;
6804 else
6805 preempt_val_l2 -= preempt_val_l1;
6806 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6807}
6808
6aa8b732
AK		 6809/*
6810 * The guest has exited. See if we can fix it or if we need userspace
6811 * assistance.
6812 */
851ba692 6813static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6814{
29bd8a78 6815 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6816 u32 exit_reason = vmx->exit_reason;
1155f76a 6817 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6818
80ced186 6819 /* If guest state is invalid, start emulating */
14168786 6820 if (vmx->emulation_required)
80ced186 6821 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6822
644d711a 6823 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6824 nested_vmx_vmexit(vcpu, exit_reason,
6825 vmcs_read32(VM_EXIT_INTR_INFO),
6826 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6827 return 1;
6828 }
6829
5120702e
MG		 6830 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6831 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6832 vcpu->run->fail_entry.hardware_entry_failure_reason
6833 = exit_reason;
6834 return 0;
6835 }
6836
29bd8a78 6837 if (unlikely(vmx->fail)) {
851ba692
AK		 6838 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6839 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6840 = vmcs_read32(VM_INSTRUCTION_ERROR);
6841 return 0;
6842 }
6aa8b732 6843
b9bf6882
XG		 6844 /*
6845 * Note:
6846 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6847 * delivery event since it indicates guest is accessing MMIO.
6848 * The vm-exit can be triggered again after return to guest that
6849 * will cause infinite loop.
6850 */
d77c26fc 6851 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6852 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6853 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6854 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6855 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6856 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6857 vcpu->run->internal.ndata = 2;
6858 vcpu->run->internal.data[0] = vectoring_info;
6859 vcpu->run->internal.data[1] = exit_reason;
6860 return 0;
6861 }
3b86cd99 6862
644d711a
NHE		 6863 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6864 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6865 get_vmcs12(vcpu))))) {
c4282df9 6866 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6867 vmx->soft_vnmi_blocked = 0;
3b86cd99 6868 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6869 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6870 /*
6871 * This CPU don't support us in finding the end of an
6872 * NMI-blocked window if the guest runs with IRQs
6873 * disabled. So we pull the trigger after 1 s of
6874 * futile waiting, but inform the user about this.
6875 */
6876 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6877 "state on VCPU %d after 1 s timeout\n",
6878 __func__, vcpu->vcpu_id);
6879 vmx->soft_vnmi_blocked = 0;
3b86cd99 6880 }
3b86cd99
JK		 6881 }
6882
6aa8b732
AK		 6883 if (exit_reason < kvm_vmx_max_exit_handlers
6884 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6885 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6886 else {
851ba692
AK		 6887 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6888 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6889 }
6890 return 0;
6891}
6892
95ba8273 6893static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6894{
95ba8273 6895 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6896 vmcs_write32(TPR_THRESHOLD, 0);
6897 return;
6898 }
6899
95ba8273 6900 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6901}
6902
8d14695f
YZ		 6903static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6904{
6905 u32 sec_exec_control;
6906
6907 /*
6908 * There is not point to enable virtualize x2apic without enable
6909 * apicv
6910 */
c7c9c56c
YZ		 6911 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6912 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6913 return;
6914
6915 if (!vm_need_tpr_shadow(vcpu->kvm))
6916 return;
6917
6918 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6919
6920 if (set) {
6921 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6922 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6923 } else {
6924 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6925 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6926 }
6927 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6928
6929 vmx_set_msr_bitmap(vcpu);
6930}
6931
c7c9c56c
YZ		 6932static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6933{
6934 u16 status;
6935 u8 old;
6936
6937 if (!vmx_vm_has_apicv(kvm))
6938 return;
6939
6940 if (isr == -1)
6941 isr = 0;
6942
6943 status = vmcs_read16(GUEST_INTR_STATUS);
6944 old = status >> 8;
6945 if (isr != old) {
6946 status &= 0xff;
6947 status |= isr << 8;
6948 vmcs_write16(GUEST_INTR_STATUS, status);
6949 }
6950}
6951
6952static void vmx_set_rvi(int vector)
6953{
6954 u16 status;
6955 u8 old;
6956
6957 status = vmcs_read16(GUEST_INTR_STATUS);
6958 old = (u8)status & 0xff;
6959 if ((u8)vector != old) {
6960 status &= ~0xff;
6961 status |= (u8)vector;
6962 vmcs_write16(GUEST_INTR_STATUS, status);
6963 }
6964}
6965
6966static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6967{
6968 if (max_irr == -1)
6969 return;
6970
6971 vmx_set_rvi(max_irr);
6972}
6973
6974static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6975{
3d81bc7e
YZ		 6976 if (!vmx_vm_has_apicv(vcpu->kvm))
6977 return;
6978
c7c9c56c
YZ		 6979 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6980 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6981 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6982 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6983}
6984
51aa01d1 6985static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6986{
00eba012
AK		 6987 u32 exit_intr_info;
6988
6989 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6990 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6991 return;
6992
c5ca8e57 6993 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6994 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6995
6996 /* Handle machine checks before interrupts are enabled */
00eba012 6997 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6998 kvm_machine_check();
6999
20f65983 7000 /* We need to handle NMIs before interrupts are enabled */
00eba012 7001 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7002 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7003 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7004 asm("int $2");
ff9d07a0
ZY		 7005 kvm_after_handle_nmi(&vmx->vcpu);
7006 }
51aa01d1 7007}
20f65983 7008
a547c6db
YZ		 7009static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7010{
7011 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7012
7013 /*
7014 * If external interrupt exists, IF bit is set in rflags/eflags on the
7015 * interrupt stack frame, and interrupt will be enabled on a return
7016 * from interrupt handler.
7017 */
7018 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7019 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7020 unsigned int vector;
7021 unsigned long entry;
7022 gate_desc *desc;
7023 struct vcpu_vmx *vmx = to_vmx(vcpu);
7024#ifdef CONFIG_X86_64
7025 unsigned long tmp;
7026#endif
7027
7028 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7029 desc = (gate_desc *)vmx->host_idt_base + vector;
7030 entry = gate_offset(*desc);
7031 asm volatile(
7032#ifdef CONFIG_X86_64
7033 "mov %%" _ASM_SP ", %[sp]\n\t"
7034 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7035 "push $%c[ss]\n\t"
7036 "push %[sp]\n\t"
7037#endif
7038 "pushf\n\t"
7039 "orl $0x200, (%%" _ASM_SP ")\n\t"
7040 __ASM_SIZE(push) " $%c[cs]\n\t"
7041 "call *%[entry]\n\t"
7042 :
7043#ifdef CONFIG_X86_64
7044 [sp]"=&r"(tmp)
7045#endif
7046 :
7047 [entry]"r"(entry),
7048 [ss]"i"(__KERNEL_DS),
7049 [cs]"i"(__KERNEL_CS)
7050 );
7051 } else
7052 local_irq_enable();
7053}
7054
51aa01d1
AK		 7055static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7056{
c5ca8e57 7057 u32 exit_intr_info;
51aa01d1
AK		 7058 bool unblock_nmi;
7059 u8 vector;
7060 bool idtv_info_valid;
7061
7062 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7063
cf393f75 7064 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7065 if (vmx->nmi_known_unmasked)
7066 return;
c5ca8e57
AK		 7067 /*
7068 * Can't use vmx->exit_intr_info since we're not sure what
7069 * the exit reason is.
7070 */
7071 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7072 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7073 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7074 /*
7b4a25cb 7075 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7076 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7077 * a guest IRET fault.
7b4a25cb
GN		 7078 * SDM 3: 23.2.2 (September 2008)
7079 * Bit 12 is undefined in any of the following cases:
7080 * If the VM exit sets the valid bit in the IDT-vectoring
7081 * information field.
7082 * If the VM exit is due to a double fault.
cf393f75 7083 */
7b4a25cb
GN		 7084 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7085 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7086 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7087 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7088 else
7089 vmx->nmi_known_unmasked =
7090 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7091 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7092 } else if (unlikely(vmx->soft_vnmi_blocked))
7093 vmx->vnmi_blocked_time +=
7094 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7095}
7096
3ab66e8a 7097static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7098 u32 idt_vectoring_info,
7099 int instr_len_field,
7100 int error_code_field)
51aa01d1 7101{
51aa01d1
AK		 7102 u8 vector;
7103 int type;
7104 bool idtv_info_valid;
7105
7106 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7107
3ab66e8a
JK		 7108 vcpu->arch.nmi_injected = false;
7109 kvm_clear_exception_queue(vcpu);
7110 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7111
7112 if (!idtv_info_valid)
7113 return;
7114
3ab66e8a 7115 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7116
668f612f
AK		 7117 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7118 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7119
64a7ec06 7120 switch (type) {
37b96e98 7121 case INTR_TYPE_NMI_INTR:
3ab66e8a 7122 vcpu->arch.nmi_injected = true;
668f612f 7123 /*
7b4a25cb 7124 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7125 * Clear bit "block by NMI" before VM entry if a NMI
7126 * delivery faulted.
668f612f 7127 */
3ab66e8a 7128 vmx_set_nmi_mask(vcpu, false);
37b96e98 7129 break;
37b96e98 7130 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7131 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7132 /* fall through */
7133 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7134 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7135 u32 err = vmcs_read32(error_code_field);
851eb667 7136 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7137 } else
851eb667 7138 kvm_requeue_exception(vcpu, vector);
37b96e98 7139 break;
66fd3f7f 7140 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7141 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7142 /* fall through */
37b96e98 7143 case INTR_TYPE_EXT_INTR:
3ab66e8a 7144 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7145 break;
7146 default:
7147 break;
f7d9238f 7148 }
cf393f75
AK		 7149}
7150
83422e17
AK		 7151static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7152{
3ab66e8a 7153 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7154 VM_EXIT_INSTRUCTION_LEN,
7155 IDT_VECTORING_ERROR_CODE);
7156}
7157
b463a6f7
AK		 7158static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7159{
3ab66e8a 7160 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7161 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7162 VM_ENTRY_INSTRUCTION_LEN,
7163 VM_ENTRY_EXCEPTION_ERROR_CODE);
7164
7165 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7166}
7167
d7cd9796
GN		 7168static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7169{
7170 int i, nr_msrs;
7171 struct perf_guest_switch_msr *msrs;
7172
7173 msrs = perf_guest_get_msrs(&nr_msrs);
7174
7175 if (!msrs)
7176 return;
7177
7178 for (i = 0; i < nr_msrs; i++)
7179 if (msrs[i].host == msrs[i].guest)
7180 clear_atomic_switch_msr(vmx, msrs[i].msr);
7181 else
7182 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7183 msrs[i].host);
7184}
7185
a3b5ba49 7186static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7187{
a2fa3e9f 7188 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7189 unsigned long debugctlmsr;
104f226b
AK		 7190
7191 /* Record the guest's net vcpu time for enforced NMI injections. */
7192 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7193 vmx->entry_time = ktime_get();
7194
7195 /* Don't enter VMX if guest state is invalid, let the exit handler
7196 start emulation until we arrive back to a valid state */
14168786 7197 if (vmx->emulation_required)
104f226b
AK		 7198 return;
7199
012f83cb
AG		 7200 if (vmx->nested.sync_shadow_vmcs) {
7201 copy_vmcs12_to_shadow(vmx);
7202 vmx->nested.sync_shadow_vmcs = false;
7203 }
7204
104f226b
AK		 7205 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7206 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7207 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7208 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7209
7210 /* When single-stepping over STI and MOV SS, we must clear the
7211 * corresponding interruptibility bits in the guest state. Otherwise
7212 * vmentry fails as it then expects bit 14 (BS) in pending debug
7213 * exceptions being set, but that's not correct for the guest debugging
7214 * case. */
7215 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7216 vmx_set_interrupt_shadow(vcpu, 0);
7217
d7cd9796 7218 atomic_switch_perf_msrs(vmx);
2a7921b7 7219 debugctlmsr = get_debugctlmsr();
d7cd9796 7220
7854cbca
ACL		 7221 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7222 nested_adjust_preemption_timer(vcpu);
d462b819 7223 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7224 asm(
6aa8b732 7225 /* Store host registers */
b188c81f
AK		 7226 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7227 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7228 "push %%" _ASM_CX " \n\t"
7229 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7230 "je 1f \n\t"
b188c81f 7231 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7232 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7233 "1: \n\t"
d3edefc0 7234 /* Reload cr2 if changed */
b188c81f
AK		 7235 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7236 "mov %%cr2, %%" _ASM_DX " \n\t"
7237 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7238 "je 2f \n\t"
b188c81f 7239 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7240 "2: \n\t"
6aa8b732 7241 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7242 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7243 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7244 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7245 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7246 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7247 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7248 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7249 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7250#ifdef CONFIG_X86_64
e08aa78a
AK		 7251 "mov %c[r8](%0), %%r8 \n\t"
7252 "mov %c[r9](%0), %%r9 \n\t"
7253 "mov %c[r10](%0), %%r10 \n\t"
7254 "mov %c[r11](%0), %%r11 \n\t"
7255 "mov %c[r12](%0), %%r12 \n\t"
7256 "mov %c[r13](%0), %%r13 \n\t"
7257 "mov %c[r14](%0), %%r14 \n\t"
7258 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7259#endif
b188c81f 7260 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7261
6aa8b732 7262 /* Enter guest mode */
83287ea4 7263 "jne 1f \n\t"
4ecac3fd 7264 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7265 "jmp 2f \n\t"
7266 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7267 "2: "
6aa8b732 7268 /* Save guest registers, load host registers, keep flags */
b188c81f 7269 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7270 "pop %0 \n\t"
b188c81f
AK		 7271 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7272 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7273 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7274 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7275 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7276 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7277 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7278#ifdef CONFIG_X86_64
e08aa78a
AK		 7279 "mov %%r8, %c[r8](%0) \n\t"
7280 "mov %%r9, %c[r9](%0) \n\t"
7281 "mov %%r10, %c[r10](%0) \n\t"
7282 "mov %%r11, %c[r11](%0) \n\t"
7283 "mov %%r12, %c[r12](%0) \n\t"
7284 "mov %%r13, %c[r13](%0) \n\t"
7285 "mov %%r14, %c[r14](%0) \n\t"
7286 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7287#endif
b188c81f
AK		 7288 "mov %%cr2, %%" _ASM_AX " \n\t"
7289 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7290
b188c81f 7291 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7292 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7293 ".pushsection .rodata \n\t"
7294 ".global vmx_return \n\t"
7295 "vmx_return: " _ASM_PTR " 2b \n\t"
7296 ".popsection"
e08aa78a 7297 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7298 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7299 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7300 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7301 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7302 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7303 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7304 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7305 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7306 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7307 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7308#ifdef CONFIG_X86_64
ad312c7c
ZX		 7309 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7310 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7311 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7312 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7313 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7314 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7315 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7316 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7317#endif
40712fae
AK		 7318 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7319 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7320 : "cc", "memory"
7321#ifdef CONFIG_X86_64
b188c81f 7322 , "rax", "rbx", "rdi", "rsi"
c2036300 7323 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7324#else
7325 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7326#endif
7327 );
6aa8b732 7328
2a7921b7
GN		 7329 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7330 if (debugctlmsr)
7331 update_debugctlmsr(debugctlmsr);
7332
aa67f609
AK		 7333#ifndef CONFIG_X86_64
7334 /*
7335 * The sysexit path does not restore ds/es, so we must set them to
7336 * a reasonable value ourselves.
7337 *
7338 * We can't defer this to vmx_load_host_state() since that function
7339 * may be executed in interrupt context, which saves and restore segments
7340 * around it, nullifying its effect.
7341 */
7342 loadsegment(ds, __USER_DS);
7343 loadsegment(es, __USER_DS);
7344#endif
7345
6de4f3ad 7346 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7347 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7348 | (1 << VCPU_EXREG_CPL)
aff48baa 7349 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7350 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7351 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7352 vcpu->arch.regs_dirty = 0;
7353
1155f76a
AK		 7354 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7355
d462b819 7356 vmx->loaded_vmcs->launched = 1;
1b6269db 7357
51aa01d1 7358 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7359 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7360
e0b890d3
GN		 7361 /*
7362 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7363 * we did not inject a still-pending event to L1 now because of
7364 * nested_run_pending, we need to re-enable this bit.
7365 */
7366 if (vmx->nested.nested_run_pending)
7367 kvm_make_request(KVM_REQ_EVENT, vcpu);
7368
7369 vmx->nested.nested_run_pending = 0;
7370
51aa01d1
AK		 7371 vmx_complete_atomic_exit(vmx);
7372 vmx_recover_nmi_blocking(vmx);
cf393f75 7373 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7374}
7375
6aa8b732
AK		 7376static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7377{
fb3f0f51
RR		 7378 struct vcpu_vmx *vmx = to_vmx(vcpu);
7379
cdbecfc3 7380 free_vpid(vmx);
d462b819 7381 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7382 free_nested(vmx);
fb3f0f51
RR		 7383 kfree(vmx->guest_msrs);
7384 kvm_vcpu_uninit(vcpu);
a4770347 7385 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7386}
7387
fb3f0f51 7388static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7389{
fb3f0f51 7390 int err;
c16f862d 7391 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7392 int cpu;
6aa8b732 7393
a2fa3e9f 7394 if (!vmx)
fb3f0f51
RR		 7395 return ERR_PTR(-ENOMEM);
7396
2384d2b3
SY		 7397 allocate_vpid(vmx);
7398
fb3f0f51
RR		 7399 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7400 if (err)
7401 goto free_vcpu;
965b58a5 7402
a2fa3e9f 7403 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7404 err = -ENOMEM;
fb3f0f51 7405 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7406 goto uninit_vcpu;
7407 }
965b58a5 7408
d462b819
NHE		 7409 vmx->loaded_vmcs = &vmx->vmcs01;
7410 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7411 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7412 goto free_msrs;
d462b819
NHE		 7413 if (!vmm_exclusive)
7414 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7415 loaded_vmcs_init(vmx->loaded_vmcs);
7416 if (!vmm_exclusive)
7417 kvm_cpu_vmxoff();
a2fa3e9f 7418
15ad7146
AK		 7419 cpu = get_cpu();
7420 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7421 vmx->vcpu.cpu = cpu;
8b9cf98c 7422 err = vmx_vcpu_setup(vmx);
fb3f0f51 7423 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7424 put_cpu();
fb3f0f51
RR		 7425 if (err)
7426 goto free_vmcs;
a63cb560 7427 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7428 err = alloc_apic_access_page(kvm);
7429 if (err)
5e4a0b3c 7430 goto free_vmcs;
a63cb560 7431 }
fb3f0f51 7432
b927a3ce
SY		 7433 if (enable_ept) {
7434 if (!kvm->arch.ept_identity_map_addr)
7435 kvm->arch.ept_identity_map_addr =
7436 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7437 err = -ENOMEM;
b7ebfb05
SY		 7438 if (alloc_identity_pagetable(kvm) != 0)
7439 goto free_vmcs;
93ea5388
GN		 7440 if (!init_rmode_identity_map(kvm))
7441 goto free_vmcs;
b927a3ce 7442 }
b7ebfb05 7443
a9d30f33
NHE		 7444 vmx->nested.current_vmptr = -1ull;
7445 vmx->nested.current_vmcs12 = NULL;
7446
fb3f0f51
RR		 7447 return &vmx->vcpu;
7448
7449free_vmcs:
5f3fbc34 7450 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7451free_msrs:
fb3f0f51
RR		 7452 kfree(vmx->guest_msrs);
7453uninit_vcpu:
7454 kvm_vcpu_uninit(&vmx->vcpu);
7455free_vcpu:
cdbecfc3 7456 free_vpid(vmx);
a4770347 7457 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7458 return ERR_PTR(err);
6aa8b732
AK		 7459}
7460
002c7f7c
YS		 7461static void __init vmx_check_processor_compat(void *rtn)
7462{
7463 struct vmcs_config vmcs_conf;
7464
7465 *(int *)rtn = 0;
7466 if (setup_vmcs_config(&vmcs_conf) < 0)
7467 *(int *)rtn = -EIO;
7468 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7469 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7470 smp_processor_id());
7471 *(int *)rtn = -EIO;
7472 }
7473}
7474
67253af5
SY		 7475static int get_ept_level(void)
7476{
7477 return VMX_EPT_DEFAULT_GAW + 1;
7478}
7479
4b12f0de 7480static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7481{
4b12f0de
SY		 7482 u64 ret;
7483
522c68c4
SY		 7484 /* For VT-d and EPT combination
7485 * 1. MMIO: always map as UC
7486 * 2. EPT with VT-d:
7487 * a. VT-d without snooping control feature: can't guarantee the
7488 * result, try to trust guest.
7489 * b. VT-d with snooping control feature: snooping control feature of
7490 * VT-d engine can guarantee the cache correctness. Just set it
7491 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7492 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7493 * consistent with host MTRR
7494 */
4b12f0de
SY		 7495 if (is_mmio)
7496 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7497 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7498 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7499 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7500 else
522c68c4 7501 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7502 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7503
7504 return ret;
64d4d521
SY		 7505}
7506
17cc3935 7507static int vmx_get_lpage_level(void)
344f414f 7508{
878403b7
SY		 7509 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7510 return PT_DIRECTORY_LEVEL;
7511 else
7512 /* For shadow and EPT supported 1GB page */
7513 return PT_PDPE_LEVEL;
344f414f
JR		 7514}
7515
0e851880
SY		 7516static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7517{
4e47c7a6
SY		 7518 struct kvm_cpuid_entry2 *best;
7519 struct vcpu_vmx *vmx = to_vmx(vcpu);
7520 u32 exec_control;
7521
7522 vmx->rdtscp_enabled = false;
7523 if (vmx_rdtscp_supported()) {
7524 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7525 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7526 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7527 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7528 vmx->rdtscp_enabled = true;
7529 else {
7530 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7531 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7532 exec_control);
7533 }
7534 }
7535 }
ad756a16 7536
ad756a16
MJ		 7537 /* Exposing INVPCID only when PCID is exposed */
7538 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7539 if (vmx_invpcid_supported() &&
4f977045 7540 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7541 guest_cpuid_has_pcid(vcpu)) {
29282fde 7542 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7543 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7544 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7545 exec_control);
7546 } else {
29282fde
TI		 7547 if (cpu_has_secondary_exec_ctrls()) {
7548 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7549 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7550 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7551 exec_control);
7552 }
ad756a16 7553 if (best)
4f977045 7554 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7555 }
0e851880
SY		 7556}
7557
d4330ef2
JR		 7558static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7559{
7b8050f5
NHE		 7560 if (func == 1 && nested)
7561 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7562}
7563
25d92081
YZ		 7564static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7565 struct x86_exception *fault)
7566{
533558bc
JK		 7567 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7568 u32 exit_reason;
25d92081
YZ		 7569
7570 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7571 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7572 else
533558bc
JK		 7573 exit_reason = EXIT_REASON_EPT_VIOLATION;
7574 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7575 vmcs12->guest_physical_address = fault->address;
7576}
7577
155a97a3
NHE		 7578/* Callbacks for nested_ept_init_mmu_context: */
7579
7580static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7581{
7582 /* return the page table to be shadowed - in our case, EPT12 */
7583 return get_vmcs12(vcpu)->ept_pointer;
7584}
7585
8a3c1a33 7586static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7587{
8a3c1a33 7588 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7589 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7590
7591 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7592 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7593 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7594
7595 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7596}
7597
7598static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7599{
7600 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7601}
7602
feaf0c7d
GN		 7603static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7604 struct x86_exception *fault)
7605{
7606 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7607
7608 WARN_ON(!is_guest_mode(vcpu));
7609
7610 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7611 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7612 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7613 vmcs_read32(VM_EXIT_INTR_INFO),
7614 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7615 else
7616 kvm_inject_page_fault(vcpu, fault);
7617}
7618
fe3ef05c
NHE		 7619/*
7620 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7621 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7622 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7623 * guest in a way that will both be appropriate to L1's requests, and our
7624 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7625 * function also has additional necessary side-effects, like setting various
7626 * vcpu->arch fields.
7627 */
7628static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7629{
7630 struct vcpu_vmx *vmx = to_vmx(vcpu);
7631 u32 exec_control;
7854cbca 7632 u32 exit_control;
fe3ef05c
NHE		 7633
7634 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7635 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7636 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7637 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7638 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7639 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7640 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7641 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7642 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7643 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7644 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7645 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7646 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7647 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7648 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7649 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7650 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7651 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7652 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7653 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7654 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7655 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7656 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7657 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7658 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7659 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7660 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7661 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7662 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7663 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7664 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7665 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7666 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7667 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7668 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7669 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7670
7671 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7672 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7673 vmcs12->vm_entry_intr_info_field);
7674 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7675 vmcs12->vm_entry_exception_error_code);
7676 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7677 vmcs12->vm_entry_instruction_len);
7678 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7679 vmcs12->guest_interruptibility_info);
fe3ef05c 7680 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7681 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7682 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7683 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7684 vmcs12->guest_pending_dbg_exceptions);
7685 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7686 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7687
7688 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7689
7690 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7691 (vmcs_config.pin_based_exec_ctrl |
7692 vmcs12->pin_based_vm_exec_control));
7693
0238ea91
JK		 7694 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7695 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7696 vmcs12->vmx_preemption_timer_value);
7697
fe3ef05c
NHE		 7698 /*
7699 * Whether page-faults are trapped is determined by a combination of
7700 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7701 * If enable_ept, L0 doesn't care about page faults and we should
7702 * set all of these to L1's desires. However, if !enable_ept, L0 does
7703 * care about (at least some) page faults, and because it is not easy
7704 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7705 * to exit on each and every L2 page fault. This is done by setting
7706 * MASK=MATCH=0 and (see below) EB.PF=1.
7707 * Note that below we don't need special code to set EB.PF beyond the
7708 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7709 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7710 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7711 *
7712 * A problem with this approach (when !enable_ept) is that L1 may be
7713 * injected with more page faults than it asked for. This could have
7714 * caused problems, but in practice existing hypervisors don't care.
7715 * To fix this, we will need to emulate the PFEC checking (on the L1
7716 * page tables), using walk_addr(), when injecting PFs to L1.
7717 */
7718 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7719 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7720 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7721 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7722
7723 if (cpu_has_secondary_exec_ctrls()) {
7724 u32 exec_control = vmx_secondary_exec_control(vmx);
7725 if (!vmx->rdtscp_enabled)
7726 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7727 /* Take the following fields only from vmcs12 */
7728 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7729 if (nested_cpu_has(vmcs12,
7730 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7731 exec_control |= vmcs12->secondary_vm_exec_control;
7732
7733 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7734 /*
7735 * Translate L1 physical address to host physical
7736 * address for vmcs02. Keep the page pinned, so this
7737 * physical address remains valid. We keep a reference
7738 * to it so we can release it later.
7739 */
7740 if (vmx->nested.apic_access_page) /* shouldn't happen */
7741 nested_release_page(vmx->nested.apic_access_page);
7742 vmx->nested.apic_access_page =
7743 nested_get_page(vcpu, vmcs12->apic_access_addr);
7744 /*
7745 * If translation failed, no matter: This feature asks
7746 * to exit when accessing the given address, and if it
7747 * can never be accessed, this feature won't do
7748 * anything anyway.
7749 */
7750 if (!vmx->nested.apic_access_page)
7751 exec_control &=
7752 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7753 else
7754 vmcs_write64(APIC_ACCESS_ADDR,
7755 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7756 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7757 exec_control |=
7758 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7759 vmcs_write64(APIC_ACCESS_ADDR,
7760 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7761 }
7762
7763 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7764 }
7765
7766
7767 /*
7768 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7769 * Some constant fields are set here by vmx_set_constant_host_state().
7770 * Other fields are different per CPU, and will be set later when
7771 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7772 */
a547c6db 7773 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7774
7775 /*
7776 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7777 * entry, but only if the current (host) sp changed from the value
7778 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7779 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7780 * here we just force the write to happen on entry.
7781 */
7782 vmx->host_rsp = 0;
7783
7784 exec_control = vmx_exec_control(vmx); /* L0's desires */
7785 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7786 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7787 exec_control &= ~CPU_BASED_TPR_SHADOW;
7788 exec_control |= vmcs12->cpu_based_vm_exec_control;
7789 /*
7790 * Merging of IO and MSR bitmaps not currently supported.
7791 * Rather, exit every time.
7792 */
7793 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7794 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7795 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7796
7797 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7798
7799 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7800 * bitwise-or of what L1 wants to trap for L2, and what we want to
7801 * trap. Note that CR0.TS also needs updating - we do this later.
7802 */
7803 update_exception_bitmap(vcpu);
7804 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7805 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7806
8049d651
NHE		 7807 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7808 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7809 * bits are further modified by vmx_set_efer() below.
7810 */
7854cbca
ACL		 7811 exit_control = vmcs_config.vmexit_ctrl;
7812 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7813 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2961e876 7814 vm_exit_controls_init(vmx, exit_control);
8049d651
NHE		 7815
7816 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7817 * emulated by vmx_set_efer(), below.
7818 */
2961e876 7819 vm_entry_controls_init(vmx,
8049d651
NHE		 7820 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7821 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7822 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7823
44811c02 7824 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7825 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7826 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7827 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7828 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7829
7830
7831 set_cr4_guest_host_mask(vmx);
7832
27fc51b2
NHE		 7833 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7834 vmcs_write64(TSC_OFFSET,
7835 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7836 else
7837 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7838
7839 if (enable_vpid) {
7840 /*
7841 * Trivially support vpid by letting L2s share their parent
7842 * L1's vpid. TODO: move to a more elaborate solution, giving
7843 * each L2 its own vpid and exposing the vpid feature to L1.
7844 */
7845 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7846 vmx_flush_tlb(vcpu);
7847 }
7848
155a97a3
NHE		 7849 if (nested_cpu_has_ept(vmcs12)) {
7850 kvm_mmu_unload(vcpu);
7851 nested_ept_init_mmu_context(vcpu);
7852 }
7853
fe3ef05c
NHE		 7854 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7855 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7856 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7857 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7858 else
7859 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7860 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7861 vmx_set_efer(vcpu, vcpu->arch.efer);
7862
7863 /*
7864 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7865 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7866 * The CR0_READ_SHADOW is what L2 should have expected to read given
7867 * the specifications by L1; It's not enough to take
7868 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7869 * have more bits than L1 expected.
7870 */
7871 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7872 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7873
7874 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7875 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7876
7877 /* shadow page tables on either EPT or shadow page tables */
7878 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7879 kvm_mmu_reset_context(vcpu);
7880
feaf0c7d
GN		 7881 if (!enable_ept)
7882 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7883
3633cfc3
NHE		 7884 /*
7885 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7886 */
7887 if (enable_ept) {
7888 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7889 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7890 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7891 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7892 }
7893
fe3ef05c
NHE		 7894 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7895 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7896}
7897
cd232ad0
NHE		 7898/*
7899 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7900 * for running an L2 nested guest.
7901 */
7902static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7903{
7904 struct vmcs12 *vmcs12;
7905 struct vcpu_vmx *vmx = to_vmx(vcpu);
7906 int cpu;
7907 struct loaded_vmcs *vmcs02;
384bb783 7908 bool ia32e;
cd232ad0
NHE		 7909
7910 if (!nested_vmx_check_permission(vcpu) ||
7911 !nested_vmx_check_vmcs12(vcpu))
7912 return 1;
7913
7914 skip_emulated_instruction(vcpu);
7915 vmcs12 = get_vmcs12(vcpu);
7916
012f83cb
AG		 7917 if (enable_shadow_vmcs)
7918 copy_shadow_to_vmcs12(vmx);
7919
7c177938
NHE		 7920 /*
7921 * The nested entry process starts with enforcing various prerequisites
7922 * on vmcs12 as required by the Intel SDM, and act appropriately when
7923 * they fail: As the SDM explains, some conditions should cause the
7924 * instruction to fail, while others will cause the instruction to seem
7925 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7926 * To speed up the normal (success) code path, we should avoid checking
7927 * for misconfigurations which will anyway be caught by the processor
7928 * when using the merged vmcs02.
7929 */
7930 if (vmcs12->launch_state == launch) {
7931 nested_vmx_failValid(vcpu,
7932 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7933 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7934 return 1;
7935 }
7936
6dfacadd
JK		 7937 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7938 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7939 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7940 return 1;
7941 }
7942
7c177938
NHE		 7943 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7944 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7945 /*TODO: Also verify bits beyond physical address width are 0*/
7946 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7947 return 1;
7948 }
7949
7950 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7951 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7952 /*TODO: Also verify bits beyond physical address width are 0*/
7953 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7954 return 1;
7955 }
7956
7957 if (vmcs12->vm_entry_msr_load_count > 0 ||
7958 vmcs12->vm_exit_msr_load_count > 0 ||
7959 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7960 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7961 __func__);
7c177938
NHE		 7962 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7963 return 1;
7964 }
7965
7966 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7967 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7968 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7969 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7970 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7971 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7972 !vmx_control_verify(vmcs12->vm_exit_controls,
7973 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7974 !vmx_control_verify(vmcs12->vm_entry_controls,
7975 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7976 {
7977 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7978 return 1;
7979 }
7980
7981 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7982 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7983 nested_vmx_failValid(vcpu,
7984 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7985 return 1;
7986 }
7987
92fbc7b1 7988 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7989 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7990 nested_vmx_entry_failure(vcpu, vmcs12,
7991 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7992 return 1;
7993 }
7994 if (vmcs12->vmcs_link_pointer != -1ull) {
7995 nested_vmx_entry_failure(vcpu, vmcs12,
7996 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7997 return 1;
7998 }
7999
384bb783 8000 /*
cb0c8cda 8001 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8002 * are performed on the field for the IA32_EFER MSR:
8003 * - Bits reserved in the IA32_EFER MSR must be 0.
8004 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8005 * the IA-32e mode guest VM-exit control. It must also be identical
8006 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8007 * CR0.PG) is 1.
8008 */
8009 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8010 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8011 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8012 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8013 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8014 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8015 nested_vmx_entry_failure(vcpu, vmcs12,
8016 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8017 return 1;
8018 }
8019 }
8020
8021 /*
8022 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8023 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8024 * the values of the LMA and LME bits in the field must each be that of
8025 * the host address-space size VM-exit control.
8026 */
8027 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8028 ia32e = (vmcs12->vm_exit_controls &
8029 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8030 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8031 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8032 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8033 nested_vmx_entry_failure(vcpu, vmcs12,
8034 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8035 return 1;
8036 }
8037 }
8038
7c177938
NHE		 8039 /*
8040 * We're finally done with prerequisite checking, and can start with
8041 * the nested entry.
8042 */
8043
cd232ad0
NHE		 8044 vmcs02 = nested_get_current_vmcs02(vmx);
8045 if (!vmcs02)
8046 return -ENOMEM;
8047
8048 enter_guest_mode(vcpu);
8049
8050 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8051
8052 cpu = get_cpu();
8053 vmx->loaded_vmcs = vmcs02;
8054 vmx_vcpu_put(vcpu);
8055 vmx_vcpu_load(vcpu, cpu);
8056 vcpu->cpu = cpu;
8057 put_cpu();
8058
36c3cc42
JK		 8059 vmx_segment_cache_clear(vmx);
8060
cd232ad0
NHE		 8061 vmcs12->launch_state = 1;
8062
8063 prepare_vmcs02(vcpu, vmcs12);
8064
6dfacadd
JK		 8065 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8066 return kvm_emulate_halt(vcpu);
8067
7af40ad3
JK		 8068 vmx->nested.nested_run_pending = 1;
8069
cd232ad0
NHE		 8070 /*
8071 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8072 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8073 * returned as far as L1 is concerned. It will only return (and set
8074 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8075 */
8076 return 1;
8077}
8078
4704d0be
NHE		 8079/*
8080 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8081 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8082 * This function returns the new value we should put in vmcs12.guest_cr0.
8083 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8084 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8085 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8086 * didn't trap the bit, because if L1 did, so would L0).
8087 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8088 * been modified by L2, and L1 knows it. So just leave the old value of
8089 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8090 * isn't relevant, because if L0 traps this bit it can set it to anything.
8091 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8092 * changed these bits, and therefore they need to be updated, but L0
8093 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8094 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8095 */
8096static inline unsigned long
8097vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8098{
8099 return
8100 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8101 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8102 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8103 vcpu->arch.cr0_guest_owned_bits));
8104}
8105
8106static inline unsigned long
8107vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8108{
8109 return
8110 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8111 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8112 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8113 vcpu->arch.cr4_guest_owned_bits));
8114}
8115
5f3d5799
JK		 8116static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8117 struct vmcs12 *vmcs12)
8118{
8119 u32 idt_vectoring;
8120 unsigned int nr;
8121
851eb667 8122 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8123 nr = vcpu->arch.exception.nr;
8124 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8125
8126 if (kvm_exception_is_soft(nr)) {
8127 vmcs12->vm_exit_instruction_len =
8128 vcpu->arch.event_exit_inst_len;
8129 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8130 } else
8131 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8132
8133 if (vcpu->arch.exception.has_error_code) {
8134 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8135 vmcs12->idt_vectoring_error_code =
8136 vcpu->arch.exception.error_code;
8137 }
8138
8139 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8140 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8141 vmcs12->idt_vectoring_info_field =
8142 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8143 } else if (vcpu->arch.interrupt.pending) {
8144 nr = vcpu->arch.interrupt.nr;
8145 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8146
8147 if (vcpu->arch.interrupt.soft) {
8148 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8149 vmcs12->vm_entry_instruction_len =
8150 vcpu->arch.event_exit_inst_len;
8151 } else
8152 idt_vectoring |= INTR_TYPE_EXT_INTR;
8153
8154 vmcs12->idt_vectoring_info_field = idt_vectoring;
8155 }
8156}
8157
4704d0be
NHE		 8158/*
8159 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8160 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8161 * and this function updates it to reflect the changes to the guest state while
8162 * L2 was running (and perhaps made some exits which were handled directly by L0
8163 * without going back to L1), and to reflect the exit reason.
8164 * Note that we do not have to copy here all VMCS fields, just those that
8165 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8166 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8167 * which already writes to vmcs12 directly.
8168 */
533558bc
JK		 8169static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8170 u32 exit_reason, u32 exit_intr_info,
8171 unsigned long exit_qualification)
4704d0be
NHE		 8172{
8173 /* update guest state fields: */
8174 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8175 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8176
8177 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8178 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8179 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8180 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8181
8182 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8183 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8184 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8185 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8186 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8187 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8188 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8189 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8190 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8191 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8192 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8193 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8194 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8195 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8196 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8197 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8198 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8199 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8200 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8201 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8202 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8203 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8204 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8205 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8206 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8207 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8208 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8209 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8210 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8211 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8212 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8213 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8214 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8215 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8216 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8217 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8218
4704d0be
NHE		 8219 vmcs12->guest_interruptibility_info =
8220 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8221 vmcs12->guest_pending_dbg_exceptions =
8222 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8223 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8224 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8225 else
8226 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8227
7854cbca
ACL		 8228 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8229 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8230 vmcs12->vmx_preemption_timer_value =
8231 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8232
3633cfc3
NHE		 8233 /*
8234 * In some cases (usually, nested EPT), L2 is allowed to change its
8235 * own CR3 without exiting. If it has changed it, we must keep it.
8236 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8237 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8238 *
8239 * Additionally, restore L2's PDPTR to vmcs12.
8240 */
8241 if (enable_ept) {
8242 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8243 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8244 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8245 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8246 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8247 }
8248
c18911a2
JK		 8249 vmcs12->vm_entry_controls =
8250 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8251 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8252
4704d0be
NHE		 8253 /* TODO: These cannot have changed unless we have MSR bitmaps and
8254 * the relevant bit asks not to trap the change */
8255 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8256 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8257 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8258 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8259 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8260 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8261 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8262 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8263
8264 /* update exit information fields: */
8265
533558bc
JK		 8266 vmcs12->vm_exit_reason = exit_reason;
8267 vmcs12->exit_qualification = exit_qualification;
4704d0be 8268
533558bc 8269 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8270 if ((vmcs12->vm_exit_intr_info &
8271 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8272 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8273 vmcs12->vm_exit_intr_error_code =
8274 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8275 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8276 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8277 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8278
5f3d5799
JK		 8279 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8280 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8281 * instead of reading the real value. */
4704d0be 8282 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8283
8284 /*
8285 * Transfer the event that L0 or L1 may wanted to inject into
8286 * L2 to IDT_VECTORING_INFO_FIELD.
8287 */
8288 vmcs12_save_pending_event(vcpu, vmcs12);
8289 }
8290
8291 /*
8292 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8293 * preserved above and would only end up incorrectly in L1.
8294 */
8295 vcpu->arch.nmi_injected = false;
8296 kvm_clear_exception_queue(vcpu);
8297 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8298}
8299
8300/*
8301 * A part of what we need to when the nested L2 guest exits and we want to
8302 * run its L1 parent, is to reset L1's guest state to the host state specified
8303 * in vmcs12.
8304 * This function is to be called not only on normal nested exit, but also on
8305 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8306 * Failures During or After Loading Guest State").
8307 * This function should be called when the active VMCS is L1's (vmcs01).
8308 */
733568f9
JK		 8309static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8310 struct vmcs12 *vmcs12)
4704d0be 8311{
21feb4eb
ACL		 8312 struct kvm_segment seg;
8313
4704d0be
NHE		 8314 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8315 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8316 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8317 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8318 else
8319 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8320 vmx_set_efer(vcpu, vcpu->arch.efer);
8321
8322 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8323 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8324 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8325 /*
8326 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8327 * actually changed, because it depends on the current state of
8328 * fpu_active (which may have changed).
8329 * Note that vmx_set_cr0 refers to efer set above.
8330 */
9e3e4dbf 8331 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8332 /*
8333 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8334 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8335 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8336 */
8337 update_exception_bitmap(vcpu);
8338 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8339 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8340
8341 /*
8342 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8343 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8344 */
8345 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8346 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8347
29bf08f1 8348 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8349
4704d0be
NHE		 8350 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8351 kvm_mmu_reset_context(vcpu);
8352
feaf0c7d
GN		 8353 if (!enable_ept)
8354 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8355
4704d0be
NHE		 8356 if (enable_vpid) {
8357 /*
8358 * Trivially support vpid by letting L2s share their parent
8359 * L1's vpid. TODO: move to a more elaborate solution, giving
8360 * each L2 its own vpid and exposing the vpid feature to L1.
8361 */
8362 vmx_flush_tlb(vcpu);
8363 }
8364
8365
8366 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8367 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8368 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8369 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8370 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8371
44811c02 8372 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8373 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8374 vcpu->arch.pat = vmcs12->host_ia32_pat;
8375 }
4704d0be
NHE		 8376 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8377 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8378 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8379
21feb4eb
ACL		 8380 /* Set L1 segment info according to Intel SDM
8381 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8382 seg = (struct kvm_segment) {
8383 .base = 0,
8384 .limit = 0xFFFFFFFF,
8385 .selector = vmcs12->host_cs_selector,
8386 .type = 11,
8387 .present = 1,
8388 .s = 1,
8389 .g = 1
8390 };
8391 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8392 seg.l = 1;
8393 else
8394 seg.db = 1;
8395 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8396 seg = (struct kvm_segment) {
8397 .base = 0,
8398 .limit = 0xFFFFFFFF,
8399 .type = 3,
8400 .present = 1,
8401 .s = 1,
8402 .db = 1,
8403 .g = 1
8404 };
8405 seg.selector = vmcs12->host_ds_selector;
8406 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8407 seg.selector = vmcs12->host_es_selector;
8408 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8409 seg.selector = vmcs12->host_ss_selector;
8410 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8411 seg.selector = vmcs12->host_fs_selector;
8412 seg.base = vmcs12->host_fs_base;
8413 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8414 seg.selector = vmcs12->host_gs_selector;
8415 seg.base = vmcs12->host_gs_base;
8416 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8417 seg = (struct kvm_segment) {
205befd9 8418 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8419 .limit = 0x67,
8420 .selector = vmcs12->host_tr_selector,
8421 .type = 11,
8422 .present = 1
8423 };
8424 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8425
503cd0c5
JK		 8426 kvm_set_dr(vcpu, 7, 0x400);
8427 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8428}
8429
8430/*
8431 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8432 * and modify vmcs12 to make it see what it would expect to see there if
8433 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8434 */
533558bc
JK		 8435static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8436 u32 exit_intr_info,
8437 unsigned long exit_qualification)
4704d0be
NHE		 8438{
8439 struct vcpu_vmx *vmx = to_vmx(vcpu);
8440 int cpu;
8441 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8442
5f3d5799
JK		 8443 /* trying to cancel vmlaunch/vmresume is a bug */
8444 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8445
4704d0be 8446 leave_guest_mode(vcpu);
533558bc
JK		 8447 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8448 exit_qualification);
4704d0be 8449
542060ea
JK		 8450 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8451 vmcs12->exit_qualification,
8452 vmcs12->idt_vectoring_info_field,
8453 vmcs12->vm_exit_intr_info,
8454 vmcs12->vm_exit_intr_error_code,
8455 KVM_ISA_VMX);
4704d0be
NHE		 8456
8457 cpu = get_cpu();
8458 vmx->loaded_vmcs = &vmx->vmcs01;
8459 vmx_vcpu_put(vcpu);
8460 vmx_vcpu_load(vcpu, cpu);
8461 vcpu->cpu = cpu;
8462 put_cpu();
8463
2961e876
GN		 8464 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8465 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8466 vmx_segment_cache_clear(vmx);
8467
4704d0be
NHE		 8468 /* if no vmcs02 cache requested, remove the one we used */
8469 if (VMCS02_POOL_SIZE == 0)
8470 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8471
8472 load_vmcs12_host_state(vcpu, vmcs12);
8473
27fc51b2 8474 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8475 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8476
8477 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8478 vmx->host_rsp = 0;
8479
8480 /* Unpin physical memory we referred to in vmcs02 */
8481 if (vmx->nested.apic_access_page) {
8482 nested_release_page(vmx->nested.apic_access_page);
8483 vmx->nested.apic_access_page = 0;
8484 }
8485
8486 /*
8487 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8488 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8489 * success or failure flag accordingly.
8490 */
8491 if (unlikely(vmx->fail)) {
8492 vmx->fail = 0;
8493 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8494 } else
8495 nested_vmx_succeed(vcpu);
012f83cb
AG		 8496 if (enable_shadow_vmcs)
8497 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8498}
8499
42124925
JK		 8500/*
8501 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8502 */
8503static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8504{
8505 if (is_guest_mode(vcpu))
533558bc 8506 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8507 free_nested(to_vmx(vcpu));
8508}
8509
7c177938
NHE		 8510/*
8511 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8512 * 23.7 "VM-entry failures during or after loading guest state" (this also
8513 * lists the acceptable exit-reason and exit-qualification parameters).
8514 * It should only be called before L2 actually succeeded to run, and when
8515 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8516 */
8517static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8518 struct vmcs12 *vmcs12,
8519 u32 reason, unsigned long qualification)
8520{
8521 load_vmcs12_host_state(vcpu, vmcs12);
8522 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8523 vmcs12->exit_qualification = qualification;
8524 nested_vmx_succeed(vcpu);
012f83cb
AG		 8525 if (enable_shadow_vmcs)
8526 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8527}
8528
8a76d7f2
JR		 8529static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8530 struct x86_instruction_info *info,
8531 enum x86_intercept_stage stage)
8532{
8533 return X86EMUL_CONTINUE;
8534}
8535
cbdd1bea 8536static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8537 .cpu_has_kvm_support = cpu_has_kvm_support,
8538 .disabled_by_bios = vmx_disabled_by_bios,
8539 .hardware_setup = hardware_setup,
8540 .hardware_unsetup = hardware_unsetup,
002c7f7c 8541 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8542 .hardware_enable = hardware_enable,
8543 .hardware_disable = hardware_disable,
04547156 8544 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8545
8546 .vcpu_create = vmx_create_vcpu,
8547 .vcpu_free = vmx_free_vcpu,
04d2cc77 8548 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8549
04d2cc77 8550 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8551 .vcpu_load = vmx_vcpu_load,
8552 .vcpu_put = vmx_vcpu_put,
8553
c8639010 8554 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8555 .get_msr = vmx_get_msr,
8556 .set_msr = vmx_set_msr,
8557 .get_segment_base = vmx_get_segment_base,
8558 .get_segment = vmx_get_segment,
8559 .set_segment = vmx_set_segment,
2e4d2653 8560 .get_cpl = vmx_get_cpl,
6aa8b732 8561 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8562 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8563 .decache_cr3 = vmx_decache_cr3,
25c4c276 8564 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8565 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8566 .set_cr3 = vmx_set_cr3,
8567 .set_cr4 = vmx_set_cr4,
6aa8b732 8568 .set_efer = vmx_set_efer,
6aa8b732
AK		 8569 .get_idt = vmx_get_idt,
8570 .set_idt = vmx_set_idt,
8571 .get_gdt = vmx_get_gdt,
8572 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8573 .get_dr6 = vmx_get_dr6,
8574 .set_dr6 = vmx_set_dr6,
020df079 8575 .set_dr7 = vmx_set_dr7,
5fdbf976 8576 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8577 .get_rflags = vmx_get_rflags,
8578 .set_rflags = vmx_set_rflags,
ebcbab4c 8579 .fpu_activate = vmx_fpu_activate,
02daab21 8580 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8581
8582 .tlb_flush = vmx_flush_tlb,
6aa8b732 8583
6aa8b732 8584 .run = vmx_vcpu_run,
6062d012 8585 .handle_exit = vmx_handle_exit,
6aa8b732 8586 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8587 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8588 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8589 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8590 .set_irq = vmx_inject_irq,
95ba8273 8591 .set_nmi = vmx_inject_nmi,
298101da 8592 .queue_exception = vmx_queue_exception,
b463a6f7 8593 .cancel_injection = vmx_cancel_injection,
78646121 8594 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8595 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8596 .get_nmi_mask = vmx_get_nmi_mask,
8597 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8598 .enable_nmi_window = enable_nmi_window,
8599 .enable_irq_window = enable_irq_window,
8600 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8601 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8602 .vm_has_apicv = vmx_vm_has_apicv,
8603 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8604 .hwapic_irr_update = vmx_hwapic_irr_update,
8605 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8606 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8607 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8608
cbc94022 8609 .set_tss_addr = vmx_set_tss_addr,
67253af5 8610 .get_tdp_level = get_ept_level,
4b12f0de 8611 .get_mt_mask = vmx_get_mt_mask,
229456fc 8612
586f9607 8613 .get_exit_info = vmx_get_exit_info,
586f9607 8614
17cc3935 8615 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8616
8617 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8618
8619 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8620 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8621
8622 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8623
8624 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8625
4051b188 8626 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8627 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8628 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8629 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8630 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8631 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8632
8633 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8634
8635 .check_intercept = vmx_check_intercept,
a547c6db 8636 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8637};
8638
8639static int __init vmx_init(void)
8640{
8d14695f 8641 int r, i, msr;
26bb0981
AK		 8642
8643 rdmsrl_safe(MSR_EFER, &host_efer);
8644
8645 for (i = 0; i < NR_VMX_MSR; ++i)
8646 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8647
3e7c73e9 8648 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8649 if (!vmx_io_bitmap_a)
8650 return -ENOMEM;
8651
2106a548
GC		 8652 r = -ENOMEM;
8653
3e7c73e9 8654 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8655 if (!vmx_io_bitmap_b)
fdef3ad1 8656 goto out;
fdef3ad1 8657
5897297b 8658 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8659 if (!vmx_msr_bitmap_legacy)
25c5f225 8660 goto out1;
2106a548 8661
8d14695f
YZ		 8662 vmx_msr_bitmap_legacy_x2apic =
8663 (unsigned long *)__get_free_page(GFP_KERNEL);
8664 if (!vmx_msr_bitmap_legacy_x2apic)
8665 goto out2;
25c5f225 8666
5897297b 8667 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8668 if (!vmx_msr_bitmap_longmode)
8d14695f 8669 goto out3;
2106a548 8670
8d14695f
YZ		 8671 vmx_msr_bitmap_longmode_x2apic =
8672 (unsigned long *)__get_free_page(GFP_KERNEL);
8673 if (!vmx_msr_bitmap_longmode_x2apic)
8674 goto out4;
4607c2d7
AG		 8675 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8676 if (!vmx_vmread_bitmap)
8677 goto out5;
8678
8679 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8680 if (!vmx_vmwrite_bitmap)
8681 goto out6;
8682
8683 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8684 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8685 /* shadowed read/write fields */
8686 for (i = 0; i < max_shadow_read_write_fields; i++) {
8687 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8688 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8689 }
8690 /* shadowed read only fields */
8691 for (i = 0; i < max_shadow_read_only_fields; i++)
8692 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8693
fdef3ad1
HQ		 8694 /*
8695 * Allow direct access to the PC debug port (it is often used for I/O
8696 * delays, but the vmexits simply slow things down).
8697 */
3e7c73e9
AK		 8698 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8699 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8700
3e7c73e9 8701 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8702
5897297b
AK		 8703 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8704 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8705
2384d2b3
SY		 8706 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8707
0ee75bea
AK		 8708 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8709 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8710 if (r)
4607c2d7 8711 goto out7;
25c5f225 8712
8f536b76
ZY		 8713#ifdef CONFIG_KEXEC
8714 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8715 crash_vmclear_local_loaded_vmcss);
8716#endif
8717
5897297b
AK		 8718 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8719 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8720 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8721 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8722 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8723 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8724 memcpy(vmx_msr_bitmap_legacy_x2apic,
8725 vmx_msr_bitmap_legacy, PAGE_SIZE);
8726 memcpy(vmx_msr_bitmap_longmode_x2apic,
8727 vmx_msr_bitmap_longmode, PAGE_SIZE);
8728
01e439be 8729 if (enable_apicv) {
8d14695f
YZ		 8730 for (msr = 0x800; msr <= 0x8ff; msr++)
8731 vmx_disable_intercept_msr_read_x2apic(msr);
8732
8733 /* According SDM, in x2apic mode, the whole id reg is used.
8734 * But in KVM, it only use the highest eight bits. Need to
8735 * intercept it */
8736 vmx_enable_intercept_msr_read_x2apic(0x802);
8737 /* TMCCT */
8738 vmx_enable_intercept_msr_read_x2apic(0x839);
8739 /* TPR */
8740 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8741 /* EOI */
8742 vmx_disable_intercept_msr_write_x2apic(0x80b);
8743 /* SELF-IPI */
8744 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8745 }
fdef3ad1 8746
089d034e 8747 if (enable_ept) {
3f6d8c8a
XH		 8748 kvm_mmu_set_mask_ptes(0ull,
8749 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8750 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8751 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8752 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8753 kvm_enable_tdp();
8754 } else
8755 kvm_disable_tdp();
1439442c 8756
fdef3ad1
HQ		 8757 return 0;
8758
4607c2d7
AG		 8759out7:
8760 free_page((unsigned long)vmx_vmwrite_bitmap);
8761out6:
8762 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8763out5:
8764 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8765out4:
5897297b 8766 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8767out3:
8768 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8769out2:
5897297b 8770 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8771out1:
3e7c73e9 8772 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8773out:
3e7c73e9 8774 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8775 return r;
6aa8b732
AK		 8776}
8777
8778static void __exit vmx_exit(void)
8779{
8d14695f
YZ		 8780 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8781 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8782 free_page((unsigned long)vmx_msr_bitmap_legacy);
8783 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8784 free_page((unsigned long)vmx_io_bitmap_b);
8785 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8786 free_page((unsigned long)vmx_vmwrite_bitmap);
8787 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8788
8f536b76
ZY		 8789#ifdef CONFIG_KEXEC
8790 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8791 synchronize_rcu();
8792#endif
8793
cb498ea2 8794 kvm_exit();
6aa8b732
AK		 8795}
8796
8797module_init(vmx_init)
8798module_exit(vmx_exit)
Linux kernel - Deliverables
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