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KVM: nVMX: Pass vmexit parameters to nested_vmx_vmexit
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
2961e876
GN		 421 u32 vm_entry_controls_shadow;
422 u32 vm_exit_controls_shadow;
d462b819
NHE		 423 /*
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
427 */
428 struct loaded_vmcs vmcs01;
429 struct loaded_vmcs *loaded_vmcs;
430 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 431 struct msr_autoload {
432 unsigned nr;
433 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
434 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
435 } msr_autoload;
a2fa3e9f
GH		 436 struct {
437 int loaded;
438 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 439#ifdef CONFIG_X86_64
440 u16 ds_sel, es_sel;
441#endif
152d3f2f
LV		 442 int gs_ldt_reload_needed;
443 int fs_reload_needed;
d77c26fc 444 } host_state;
9c8cba37 445 struct {
7ffd92c5 446 int vm86_active;
78ac8b47 447 ulong save_rflags;
f5f7b2fe
AK		 448 struct kvm_segment segs[8];
449 } rmode;
450 struct {
451 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 452 struct kvm_save_segment {
453 u16 selector;
454 unsigned long base;
455 u32 limit;
456 u32 ar;
f5f7b2fe 457 } seg[8];
2fb92db1 458 } segment_cache;
2384d2b3 459 int vpid;
04fa4d32 460 bool emulation_required;
3b86cd99
JK		 461
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked;
464 ktime_t entry_time;
465 s64 vnmi_blocked_time;
a0861c02 466 u32 exit_reason;
4e47c7a6
SY		 467
468 bool rdtscp_enabled;
ec378aee 469
01e439be
YZ		 470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc;
472
ec378aee
NHE		 473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested;
a2fa3e9f
GH		 475};
476
2fb92db1
AK		 477enum segment_cache_field {
478 SEG_FIELD_SEL = 0,
479 SEG_FIELD_BASE = 1,
480 SEG_FIELD_LIMIT = 2,
481 SEG_FIELD_AR = 3,
482
483 SEG_FIELD_NR = 4
484};
485
a2fa3e9f
GH		 486static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
487{
fb3f0f51 488 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 489}
490
22bd0358
NHE		 491#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
495
4607c2d7
AG		 496
497static const unsigned long shadow_read_only_fields[] = {
498 /*
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
509 */
510 VM_EXIT_REASON,
511 VM_EXIT_INTR_INFO,
512 VM_EXIT_INSTRUCTION_LEN,
513 IDT_VECTORING_INFO_FIELD,
514 IDT_VECTORING_ERROR_CODE,
515 VM_EXIT_INTR_ERROR_CODE,
516 EXIT_QUALIFICATION,
517 GUEST_LINEAR_ADDRESS,
518 GUEST_PHYSICAL_ADDRESS
519};
520static const int max_shadow_read_only_fields =
521 ARRAY_SIZE(shadow_read_only_fields);
522
523static const unsigned long shadow_read_write_fields[] = {
524 GUEST_RIP,
525 GUEST_RSP,
526 GUEST_CR0,
527 GUEST_CR3,
528 GUEST_CR4,
529 GUEST_INTERRUPTIBILITY_INFO,
530 GUEST_RFLAGS,
531 GUEST_CS_SELECTOR,
532 GUEST_CS_AR_BYTES,
533 GUEST_CS_LIMIT,
534 GUEST_CS_BASE,
535 GUEST_ES_BASE,
536 CR0_GUEST_HOST_MASK,
537 CR0_READ_SHADOW,
538 CR4_READ_SHADOW,
539 TSC_OFFSET,
540 EXCEPTION_BITMAP,
541 CPU_BASED_VM_EXEC_CONTROL,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 VM_ENTRY_INTR_INFO_FIELD,
544 VM_ENTRY_INSTRUCTION_LEN,
545 VM_ENTRY_EXCEPTION_ERROR_CODE,
546 HOST_FS_BASE,
547 HOST_GS_BASE,
548 HOST_FS_SELECTOR,
549 HOST_GS_SELECTOR
550};
551static const int max_shadow_read_write_fields =
552 ARRAY_SIZE(shadow_read_write_fields);
553
772e0318 554static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 555 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
556 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
557 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
558 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
559 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
560 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
561 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
562 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
563 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
564 FIELD(HOST_ES_SELECTOR, host_es_selector),
565 FIELD(HOST_CS_SELECTOR, host_cs_selector),
566 FIELD(HOST_SS_SELECTOR, host_ss_selector),
567 FIELD(HOST_DS_SELECTOR, host_ds_selector),
568 FIELD(HOST_FS_SELECTOR, host_fs_selector),
569 FIELD(HOST_GS_SELECTOR, host_gs_selector),
570 FIELD(HOST_TR_SELECTOR, host_tr_selector),
571 FIELD64(IO_BITMAP_A, io_bitmap_a),
572 FIELD64(IO_BITMAP_B, io_bitmap_b),
573 FIELD64(MSR_BITMAP, msr_bitmap),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
577 FIELD64(TSC_OFFSET, tsc_offset),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
579 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
580 FIELD64(EPT_POINTER, ept_pointer),
581 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
582 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
583 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
584 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
585 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
587 FIELD64(GUEST_PDPTR0, guest_pdptr0),
588 FIELD64(GUEST_PDPTR1, guest_pdptr1),
589 FIELD64(GUEST_PDPTR2, guest_pdptr2),
590 FIELD64(GUEST_PDPTR3, guest_pdptr3),
591 FIELD64(HOST_IA32_PAT, host_ia32_pat),
592 FIELD64(HOST_IA32_EFER, host_ia32_efer),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
596 FIELD(EXCEPTION_BITMAP, exception_bitmap),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
599 FIELD(CR3_TARGET_COUNT, cr3_target_count),
600 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
601 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
603 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
608 FIELD(TPR_THRESHOLD, tpr_threshold),
609 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
610 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
611 FIELD(VM_EXIT_REASON, vm_exit_reason),
612 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
613 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
614 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
615 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
616 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
617 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
618 FIELD(GUEST_ES_LIMIT, guest_es_limit),
619 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
620 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
621 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
622 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
623 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
624 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
625 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
626 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
627 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
628 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
629 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
630 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
631 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
632 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
633 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
634 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
635 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
637 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
638 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
639 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 640 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 641 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
642 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
643 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
644 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
645 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
646 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
647 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
648 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
649 FIELD(EXIT_QUALIFICATION, exit_qualification),
650 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
651 FIELD(GUEST_CR0, guest_cr0),
652 FIELD(GUEST_CR3, guest_cr3),
653 FIELD(GUEST_CR4, guest_cr4),
654 FIELD(GUEST_ES_BASE, guest_es_base),
655 FIELD(GUEST_CS_BASE, guest_cs_base),
656 FIELD(GUEST_SS_BASE, guest_ss_base),
657 FIELD(GUEST_DS_BASE, guest_ds_base),
658 FIELD(GUEST_FS_BASE, guest_fs_base),
659 FIELD(GUEST_GS_BASE, guest_gs_base),
660 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
661 FIELD(GUEST_TR_BASE, guest_tr_base),
662 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
663 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
664 FIELD(GUEST_DR7, guest_dr7),
665 FIELD(GUEST_RSP, guest_rsp),
666 FIELD(GUEST_RIP, guest_rip),
667 FIELD(GUEST_RFLAGS, guest_rflags),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
669 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
670 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
671 FIELD(HOST_CR0, host_cr0),
672 FIELD(HOST_CR3, host_cr3),
673 FIELD(HOST_CR4, host_cr4),
674 FIELD(HOST_FS_BASE, host_fs_base),
675 FIELD(HOST_GS_BASE, host_gs_base),
676 FIELD(HOST_TR_BASE, host_tr_base),
677 FIELD(HOST_GDTR_BASE, host_gdtr_base),
678 FIELD(HOST_IDTR_BASE, host_idtr_base),
679 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
680 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
681 FIELD(HOST_RSP, host_rsp),
682 FIELD(HOST_RIP, host_rip),
683};
684static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
685
686static inline short vmcs_field_to_offset(unsigned long field)
687{
688 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
689 return -1;
690 return vmcs_field_to_offset_table[field];
691}
692
a9d30f33
NHE		 693static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
694{
695 return to_vmx(vcpu)->nested.current_vmcs12;
696}
697
698static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
699{
700 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 701 if (is_error_page(page))
a9d30f33 702 return NULL;
32cad84f 703
a9d30f33
NHE		 704 return page;
705}
706
707static void nested_release_page(struct page *page)
708{
709 kvm_release_page_dirty(page);
710}
711
712static void nested_release_page_clean(struct page *page)
713{
714 kvm_release_page_clean(page);
715}
716
bfd0a56b 717static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 718static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 719static void kvm_cpu_vmxon(u64 addr);
720static void kvm_cpu_vmxoff(void);
776e58ea 721static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 722static void vmx_set_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724static void vmx_get_segment(struct kvm_vcpu *vcpu,
725 struct kvm_segment *var, int seg);
d99e4152
GN		 726static bool guest_state_valid(struct kvm_vcpu *vcpu);
727static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 728static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 729static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 730static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 731
6aa8b732
AK		 732static DEFINE_PER_CPU(struct vmcs *, vmxarea);
733static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 734/*
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
737 */
738static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 739static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 740
3e7c73e9
AK		 741static unsigned long *vmx_io_bitmap_a;
742static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 743static unsigned long *vmx_msr_bitmap_legacy;
744static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 745static unsigned long *vmx_msr_bitmap_legacy_x2apic;
746static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 747static unsigned long *vmx_vmread_bitmap;
748static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 749
110312c8 750static bool cpu_has_load_ia32_efer;
8bf00a52 751static bool cpu_has_load_perf_global_ctrl;
110312c8 752
2384d2b3
SY		 753static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
754static DEFINE_SPINLOCK(vmx_vpid_lock);
755
1c3d14fe 756static struct vmcs_config {
6aa8b732
AK		 757 int size;
758 int order;
759 u32 revision_id;
1c3d14fe
YS		 760 u32 pin_based_exec_ctrl;
761 u32 cpu_based_exec_ctrl;
f78e0e2e 762 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 763 u32 vmexit_ctrl;
764 u32 vmentry_ctrl;
765} vmcs_config;
6aa8b732 766
efff9e53 767static struct vmx_capability {
d56f546d
SY		 768 u32 ept;
769 u32 vpid;
770} vmx_capability;
771
6aa8b732
AK		 772#define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 }
779
772e0318 780static const struct kvm_vmx_segment_field {
6aa8b732
AK		 781 unsigned selector;
782 unsigned base;
783 unsigned limit;
784 unsigned ar_bytes;
785} kvm_vmx_segment_fields[] = {
786 VMX_SEGMENT_FIELD(CS),
787 VMX_SEGMENT_FIELD(DS),
788 VMX_SEGMENT_FIELD(ES),
789 VMX_SEGMENT_FIELD(FS),
790 VMX_SEGMENT_FIELD(GS),
791 VMX_SEGMENT_FIELD(SS),
792 VMX_SEGMENT_FIELD(TR),
793 VMX_SEGMENT_FIELD(LDTR),
794};
795
26bb0981
AK		 796static u64 host_efer;
797
6de4f3ad
AK		 798static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
799
4d56c8a7 800/*
8c06585d 801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 802 * away by decrementing the array size.
803 */
6aa8b732 804static const u32 vmx_msr_index[] = {
05b3e0c2 805#ifdef CONFIG_X86_64
44ea2b17 806 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 807#endif
8c06585d 808 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 809};
9d8f549d 810#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 811
31299944 812static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 813{
814 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
815 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 816 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 817}
818
31299944 819static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 820{
821 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
822 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 823 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 824}
825
31299944 826static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 831}
832
31299944 833static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
836 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
837}
838
31299944 839static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
843 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
844}
845
31299944 846static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 847{
04547156 848 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 852{
04547156 853 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 854}
855
31299944 856static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 857{
04547156 858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 859}
860
31299944 861static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 862{
04547156
SY		 863 return vmcs_config.cpu_based_exec_ctrl &
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 865}
866
774ead3a 867static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 868{
04547156
SY		 869 return vmcs_config.cpu_based_2nd_exec_ctrl &
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
871}
872
8d14695f
YZ		 873static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
874{
875 return vmcs_config.cpu_based_2nd_exec_ctrl &
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
877}
878
83d4c286
YZ		 879static inline bool cpu_has_vmx_apic_register_virt(void)
880{
881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_APIC_REGISTER_VIRT;
883}
884
c7c9c56c
YZ		 885static inline bool cpu_has_vmx_virtual_intr_delivery(void)
886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
889}
890
01e439be
YZ		 891static inline bool cpu_has_vmx_posted_intr(void)
892{
893 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
894}
895
896static inline bool cpu_has_vmx_apicv(void)
897{
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
901}
902
04547156
SY		 903static inline bool cpu_has_vmx_flexpriority(void)
904{
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 907}
908
e799794e
MT		 909static inline bool cpu_has_vmx_ept_execute_only(void)
910{
31299944 911 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 912}
913
914static inline bool cpu_has_vmx_eptp_uncacheable(void)
915{
31299944 916 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 917}
918
919static inline bool cpu_has_vmx_eptp_writeback(void)
920{
31299944 921 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 922}
923
924static inline bool cpu_has_vmx_ept_2m_page(void)
925{
31299944 926 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 927}
928
878403b7
SY		 929static inline bool cpu_has_vmx_ept_1g_page(void)
930{
31299944 931 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 932}
933
4bc9b982
SY		 934static inline bool cpu_has_vmx_ept_4levels(void)
935{
936 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
937}
938
83c3a331
XH		 939static inline bool cpu_has_vmx_ept_ad_bits(void)
940{
941 return vmx_capability.ept & VMX_EPT_AD_BIT;
942}
943
31299944 944static inline bool cpu_has_vmx_invept_context(void)
d56f546d 945{
31299944 946 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 947}
948
31299944 949static inline bool cpu_has_vmx_invept_global(void)
d56f546d 950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 952}
953
518c8aee
GJ		 954static inline bool cpu_has_vmx_invvpid_single(void)
955{
956 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
957}
958
b9d762fa
GJ		 959static inline bool cpu_has_vmx_invvpid_global(void)
960{
961 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
962}
963
31299944 964static inline bool cpu_has_vmx_ept(void)
d56f546d 965{
04547156
SY		 966 return vmcs_config.cpu_based_2nd_exec_ctrl &
967 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 968}
969
31299944 970static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 971{
972 return vmcs_config.cpu_based_2nd_exec_ctrl &
973 SECONDARY_EXEC_UNRESTRICTED_GUEST;
974}
975
31299944 976static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 977{
978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
980}
981
31299944 982static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 983{
6d3e435e 984 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 985}
986
31299944 987static inline bool cpu_has_vmx_vpid(void)
2384d2b3 988{
04547156
SY		 989 return vmcs_config.cpu_based_2nd_exec_ctrl &
990 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 991}
992
31299944 993static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 994{
995 return vmcs_config.cpu_based_2nd_exec_ctrl &
996 SECONDARY_EXEC_RDTSCP;
997}
998
ad756a16
MJ		 999static inline bool cpu_has_vmx_invpcid(void)
1000{
1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_ENABLE_INVPCID;
1003}
1004
31299944 1005static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1006{
1007 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008}
1009
f5f48ee1
SY		 1010static inline bool cpu_has_vmx_wbinvd_exit(void)
1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_WBINVD_EXITING;
1014}
1015
abc4fc58
AG		 1016static inline bool cpu_has_vmx_shadow_vmcs(void)
1017{
1018 u64 vmx_msr;
1019 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022 return false;
1023
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_SHADOW_VMCS;
1026}
1027
04547156
SY		 1028static inline bool report_flexpriority(void)
1029{
1030 return flexpriority_enabled;
1031}
1032
fe3ef05c
NHE		 1033static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1034{
1035 return vmcs12->cpu_based_vm_exec_control & bit;
1036}
1037
1038static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1039{
1040 return (vmcs12->cpu_based_vm_exec_control &
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1042 (vmcs12->secondary_vm_exec_control & bit);
1043}
1044
f5c4368f 1045static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
155a97a3
NHE		 1050static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051{
1052 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053}
1054
644d711a
NHE		 1055static inline bool is_exception(u32 intr_info)
1056{
1057 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059}
1060
533558bc
JK		 1061static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1062 u32 exit_intr_info,
1063 unsigned long exit_qualification);
7c177938
NHE		 1064static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1065 struct vmcs12 *vmcs12,
1066 u32 reason, unsigned long qualification);
1067
8b9cf98c 1068static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1069{
1070 int i;
1071
a2fa3e9f 1072 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1073 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1074 return i;
1075 return -1;
1076}
1077
2384d2b3
SY		 1078static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1079{
1080 struct {
1081 u64 vpid : 16;
1082 u64 rsvd : 48;
1083 u64 gva;
1084 } operand = { vpid, 0, gva };
1085
4ecac3fd 1086 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1087 /* CF==1 or ZF==1 --> rc = -1 */
1088 "; ja 1f ; ud2 ; 1:"
1089 : : "a"(&operand), "c"(ext) : "cc", "memory");
1090}
1091
1439442c
SY		 1092static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1093{
1094 struct {
1095 u64 eptp, gpa;
1096 } operand = {eptp, gpa};
1097
4ecac3fd 1098 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1099 /* CF==1 or ZF==1 --> rc = -1 */
1100 "; ja 1f ; ud2 ; 1:\n"
1101 : : "a" (&operand), "c" (ext) : "cc", "memory");
1102}
1103
26bb0981 1104static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1105{
1106 int i;
1107
8b9cf98c 1108 i = __find_msr_index(vmx, msr);
a75beee6 1109 if (i >= 0)
a2fa3e9f 1110 return &vmx->guest_msrs[i];
8b6d44c7 1111 return NULL;
7725f0ba
AK		 1112}
1113
6aa8b732
AK		 1114static void vmcs_clear(struct vmcs *vmcs)
1115{
1116 u64 phys_addr = __pa(vmcs);
1117 u8 error;
1118
4ecac3fd 1119 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1120 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1121 : "cc", "memory");
1122 if (error)
1123 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1124 vmcs, phys_addr);
1125}
1126
d462b819
NHE		 1127static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1128{
1129 vmcs_clear(loaded_vmcs->vmcs);
1130 loaded_vmcs->cpu = -1;
1131 loaded_vmcs->launched = 0;
1132}
1133
7725b894
DX		 1134static void vmcs_load(struct vmcs *vmcs)
1135{
1136 u64 phys_addr = __pa(vmcs);
1137 u8 error;
1138
1139 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1140 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1141 : "cc", "memory");
1142 if (error)
2844d849 1143 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1144 vmcs, phys_addr);
1145}
1146
8f536b76
ZY		 1147#ifdef CONFIG_KEXEC
1148/*
1149 * This bitmap is used to indicate whether the vmclear
1150 * operation is enabled on all cpus. All disabled by
1151 * default.
1152 */
1153static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1154
1155static inline void crash_enable_local_vmclear(int cpu)
1156{
1157 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1158}
1159
1160static inline void crash_disable_local_vmclear(int cpu)
1161{
1162 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1163}
1164
1165static inline int crash_local_vmclear_enabled(int cpu)
1166{
1167 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1168}
1169
1170static void crash_vmclear_local_loaded_vmcss(void)
1171{
1172 int cpu = raw_smp_processor_id();
1173 struct loaded_vmcs *v;
1174
1175 if (!crash_local_vmclear_enabled(cpu))
1176 return;
1177
1178 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1179 loaded_vmcss_on_cpu_link)
1180 vmcs_clear(v->vmcs);
1181}
1182#else
1183static inline void crash_enable_local_vmclear(int cpu) { }
1184static inline void crash_disable_local_vmclear(int cpu) { }
1185#endif /* CONFIG_KEXEC */
1186
d462b819 1187static void __loaded_vmcs_clear(void *arg)
6aa8b732 1188{
d462b819 1189 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1190 int cpu = raw_smp_processor_id();
6aa8b732 1191
d462b819
NHE		 1192 if (loaded_vmcs->cpu != cpu)
1193 return; /* vcpu migration can race with cpu offline */
1194 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1195 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1196 crash_disable_local_vmclear(cpu);
d462b819 1197 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1198
1199 /*
1200 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1201 * is before setting loaded_vmcs->vcpu to -1 which is done in
1202 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1203 * then adds the vmcs into percpu list before it is deleted.
1204 */
1205 smp_wmb();
1206
d462b819 1207 loaded_vmcs_init(loaded_vmcs);
8f536b76 1208 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1209}
1210
d462b819 1211static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1212{
e6c7d321
XG		 1213 int cpu = loaded_vmcs->cpu;
1214
1215 if (cpu != -1)
1216 smp_call_function_single(cpu,
1217 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1218}
1219
1760dd49 1220static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1221{
1222 if (vmx->vpid == 0)
1223 return;
1224
518c8aee
GJ		 1225 if (cpu_has_vmx_invvpid_single())
1226 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1227}
1228
b9d762fa
GJ		 1229static inline void vpid_sync_vcpu_global(void)
1230{
1231 if (cpu_has_vmx_invvpid_global())
1232 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1233}
1234
1235static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1236{
1237 if (cpu_has_vmx_invvpid_single())
1760dd49 1238 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1239 else
1240 vpid_sync_vcpu_global();
1241}
1242
1439442c
SY		 1243static inline void ept_sync_global(void)
1244{
1245 if (cpu_has_vmx_invept_global())
1246 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1247}
1248
1249static inline void ept_sync_context(u64 eptp)
1250{
089d034e 1251 if (enable_ept) {
1439442c
SY		 1252 if (cpu_has_vmx_invept_context())
1253 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1254 else
1255 ept_sync_global();
1256 }
1257}
1258
96304217 1259static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1260{
5e520e62 1261 unsigned long value;
6aa8b732 1262
5e520e62
AK		 1263 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1264 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1265 return value;
1266}
1267
96304217 1268static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1269{
1270 return vmcs_readl(field);
1271}
1272
96304217 1273static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1274{
1275 return vmcs_readl(field);
1276}
1277
96304217 1278static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1279{
05b3e0c2 1280#ifdef CONFIG_X86_64
6aa8b732
AK		 1281 return vmcs_readl(field);
1282#else
1283 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1284#endif
1285}
1286
e52de1b8
AK		 1287static noinline void vmwrite_error(unsigned long field, unsigned long value)
1288{
1289 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1290 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1291 dump_stack();
1292}
1293
6aa8b732
AK		 1294static void vmcs_writel(unsigned long field, unsigned long value)
1295{
1296 u8 error;
1297
4ecac3fd 1298 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1299 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1300 if (unlikely(error))
1301 vmwrite_error(field, value);
6aa8b732
AK		 1302}
1303
1304static void vmcs_write16(unsigned long field, u16 value)
1305{
1306 vmcs_writel(field, value);
1307}
1308
1309static void vmcs_write32(unsigned long field, u32 value)
1310{
1311 vmcs_writel(field, value);
1312}
1313
1314static void vmcs_write64(unsigned long field, u64 value)
1315{
6aa8b732 1316 vmcs_writel(field, value);
7682f2d0 1317#ifndef CONFIG_X86_64
6aa8b732
AK		 1318 asm volatile ("");
1319 vmcs_writel(field+1, value >> 32);
1320#endif
1321}
1322
2ab455cc
AL		 1323static void vmcs_clear_bits(unsigned long field, u32 mask)
1324{
1325 vmcs_writel(field, vmcs_readl(field) & ~mask);
1326}
1327
1328static void vmcs_set_bits(unsigned long field, u32 mask)
1329{
1330 vmcs_writel(field, vmcs_readl(field) | mask);
1331}
1332
2961e876
GN		 1333static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1334{
1335 vmcs_write32(VM_ENTRY_CONTROLS, val);
1336 vmx->vm_entry_controls_shadow = val;
1337}
1338
1339static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1340{
1341 if (vmx->vm_entry_controls_shadow != val)
1342 vm_entry_controls_init(vmx, val);
1343}
1344
1345static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1346{
1347 return vmx->vm_entry_controls_shadow;
1348}
1349
1350
1351static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1352{
1353 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1354}
1355
1356static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1357{
1358 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1359}
1360
1361static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1362{
1363 vmcs_write32(VM_EXIT_CONTROLS, val);
1364 vmx->vm_exit_controls_shadow = val;
1365}
1366
1367static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1368{
1369 if (vmx->vm_exit_controls_shadow != val)
1370 vm_exit_controls_init(vmx, val);
1371}
1372
1373static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1374{
1375 return vmx->vm_exit_controls_shadow;
1376}
1377
1378
1379static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1380{
1381 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1382}
1383
1384static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1385{
1386 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1387}
1388
2fb92db1
AK		 1389static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1390{
1391 vmx->segment_cache.bitmask = 0;
1392}
1393
1394static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1395 unsigned field)
1396{
1397 bool ret;
1398 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1399
1400 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1401 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1402 vmx->segment_cache.bitmask = 0;
1403 }
1404 ret = vmx->segment_cache.bitmask & mask;
1405 vmx->segment_cache.bitmask |= mask;
1406 return ret;
1407}
1408
1409static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1410{
1411 u16 *p = &vmx->segment_cache.seg[seg].selector;
1412
1413 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1414 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1415 return *p;
1416}
1417
1418static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1419{
1420 ulong *p = &vmx->segment_cache.seg[seg].base;
1421
1422 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1423 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1424 return *p;
1425}
1426
1427static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1428{
1429 u32 *p = &vmx->segment_cache.seg[seg].limit;
1430
1431 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1432 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1433 return *p;
1434}
1435
1436static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1437{
1438 u32 *p = &vmx->segment_cache.seg[seg].ar;
1439
1440 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1441 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1442 return *p;
1443}
1444
abd3f2d6
AK		 1445static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1446{
1447 u32 eb;
1448
fd7373cc
JK		 1449 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1450 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1451 if ((vcpu->guest_debug &
1452 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1453 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1454 eb |= 1u << BP_VECTOR;
7ffd92c5 1455 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1456 eb = ~0;
089d034e 1457 if (enable_ept)
1439442c 1458 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1459 if (vcpu->fpu_active)
1460 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1461
1462 /* When we are running a nested L2 guest and L1 specified for it a
1463 * certain exception bitmap, we must trap the same exceptions and pass
1464 * them to L1. When running L2, we will only handle the exceptions
1465 * specified above if L1 did not want them.
1466 */
1467 if (is_guest_mode(vcpu))
1468 eb |= get_vmcs12(vcpu)->exception_bitmap;
1469
abd3f2d6
AK		 1470 vmcs_write32(EXCEPTION_BITMAP, eb);
1471}
1472
2961e876
GN		 1473static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1474 unsigned long entry, unsigned long exit)
8bf00a52 1475{
2961e876
GN		 1476 vm_entry_controls_clearbit(vmx, entry);
1477 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1478}
1479
61d2ef2c
AK		 1480static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1481{
1482 unsigned i;
1483 struct msr_autoload *m = &vmx->msr_autoload;
1484
8bf00a52
GN		 1485 switch (msr) {
1486 case MSR_EFER:
1487 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1488 clear_atomic_switch_msr_special(vmx,
1489 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1490 VM_EXIT_LOAD_IA32_EFER);
1491 return;
1492 }
1493 break;
1494 case MSR_CORE_PERF_GLOBAL_CTRL:
1495 if (cpu_has_load_perf_global_ctrl) {
2961e876 1496 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1497 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1498 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1499 return;
1500 }
1501 break;
110312c8
AK		 1502 }
1503
61d2ef2c
AK		 1504 for (i = 0; i < m->nr; ++i)
1505 if (m->guest[i].index == msr)
1506 break;
1507
1508 if (i == m->nr)
1509 return;
1510 --m->nr;
1511 m->guest[i] = m->guest[m->nr];
1512 m->host[i] = m->host[m->nr];
1513 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1514 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1515}
1516
2961e876
GN		 1517static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1518 unsigned long entry, unsigned long exit,
1519 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1520 u64 guest_val, u64 host_val)
8bf00a52
GN		 1521{
1522 vmcs_write64(guest_val_vmcs, guest_val);
1523 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1524 vm_entry_controls_setbit(vmx, entry);
1525 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1526}
1527
61d2ef2c
AK		 1528static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1529 u64 guest_val, u64 host_val)
1530{
1531 unsigned i;
1532 struct msr_autoload *m = &vmx->msr_autoload;
1533
8bf00a52
GN		 1534 switch (msr) {
1535 case MSR_EFER:
1536 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1537 add_atomic_switch_msr_special(vmx,
1538 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1539 VM_EXIT_LOAD_IA32_EFER,
1540 GUEST_IA32_EFER,
1541 HOST_IA32_EFER,
1542 guest_val, host_val);
1543 return;
1544 }
1545 break;
1546 case MSR_CORE_PERF_GLOBAL_CTRL:
1547 if (cpu_has_load_perf_global_ctrl) {
2961e876 1548 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1549 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1550 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1551 GUEST_IA32_PERF_GLOBAL_CTRL,
1552 HOST_IA32_PERF_GLOBAL_CTRL,
1553 guest_val, host_val);
1554 return;
1555 }
1556 break;
110312c8
AK		 1557 }
1558
61d2ef2c
AK		 1559 for (i = 0; i < m->nr; ++i)
1560 if (m->guest[i].index == msr)
1561 break;
1562
e7fc6f93 1563 if (i == NR_AUTOLOAD_MSRS) {
60266204 1564 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1565 "Can't add msr %x\n", msr);
1566 return;
1567 } else if (i == m->nr) {
61d2ef2c
AK		 1568 ++m->nr;
1569 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1570 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1571 }
1572
1573 m->guest[i].index = msr;
1574 m->guest[i].value = guest_val;
1575 m->host[i].index = msr;
1576 m->host[i].value = host_val;
1577}
1578
33ed6329
AK		 1579static void reload_tss(void)
1580{
33ed6329
AK		 1581 /*
1582 * VT restores TR but not its size. Useless.
1583 */
d359192f 1584 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1585 struct desc_struct *descs;
33ed6329 1586
d359192f 1587 descs = (void *)gdt->address;
33ed6329
AK		 1588 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1589 load_TR_desc();
33ed6329
AK		 1590}
1591
92c0d900 1592static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1593{
3a34a881 1594 u64 guest_efer;
51c6cf66
AK		 1595 u64 ignore_bits;
1596
f6801dff 1597 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1598
51c6cf66 1599 /*
0fa06071 1600 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1601 * outside long mode
1602 */
1603 ignore_bits = EFER_NX | EFER_SCE;
1604#ifdef CONFIG_X86_64
1605 ignore_bits |= EFER_LMA | EFER_LME;
1606 /* SCE is meaningful only in long mode on Intel */
1607 if (guest_efer & EFER_LMA)
1608 ignore_bits &= ~(u64)EFER_SCE;
1609#endif
51c6cf66
AK		 1610 guest_efer &= ~ignore_bits;
1611 guest_efer |= host_efer & ignore_bits;
26bb0981 1612 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1613 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1614
1615 clear_atomic_switch_msr(vmx, MSR_EFER);
1616 /* On ept, can't emulate nx, and must switch nx atomically */
1617 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1618 guest_efer = vmx->vcpu.arch.efer;
1619 if (!(guest_efer & EFER_LMA))
1620 guest_efer &= ~EFER_LME;
1621 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1622 return false;
1623 }
1624
26bb0981 1625 return true;
51c6cf66
AK		 1626}
1627
2d49ec72
GN		 1628static unsigned long segment_base(u16 selector)
1629{
d359192f 1630 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1631 struct desc_struct *d;
1632 unsigned long table_base;
1633 unsigned long v;
1634
1635 if (!(selector & ~3))
1636 return 0;
1637
d359192f 1638 table_base = gdt->address;
2d49ec72
GN		 1639
1640 if (selector & 4) { /* from ldt */
1641 u16 ldt_selector = kvm_read_ldt();
1642
1643 if (!(ldt_selector & ~3))
1644 return 0;
1645
1646 table_base = segment_base(ldt_selector);
1647 }
1648 d = (struct desc_struct *)(table_base + (selector & ~7));
1649 v = get_desc_base(d);
1650#ifdef CONFIG_X86_64
1651 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1652 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1653#endif
1654 return v;
1655}
1656
1657static inline unsigned long kvm_read_tr_base(void)
1658{
1659 u16 tr;
1660 asm("str %0" : "=g"(tr));
1661 return segment_base(tr);
1662}
1663
04d2cc77 1664static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1665{
04d2cc77 1666 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1667 int i;
04d2cc77 1668
a2fa3e9f 1669 if (vmx->host_state.loaded)
33ed6329
AK		 1670 return;
1671
a2fa3e9f 1672 vmx->host_state.loaded = 1;
33ed6329
AK		 1673 /*
1674 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1675 * allow segment selectors with cpl > 0 or ti == 1.
1676 */
d6e88aec 1677 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1678 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1679 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1680 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1681 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1682 vmx->host_state.fs_reload_needed = 0;
1683 } else {
33ed6329 1684 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1685 vmx->host_state.fs_reload_needed = 1;
33ed6329 1686 }
9581d442 1687 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1688 if (!(vmx->host_state.gs_sel & 7))
1689 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1690 else {
1691 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1692 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1693 }
1694
b2da15ac
AK		 1695#ifdef CONFIG_X86_64
1696 savesegment(ds, vmx->host_state.ds_sel);
1697 savesegment(es, vmx->host_state.es_sel);
1698#endif
1699
33ed6329
AK		 1700#ifdef CONFIG_X86_64
1701 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1702 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1703#else
a2fa3e9f
GH		 1704 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1705 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1706#endif
707c0874
AK		 1707
1708#ifdef CONFIG_X86_64
c8770e7b
AK		 1709 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1710 if (is_long_mode(&vmx->vcpu))
44ea2b17 1711 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1712#endif
26bb0981
AK		 1713 for (i = 0; i < vmx->save_nmsrs; ++i)
1714 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1715 vmx->guest_msrs[i].data,
1716 vmx->guest_msrs[i].mask);
33ed6329
AK		 1717}
1718
a9b21b62 1719static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1720{
a2fa3e9f 1721 if (!vmx->host_state.loaded)
33ed6329
AK		 1722 return;
1723
e1beb1d3 1724 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1725 vmx->host_state.loaded = 0;
c8770e7b
AK		 1726#ifdef CONFIG_X86_64
1727 if (is_long_mode(&vmx->vcpu))
1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1729#endif
152d3f2f 1730 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1731 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1732#ifdef CONFIG_X86_64
9581d442 1733 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1734#else
1735 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1736#endif
33ed6329 1737 }
0a77fe4c
AK		 1738 if (vmx->host_state.fs_reload_needed)
1739 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1740#ifdef CONFIG_X86_64
1741 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1742 loadsegment(ds, vmx->host_state.ds_sel);
1743 loadsegment(es, vmx->host_state.es_sel);
1744 }
b2da15ac 1745#endif
152d3f2f 1746 reload_tss();
44ea2b17 1747#ifdef CONFIG_X86_64
c8770e7b 1748 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1749#endif
b1a74bf8
SS		 1750 /*
1751 * If the FPU is not active (through the host task or
1752 * the guest vcpu), then restore the cr0.TS bit.
1753 */
1754 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1755 stts();
3444d7da 1756 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1757}
1758
a9b21b62
AK		 1759static void vmx_load_host_state(struct vcpu_vmx *vmx)
1760{
1761 preempt_disable();
1762 __vmx_load_host_state(vmx);
1763 preempt_enable();
1764}
1765
6aa8b732
AK		 1766/*
1767 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1768 * vcpu mutex is already taken.
1769 */
15ad7146 1770static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1771{
a2fa3e9f 1772 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1773 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1774
4610c9cc
DX		 1775 if (!vmm_exclusive)
1776 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1777 else if (vmx->loaded_vmcs->cpu != cpu)
1778 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1779
d462b819
NHE		 1780 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1781 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1782 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1783 }
1784
d462b819 1785 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1786 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1787 unsigned long sysenter_esp;
1788
a8eeb04a 1789 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1790 local_irq_disable();
8f536b76 1791 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1792
1793 /*
1794 * Read loaded_vmcs->cpu should be before fetching
1795 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1796 * See the comments in __loaded_vmcs_clear().
1797 */
1798 smp_rmb();
1799
d462b819
NHE		 1800 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1801 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1802 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1803 local_irq_enable();
1804
6aa8b732
AK		 1805 /*
1806 * Linux uses per-cpu TSS and GDT, so set these when switching
1807 * processors.
1808 */
d6e88aec 1809 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1810 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1811
1812 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1813 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1814 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1815 }
6aa8b732
AK		 1816}
1817
1818static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1819{
a9b21b62 1820 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1821 if (!vmm_exclusive) {
d462b819
NHE		 1822 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1823 vcpu->cpu = -1;
4610c9cc
DX		 1824 kvm_cpu_vmxoff();
1825 }
6aa8b732
AK		 1826}
1827
5fd86fcf
AK		 1828static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1829{
81231c69
AK		 1830 ulong cr0;
1831
5fd86fcf
AK		 1832 if (vcpu->fpu_active)
1833 return;
1834 vcpu->fpu_active = 1;
81231c69
AK		 1835 cr0 = vmcs_readl(GUEST_CR0);
1836 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1837 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1838 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1839 update_exception_bitmap(vcpu);
edcafe3c 1840 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1841 if (is_guest_mode(vcpu))
1842 vcpu->arch.cr0_guest_owned_bits &=
1843 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1844 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1845}
1846
edcafe3c
AK		 1847static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1848
fe3ef05c
NHE		 1849/*
1850 * Return the cr0 value that a nested guest would read. This is a combination
1851 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1852 * its hypervisor (cr0_read_shadow).
1853 */
1854static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1855{
1856 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1857 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1858}
1859static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1860{
1861 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1862 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1863}
1864
5fd86fcf
AK		 1865static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1866{
36cf24e0
NHE		 1867 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1868 * set this *before* calling this function.
1869 */
edcafe3c 1870 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1871 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1872 update_exception_bitmap(vcpu);
edcafe3c
AK		 1873 vcpu->arch.cr0_guest_owned_bits = 0;
1874 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1875 if (is_guest_mode(vcpu)) {
1876 /*
1877 * L1's specified read shadow might not contain the TS bit,
1878 * so now that we turned on shadowing of this bit, we need to
1879 * set this bit of the shadow. Like in nested_vmx_run we need
1880 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1881 * up-to-date here because we just decached cr0.TS (and we'll
1882 * only update vmcs12->guest_cr0 on nested exit).
1883 */
1884 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1885 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1886 (vcpu->arch.cr0 & X86_CR0_TS);
1887 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1888 } else
1889 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1890}
1891
6aa8b732
AK		 1892static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1893{
78ac8b47 1894 unsigned long rflags, save_rflags;
345dcaa8 1895
6de12732
AK		 1896 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1897 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1898 rflags = vmcs_readl(GUEST_RFLAGS);
1899 if (to_vmx(vcpu)->rmode.vm86_active) {
1900 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1901 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1902 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1903 }
1904 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1905 }
6de12732 1906 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1907}
1908
1909static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1910{
6de12732
AK		 1911 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1912 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1913 if (to_vmx(vcpu)->rmode.vm86_active) {
1914 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1915 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1916 }
6aa8b732
AK		 1917 vmcs_writel(GUEST_RFLAGS, rflags);
1918}
1919
2809f5d2
GC		 1920static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1921{
1922 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1923 int ret = 0;
1924
1925 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1926 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1927 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1928 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1929
1930 return ret & mask;
1931}
1932
1933static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1934{
1935 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1936 u32 interruptibility = interruptibility_old;
1937
1938 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1939
48005f64 1940 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1941 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1942 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1943 interruptibility |= GUEST_INTR_STATE_STI;
1944
1945 if ((interruptibility != interruptibility_old))
1946 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1947}
1948
6aa8b732
AK		 1949static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1950{
1951 unsigned long rip;
6aa8b732 1952
5fdbf976 1953 rip = kvm_rip_read(vcpu);
6aa8b732 1954 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1955 kvm_rip_write(vcpu, rip);
6aa8b732 1956
2809f5d2
GC		 1957 /* skipping an emulated instruction also counts */
1958 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1959}
1960
0b6ac343
NHE		 1961/*
1962 * KVM wants to inject page-faults which it got to the guest. This function
1963 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1964 */
e011c663 1965static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1966{
1967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1968
e011c663 1969 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1970 return 0;
1971
533558bc
JK		 1972 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1973 vmcs_read32(VM_EXIT_INTR_INFO),
1974 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1975 return 1;
1976}
1977
298101da 1978static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1979 bool has_error_code, u32 error_code,
1980 bool reinject)
298101da 1981{
77ab6db0 1982 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1983 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1984
e011c663
GN		 1985 if (!reinject && is_guest_mode(vcpu) &&
1986 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1987 return;
1988
8ab2d2e2 1989 if (has_error_code) {
77ab6db0 1990 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1991 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1992 }
77ab6db0 1993
7ffd92c5 1994 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1995 int inc_eip = 0;
1996 if (kvm_exception_is_soft(nr))
1997 inc_eip = vcpu->arch.event_exit_inst_len;
1998 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1999 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2000 return;
2001 }
2002
66fd3f7f
GN		 2003 if (kvm_exception_is_soft(nr)) {
2004 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2005 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2006 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2007 } else
2008 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2009
2010 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2011}
2012
4e47c7a6
SY		 2013static bool vmx_rdtscp_supported(void)
2014{
2015 return cpu_has_vmx_rdtscp();
2016}
2017
ad756a16
MJ		 2018static bool vmx_invpcid_supported(void)
2019{
2020 return cpu_has_vmx_invpcid() && enable_ept;
2021}
2022
a75beee6
ED		 2023/*
2024 * Swap MSR entry in host/guest MSR entry array.
2025 */
8b9cf98c 2026static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2027{
26bb0981 2028 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2029
2030 tmp = vmx->guest_msrs[to];
2031 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2032 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2033}
2034
8d14695f
YZ		 2035static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2036{
2037 unsigned long *msr_bitmap;
2038
2039 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2040 if (is_long_mode(vcpu))
2041 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2042 else
2043 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2044 } else {
2045 if (is_long_mode(vcpu))
2046 msr_bitmap = vmx_msr_bitmap_longmode;
2047 else
2048 msr_bitmap = vmx_msr_bitmap_legacy;
2049 }
2050
2051 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2052}
2053
e38aea3e
AK		 2054/*
2055 * Set up the vmcs to automatically save and restore system
2056 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2057 * mode, as fiddling with msrs is very expensive.
2058 */
8b9cf98c 2059static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2060{
26bb0981 2061 int save_nmsrs, index;
e38aea3e 2062
a75beee6
ED		 2063 save_nmsrs = 0;
2064#ifdef CONFIG_X86_64
8b9cf98c 2065 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2066 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2067 if (index >= 0)
8b9cf98c
RR		 2068 move_msr_up(vmx, index, save_nmsrs++);
2069 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2070 if (index >= 0)
8b9cf98c
RR		 2071 move_msr_up(vmx, index, save_nmsrs++);
2072 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2073 if (index >= 0)
8b9cf98c 2074 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2075 index = __find_msr_index(vmx, MSR_TSC_AUX);
2076 if (index >= 0 && vmx->rdtscp_enabled)
2077 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2078 /*
8c06585d 2079 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2080 * if efer.sce is enabled.
2081 */
8c06585d 2082 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2083 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2084 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2085 }
2086#endif
92c0d900
AK		 2087 index = __find_msr_index(vmx, MSR_EFER);
2088 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2089 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2090
26bb0981 2091 vmx->save_nmsrs = save_nmsrs;
5897297b 2092
8d14695f
YZ		 2093 if (cpu_has_vmx_msr_bitmap())
2094 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2095}
2096
6aa8b732
AK		 2097/*
2098 * reads and returns guest's timestamp counter "register"
2099 * guest_tsc = host_tsc + tsc_offset -- 21.3
2100 */
2101static u64 guest_read_tsc(void)
2102{
2103 u64 host_tsc, tsc_offset;
2104
2105 rdtscll(host_tsc);
2106 tsc_offset = vmcs_read64(TSC_OFFSET);
2107 return host_tsc + tsc_offset;
2108}
2109
d5c1785d
NHE		 2110/*
2111 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2112 * counter, even if a nested guest (L2) is currently running.
2113 */
886b470c 2114u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2115{
886b470c 2116 u64 tsc_offset;
d5c1785d 2117
d5c1785d
NHE		 2118 tsc_offset = is_guest_mode(vcpu) ?
2119 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2120 vmcs_read64(TSC_OFFSET);
2121 return host_tsc + tsc_offset;
2122}
2123
4051b188 2124/*
cc578287
ZA		 2125 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2126 * software catchup for faster rates on slower CPUs.
4051b188 2127 */
cc578287 2128static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2129{
cc578287
ZA		 2130 if (!scale)
2131 return;
2132
2133 if (user_tsc_khz > tsc_khz) {
2134 vcpu->arch.tsc_catchup = 1;
2135 vcpu->arch.tsc_always_catchup = 1;
2136 } else
2137 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2138}
2139
ba904635
WA		 2140static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2141{
2142 return vmcs_read64(TSC_OFFSET);
2143}
2144
6aa8b732 2145/*
99e3e30a 2146 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2147 */
99e3e30a 2148static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2149{
27fc51b2 2150 if (is_guest_mode(vcpu)) {
7991825b 2151 /*
27fc51b2
NHE		 2152 * We're here if L1 chose not to trap WRMSR to TSC. According
2153 * to the spec, this should set L1's TSC; The offset that L1
2154 * set for L2 remains unchanged, and still needs to be added
2155 * to the newly set TSC to get L2's TSC.
7991825b 2156 */
27fc51b2
NHE		 2157 struct vmcs12 *vmcs12;
2158 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2159 /* recalculate vmcs02.TSC_OFFSET: */
2160 vmcs12 = get_vmcs12(vcpu);
2161 vmcs_write64(TSC_OFFSET, offset +
2162 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2163 vmcs12->tsc_offset : 0));
2164 } else {
489223ed
YY		 2165 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2166 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2167 vmcs_write64(TSC_OFFSET, offset);
2168 }
6aa8b732
AK		 2169}
2170
f1e2b260 2171static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2172{
2173 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2174
e48672fa 2175 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2176 if (is_guest_mode(vcpu)) {
2177 /* Even when running L2, the adjustment needs to apply to L1 */
2178 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2179 } else
2180 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2181 offset + adjustment);
e48672fa
ZA		 2182}
2183
857e4099
JR		 2184static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2185{
2186 return target_tsc - native_read_tsc();
2187}
2188
801d3424
NHE		 2189static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2190{
2191 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2192 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2193}
2194
2195/*
2196 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2197 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2198 * all guests if the "nested" module option is off, and can also be disabled
2199 * for a single guest by disabling its VMX cpuid bit.
2200 */
2201static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2202{
2203 return nested && guest_cpuid_has_vmx(vcpu);
2204}
2205
b87a51ae
NHE		 2206/*
2207 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2208 * returned for the various VMX controls MSRs when nested VMX is enabled.
2209 * The same values should also be used to verify that vmcs12 control fields are
2210 * valid during nested entry from L1 to L2.
2211 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2212 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2213 * bit in the high half is on if the corresponding bit in the control field
2214 * may be on. See also vmx_control_verify().
2215 * TODO: allow these variables to be modified (downgraded) by module options
2216 * or other means.
2217 */
2218static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2219static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2220static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2221static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2222static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2223static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2224static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2225static __init void nested_vmx_setup_ctls_msrs(void)
2226{
2227 /*
2228 * Note that as a general rule, the high half of the MSRs (bits in
2229 * the control fields which may be 1) should be initialized by the
2230 * intersection of the underlying hardware's MSR (i.e., features which
2231 * can be supported) and the list of features we want to expose -
2232 * because they are known to be properly supported in our code.
2233 * Also, usually, the low half of the MSRs (bits which must be 1) can
2234 * be set to 0, meaning that L1 may turn off any of these bits. The
2235 * reason is that if one of these bits is necessary, it will appear
2236 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2237 * fields of vmcs01 and vmcs02, will turn these bits off - and
2238 * nested_vmx_exit_handled() will not pass related exits to L1.
2239 * These rules have exceptions below.
2240 */
2241
2242 /* pin-based controls */
eabeaacc
JK		 2243 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2244 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2245 /*
2246 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2247 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2248 */
eabeaacc
JK		 2249 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2250 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2251 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2252 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2253 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2254
33fb20c3
JK		 2255 /*
2256 * Exit controls
2257 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2258 * 17 must be 1.
2259 */
c0dfee58
ACL		 2260 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2261 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2262 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2263 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2264 nested_vmx_exit_ctls_high &=
b87a51ae 2265#ifdef CONFIG_X86_64
c0dfee58 2266 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2267#endif
7854cbca
ACL		 2268 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2269 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2270 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2271 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2272 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2273 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2274 }
8049d651 2275 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2276 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2277
2278 /* entry controls */
2279 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2280 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2281 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2282 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2283 nested_vmx_entry_ctls_high &=
57435349
JK		 2284#ifdef CONFIG_X86_64
2285 VM_ENTRY_IA32E_MODE |
2286#endif
2287 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2288 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2289 VM_ENTRY_LOAD_IA32_EFER);
57435349 2290
b87a51ae
NHE		 2291 /* cpu-based controls */
2292 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2293 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2294 nested_vmx_procbased_ctls_low = 0;
2295 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2296 CPU_BASED_VIRTUAL_INTR_PENDING |
2297 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2298 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2299 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2300 CPU_BASED_CR3_STORE_EXITING |
2301#ifdef CONFIG_X86_64
2302 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2303#endif
2304 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2305 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2306 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2307 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2309 /*
2310 * We can allow some features even when not supported by the
2311 * hardware. For example, L1 can specify an MSR bitmap - and we
2312 * can use it to avoid exits to L1 - even when L0 runs L2
2313 * without MSR bitmaps.
2314 */
2315 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2316
2317 /* secondary cpu-based controls */
2318 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2319 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2320 nested_vmx_secondary_ctls_low = 0;
2321 nested_vmx_secondary_ctls_high &=
d6851fbe 2322 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2323 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2324 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2325
afa61f75
NHE		 2326 if (enable_ept) {
2327 /* nested EPT: emulate EPT also to L1 */
2328 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2329 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2330 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2331 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2332 nested_vmx_ept_caps &= vmx_capability.ept;
2333 /*
2334 * Since invept is completely emulated we support both global
2335 * and context invalidation independent of what host cpu
2336 * supports
2337 */
2338 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2339 VMX_EPT_EXTENT_CONTEXT_BIT;
2340 } else
2341 nested_vmx_ept_caps = 0;
2342
c18911a2
JK		 2343 /* miscellaneous data */
2344 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2345 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2346 VMX_MISC_SAVE_EFER_LMA;
6dfacadd 2347 nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
c18911a2 2348 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2349}
2350
2351static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2352{
2353 /*
2354 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2355 */
2356 return ((control & high) | low) == control;
2357}
2358
2359static inline u64 vmx_control_msr(u32 low, u32 high)
2360{
2361 return low | ((u64)high << 32);
2362}
2363
2364/*
2365 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2366 * also let it use VMX-specific MSRs.
2367 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2368 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2369 * like all other MSRs).
2370 */
2371static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2372{
2373 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2374 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2375 /*
2376 * According to the spec, processors which do not support VMX
2377 * should throw a #GP(0) when VMX capability MSRs are read.
2378 */
2379 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2380 return 1;
2381 }
2382
2383 switch (msr_index) {
2384 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2385 if (nested_vmx_allowed(vcpu)) {
2386 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2387 break;
2388 }
2389 return 0;
b87a51ae
NHE		 2390 case MSR_IA32_VMX_BASIC:
2391 /*
2392 * This MSR reports some information about VMX support. We
2393 * should return information about the VMX we emulate for the
2394 * guest, and the VMCS structure we give it - not about the
2395 * VMX support of the underlying hardware.
2396 */
2397 *pdata = VMCS12_REVISION |
2398 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400 break;
2401 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402 case MSR_IA32_VMX_PINBASED_CTLS:
2403 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404 nested_vmx_pinbased_ctls_high);
2405 break;
2406 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407 case MSR_IA32_VMX_PROCBASED_CTLS:
2408 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409 nested_vmx_procbased_ctls_high);
2410 break;
2411 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412 case MSR_IA32_VMX_EXIT_CTLS:
2413 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414 nested_vmx_exit_ctls_high);
2415 break;
2416 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417 case MSR_IA32_VMX_ENTRY_CTLS:
2418 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419 nested_vmx_entry_ctls_high);
2420 break;
2421 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2422 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423 nested_vmx_misc_high);
b87a51ae
NHE		 2424 break;
2425 /*
2426 * These MSRs specify bits which the guest must keep fixed (on or off)
2427 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428 * We picked the standard core2 setting.
2429 */
2430#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2432 case MSR_IA32_VMX_CR0_FIXED0:
2433 *pdata = VMXON_CR0_ALWAYSON;
2434 break;
2435 case MSR_IA32_VMX_CR0_FIXED1:
2436 *pdata = -1ULL;
2437 break;
2438 case MSR_IA32_VMX_CR4_FIXED0:
2439 *pdata = VMXON_CR4_ALWAYSON;
2440 break;
2441 case MSR_IA32_VMX_CR4_FIXED1:
2442 *pdata = -1ULL;
2443 break;
2444 case MSR_IA32_VMX_VMCS_ENUM:
2445 *pdata = 0x1f;
2446 break;
2447 case MSR_IA32_VMX_PROCBASED_CTLS2:
2448 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449 nested_vmx_secondary_ctls_high);
2450 break;
2451 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2452 /* Currently, no nested vpid support */
2453 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2454 break;
2455 default:
2456 return 0;
2457 }
2458
2459 return 1;
2460}
2461
42124925
JK		 2462static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2463
b3897a49 2464static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2465{
b3897a49
NHE		 2466 u32 msr_index = msr_info->index;
2467 u64 data = msr_info->data;
2468 bool host_initialized = msr_info->host_initiated;
2469
b87a51ae
NHE		 2470 if (!nested_vmx_allowed(vcpu))
2471 return 0;
2472
b3897a49
NHE		 2473 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2474 if (!host_initialized &&
2475 to_vmx(vcpu)->nested.msr_ia32_feature_control
2476 & FEATURE_CONTROL_LOCKED)
2477 return 0;
2478 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
42124925
JK		 2479 if (host_initialized && data == 0)
2480 vmx_leave_nested(vcpu);
b87a51ae 2481 return 1;
b3897a49
NHE		 2482 }
2483
b87a51ae
NHE		 2484 /*
2485 * No need to treat VMX capability MSRs specially: If we don't handle
2486 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2487 */
2488 return 0;
2489}
2490
6aa8b732
AK		 2491/*
2492 * Reads an msr value (of 'msr_index') into 'pdata'.
2493 * Returns 0 on success, non-0 otherwise.
2494 * Assumes vcpu_load() was already called.
2495 */
2496static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2497{
2498 u64 data;
26bb0981 2499 struct shared_msr_entry *msr;
6aa8b732
AK		 2500
2501 if (!pdata) {
2502 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2503 return -EINVAL;
2504 }
2505
2506 switch (msr_index) {
05b3e0c2 2507#ifdef CONFIG_X86_64
6aa8b732
AK		 2508 case MSR_FS_BASE:
2509 data = vmcs_readl(GUEST_FS_BASE);
2510 break;
2511 case MSR_GS_BASE:
2512 data = vmcs_readl(GUEST_GS_BASE);
2513 break;
44ea2b17
AK		 2514 case MSR_KERNEL_GS_BASE:
2515 vmx_load_host_state(to_vmx(vcpu));
2516 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2517 break;
26bb0981 2518#endif
6aa8b732 2519 case MSR_EFER:
3bab1f5d 2520 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2521 case MSR_IA32_TSC:
6aa8b732
AK		 2522 data = guest_read_tsc();
2523 break;
2524 case MSR_IA32_SYSENTER_CS:
2525 data = vmcs_read32(GUEST_SYSENTER_CS);
2526 break;
2527 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2528 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2529 break;
2530 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2531 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2532 break;
4e47c7a6
SY		 2533 case MSR_TSC_AUX:
2534 if (!to_vmx(vcpu)->rdtscp_enabled)
2535 return 1;
2536 /* Otherwise falls through */
6aa8b732 2537 default:
b87a51ae
NHE		 2538 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2539 return 0;
8b9cf98c 2540 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2541 if (msr) {
2542 data = msr->data;
2543 break;
6aa8b732 2544 }
3bab1f5d 2545 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2546 }
2547
2548 *pdata = data;
2549 return 0;
2550}
2551
2552/*
2553 * Writes msr value into into the appropriate "register".
2554 * Returns 0 on success, non-0 otherwise.
2555 * Assumes vcpu_load() was already called.
2556 */
8fe8ab46 2557static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2558{
a2fa3e9f 2559 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2560 struct shared_msr_entry *msr;
2cc51560 2561 int ret = 0;
8fe8ab46
WA		 2562 u32 msr_index = msr_info->index;
2563 u64 data = msr_info->data;
2cc51560 2564
6aa8b732 2565 switch (msr_index) {
3bab1f5d 2566 case MSR_EFER:
8fe8ab46 2567 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2568 break;
16175a79 2569#ifdef CONFIG_X86_64
6aa8b732 2570 case MSR_FS_BASE:
2fb92db1 2571 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2572 vmcs_writel(GUEST_FS_BASE, data);
2573 break;
2574 case MSR_GS_BASE:
2fb92db1 2575 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2576 vmcs_writel(GUEST_GS_BASE, data);
2577 break;
44ea2b17
AK		 2578 case MSR_KERNEL_GS_BASE:
2579 vmx_load_host_state(vmx);
2580 vmx->msr_guest_kernel_gs_base = data;
2581 break;
6aa8b732
AK		 2582#endif
2583 case MSR_IA32_SYSENTER_CS:
2584 vmcs_write32(GUEST_SYSENTER_CS, data);
2585 break;
2586 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2587 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2588 break;
2589 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2590 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2591 break;
af24a4e4 2592 case MSR_IA32_TSC:
8fe8ab46 2593 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2594 break;
468d472f
SY		 2595 case MSR_IA32_CR_PAT:
2596 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2597 vmcs_write64(GUEST_IA32_PAT, data);
2598 vcpu->arch.pat = data;
2599 break;
2600 }
8fe8ab46 2601 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2602 break;
ba904635
WA		 2603 case MSR_IA32_TSC_ADJUST:
2604 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2605 break;
2606 case MSR_TSC_AUX:
2607 if (!vmx->rdtscp_enabled)
2608 return 1;
2609 /* Check reserved bit, higher 32 bits should be zero */
2610 if ((data >> 32) != 0)
2611 return 1;
2612 /* Otherwise falls through */
6aa8b732 2613 default:
b3897a49 2614 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2615 break;
8b9cf98c 2616 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2617 if (msr) {
2618 msr->data = data;
2225fd56
AK		 2619 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2620 preempt_disable();
9ee73970
AK		 2621 kvm_set_shared_msr(msr->index, msr->data,
2622 msr->mask);
2225fd56
AK		 2623 preempt_enable();
2624 }
3bab1f5d 2625 break;
6aa8b732 2626 }
8fe8ab46 2627 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2628 }
2629
2cc51560 2630 return ret;
6aa8b732
AK		 2631}
2632
5fdbf976 2633static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2634{
5fdbf976
MT		 2635 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2636 switch (reg) {
2637 case VCPU_REGS_RSP:
2638 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2639 break;
2640 case VCPU_REGS_RIP:
2641 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2642 break;
6de4f3ad
AK		 2643 case VCPU_EXREG_PDPTR:
2644 if (enable_ept)
2645 ept_save_pdptrs(vcpu);
2646 break;
5fdbf976
MT		 2647 default:
2648 break;
2649 }
6aa8b732
AK		 2650}
2651
6aa8b732
AK		 2652static __init int cpu_has_kvm_support(void)
2653{
6210e37b 2654 return cpu_has_vmx();
6aa8b732
AK		 2655}
2656
2657static __init int vmx_disabled_by_bios(void)
2658{
2659 u64 msr;
2660
2661 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2662 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2663 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2664 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2665 && tboot_enabled())
2666 return 1;
23f3e991 2667 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2668 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2669 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2670 && !tboot_enabled()) {
2671 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2672 "activate TXT before enabling KVM\n");
cafd6659 2673 return 1;
f9335afe 2674 }
23f3e991
JC		 2675 /* launched w/o TXT and VMX disabled */
2676 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2677 && !tboot_enabled())
2678 return 1;
cafd6659
SW		 2679 }
2680
2681 return 0;
6aa8b732
AK		 2682}
2683
7725b894
DX		 2684static void kvm_cpu_vmxon(u64 addr)
2685{
2686 asm volatile (ASM_VMX_VMXON_RAX
2687 : : "a"(&addr), "m"(addr)
2688 : "memory", "cc");
2689}
2690
10474ae8 2691static int hardware_enable(void *garbage)
6aa8b732
AK		 2692{
2693 int cpu = raw_smp_processor_id();
2694 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2695 u64 old, test_bits;
6aa8b732 2696
10474ae8
AG		 2697 if (read_cr4() & X86_CR4_VMXE)
2698 return -EBUSY;
2699
d462b819 2700 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2701
2702 /*
2703 * Now we can enable the vmclear operation in kdump
2704 * since the loaded_vmcss_on_cpu list on this cpu
2705 * has been initialized.
2706 *
2707 * Though the cpu is not in VMX operation now, there
2708 * is no problem to enable the vmclear operation
2709 * for the loaded_vmcss_on_cpu list is empty!
2710 */
2711 crash_enable_local_vmclear(cpu);
2712
6aa8b732 2713 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2714
2715 test_bits = FEATURE_CONTROL_LOCKED;
2716 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2717 if (tboot_enabled())
2718 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2719
2720 if ((old & test_bits) != test_bits) {
6aa8b732 2721 /* enable and lock */
cafd6659
SW		 2722 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2723 }
66aee91a 2724 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2725
4610c9cc
DX		 2726 if (vmm_exclusive) {
2727 kvm_cpu_vmxon(phys_addr);
2728 ept_sync_global();
2729 }
10474ae8 2730
357d1226 2731 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2732
10474ae8 2733 return 0;
6aa8b732
AK		 2734}
2735
d462b819 2736static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2737{
2738 int cpu = raw_smp_processor_id();
d462b819 2739 struct loaded_vmcs *v, *n;
543e4243 2740
d462b819
NHE		 2741 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2742 loaded_vmcss_on_cpu_link)
2743 __loaded_vmcs_clear(v);
543e4243
AK		 2744}
2745
710ff4a8
EH		 2746
2747/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2748 * tricks.
2749 */
2750static void kvm_cpu_vmxoff(void)
6aa8b732 2751{
4ecac3fd 2752 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2753}
2754
710ff4a8
EH		 2755static void hardware_disable(void *garbage)
2756{
4610c9cc 2757 if (vmm_exclusive) {
d462b819 2758 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2759 kvm_cpu_vmxoff();
2760 }
7725b894 2761 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2762}
2763
1c3d14fe 2764static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2765 u32 msr, u32 *result)
1c3d14fe
YS		 2766{
2767 u32 vmx_msr_low, vmx_msr_high;
2768 u32 ctl = ctl_min | ctl_opt;
2769
2770 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2771
2772 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2773 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2774
2775 /* Ensure minimum (required) set of control bits are supported. */
2776 if (ctl_min & ~ctl)
002c7f7c 2777 return -EIO;
1c3d14fe
YS		 2778
2779 *result = ctl;
2780 return 0;
2781}
2782
110312c8
AK		 2783static __init bool allow_1_setting(u32 msr, u32 ctl)
2784{
2785 u32 vmx_msr_low, vmx_msr_high;
2786
2787 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2788 return vmx_msr_high & ctl;
2789}
2790
002c7f7c 2791static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2792{
2793 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2794 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2795 u32 _pin_based_exec_control = 0;
2796 u32 _cpu_based_exec_control = 0;
f78e0e2e 2797 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2798 u32 _vmexit_control = 0;
2799 u32 _vmentry_control = 0;
2800
10166744 2801 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2802#ifdef CONFIG_X86_64
2803 CPU_BASED_CR8_LOAD_EXITING |
2804 CPU_BASED_CR8_STORE_EXITING |
2805#endif
d56f546d
SY		 2806 CPU_BASED_CR3_LOAD_EXITING |
2807 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2808 CPU_BASED_USE_IO_BITMAPS |
2809 CPU_BASED_MOV_DR_EXITING |
a7052897 2810 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2811 CPU_BASED_MWAIT_EXITING |
2812 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2813 CPU_BASED_INVLPG_EXITING |
2814 CPU_BASED_RDPMC_EXITING;
443381a8 2815
f78e0e2e 2816 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2817 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2818 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2819 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2820 &_cpu_based_exec_control) < 0)
002c7f7c 2821 return -EIO;
6e5d865c
YS		 2822#ifdef CONFIG_X86_64
2823 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2824 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2825 ~CPU_BASED_CR8_STORE_EXITING;
2826#endif
f78e0e2e 2827 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2828 min2 = 0;
2829 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2830 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2831 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2832 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2833 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2834 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2835 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2836 SECONDARY_EXEC_RDTSCP |
83d4c286 2837 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2838 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2839 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2840 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2841 if (adjust_vmx_controls(min2, opt2,
2842 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2843 &_cpu_based_2nd_exec_control) < 0)
2844 return -EIO;
2845 }
2846#ifndef CONFIG_X86_64
2847 if (!(_cpu_based_2nd_exec_control &
2848 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2849 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2850#endif
83d4c286
YZ		 2851
2852 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2853 _cpu_based_2nd_exec_control &= ~(
8d14695f 2854 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2855 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2856 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2857
d56f546d 2858 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2859 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2860 enabled */
5fff7d27
GN		 2861 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2862 CPU_BASED_CR3_STORE_EXITING |
2863 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2864 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2865 vmx_capability.ept, vmx_capability.vpid);
2866 }
1c3d14fe
YS		 2867
2868 min = 0;
2869#ifdef CONFIG_X86_64
2870 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2871#endif
a547c6db
YZ		 2872 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2873 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2874 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2875 &_vmexit_control) < 0)
002c7f7c 2876 return -EIO;
1c3d14fe 2877
01e439be
YZ		 2878 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2879 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2880 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2881 &_pin_based_exec_control) < 0)
2882 return -EIO;
2883
2884 if (!(_cpu_based_2nd_exec_control &
2885 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2886 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2887 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2888
468d472f
SY		 2889 min = 0;
2890 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2891 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2892 &_vmentry_control) < 0)
002c7f7c 2893 return -EIO;
6aa8b732 2894
c68876fd 2895 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2896
2897 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2898 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2899 return -EIO;
1c3d14fe
YS		 2900
2901#ifdef CONFIG_X86_64
2902 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2903 if (vmx_msr_high & (1u<<16))
002c7f7c 2904 return -EIO;
1c3d14fe
YS		 2905#endif
2906
2907 /* Require Write-Back (WB) memory type for VMCS accesses. */
2908 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2909 return -EIO;
1c3d14fe 2910
002c7f7c
YS		 2911 vmcs_conf->size = vmx_msr_high & 0x1fff;
2912 vmcs_conf->order = get_order(vmcs_config.size);
2913 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2914
002c7f7c
YS		 2915 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2916 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2917 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2918 vmcs_conf->vmexit_ctrl = _vmexit_control;
2919 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2920
110312c8
AK		 2921 cpu_has_load_ia32_efer =
2922 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2923 VM_ENTRY_LOAD_IA32_EFER)
2924 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2925 VM_EXIT_LOAD_IA32_EFER);
2926
8bf00a52
GN		 2927 cpu_has_load_perf_global_ctrl =
2928 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2929 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2930 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2931 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2932
2933 /*
2934 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2935 * but due to arrata below it can't be used. Workaround is to use
2936 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2937 *
2938 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2939 *
2940 * AAK155 (model 26)
2941 * AAP115 (model 30)
2942 * AAT100 (model 37)
2943 * BC86,AAY89,BD102 (model 44)
2944 * BA97 (model 46)
2945 *
2946 */
2947 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2948 switch (boot_cpu_data.x86_model) {
2949 case 26:
2950 case 30:
2951 case 37:
2952 case 44:
2953 case 46:
2954 cpu_has_load_perf_global_ctrl = false;
2955 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2956 "does not work properly. Using workaround\n");
2957 break;
2958 default:
2959 break;
2960 }
2961 }
2962
1c3d14fe 2963 return 0;
c68876fd 2964}
6aa8b732
AK		 2965
2966static struct vmcs *alloc_vmcs_cpu(int cpu)
2967{
2968 int node = cpu_to_node(cpu);
2969 struct page *pages;
2970 struct vmcs *vmcs;
2971
6484eb3e 2972 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2973 if (!pages)
2974 return NULL;
2975 vmcs = page_address(pages);
1c3d14fe
YS		 2976 memset(vmcs, 0, vmcs_config.size);
2977 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2978 return vmcs;
2979}
2980
2981static struct vmcs *alloc_vmcs(void)
2982{
d3b2c338 2983 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2984}
2985
2986static void free_vmcs(struct vmcs *vmcs)
2987{
1c3d14fe 2988 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2989}
2990
d462b819
NHE		 2991/*
2992 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2993 */
2994static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2995{
2996 if (!loaded_vmcs->vmcs)
2997 return;
2998 loaded_vmcs_clear(loaded_vmcs);
2999 free_vmcs(loaded_vmcs->vmcs);
3000 loaded_vmcs->vmcs = NULL;
3001}
3002
39959588 3003static void free_kvm_area(void)
6aa8b732
AK		 3004{
3005 int cpu;
3006
3230bb47 3007 for_each_possible_cpu(cpu) {
6aa8b732 3008 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3009 per_cpu(vmxarea, cpu) = NULL;
3010 }
6aa8b732
AK		 3011}
3012
6aa8b732
AK		 3013static __init int alloc_kvm_area(void)
3014{
3015 int cpu;
3016
3230bb47 3017 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3018 struct vmcs *vmcs;
3019
3020 vmcs = alloc_vmcs_cpu(cpu);
3021 if (!vmcs) {
3022 free_kvm_area();
3023 return -ENOMEM;
3024 }
3025
3026 per_cpu(vmxarea, cpu) = vmcs;
3027 }
3028 return 0;
3029}
3030
3031static __init int hardware_setup(void)
3032{
002c7f7c
YS		 3033 if (setup_vmcs_config(&vmcs_config) < 0)
3034 return -EIO;
50a37eb4
JR		 3035
3036 if (boot_cpu_has(X86_FEATURE_NX))
3037 kvm_enable_efer_bits(EFER_NX);
3038
93ba03c2
SY		 3039 if (!cpu_has_vmx_vpid())
3040 enable_vpid = 0;
abc4fc58
AG		 3041 if (!cpu_has_vmx_shadow_vmcs())
3042 enable_shadow_vmcs = 0;
93ba03c2 3043
4bc9b982
SY		 3044 if (!cpu_has_vmx_ept() ||
3045 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3046 enable_ept = 0;
3a624e29 3047 enable_unrestricted_guest = 0;
83c3a331 3048 enable_ept_ad_bits = 0;
3a624e29
NK		 3049 }
3050
83c3a331
XH		 3051 if (!cpu_has_vmx_ept_ad_bits())
3052 enable_ept_ad_bits = 0;
3053
3a624e29
NK		 3054 if (!cpu_has_vmx_unrestricted_guest())
3055 enable_unrestricted_guest = 0;
93ba03c2
SY		 3056
3057 if (!cpu_has_vmx_flexpriority())
3058 flexpriority_enabled = 0;
3059
95ba8273
GN		 3060 if (!cpu_has_vmx_tpr_shadow())
3061 kvm_x86_ops->update_cr8_intercept = NULL;
3062
54dee993
MT		 3063 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3064 kvm_disable_largepages();
3065
4b8d54f9
ZE		 3066 if (!cpu_has_vmx_ple())
3067 ple_gap = 0;
3068
01e439be
YZ		 3069 if (!cpu_has_vmx_apicv())
3070 enable_apicv = 0;
c7c9c56c 3071
01e439be 3072 if (enable_apicv)
c7c9c56c 3073 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3074 else {
c7c9c56c 3075 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3076 kvm_x86_ops->deliver_posted_interrupt = NULL;
3077 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3078 }
83d4c286 3079
b87a51ae
NHE		 3080 if (nested)
3081 nested_vmx_setup_ctls_msrs();
3082
6aa8b732
AK		 3083 return alloc_kvm_area();
3084}
3085
3086static __exit void hardware_unsetup(void)
3087{
3088 free_kvm_area();
3089}
3090
14168786
GN		 3091static bool emulation_required(struct kvm_vcpu *vcpu)
3092{
3093 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3094}
3095
91b0aa2c 3096static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3097 struct kvm_segment *save)
6aa8b732 3098{
d99e4152
GN		 3099 if (!emulate_invalid_guest_state) {
3100 /*
3101 * CS and SS RPL should be equal during guest entry according
3102 * to VMX spec, but in reality it is not always so. Since vcpu
3103 * is in the middle of the transition from real mode to
3104 * protected mode it is safe to assume that RPL 0 is a good
3105 * default value.
3106 */
3107 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3108 save->selector &= ~SELECTOR_RPL_MASK;
3109 save->dpl = save->selector & SELECTOR_RPL_MASK;
3110 save->s = 1;
6aa8b732 3111 }
d99e4152 3112 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3113}
3114
3115static void enter_pmode(struct kvm_vcpu *vcpu)
3116{
3117 unsigned long flags;
a89a8fb9 3118 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3119
d99e4152
GN		 3120 /*
3121 * Update real mode segment cache. It may be not up-to-date if sement
3122 * register was written while vcpu was in a guest mode.
3123 */
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3129 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3130
7ffd92c5 3131 vmx->rmode.vm86_active = 0;
6aa8b732 3132
2fb92db1
AK		 3133 vmx_segment_cache_clear(vmx);
3134
f5f7b2fe 3135 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3136
3137 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3138 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3139 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3140 vmcs_writel(GUEST_RFLAGS, flags);
3141
66aee91a
RR		 3142 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3143 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3144
3145 update_exception_bitmap(vcpu);
3146
91b0aa2c
GN		 3147 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3148 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3149 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3150 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3151 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3152 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3153
3154 /* CPL is always 0 when CPU enters protected mode */
3155 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3156 vmx->cpl = 0;
6aa8b732
AK		 3157}
3158
f5f7b2fe 3159static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3160{
772e0318 3161 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3162 struct kvm_segment var = *save;
3163
3164 var.dpl = 0x3;
3165 if (seg == VCPU_SREG_CS)
3166 var.type = 0x3;
3167
3168 if (!emulate_invalid_guest_state) {
3169 var.selector = var.base >> 4;
3170 var.base = var.base & 0xffff0;
3171 var.limit = 0xffff;
3172 var.g = 0;
3173 var.db = 0;
3174 var.present = 1;
3175 var.s = 1;
3176 var.l = 0;
3177 var.unusable = 0;
3178 var.type = 0x3;
3179 var.avl = 0;
3180 if (save->base & 0xf)
3181 printk_once(KERN_WARNING "kvm: segment base is not "
3182 "paragraph aligned when entering "
3183 "protected mode (seg=%d)", seg);
3184 }
6aa8b732 3185
d99e4152
GN		 3186 vmcs_write16(sf->selector, var.selector);
3187 vmcs_write32(sf->base, var.base);
3188 vmcs_write32(sf->limit, var.limit);
3189 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3190}
3191
3192static void enter_rmode(struct kvm_vcpu *vcpu)
3193{
3194 unsigned long flags;
a89a8fb9 3195 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3196
f5f7b2fe
AK		 3197 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3198 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3200 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3203 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3204
7ffd92c5 3205 vmx->rmode.vm86_active = 1;
6aa8b732 3206
776e58ea
GN		 3207 /*
3208 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3209 * vcpu. Warn the user that an update is overdue.
776e58ea 3210 */
4918c6ca 3211 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3212 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3213 "called before entering vcpu\n");
776e58ea 3214
2fb92db1
AK		 3215 vmx_segment_cache_clear(vmx);
3216
4918c6ca 3217 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3218 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3219 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3220
3221 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3222 vmx->rmode.save_rflags = flags;
6aa8b732 3223
053de044 3224 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3225
3226 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3227 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3228 update_exception_bitmap(vcpu);
3229
d99e4152
GN		 3230 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3231 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3232 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3233 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3234 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3235 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3236
8668a3c4 3237 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3238}
3239
401d10de
AS		 3240static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3241{
3242 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3243 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3244
3245 if (!msr)
3246 return;
401d10de 3247
44ea2b17
AK		 3248 /*
3249 * Force kernel_gs_base reloading before EFER changes, as control
3250 * of this msr depends on is_long_mode().
3251 */
3252 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3253 vcpu->arch.efer = efer;
401d10de 3254 if (efer & EFER_LMA) {
2961e876 3255 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3256 msr->data = efer;
3257 } else {
2961e876 3258 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3259
3260 msr->data = efer & ~EFER_LME;
3261 }
3262 setup_msrs(vmx);
3263}
3264
05b3e0c2 3265#ifdef CONFIG_X86_64
6aa8b732
AK		 3266
3267static void enter_lmode(struct kvm_vcpu *vcpu)
3268{
3269 u32 guest_tr_ar;
3270
2fb92db1
AK		 3271 vmx_segment_cache_clear(to_vmx(vcpu));
3272
6aa8b732
AK		 3273 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3274 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3275 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3276 __func__);
6aa8b732
AK		 3277 vmcs_write32(GUEST_TR_AR_BYTES,
3278 (guest_tr_ar & ~AR_TYPE_MASK)
3279 | AR_TYPE_BUSY_64_TSS);
3280 }
da38f438 3281 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3282}
3283
3284static void exit_lmode(struct kvm_vcpu *vcpu)
3285{
2961e876 3286 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3287 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3288}
3289
3290#endif
3291
2384d2b3
SY		 3292static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3293{
b9d762fa 3294 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3295 if (enable_ept) {
3296 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3297 return;
4e1096d2 3298 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3299 }
2384d2b3
SY		 3300}
3301
e8467fda
AK		 3302static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3303{
3304 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3305
3306 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3307 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3308}
3309
aff48baa
AK		 3310static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3311{
3312 if (enable_ept && is_paging(vcpu))
3313 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3314 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3315}
3316
25c4c276 3317static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3318{
fc78f519
AK		 3319 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3320
3321 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3322 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3323}
3324
1439442c
SY		 3325static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3326{
d0d538b9
GN		 3327 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3328
6de4f3ad
AK		 3329 if (!test_bit(VCPU_EXREG_PDPTR,
3330 (unsigned long *)&vcpu->arch.regs_dirty))
3331 return;
3332
1439442c 3333 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3334 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3335 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3336 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3337 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3338 }
3339}
3340
8f5d549f
AK		 3341static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3342{
d0d538b9
GN		 3343 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3344
8f5d549f 3345 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3346 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3347 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3348 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3349 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3350 }
6de4f3ad
AK		 3351
3352 __set_bit(VCPU_EXREG_PDPTR,
3353 (unsigned long *)&vcpu->arch.regs_avail);
3354 __set_bit(VCPU_EXREG_PDPTR,
3355 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3356}
3357
5e1746d6 3358static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3359
3360static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3361 unsigned long cr0,
3362 struct kvm_vcpu *vcpu)
3363{
5233dd51
MT		 3364 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3365 vmx_decache_cr3(vcpu);
1439442c
SY		 3366 if (!(cr0 & X86_CR0_PG)) {
3367 /* From paging/starting to nonpaging */
3368 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3369 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3370 (CPU_BASED_CR3_LOAD_EXITING |
3371 CPU_BASED_CR3_STORE_EXITING));
3372 vcpu->arch.cr0 = cr0;
fc78f519 3373 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3374 } else if (!is_paging(vcpu)) {
3375 /* From nonpaging to paging */
3376 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3377 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3378 ~(CPU_BASED_CR3_LOAD_EXITING |
3379 CPU_BASED_CR3_STORE_EXITING));
3380 vcpu->arch.cr0 = cr0;
fc78f519 3381 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3382 }
95eb84a7
SY		 3383
3384 if (!(cr0 & X86_CR0_WP))
3385 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3386}
3387
6aa8b732
AK		 3388static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3389{
7ffd92c5 3390 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3391 unsigned long hw_cr0;
3392
5037878e 3393 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3394 if (enable_unrestricted_guest)
5037878e 3395 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3396 else {
5037878e 3397 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3398
218e763f
GN		 3399 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3400 enter_pmode(vcpu);
6aa8b732 3401
218e763f
GN		 3402 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3403 enter_rmode(vcpu);
3404 }
6aa8b732 3405
05b3e0c2 3406#ifdef CONFIG_X86_64
f6801dff 3407 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3408 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3409 enter_lmode(vcpu);
707d92fa 3410 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3411 exit_lmode(vcpu);
3412 }
3413#endif
3414
089d034e 3415 if (enable_ept)
1439442c
SY		 3416 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3417
02daab21 3418 if (!vcpu->fpu_active)
81231c69 3419 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3420
6aa8b732 3421 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3422 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3423 vcpu->arch.cr0 = cr0;
14168786
GN		 3424
3425 /* depends on vcpu->arch.cr0 to be set to a new value */
3426 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3427}
3428
1439442c
SY		 3429static u64 construct_eptp(unsigned long root_hpa)
3430{
3431 u64 eptp;
3432
3433 /* TODO write the value reading from MSR */
3434 eptp = VMX_EPT_DEFAULT_MT |
3435 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3436 if (enable_ept_ad_bits)
3437 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3438 eptp |= (root_hpa & PAGE_MASK);
3439
3440 return eptp;
3441}
3442
6aa8b732
AK		 3443static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3444{
1439442c
SY		 3445 unsigned long guest_cr3;
3446 u64 eptp;
3447
3448 guest_cr3 = cr3;
089d034e 3449 if (enable_ept) {
1439442c
SY		 3450 eptp = construct_eptp(cr3);
3451 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3452 if (is_paging(vcpu) || is_guest_mode(vcpu))
3453 guest_cr3 = kvm_read_cr3(vcpu);
3454 else
3455 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3456 ept_load_pdptrs(vcpu);
1439442c
SY		 3457 }
3458
2384d2b3 3459 vmx_flush_tlb(vcpu);
1439442c 3460 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3461}
3462
5e1746d6 3463static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3464{
7ffd92c5 3465 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3466 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3467
5e1746d6
NHE		 3468 if (cr4 & X86_CR4_VMXE) {
3469 /*
3470 * To use VMXON (and later other VMX instructions), a guest
3471 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3472 * So basically the check on whether to allow nested VMX
3473 * is here.
3474 */
3475 if (!nested_vmx_allowed(vcpu))
3476 return 1;
1a0d74e6
JK		 3477 }
3478 if (to_vmx(vcpu)->nested.vmxon &&
3479 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3480 return 1;
3481
ad312c7c 3482 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3483 if (enable_ept) {
3484 if (!is_paging(vcpu)) {
3485 hw_cr4 &= ~X86_CR4_PAE;
3486 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3487 /*
3488 * SMEP is disabled if CPU is in non-paging mode in
3489 * hardware. However KVM always uses paging mode to
3490 * emulate guest non-paging mode with TDP.
3491 * To emulate this behavior, SMEP needs to be manually
3492 * disabled when guest switches to non-paging mode.
3493 */
3494 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3495 } else if (!(cr4 & X86_CR4_PAE)) {
3496 hw_cr4 &= ~X86_CR4_PAE;
3497 }
3498 }
1439442c
SY		 3499
3500 vmcs_writel(CR4_READ_SHADOW, cr4);
3501 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3502 return 0;
6aa8b732
AK		 3503}
3504
6aa8b732
AK		 3505static void vmx_get_segment(struct kvm_vcpu *vcpu,
3506 struct kvm_segment *var, int seg)
3507{
a9179499 3508 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3509 u32 ar;
3510
c6ad1153 3511 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3512 *var = vmx->rmode.segs[seg];
a9179499 3513 if (seg == VCPU_SREG_TR
2fb92db1 3514 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3515 return;
1390a28b
AK		 3516 var->base = vmx_read_guest_seg_base(vmx, seg);
3517 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3518 return;
a9179499 3519 }
2fb92db1
AK		 3520 var->base = vmx_read_guest_seg_base(vmx, seg);
3521 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3522 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3523 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3524 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3525 var->type = ar & 15;
3526 var->s = (ar >> 4) & 1;
3527 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3528 /*
3529 * Some userspaces do not preserve unusable property. Since usable
3530 * segment has to be present according to VMX spec we can use present
3531 * property to amend userspace bug by making unusable segment always
3532 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3533 * segment as unusable.
3534 */
3535 var->present = !var->unusable;
6aa8b732
AK		 3536 var->avl = (ar >> 12) & 1;
3537 var->l = (ar >> 13) & 1;
3538 var->db = (ar >> 14) & 1;
3539 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3540}
3541
a9179499
AK		 3542static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3543{
a9179499
AK		 3544 struct kvm_segment s;
3545
3546 if (to_vmx(vcpu)->rmode.vm86_active) {
3547 vmx_get_segment(vcpu, &s, seg);
3548 return s.base;
3549 }
2fb92db1 3550 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3551}
3552
b09408d0 3553static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3554{
b09408d0
MT		 3555 struct vcpu_vmx *vmx = to_vmx(vcpu);
3556
3eeb3288 3557 if (!is_protmode(vcpu))
2e4d2653
IE		 3558 return 0;
3559
f4c63e5d
AK		 3560 if (!is_long_mode(vcpu)
3561 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3562 return 3;
3563
69c73028
AK		 3564 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3565 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3566 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3567 }
d881e6f6
AK		 3568
3569 return vmx->cpl;
69c73028
AK		 3570}
3571
3572
653e3108 3573static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3574{
6aa8b732
AK		 3575 u32 ar;
3576
f0495f9b 3577 if (var->unusable || !var->present)
6aa8b732
AK		 3578 ar = 1 << 16;
3579 else {
3580 ar = var->type & 15;
3581 ar |= (var->s & 1) << 4;
3582 ar |= (var->dpl & 3) << 5;
3583 ar |= (var->present & 1) << 7;
3584 ar |= (var->avl & 1) << 12;
3585 ar |= (var->l & 1) << 13;
3586 ar |= (var->db & 1) << 14;
3587 ar |= (var->g & 1) << 15;
3588 }
653e3108
AK		 3589
3590 return ar;
3591}
3592
3593static void vmx_set_segment(struct kvm_vcpu *vcpu,
3594 struct kvm_segment *var, int seg)
3595{
7ffd92c5 3596 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3597 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3598
2fb92db1 3599 vmx_segment_cache_clear(vmx);
2f143240
GN		 3600 if (seg == VCPU_SREG_CS)
3601 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3602
1ecd50a9
GN		 3603 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3604 vmx->rmode.segs[seg] = *var;
3605 if (seg == VCPU_SREG_TR)
3606 vmcs_write16(sf->selector, var->selector);
3607 else if (var->s)
3608 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3609 goto out;
653e3108 3610 }
1ecd50a9 3611
653e3108
AK		 3612 vmcs_writel(sf->base, var->base);
3613 vmcs_write32(sf->limit, var->limit);
3614 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3615
3616 /*
3617 * Fix the "Accessed" bit in AR field of segment registers for older
3618 * qemu binaries.
3619 * IA32 arch specifies that at the time of processor reset the
3620 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3621 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3622 * state vmexit when "unrestricted guest" mode is turned on.
3623 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3624 * tree. Newer qemu binaries with that qemu fix would not need this
3625 * kvm hack.
3626 */
3627 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3628 var->type |= 0x1; /* Accessed */
3a624e29 3629
f924d66d 3630 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3631
3632out:
14168786 3633 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3634}
3635
6aa8b732
AK		 3636static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3637{
2fb92db1 3638 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3639
3640 *db = (ar >> 14) & 1;
3641 *l = (ar >> 13) & 1;
3642}
3643
89a27f4d 3644static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3645{
89a27f4d
GN		 3646 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3647 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3648}
3649
89a27f4d 3650static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3651{
89a27f4d
GN		 3652 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3653 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3654}
3655
89a27f4d 3656static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3657{
89a27f4d
GN		 3658 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3659 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3660}
3661
89a27f4d 3662static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3663{
89a27f4d
GN		 3664 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3665 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3666}
3667
648dfaa7
MG		 3668static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3669{
3670 struct kvm_segment var;
3671 u32 ar;
3672
3673 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3674 var.dpl = 0x3;
0647f4aa
GN		 3675 if (seg == VCPU_SREG_CS)
3676 var.type = 0x3;
648dfaa7
MG		 3677 ar = vmx_segment_access_rights(&var);
3678
3679 if (var.base != (var.selector << 4))
3680 return false;
89efbed0 3681 if (var.limit != 0xffff)
648dfaa7 3682 return false;
07f42f5f 3683 if (ar != 0xf3)
648dfaa7
MG		 3684 return false;
3685
3686 return true;
3687}
3688
3689static bool code_segment_valid(struct kvm_vcpu *vcpu)
3690{
3691 struct kvm_segment cs;
3692 unsigned int cs_rpl;
3693
3694 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3695 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3696
1872a3f4
AK		 3697 if (cs.unusable)
3698 return false;
648dfaa7
MG		 3699 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3700 return false;
3701 if (!cs.s)
3702 return false;
1872a3f4 3703 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3704 if (cs.dpl > cs_rpl)
3705 return false;
1872a3f4 3706 } else {
648dfaa7
MG		 3707 if (cs.dpl != cs_rpl)
3708 return false;
3709 }
3710 if (!cs.present)
3711 return false;
3712
3713 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3714 return true;
3715}
3716
3717static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3718{
3719 struct kvm_segment ss;
3720 unsigned int ss_rpl;
3721
3722 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3723 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3724
1872a3f4
AK		 3725 if (ss.unusable)
3726 return true;
3727 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3728 return false;
3729 if (!ss.s)
3730 return false;
3731 if (ss.dpl != ss_rpl) /* DPL != RPL */
3732 return false;
3733 if (!ss.present)
3734 return false;
3735
3736 return true;
3737}
3738
3739static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3740{
3741 struct kvm_segment var;
3742 unsigned int rpl;
3743
3744 vmx_get_segment(vcpu, &var, seg);
3745 rpl = var.selector & SELECTOR_RPL_MASK;
3746
1872a3f4
AK		 3747 if (var.unusable)
3748 return true;
648dfaa7
MG		 3749 if (!var.s)
3750 return false;
3751 if (!var.present)
3752 return false;
3753 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3754 if (var.dpl < rpl) /* DPL < RPL */
3755 return false;
3756 }
3757
3758 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3759 * rights flags
3760 */
3761 return true;
3762}
3763
3764static bool tr_valid(struct kvm_vcpu *vcpu)
3765{
3766 struct kvm_segment tr;
3767
3768 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3769
1872a3f4
AK		 3770 if (tr.unusable)
3771 return false;
648dfaa7
MG		 3772 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3773 return false;
1872a3f4 3774 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3775 return false;
3776 if (!tr.present)
3777 return false;
3778
3779 return true;
3780}
3781
3782static bool ldtr_valid(struct kvm_vcpu *vcpu)
3783{
3784 struct kvm_segment ldtr;
3785
3786 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3787
1872a3f4
AK		 3788 if (ldtr.unusable)
3789 return true;
648dfaa7
MG		 3790 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3791 return false;
3792 if (ldtr.type != 2)
3793 return false;
3794 if (!ldtr.present)
3795 return false;
3796
3797 return true;
3798}
3799
3800static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3801{
3802 struct kvm_segment cs, ss;
3803
3804 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3805 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3806
3807 return ((cs.selector & SELECTOR_RPL_MASK) ==
3808 (ss.selector & SELECTOR_RPL_MASK));
3809}
3810
3811/*
3812 * Check if guest state is valid. Returns true if valid, false if
3813 * not.
3814 * We assume that registers are always usable
3815 */
3816static bool guest_state_valid(struct kvm_vcpu *vcpu)
3817{
c5e97c80
GN		 3818 if (enable_unrestricted_guest)
3819 return true;
3820
648dfaa7 3821 /* real mode guest state checks */
f13882d8 3822 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3823 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3824 return false;
3825 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3826 return false;
3827 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3828 return false;
3829 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3830 return false;
3831 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3832 return false;
3833 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3834 return false;
3835 } else {
3836 /* protected mode guest state checks */
3837 if (!cs_ss_rpl_check(vcpu))
3838 return false;
3839 if (!code_segment_valid(vcpu))
3840 return false;
3841 if (!stack_segment_valid(vcpu))
3842 return false;
3843 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3844 return false;
3845 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3846 return false;
3847 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3848 return false;
3849 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3850 return false;
3851 if (!tr_valid(vcpu))
3852 return false;
3853 if (!ldtr_valid(vcpu))
3854 return false;
3855 }
3856 /* TODO:
3857 * - Add checks on RIP
3858 * - Add checks on RFLAGS
3859 */
3860
3861 return true;
3862}
3863
d77c26fc 3864static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3865{
40dcaa9f 3866 gfn_t fn;
195aefde 3867 u16 data = 0;
40dcaa9f 3868 int r, idx, ret = 0;
6aa8b732 3869
40dcaa9f 3870 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3871 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3872 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3873 if (r < 0)
10589a46 3874 goto out;
195aefde 3875 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3876 r = kvm_write_guest_page(kvm, fn++, &data,
3877 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3878 if (r < 0)
10589a46 3879 goto out;
195aefde
IE		 3880 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3881 if (r < 0)
10589a46 3882 goto out;
195aefde
IE		 3883 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3884 if (r < 0)
10589a46 3885 goto out;
195aefde 3886 data = ~0;
10589a46
MT		 3887 r = kvm_write_guest_page(kvm, fn, &data,
3888 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3889 sizeof(u8));
195aefde 3890 if (r < 0)
10589a46
MT		 3891 goto out;
3892
3893 ret = 1;
3894out:
40dcaa9f 3895 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3896 return ret;
6aa8b732
AK		 3897}
3898
b7ebfb05
SY		 3899static int init_rmode_identity_map(struct kvm *kvm)
3900{
40dcaa9f 3901 int i, idx, r, ret;
b7ebfb05
SY		 3902 pfn_t identity_map_pfn;
3903 u32 tmp;
3904
089d034e 3905 if (!enable_ept)
b7ebfb05
SY		 3906 return 1;
3907 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3908 printk(KERN_ERR "EPT: identity-mapping pagetable "
3909 "haven't been allocated!\n");
3910 return 0;
3911 }
3912 if (likely(kvm->arch.ept_identity_pagetable_done))
3913 return 1;
3914 ret = 0;
b927a3ce 3915 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3916 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3917 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3918 if (r < 0)
3919 goto out;
3920 /* Set up identity-mapping pagetable for EPT in real mode */
3921 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3922 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3923 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3924 r = kvm_write_guest_page(kvm, identity_map_pfn,
3925 &tmp, i * sizeof(tmp), sizeof(tmp));
3926 if (r < 0)
3927 goto out;
3928 }
3929 kvm->arch.ept_identity_pagetable_done = true;
3930 ret = 1;
3931out:
40dcaa9f 3932 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3933 return ret;
3934}
3935
6aa8b732
AK		 3936static void seg_setup(int seg)
3937{
772e0318 3938 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3939 unsigned int ar;
6aa8b732
AK		 3940
3941 vmcs_write16(sf->selector, 0);
3942 vmcs_writel(sf->base, 0);
3943 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3944 ar = 0x93;
3945 if (seg == VCPU_SREG_CS)
3946 ar |= 0x08; /* code segment */
3a624e29
NK		 3947
3948 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3949}
3950
f78e0e2e
SY		 3951static int alloc_apic_access_page(struct kvm *kvm)
3952{
4484141a 3953 struct page *page;
f78e0e2e
SY		 3954 struct kvm_userspace_memory_region kvm_userspace_mem;
3955 int r = 0;
3956
79fac95e 3957 mutex_lock(&kvm->slots_lock);
bfc6d222 3958 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3959 goto out;
3960 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3961 kvm_userspace_mem.flags = 0;
3962 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3963 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3964 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3965 if (r)
3966 goto out;
72dc67a6 3967
4484141a
XG		 3968 page = gfn_to_page(kvm, 0xfee00);
3969 if (is_error_page(page)) {
3970 r = -EFAULT;
3971 goto out;
3972 }
3973
3974 kvm->arch.apic_access_page = page;
f78e0e2e 3975out:
79fac95e 3976 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3977 return r;
3978}
3979
b7ebfb05
SY		 3980static int alloc_identity_pagetable(struct kvm *kvm)
3981{
4484141a 3982 struct page *page;
b7ebfb05
SY		 3983 struct kvm_userspace_memory_region kvm_userspace_mem;
3984 int r = 0;
3985
79fac95e 3986 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3987 if (kvm->arch.ept_identity_pagetable)
3988 goto out;
3989 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3990 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3991 kvm_userspace_mem.guest_phys_addr =
3992 kvm->arch.ept_identity_map_addr;
b7ebfb05 3993 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3994 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3995 if (r)
3996 goto out;
3997
4484141a
XG		 3998 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3999 if (is_error_page(page)) {
4000 r = -EFAULT;
4001 goto out;
4002 }
4003
4004 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4005out:
79fac95e 4006 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4007 return r;
4008}
4009
2384d2b3
SY		 4010static void allocate_vpid(struct vcpu_vmx *vmx)
4011{
4012 int vpid;
4013
4014 vmx->vpid = 0;
919818ab 4015 if (!enable_vpid)
2384d2b3
SY		 4016 return;
4017 spin_lock(&vmx_vpid_lock);
4018 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4019 if (vpid < VMX_NR_VPIDS) {
4020 vmx->vpid = vpid;
4021 __set_bit(vpid, vmx_vpid_bitmap);
4022 }
4023 spin_unlock(&vmx_vpid_lock);
4024}
4025
cdbecfc3
LJ		 4026static void free_vpid(struct vcpu_vmx *vmx)
4027{
4028 if (!enable_vpid)
4029 return;
4030 spin_lock(&vmx_vpid_lock);
4031 if (vmx->vpid != 0)
4032 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4033 spin_unlock(&vmx_vpid_lock);
4034}
4035
8d14695f
YZ		 4036#define MSR_TYPE_R 1
4037#define MSR_TYPE_W 2
4038static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4039 u32 msr, int type)
25c5f225 4040{
3e7c73e9 4041 int f = sizeof(unsigned long);
25c5f225
SY		 4042
4043 if (!cpu_has_vmx_msr_bitmap())
4044 return;
4045
4046 /*
4047 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4048 * have the write-low and read-high bitmap offsets the wrong way round.
4049 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4050 */
25c5f225 4051 if (msr <= 0x1fff) {
8d14695f
YZ		 4052 if (type & MSR_TYPE_R)
4053 /* read-low */
4054 __clear_bit(msr, msr_bitmap + 0x000 / f);
4055
4056 if (type & MSR_TYPE_W)
4057 /* write-low */
4058 __clear_bit(msr, msr_bitmap + 0x800 / f);
4059
25c5f225
SY		 4060 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4061 msr &= 0x1fff;
8d14695f
YZ		 4062 if (type & MSR_TYPE_R)
4063 /* read-high */
4064 __clear_bit(msr, msr_bitmap + 0x400 / f);
4065
4066 if (type & MSR_TYPE_W)
4067 /* write-high */
4068 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4069
4070 }
4071}
4072
4073static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4074 u32 msr, int type)
4075{
4076 int f = sizeof(unsigned long);
4077
4078 if (!cpu_has_vmx_msr_bitmap())
4079 return;
4080
4081 /*
4082 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4083 * have the write-low and read-high bitmap offsets the wrong way round.
4084 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4085 */
4086 if (msr <= 0x1fff) {
4087 if (type & MSR_TYPE_R)
4088 /* read-low */
4089 __set_bit(msr, msr_bitmap + 0x000 / f);
4090
4091 if (type & MSR_TYPE_W)
4092 /* write-low */
4093 __set_bit(msr, msr_bitmap + 0x800 / f);
4094
4095 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4096 msr &= 0x1fff;
4097 if (type & MSR_TYPE_R)
4098 /* read-high */
4099 __set_bit(msr, msr_bitmap + 0x400 / f);
4100
4101 if (type & MSR_TYPE_W)
4102 /* write-high */
4103 __set_bit(msr, msr_bitmap + 0xc00 / f);
4104
25c5f225 4105 }
25c5f225
SY		 4106}
4107
5897297b
AK		 4108static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4109{
4110 if (!longmode_only)
8d14695f
YZ		 4111 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4112 msr, MSR_TYPE_R | MSR_TYPE_W);
4113 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4114 msr, MSR_TYPE_R | MSR_TYPE_W);
4115}
4116
4117static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4118{
4119 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4120 msr, MSR_TYPE_R);
4121 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4122 msr, MSR_TYPE_R);
4123}
4124
4125static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4126{
4127 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4128 msr, MSR_TYPE_R);
4129 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4130 msr, MSR_TYPE_R);
4131}
4132
4133static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4134{
4135 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4136 msr, MSR_TYPE_W);
4137 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4138 msr, MSR_TYPE_W);
5897297b
AK		 4139}
4140
01e439be
YZ		 4141static int vmx_vm_has_apicv(struct kvm *kvm)
4142{
4143 return enable_apicv && irqchip_in_kernel(kvm);
4144}
4145
a20ed54d
YZ		 4146/*
4147 * Send interrupt to vcpu via posted interrupt way.
4148 * 1. If target vcpu is running(non-root mode), send posted interrupt
4149 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4150 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4151 * interrupt from PIR in next vmentry.
4152 */
4153static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4154{
4155 struct vcpu_vmx *vmx = to_vmx(vcpu);
4156 int r;
4157
4158 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4159 return;
4160
4161 r = pi_test_and_set_on(&vmx->pi_desc);
4162 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4163#ifdef CONFIG_SMP
a20ed54d
YZ		 4164 if (!r && (vcpu->mode == IN_GUEST_MODE))
4165 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4166 POSTED_INTR_VECTOR);
4167 else
6ffbbbba 4168#endif
a20ed54d
YZ		 4169 kvm_vcpu_kick(vcpu);
4170}
4171
4172static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4173{
4174 struct vcpu_vmx *vmx = to_vmx(vcpu);
4175
4176 if (!pi_test_and_clear_on(&vmx->pi_desc))
4177 return;
4178
4179 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4180}
4181
4182static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4183{
4184 return;
4185}
4186
a3a8ff8e
NHE		 4187/*
4188 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4189 * will not change in the lifetime of the guest.
4190 * Note that host-state that does change is set elsewhere. E.g., host-state
4191 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4192 */
a547c6db 4193static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4194{
4195 u32 low32, high32;
4196 unsigned long tmpl;
4197 struct desc_ptr dt;
4198
b1a74bf8 4199 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4200 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4201 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4202
4203 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4204#ifdef CONFIG_X86_64
4205 /*
4206 * Load null selectors, so we can avoid reloading them in
4207 * __vmx_load_host_state(), in case userspace uses the null selectors
4208 * too (the expected case).
4209 */
4210 vmcs_write16(HOST_DS_SELECTOR, 0);
4211 vmcs_write16(HOST_ES_SELECTOR, 0);
4212#else
a3a8ff8e
NHE		 4213 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4214 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4215#endif
a3a8ff8e
NHE		 4216 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4217 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4218
4219 native_store_idt(&dt);
4220 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4221 vmx->host_idt_base = dt.address;
a3a8ff8e 4222
83287ea4 4223 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4224
4225 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4226 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4227 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4228 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4229
4230 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4231 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4232 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4233 }
4234}
4235
bf8179a0
NHE		 4236static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4237{
4238 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4239 if (enable_ept)
4240 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4241 if (is_guest_mode(&vmx->vcpu))
4242 vmx->vcpu.arch.cr4_guest_owned_bits &=
4243 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4244 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4245}
4246
01e439be
YZ		 4247static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4248{
4249 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4250
4251 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4252 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4253 return pin_based_exec_ctrl;
4254}
4255
bf8179a0
NHE		 4256static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4257{
4258 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4259 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4260 exec_control &= ~CPU_BASED_TPR_SHADOW;
4261#ifdef CONFIG_X86_64
4262 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4263 CPU_BASED_CR8_LOAD_EXITING;
4264#endif
4265 }
4266 if (!enable_ept)
4267 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4268 CPU_BASED_CR3_LOAD_EXITING |
4269 CPU_BASED_INVLPG_EXITING;
4270 return exec_control;
4271}
4272
4273static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4274{
4275 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4276 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4277 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4278 if (vmx->vpid == 0)
4279 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4280 if (!enable_ept) {
4281 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4282 enable_unrestricted_guest = 0;
ad756a16
MJ		 4283 /* Enable INVPCID for non-ept guests may cause performance regression. */
4284 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4285 }
4286 if (!enable_unrestricted_guest)
4287 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4288 if (!ple_gap)
4289 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4290 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4291 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4292 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4293 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4294 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4295 (handle_vmptrld).
4296 We can NOT enable shadow_vmcs here because we don't have yet
4297 a current VMCS12
4298 */
4299 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4300 return exec_control;
4301}
4302
ce88decf
XG		 4303static void ept_set_mmio_spte_mask(void)
4304{
4305 /*
4306 * EPT Misconfigurations can be generated if the value of bits 2:0
4307 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4308 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4309 * spte.
4310 */
885032b9 4311 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4312}
4313
6aa8b732
AK		 4314/*
4315 * Sets up the vmcs for emulated real mode.
4316 */
8b9cf98c 4317static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4318{
2e4ce7f5 4319#ifdef CONFIG_X86_64
6aa8b732 4320 unsigned long a;
2e4ce7f5 4321#endif
6aa8b732 4322 int i;
6aa8b732 4323
6aa8b732 4324 /* I/O */
3e7c73e9
AK		 4325 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4326 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4327
4607c2d7
AG		 4328 if (enable_shadow_vmcs) {
4329 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4330 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4331 }
25c5f225 4332 if (cpu_has_vmx_msr_bitmap())
5897297b 4333 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4334
6aa8b732
AK		 4335 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4336
6aa8b732 4337 /* Control */
01e439be 4338 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4339
bf8179a0 4340 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4341
83ff3b9d 4342 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4343 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4344 vmx_secondary_exec_control(vmx));
83ff3b9d 4345 }
f78e0e2e 4346
01e439be 4347 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4348 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4349 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4350 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4351 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4352
4353 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4354
4355 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4356 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4357 }
4358
4b8d54f9
ZE		 4359 if (ple_gap) {
4360 vmcs_write32(PLE_GAP, ple_gap);
4361 vmcs_write32(PLE_WINDOW, ple_window);
4362 }
4363
c3707958
XG		 4364 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4365 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4366 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4367
9581d442
AK		 4368 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4369 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4370 vmx_set_constant_host_state(vmx);
05b3e0c2 4371#ifdef CONFIG_X86_64
6aa8b732
AK		 4372 rdmsrl(MSR_FS_BASE, a);
4373 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4374 rdmsrl(MSR_GS_BASE, a);
4375 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4376#else
4377 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4378 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4379#endif
4380
2cc51560
ED		 4381 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4382 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4383 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4384 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4385 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4386
468d472f 4387 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4388 u32 msr_low, msr_high;
4389 u64 host_pat;
468d472f
SY		 4390 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4391 host_pat = msr_low | ((u64) msr_high << 32);
4392 /* Write the default value follow host pat */
4393 vmcs_write64(GUEST_IA32_PAT, host_pat);
4394 /* Keep arch.pat sync with GUEST_IA32_PAT */
4395 vmx->vcpu.arch.pat = host_pat;
4396 }
4397
6aa8b732
AK		 4398 for (i = 0; i < NR_VMX_MSR; ++i) {
4399 u32 index = vmx_msr_index[i];
4400 u32 data_low, data_high;
a2fa3e9f 4401 int j = vmx->nmsrs;
6aa8b732
AK		 4402
4403 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4404 continue;
432bd6cb
AK		 4405 if (wrmsr_safe(index, data_low, data_high) < 0)
4406 continue;
26bb0981
AK		 4407 vmx->guest_msrs[j].index = i;
4408 vmx->guest_msrs[j].data = 0;
d5696725 4409 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4410 ++vmx->nmsrs;
6aa8b732 4411 }
6aa8b732 4412
2961e876
GN		 4413
4414 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4415
4416 /* 22.2.1, 20.8.1 */
2961e876 4417 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4418
e00c8cf2 4419 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4420 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4421
4422 return 0;
4423}
4424
57f252f2 4425static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4426{
4427 struct vcpu_vmx *vmx = to_vmx(vcpu);
4428 u64 msr;
e00c8cf2 4429
7ffd92c5 4430 vmx->rmode.vm86_active = 0;
e00c8cf2 4431
3b86cd99
JK		 4432 vmx->soft_vnmi_blocked = 0;
4433
ad312c7c 4434 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4435 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4436 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4437 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4438 msr |= MSR_IA32_APICBASE_BSP;
4439 kvm_set_apic_base(&vmx->vcpu, msr);
4440
2fb92db1
AK		 4441 vmx_segment_cache_clear(vmx);
4442
5706be0d 4443 seg_setup(VCPU_SREG_CS);
66450a21 4444 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4445 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4446
4447 seg_setup(VCPU_SREG_DS);
4448 seg_setup(VCPU_SREG_ES);
4449 seg_setup(VCPU_SREG_FS);
4450 seg_setup(VCPU_SREG_GS);
4451 seg_setup(VCPU_SREG_SS);
4452
4453 vmcs_write16(GUEST_TR_SELECTOR, 0);
4454 vmcs_writel(GUEST_TR_BASE, 0);
4455 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4456 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4457
4458 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4459 vmcs_writel(GUEST_LDTR_BASE, 0);
4460 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4461 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4462
4463 vmcs_write32(GUEST_SYSENTER_CS, 0);
4464 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4465 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4466
4467 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4468 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4469
e00c8cf2
AK		 4470 vmcs_writel(GUEST_GDTR_BASE, 0);
4471 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4472
4473 vmcs_writel(GUEST_IDTR_BASE, 0);
4474 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4475
443381a8 4476 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4477 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4478 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4479
e00c8cf2
AK		 4480 /* Special registers */
4481 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4482
4483 setup_msrs(vmx);
4484
6aa8b732
AK		 4485 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4486
f78e0e2e
SY		 4487 if (cpu_has_vmx_tpr_shadow()) {
4488 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4489 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4490 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4491 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4492 vmcs_write32(TPR_THRESHOLD, 0);
4493 }
4494
4495 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4496 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4497 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4498
01e439be
YZ		 4499 if (vmx_vm_has_apicv(vcpu->kvm))
4500 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4501
2384d2b3
SY		 4502 if (vmx->vpid != 0)
4503 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4504
fa40052c 4505 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4506 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4507 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4508 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4509 vmx_fpu_activate(&vmx->vcpu);
4510 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4511
b9d762fa 4512 vpid_sync_context(vmx);
6aa8b732
AK		 4513}
4514
b6f1250e
NHE		 4515/*
4516 * In nested virtualization, check if L1 asked to exit on external interrupts.
4517 * For most existing hypervisors, this will always return true.
4518 */
4519static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4520{
4521 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4522 PIN_BASED_EXT_INTR_MASK;
4523}
4524
ea8ceb83
JK		 4525static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4526{
4527 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4528 PIN_BASED_NMI_EXITING;
4529}
4530
730dca42 4531static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4532{
4533 u32 cpu_based_vm_exec_control;
730dca42
JK		 4534
4535 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4536 /*
4537 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4538 * inject to L1 now because L2 must run. The caller will have
4539 * to make L2 exit right after entry, so we can inject to L1
4540 * more promptly.
b6f1250e 4541 */
730dca42 4542 return -EBUSY;
3b86cd99
JK		 4543
4544 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4545 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4546 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4547 return 0;
3b86cd99
JK		 4548}
4549
03b28f81 4550static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4551{
4552 u32 cpu_based_vm_exec_control;
4553
03b28f81
JK		 4554 if (!cpu_has_virtual_nmis())
4555 return enable_irq_window(vcpu);
4556
4557 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4558 return enable_irq_window(vcpu);
3b86cd99
JK		 4559
4560 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4561 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4562 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4563 return 0;
3b86cd99
JK		 4564}
4565
66fd3f7f 4566static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4567{
9c8cba37 4568 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4569 uint32_t intr;
4570 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4571
229456fc 4572 trace_kvm_inj_virq(irq);
2714d1d3 4573
fa89a817 4574 ++vcpu->stat.irq_injections;
7ffd92c5 4575 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4576 int inc_eip = 0;
4577 if (vcpu->arch.interrupt.soft)
4578 inc_eip = vcpu->arch.event_exit_inst_len;
4579 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4580 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4581 return;
4582 }
66fd3f7f
GN		 4583 intr = irq | INTR_INFO_VALID_MASK;
4584 if (vcpu->arch.interrupt.soft) {
4585 intr |= INTR_TYPE_SOFT_INTR;
4586 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4587 vmx->vcpu.arch.event_exit_inst_len);
4588 } else
4589 intr |= INTR_TYPE_EXT_INTR;
4590 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4591}
4592
f08864b4
SY		 4593static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4594{
66a5a347
JK		 4595 struct vcpu_vmx *vmx = to_vmx(vcpu);
4596
0b6ac343
NHE		 4597 if (is_guest_mode(vcpu))
4598 return;
4599
3b86cd99
JK		 4600 if (!cpu_has_virtual_nmis()) {
4601 /*
4602 * Tracking the NMI-blocked state in software is built upon
4603 * finding the next open IRQ window. This, in turn, depends on
4604 * well-behaving guests: They have to keep IRQs disabled at
4605 * least as long as the NMI handler runs. Otherwise we may
4606 * cause NMI nesting, maybe breaking the guest. But as this is
4607 * highly unlikely, we can live with the residual risk.
4608 */
4609 vmx->soft_vnmi_blocked = 1;
4610 vmx->vnmi_blocked_time = 0;
4611 }
4612
487b391d 4613 ++vcpu->stat.nmi_injections;
9d58b931 4614 vmx->nmi_known_unmasked = false;
7ffd92c5 4615 if (vmx->rmode.vm86_active) {
71f9833b 4616 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4617 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4618 return;
4619 }
f08864b4
SY		 4620 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4621 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4622}
4623
3cfc3092
JK		 4624static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4625{
4626 if (!cpu_has_virtual_nmis())
4627 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4628 if (to_vmx(vcpu)->nmi_known_unmasked)
4629 return false;
c332c83a 4630 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4631}
4632
4633static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4634{
4635 struct vcpu_vmx *vmx = to_vmx(vcpu);
4636
4637 if (!cpu_has_virtual_nmis()) {
4638 if (vmx->soft_vnmi_blocked != masked) {
4639 vmx->soft_vnmi_blocked = masked;
4640 vmx->vnmi_blocked_time = 0;
4641 }
4642 } else {
9d58b931 4643 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4644 if (masked)
4645 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4646 GUEST_INTR_STATE_NMI);
4647 else
4648 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4649 GUEST_INTR_STATE_NMI);
4650 }
4651}
4652
2505dc9f
JK		 4653static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4654{
ea8ceb83 4655 if (is_guest_mode(vcpu)) {
ea8ceb83
JK		 4656 if (to_vmx(vcpu)->nested.nested_run_pending)
4657 return 0;
4658 if (nested_exit_on_nmi(vcpu)) {
533558bc
JK		 4659 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
4660 NMI_VECTOR | INTR_TYPE_NMI_INTR |
4661 INTR_INFO_VALID_MASK, 0);
ea8ceb83
JK		 4662 /*
4663 * The NMI-triggered VM exit counts as injection:
4664 * clear this one and block further NMIs.
4665 */
4666 vcpu->arch.nmi_pending = 0;
4667 vmx_set_nmi_mask(vcpu, true);
4668 return 0;
4669 }
4670 }
4671
2505dc9f
JK		 4672 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4673 return 0;
4674
4675 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4676 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4677 | GUEST_INTR_STATE_NMI));
4678}
4679
78646121
GN		 4680static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4681{
e8457c67 4682 if (is_guest_mode(vcpu)) {
e8457c67 4683 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4684 return 0;
e8457c67 4685 if (nested_exit_on_intr(vcpu)) {
533558bc
JK		 4686 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT,
4687 0, 0);
e8457c67
JK		 4688 /*
4689 * fall through to normal code, but now in L1, not L2
4690 */
4691 }
b6f1250e
NHE		 4692 }
4693
c4282df9
GN		 4694 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4695 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4696 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4697}
4698
cbc94022
IE		 4699static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4700{
4701 int ret;
4702 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4703 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4704 .guest_phys_addr = addr,
4705 .memory_size = PAGE_SIZE * 3,
4706 .flags = 0,
4707 };
4708
47ae31e2 4709 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4710 if (ret)
4711 return ret;
bfc6d222 4712 kvm->arch.tss_addr = addr;
93ea5388
GN		 4713 if (!init_rmode_tss(kvm))
4714 return -ENOMEM;
4715
cbc94022
IE		 4716 return 0;
4717}
4718
0ca1b4f4 4719static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4720{
77ab6db0 4721 switch (vec) {
77ab6db0 4722 case BP_VECTOR:
c573cd22
JK		 4723 /*
4724 * Update instruction length as we may reinject the exception
4725 * from user space while in guest debugging mode.
4726 */
4727 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4728 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4729 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4730 return false;
4731 /* fall through */
4732 case DB_VECTOR:
4733 if (vcpu->guest_debug &
4734 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4735 return false;
d0bfb940
JK		 4736 /* fall through */
4737 case DE_VECTOR:
77ab6db0
JK		 4738 case OF_VECTOR:
4739 case BR_VECTOR:
4740 case UD_VECTOR:
4741 case DF_VECTOR:
4742 case SS_VECTOR:
4743 case GP_VECTOR:
4744 case MF_VECTOR:
0ca1b4f4
GN		 4745 return true;
4746 break;
77ab6db0 4747 }
0ca1b4f4
GN		 4748 return false;
4749}
4750
4751static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4752 int vec, u32 err_code)
4753{
4754 /*
4755 * Instruction with address size override prefix opcode 0x67
4756 * Cause the #SS fault with 0 error code in VM86 mode.
4757 */
4758 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4759 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4760 if (vcpu->arch.halt_request) {
4761 vcpu->arch.halt_request = 0;
4762 return kvm_emulate_halt(vcpu);
4763 }
4764 return 1;
4765 }
4766 return 0;
4767 }
4768
4769 /*
4770 * Forward all other exceptions that are valid in real mode.
4771 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4772 * the required debugging infrastructure rework.
4773 */
4774 kvm_queue_exception(vcpu, vec);
4775 return 1;
6aa8b732
AK		 4776}
4777
a0861c02
AK		 4778/*
4779 * Trigger machine check on the host. We assume all the MSRs are already set up
4780 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4781 * We pass a fake environment to the machine check handler because we want
4782 * the guest to be always treated like user space, no matter what context
4783 * it used internally.
4784 */
4785static void kvm_machine_check(void)
4786{
4787#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4788 struct pt_regs regs = {
4789 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4790 .flags = X86_EFLAGS_IF,
4791 };
4792
4793 do_machine_check(&regs, 0);
4794#endif
4795}
4796
851ba692 4797static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4798{
4799 /* already handled by vcpu_run */
4800 return 1;
4801}
4802
851ba692 4803static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4804{
1155f76a 4805 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4806 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4807 u32 intr_info, ex_no, error_code;
42dbaa5a 4808 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4809 u32 vect_info;
4810 enum emulation_result er;
4811
1155f76a 4812 vect_info = vmx->idt_vectoring_info;
88786475 4813 intr_info = vmx->exit_intr_info;
6aa8b732 4814
a0861c02 4815 if (is_machine_check(intr_info))
851ba692 4816 return handle_machine_check(vcpu);
a0861c02 4817
e4a41889 4818 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4819 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4820
4821 if (is_no_device(intr_info)) {
5fd86fcf 4822 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4823 return 1;
4824 }
4825
7aa81cc0 4826 if (is_invalid_opcode(intr_info)) {
51d8b661 4827 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4828 if (er != EMULATE_DONE)
7ee5d940 4829 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4830 return 1;
4831 }
4832
6aa8b732 4833 error_code = 0;
2e11384c 4834 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4835 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4836
4837 /*
4838 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4839 * MMIO, it is better to report an internal error.
4840 * See the comments in vmx_handle_exit.
4841 */
4842 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4843 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4844 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4845 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4846 vcpu->run->internal.ndata = 2;
4847 vcpu->run->internal.data[0] = vect_info;
4848 vcpu->run->internal.data[1] = intr_info;
4849 return 0;
4850 }
4851
6aa8b732 4852 if (is_page_fault(intr_info)) {
1439442c 4853 /* EPT won't cause page fault directly */
cf3ace79 4854 BUG_ON(enable_ept);
6aa8b732 4855 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4856 trace_kvm_page_fault(cr2, error_code);
4857
3298b75c 4858 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4859 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4860 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4861 }
4862
d0bfb940 4863 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4864
4865 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4866 return handle_rmode_exception(vcpu, ex_no, error_code);
4867
42dbaa5a
JK		 4868 switch (ex_no) {
4869 case DB_VECTOR:
4870 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4871 if (!(vcpu->guest_debug &
4872 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4873 vcpu->arch.dr6 &= ~15;
4874 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4875 kvm_queue_exception(vcpu, DB_VECTOR);
4876 return 1;
4877 }
4878 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4879 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4880 /* fall through */
4881 case BP_VECTOR:
c573cd22
JK		 4882 /*
4883 * Update instruction length as we may reinject #BP from
4884 * user space while in guest debugging mode. Reading it for
4885 * #DB as well causes no harm, it is not used in that case.
4886 */
4887 vmx->vcpu.arch.event_exit_inst_len =
4888 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4889 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4890 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4891 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4892 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4893 break;
4894 default:
d0bfb940
JK		 4895 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4896 kvm_run->ex.exception = ex_no;
4897 kvm_run->ex.error_code = error_code;
42dbaa5a 4898 break;
6aa8b732 4899 }
6aa8b732
AK		 4900 return 0;
4901}
4902
851ba692 4903static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4904{
1165f5fe 4905 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4906 return 1;
4907}
4908
851ba692 4909static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4910{
851ba692 4911 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4912 return 0;
4913}
6aa8b732 4914
851ba692 4915static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4916{
bfdaab09 4917 unsigned long exit_qualification;
34c33d16 4918 int size, in, string;
039576c0 4919 unsigned port;
6aa8b732 4920
bfdaab09 4921 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4922 string = (exit_qualification & 16) != 0;
cf8f70bf 4923 in = (exit_qualification & 8) != 0;
e70669ab 4924
cf8f70bf 4925 ++vcpu->stat.io_exits;
e70669ab 4926
cf8f70bf 4927 if (string || in)
51d8b661 4928 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4929
cf8f70bf
GN		 4930 port = exit_qualification >> 16;
4931 size = (exit_qualification & 7) + 1;
e93f36bc 4932 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4933
4934 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4935}
4936
102d8325
IM		 4937static void
4938vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4939{
4940 /*
4941 * Patch in the VMCALL instruction:
4942 */
4943 hypercall[0] = 0x0f;
4944 hypercall[1] = 0x01;
4945 hypercall[2] = 0xc1;
102d8325
IM		 4946}
4947
92fbc7b1
JK		 4948static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4949{
4950 unsigned long always_on = VMXON_CR0_ALWAYSON;
4951
4952 if (nested_vmx_secondary_ctls_high &
4953 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4954 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4955 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4956 return (val & always_on) == always_on;
4957}
4958
0fa06071 4959/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4960static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4961{
eeadf9e7 4962 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4963 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4964 unsigned long orig_val = val;
4965
eeadf9e7
NHE		 4966 /*
4967 * We get here when L2 changed cr0 in a way that did not change
4968 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4969 * but did change L0 shadowed bits. So we first calculate the
4970 * effective cr0 value that L1 would like to write into the
4971 * hardware. It consists of the L2-owned bits from the new
4972 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4973 */
1a0d74e6
JK		 4974 val = (val & ~vmcs12->cr0_guest_host_mask) |
4975 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4976
92fbc7b1 4977 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4978 return 1;
1a0d74e6
JK		 4979
4980 if (kvm_set_cr0(vcpu, val))
4981 return 1;
4982 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4983 return 0;
1a0d74e6
JK		 4984 } else {
4985 if (to_vmx(vcpu)->nested.vmxon &&
4986 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4987 return 1;
eeadf9e7 4988 return kvm_set_cr0(vcpu, val);
1a0d74e6 4989 }
eeadf9e7
NHE		 4990}
4991
4992static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4993{
4994 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4995 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4996 unsigned long orig_val = val;
4997
4998 /* analogously to handle_set_cr0 */
4999 val = (val & ~vmcs12->cr4_guest_host_mask) |
5000 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5001 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5002 return 1;
1a0d74e6 5003 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5004 return 0;
5005 } else
5006 return kvm_set_cr4(vcpu, val);
5007}
5008
5009/* called to set cr0 as approriate for clts instruction exit. */
5010static void handle_clts(struct kvm_vcpu *vcpu)
5011{
5012 if (is_guest_mode(vcpu)) {
5013 /*
5014 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5015 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5016 * just pretend it's off (also in arch.cr0 for fpu_activate).
5017 */
5018 vmcs_writel(CR0_READ_SHADOW,
5019 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5020 vcpu->arch.cr0 &= ~X86_CR0_TS;
5021 } else
5022 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5023}
5024
851ba692 5025static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5026{
229456fc 5027 unsigned long exit_qualification, val;
6aa8b732
AK		 5028 int cr;
5029 int reg;
49a9b07e 5030 int err;
6aa8b732 5031
bfdaab09 5032 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5033 cr = exit_qualification & 15;
5034 reg = (exit_qualification >> 8) & 15;
5035 switch ((exit_qualification >> 4) & 3) {
5036 case 0: /* mov to cr */
229456fc
MT		 5037 val = kvm_register_read(vcpu, reg);
5038 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5039 switch (cr) {
5040 case 0:
eeadf9e7 5041 err = handle_set_cr0(vcpu, val);
db8fcefa 5042 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5043 return 1;
5044 case 3:
2390218b 5045 err = kvm_set_cr3(vcpu, val);
db8fcefa 5046 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5047 return 1;
5048 case 4:
eeadf9e7 5049 err = handle_set_cr4(vcpu, val);
db8fcefa 5050 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5051 return 1;
0a5fff19
GN		 5052 case 8: {
5053 u8 cr8_prev = kvm_get_cr8(vcpu);
5054 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5055 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5056 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5057 if (irqchip_in_kernel(vcpu->kvm))
5058 return 1;
5059 if (cr8_prev <= cr8)
5060 return 1;
851ba692 5061 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5062 return 0;
5063 }
4b8073e4 5064 }
6aa8b732 5065 break;
25c4c276 5066 case 2: /* clts */
eeadf9e7 5067 handle_clts(vcpu);
4d4ec087 5068 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5069 skip_emulated_instruction(vcpu);
6b52d186 5070 vmx_fpu_activate(vcpu);
25c4c276 5071 return 1;
6aa8b732
AK		 5072 case 1: /*mov from cr*/
5073 switch (cr) {
5074 case 3:
9f8fe504
AK		 5075 val = kvm_read_cr3(vcpu);
5076 kvm_register_write(vcpu, reg, val);
5077 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5078 skip_emulated_instruction(vcpu);
5079 return 1;
5080 case 8:
229456fc
MT		 5081 val = kvm_get_cr8(vcpu);
5082 kvm_register_write(vcpu, reg, val);
5083 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5084 skip_emulated_instruction(vcpu);
5085 return 1;
5086 }
5087 break;
5088 case 3: /* lmsw */
a1f83a74 5089 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5090 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5091 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5092
5093 skip_emulated_instruction(vcpu);
5094 return 1;
5095 default:
5096 break;
5097 }
851ba692 5098 vcpu->run->exit_reason = 0;
a737f256 5099 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5100 (int)(exit_qualification >> 4) & 3, cr);
5101 return 0;
5102}
5103
851ba692 5104static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5105{
bfdaab09 5106 unsigned long exit_qualification;
6aa8b732
AK		 5107 int dr, reg;
5108
f2483415 5109 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5110 if (!kvm_require_cpl(vcpu, 0))
5111 return 1;
42dbaa5a
JK		 5112 dr = vmcs_readl(GUEST_DR7);
5113 if (dr & DR7_GD) {
5114 /*
5115 * As the vm-exit takes precedence over the debug trap, we
5116 * need to emulate the latter, either for the host or the
5117 * guest debugging itself.
5118 */
5119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5120 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5121 vcpu->run->debug.arch.dr7 = dr;
5122 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5123 vmcs_readl(GUEST_CS_BASE) +
5124 vmcs_readl(GUEST_RIP);
851ba692
AK		 5125 vcpu->run->debug.arch.exception = DB_VECTOR;
5126 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5127 return 0;
5128 } else {
5129 vcpu->arch.dr7 &= ~DR7_GD;
5130 vcpu->arch.dr6 |= DR6_BD;
5131 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5132 kvm_queue_exception(vcpu, DB_VECTOR);
5133 return 1;
5134 }
5135 }
5136
bfdaab09 5137 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5138 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5139 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5140 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5141 unsigned long val;
4c4d563b
JK		 5142
5143 if (kvm_get_dr(vcpu, dr, &val))
5144 return 1;
5145 kvm_register_write(vcpu, reg, val);
020df079 5146 } else
4c4d563b
JK		 5147 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5148 return 1;
5149
6aa8b732
AK		 5150 skip_emulated_instruction(vcpu);
5151 return 1;
5152}
5153
73aaf249
JK		 5154static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5155{
5156 return vcpu->arch.dr6;
5157}
5158
5159static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5160{
5161}
5162
020df079
GN		 5163static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5164{
5165 vmcs_writel(GUEST_DR7, val);
5166}
5167
851ba692 5168static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5169{
06465c5a
AK		 5170 kvm_emulate_cpuid(vcpu);
5171 return 1;
6aa8b732
AK		 5172}
5173
851ba692 5174static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5175{
ad312c7c 5176 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5177 u64 data;
5178
5179 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5180 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5181 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5182 return 1;
5183 }
5184
229456fc 5185 trace_kvm_msr_read(ecx, data);
2714d1d3 5186
6aa8b732 5187 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5188 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5189 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5190 skip_emulated_instruction(vcpu);
5191 return 1;
5192}
5193
851ba692 5194static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5195{
8fe8ab46 5196 struct msr_data msr;
ad312c7c
ZX		 5197 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5198 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5199 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5200
8fe8ab46
WA		 5201 msr.data = data;
5202 msr.index = ecx;
5203 msr.host_initiated = false;
5204 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5205 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5206 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5207 return 1;
5208 }
5209
59200273 5210 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5211 skip_emulated_instruction(vcpu);
5212 return 1;
5213}
5214
851ba692 5215static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5216{
3842d135 5217 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5218 return 1;
5219}
5220
851ba692 5221static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5222{
85f455f7
ED		 5223 u32 cpu_based_vm_exec_control;
5224
5225 /* clear pending irq */
5226 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5227 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5228 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5229
3842d135
AK		 5230 kvm_make_request(KVM_REQ_EVENT, vcpu);
5231
a26bf12a 5232 ++vcpu->stat.irq_window_exits;
2714d1d3 5233
c1150d8c
DL		 5234 /*
5235 * If the user space waits to inject interrupts, exit as soon as
5236 * possible
5237 */
8061823a 5238 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5239 vcpu->run->request_interrupt_window &&
8061823a 5240 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5241 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5242 return 0;
5243 }
6aa8b732
AK		 5244 return 1;
5245}
5246
851ba692 5247static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5248{
5249 skip_emulated_instruction(vcpu);
d3bef15f 5250 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5251}
5252
851ba692 5253static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5254{
510043da 5255 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5256 kvm_emulate_hypercall(vcpu);
5257 return 1;
c21415e8
IM		 5258}
5259
ec25d5e6
GN		 5260static int handle_invd(struct kvm_vcpu *vcpu)
5261{
51d8b661 5262 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5263}
5264
851ba692 5265static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5266{
f9c617f6 5267 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5268
5269 kvm_mmu_invlpg(vcpu, exit_qualification);
5270 skip_emulated_instruction(vcpu);
5271 return 1;
5272}
5273
fee84b07
AK		 5274static int handle_rdpmc(struct kvm_vcpu *vcpu)
5275{
5276 int err;
5277
5278 err = kvm_rdpmc(vcpu);
5279 kvm_complete_insn_gp(vcpu, err);
5280
5281 return 1;
5282}
5283
851ba692 5284static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5285{
5286 skip_emulated_instruction(vcpu);
f5f48ee1 5287 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5288 return 1;
5289}
5290
2acf923e
DC		 5291static int handle_xsetbv(struct kvm_vcpu *vcpu)
5292{
5293 u64 new_bv = kvm_read_edx_eax(vcpu);
5294 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5295
5296 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5297 skip_emulated_instruction(vcpu);
5298 return 1;
5299}
5300
851ba692 5301static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5302{
58fbbf26
KT		 5303 if (likely(fasteoi)) {
5304 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5305 int access_type, offset;
5306
5307 access_type = exit_qualification & APIC_ACCESS_TYPE;
5308 offset = exit_qualification & APIC_ACCESS_OFFSET;
5309 /*
5310 * Sane guest uses MOV to write EOI, with written value
5311 * not cared. So make a short-circuit here by avoiding
5312 * heavy instruction emulation.
5313 */
5314 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5315 (offset == APIC_EOI)) {
5316 kvm_lapic_set_eoi(vcpu);
5317 skip_emulated_instruction(vcpu);
5318 return 1;
5319 }
5320 }
51d8b661 5321 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5322}
5323
c7c9c56c
YZ		 5324static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5325{
5326 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5327 int vector = exit_qualification & 0xff;
5328
5329 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5330 kvm_apic_set_eoi_accelerated(vcpu, vector);
5331 return 1;
5332}
5333
83d4c286
YZ		 5334static int handle_apic_write(struct kvm_vcpu *vcpu)
5335{
5336 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5337 u32 offset = exit_qualification & 0xfff;
5338
5339 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5340 kvm_apic_write_nodecode(vcpu, offset);
5341 return 1;
5342}
5343
851ba692 5344static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5345{
60637aac 5346 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5347 unsigned long exit_qualification;
e269fb21
JK		 5348 bool has_error_code = false;
5349 u32 error_code = 0;
37817f29 5350 u16 tss_selector;
7f3d35fd 5351 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5352
5353 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5354 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5355 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5356
5357 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5358
5359 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5360 if (reason == TASK_SWITCH_GATE && idt_v) {
5361 switch (type) {
5362 case INTR_TYPE_NMI_INTR:
5363 vcpu->arch.nmi_injected = false;
654f06fc 5364 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5365 break;
5366 case INTR_TYPE_EXT_INTR:
66fd3f7f 5367 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5368 kvm_clear_interrupt_queue(vcpu);
5369 break;
5370 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5371 if (vmx->idt_vectoring_info &
5372 VECTORING_INFO_DELIVER_CODE_MASK) {
5373 has_error_code = true;
5374 error_code =
5375 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5376 }
5377 /* fall through */
64a7ec06
GN		 5378 case INTR_TYPE_SOFT_EXCEPTION:
5379 kvm_clear_exception_queue(vcpu);
5380 break;
5381 default:
5382 break;
5383 }
60637aac 5384 }
37817f29
IE		 5385 tss_selector = exit_qualification;
5386
64a7ec06
GN		 5387 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5388 type != INTR_TYPE_EXT_INTR &&
5389 type != INTR_TYPE_NMI_INTR))
5390 skip_emulated_instruction(vcpu);
5391
7f3d35fd
KW		 5392 if (kvm_task_switch(vcpu, tss_selector,
5393 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5394 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5395 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5396 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5397 vcpu->run->internal.ndata = 0;
42dbaa5a 5398 return 0;
acb54517 5399 }
42dbaa5a
JK		 5400
5401 /* clear all local breakpoint enable flags */
5402 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5403
5404 /*
5405 * TODO: What about debug traps on tss switch?
5406 * Are we supposed to inject them and update dr6?
5407 */
5408
5409 return 1;
37817f29
IE		 5410}
5411
851ba692 5412static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5413{
f9c617f6 5414 unsigned long exit_qualification;
1439442c 5415 gpa_t gpa;
4f5982a5 5416 u32 error_code;
1439442c 5417 int gla_validity;
1439442c 5418
f9c617f6 5419 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5420
1439442c
SY		 5421 gla_validity = (exit_qualification >> 7) & 0x3;
5422 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5423 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5424 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5425 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5426 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5427 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5428 (long unsigned int)exit_qualification);
851ba692
AK		 5429 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5430 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5431 return 0;
1439442c
SY		 5432 }
5433
0be9c7a8
GN		 5434 /*
5435 * EPT violation happened while executing iret from NMI,
5436 * "blocked by NMI" bit has to be set before next VM entry.
5437 * There are errata that may cause this bit to not be set:
5438 * AAK134, BY25.
5439 */
bcd1c294
GN		 5440 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5441 cpu_has_virtual_nmis() &&
5442 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5443 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5444
1439442c 5445 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5446 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5447
5448 /* It is a write fault? */
5449 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5450 /* It is a fetch fault? */
5451 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5452 /* ept page table is present? */
5453 error_code |= (exit_qualification >> 3) & 0x1;
5454
25d92081
YZ		 5455 vcpu->arch.exit_qualification = exit_qualification;
5456
4f5982a5 5457 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5458}
5459
68f89400
MT		 5460static u64 ept_rsvd_mask(u64 spte, int level)
5461{
5462 int i;
5463 u64 mask = 0;
5464
5465 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5466 mask |= (1ULL << i);
5467
5468 if (level > 2)
5469 /* bits 7:3 reserved */
5470 mask |= 0xf8;
5471 else if (level == 2) {
5472 if (spte & (1ULL << 7))
5473 /* 2MB ref, bits 20:12 reserved */
5474 mask |= 0x1ff000;
5475 else
5476 /* bits 6:3 reserved */
5477 mask |= 0x78;
5478 }
5479
5480 return mask;
5481}
5482
5483static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5484 int level)
5485{
5486 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5487
5488 /* 010b (write-only) */
5489 WARN_ON((spte & 0x7) == 0x2);
5490
5491 /* 110b (write/execute) */
5492 WARN_ON((spte & 0x7) == 0x6);
5493
5494 /* 100b (execute-only) and value not supported by logical processor */
5495 if (!cpu_has_vmx_ept_execute_only())
5496 WARN_ON((spte & 0x7) == 0x4);
5497
5498 /* not 000b */
5499 if ((spte & 0x7)) {
5500 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5501
5502 if (rsvd_bits != 0) {
5503 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5504 __func__, rsvd_bits);
5505 WARN_ON(1);
5506 }
5507
5508 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5509 u64 ept_mem_type = (spte & 0x38) >> 3;
5510
5511 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5512 ept_mem_type == 7) {
5513 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5514 __func__, ept_mem_type);
5515 WARN_ON(1);
5516 }
5517 }
5518 }
5519}
5520
851ba692 5521static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5522{
5523 u64 sptes[4];
ce88decf 5524 int nr_sptes, i, ret;
68f89400
MT		 5525 gpa_t gpa;
5526
5527 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5528
ce88decf 5529 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5530 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5531 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5532 EMULATE_DONE;
f8f55942
XG		 5533
5534 if (unlikely(ret == RET_MMIO_PF_INVALID))
5535 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5536
b37fbea6 5537 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5538 return 1;
5539
5540 /* It is the real ept misconfig */
68f89400
MT		 5541 printk(KERN_ERR "EPT: Misconfiguration.\n");
5542 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5543
5544 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5545
5546 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5547 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5548
851ba692
AK		 5549 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5550 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5551
5552 return 0;
5553}
5554
851ba692 5555static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5556{
5557 u32 cpu_based_vm_exec_control;
5558
5559 /* clear pending NMI */
5560 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5561 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5562 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5563 ++vcpu->stat.nmi_window_exits;
3842d135 5564 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5565
5566 return 1;
5567}
5568
80ced186 5569static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5570{
8b3079a5
AK		 5571 struct vcpu_vmx *vmx = to_vmx(vcpu);
5572 enum emulation_result err = EMULATE_DONE;
80ced186 5573 int ret = 1;
49e9d557
AK		 5574 u32 cpu_exec_ctrl;
5575 bool intr_window_requested;
b8405c18 5576 unsigned count = 130;
49e9d557
AK		 5577
5578 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5579 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5580
b8405c18 5581 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5582 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5583 return handle_interrupt_window(&vmx->vcpu);
5584
de87dcdd
AK		 5585 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5586 return 1;
5587
991eebf9 5588 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5589
ac0a48c3 5590 if (err == EMULATE_USER_EXIT) {
94452b9e 5591 ++vcpu->stat.mmio_exits;
80ced186
MG		 5592 ret = 0;
5593 goto out;
5594 }
1d5a4d9b 5595
de5f70e0
AK		 5596 if (err != EMULATE_DONE) {
5597 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5598 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5599 vcpu->run->internal.ndata = 0;
6d77dbfc 5600 return 0;
de5f70e0 5601 }
ea953ef0 5602
8d76c49e
GN		 5603 if (vcpu->arch.halt_request) {
5604 vcpu->arch.halt_request = 0;
5605 ret = kvm_emulate_halt(vcpu);
5606 goto out;
5607 }
5608
ea953ef0 5609 if (signal_pending(current))
80ced186 5610 goto out;
ea953ef0
MG		 5611 if (need_resched())
5612 schedule();
5613 }
5614
14168786 5615 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5616out:
5617 return ret;
ea953ef0
MG		 5618}
5619
4b8d54f9
ZE		 5620/*
5621 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5622 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5623 */
9fb41ba8 5624static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5625{
5626 skip_emulated_instruction(vcpu);
5627 kvm_vcpu_on_spin(vcpu);
5628
5629 return 1;
5630}
5631
59708670
SY		 5632static int handle_invalid_op(struct kvm_vcpu *vcpu)
5633{
5634 kvm_queue_exception(vcpu, UD_VECTOR);
5635 return 1;
5636}
5637
ff2f6fe9
NHE		 5638/*
5639 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5640 * We could reuse a single VMCS for all the L2 guests, but we also want the
5641 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5642 * allows keeping them loaded on the processor, and in the future will allow
5643 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5644 * every entry if they never change.
5645 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5646 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5647 *
5648 * The following functions allocate and free a vmcs02 in this pool.
5649 */
5650
5651/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5652static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5653{
5654 struct vmcs02_list *item;
5655 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5656 if (item->vmptr == vmx->nested.current_vmptr) {
5657 list_move(&item->list, &vmx->nested.vmcs02_pool);
5658 return &item->vmcs02;
5659 }
5660
5661 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5662 /* Recycle the least recently used VMCS. */
5663 item = list_entry(vmx->nested.vmcs02_pool.prev,
5664 struct vmcs02_list, list);
5665 item->vmptr = vmx->nested.current_vmptr;
5666 list_move(&item->list, &vmx->nested.vmcs02_pool);
5667 return &item->vmcs02;
5668 }
5669
5670 /* Create a new VMCS */
0fa24ce3 5671 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5672 if (!item)
5673 return NULL;
5674 item->vmcs02.vmcs = alloc_vmcs();
5675 if (!item->vmcs02.vmcs) {
5676 kfree(item);
5677 return NULL;
5678 }
5679 loaded_vmcs_init(&item->vmcs02);
5680 item->vmptr = vmx->nested.current_vmptr;
5681 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5682 vmx->nested.vmcs02_num++;
5683 return &item->vmcs02;
5684}
5685
5686/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5687static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5688{
5689 struct vmcs02_list *item;
5690 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5691 if (item->vmptr == vmptr) {
5692 free_loaded_vmcs(&item->vmcs02);
5693 list_del(&item->list);
5694 kfree(item);
5695 vmx->nested.vmcs02_num--;
5696 return;
5697 }
5698}
5699
5700/*
5701 * Free all VMCSs saved for this vcpu, except the one pointed by
5702 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5703 * currently used, if running L2), and vmcs01 when running L2.
5704 */
5705static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5706{
5707 struct vmcs02_list *item, *n;
5708 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5709 if (vmx->loaded_vmcs != &item->vmcs02)
5710 free_loaded_vmcs(&item->vmcs02);
5711 list_del(&item->list);
5712 kfree(item);
5713 }
5714 vmx->nested.vmcs02_num = 0;
5715
5716 if (vmx->loaded_vmcs != &vmx->vmcs01)
5717 free_loaded_vmcs(&vmx->vmcs01);
5718}
5719
0658fbaa
ACL		 5720/*
5721 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5722 * set the success or error code of an emulated VMX instruction, as specified
5723 * by Vol 2B, VMX Instruction Reference, "Conventions".
5724 */
5725static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5726{
5727 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5728 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5729 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5730}
5731
5732static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5733{
5734 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5735 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5736 X86_EFLAGS_SF | X86_EFLAGS_OF))
5737 | X86_EFLAGS_CF);
5738}
5739
145c28dd 5740static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5741 u32 vm_instruction_error)
5742{
5743 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5744 /*
5745 * failValid writes the error number to the current VMCS, which
5746 * can't be done there isn't a current VMCS.
5747 */
5748 nested_vmx_failInvalid(vcpu);
5749 return;
5750 }
5751 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5752 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5753 X86_EFLAGS_SF | X86_EFLAGS_OF))
5754 | X86_EFLAGS_ZF);
5755 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5756 /*
5757 * We don't need to force a shadow sync because
5758 * VM_INSTRUCTION_ERROR is not shadowed
5759 */
5760}
145c28dd 5761
ec378aee
NHE		 5762/*
5763 * Emulate the VMXON instruction.
5764 * Currently, we just remember that VMX is active, and do not save or even
5765 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5766 * do not currently need to store anything in that guest-allocated memory
5767 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5768 * argument is different from the VMXON pointer (which the spec says they do).
5769 */
5770static int handle_vmon(struct kvm_vcpu *vcpu)
5771{
5772 struct kvm_segment cs;
5773 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5774 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5775 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5776 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5777
5778 /* The Intel VMX Instruction Reference lists a bunch of bits that
5779 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5780 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5781 * Otherwise, we should fail with #UD. We test these now:
5782 */
5783 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5784 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5785 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5786 kvm_queue_exception(vcpu, UD_VECTOR);
5787 return 1;
5788 }
5789
5790 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5791 if (is_long_mode(vcpu) && !cs.l) {
5792 kvm_queue_exception(vcpu, UD_VECTOR);
5793 return 1;
5794 }
5795
5796 if (vmx_get_cpl(vcpu)) {
5797 kvm_inject_gp(vcpu, 0);
5798 return 1;
5799 }
145c28dd
AG		 5800 if (vmx->nested.vmxon) {
5801 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5802 skip_emulated_instruction(vcpu);
5803 return 1;
5804 }
b3897a49
NHE		 5805
5806 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5807 != VMXON_NEEDED_FEATURES) {
5808 kvm_inject_gp(vcpu, 0);
5809 return 1;
5810 }
5811
8de48833
AG		 5812 if (enable_shadow_vmcs) {
5813 shadow_vmcs = alloc_vmcs();
5814 if (!shadow_vmcs)
5815 return -ENOMEM;
5816 /* mark vmcs as shadow */
5817 shadow_vmcs->revision_id |= (1u << 31);
5818 /* init shadow vmcs */
5819 vmcs_clear(shadow_vmcs);
5820 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5821 }
ec378aee 5822
ff2f6fe9
NHE		 5823 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5824 vmx->nested.vmcs02_num = 0;
5825
ec378aee
NHE		 5826 vmx->nested.vmxon = true;
5827
5828 skip_emulated_instruction(vcpu);
a25eb114 5829 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5830 return 1;
5831}
5832
5833/*
5834 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5835 * for running VMX instructions (except VMXON, whose prerequisites are
5836 * slightly different). It also specifies what exception to inject otherwise.
5837 */
5838static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5839{
5840 struct kvm_segment cs;
5841 struct vcpu_vmx *vmx = to_vmx(vcpu);
5842
5843 if (!vmx->nested.vmxon) {
5844 kvm_queue_exception(vcpu, UD_VECTOR);
5845 return 0;
5846 }
5847
5848 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5849 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5850 (is_long_mode(vcpu) && !cs.l)) {
5851 kvm_queue_exception(vcpu, UD_VECTOR);
5852 return 0;
5853 }
5854
5855 if (vmx_get_cpl(vcpu)) {
5856 kvm_inject_gp(vcpu, 0);
5857 return 0;
5858 }
5859
5860 return 1;
5861}
5862
e7953d7f
AG		 5863static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5864{
8a1b9dd0 5865 u32 exec_control;
012f83cb
AG		 5866 if (enable_shadow_vmcs) {
5867 if (vmx->nested.current_vmcs12 != NULL) {
5868 /* copy to memory all shadowed fields in case
5869 they were modified */
5870 copy_shadow_to_vmcs12(vmx);
5871 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5872 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5873 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5874 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5875 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5876 }
5877 }
e7953d7f
AG		 5878 kunmap(vmx->nested.current_vmcs12_page);
5879 nested_release_page(vmx->nested.current_vmcs12_page);
5880}
5881
ec378aee
NHE		 5882/*
5883 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5884 * just stops using VMX.
5885 */
5886static void free_nested(struct vcpu_vmx *vmx)
5887{
5888 if (!vmx->nested.vmxon)
5889 return;
5890 vmx->nested.vmxon = false;
a9d30f33 5891 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5892 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5893 vmx->nested.current_vmptr = -1ull;
5894 vmx->nested.current_vmcs12 = NULL;
5895 }
e7953d7f
AG		 5896 if (enable_shadow_vmcs)
5897 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5898 /* Unpin physical memory we referred to in current vmcs02 */
5899 if (vmx->nested.apic_access_page) {
5900 nested_release_page(vmx->nested.apic_access_page);
5901 vmx->nested.apic_access_page = 0;
5902 }
ff2f6fe9
NHE		 5903
5904 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5905}
5906
5907/* Emulate the VMXOFF instruction */
5908static int handle_vmoff(struct kvm_vcpu *vcpu)
5909{
5910 if (!nested_vmx_check_permission(vcpu))
5911 return 1;
5912 free_nested(to_vmx(vcpu));
5913 skip_emulated_instruction(vcpu);
a25eb114 5914 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5915 return 1;
5916}
5917
064aea77
NHE		 5918/*
5919 * Decode the memory-address operand of a vmx instruction, as recorded on an
5920 * exit caused by such an instruction (run by a guest hypervisor).
5921 * On success, returns 0. When the operand is invalid, returns 1 and throws
5922 * #UD or #GP.
5923 */
5924static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5925 unsigned long exit_qualification,
5926 u32 vmx_instruction_info, gva_t *ret)
5927{
5928 /*
5929 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5930 * Execution", on an exit, vmx_instruction_info holds most of the
5931 * addressing components of the operand. Only the displacement part
5932 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5933 * For how an actual address is calculated from all these components,
5934 * refer to Vol. 1, "Operand Addressing".
5935 */
5936 int scaling = vmx_instruction_info & 3;
5937 int addr_size = (vmx_instruction_info >> 7) & 7;
5938 bool is_reg = vmx_instruction_info & (1u << 10);
5939 int seg_reg = (vmx_instruction_info >> 15) & 7;
5940 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5941 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5942 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5943 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5944
5945 if (is_reg) {
5946 kvm_queue_exception(vcpu, UD_VECTOR);
5947 return 1;
5948 }
5949
5950 /* Addr = segment_base + offset */
5951 /* offset = base + [index * scale] + displacement */
5952 *ret = vmx_get_segment_base(vcpu, seg_reg);
5953 if (base_is_valid)
5954 *ret += kvm_register_read(vcpu, base_reg);
5955 if (index_is_valid)
5956 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5957 *ret += exit_qualification; /* holds the displacement */
5958
5959 if (addr_size == 1) /* 32 bit */
5960 *ret &= 0xffffffff;
5961
5962 /*
5963 * TODO: throw #GP (and return 1) in various cases that the VM*
5964 * instructions require it - e.g., offset beyond segment limit,
5965 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5966 * address, and so on. Currently these are not checked.
5967 */
5968 return 0;
5969}
5970
27d6c865
NHE		 5971/* Emulate the VMCLEAR instruction */
5972static int handle_vmclear(struct kvm_vcpu *vcpu)
5973{
5974 struct vcpu_vmx *vmx = to_vmx(vcpu);
5975 gva_t gva;
5976 gpa_t vmptr;
5977 struct vmcs12 *vmcs12;
5978 struct page *page;
5979 struct x86_exception e;
5980
5981 if (!nested_vmx_check_permission(vcpu))
5982 return 1;
5983
5984 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5985 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5986 return 1;
5987
5988 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5989 sizeof(vmptr), &e)) {
5990 kvm_inject_page_fault(vcpu, &e);
5991 return 1;
5992 }
5993
5994 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5995 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5996 skip_emulated_instruction(vcpu);
5997 return 1;
5998 }
5999
6000 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6001 nested_release_vmcs12(vmx);
27d6c865
NHE		 6002 vmx->nested.current_vmptr = -1ull;
6003 vmx->nested.current_vmcs12 = NULL;
6004 }
6005
6006 page = nested_get_page(vcpu, vmptr);
6007 if (page == NULL) {
6008 /*
6009 * For accurate processor emulation, VMCLEAR beyond available
6010 * physical memory should do nothing at all. However, it is
6011 * possible that a nested vmx bug, not a guest hypervisor bug,
6012 * resulted in this case, so let's shut down before doing any
6013 * more damage:
6014 */
6015 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6016 return 1;
6017 }
6018 vmcs12 = kmap(page);
6019 vmcs12->launch_state = 0;
6020 kunmap(page);
6021 nested_release_page(page);
6022
6023 nested_free_vmcs02(vmx, vmptr);
6024
6025 skip_emulated_instruction(vcpu);
6026 nested_vmx_succeed(vcpu);
6027 return 1;
6028}
6029
cd232ad0
NHE		 6030static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6031
6032/* Emulate the VMLAUNCH instruction */
6033static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6034{
6035 return nested_vmx_run(vcpu, true);
6036}
6037
6038/* Emulate the VMRESUME instruction */
6039static int handle_vmresume(struct kvm_vcpu *vcpu)
6040{
6041
6042 return nested_vmx_run(vcpu, false);
6043}
6044
49f705c5
NHE		 6045enum vmcs_field_type {
6046 VMCS_FIELD_TYPE_U16 = 0,
6047 VMCS_FIELD_TYPE_U64 = 1,
6048 VMCS_FIELD_TYPE_U32 = 2,
6049 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6050};
6051
6052static inline int vmcs_field_type(unsigned long field)
6053{
6054 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6055 return VMCS_FIELD_TYPE_U32;
6056 return (field >> 13) & 0x3 ;
6057}
6058
6059static inline int vmcs_field_readonly(unsigned long field)
6060{
6061 return (((field >> 10) & 0x3) == 1);
6062}
6063
6064/*
6065 * Read a vmcs12 field. Since these can have varying lengths and we return
6066 * one type, we chose the biggest type (u64) and zero-extend the return value
6067 * to that size. Note that the caller, handle_vmread, might need to use only
6068 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6069 * 64-bit fields are to be returned).
6070 */
6071static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6072 unsigned long field, u64 *ret)
6073{
6074 short offset = vmcs_field_to_offset(field);
6075 char *p;
6076
6077 if (offset < 0)
6078 return 0;
6079
6080 p = ((char *)(get_vmcs12(vcpu))) + offset;
6081
6082 switch (vmcs_field_type(field)) {
6083 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6084 *ret = *((natural_width *)p);
6085 return 1;
6086 case VMCS_FIELD_TYPE_U16:
6087 *ret = *((u16 *)p);
6088 return 1;
6089 case VMCS_FIELD_TYPE_U32:
6090 *ret = *((u32 *)p);
6091 return 1;
6092 case VMCS_FIELD_TYPE_U64:
6093 *ret = *((u64 *)p);
6094 return 1;
6095 default:
6096 return 0; /* can never happen. */
6097 }
6098}
6099
20b97fea
AG		 6100
6101static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6102 unsigned long field, u64 field_value){
6103 short offset = vmcs_field_to_offset(field);
6104 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6105 if (offset < 0)
6106 return false;
6107
6108 switch (vmcs_field_type(field)) {
6109 case VMCS_FIELD_TYPE_U16:
6110 *(u16 *)p = field_value;
6111 return true;
6112 case VMCS_FIELD_TYPE_U32:
6113 *(u32 *)p = field_value;
6114 return true;
6115 case VMCS_FIELD_TYPE_U64:
6116 *(u64 *)p = field_value;
6117 return true;
6118 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6119 *(natural_width *)p = field_value;
6120 return true;
6121 default:
6122 return false; /* can never happen. */
6123 }
6124
6125}
6126
16f5b903
AG		 6127static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6128{
6129 int i;
6130 unsigned long field;
6131 u64 field_value;
6132 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6133 const unsigned long *fields = shadow_read_write_fields;
6134 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6135
6136 vmcs_load(shadow_vmcs);
6137
6138 for (i = 0; i < num_fields; i++) {
6139 field = fields[i];
6140 switch (vmcs_field_type(field)) {
6141 case VMCS_FIELD_TYPE_U16:
6142 field_value = vmcs_read16(field);
6143 break;
6144 case VMCS_FIELD_TYPE_U32:
6145 field_value = vmcs_read32(field);
6146 break;
6147 case VMCS_FIELD_TYPE_U64:
6148 field_value = vmcs_read64(field);
6149 break;
6150 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6151 field_value = vmcs_readl(field);
6152 break;
6153 }
6154 vmcs12_write_any(&vmx->vcpu, field, field_value);
6155 }
6156
6157 vmcs_clear(shadow_vmcs);
6158 vmcs_load(vmx->loaded_vmcs->vmcs);
6159}
6160
c3114420
AG		 6161static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6162{
c2bae893
MK		 6163 const unsigned long *fields[] = {
6164 shadow_read_write_fields,
6165 shadow_read_only_fields
c3114420 6166 };
c2bae893 6167 const int max_fields[] = {
c3114420
AG		 6168 max_shadow_read_write_fields,
6169 max_shadow_read_only_fields
6170 };
6171 int i, q;
6172 unsigned long field;
6173 u64 field_value = 0;
6174 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6175
6176 vmcs_load(shadow_vmcs);
6177
c2bae893 6178 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6179 for (i = 0; i < max_fields[q]; i++) {
6180 field = fields[q][i];
6181 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6182
6183 switch (vmcs_field_type(field)) {
6184 case VMCS_FIELD_TYPE_U16:
6185 vmcs_write16(field, (u16)field_value);
6186 break;
6187 case VMCS_FIELD_TYPE_U32:
6188 vmcs_write32(field, (u32)field_value);
6189 break;
6190 case VMCS_FIELD_TYPE_U64:
6191 vmcs_write64(field, (u64)field_value);
6192 break;
6193 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6194 vmcs_writel(field, (long)field_value);
6195 break;
6196 }
6197 }
6198 }
6199
6200 vmcs_clear(shadow_vmcs);
6201 vmcs_load(vmx->loaded_vmcs->vmcs);
6202}
6203
49f705c5
NHE		 6204/*
6205 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6206 * used before) all generate the same failure when it is missing.
6207 */
6208static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6209{
6210 struct vcpu_vmx *vmx = to_vmx(vcpu);
6211 if (vmx->nested.current_vmptr == -1ull) {
6212 nested_vmx_failInvalid(vcpu);
6213 skip_emulated_instruction(vcpu);
6214 return 0;
6215 }
6216 return 1;
6217}
6218
6219static int handle_vmread(struct kvm_vcpu *vcpu)
6220{
6221 unsigned long field;
6222 u64 field_value;
6223 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6224 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6225 gva_t gva = 0;
6226
6227 if (!nested_vmx_check_permission(vcpu) ||
6228 !nested_vmx_check_vmcs12(vcpu))
6229 return 1;
6230
6231 /* Decode instruction info and find the field to read */
6232 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6233 /* Read the field, zero-extended to a u64 field_value */
6234 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6235 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6236 skip_emulated_instruction(vcpu);
6237 return 1;
6238 }
6239 /*
6240 * Now copy part of this value to register or memory, as requested.
6241 * Note that the number of bits actually copied is 32 or 64 depending
6242 * on the guest's mode (32 or 64 bit), not on the given field's length.
6243 */
6244 if (vmx_instruction_info & (1u << 10)) {
6245 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6246 field_value);
6247 } else {
6248 if (get_vmx_mem_address(vcpu, exit_qualification,
6249 vmx_instruction_info, &gva))
6250 return 1;
6251 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6252 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6253 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6254 }
6255
6256 nested_vmx_succeed(vcpu);
6257 skip_emulated_instruction(vcpu);
6258 return 1;
6259}
6260
6261
6262static int handle_vmwrite(struct kvm_vcpu *vcpu)
6263{
6264 unsigned long field;
6265 gva_t gva;
6266 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6267 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6268 /* The value to write might be 32 or 64 bits, depending on L1's long
6269 * mode, and eventually we need to write that into a field of several
6270 * possible lengths. The code below first zero-extends the value to 64
6271 * bit (field_value), and then copies only the approriate number of
6272 * bits into the vmcs12 field.
6273 */
6274 u64 field_value = 0;
6275 struct x86_exception e;
6276
6277 if (!nested_vmx_check_permission(vcpu) ||
6278 !nested_vmx_check_vmcs12(vcpu))
6279 return 1;
6280
6281 if (vmx_instruction_info & (1u << 10))
6282 field_value = kvm_register_read(vcpu,
6283 (((vmx_instruction_info) >> 3) & 0xf));
6284 else {
6285 if (get_vmx_mem_address(vcpu, exit_qualification,
6286 vmx_instruction_info, &gva))
6287 return 1;
6288 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6289 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6290 kvm_inject_page_fault(vcpu, &e);
6291 return 1;
6292 }
6293 }
6294
6295
6296 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6297 if (vmcs_field_readonly(field)) {
6298 nested_vmx_failValid(vcpu,
6299 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6300 skip_emulated_instruction(vcpu);
6301 return 1;
6302 }
6303
20b97fea 6304 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6305 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6306 skip_emulated_instruction(vcpu);
6307 return 1;
6308 }
6309
6310 nested_vmx_succeed(vcpu);
6311 skip_emulated_instruction(vcpu);
6312 return 1;
6313}
6314
63846663
NHE		 6315/* Emulate the VMPTRLD instruction */
6316static int handle_vmptrld(struct kvm_vcpu *vcpu)
6317{
6318 struct vcpu_vmx *vmx = to_vmx(vcpu);
6319 gva_t gva;
6320 gpa_t vmptr;
6321 struct x86_exception e;
8a1b9dd0 6322 u32 exec_control;
63846663
NHE		 6323
6324 if (!nested_vmx_check_permission(vcpu))
6325 return 1;
6326
6327 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6328 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6329 return 1;
6330
6331 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6332 sizeof(vmptr), &e)) {
6333 kvm_inject_page_fault(vcpu, &e);
6334 return 1;
6335 }
6336
6337 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6338 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6339 skip_emulated_instruction(vcpu);
6340 return 1;
6341 }
6342
6343 if (vmx->nested.current_vmptr != vmptr) {
6344 struct vmcs12 *new_vmcs12;
6345 struct page *page;
6346 page = nested_get_page(vcpu, vmptr);
6347 if (page == NULL) {
6348 nested_vmx_failInvalid(vcpu);
6349 skip_emulated_instruction(vcpu);
6350 return 1;
6351 }
6352 new_vmcs12 = kmap(page);
6353 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6354 kunmap(page);
6355 nested_release_page_clean(page);
6356 nested_vmx_failValid(vcpu,
6357 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6358 skip_emulated_instruction(vcpu);
6359 return 1;
6360 }
e7953d7f
AG		 6361 if (vmx->nested.current_vmptr != -1ull)
6362 nested_release_vmcs12(vmx);
63846663
NHE		 6363
6364 vmx->nested.current_vmptr = vmptr;
6365 vmx->nested.current_vmcs12 = new_vmcs12;
6366 vmx->nested.current_vmcs12_page = page;
012f83cb 6367 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6368 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6369 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6370 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6371 vmcs_write64(VMCS_LINK_POINTER,
6372 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6373 vmx->nested.sync_shadow_vmcs = true;
6374 }
63846663
NHE		 6375 }
6376
6377 nested_vmx_succeed(vcpu);
6378 skip_emulated_instruction(vcpu);
6379 return 1;
6380}
6381
6a4d7550
NHE		 6382/* Emulate the VMPTRST instruction */
6383static int handle_vmptrst(struct kvm_vcpu *vcpu)
6384{
6385 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6386 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6387 gva_t vmcs_gva;
6388 struct x86_exception e;
6389
6390 if (!nested_vmx_check_permission(vcpu))
6391 return 1;
6392
6393 if (get_vmx_mem_address(vcpu, exit_qualification,
6394 vmx_instruction_info, &vmcs_gva))
6395 return 1;
6396 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6397 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6398 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6399 sizeof(u64), &e)) {
6400 kvm_inject_page_fault(vcpu, &e);
6401 return 1;
6402 }
6403 nested_vmx_succeed(vcpu);
6404 skip_emulated_instruction(vcpu);
6405 return 1;
6406}
6407
bfd0a56b
NHE		 6408/* Emulate the INVEPT instruction */
6409static int handle_invept(struct kvm_vcpu *vcpu)
6410{
6411 u32 vmx_instruction_info, types;
6412 unsigned long type;
6413 gva_t gva;
6414 struct x86_exception e;
6415 struct {
6416 u64 eptp, gpa;
6417 } operand;
6418 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6419
6420 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6421 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6422 kvm_queue_exception(vcpu, UD_VECTOR);
6423 return 1;
6424 }
6425
6426 if (!nested_vmx_check_permission(vcpu))
6427 return 1;
6428
6429 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6430 kvm_queue_exception(vcpu, UD_VECTOR);
6431 return 1;
6432 }
6433
6434 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6435 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6436
6437 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6438
6439 if (!(types & (1UL << type))) {
6440 nested_vmx_failValid(vcpu,
6441 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6442 return 1;
6443 }
6444
6445 /* According to the Intel VMX instruction reference, the memory
6446 * operand is read even if it isn't needed (e.g., for type==global)
6447 */
6448 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6449 vmx_instruction_info, &gva))
6450 return 1;
6451 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6452 sizeof(operand), &e)) {
6453 kvm_inject_page_fault(vcpu, &e);
6454 return 1;
6455 }
6456
6457 switch (type) {
6458 case VMX_EPT_EXTENT_CONTEXT:
6459 if ((operand.eptp & eptp_mask) !=
6460 (nested_ept_get_cr3(vcpu) & eptp_mask))
6461 break;
6462 case VMX_EPT_EXTENT_GLOBAL:
6463 kvm_mmu_sync_roots(vcpu);
6464 kvm_mmu_flush_tlb(vcpu);
6465 nested_vmx_succeed(vcpu);
6466 break;
6467 default:
6468 BUG_ON(1);
6469 break;
6470 }
6471
6472 skip_emulated_instruction(vcpu);
6473 return 1;
6474}
6475
6aa8b732
AK		 6476/*
6477 * The exit handlers return 1 if the exit was handled fully and guest execution
6478 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6479 * to be done to userspace and return 0.
6480 */
772e0318 6481static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6482 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6483 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6484 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6485 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6486 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6487 [EXIT_REASON_CR_ACCESS] = handle_cr,
6488 [EXIT_REASON_DR_ACCESS] = handle_dr,
6489 [EXIT_REASON_CPUID] = handle_cpuid,
6490 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6491 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6492 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6493 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6494 [EXIT_REASON_INVD] = handle_invd,
a7052897 6495 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6496 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6497 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6498 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6499 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6500 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6501 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6502 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6503 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6504 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6505 [EXIT_REASON_VMOFF] = handle_vmoff,
6506 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6507 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6508 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6509 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6510 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6511 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6512 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6513 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6514 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6515 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6516 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6517 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6518 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6519 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6520 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6521};
6522
6523static const int kvm_vmx_max_exit_handlers =
50a3485c 6524 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6525
908a7bdd
JK		 6526static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6527 struct vmcs12 *vmcs12)
6528{
6529 unsigned long exit_qualification;
6530 gpa_t bitmap, last_bitmap;
6531 unsigned int port;
6532 int size;
6533 u8 b;
6534
908a7bdd 6535 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6536 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6537
6538 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6539
6540 port = exit_qualification >> 16;
6541 size = (exit_qualification & 7) + 1;
6542
6543 last_bitmap = (gpa_t)-1;
6544 b = -1;
6545
6546 while (size > 0) {
6547 if (port < 0x8000)
6548 bitmap = vmcs12->io_bitmap_a;
6549 else if (port < 0x10000)
6550 bitmap = vmcs12->io_bitmap_b;
6551 else
6552 return 1;
6553 bitmap += (port & 0x7fff) / 8;
6554
6555 if (last_bitmap != bitmap)
6556 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6557 return 1;
6558 if (b & (1 << (port & 7)))
6559 return 1;
6560
6561 port++;
6562 size--;
6563 last_bitmap = bitmap;
6564 }
6565
6566 return 0;
6567}
6568
644d711a
NHE		 6569/*
6570 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6571 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6572 * disinterest in the current event (read or write a specific MSR) by using an
6573 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6574 */
6575static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6576 struct vmcs12 *vmcs12, u32 exit_reason)
6577{
6578 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6579 gpa_t bitmap;
6580
cbd29cb6 6581 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6582 return 1;
6583
6584 /*
6585 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6586 * for the four combinations of read/write and low/high MSR numbers.
6587 * First we need to figure out which of the four to use:
6588 */
6589 bitmap = vmcs12->msr_bitmap;
6590 if (exit_reason == EXIT_REASON_MSR_WRITE)
6591 bitmap += 2048;
6592 if (msr_index >= 0xc0000000) {
6593 msr_index -= 0xc0000000;
6594 bitmap += 1024;
6595 }
6596
6597 /* Then read the msr_index'th bit from this bitmap: */
6598 if (msr_index < 1024*8) {
6599 unsigned char b;
bd31a7f5
JK		 6600 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6601 return 1;
644d711a
NHE		 6602 return 1 & (b >> (msr_index & 7));
6603 } else
6604 return 1; /* let L1 handle the wrong parameter */
6605}
6606
6607/*
6608 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6609 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6610 * intercept (via guest_host_mask etc.) the current event.
6611 */
6612static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6613 struct vmcs12 *vmcs12)
6614{
6615 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6616 int cr = exit_qualification & 15;
6617 int reg = (exit_qualification >> 8) & 15;
6618 unsigned long val = kvm_register_read(vcpu, reg);
6619
6620 switch ((exit_qualification >> 4) & 3) {
6621 case 0: /* mov to cr */
6622 switch (cr) {
6623 case 0:
6624 if (vmcs12->cr0_guest_host_mask &
6625 (val ^ vmcs12->cr0_read_shadow))
6626 return 1;
6627 break;
6628 case 3:
6629 if ((vmcs12->cr3_target_count >= 1 &&
6630 vmcs12->cr3_target_value0 == val) ||
6631 (vmcs12->cr3_target_count >= 2 &&
6632 vmcs12->cr3_target_value1 == val) ||
6633 (vmcs12->cr3_target_count >= 3 &&
6634 vmcs12->cr3_target_value2 == val) ||
6635 (vmcs12->cr3_target_count >= 4 &&
6636 vmcs12->cr3_target_value3 == val))
6637 return 0;
6638 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6639 return 1;
6640 break;
6641 case 4:
6642 if (vmcs12->cr4_guest_host_mask &
6643 (vmcs12->cr4_read_shadow ^ val))
6644 return 1;
6645 break;
6646 case 8:
6647 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6648 return 1;
6649 break;
6650 }
6651 break;
6652 case 2: /* clts */
6653 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6654 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6655 return 1;
6656 break;
6657 case 1: /* mov from cr */
6658 switch (cr) {
6659 case 3:
6660 if (vmcs12->cpu_based_vm_exec_control &
6661 CPU_BASED_CR3_STORE_EXITING)
6662 return 1;
6663 break;
6664 case 8:
6665 if (vmcs12->cpu_based_vm_exec_control &
6666 CPU_BASED_CR8_STORE_EXITING)
6667 return 1;
6668 break;
6669 }
6670 break;
6671 case 3: /* lmsw */
6672 /*
6673 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6674 * cr0. Other attempted changes are ignored, with no exit.
6675 */
6676 if (vmcs12->cr0_guest_host_mask & 0xe &
6677 (val ^ vmcs12->cr0_read_shadow))
6678 return 1;
6679 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6680 !(vmcs12->cr0_read_shadow & 0x1) &&
6681 (val & 0x1))
6682 return 1;
6683 break;
6684 }
6685 return 0;
6686}
6687
6688/*
6689 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6690 * should handle it ourselves in L0 (and then continue L2). Only call this
6691 * when in is_guest_mode (L2).
6692 */
6693static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6694{
644d711a
NHE		 6695 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6696 struct vcpu_vmx *vmx = to_vmx(vcpu);
6697 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6698 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6699
6700 if (vmx->nested.nested_run_pending)
6701 return 0;
6702
6703 if (unlikely(vmx->fail)) {
bd80158a
JK		 6704 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6705 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6706 return 1;
6707 }
6708
6709 switch (exit_reason) {
6710 case EXIT_REASON_EXCEPTION_NMI:
6711 if (!is_exception(intr_info))
6712 return 0;
6713 else if (is_page_fault(intr_info))
6714 return enable_ept;
e504c909
AB		 6715 else if (is_no_device(intr_info) &&
6716 !(nested_read_cr0(vmcs12) & X86_CR0_TS))
6717 return 0;
644d711a
NHE		 6718 return vmcs12->exception_bitmap &
6719 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6720 case EXIT_REASON_EXTERNAL_INTERRUPT:
6721 return 0;
6722 case EXIT_REASON_TRIPLE_FAULT:
6723 return 1;
6724 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6725 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6726 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6727 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6728 case EXIT_REASON_TASK_SWITCH:
6729 return 1;
6730 case EXIT_REASON_CPUID:
6731 return 1;
6732 case EXIT_REASON_HLT:
6733 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6734 case EXIT_REASON_INVD:
6735 return 1;
6736 case EXIT_REASON_INVLPG:
6737 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6738 case EXIT_REASON_RDPMC:
6739 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6740 case EXIT_REASON_RDTSC:
6741 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6742 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6743 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6744 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6745 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6746 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6747 case EXIT_REASON_INVEPT:
644d711a
NHE		 6748 /*
6749 * VMX instructions trap unconditionally. This allows L1 to
6750 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6751 */
6752 return 1;
6753 case EXIT_REASON_CR_ACCESS:
6754 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6755 case EXIT_REASON_DR_ACCESS:
6756 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6757 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6758 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6759 case EXIT_REASON_MSR_READ:
6760 case EXIT_REASON_MSR_WRITE:
6761 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6762 case EXIT_REASON_INVALID_STATE:
6763 return 1;
6764 case EXIT_REASON_MWAIT_INSTRUCTION:
6765 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6766 case EXIT_REASON_MONITOR_INSTRUCTION:
6767 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6768 case EXIT_REASON_PAUSE_INSTRUCTION:
6769 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6770 nested_cpu_has2(vmcs12,
6771 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6772 case EXIT_REASON_MCE_DURING_VMENTRY:
6773 return 0;
6774 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6775 return 1;
6776 case EXIT_REASON_APIC_ACCESS:
6777 return nested_cpu_has2(vmcs12,
6778 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6779 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6780 /*
6781 * L0 always deals with the EPT violation. If nested EPT is
6782 * used, and the nested mmu code discovers that the address is
6783 * missing in the guest EPT table (EPT12), the EPT violation
6784 * will be injected with nested_ept_inject_page_fault()
6785 */
6786 return 0;
644d711a 6787 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6788 /*
6789 * L2 never uses directly L1's EPT, but rather L0's own EPT
6790 * table (shadow on EPT) or a merged EPT table that L0 built
6791 * (EPT on EPT). So any problems with the structure of the
6792 * table is L0's fault.
6793 */
644d711a 6794 return 0;
0238ea91
JK		 6795 case EXIT_REASON_PREEMPTION_TIMER:
6796 return vmcs12->pin_based_vm_exec_control &
6797 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6798 case EXIT_REASON_WBINVD:
6799 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6800 case EXIT_REASON_XSETBV:
6801 return 1;
6802 default:
6803 return 1;
6804 }
6805}
6806
586f9607
AK		 6807static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6808{
6809 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6810 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6811}
6812
7854cbca
ACL		 6813static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6814{
6815 u64 delta_tsc_l1;
6816 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6817
6818 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6819 PIN_BASED_VMX_PREEMPTION_TIMER))
6820 return;
6821 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6822 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6823 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6824 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6825 - vcpu->arch.last_guest_tsc;
6826 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6827 if (preempt_val_l2 <= preempt_val_l1)
6828 preempt_val_l2 = 0;
6829 else
6830 preempt_val_l2 -= preempt_val_l1;
6831 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6832}
6833
6aa8b732
AK		 6834/*
6835 * The guest has exited. See if we can fix it or if we need userspace
6836 * assistance.
6837 */
851ba692 6838static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6839{
29bd8a78 6840 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6841 u32 exit_reason = vmx->exit_reason;
1155f76a 6842 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6843
80ced186 6844 /* If guest state is invalid, start emulating */
14168786 6845 if (vmx->emulation_required)
80ced186 6846 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6847
644d711a 6848 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6849 nested_vmx_vmexit(vcpu, exit_reason,
6850 vmcs_read32(VM_EXIT_INTR_INFO),
6851 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6852 return 1;
6853 }
6854
5120702e
MG		 6855 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6856 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6857 vcpu->run->fail_entry.hardware_entry_failure_reason
6858 = exit_reason;
6859 return 0;
6860 }
6861
29bd8a78 6862 if (unlikely(vmx->fail)) {
851ba692
AK		 6863 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6864 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6865 = vmcs_read32(VM_INSTRUCTION_ERROR);
6866 return 0;
6867 }
6aa8b732 6868
b9bf6882
XG		 6869 /*
6870 * Note:
6871 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6872 * delivery event since it indicates guest is accessing MMIO.
6873 * The vm-exit can be triggered again after return to guest that
6874 * will cause infinite loop.
6875 */
d77c26fc 6876 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6877 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6878 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6879 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6880 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6881 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6882 vcpu->run->internal.ndata = 2;
6883 vcpu->run->internal.data[0] = vectoring_info;
6884 vcpu->run->internal.data[1] = exit_reason;
6885 return 0;
6886 }
3b86cd99 6887
644d711a
NHE		 6888 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6889 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6890 get_vmcs12(vcpu))))) {
c4282df9 6891 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6892 vmx->soft_vnmi_blocked = 0;
3b86cd99 6893 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6894 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6895 /*
6896 * This CPU don't support us in finding the end of an
6897 * NMI-blocked window if the guest runs with IRQs
6898 * disabled. So we pull the trigger after 1 s of
6899 * futile waiting, but inform the user about this.
6900 */
6901 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6902 "state on VCPU %d after 1 s timeout\n",
6903 __func__, vcpu->vcpu_id);
6904 vmx->soft_vnmi_blocked = 0;
3b86cd99 6905 }
3b86cd99
JK		 6906 }
6907
6aa8b732
AK		 6908 if (exit_reason < kvm_vmx_max_exit_handlers
6909 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6910 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6911 else {
851ba692
AK		 6912 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6913 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6914 }
6915 return 0;
6916}
6917
95ba8273 6918static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6919{
95ba8273 6920 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6921 vmcs_write32(TPR_THRESHOLD, 0);
6922 return;
6923 }
6924
95ba8273 6925 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6926}
6927
8d14695f
YZ		 6928static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6929{
6930 u32 sec_exec_control;
6931
6932 /*
6933 * There is not point to enable virtualize x2apic without enable
6934 * apicv
6935 */
c7c9c56c
YZ		 6936 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6937 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6938 return;
6939
6940 if (!vm_need_tpr_shadow(vcpu->kvm))
6941 return;
6942
6943 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6944
6945 if (set) {
6946 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6947 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6948 } else {
6949 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6950 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6951 }
6952 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6953
6954 vmx_set_msr_bitmap(vcpu);
6955}
6956
c7c9c56c
YZ		 6957static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6958{
6959 u16 status;
6960 u8 old;
6961
6962 if (!vmx_vm_has_apicv(kvm))
6963 return;
6964
6965 if (isr == -1)
6966 isr = 0;
6967
6968 status = vmcs_read16(GUEST_INTR_STATUS);
6969 old = status >> 8;
6970 if (isr != old) {
6971 status &= 0xff;
6972 status |= isr << 8;
6973 vmcs_write16(GUEST_INTR_STATUS, status);
6974 }
6975}
6976
6977static void vmx_set_rvi(int vector)
6978{
6979 u16 status;
6980 u8 old;
6981
6982 status = vmcs_read16(GUEST_INTR_STATUS);
6983 old = (u8)status & 0xff;
6984 if ((u8)vector != old) {
6985 status &= ~0xff;
6986 status |= (u8)vector;
6987 vmcs_write16(GUEST_INTR_STATUS, status);
6988 }
6989}
6990
6991static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6992{
6993 if (max_irr == -1)
6994 return;
6995
6996 vmx_set_rvi(max_irr);
6997}
6998
6999static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7000{
3d81bc7e
YZ		 7001 if (!vmx_vm_has_apicv(vcpu->kvm))
7002 return;
7003
c7c9c56c
YZ		 7004 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7005 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7006 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7007 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7008}
7009
51aa01d1 7010static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7011{
00eba012
AK		 7012 u32 exit_intr_info;
7013
7014 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7015 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7016 return;
7017
c5ca8e57 7018 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7019 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7020
7021 /* Handle machine checks before interrupts are enabled */
00eba012 7022 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7023 kvm_machine_check();
7024
20f65983 7025 /* We need to handle NMIs before interrupts are enabled */
00eba012 7026 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7027 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7028 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7029 asm("int $2");
ff9d07a0
ZY		 7030 kvm_after_handle_nmi(&vmx->vcpu);
7031 }
51aa01d1 7032}
20f65983 7033
a547c6db
YZ		 7034static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7035{
7036 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7037
7038 /*
7039 * If external interrupt exists, IF bit is set in rflags/eflags on the
7040 * interrupt stack frame, and interrupt will be enabled on a return
7041 * from interrupt handler.
7042 */
7043 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7044 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7045 unsigned int vector;
7046 unsigned long entry;
7047 gate_desc *desc;
7048 struct vcpu_vmx *vmx = to_vmx(vcpu);
7049#ifdef CONFIG_X86_64
7050 unsigned long tmp;
7051#endif
7052
7053 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7054 desc = (gate_desc *)vmx->host_idt_base + vector;
7055 entry = gate_offset(*desc);
7056 asm volatile(
7057#ifdef CONFIG_X86_64
7058 "mov %%" _ASM_SP ", %[sp]\n\t"
7059 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7060 "push $%c[ss]\n\t"
7061 "push %[sp]\n\t"
7062#endif
7063 "pushf\n\t"
7064 "orl $0x200, (%%" _ASM_SP ")\n\t"
7065 __ASM_SIZE(push) " $%c[cs]\n\t"
7066 "call *%[entry]\n\t"
7067 :
7068#ifdef CONFIG_X86_64
7069 [sp]"=&r"(tmp)
7070#endif
7071 :
7072 [entry]"r"(entry),
7073 [ss]"i"(__KERNEL_DS),
7074 [cs]"i"(__KERNEL_CS)
7075 );
7076 } else
7077 local_irq_enable();
7078}
7079
51aa01d1
AK		 7080static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7081{
c5ca8e57 7082 u32 exit_intr_info;
51aa01d1
AK		 7083 bool unblock_nmi;
7084 u8 vector;
7085 bool idtv_info_valid;
7086
7087 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7088
cf393f75 7089 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7090 if (vmx->nmi_known_unmasked)
7091 return;
c5ca8e57
AK		 7092 /*
7093 * Can't use vmx->exit_intr_info since we're not sure what
7094 * the exit reason is.
7095 */
7096 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7097 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7098 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7099 /*
7b4a25cb 7100 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7101 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7102 * a guest IRET fault.
7b4a25cb
GN		 7103 * SDM 3: 23.2.2 (September 2008)
7104 * Bit 12 is undefined in any of the following cases:
7105 * If the VM exit sets the valid bit in the IDT-vectoring
7106 * information field.
7107 * If the VM exit is due to a double fault.
cf393f75 7108 */
7b4a25cb
GN		 7109 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7110 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7111 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7112 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7113 else
7114 vmx->nmi_known_unmasked =
7115 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7116 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7117 } else if (unlikely(vmx->soft_vnmi_blocked))
7118 vmx->vnmi_blocked_time +=
7119 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7120}
7121
3ab66e8a 7122static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7123 u32 idt_vectoring_info,
7124 int instr_len_field,
7125 int error_code_field)
51aa01d1 7126{
51aa01d1
AK		 7127 u8 vector;
7128 int type;
7129 bool idtv_info_valid;
7130
7131 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7132
3ab66e8a
JK		 7133 vcpu->arch.nmi_injected = false;
7134 kvm_clear_exception_queue(vcpu);
7135 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7136
7137 if (!idtv_info_valid)
7138 return;
7139
3ab66e8a 7140 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7141
668f612f
AK		 7142 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7143 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7144
64a7ec06 7145 switch (type) {
37b96e98 7146 case INTR_TYPE_NMI_INTR:
3ab66e8a 7147 vcpu->arch.nmi_injected = true;
668f612f 7148 /*
7b4a25cb 7149 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7150 * Clear bit "block by NMI" before VM entry if a NMI
7151 * delivery faulted.
668f612f 7152 */
3ab66e8a 7153 vmx_set_nmi_mask(vcpu, false);
37b96e98 7154 break;
37b96e98 7155 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7156 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7157 /* fall through */
7158 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7159 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7160 u32 err = vmcs_read32(error_code_field);
851eb667 7161 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7162 } else
851eb667 7163 kvm_requeue_exception(vcpu, vector);
37b96e98 7164 break;
66fd3f7f 7165 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7166 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7167 /* fall through */
37b96e98 7168 case INTR_TYPE_EXT_INTR:
3ab66e8a 7169 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7170 break;
7171 default:
7172 break;
f7d9238f 7173 }
cf393f75
AK		 7174}
7175
83422e17
AK		 7176static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7177{
3ab66e8a 7178 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7179 VM_EXIT_INSTRUCTION_LEN,
7180 IDT_VECTORING_ERROR_CODE);
7181}
7182
b463a6f7
AK		 7183static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7184{
3ab66e8a 7185 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7186 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7187 VM_ENTRY_INSTRUCTION_LEN,
7188 VM_ENTRY_EXCEPTION_ERROR_CODE);
7189
7190 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7191}
7192
d7cd9796
GN		 7193static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7194{
7195 int i, nr_msrs;
7196 struct perf_guest_switch_msr *msrs;
7197
7198 msrs = perf_guest_get_msrs(&nr_msrs);
7199
7200 if (!msrs)
7201 return;
7202
7203 for (i = 0; i < nr_msrs; i++)
7204 if (msrs[i].host == msrs[i].guest)
7205 clear_atomic_switch_msr(vmx, msrs[i].msr);
7206 else
7207 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7208 msrs[i].host);
7209}
7210
a3b5ba49 7211static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7212{
a2fa3e9f 7213 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7214 unsigned long debugctlmsr;
104f226b
AK		 7215
7216 /* Record the guest's net vcpu time for enforced NMI injections. */
7217 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7218 vmx->entry_time = ktime_get();
7219
7220 /* Don't enter VMX if guest state is invalid, let the exit handler
7221 start emulation until we arrive back to a valid state */
14168786 7222 if (vmx->emulation_required)
104f226b
AK		 7223 return;
7224
012f83cb
AG		 7225 if (vmx->nested.sync_shadow_vmcs) {
7226 copy_vmcs12_to_shadow(vmx);
7227 vmx->nested.sync_shadow_vmcs = false;
7228 }
7229
104f226b
AK		 7230 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7231 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7232 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7233 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7234
7235 /* When single-stepping over STI and MOV SS, we must clear the
7236 * corresponding interruptibility bits in the guest state. Otherwise
7237 * vmentry fails as it then expects bit 14 (BS) in pending debug
7238 * exceptions being set, but that's not correct for the guest debugging
7239 * case. */
7240 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7241 vmx_set_interrupt_shadow(vcpu, 0);
7242
d7cd9796 7243 atomic_switch_perf_msrs(vmx);
2a7921b7 7244 debugctlmsr = get_debugctlmsr();
d7cd9796 7245
7854cbca
ACL		 7246 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7247 nested_adjust_preemption_timer(vcpu);
d462b819 7248 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7249 asm(
6aa8b732 7250 /* Store host registers */
b188c81f
AK		 7251 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7252 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7253 "push %%" _ASM_CX " \n\t"
7254 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7255 "je 1f \n\t"
b188c81f 7256 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7257 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7258 "1: \n\t"
d3edefc0 7259 /* Reload cr2 if changed */
b188c81f
AK		 7260 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7261 "mov %%cr2, %%" _ASM_DX " \n\t"
7262 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7263 "je 2f \n\t"
b188c81f 7264 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7265 "2: \n\t"
6aa8b732 7266 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7267 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7268 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7269 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7270 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7271 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7272 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7273 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7274 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7275#ifdef CONFIG_X86_64
e08aa78a
AK		 7276 "mov %c[r8](%0), %%r8 \n\t"
7277 "mov %c[r9](%0), %%r9 \n\t"
7278 "mov %c[r10](%0), %%r10 \n\t"
7279 "mov %c[r11](%0), %%r11 \n\t"
7280 "mov %c[r12](%0), %%r12 \n\t"
7281 "mov %c[r13](%0), %%r13 \n\t"
7282 "mov %c[r14](%0), %%r14 \n\t"
7283 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7284#endif
b188c81f 7285 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7286
6aa8b732 7287 /* Enter guest mode */
83287ea4 7288 "jne 1f \n\t"
4ecac3fd 7289 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7290 "jmp 2f \n\t"
7291 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7292 "2: "
6aa8b732 7293 /* Save guest registers, load host registers, keep flags */
b188c81f 7294 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7295 "pop %0 \n\t"
b188c81f
AK		 7296 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7297 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7298 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7299 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7300 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7301 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7302 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7303#ifdef CONFIG_X86_64
e08aa78a
AK		 7304 "mov %%r8, %c[r8](%0) \n\t"
7305 "mov %%r9, %c[r9](%0) \n\t"
7306 "mov %%r10, %c[r10](%0) \n\t"
7307 "mov %%r11, %c[r11](%0) \n\t"
7308 "mov %%r12, %c[r12](%0) \n\t"
7309 "mov %%r13, %c[r13](%0) \n\t"
7310 "mov %%r14, %c[r14](%0) \n\t"
7311 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7312#endif
b188c81f
AK		 7313 "mov %%cr2, %%" _ASM_AX " \n\t"
7314 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7315
b188c81f 7316 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7317 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7318 ".pushsection .rodata \n\t"
7319 ".global vmx_return \n\t"
7320 "vmx_return: " _ASM_PTR " 2b \n\t"
7321 ".popsection"
e08aa78a 7322 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7323 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7324 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7325 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7326 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7327 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7328 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7329 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7330 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7331 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7332 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7333#ifdef CONFIG_X86_64
ad312c7c
ZX		 7334 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7335 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7336 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7337 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7338 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7339 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7340 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7341 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7342#endif
40712fae
AK		 7343 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7344 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7345 : "cc", "memory"
7346#ifdef CONFIG_X86_64
b188c81f 7347 , "rax", "rbx", "rdi", "rsi"
c2036300 7348 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7349#else
7350 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7351#endif
7352 );
6aa8b732 7353
2a7921b7
GN		 7354 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7355 if (debugctlmsr)
7356 update_debugctlmsr(debugctlmsr);
7357
aa67f609
AK		 7358#ifndef CONFIG_X86_64
7359 /*
7360 * The sysexit path does not restore ds/es, so we must set them to
7361 * a reasonable value ourselves.
7362 *
7363 * We can't defer this to vmx_load_host_state() since that function
7364 * may be executed in interrupt context, which saves and restore segments
7365 * around it, nullifying its effect.
7366 */
7367 loadsegment(ds, __USER_DS);
7368 loadsegment(es, __USER_DS);
7369#endif
7370
6de4f3ad 7371 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7372 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7373 | (1 << VCPU_EXREG_CPL)
aff48baa 7374 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7375 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7376 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7377 vcpu->arch.regs_dirty = 0;
7378
1155f76a
AK		 7379 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7380
d462b819 7381 vmx->loaded_vmcs->launched = 1;
1b6269db 7382
51aa01d1 7383 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7384 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7385
e0b890d3
GN		 7386 /*
7387 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7388 * we did not inject a still-pending event to L1 now because of
7389 * nested_run_pending, we need to re-enable this bit.
7390 */
7391 if (vmx->nested.nested_run_pending)
7392 kvm_make_request(KVM_REQ_EVENT, vcpu);
7393
7394 vmx->nested.nested_run_pending = 0;
7395
51aa01d1
AK		 7396 vmx_complete_atomic_exit(vmx);
7397 vmx_recover_nmi_blocking(vmx);
cf393f75 7398 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7399}
7400
6aa8b732
AK		 7401static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7402{
fb3f0f51
RR		 7403 struct vcpu_vmx *vmx = to_vmx(vcpu);
7404
cdbecfc3 7405 free_vpid(vmx);
d462b819 7406 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7407 free_nested(vmx);
fb3f0f51
RR		 7408 kfree(vmx->guest_msrs);
7409 kvm_vcpu_uninit(vcpu);
a4770347 7410 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7411}
7412
fb3f0f51 7413static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7414{
fb3f0f51 7415 int err;
c16f862d 7416 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7417 int cpu;
6aa8b732 7418
a2fa3e9f 7419 if (!vmx)
fb3f0f51
RR		 7420 return ERR_PTR(-ENOMEM);
7421
2384d2b3
SY		 7422 allocate_vpid(vmx);
7423
fb3f0f51
RR		 7424 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7425 if (err)
7426 goto free_vcpu;
965b58a5 7427
a2fa3e9f 7428 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7429 err = -ENOMEM;
fb3f0f51 7430 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7431 goto uninit_vcpu;
7432 }
965b58a5 7433
d462b819
NHE		 7434 vmx->loaded_vmcs = &vmx->vmcs01;
7435 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7436 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7437 goto free_msrs;
d462b819
NHE		 7438 if (!vmm_exclusive)
7439 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7440 loaded_vmcs_init(vmx->loaded_vmcs);
7441 if (!vmm_exclusive)
7442 kvm_cpu_vmxoff();
a2fa3e9f 7443
15ad7146
AK		 7444 cpu = get_cpu();
7445 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7446 vmx->vcpu.cpu = cpu;
8b9cf98c 7447 err = vmx_vcpu_setup(vmx);
fb3f0f51 7448 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7449 put_cpu();
fb3f0f51
RR		 7450 if (err)
7451 goto free_vmcs;
a63cb560 7452 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7453 err = alloc_apic_access_page(kvm);
7454 if (err)
5e4a0b3c 7455 goto free_vmcs;
a63cb560 7456 }
fb3f0f51 7457
b927a3ce
SY		 7458 if (enable_ept) {
7459 if (!kvm->arch.ept_identity_map_addr)
7460 kvm->arch.ept_identity_map_addr =
7461 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7462 err = -ENOMEM;
b7ebfb05
SY		 7463 if (alloc_identity_pagetable(kvm) != 0)
7464 goto free_vmcs;
93ea5388
GN		 7465 if (!init_rmode_identity_map(kvm))
7466 goto free_vmcs;
b927a3ce 7467 }
b7ebfb05 7468
a9d30f33
NHE		 7469 vmx->nested.current_vmptr = -1ull;
7470 vmx->nested.current_vmcs12 = NULL;
7471
fb3f0f51
RR		 7472 return &vmx->vcpu;
7473
7474free_vmcs:
5f3fbc34 7475 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7476free_msrs:
fb3f0f51
RR		 7477 kfree(vmx->guest_msrs);
7478uninit_vcpu:
7479 kvm_vcpu_uninit(&vmx->vcpu);
7480free_vcpu:
cdbecfc3 7481 free_vpid(vmx);
a4770347 7482 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7483 return ERR_PTR(err);
6aa8b732
AK		 7484}
7485
002c7f7c
YS		 7486static void __init vmx_check_processor_compat(void *rtn)
7487{
7488 struct vmcs_config vmcs_conf;
7489
7490 *(int *)rtn = 0;
7491 if (setup_vmcs_config(&vmcs_conf) < 0)
7492 *(int *)rtn = -EIO;
7493 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7494 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7495 smp_processor_id());
7496 *(int *)rtn = -EIO;
7497 }
7498}
7499
67253af5
SY		 7500static int get_ept_level(void)
7501{
7502 return VMX_EPT_DEFAULT_GAW + 1;
7503}
7504
4b12f0de 7505static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7506{
4b12f0de
SY		 7507 u64 ret;
7508
522c68c4
SY		 7509 /* For VT-d and EPT combination
7510 * 1. MMIO: always map as UC
7511 * 2. EPT with VT-d:
7512 * a. VT-d without snooping control feature: can't guarantee the
7513 * result, try to trust guest.
7514 * b. VT-d with snooping control feature: snooping control feature of
7515 * VT-d engine can guarantee the cache correctness. Just set it
7516 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7517 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7518 * consistent with host MTRR
7519 */
4b12f0de
SY		 7520 if (is_mmio)
7521 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7522 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7523 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7524 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7525 else
522c68c4 7526 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7527 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7528
7529 return ret;
64d4d521
SY		 7530}
7531
17cc3935 7532static int vmx_get_lpage_level(void)
344f414f 7533{
878403b7
SY		 7534 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7535 return PT_DIRECTORY_LEVEL;
7536 else
7537 /* For shadow and EPT supported 1GB page */
7538 return PT_PDPE_LEVEL;
344f414f
JR		 7539}
7540
0e851880
SY		 7541static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7542{
4e47c7a6
SY		 7543 struct kvm_cpuid_entry2 *best;
7544 struct vcpu_vmx *vmx = to_vmx(vcpu);
7545 u32 exec_control;
7546
7547 vmx->rdtscp_enabled = false;
7548 if (vmx_rdtscp_supported()) {
7549 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7550 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7551 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7552 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7553 vmx->rdtscp_enabled = true;
7554 else {
7555 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7556 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7557 exec_control);
7558 }
7559 }
7560 }
ad756a16 7561
ad756a16
MJ		 7562 /* Exposing INVPCID only when PCID is exposed */
7563 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7564 if (vmx_invpcid_supported() &&
4f977045 7565 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7566 guest_cpuid_has_pcid(vcpu)) {
29282fde 7567 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7568 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7569 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7570 exec_control);
7571 } else {
29282fde
TI		 7572 if (cpu_has_secondary_exec_ctrls()) {
7573 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7574 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7575 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7576 exec_control);
7577 }
ad756a16 7578 if (best)
4f977045 7579 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7580 }
0e851880
SY		 7581}
7582
d4330ef2
JR		 7583static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7584{
7b8050f5
NHE		 7585 if (func == 1 && nested)
7586 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7587}
7588
25d92081
YZ		 7589static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7590 struct x86_exception *fault)
7591{
533558bc
JK		 7592 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7593 u32 exit_reason;
25d92081
YZ		 7594
7595 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7596 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7597 else
533558bc
JK		 7598 exit_reason = EXIT_REASON_EPT_VIOLATION;
7599 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7600 vmcs12->guest_physical_address = fault->address;
7601}
7602
155a97a3
NHE		 7603/* Callbacks for nested_ept_init_mmu_context: */
7604
7605static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7606{
7607 /* return the page table to be shadowed - in our case, EPT12 */
7608 return get_vmcs12(vcpu)->ept_pointer;
7609}
7610
8a3c1a33 7611static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7612{
8a3c1a33 7613 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7614 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7615
7616 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7617 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7618 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7619
7620 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7621}
7622
7623static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7624{
7625 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7626}
7627
feaf0c7d
GN		 7628static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7629 struct x86_exception *fault)
7630{
7631 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7632
7633 WARN_ON(!is_guest_mode(vcpu));
7634
7635 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7636 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7637 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7638 vmcs_read32(VM_EXIT_INTR_INFO),
7639 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7640 else
7641 kvm_inject_page_fault(vcpu, fault);
7642}
7643
fe3ef05c
NHE		 7644/*
7645 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7646 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7647 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7648 * guest in a way that will both be appropriate to L1's requests, and our
7649 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7650 * function also has additional necessary side-effects, like setting various
7651 * vcpu->arch fields.
7652 */
7653static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7654{
7655 struct vcpu_vmx *vmx = to_vmx(vcpu);
7656 u32 exec_control;
7854cbca 7657 u32 exit_control;
fe3ef05c
NHE		 7658
7659 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7660 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7661 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7662 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7663 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7664 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7665 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7666 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7667 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7668 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7669 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7670 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7671 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7672 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7673 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7674 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7675 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7676 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7677 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7678 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7679 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7680 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7681 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7682 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7683 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7684 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7685 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7686 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7687 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7688 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7689 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7690 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7691 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7692 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7693 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7694 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7695
7696 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7697 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7698 vmcs12->vm_entry_intr_info_field);
7699 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7700 vmcs12->vm_entry_exception_error_code);
7701 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7702 vmcs12->vm_entry_instruction_len);
7703 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7704 vmcs12->guest_interruptibility_info);
fe3ef05c 7705 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7706 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7707 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7708 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7709 vmcs12->guest_pending_dbg_exceptions);
7710 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7711 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7712
7713 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7714
7715 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7716 (vmcs_config.pin_based_exec_ctrl |
7717 vmcs12->pin_based_vm_exec_control));
7718
0238ea91
JK		 7719 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7720 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7721 vmcs12->vmx_preemption_timer_value);
7722
fe3ef05c
NHE		 7723 /*
7724 * Whether page-faults are trapped is determined by a combination of
7725 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7726 * If enable_ept, L0 doesn't care about page faults and we should
7727 * set all of these to L1's desires. However, if !enable_ept, L0 does
7728 * care about (at least some) page faults, and because it is not easy
7729 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7730 * to exit on each and every L2 page fault. This is done by setting
7731 * MASK=MATCH=0 and (see below) EB.PF=1.
7732 * Note that below we don't need special code to set EB.PF beyond the
7733 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7734 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7735 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7736 *
7737 * A problem with this approach (when !enable_ept) is that L1 may be
7738 * injected with more page faults than it asked for. This could have
7739 * caused problems, but in practice existing hypervisors don't care.
7740 * To fix this, we will need to emulate the PFEC checking (on the L1
7741 * page tables), using walk_addr(), when injecting PFs to L1.
7742 */
7743 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7744 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7745 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7746 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7747
7748 if (cpu_has_secondary_exec_ctrls()) {
7749 u32 exec_control = vmx_secondary_exec_control(vmx);
7750 if (!vmx->rdtscp_enabled)
7751 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7752 /* Take the following fields only from vmcs12 */
7753 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7754 if (nested_cpu_has(vmcs12,
7755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7756 exec_control |= vmcs12->secondary_vm_exec_control;
7757
7758 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7759 /*
7760 * Translate L1 physical address to host physical
7761 * address for vmcs02. Keep the page pinned, so this
7762 * physical address remains valid. We keep a reference
7763 * to it so we can release it later.
7764 */
7765 if (vmx->nested.apic_access_page) /* shouldn't happen */
7766 nested_release_page(vmx->nested.apic_access_page);
7767 vmx->nested.apic_access_page =
7768 nested_get_page(vcpu, vmcs12->apic_access_addr);
7769 /*
7770 * If translation failed, no matter: This feature asks
7771 * to exit when accessing the given address, and if it
7772 * can never be accessed, this feature won't do
7773 * anything anyway.
7774 */
7775 if (!vmx->nested.apic_access_page)
7776 exec_control &=
7777 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7778 else
7779 vmcs_write64(APIC_ACCESS_ADDR,
7780 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7781 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7782 exec_control |=
7783 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7784 vmcs_write64(APIC_ACCESS_ADDR,
7785 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7786 }
7787
7788 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7789 }
7790
7791
7792 /*
7793 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7794 * Some constant fields are set here by vmx_set_constant_host_state().
7795 * Other fields are different per CPU, and will be set later when
7796 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7797 */
a547c6db 7798 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7799
7800 /*
7801 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7802 * entry, but only if the current (host) sp changed from the value
7803 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7804 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7805 * here we just force the write to happen on entry.
7806 */
7807 vmx->host_rsp = 0;
7808
7809 exec_control = vmx_exec_control(vmx); /* L0's desires */
7810 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7811 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7812 exec_control &= ~CPU_BASED_TPR_SHADOW;
7813 exec_control |= vmcs12->cpu_based_vm_exec_control;
7814 /*
7815 * Merging of IO and MSR bitmaps not currently supported.
7816 * Rather, exit every time.
7817 */
7818 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7819 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7820 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7821
7822 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7823
7824 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7825 * bitwise-or of what L1 wants to trap for L2, and what we want to
7826 * trap. Note that CR0.TS also needs updating - we do this later.
7827 */
7828 update_exception_bitmap(vcpu);
7829 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7830 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7831
8049d651
NHE		 7832 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7833 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7834 * bits are further modified by vmx_set_efer() below.
7835 */
7854cbca
ACL		 7836 exit_control = vmcs_config.vmexit_ctrl;
7837 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7838 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2961e876 7839 vm_exit_controls_init(vmx, exit_control);
8049d651
NHE		 7840
7841 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7842 * emulated by vmx_set_efer(), below.
7843 */
2961e876 7844 vm_entry_controls_init(vmx,
8049d651
NHE		 7845 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7846 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7847 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7848
44811c02 7849 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7850 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7851 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7852 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7853 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7854
7855
7856 set_cr4_guest_host_mask(vmx);
7857
27fc51b2
NHE		 7858 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7859 vmcs_write64(TSC_OFFSET,
7860 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7861 else
7862 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7863
7864 if (enable_vpid) {
7865 /*
7866 * Trivially support vpid by letting L2s share their parent
7867 * L1's vpid. TODO: move to a more elaborate solution, giving
7868 * each L2 its own vpid and exposing the vpid feature to L1.
7869 */
7870 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7871 vmx_flush_tlb(vcpu);
7872 }
7873
155a97a3
NHE		 7874 if (nested_cpu_has_ept(vmcs12)) {
7875 kvm_mmu_unload(vcpu);
7876 nested_ept_init_mmu_context(vcpu);
7877 }
7878
fe3ef05c
NHE		 7879 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7880 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7881 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7882 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7883 else
7884 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7885 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7886 vmx_set_efer(vcpu, vcpu->arch.efer);
7887
7888 /*
7889 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7890 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7891 * The CR0_READ_SHADOW is what L2 should have expected to read given
7892 * the specifications by L1; It's not enough to take
7893 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7894 * have more bits than L1 expected.
7895 */
7896 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7897 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7898
7899 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7900 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7901
7902 /* shadow page tables on either EPT or shadow page tables */
7903 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7904 kvm_mmu_reset_context(vcpu);
7905
feaf0c7d
GN		 7906 if (!enable_ept)
7907 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7908
3633cfc3
NHE		 7909 /*
7910 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7911 */
7912 if (enable_ept) {
7913 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7914 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7915 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7916 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7917 }
7918
fe3ef05c
NHE		 7919 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7920 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7921}
7922
cd232ad0
NHE		 7923/*
7924 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7925 * for running an L2 nested guest.
7926 */
7927static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7928{
7929 struct vmcs12 *vmcs12;
7930 struct vcpu_vmx *vmx = to_vmx(vcpu);
7931 int cpu;
7932 struct loaded_vmcs *vmcs02;
384bb783 7933 bool ia32e;
cd232ad0
NHE		 7934
7935 if (!nested_vmx_check_permission(vcpu) ||
7936 !nested_vmx_check_vmcs12(vcpu))
7937 return 1;
7938
7939 skip_emulated_instruction(vcpu);
7940 vmcs12 = get_vmcs12(vcpu);
7941
012f83cb
AG		 7942 if (enable_shadow_vmcs)
7943 copy_shadow_to_vmcs12(vmx);
7944
7c177938
NHE		 7945 /*
7946 * The nested entry process starts with enforcing various prerequisites
7947 * on vmcs12 as required by the Intel SDM, and act appropriately when
7948 * they fail: As the SDM explains, some conditions should cause the
7949 * instruction to fail, while others will cause the instruction to seem
7950 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7951 * To speed up the normal (success) code path, we should avoid checking
7952 * for misconfigurations which will anyway be caught by the processor
7953 * when using the merged vmcs02.
7954 */
7955 if (vmcs12->launch_state == launch) {
7956 nested_vmx_failValid(vcpu,
7957 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7958 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7959 return 1;
7960 }
7961
6dfacadd
JK		 7962 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7963 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7964 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7965 return 1;
7966 }
7967
7c177938
NHE		 7968 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7969 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7970 /*TODO: Also verify bits beyond physical address width are 0*/
7971 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7972 return 1;
7973 }
7974
7975 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7976 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7977 /*TODO: Also verify bits beyond physical address width are 0*/
7978 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7979 return 1;
7980 }
7981
7982 if (vmcs12->vm_entry_msr_load_count > 0 ||
7983 vmcs12->vm_exit_msr_load_count > 0 ||
7984 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7985 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7986 __func__);
7c177938
NHE		 7987 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7988 return 1;
7989 }
7990
7991 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7992 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7993 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7994 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7995 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7996 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7997 !vmx_control_verify(vmcs12->vm_exit_controls,
7998 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7999 !vmx_control_verify(vmcs12->vm_entry_controls,
8000 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8001 {
8002 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8003 return 1;
8004 }
8005
8006 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8007 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8008 nested_vmx_failValid(vcpu,
8009 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8010 return 1;
8011 }
8012
92fbc7b1 8013 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8014 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8015 nested_vmx_entry_failure(vcpu, vmcs12,
8016 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8017 return 1;
8018 }
8019 if (vmcs12->vmcs_link_pointer != -1ull) {
8020 nested_vmx_entry_failure(vcpu, vmcs12,
8021 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8022 return 1;
8023 }
8024
384bb783 8025 /*
cb0c8cda 8026 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8027 * are performed on the field for the IA32_EFER MSR:
8028 * - Bits reserved in the IA32_EFER MSR must be 0.
8029 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8030 * the IA-32e mode guest VM-exit control. It must also be identical
8031 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8032 * CR0.PG) is 1.
8033 */
8034 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8035 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8036 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8037 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8038 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8039 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8040 nested_vmx_entry_failure(vcpu, vmcs12,
8041 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8042 return 1;
8043 }
8044 }
8045
8046 /*
8047 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8048 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8049 * the values of the LMA and LME bits in the field must each be that of
8050 * the host address-space size VM-exit control.
8051 */
8052 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8053 ia32e = (vmcs12->vm_exit_controls &
8054 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8055 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8056 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8057 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8058 nested_vmx_entry_failure(vcpu, vmcs12,
8059 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8060 return 1;
8061 }
8062 }
8063
7c177938
NHE		 8064 /*
8065 * We're finally done with prerequisite checking, and can start with
8066 * the nested entry.
8067 */
8068
cd232ad0
NHE		 8069 vmcs02 = nested_get_current_vmcs02(vmx);
8070 if (!vmcs02)
8071 return -ENOMEM;
8072
8073 enter_guest_mode(vcpu);
8074
e0b890d3
GN		 8075 vmx->nested.nested_run_pending = 1;
8076
cd232ad0
NHE		 8077 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8078
8079 cpu = get_cpu();
8080 vmx->loaded_vmcs = vmcs02;
8081 vmx_vcpu_put(vcpu);
8082 vmx_vcpu_load(vcpu, cpu);
8083 vcpu->cpu = cpu;
8084 put_cpu();
8085
36c3cc42
JK		 8086 vmx_segment_cache_clear(vmx);
8087
cd232ad0
NHE		 8088 vmcs12->launch_state = 1;
8089
8090 prepare_vmcs02(vcpu, vmcs12);
8091
6dfacadd
JK		 8092 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8093 return kvm_emulate_halt(vcpu);
8094
cd232ad0
NHE		 8095 /*
8096 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8097 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8098 * returned as far as L1 is concerned. It will only return (and set
8099 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8100 */
8101 return 1;
8102}
8103
4704d0be
NHE		 8104/*
8105 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8106 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8107 * This function returns the new value we should put in vmcs12.guest_cr0.
8108 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8109 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8110 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8111 * didn't trap the bit, because if L1 did, so would L0).
8112 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8113 * been modified by L2, and L1 knows it. So just leave the old value of
8114 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8115 * isn't relevant, because if L0 traps this bit it can set it to anything.
8116 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8117 * changed these bits, and therefore they need to be updated, but L0
8118 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8119 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8120 */
8121static inline unsigned long
8122vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8123{
8124 return
8125 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8126 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8127 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8128 vcpu->arch.cr0_guest_owned_bits));
8129}
8130
8131static inline unsigned long
8132vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8133{
8134 return
8135 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8136 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8137 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8138 vcpu->arch.cr4_guest_owned_bits));
8139}
8140
5f3d5799
JK		 8141static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8142 struct vmcs12 *vmcs12)
8143{
8144 u32 idt_vectoring;
8145 unsigned int nr;
8146
851eb667 8147 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8148 nr = vcpu->arch.exception.nr;
8149 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8150
8151 if (kvm_exception_is_soft(nr)) {
8152 vmcs12->vm_exit_instruction_len =
8153 vcpu->arch.event_exit_inst_len;
8154 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8155 } else
8156 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8157
8158 if (vcpu->arch.exception.has_error_code) {
8159 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8160 vmcs12->idt_vectoring_error_code =
8161 vcpu->arch.exception.error_code;
8162 }
8163
8164 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8165 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8166 vmcs12->idt_vectoring_info_field =
8167 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8168 } else if (vcpu->arch.interrupt.pending) {
8169 nr = vcpu->arch.interrupt.nr;
8170 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8171
8172 if (vcpu->arch.interrupt.soft) {
8173 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8174 vmcs12->vm_entry_instruction_len =
8175 vcpu->arch.event_exit_inst_len;
8176 } else
8177 idt_vectoring |= INTR_TYPE_EXT_INTR;
8178
8179 vmcs12->idt_vectoring_info_field = idt_vectoring;
8180 }
8181}
8182
4704d0be
NHE		 8183/*
8184 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8185 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8186 * and this function updates it to reflect the changes to the guest state while
8187 * L2 was running (and perhaps made some exits which were handled directly by L0
8188 * without going back to L1), and to reflect the exit reason.
8189 * Note that we do not have to copy here all VMCS fields, just those that
8190 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8191 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8192 * which already writes to vmcs12 directly.
8193 */
533558bc
JK		 8194static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8195 u32 exit_reason, u32 exit_intr_info,
8196 unsigned long exit_qualification)
4704d0be
NHE		 8197{
8198 /* update guest state fields: */
8199 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8200 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8201
8202 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8203 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8204 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8205 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8206
8207 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8208 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8209 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8210 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8211 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8212 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8213 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8214 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8215 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8216 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8217 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8218 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8219 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8220 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8221 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8222 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8223 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8224 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8225 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8226 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8227 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8228 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8229 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8230 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8231 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8232 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8233 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8234 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8235 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8236 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8237 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8238 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8239 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8240 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8241 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8242 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8243
4704d0be
NHE		 8244 vmcs12->guest_interruptibility_info =
8245 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8246 vmcs12->guest_pending_dbg_exceptions =
8247 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8248
7854cbca
ACL		 8249 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8250 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8251 vmcs12->vmx_preemption_timer_value =
8252 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8253
3633cfc3
NHE		 8254 /*
8255 * In some cases (usually, nested EPT), L2 is allowed to change its
8256 * own CR3 without exiting. If it has changed it, we must keep it.
8257 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8258 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8259 *
8260 * Additionally, restore L2's PDPTR to vmcs12.
8261 */
8262 if (enable_ept) {
8263 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8264 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8265 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8266 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8267 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8268 }
8269
c18911a2
JK		 8270 vmcs12->vm_entry_controls =
8271 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8272 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8273
4704d0be
NHE		 8274 /* TODO: These cannot have changed unless we have MSR bitmaps and
8275 * the relevant bit asks not to trap the change */
8276 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8277 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8278 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8279 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8280 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8281 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8282 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8283 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8284
8285 /* update exit information fields: */
8286
533558bc
JK		 8287 vmcs12->vm_exit_reason = exit_reason;
8288 vmcs12->exit_qualification = exit_qualification;
4704d0be 8289
533558bc 8290 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8291 if ((vmcs12->vm_exit_intr_info &
8292 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8293 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8294 vmcs12->vm_exit_intr_error_code =
8295 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8296 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8297 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8298 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8299
5f3d5799
JK		 8300 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8301 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8302 * instead of reading the real value. */
4704d0be 8303 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8304
8305 /*
8306 * Transfer the event that L0 or L1 may wanted to inject into
8307 * L2 to IDT_VECTORING_INFO_FIELD.
8308 */
8309 vmcs12_save_pending_event(vcpu, vmcs12);
8310 }
8311
8312 /*
8313 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8314 * preserved above and would only end up incorrectly in L1.
8315 */
8316 vcpu->arch.nmi_injected = false;
8317 kvm_clear_exception_queue(vcpu);
8318 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8319}
8320
8321/*
8322 * A part of what we need to when the nested L2 guest exits and we want to
8323 * run its L1 parent, is to reset L1's guest state to the host state specified
8324 * in vmcs12.
8325 * This function is to be called not only on normal nested exit, but also on
8326 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8327 * Failures During or After Loading Guest State").
8328 * This function should be called when the active VMCS is L1's (vmcs01).
8329 */
733568f9
JK		 8330static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8331 struct vmcs12 *vmcs12)
4704d0be 8332{
21feb4eb
ACL		 8333 struct kvm_segment seg;
8334
4704d0be
NHE		 8335 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8336 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8337 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8338 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8339 else
8340 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8341 vmx_set_efer(vcpu, vcpu->arch.efer);
8342
8343 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8344 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8345 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8346 /*
8347 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8348 * actually changed, because it depends on the current state of
8349 * fpu_active (which may have changed).
8350 * Note that vmx_set_cr0 refers to efer set above.
8351 */
9e3e4dbf 8352 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8353 /*
8354 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8355 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8356 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8357 */
8358 update_exception_bitmap(vcpu);
8359 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8360 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8361
8362 /*
8363 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8364 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8365 */
8366 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8367 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8368
155a97a3
NHE		 8369 if (nested_cpu_has_ept(vmcs12))
8370 nested_ept_uninit_mmu_context(vcpu);
8371
4704d0be
NHE		 8372 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8373 kvm_mmu_reset_context(vcpu);
8374
feaf0c7d
GN		 8375 if (!enable_ept)
8376 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8377
4704d0be
NHE		 8378 if (enable_vpid) {
8379 /*
8380 * Trivially support vpid by letting L2s share their parent
8381 * L1's vpid. TODO: move to a more elaborate solution, giving
8382 * each L2 its own vpid and exposing the vpid feature to L1.
8383 */
8384 vmx_flush_tlb(vcpu);
8385 }
8386
8387
8388 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8389 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8390 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8391 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8392 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8393
44811c02 8394 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8395 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8396 vcpu->arch.pat = vmcs12->host_ia32_pat;
8397 }
4704d0be
NHE		 8398 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8399 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8400 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8401
21feb4eb
ACL		 8402 /* Set L1 segment info according to Intel SDM
8403 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8404 seg = (struct kvm_segment) {
8405 .base = 0,
8406 .limit = 0xFFFFFFFF,
8407 .selector = vmcs12->host_cs_selector,
8408 .type = 11,
8409 .present = 1,
8410 .s = 1,
8411 .g = 1
8412 };
8413 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8414 seg.l = 1;
8415 else
8416 seg.db = 1;
8417 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8418 seg = (struct kvm_segment) {
8419 .base = 0,
8420 .limit = 0xFFFFFFFF,
8421 .type = 3,
8422 .present = 1,
8423 .s = 1,
8424 .db = 1,
8425 .g = 1
8426 };
8427 seg.selector = vmcs12->host_ds_selector;
8428 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8429 seg.selector = vmcs12->host_es_selector;
8430 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8431 seg.selector = vmcs12->host_ss_selector;
8432 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8433 seg.selector = vmcs12->host_fs_selector;
8434 seg.base = vmcs12->host_fs_base;
8435 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8436 seg.selector = vmcs12->host_gs_selector;
8437 seg.base = vmcs12->host_gs_base;
8438 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8439 seg = (struct kvm_segment) {
205befd9 8440 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8441 .limit = 0x67,
8442 .selector = vmcs12->host_tr_selector,
8443 .type = 11,
8444 .present = 1
8445 };
8446 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8447
503cd0c5
JK		 8448 kvm_set_dr(vcpu, 7, 0x400);
8449 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8450}
8451
8452/*
8453 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8454 * and modify vmcs12 to make it see what it would expect to see there if
8455 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8456 */
533558bc
JK		 8457static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8458 u32 exit_intr_info,
8459 unsigned long exit_qualification)
4704d0be
NHE		 8460{
8461 struct vcpu_vmx *vmx = to_vmx(vcpu);
8462 int cpu;
8463 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8464
5f3d5799
JK		 8465 /* trying to cancel vmlaunch/vmresume is a bug */
8466 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8467
4704d0be 8468 leave_guest_mode(vcpu);
533558bc
JK		 8469 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8470 exit_qualification);
4704d0be
NHE		 8471
8472 cpu = get_cpu();
8473 vmx->loaded_vmcs = &vmx->vmcs01;
8474 vmx_vcpu_put(vcpu);
8475 vmx_vcpu_load(vcpu, cpu);
8476 vcpu->cpu = cpu;
8477 put_cpu();
8478
2961e876
GN		 8479 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8480 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8481 vmx_segment_cache_clear(vmx);
8482
4704d0be
NHE		 8483 /* if no vmcs02 cache requested, remove the one we used */
8484 if (VMCS02_POOL_SIZE == 0)
8485 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8486
8487 load_vmcs12_host_state(vcpu, vmcs12);
8488
27fc51b2 8489 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8490 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8491
8492 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8493 vmx->host_rsp = 0;
8494
8495 /* Unpin physical memory we referred to in vmcs02 */
8496 if (vmx->nested.apic_access_page) {
8497 nested_release_page(vmx->nested.apic_access_page);
8498 vmx->nested.apic_access_page = 0;
8499 }
8500
8501 /*
8502 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8503 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8504 * success or failure flag accordingly.
8505 */
8506 if (unlikely(vmx->fail)) {
8507 vmx->fail = 0;
8508 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8509 } else
8510 nested_vmx_succeed(vcpu);
012f83cb
AG		 8511 if (enable_shadow_vmcs)
8512 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8513}
8514
42124925
JK		 8515/*
8516 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8517 */
8518static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8519{
8520 if (is_guest_mode(vcpu))
533558bc 8521 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8522 free_nested(to_vmx(vcpu));
8523}
8524
7c177938
NHE		 8525/*
8526 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8527 * 23.7 "VM-entry failures during or after loading guest state" (this also
8528 * lists the acceptable exit-reason and exit-qualification parameters).
8529 * It should only be called before L2 actually succeeded to run, and when
8530 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8531 */
8532static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8533 struct vmcs12 *vmcs12,
8534 u32 reason, unsigned long qualification)
8535{
8536 load_vmcs12_host_state(vcpu, vmcs12);
8537 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8538 vmcs12->exit_qualification = qualification;
8539 nested_vmx_succeed(vcpu);
012f83cb
AG		 8540 if (enable_shadow_vmcs)
8541 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8542}
8543
8a76d7f2
JR		 8544static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8545 struct x86_instruction_info *info,
8546 enum x86_intercept_stage stage)
8547{
8548 return X86EMUL_CONTINUE;
8549}
8550
cbdd1bea 8551static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8552 .cpu_has_kvm_support = cpu_has_kvm_support,
8553 .disabled_by_bios = vmx_disabled_by_bios,
8554 .hardware_setup = hardware_setup,
8555 .hardware_unsetup = hardware_unsetup,
002c7f7c 8556 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8557 .hardware_enable = hardware_enable,
8558 .hardware_disable = hardware_disable,
04547156 8559 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8560
8561 .vcpu_create = vmx_create_vcpu,
8562 .vcpu_free = vmx_free_vcpu,
04d2cc77 8563 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8564
04d2cc77 8565 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8566 .vcpu_load = vmx_vcpu_load,
8567 .vcpu_put = vmx_vcpu_put,
8568
c8639010 8569 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8570 .get_msr = vmx_get_msr,
8571 .set_msr = vmx_set_msr,
8572 .get_segment_base = vmx_get_segment_base,
8573 .get_segment = vmx_get_segment,
8574 .set_segment = vmx_set_segment,
2e4d2653 8575 .get_cpl = vmx_get_cpl,
6aa8b732 8576 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8577 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8578 .decache_cr3 = vmx_decache_cr3,
25c4c276 8579 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8580 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8581 .set_cr3 = vmx_set_cr3,
8582 .set_cr4 = vmx_set_cr4,
6aa8b732 8583 .set_efer = vmx_set_efer,
6aa8b732
AK		 8584 .get_idt = vmx_get_idt,
8585 .set_idt = vmx_set_idt,
8586 .get_gdt = vmx_get_gdt,
8587 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8588 .get_dr6 = vmx_get_dr6,
8589 .set_dr6 = vmx_set_dr6,
020df079 8590 .set_dr7 = vmx_set_dr7,
5fdbf976 8591 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8592 .get_rflags = vmx_get_rflags,
8593 .set_rflags = vmx_set_rflags,
ebcbab4c 8594 .fpu_activate = vmx_fpu_activate,
02daab21 8595 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8596
8597 .tlb_flush = vmx_flush_tlb,
6aa8b732 8598
6aa8b732 8599 .run = vmx_vcpu_run,
6062d012 8600 .handle_exit = vmx_handle_exit,
6aa8b732 8601 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8602 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8603 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8604 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8605 .set_irq = vmx_inject_irq,
95ba8273 8606 .set_nmi = vmx_inject_nmi,
298101da 8607 .queue_exception = vmx_queue_exception,
b463a6f7 8608 .cancel_injection = vmx_cancel_injection,
78646121 8609 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8610 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8611 .get_nmi_mask = vmx_get_nmi_mask,
8612 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8613 .enable_nmi_window = enable_nmi_window,
8614 .enable_irq_window = enable_irq_window,
8615 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8616 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8617 .vm_has_apicv = vmx_vm_has_apicv,
8618 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8619 .hwapic_irr_update = vmx_hwapic_irr_update,
8620 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8621 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8622 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8623
cbc94022 8624 .set_tss_addr = vmx_set_tss_addr,
67253af5 8625 .get_tdp_level = get_ept_level,
4b12f0de 8626 .get_mt_mask = vmx_get_mt_mask,
229456fc 8627
586f9607 8628 .get_exit_info = vmx_get_exit_info,
586f9607 8629
17cc3935 8630 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8631
8632 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8633
8634 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8635 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8636
8637 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8638
8639 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8640
4051b188 8641 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8642 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8643 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8644 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8645 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8646 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8647
8648 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8649
8650 .check_intercept = vmx_check_intercept,
a547c6db 8651 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8652};
8653
8654static int __init vmx_init(void)
8655{
8d14695f 8656 int r, i, msr;
26bb0981
AK		 8657
8658 rdmsrl_safe(MSR_EFER, &host_efer);
8659
8660 for (i = 0; i < NR_VMX_MSR; ++i)
8661 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8662
3e7c73e9 8663 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8664 if (!vmx_io_bitmap_a)
8665 return -ENOMEM;
8666
2106a548
GC		 8667 r = -ENOMEM;
8668
3e7c73e9 8669 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8670 if (!vmx_io_bitmap_b)
fdef3ad1 8671 goto out;
fdef3ad1 8672
5897297b 8673 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8674 if (!vmx_msr_bitmap_legacy)
25c5f225 8675 goto out1;
2106a548 8676
8d14695f
YZ		 8677 vmx_msr_bitmap_legacy_x2apic =
8678 (unsigned long *)__get_free_page(GFP_KERNEL);
8679 if (!vmx_msr_bitmap_legacy_x2apic)
8680 goto out2;
25c5f225 8681
5897297b 8682 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8683 if (!vmx_msr_bitmap_longmode)
8d14695f 8684 goto out3;
2106a548 8685
8d14695f
YZ		 8686 vmx_msr_bitmap_longmode_x2apic =
8687 (unsigned long *)__get_free_page(GFP_KERNEL);
8688 if (!vmx_msr_bitmap_longmode_x2apic)
8689 goto out4;
4607c2d7
AG		 8690 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8691 if (!vmx_vmread_bitmap)
8692 goto out5;
8693
8694 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8695 if (!vmx_vmwrite_bitmap)
8696 goto out6;
8697
8698 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8699 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8700 /* shadowed read/write fields */
8701 for (i = 0; i < max_shadow_read_write_fields; i++) {
8702 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8703 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8704 }
8705 /* shadowed read only fields */
8706 for (i = 0; i < max_shadow_read_only_fields; i++)
8707 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8708
fdef3ad1
HQ		 8709 /*
8710 * Allow direct access to the PC debug port (it is often used for I/O
8711 * delays, but the vmexits simply slow things down).
8712 */
3e7c73e9
AK		 8713 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8714 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8715
3e7c73e9 8716 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8717
5897297b
AK		 8718 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8719 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8720
2384d2b3
SY		 8721 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8722
0ee75bea
AK		 8723 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8724 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8725 if (r)
4607c2d7 8726 goto out7;
25c5f225 8727
8f536b76
ZY		 8728#ifdef CONFIG_KEXEC
8729 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8730 crash_vmclear_local_loaded_vmcss);
8731#endif
8732
5897297b
AK		 8733 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8734 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8735 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8736 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8737 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8738 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8739 memcpy(vmx_msr_bitmap_legacy_x2apic,
8740 vmx_msr_bitmap_legacy, PAGE_SIZE);
8741 memcpy(vmx_msr_bitmap_longmode_x2apic,
8742 vmx_msr_bitmap_longmode, PAGE_SIZE);
8743
01e439be 8744 if (enable_apicv) {
8d14695f
YZ		 8745 for (msr = 0x800; msr <= 0x8ff; msr++)
8746 vmx_disable_intercept_msr_read_x2apic(msr);
8747
8748 /* According SDM, in x2apic mode, the whole id reg is used.
8749 * But in KVM, it only use the highest eight bits. Need to
8750 * intercept it */
8751 vmx_enable_intercept_msr_read_x2apic(0x802);
8752 /* TMCCT */
8753 vmx_enable_intercept_msr_read_x2apic(0x839);
8754 /* TPR */
8755 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8756 /* EOI */
8757 vmx_disable_intercept_msr_write_x2apic(0x80b);
8758 /* SELF-IPI */
8759 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8760 }
fdef3ad1 8761
089d034e 8762 if (enable_ept) {
3f6d8c8a
XH		 8763 kvm_mmu_set_mask_ptes(0ull,
8764 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8765 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8766 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8767 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8768 kvm_enable_tdp();
8769 } else
8770 kvm_disable_tdp();
1439442c 8771
fdef3ad1
HQ		 8772 return 0;
8773
4607c2d7
AG		 8774out7:
8775 free_page((unsigned long)vmx_vmwrite_bitmap);
8776out6:
8777 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8778out5:
8779 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8780out4:
5897297b 8781 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8782out3:
8783 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8784out2:
5897297b 8785 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8786out1:
3e7c73e9 8787 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8788out:
3e7c73e9 8789 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8790 return r;
6aa8b732
AK		 8791}
8792
8793static void __exit vmx_exit(void)
8794{
8d14695f
YZ		 8795 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8796 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8797 free_page((unsigned long)vmx_msr_bitmap_legacy);
8798 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8799 free_page((unsigned long)vmx_io_bitmap_b);
8800 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8801 free_page((unsigned long)vmx_vmwrite_bitmap);
8802 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8803
8f536b76
ZY		 8804#ifdef CONFIG_KEXEC
8805 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8806 synchronize_rcu();
8807#endif
8808
cb498ea2 8809 kvm_exit();
6aa8b732
AK		 8810}
8811
8812module_init(vmx_init)
8813module_exit(vmx_exit)
Linux kernel - Deliverables
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