Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
cafd6659 | 31 | #include <linux/tboot.h> |
5fdbf976 | 32 | #include "kvm_cache_regs.h" |
35920a35 | 33 | #include "x86.h" |
e495606d | 34 | |
6aa8b732 | 35 | #include <asm/io.h> |
3b3be0d1 | 36 | #include <asm/desc.h> |
13673a90 | 37 | #include <asm/vmx.h> |
6210e37b | 38 | #include <asm/virtext.h> |
a0861c02 | 39 | #include <asm/mce.h> |
2acf923e DC |
40 | #include <asm/i387.h> |
41 | #include <asm/xcr.h> | |
6aa8b732 | 42 | |
229456fc MT |
43 | #include "trace.h" |
44 | ||
4ecac3fd AK |
45 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
46 | ||
6aa8b732 AK |
47 | MODULE_AUTHOR("Qumranet"); |
48 | MODULE_LICENSE("GPL"); | |
49 | ||
4462d21a | 50 | static int __read_mostly bypass_guest_pf = 1; |
c1f8bc04 | 51 | module_param(bypass_guest_pf, bool, S_IRUGO); |
c7addb90 | 52 | |
4462d21a | 53 | static int __read_mostly enable_vpid = 1; |
736caefe | 54 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 55 | |
4462d21a | 56 | static int __read_mostly flexpriority_enabled = 1; |
736caefe | 57 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 58 | |
4462d21a | 59 | static int __read_mostly enable_ept = 1; |
736caefe | 60 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 61 | |
3a624e29 NK |
62 | static int __read_mostly enable_unrestricted_guest = 1; |
63 | module_param_named(unrestricted_guest, | |
64 | enable_unrestricted_guest, bool, S_IRUGO); | |
65 | ||
4462d21a | 66 | static int __read_mostly emulate_invalid_guest_state = 0; |
c1f8bc04 | 67 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 68 | |
b923e62e DX |
69 | static int __read_mostly vmm_exclusive = 1; |
70 | module_param(vmm_exclusive, bool, S_IRUGO); | |
71 | ||
443381a8 AL |
72 | static int __read_mostly yield_on_hlt = 1; |
73 | module_param(yield_on_hlt, bool, S_IRUGO); | |
74 | ||
cdc0e244 AK |
75 | #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \ |
76 | (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD) | |
77 | #define KVM_GUEST_CR0_MASK \ | |
78 | (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
79 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \ | |
81231c69 | 80 | (X86_CR0_WP | X86_CR0_NE) |
cdc0e244 AK |
81 | #define KVM_VM_CR0_ALWAYS_ON \ |
82 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
83 | #define KVM_CR4_GUEST_OWNED_BITS \ |
84 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
85 | | X86_CR4_OSXMMEXCPT) | |
86 | ||
cdc0e244 AK |
87 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
88 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
89 | ||
78ac8b47 AK |
90 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
91 | ||
4b8d54f9 ZE |
92 | /* |
93 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
94 | * ple_gap: upper bound on the amount of time between two successive | |
95 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 96 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
97 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
98 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
99 | * less than 2^12 cycles | |
100 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
101 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
102 | */ | |
00c25bce | 103 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
4b8d54f9 ZE |
104 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 |
105 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; | |
106 | module_param(ple_gap, int, S_IRUGO); | |
107 | ||
108 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
109 | module_param(ple_window, int, S_IRUGO); | |
110 | ||
61d2ef2c AK |
111 | #define NR_AUTOLOAD_MSRS 1 |
112 | ||
a2fa3e9f GH |
113 | struct vmcs { |
114 | u32 revision_id; | |
115 | u32 abort; | |
116 | char data[0]; | |
117 | }; | |
118 | ||
26bb0981 AK |
119 | struct shared_msr_entry { |
120 | unsigned index; | |
121 | u64 data; | |
d5696725 | 122 | u64 mask; |
26bb0981 AK |
123 | }; |
124 | ||
a2fa3e9f | 125 | struct vcpu_vmx { |
fb3f0f51 | 126 | struct kvm_vcpu vcpu; |
543e4243 | 127 | struct list_head local_vcpus_link; |
313dbd49 | 128 | unsigned long host_rsp; |
a2fa3e9f | 129 | int launched; |
29bd8a78 | 130 | u8 fail; |
51aa01d1 | 131 | u32 exit_intr_info; |
1155f76a | 132 | u32 idt_vectoring_info; |
26bb0981 | 133 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
134 | int nmsrs; |
135 | int save_nmsrs; | |
a2fa3e9f | 136 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
137 | u64 msr_host_kernel_gs_base; |
138 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f GH |
139 | #endif |
140 | struct vmcs *vmcs; | |
61d2ef2c AK |
141 | struct msr_autoload { |
142 | unsigned nr; | |
143 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
144 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
145 | } msr_autoload; | |
a2fa3e9f GH |
146 | struct { |
147 | int loaded; | |
148 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
149 | int gs_ldt_reload_needed; |
150 | int fs_reload_needed; | |
d77c26fc | 151 | } host_state; |
9c8cba37 | 152 | struct { |
7ffd92c5 | 153 | int vm86_active; |
78ac8b47 | 154 | ulong save_rflags; |
7ffd92c5 AK |
155 | struct kvm_save_segment { |
156 | u16 selector; | |
157 | unsigned long base; | |
158 | u32 limit; | |
159 | u32 ar; | |
160 | } tr, es, ds, fs, gs; | |
9c8cba37 | 161 | } rmode; |
2384d2b3 | 162 | int vpid; |
04fa4d32 | 163 | bool emulation_required; |
3b86cd99 JK |
164 | |
165 | /* Support for vnmi-less CPUs */ | |
166 | int soft_vnmi_blocked; | |
167 | ktime_t entry_time; | |
168 | s64 vnmi_blocked_time; | |
a0861c02 | 169 | u32 exit_reason; |
4e47c7a6 SY |
170 | |
171 | bool rdtscp_enabled; | |
a2fa3e9f GH |
172 | }; |
173 | ||
174 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
175 | { | |
fb3f0f51 | 176 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
177 | } |
178 | ||
4e1096d2 | 179 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
180 | static void kvm_cpu_vmxon(u64 addr); |
181 | static void kvm_cpu_vmxoff(void); | |
aff48baa | 182 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
776e58ea | 183 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
75880a01 | 184 | |
6aa8b732 AK |
185 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
186 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 187 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
3444d7da | 188 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 189 | |
3e7c73e9 AK |
190 | static unsigned long *vmx_io_bitmap_a; |
191 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
192 | static unsigned long *vmx_msr_bitmap_legacy; |
193 | static unsigned long *vmx_msr_bitmap_longmode; | |
fdef3ad1 | 194 | |
110312c8 AK |
195 | static bool cpu_has_load_ia32_efer; |
196 | ||
2384d2b3 SY |
197 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
198 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
199 | ||
1c3d14fe | 200 | static struct vmcs_config { |
6aa8b732 AK |
201 | int size; |
202 | int order; | |
203 | u32 revision_id; | |
1c3d14fe YS |
204 | u32 pin_based_exec_ctrl; |
205 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 206 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
207 | u32 vmexit_ctrl; |
208 | u32 vmentry_ctrl; | |
209 | } vmcs_config; | |
6aa8b732 | 210 | |
efff9e53 | 211 | static struct vmx_capability { |
d56f546d SY |
212 | u32 ept; |
213 | u32 vpid; | |
214 | } vmx_capability; | |
215 | ||
6aa8b732 AK |
216 | #define VMX_SEGMENT_FIELD(seg) \ |
217 | [VCPU_SREG_##seg] = { \ | |
218 | .selector = GUEST_##seg##_SELECTOR, \ | |
219 | .base = GUEST_##seg##_BASE, \ | |
220 | .limit = GUEST_##seg##_LIMIT, \ | |
221 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
222 | } | |
223 | ||
224 | static struct kvm_vmx_segment_field { | |
225 | unsigned selector; | |
226 | unsigned base; | |
227 | unsigned limit; | |
228 | unsigned ar_bytes; | |
229 | } kvm_vmx_segment_fields[] = { | |
230 | VMX_SEGMENT_FIELD(CS), | |
231 | VMX_SEGMENT_FIELD(DS), | |
232 | VMX_SEGMENT_FIELD(ES), | |
233 | VMX_SEGMENT_FIELD(FS), | |
234 | VMX_SEGMENT_FIELD(GS), | |
235 | VMX_SEGMENT_FIELD(SS), | |
236 | VMX_SEGMENT_FIELD(TR), | |
237 | VMX_SEGMENT_FIELD(LDTR), | |
238 | }; | |
239 | ||
26bb0981 AK |
240 | static u64 host_efer; |
241 | ||
6de4f3ad AK |
242 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
243 | ||
4d56c8a7 | 244 | /* |
8c06585d | 245 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
246 | * away by decrementing the array size. |
247 | */ | |
6aa8b732 | 248 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 249 | #ifdef CONFIG_X86_64 |
44ea2b17 | 250 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 251 | #endif |
8c06585d | 252 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 253 | }; |
9d8f549d | 254 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 255 | |
31299944 | 256 | static inline bool is_page_fault(u32 intr_info) |
6aa8b732 AK |
257 | { |
258 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
259 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 260 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
261 | } |
262 | ||
31299944 | 263 | static inline bool is_no_device(u32 intr_info) |
2ab455cc AL |
264 | { |
265 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
266 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 267 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
268 | } |
269 | ||
31299944 | 270 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 AL |
271 | { |
272 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
273 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 274 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
275 | } |
276 | ||
31299944 | 277 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
278 | { |
279 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
280 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
281 | } | |
282 | ||
31299944 | 283 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
284 | { |
285 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
286 | INTR_INFO_VALID_MASK)) == | |
287 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
288 | } | |
289 | ||
31299944 | 290 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 291 | { |
04547156 | 292 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
293 | } |
294 | ||
31299944 | 295 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 296 | { |
04547156 | 297 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
298 | } |
299 | ||
31299944 | 300 | static inline bool vm_need_tpr_shadow(struct kvm *kvm) |
6e5d865c | 301 | { |
04547156 | 302 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
6e5d865c YS |
303 | } |
304 | ||
31299944 | 305 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 306 | { |
04547156 SY |
307 | return vmcs_config.cpu_based_exec_ctrl & |
308 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
309 | } |
310 | ||
774ead3a | 311 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 312 | { |
04547156 SY |
313 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
314 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
315 | } | |
316 | ||
317 | static inline bool cpu_has_vmx_flexpriority(void) | |
318 | { | |
319 | return cpu_has_vmx_tpr_shadow() && | |
320 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
321 | } |
322 | ||
e799794e MT |
323 | static inline bool cpu_has_vmx_ept_execute_only(void) |
324 | { | |
31299944 | 325 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
326 | } |
327 | ||
328 | static inline bool cpu_has_vmx_eptp_uncacheable(void) | |
329 | { | |
31299944 | 330 | return vmx_capability.ept & VMX_EPTP_UC_BIT; |
e799794e MT |
331 | } |
332 | ||
333 | static inline bool cpu_has_vmx_eptp_writeback(void) | |
334 | { | |
31299944 | 335 | return vmx_capability.ept & VMX_EPTP_WB_BIT; |
e799794e MT |
336 | } |
337 | ||
338 | static inline bool cpu_has_vmx_ept_2m_page(void) | |
339 | { | |
31299944 | 340 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
341 | } |
342 | ||
878403b7 SY |
343 | static inline bool cpu_has_vmx_ept_1g_page(void) |
344 | { | |
31299944 | 345 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
346 | } |
347 | ||
4bc9b982 SY |
348 | static inline bool cpu_has_vmx_ept_4levels(void) |
349 | { | |
350 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
351 | } | |
352 | ||
31299944 | 353 | static inline bool cpu_has_vmx_invept_individual_addr(void) |
d56f546d | 354 | { |
31299944 | 355 | return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT; |
d56f546d SY |
356 | } |
357 | ||
31299944 | 358 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 359 | { |
31299944 | 360 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
361 | } |
362 | ||
31299944 | 363 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 364 | { |
31299944 | 365 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
366 | } |
367 | ||
518c8aee GJ |
368 | static inline bool cpu_has_vmx_invvpid_single(void) |
369 | { | |
370 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
371 | } | |
372 | ||
b9d762fa GJ |
373 | static inline bool cpu_has_vmx_invvpid_global(void) |
374 | { | |
375 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
376 | } | |
377 | ||
31299944 | 378 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 379 | { |
04547156 SY |
380 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
381 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
382 | } |
383 | ||
31299944 | 384 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
385 | { |
386 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
387 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
388 | } | |
389 | ||
31299944 | 390 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
391 | { |
392 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
393 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
394 | } | |
395 | ||
31299944 | 396 | static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) |
f78e0e2e | 397 | { |
6d3e435e | 398 | return flexpriority_enabled && irqchip_in_kernel(kvm); |
f78e0e2e SY |
399 | } |
400 | ||
31299944 | 401 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 402 | { |
04547156 SY |
403 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
404 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
405 | } |
406 | ||
31299944 | 407 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
408 | { |
409 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
410 | SECONDARY_EXEC_RDTSCP; | |
411 | } | |
412 | ||
31299944 | 413 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
414 | { |
415 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
416 | } | |
417 | ||
f5f48ee1 SY |
418 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
419 | { | |
420 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
421 | SECONDARY_EXEC_WBINVD_EXITING; | |
422 | } | |
423 | ||
04547156 SY |
424 | static inline bool report_flexpriority(void) |
425 | { | |
426 | return flexpriority_enabled; | |
427 | } | |
428 | ||
8b9cf98c | 429 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
430 | { |
431 | int i; | |
432 | ||
a2fa3e9f | 433 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 434 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
435 | return i; |
436 | return -1; | |
437 | } | |
438 | ||
2384d2b3 SY |
439 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
440 | { | |
441 | struct { | |
442 | u64 vpid : 16; | |
443 | u64 rsvd : 48; | |
444 | u64 gva; | |
445 | } operand = { vpid, 0, gva }; | |
446 | ||
4ecac3fd | 447 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
448 | /* CF==1 or ZF==1 --> rc = -1 */ |
449 | "; ja 1f ; ud2 ; 1:" | |
450 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
451 | } | |
452 | ||
1439442c SY |
453 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
454 | { | |
455 | struct { | |
456 | u64 eptp, gpa; | |
457 | } operand = {eptp, gpa}; | |
458 | ||
4ecac3fd | 459 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
460 | /* CF==1 or ZF==1 --> rc = -1 */ |
461 | "; ja 1f ; ud2 ; 1:\n" | |
462 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
463 | } | |
464 | ||
26bb0981 | 465 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
466 | { |
467 | int i; | |
468 | ||
8b9cf98c | 469 | i = __find_msr_index(vmx, msr); |
a75beee6 | 470 | if (i >= 0) |
a2fa3e9f | 471 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 472 | return NULL; |
7725f0ba AK |
473 | } |
474 | ||
6aa8b732 AK |
475 | static void vmcs_clear(struct vmcs *vmcs) |
476 | { | |
477 | u64 phys_addr = __pa(vmcs); | |
478 | u8 error; | |
479 | ||
4ecac3fd | 480 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 481 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
482 | : "cc", "memory"); |
483 | if (error) | |
484 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
485 | vmcs, phys_addr); | |
486 | } | |
487 | ||
7725b894 DX |
488 | static void vmcs_load(struct vmcs *vmcs) |
489 | { | |
490 | u64 phys_addr = __pa(vmcs); | |
491 | u8 error; | |
492 | ||
493 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 494 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
495 | : "cc", "memory"); |
496 | if (error) | |
497 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
498 | vmcs, phys_addr); | |
499 | } | |
500 | ||
6aa8b732 AK |
501 | static void __vcpu_clear(void *arg) |
502 | { | |
8b9cf98c | 503 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 504 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 505 | |
8b9cf98c | 506 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
507 | vmcs_clear(vmx->vmcs); |
508 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 509 | per_cpu(current_vmcs, cpu) = NULL; |
543e4243 AK |
510 | list_del(&vmx->local_vcpus_link); |
511 | vmx->vcpu.cpu = -1; | |
512 | vmx->launched = 0; | |
6aa8b732 AK |
513 | } |
514 | ||
8b9cf98c | 515 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 516 | { |
eae5ecb5 AK |
517 | if (vmx->vcpu.cpu == -1) |
518 | return; | |
8691e5a8 | 519 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
520 | } |
521 | ||
1760dd49 | 522 | static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx) |
2384d2b3 SY |
523 | { |
524 | if (vmx->vpid == 0) | |
525 | return; | |
526 | ||
518c8aee GJ |
527 | if (cpu_has_vmx_invvpid_single()) |
528 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
2384d2b3 SY |
529 | } |
530 | ||
b9d762fa GJ |
531 | static inline void vpid_sync_vcpu_global(void) |
532 | { | |
533 | if (cpu_has_vmx_invvpid_global()) | |
534 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
535 | } | |
536 | ||
537 | static inline void vpid_sync_context(struct vcpu_vmx *vmx) | |
538 | { | |
539 | if (cpu_has_vmx_invvpid_single()) | |
1760dd49 | 540 | vpid_sync_vcpu_single(vmx); |
b9d762fa GJ |
541 | else |
542 | vpid_sync_vcpu_global(); | |
543 | } | |
544 | ||
1439442c SY |
545 | static inline void ept_sync_global(void) |
546 | { | |
547 | if (cpu_has_vmx_invept_global()) | |
548 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
549 | } | |
550 | ||
551 | static inline void ept_sync_context(u64 eptp) | |
552 | { | |
089d034e | 553 | if (enable_ept) { |
1439442c SY |
554 | if (cpu_has_vmx_invept_context()) |
555 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
556 | else | |
557 | ept_sync_global(); | |
558 | } | |
559 | } | |
560 | ||
561 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
562 | { | |
089d034e | 563 | if (enable_ept) { |
1439442c SY |
564 | if (cpu_has_vmx_invept_individual_addr()) |
565 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
566 | eptp, gpa); | |
567 | else | |
568 | ept_sync_context(eptp); | |
569 | } | |
570 | } | |
571 | ||
6aa8b732 AK |
572 | static unsigned long vmcs_readl(unsigned long field) |
573 | { | |
a295673a | 574 | unsigned long value = 0; |
6aa8b732 | 575 | |
4ecac3fd | 576 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
a295673a | 577 | : "+a"(value) : "d"(field) : "cc"); |
6aa8b732 AK |
578 | return value; |
579 | } | |
580 | ||
581 | static u16 vmcs_read16(unsigned long field) | |
582 | { | |
583 | return vmcs_readl(field); | |
584 | } | |
585 | ||
586 | static u32 vmcs_read32(unsigned long field) | |
587 | { | |
588 | return vmcs_readl(field); | |
589 | } | |
590 | ||
591 | static u64 vmcs_read64(unsigned long field) | |
592 | { | |
05b3e0c2 | 593 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
594 | return vmcs_readl(field); |
595 | #else | |
596 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
597 | #endif | |
598 | } | |
599 | ||
e52de1b8 AK |
600 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
601 | { | |
602 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
603 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
604 | dump_stack(); | |
605 | } | |
606 | ||
6aa8b732 AK |
607 | static void vmcs_writel(unsigned long field, unsigned long value) |
608 | { | |
609 | u8 error; | |
610 | ||
4ecac3fd | 611 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 612 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
613 | if (unlikely(error)) |
614 | vmwrite_error(field, value); | |
6aa8b732 AK |
615 | } |
616 | ||
617 | static void vmcs_write16(unsigned long field, u16 value) | |
618 | { | |
619 | vmcs_writel(field, value); | |
620 | } | |
621 | ||
622 | static void vmcs_write32(unsigned long field, u32 value) | |
623 | { | |
624 | vmcs_writel(field, value); | |
625 | } | |
626 | ||
627 | static void vmcs_write64(unsigned long field, u64 value) | |
628 | { | |
6aa8b732 | 629 | vmcs_writel(field, value); |
7682f2d0 | 630 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
631 | asm volatile (""); |
632 | vmcs_writel(field+1, value >> 32); | |
633 | #endif | |
634 | } | |
635 | ||
2ab455cc AL |
636 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
637 | { | |
638 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
639 | } | |
640 | ||
641 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
642 | { | |
643 | vmcs_writel(field, vmcs_readl(field) | mask); | |
644 | } | |
645 | ||
abd3f2d6 AK |
646 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
647 | { | |
648 | u32 eb; | |
649 | ||
fd7373cc JK |
650 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
651 | (1u << NM_VECTOR) | (1u << DB_VECTOR); | |
652 | if ((vcpu->guest_debug & | |
653 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
654 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
655 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 656 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 657 | eb = ~0; |
089d034e | 658 | if (enable_ept) |
1439442c | 659 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
660 | if (vcpu->fpu_active) |
661 | eb &= ~(1u << NM_VECTOR); | |
abd3f2d6 AK |
662 | vmcs_write32(EXCEPTION_BITMAP, eb); |
663 | } | |
664 | ||
61d2ef2c AK |
665 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
666 | { | |
667 | unsigned i; | |
668 | struct msr_autoload *m = &vmx->msr_autoload; | |
669 | ||
110312c8 AK |
670 | if (msr == MSR_EFER && cpu_has_load_ia32_efer) { |
671 | vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER); | |
672 | vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER); | |
673 | return; | |
674 | } | |
675 | ||
61d2ef2c AK |
676 | for (i = 0; i < m->nr; ++i) |
677 | if (m->guest[i].index == msr) | |
678 | break; | |
679 | ||
680 | if (i == m->nr) | |
681 | return; | |
682 | --m->nr; | |
683 | m->guest[i] = m->guest[m->nr]; | |
684 | m->host[i] = m->host[m->nr]; | |
685 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
686 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
687 | } | |
688 | ||
689 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, | |
690 | u64 guest_val, u64 host_val) | |
691 | { | |
692 | unsigned i; | |
693 | struct msr_autoload *m = &vmx->msr_autoload; | |
694 | ||
110312c8 AK |
695 | if (msr == MSR_EFER && cpu_has_load_ia32_efer) { |
696 | vmcs_write64(GUEST_IA32_EFER, guest_val); | |
697 | vmcs_write64(HOST_IA32_EFER, host_val); | |
698 | vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER); | |
699 | vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER); | |
700 | return; | |
701 | } | |
702 | ||
61d2ef2c AK |
703 | for (i = 0; i < m->nr; ++i) |
704 | if (m->guest[i].index == msr) | |
705 | break; | |
706 | ||
707 | if (i == m->nr) { | |
708 | ++m->nr; | |
709 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
710 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
711 | } | |
712 | ||
713 | m->guest[i].index = msr; | |
714 | m->guest[i].value = guest_val; | |
715 | m->host[i].index = msr; | |
716 | m->host[i].value = host_val; | |
717 | } | |
718 | ||
33ed6329 AK |
719 | static void reload_tss(void) |
720 | { | |
33ed6329 AK |
721 | /* |
722 | * VT restores TR but not its size. Useless. | |
723 | */ | |
d359192f | 724 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
a5f61300 | 725 | struct desc_struct *descs; |
33ed6329 | 726 | |
d359192f | 727 | descs = (void *)gdt->address; |
33ed6329 AK |
728 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
729 | load_TR_desc(); | |
33ed6329 AK |
730 | } |
731 | ||
92c0d900 | 732 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 733 | { |
3a34a881 | 734 | u64 guest_efer; |
51c6cf66 AK |
735 | u64 ignore_bits; |
736 | ||
f6801dff | 737 | guest_efer = vmx->vcpu.arch.efer; |
3a34a881 | 738 | |
51c6cf66 AK |
739 | /* |
740 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
741 | * outside long mode | |
742 | */ | |
743 | ignore_bits = EFER_NX | EFER_SCE; | |
744 | #ifdef CONFIG_X86_64 | |
745 | ignore_bits |= EFER_LMA | EFER_LME; | |
746 | /* SCE is meaningful only in long mode on Intel */ | |
747 | if (guest_efer & EFER_LMA) | |
748 | ignore_bits &= ~(u64)EFER_SCE; | |
749 | #endif | |
51c6cf66 AK |
750 | guest_efer &= ~ignore_bits; |
751 | guest_efer |= host_efer & ignore_bits; | |
26bb0981 | 752 | vmx->guest_msrs[efer_offset].data = guest_efer; |
d5696725 | 753 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
84ad33ef AK |
754 | |
755 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
756 | /* On ept, can't emulate nx, and must switch nx atomically */ | |
757 | if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) { | |
758 | guest_efer = vmx->vcpu.arch.efer; | |
759 | if (!(guest_efer & EFER_LMA)) | |
760 | guest_efer &= ~EFER_LME; | |
761 | add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer); | |
762 | return false; | |
763 | } | |
764 | ||
26bb0981 | 765 | return true; |
51c6cf66 AK |
766 | } |
767 | ||
2d49ec72 GN |
768 | static unsigned long segment_base(u16 selector) |
769 | { | |
d359192f | 770 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
2d49ec72 GN |
771 | struct desc_struct *d; |
772 | unsigned long table_base; | |
773 | unsigned long v; | |
774 | ||
775 | if (!(selector & ~3)) | |
776 | return 0; | |
777 | ||
d359192f | 778 | table_base = gdt->address; |
2d49ec72 GN |
779 | |
780 | if (selector & 4) { /* from ldt */ | |
781 | u16 ldt_selector = kvm_read_ldt(); | |
782 | ||
783 | if (!(ldt_selector & ~3)) | |
784 | return 0; | |
785 | ||
786 | table_base = segment_base(ldt_selector); | |
787 | } | |
788 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
789 | v = get_desc_base(d); | |
790 | #ifdef CONFIG_X86_64 | |
791 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
792 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
793 | #endif | |
794 | return v; | |
795 | } | |
796 | ||
797 | static inline unsigned long kvm_read_tr_base(void) | |
798 | { | |
799 | u16 tr; | |
800 | asm("str %0" : "=g"(tr)); | |
801 | return segment_base(tr); | |
802 | } | |
803 | ||
04d2cc77 | 804 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 805 | { |
04d2cc77 | 806 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 807 | int i; |
04d2cc77 | 808 | |
a2fa3e9f | 809 | if (vmx->host_state.loaded) |
33ed6329 AK |
810 | return; |
811 | ||
a2fa3e9f | 812 | vmx->host_state.loaded = 1; |
33ed6329 AK |
813 | /* |
814 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
815 | * allow segment selectors with cpl > 0 or ti == 1. | |
816 | */ | |
d6e88aec | 817 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 818 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 819 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 820 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 821 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
822 | vmx->host_state.fs_reload_needed = 0; |
823 | } else { | |
33ed6329 | 824 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 825 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 826 | } |
9581d442 | 827 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
828 | if (!(vmx->host_state.gs_sel & 7)) |
829 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
830 | else { |
831 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 832 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
833 | } |
834 | ||
835 | #ifdef CONFIG_X86_64 | |
836 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
837 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
838 | #else | |
a2fa3e9f GH |
839 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
840 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 841 | #endif |
707c0874 AK |
842 | |
843 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
844 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
845 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 846 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 847 | #endif |
26bb0981 AK |
848 | for (i = 0; i < vmx->save_nmsrs; ++i) |
849 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
850 | vmx->guest_msrs[i].data, |
851 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
852 | } |
853 | ||
a9b21b62 | 854 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 855 | { |
a2fa3e9f | 856 | if (!vmx->host_state.loaded) |
33ed6329 AK |
857 | return; |
858 | ||
e1beb1d3 | 859 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 860 | vmx->host_state.loaded = 0; |
c8770e7b AK |
861 | #ifdef CONFIG_X86_64 |
862 | if (is_long_mode(&vmx->vcpu)) | |
863 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
864 | #endif | |
152d3f2f | 865 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 866 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 867 | #ifdef CONFIG_X86_64 |
9581d442 | 868 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
869 | #else |
870 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 871 | #endif |
33ed6329 | 872 | } |
0a77fe4c AK |
873 | if (vmx->host_state.fs_reload_needed) |
874 | loadsegment(fs, vmx->host_state.fs_sel); | |
152d3f2f | 875 | reload_tss(); |
44ea2b17 | 876 | #ifdef CONFIG_X86_64 |
c8770e7b | 877 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 878 | #endif |
1c11e713 AK |
879 | if (current_thread_info()->status & TS_USEDFPU) |
880 | clts(); | |
3444d7da | 881 | load_gdt(&__get_cpu_var(host_gdt)); |
33ed6329 AK |
882 | } |
883 | ||
a9b21b62 AK |
884 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
885 | { | |
886 | preempt_disable(); | |
887 | __vmx_load_host_state(vmx); | |
888 | preempt_enable(); | |
889 | } | |
890 | ||
6aa8b732 AK |
891 | /* |
892 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
893 | * vcpu mutex is already taken. | |
894 | */ | |
15ad7146 | 895 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 896 | { |
a2fa3e9f | 897 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 898 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 899 | |
4610c9cc DX |
900 | if (!vmm_exclusive) |
901 | kvm_cpu_vmxon(phys_addr); | |
902 | else if (vcpu->cpu != cpu) | |
8b9cf98c | 903 | vcpu_clear(vmx); |
6aa8b732 | 904 | |
a2fa3e9f | 905 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
a2fa3e9f | 906 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
7725b894 | 907 | vmcs_load(vmx->vmcs); |
6aa8b732 AK |
908 | } |
909 | ||
910 | if (vcpu->cpu != cpu) { | |
d359192f | 911 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
6aa8b732 AK |
912 | unsigned long sysenter_esp; |
913 | ||
a8eeb04a | 914 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be DX |
915 | local_irq_disable(); |
916 | list_add(&vmx->local_vcpus_link, | |
917 | &per_cpu(vcpus_on_cpu, cpu)); | |
918 | local_irq_enable(); | |
919 | ||
6aa8b732 AK |
920 | /* |
921 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
922 | * processors. | |
923 | */ | |
d6e88aec | 924 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 925 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
926 | |
927 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
928 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
929 | } | |
6aa8b732 AK |
930 | } |
931 | ||
932 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
933 | { | |
a9b21b62 | 934 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 935 | if (!vmm_exclusive) { |
b923e62e | 936 | __vcpu_clear(to_vmx(vcpu)); |
4610c9cc DX |
937 | kvm_cpu_vmxoff(); |
938 | } | |
6aa8b732 AK |
939 | } |
940 | ||
5fd86fcf AK |
941 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
942 | { | |
81231c69 AK |
943 | ulong cr0; |
944 | ||
5fd86fcf AK |
945 | if (vcpu->fpu_active) |
946 | return; | |
947 | vcpu->fpu_active = 1; | |
81231c69 AK |
948 | cr0 = vmcs_readl(GUEST_CR0); |
949 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
950 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
951 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 952 | update_exception_bitmap(vcpu); |
edcafe3c AK |
953 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
954 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
5fd86fcf AK |
955 | } |
956 | ||
edcafe3c AK |
957 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
958 | ||
5fd86fcf AK |
959 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
960 | { | |
edcafe3c | 961 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 962 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 963 | update_exception_bitmap(vcpu); |
edcafe3c AK |
964 | vcpu->arch.cr0_guest_owned_bits = 0; |
965 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
966 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
967 | } |
968 | ||
6aa8b732 AK |
969 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
970 | { | |
78ac8b47 | 971 | unsigned long rflags, save_rflags; |
345dcaa8 AK |
972 | |
973 | rflags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
974 | if (to_vmx(vcpu)->rmode.vm86_active) { |
975 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
976 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
977 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
978 | } | |
345dcaa8 | 979 | return rflags; |
6aa8b732 AK |
980 | } |
981 | ||
982 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
983 | { | |
78ac8b47 AK |
984 | if (to_vmx(vcpu)->rmode.vm86_active) { |
985 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 986 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 987 | } |
6aa8b732 AK |
988 | vmcs_writel(GUEST_RFLAGS, rflags); |
989 | } | |
990 | ||
2809f5d2 GC |
991 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
992 | { | |
993 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
994 | int ret = 0; | |
995 | ||
996 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 997 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 998 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 999 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
1000 | |
1001 | return ret & mask; | |
1002 | } | |
1003 | ||
1004 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
1005 | { | |
1006 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1007 | u32 interruptibility = interruptibility_old; | |
1008 | ||
1009 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
1010 | ||
48005f64 | 1011 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 1012 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 1013 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
1014 | interruptibility |= GUEST_INTR_STATE_STI; |
1015 | ||
1016 | if ((interruptibility != interruptibility_old)) | |
1017 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
1018 | } | |
1019 | ||
6aa8b732 AK |
1020 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
1021 | { | |
1022 | unsigned long rip; | |
6aa8b732 | 1023 | |
5fdbf976 | 1024 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 1025 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 1026 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 1027 | |
2809f5d2 GC |
1028 | /* skipping an emulated instruction also counts */ |
1029 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
1030 | } |
1031 | ||
443381a8 AL |
1032 | static void vmx_clear_hlt(struct kvm_vcpu *vcpu) |
1033 | { | |
1034 | /* Ensure that we clear the HLT state in the VMCS. We don't need to | |
1035 | * explicitly skip the instruction because if the HLT state is set, then | |
1036 | * the instruction is already executing and RIP has already been | |
1037 | * advanced. */ | |
1038 | if (!yield_on_hlt && | |
1039 | vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) | |
1040 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); | |
1041 | } | |
1042 | ||
298101da | 1043 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
1044 | bool has_error_code, u32 error_code, |
1045 | bool reinject) | |
298101da | 1046 | { |
77ab6db0 | 1047 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 1048 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 1049 | |
8ab2d2e2 | 1050 | if (has_error_code) { |
77ab6db0 | 1051 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
1052 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
1053 | } | |
77ab6db0 | 1054 | |
7ffd92c5 | 1055 | if (vmx->rmode.vm86_active) { |
a92601bb MG |
1056 | if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE) |
1057 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
77ab6db0 JK |
1058 | return; |
1059 | } | |
1060 | ||
66fd3f7f GN |
1061 | if (kvm_exception_is_soft(nr)) { |
1062 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
1063 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
1064 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
1065 | } else | |
1066 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
1067 | ||
1068 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
443381a8 | 1069 | vmx_clear_hlt(vcpu); |
298101da AK |
1070 | } |
1071 | ||
4e47c7a6 SY |
1072 | static bool vmx_rdtscp_supported(void) |
1073 | { | |
1074 | return cpu_has_vmx_rdtscp(); | |
1075 | } | |
1076 | ||
a75beee6 ED |
1077 | /* |
1078 | * Swap MSR entry in host/guest MSR entry array. | |
1079 | */ | |
8b9cf98c | 1080 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 1081 | { |
26bb0981 | 1082 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
1083 | |
1084 | tmp = vmx->guest_msrs[to]; | |
1085 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
1086 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
1087 | } |
1088 | ||
e38aea3e AK |
1089 | /* |
1090 | * Set up the vmcs to automatically save and restore system | |
1091 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
1092 | * mode, as fiddling with msrs is very expensive. | |
1093 | */ | |
8b9cf98c | 1094 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 1095 | { |
26bb0981 | 1096 | int save_nmsrs, index; |
5897297b | 1097 | unsigned long *msr_bitmap; |
e38aea3e | 1098 | |
33f9c505 | 1099 | vmx_load_host_state(vmx); |
a75beee6 ED |
1100 | save_nmsrs = 0; |
1101 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 1102 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 1103 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 1104 | if (index >= 0) |
8b9cf98c RR |
1105 | move_msr_up(vmx, index, save_nmsrs++); |
1106 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 1107 | if (index >= 0) |
8b9cf98c RR |
1108 | move_msr_up(vmx, index, save_nmsrs++); |
1109 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 1110 | if (index >= 0) |
8b9cf98c | 1111 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 SY |
1112 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1113 | if (index >= 0 && vmx->rdtscp_enabled) | |
1114 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 | 1115 | /* |
8c06585d | 1116 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
1117 | * if efer.sce is enabled. |
1118 | */ | |
8c06585d | 1119 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 1120 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 1121 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
1122 | } |
1123 | #endif | |
92c0d900 AK |
1124 | index = __find_msr_index(vmx, MSR_EFER); |
1125 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 1126 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 1127 | |
26bb0981 | 1128 | vmx->save_nmsrs = save_nmsrs; |
5897297b AK |
1129 | |
1130 | if (cpu_has_vmx_msr_bitmap()) { | |
1131 | if (is_long_mode(&vmx->vcpu)) | |
1132 | msr_bitmap = vmx_msr_bitmap_longmode; | |
1133 | else | |
1134 | msr_bitmap = vmx_msr_bitmap_legacy; | |
1135 | ||
1136 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
1137 | } | |
e38aea3e AK |
1138 | } |
1139 | ||
6aa8b732 AK |
1140 | /* |
1141 | * reads and returns guest's timestamp counter "register" | |
1142 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
1143 | */ | |
1144 | static u64 guest_read_tsc(void) | |
1145 | { | |
1146 | u64 host_tsc, tsc_offset; | |
1147 | ||
1148 | rdtscll(host_tsc); | |
1149 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
1150 | return host_tsc + tsc_offset; | |
1151 | } | |
1152 | ||
1153 | /* | |
99e3e30a | 1154 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 1155 | */ |
99e3e30a | 1156 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 1157 | { |
f4e1b3c8 | 1158 | vmcs_write64(TSC_OFFSET, offset); |
6aa8b732 AK |
1159 | } |
1160 | ||
e48672fa ZA |
1161 | static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
1162 | { | |
1163 | u64 offset = vmcs_read64(TSC_OFFSET); | |
1164 | vmcs_write64(TSC_OFFSET, offset + adjustment); | |
1165 | } | |
1166 | ||
6aa8b732 AK |
1167 | /* |
1168 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1169 | * Returns 0 on success, non-0 otherwise. | |
1170 | * Assumes vcpu_load() was already called. | |
1171 | */ | |
1172 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1173 | { | |
1174 | u64 data; | |
26bb0981 | 1175 | struct shared_msr_entry *msr; |
6aa8b732 AK |
1176 | |
1177 | if (!pdata) { | |
1178 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
1179 | return -EINVAL; | |
1180 | } | |
1181 | ||
1182 | switch (msr_index) { | |
05b3e0c2 | 1183 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1184 | case MSR_FS_BASE: |
1185 | data = vmcs_readl(GUEST_FS_BASE); | |
1186 | break; | |
1187 | case MSR_GS_BASE: | |
1188 | data = vmcs_readl(GUEST_GS_BASE); | |
1189 | break; | |
44ea2b17 AK |
1190 | case MSR_KERNEL_GS_BASE: |
1191 | vmx_load_host_state(to_vmx(vcpu)); | |
1192 | data = to_vmx(vcpu)->msr_guest_kernel_gs_base; | |
1193 | break; | |
26bb0981 | 1194 | #endif |
6aa8b732 | 1195 | case MSR_EFER: |
3bab1f5d | 1196 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
af24a4e4 | 1197 | case MSR_IA32_TSC: |
6aa8b732 AK |
1198 | data = guest_read_tsc(); |
1199 | break; | |
1200 | case MSR_IA32_SYSENTER_CS: | |
1201 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
1202 | break; | |
1203 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1204 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
1205 | break; |
1206 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1207 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 1208 | break; |
4e47c7a6 SY |
1209 | case MSR_TSC_AUX: |
1210 | if (!to_vmx(vcpu)->rdtscp_enabled) | |
1211 | return 1; | |
1212 | /* Otherwise falls through */ | |
6aa8b732 | 1213 | default: |
26bb0981 | 1214 | vmx_load_host_state(to_vmx(vcpu)); |
8b9cf98c | 1215 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d | 1216 | if (msr) { |
542423b0 | 1217 | vmx_load_host_state(to_vmx(vcpu)); |
3bab1f5d AK |
1218 | data = msr->data; |
1219 | break; | |
6aa8b732 | 1220 | } |
3bab1f5d | 1221 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
1222 | } |
1223 | ||
1224 | *pdata = data; | |
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | /* | |
1229 | * Writes msr value into into the appropriate "register". | |
1230 | * Returns 0 on success, non-0 otherwise. | |
1231 | * Assumes vcpu_load() was already called. | |
1232 | */ | |
1233 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
1234 | { | |
a2fa3e9f | 1235 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 1236 | struct shared_msr_entry *msr; |
2cc51560 ED |
1237 | int ret = 0; |
1238 | ||
6aa8b732 | 1239 | switch (msr_index) { |
3bab1f5d | 1240 | case MSR_EFER: |
a9b21b62 | 1241 | vmx_load_host_state(vmx); |
2cc51560 | 1242 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 1243 | break; |
16175a79 | 1244 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1245 | case MSR_FS_BASE: |
1246 | vmcs_writel(GUEST_FS_BASE, data); | |
1247 | break; | |
1248 | case MSR_GS_BASE: | |
1249 | vmcs_writel(GUEST_GS_BASE, data); | |
1250 | break; | |
44ea2b17 AK |
1251 | case MSR_KERNEL_GS_BASE: |
1252 | vmx_load_host_state(vmx); | |
1253 | vmx->msr_guest_kernel_gs_base = data; | |
1254 | break; | |
6aa8b732 AK |
1255 | #endif |
1256 | case MSR_IA32_SYSENTER_CS: | |
1257 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
1258 | break; | |
1259 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 1260 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
1261 | break; |
1262 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 1263 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 1264 | break; |
af24a4e4 | 1265 | case MSR_IA32_TSC: |
99e3e30a | 1266 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 1267 | break; |
468d472f SY |
1268 | case MSR_IA32_CR_PAT: |
1269 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
1270 | vmcs_write64(GUEST_IA32_PAT, data); | |
1271 | vcpu->arch.pat = data; | |
1272 | break; | |
1273 | } | |
4e47c7a6 SY |
1274 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
1275 | break; | |
1276 | case MSR_TSC_AUX: | |
1277 | if (!vmx->rdtscp_enabled) | |
1278 | return 1; | |
1279 | /* Check reserved bit, higher 32 bits should be zero */ | |
1280 | if ((data >> 32) != 0) | |
1281 | return 1; | |
1282 | /* Otherwise falls through */ | |
6aa8b732 | 1283 | default: |
8b9cf98c | 1284 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 1285 | if (msr) { |
542423b0 | 1286 | vmx_load_host_state(vmx); |
3bab1f5d AK |
1287 | msr->data = data; |
1288 | break; | |
6aa8b732 | 1289 | } |
2cc51560 | 1290 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
1291 | } |
1292 | ||
2cc51560 | 1293 | return ret; |
6aa8b732 AK |
1294 | } |
1295 | ||
5fdbf976 | 1296 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 1297 | { |
5fdbf976 MT |
1298 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
1299 | switch (reg) { | |
1300 | case VCPU_REGS_RSP: | |
1301 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
1302 | break; | |
1303 | case VCPU_REGS_RIP: | |
1304 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
1305 | break; | |
6de4f3ad AK |
1306 | case VCPU_EXREG_PDPTR: |
1307 | if (enable_ept) | |
1308 | ept_save_pdptrs(vcpu); | |
1309 | break; | |
5fdbf976 MT |
1310 | default: |
1311 | break; | |
1312 | } | |
6aa8b732 AK |
1313 | } |
1314 | ||
355be0b9 | 1315 | static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
6aa8b732 | 1316 | { |
ae675ef0 JK |
1317 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1318 | vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); | |
1319 | else | |
1320 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
1321 | ||
abd3f2d6 | 1322 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1323 | } |
1324 | ||
1325 | static __init int cpu_has_kvm_support(void) | |
1326 | { | |
6210e37b | 1327 | return cpu_has_vmx(); |
6aa8b732 AK |
1328 | } |
1329 | ||
1330 | static __init int vmx_disabled_by_bios(void) | |
1331 | { | |
1332 | u64 msr; | |
1333 | ||
1334 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 1335 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 1336 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
1337 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
1338 | && tboot_enabled()) | |
1339 | return 1; | |
23f3e991 | 1340 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 1341 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 1342 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
1343 | && !tboot_enabled()) { |
1344 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 1345 | "activate TXT before enabling KVM\n"); |
cafd6659 | 1346 | return 1; |
f9335afe | 1347 | } |
23f3e991 JC |
1348 | /* launched w/o TXT and VMX disabled */ |
1349 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
1350 | && !tboot_enabled()) | |
1351 | return 1; | |
cafd6659 SW |
1352 | } |
1353 | ||
1354 | return 0; | |
6aa8b732 AK |
1355 | } |
1356 | ||
7725b894 DX |
1357 | static void kvm_cpu_vmxon(u64 addr) |
1358 | { | |
1359 | asm volatile (ASM_VMX_VMXON_RAX | |
1360 | : : "a"(&addr), "m"(addr) | |
1361 | : "memory", "cc"); | |
1362 | } | |
1363 | ||
10474ae8 | 1364 | static int hardware_enable(void *garbage) |
6aa8b732 AK |
1365 | { |
1366 | int cpu = raw_smp_processor_id(); | |
1367 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 1368 | u64 old, test_bits; |
6aa8b732 | 1369 | |
10474ae8 AG |
1370 | if (read_cr4() & X86_CR4_VMXE) |
1371 | return -EBUSY; | |
1372 | ||
543e4243 | 1373 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1374 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
1375 | |
1376 | test_bits = FEATURE_CONTROL_LOCKED; | |
1377 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
1378 | if (tboot_enabled()) | |
1379 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
1380 | ||
1381 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 1382 | /* enable and lock */ |
cafd6659 SW |
1383 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
1384 | } | |
66aee91a | 1385 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
10474ae8 | 1386 | |
4610c9cc DX |
1387 | if (vmm_exclusive) { |
1388 | kvm_cpu_vmxon(phys_addr); | |
1389 | ept_sync_global(); | |
1390 | } | |
10474ae8 | 1391 | |
3444d7da AK |
1392 | store_gdt(&__get_cpu_var(host_gdt)); |
1393 | ||
10474ae8 | 1394 | return 0; |
6aa8b732 AK |
1395 | } |
1396 | ||
543e4243 AK |
1397 | static void vmclear_local_vcpus(void) |
1398 | { | |
1399 | int cpu = raw_smp_processor_id(); | |
1400 | struct vcpu_vmx *vmx, *n; | |
1401 | ||
1402 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1403 | local_vcpus_link) | |
1404 | __vcpu_clear(vmx); | |
1405 | } | |
1406 | ||
710ff4a8 EH |
1407 | |
1408 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
1409 | * tricks. | |
1410 | */ | |
1411 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 1412 | { |
4ecac3fd | 1413 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
6aa8b732 AK |
1414 | } |
1415 | ||
710ff4a8 EH |
1416 | static void hardware_disable(void *garbage) |
1417 | { | |
4610c9cc DX |
1418 | if (vmm_exclusive) { |
1419 | vmclear_local_vcpus(); | |
1420 | kvm_cpu_vmxoff(); | |
1421 | } | |
7725b894 | 1422 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
710ff4a8 EH |
1423 | } |
1424 | ||
1c3d14fe | 1425 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1426 | u32 msr, u32 *result) |
1c3d14fe YS |
1427 | { |
1428 | u32 vmx_msr_low, vmx_msr_high; | |
1429 | u32 ctl = ctl_min | ctl_opt; | |
1430 | ||
1431 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1432 | ||
1433 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1434 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1435 | ||
1436 | /* Ensure minimum (required) set of control bits are supported. */ | |
1437 | if (ctl_min & ~ctl) | |
002c7f7c | 1438 | return -EIO; |
1c3d14fe YS |
1439 | |
1440 | *result = ctl; | |
1441 | return 0; | |
1442 | } | |
1443 | ||
110312c8 AK |
1444 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
1445 | { | |
1446 | u32 vmx_msr_low, vmx_msr_high; | |
1447 | ||
1448 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1449 | return vmx_msr_high & ctl; | |
1450 | } | |
1451 | ||
002c7f7c | 1452 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1453 | { |
1454 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1455 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1456 | u32 _pin_based_exec_control = 0; |
1457 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1458 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1459 | u32 _vmexit_control = 0; |
1460 | u32 _vmentry_control = 0; | |
1461 | ||
1462 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1463 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1464 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1465 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1466 | return -EIO; |
1c3d14fe | 1467 | |
443381a8 | 1468 | min = |
1c3d14fe YS |
1469 | #ifdef CONFIG_X86_64 |
1470 | CPU_BASED_CR8_LOAD_EXITING | | |
1471 | CPU_BASED_CR8_STORE_EXITING | | |
1472 | #endif | |
d56f546d SY |
1473 | CPU_BASED_CR3_LOAD_EXITING | |
1474 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1475 | CPU_BASED_USE_IO_BITMAPS | |
1476 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 1477 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
1478 | CPU_BASED_MWAIT_EXITING | |
1479 | CPU_BASED_MONITOR_EXITING | | |
a7052897 | 1480 | CPU_BASED_INVLPG_EXITING; |
443381a8 AL |
1481 | |
1482 | if (yield_on_hlt) | |
1483 | min |= CPU_BASED_HLT_EXITING; | |
1484 | ||
f78e0e2e | 1485 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1486 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1487 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1488 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1489 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1490 | return -EIO; |
6e5d865c YS |
1491 | #ifdef CONFIG_X86_64 |
1492 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1493 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1494 | ~CPU_BASED_CR8_STORE_EXITING; | |
1495 | #endif | |
f78e0e2e | 1496 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1497 | min2 = 0; |
1498 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1499 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 1500 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 1501 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 1502 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 SY |
1503 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
1504 | SECONDARY_EXEC_RDTSCP; | |
d56f546d SY |
1505 | if (adjust_vmx_controls(min2, opt2, |
1506 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1507 | &_cpu_based_2nd_exec_control) < 0) |
1508 | return -EIO; | |
1509 | } | |
1510 | #ifndef CONFIG_X86_64 | |
1511 | if (!(_cpu_based_2nd_exec_control & | |
1512 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1513 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1514 | #endif | |
d56f546d | 1515 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
1516 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
1517 | enabled */ | |
5fff7d27 GN |
1518 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
1519 | CPU_BASED_CR3_STORE_EXITING | | |
1520 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
1521 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
1522 | vmx_capability.ept, vmx_capability.vpid); | |
1523 | } | |
1c3d14fe YS |
1524 | |
1525 | min = 0; | |
1526 | #ifdef CONFIG_X86_64 | |
1527 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1528 | #endif | |
468d472f | 1529 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
1530 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
1531 | &_vmexit_control) < 0) | |
002c7f7c | 1532 | return -EIO; |
1c3d14fe | 1533 | |
468d472f SY |
1534 | min = 0; |
1535 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
1536 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
1537 | &_vmentry_control) < 0) | |
002c7f7c | 1538 | return -EIO; |
6aa8b732 | 1539 | |
c68876fd | 1540 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1541 | |
1542 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1543 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1544 | return -EIO; |
1c3d14fe YS |
1545 | |
1546 | #ifdef CONFIG_X86_64 | |
1547 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1548 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1549 | return -EIO; |
1c3d14fe YS |
1550 | #endif |
1551 | ||
1552 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1553 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1554 | return -EIO; |
1c3d14fe | 1555 | |
002c7f7c YS |
1556 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1557 | vmcs_conf->order = get_order(vmcs_config.size); | |
1558 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1559 | |
002c7f7c YS |
1560 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1561 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1562 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1563 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1564 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 1565 | |
110312c8 AK |
1566 | cpu_has_load_ia32_efer = |
1567 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
1568 | VM_ENTRY_LOAD_IA32_EFER) | |
1569 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
1570 | VM_EXIT_LOAD_IA32_EFER); | |
1571 | ||
1c3d14fe | 1572 | return 0; |
c68876fd | 1573 | } |
6aa8b732 AK |
1574 | |
1575 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1576 | { | |
1577 | int node = cpu_to_node(cpu); | |
1578 | struct page *pages; | |
1579 | struct vmcs *vmcs; | |
1580 | ||
6484eb3e | 1581 | pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1582 | if (!pages) |
1583 | return NULL; | |
1584 | vmcs = page_address(pages); | |
1c3d14fe YS |
1585 | memset(vmcs, 0, vmcs_config.size); |
1586 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1587 | return vmcs; |
1588 | } | |
1589 | ||
1590 | static struct vmcs *alloc_vmcs(void) | |
1591 | { | |
d3b2c338 | 1592 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1593 | } |
1594 | ||
1595 | static void free_vmcs(struct vmcs *vmcs) | |
1596 | { | |
1c3d14fe | 1597 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1598 | } |
1599 | ||
39959588 | 1600 | static void free_kvm_area(void) |
6aa8b732 AK |
1601 | { |
1602 | int cpu; | |
1603 | ||
3230bb47 | 1604 | for_each_possible_cpu(cpu) { |
6aa8b732 | 1605 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
1606 | per_cpu(vmxarea, cpu) = NULL; |
1607 | } | |
6aa8b732 AK |
1608 | } |
1609 | ||
6aa8b732 AK |
1610 | static __init int alloc_kvm_area(void) |
1611 | { | |
1612 | int cpu; | |
1613 | ||
3230bb47 | 1614 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
1615 | struct vmcs *vmcs; |
1616 | ||
1617 | vmcs = alloc_vmcs_cpu(cpu); | |
1618 | if (!vmcs) { | |
1619 | free_kvm_area(); | |
1620 | return -ENOMEM; | |
1621 | } | |
1622 | ||
1623 | per_cpu(vmxarea, cpu) = vmcs; | |
1624 | } | |
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | static __init int hardware_setup(void) | |
1629 | { | |
002c7f7c YS |
1630 | if (setup_vmcs_config(&vmcs_config) < 0) |
1631 | return -EIO; | |
50a37eb4 JR |
1632 | |
1633 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1634 | kvm_enable_efer_bits(EFER_NX); | |
1635 | ||
93ba03c2 SY |
1636 | if (!cpu_has_vmx_vpid()) |
1637 | enable_vpid = 0; | |
1638 | ||
4bc9b982 SY |
1639 | if (!cpu_has_vmx_ept() || |
1640 | !cpu_has_vmx_ept_4levels()) { | |
93ba03c2 | 1641 | enable_ept = 0; |
3a624e29 NK |
1642 | enable_unrestricted_guest = 0; |
1643 | } | |
1644 | ||
1645 | if (!cpu_has_vmx_unrestricted_guest()) | |
1646 | enable_unrestricted_guest = 0; | |
93ba03c2 SY |
1647 | |
1648 | if (!cpu_has_vmx_flexpriority()) | |
1649 | flexpriority_enabled = 0; | |
1650 | ||
95ba8273 GN |
1651 | if (!cpu_has_vmx_tpr_shadow()) |
1652 | kvm_x86_ops->update_cr8_intercept = NULL; | |
1653 | ||
54dee993 MT |
1654 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) |
1655 | kvm_disable_largepages(); | |
1656 | ||
4b8d54f9 ZE |
1657 | if (!cpu_has_vmx_ple()) |
1658 | ple_gap = 0; | |
1659 | ||
6aa8b732 AK |
1660 | return alloc_kvm_area(); |
1661 | } | |
1662 | ||
1663 | static __exit void hardware_unsetup(void) | |
1664 | { | |
1665 | free_kvm_area(); | |
1666 | } | |
1667 | ||
6aa8b732 AK |
1668 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1669 | { | |
1670 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1671 | ||
6af11b9e | 1672 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1673 | vmcs_write16(sf->selector, save->selector); |
1674 | vmcs_writel(sf->base, save->base); | |
1675 | vmcs_write32(sf->limit, save->limit); | |
1676 | vmcs_write32(sf->ar_bytes, save->ar); | |
1677 | } else { | |
1678 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1679 | << AR_DPL_SHIFT; | |
1680 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1685 | { | |
1686 | unsigned long flags; | |
a89a8fb9 | 1687 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1688 | |
a89a8fb9 | 1689 | vmx->emulation_required = 1; |
7ffd92c5 | 1690 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 1691 | |
d0ba64f9 | 1692 | vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector); |
7ffd92c5 AK |
1693 | vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base); |
1694 | vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit); | |
1695 | vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar); | |
6aa8b732 AK |
1696 | |
1697 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
1698 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
1699 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
1700 | vmcs_writel(GUEST_RFLAGS, flags); |
1701 | ||
66aee91a RR |
1702 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1703 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1704 | |
1705 | update_exception_bitmap(vcpu); | |
1706 | ||
a89a8fb9 MG |
1707 | if (emulate_invalid_guest_state) |
1708 | return; | |
1709 | ||
7ffd92c5 AK |
1710 | fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es); |
1711 | fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds); | |
1712 | fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs); | |
1713 | fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs); | |
6aa8b732 AK |
1714 | |
1715 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1716 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1717 | ||
1718 | vmcs_write16(GUEST_CS_SELECTOR, | |
1719 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1720 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1721 | } | |
1722 | ||
d77c26fc | 1723 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1724 | { |
bfc6d222 | 1725 | if (!kvm->arch.tss_addr) { |
bc6678a3 MT |
1726 | struct kvm_memslots *slots; |
1727 | gfn_t base_gfn; | |
1728 | ||
90d83dc3 | 1729 | slots = kvm_memslots(kvm); |
f495c6e5 | 1730 | base_gfn = slots->memslots[0].base_gfn + |
46a26bf5 | 1731 | kvm->memslots->memslots[0].npages - 3; |
cbc94022 IE |
1732 | return base_gfn << PAGE_SHIFT; |
1733 | } | |
bfc6d222 | 1734 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1735 | } |
1736 | ||
1737 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1738 | { | |
1739 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1740 | ||
1741 | save->selector = vmcs_read16(sf->selector); | |
1742 | save->base = vmcs_readl(sf->base); | |
1743 | save->limit = vmcs_read32(sf->limit); | |
1744 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 | 1745 | vmcs_write16(sf->selector, save->base >> 4); |
444e863d | 1746 | vmcs_write32(sf->base, save->base & 0xffff0); |
6aa8b732 AK |
1747 | vmcs_write32(sf->limit, 0xffff); |
1748 | vmcs_write32(sf->ar_bytes, 0xf3); | |
444e863d GN |
1749 | if (save->base & 0xf) |
1750 | printk_once(KERN_WARNING "kvm: segment base is not paragraph" | |
1751 | " aligned when entering protected mode (seg=%d)", | |
1752 | seg); | |
6aa8b732 AK |
1753 | } |
1754 | ||
1755 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1756 | { | |
1757 | unsigned long flags; | |
a89a8fb9 | 1758 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 1759 | |
3a624e29 NK |
1760 | if (enable_unrestricted_guest) |
1761 | return; | |
1762 | ||
a89a8fb9 | 1763 | vmx->emulation_required = 1; |
7ffd92c5 | 1764 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 1765 | |
776e58ea GN |
1766 | /* |
1767 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
1768 | * vcpu. Call it here with phys address pointing 16M below 4G. | |
1769 | */ | |
1770 | if (!vcpu->kvm->arch.tss_addr) { | |
1771 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " | |
1772 | "called before entering vcpu\n"); | |
1773 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
1774 | vmx_set_tss_addr(vcpu->kvm, 0xfeffd000); | |
1775 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
1776 | } | |
1777 | ||
d0ba64f9 | 1778 | vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR); |
7ffd92c5 | 1779 | vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1780 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1781 | ||
7ffd92c5 | 1782 | vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1783 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1784 | ||
7ffd92c5 | 1785 | vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1786 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1787 | ||
1788 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 1789 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 1790 | |
053de044 | 1791 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1792 | |
1793 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1794 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1795 | update_exception_bitmap(vcpu); |
1796 | ||
a89a8fb9 MG |
1797 | if (emulate_invalid_guest_state) |
1798 | goto continue_rmode; | |
1799 | ||
6aa8b732 AK |
1800 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
1801 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1802 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1803 | ||
1804 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1805 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1806 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1807 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1808 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1809 | ||
7ffd92c5 AK |
1810 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es); |
1811 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds); | |
1812 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs); | |
1813 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs); | |
75880a01 | 1814 | |
a89a8fb9 | 1815 | continue_rmode: |
8668a3c4 | 1816 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
1817 | } |
1818 | ||
401d10de AS |
1819 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1820 | { | |
1821 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
1822 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
1823 | ||
1824 | if (!msr) | |
1825 | return; | |
401d10de | 1826 | |
44ea2b17 AK |
1827 | /* |
1828 | * Force kernel_gs_base reloading before EFER changes, as control | |
1829 | * of this msr depends on is_long_mode(). | |
1830 | */ | |
1831 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 1832 | vcpu->arch.efer = efer; |
401d10de AS |
1833 | if (efer & EFER_LMA) { |
1834 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1835 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1836 | VM_ENTRY_IA32E_MODE); | |
1837 | msr->data = efer; | |
1838 | } else { | |
1839 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1840 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1841 | ~VM_ENTRY_IA32E_MODE); | |
1842 | ||
1843 | msr->data = efer & ~EFER_LME; | |
1844 | } | |
1845 | setup_msrs(vmx); | |
1846 | } | |
1847 | ||
05b3e0c2 | 1848 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1849 | |
1850 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1851 | { | |
1852 | u32 guest_tr_ar; | |
1853 | ||
1854 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1855 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1856 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1857 | __func__); |
6aa8b732 AK |
1858 | vmcs_write32(GUEST_TR_AR_BYTES, |
1859 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1860 | | AR_TYPE_BUSY_64_TSS); | |
1861 | } | |
da38f438 | 1862 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
1863 | } |
1864 | ||
1865 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1866 | { | |
6aa8b732 AK |
1867 | vmcs_write32(VM_ENTRY_CONTROLS, |
1868 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1869 | & ~VM_ENTRY_IA32E_MODE); |
da38f438 | 1870 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
1871 | } |
1872 | ||
1873 | #endif | |
1874 | ||
2384d2b3 SY |
1875 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1876 | { | |
b9d762fa | 1877 | vpid_sync_context(to_vmx(vcpu)); |
dd180b3e XG |
1878 | if (enable_ept) { |
1879 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
1880 | return; | |
4e1096d2 | 1881 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 1882 | } |
2384d2b3 SY |
1883 | } |
1884 | ||
e8467fda AK |
1885 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1886 | { | |
1887 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
1888 | ||
1889 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
1890 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
1891 | } | |
1892 | ||
aff48baa AK |
1893 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
1894 | { | |
1895 | if (enable_ept && is_paging(vcpu)) | |
1896 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
1897 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
1898 | } | |
1899 | ||
25c4c276 | 1900 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1901 | { |
fc78f519 AK |
1902 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
1903 | ||
1904 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
1905 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
1906 | } |
1907 | ||
1439442c SY |
1908 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1909 | { | |
6de4f3ad AK |
1910 | if (!test_bit(VCPU_EXREG_PDPTR, |
1911 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
1912 | return; | |
1913 | ||
1439442c | 1914 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
ff03a073 JR |
1915 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]); |
1916 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]); | |
1917 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]); | |
1918 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]); | |
1439442c SY |
1919 | } |
1920 | } | |
1921 | ||
8f5d549f AK |
1922 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
1923 | { | |
1924 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
ff03a073 JR |
1925 | vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
1926 | vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
1927 | vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
1928 | vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 1929 | } |
6de4f3ad AK |
1930 | |
1931 | __set_bit(VCPU_EXREG_PDPTR, | |
1932 | (unsigned long *)&vcpu->arch.regs_avail); | |
1933 | __set_bit(VCPU_EXREG_PDPTR, | |
1934 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
1935 | } |
1936 | ||
1439442c SY |
1937 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1938 | ||
1939 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1940 | unsigned long cr0, | |
1941 | struct kvm_vcpu *vcpu) | |
1942 | { | |
aff48baa | 1943 | vmx_decache_cr3(vcpu); |
1439442c SY |
1944 | if (!(cr0 & X86_CR0_PG)) { |
1945 | /* From paging/starting to nonpaging */ | |
1946 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1947 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1948 | (CPU_BASED_CR3_LOAD_EXITING | |
1949 | CPU_BASED_CR3_STORE_EXITING)); | |
1950 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 1951 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
1952 | } else if (!is_paging(vcpu)) { |
1953 | /* From nonpaging to paging */ | |
1954 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1955 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1956 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1957 | CPU_BASED_CR3_STORE_EXITING)); | |
1958 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 1959 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 1960 | } |
95eb84a7 SY |
1961 | |
1962 | if (!(cr0 & X86_CR0_WP)) | |
1963 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
1964 | } |
1965 | ||
6aa8b732 AK |
1966 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1967 | { | |
7ffd92c5 | 1968 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
1969 | unsigned long hw_cr0; |
1970 | ||
1971 | if (enable_unrestricted_guest) | |
1972 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST) | |
1973 | | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; | |
1974 | else | |
1975 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON; | |
1439442c | 1976 | |
7ffd92c5 | 1977 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1978 | enter_pmode(vcpu); |
1979 | ||
7ffd92c5 | 1980 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1981 | enter_rmode(vcpu); |
1982 | ||
05b3e0c2 | 1983 | #ifdef CONFIG_X86_64 |
f6801dff | 1984 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1985 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1986 | enter_lmode(vcpu); |
707d92fa | 1987 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1988 | exit_lmode(vcpu); |
1989 | } | |
1990 | #endif | |
1991 | ||
089d034e | 1992 | if (enable_ept) |
1439442c SY |
1993 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
1994 | ||
02daab21 | 1995 | if (!vcpu->fpu_active) |
81231c69 | 1996 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 1997 | |
6aa8b732 | 1998 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1999 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 2000 | vcpu->arch.cr0 = cr0; |
6aa8b732 AK |
2001 | } |
2002 | ||
1439442c SY |
2003 | static u64 construct_eptp(unsigned long root_hpa) |
2004 | { | |
2005 | u64 eptp; | |
2006 | ||
2007 | /* TODO write the value reading from MSR */ | |
2008 | eptp = VMX_EPT_DEFAULT_MT | | |
2009 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
2010 | eptp |= (root_hpa & PAGE_MASK); | |
2011 | ||
2012 | return eptp; | |
2013 | } | |
2014 | ||
6aa8b732 AK |
2015 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
2016 | { | |
1439442c SY |
2017 | unsigned long guest_cr3; |
2018 | u64 eptp; | |
2019 | ||
2020 | guest_cr3 = cr3; | |
089d034e | 2021 | if (enable_ept) { |
1439442c SY |
2022 | eptp = construct_eptp(cr3); |
2023 | vmcs_write64(EPT_POINTER, eptp); | |
9f8fe504 | 2024 | guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) : |
b927a3ce | 2025 | vcpu->kvm->arch.ept_identity_map_addr; |
7c93be44 | 2026 | ept_load_pdptrs(vcpu); |
1439442c SY |
2027 | } |
2028 | ||
2384d2b3 | 2029 | vmx_flush_tlb(vcpu); |
1439442c | 2030 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
2031 | } |
2032 | ||
2033 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
2034 | { | |
7ffd92c5 | 2035 | unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
1439442c SY |
2036 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
2037 | ||
ad312c7c | 2038 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
2039 | if (enable_ept) { |
2040 | if (!is_paging(vcpu)) { | |
2041 | hw_cr4 &= ~X86_CR4_PAE; | |
2042 | hw_cr4 |= X86_CR4_PSE; | |
2043 | } else if (!(cr4 & X86_CR4_PAE)) { | |
2044 | hw_cr4 &= ~X86_CR4_PAE; | |
2045 | } | |
2046 | } | |
1439442c SY |
2047 | |
2048 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
2049 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
2050 | } |
2051 | ||
6aa8b732 AK |
2052 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
2053 | struct kvm_segment *var, int seg) | |
2054 | { | |
a9179499 | 2055 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2056 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
a9179499 | 2057 | struct kvm_save_segment *save; |
6aa8b732 AK |
2058 | u32 ar; |
2059 | ||
a9179499 AK |
2060 | if (vmx->rmode.vm86_active |
2061 | && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES | |
2062 | || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS | |
2063 | || seg == VCPU_SREG_GS) | |
2064 | && !emulate_invalid_guest_state) { | |
2065 | switch (seg) { | |
2066 | case VCPU_SREG_TR: save = &vmx->rmode.tr; break; | |
2067 | case VCPU_SREG_ES: save = &vmx->rmode.es; break; | |
2068 | case VCPU_SREG_DS: save = &vmx->rmode.ds; break; | |
2069 | case VCPU_SREG_FS: save = &vmx->rmode.fs; break; | |
2070 | case VCPU_SREG_GS: save = &vmx->rmode.gs; break; | |
2071 | default: BUG(); | |
2072 | } | |
2073 | var->selector = save->selector; | |
2074 | var->base = save->base; | |
2075 | var->limit = save->limit; | |
2076 | ar = save->ar; | |
2077 | if (seg == VCPU_SREG_TR | |
2078 | || var->selector == vmcs_read16(sf->selector)) | |
2079 | goto use_saved_rmode_seg; | |
2080 | } | |
6aa8b732 AK |
2081 | var->base = vmcs_readl(sf->base); |
2082 | var->limit = vmcs_read32(sf->limit); | |
2083 | var->selector = vmcs_read16(sf->selector); | |
2084 | ar = vmcs_read32(sf->ar_bytes); | |
a9179499 | 2085 | use_saved_rmode_seg: |
9fd4a3b7 | 2086 | if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
6aa8b732 AK |
2087 | ar = 0; |
2088 | var->type = ar & 15; | |
2089 | var->s = (ar >> 4) & 1; | |
2090 | var->dpl = (ar >> 5) & 3; | |
2091 | var->present = (ar >> 7) & 1; | |
2092 | var->avl = (ar >> 12) & 1; | |
2093 | var->l = (ar >> 13) & 1; | |
2094 | var->db = (ar >> 14) & 1; | |
2095 | var->g = (ar >> 15) & 1; | |
2096 | var->unusable = (ar >> 16) & 1; | |
2097 | } | |
2098 | ||
a9179499 AK |
2099 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
2100 | { | |
2101 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2102 | struct kvm_segment s; | |
2103 | ||
2104 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
2105 | vmx_get_segment(vcpu, &s, seg); | |
2106 | return s.base; | |
2107 | } | |
2108 | return vmcs_readl(sf->base); | |
2109 | } | |
2110 | ||
2e4d2653 IE |
2111 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2112 | { | |
3eeb3288 | 2113 | if (!is_protmode(vcpu)) |
2e4d2653 IE |
2114 | return 0; |
2115 | ||
2116 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
2117 | return 3; | |
2118 | ||
eab4b8aa | 2119 | return vmcs_read16(GUEST_CS_SELECTOR) & 3; |
2e4d2653 IE |
2120 | } |
2121 | ||
653e3108 | 2122 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 2123 | { |
6aa8b732 AK |
2124 | u32 ar; |
2125 | ||
653e3108 | 2126 | if (var->unusable) |
6aa8b732 AK |
2127 | ar = 1 << 16; |
2128 | else { | |
2129 | ar = var->type & 15; | |
2130 | ar |= (var->s & 1) << 4; | |
2131 | ar |= (var->dpl & 3) << 5; | |
2132 | ar |= (var->present & 1) << 7; | |
2133 | ar |= (var->avl & 1) << 12; | |
2134 | ar |= (var->l & 1) << 13; | |
2135 | ar |= (var->db & 1) << 14; | |
2136 | ar |= (var->g & 1) << 15; | |
2137 | } | |
f7fbf1fd UL |
2138 | if (ar == 0) /* a 0 value means unusable */ |
2139 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
2140 | |
2141 | return ar; | |
2142 | } | |
2143 | ||
2144 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
2145 | struct kvm_segment *var, int seg) | |
2146 | { | |
7ffd92c5 | 2147 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
653e3108 AK |
2148 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
2149 | u32 ar; | |
2150 | ||
7ffd92c5 | 2151 | if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) { |
a8ba6c26 | 2152 | vmcs_write16(sf->selector, var->selector); |
7ffd92c5 AK |
2153 | vmx->rmode.tr.selector = var->selector; |
2154 | vmx->rmode.tr.base = var->base; | |
2155 | vmx->rmode.tr.limit = var->limit; | |
2156 | vmx->rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
2157 | return; |
2158 | } | |
2159 | vmcs_writel(sf->base, var->base); | |
2160 | vmcs_write32(sf->limit, var->limit); | |
2161 | vmcs_write16(sf->selector, var->selector); | |
7ffd92c5 | 2162 | if (vmx->rmode.vm86_active && var->s) { |
653e3108 AK |
2163 | /* |
2164 | * Hack real-mode segments into vm86 compatibility. | |
2165 | */ | |
2166 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
2167 | vmcs_writel(sf->base, 0xf0000); | |
2168 | ar = 0xf3; | |
2169 | } else | |
2170 | ar = vmx_segment_access_rights(var); | |
3a624e29 NK |
2171 | |
2172 | /* | |
2173 | * Fix the "Accessed" bit in AR field of segment registers for older | |
2174 | * qemu binaries. | |
2175 | * IA32 arch specifies that at the time of processor reset the | |
2176 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
2177 | * is setting it to 0 in the usedland code. This causes invalid guest | |
2178 | * state vmexit when "unrestricted guest" mode is turned on. | |
2179 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
2180 | * tree. Newer qemu binaries with that qemu fix would not need this | |
2181 | * kvm hack. | |
2182 | */ | |
2183 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
2184 | ar |= 0x1; /* Accessed */ | |
2185 | ||
6aa8b732 AK |
2186 | vmcs_write32(sf->ar_bytes, ar); |
2187 | } | |
2188 | ||
6aa8b732 AK |
2189 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
2190 | { | |
2191 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
2192 | ||
2193 | *db = (ar >> 14) & 1; | |
2194 | *l = (ar >> 13) & 1; | |
2195 | } | |
2196 | ||
89a27f4d | 2197 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2198 | { |
89a27f4d GN |
2199 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
2200 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
2201 | } |
2202 | ||
89a27f4d | 2203 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2204 | { |
89a27f4d GN |
2205 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
2206 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
2207 | } |
2208 | ||
89a27f4d | 2209 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2210 | { |
89a27f4d GN |
2211 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
2212 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
2213 | } |
2214 | ||
89a27f4d | 2215 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 2216 | { |
89a27f4d GN |
2217 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
2218 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
2219 | } |
2220 | ||
648dfaa7 MG |
2221 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
2222 | { | |
2223 | struct kvm_segment var; | |
2224 | u32 ar; | |
2225 | ||
2226 | vmx_get_segment(vcpu, &var, seg); | |
2227 | ar = vmx_segment_access_rights(&var); | |
2228 | ||
2229 | if (var.base != (var.selector << 4)) | |
2230 | return false; | |
2231 | if (var.limit != 0xffff) | |
2232 | return false; | |
2233 | if (ar != 0xf3) | |
2234 | return false; | |
2235 | ||
2236 | return true; | |
2237 | } | |
2238 | ||
2239 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
2240 | { | |
2241 | struct kvm_segment cs; | |
2242 | unsigned int cs_rpl; | |
2243 | ||
2244 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2245 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
2246 | ||
1872a3f4 AK |
2247 | if (cs.unusable) |
2248 | return false; | |
648dfaa7 MG |
2249 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
2250 | return false; | |
2251 | if (!cs.s) | |
2252 | return false; | |
1872a3f4 | 2253 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
2254 | if (cs.dpl > cs_rpl) |
2255 | return false; | |
1872a3f4 | 2256 | } else { |
648dfaa7 MG |
2257 | if (cs.dpl != cs_rpl) |
2258 | return false; | |
2259 | } | |
2260 | if (!cs.present) | |
2261 | return false; | |
2262 | ||
2263 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
2264 | return true; | |
2265 | } | |
2266 | ||
2267 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
2268 | { | |
2269 | struct kvm_segment ss; | |
2270 | unsigned int ss_rpl; | |
2271 | ||
2272 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2273 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
2274 | ||
1872a3f4 AK |
2275 | if (ss.unusable) |
2276 | return true; | |
2277 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
2278 | return false; |
2279 | if (!ss.s) | |
2280 | return false; | |
2281 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
2282 | return false; | |
2283 | if (!ss.present) | |
2284 | return false; | |
2285 | ||
2286 | return true; | |
2287 | } | |
2288 | ||
2289 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
2290 | { | |
2291 | struct kvm_segment var; | |
2292 | unsigned int rpl; | |
2293 | ||
2294 | vmx_get_segment(vcpu, &var, seg); | |
2295 | rpl = var.selector & SELECTOR_RPL_MASK; | |
2296 | ||
1872a3f4 AK |
2297 | if (var.unusable) |
2298 | return true; | |
648dfaa7 MG |
2299 | if (!var.s) |
2300 | return false; | |
2301 | if (!var.present) | |
2302 | return false; | |
2303 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
2304 | if (var.dpl < rpl) /* DPL < RPL */ | |
2305 | return false; | |
2306 | } | |
2307 | ||
2308 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
2309 | * rights flags | |
2310 | */ | |
2311 | return true; | |
2312 | } | |
2313 | ||
2314 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
2315 | { | |
2316 | struct kvm_segment tr; | |
2317 | ||
2318 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
2319 | ||
1872a3f4 AK |
2320 | if (tr.unusable) |
2321 | return false; | |
648dfaa7 MG |
2322 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2323 | return false; | |
1872a3f4 | 2324 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
2325 | return false; |
2326 | if (!tr.present) | |
2327 | return false; | |
2328 | ||
2329 | return true; | |
2330 | } | |
2331 | ||
2332 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
2333 | { | |
2334 | struct kvm_segment ldtr; | |
2335 | ||
2336 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
2337 | ||
1872a3f4 AK |
2338 | if (ldtr.unusable) |
2339 | return true; | |
648dfaa7 MG |
2340 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
2341 | return false; | |
2342 | if (ldtr.type != 2) | |
2343 | return false; | |
2344 | if (!ldtr.present) | |
2345 | return false; | |
2346 | ||
2347 | return true; | |
2348 | } | |
2349 | ||
2350 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
2351 | { | |
2352 | struct kvm_segment cs, ss; | |
2353 | ||
2354 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
2355 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
2356 | ||
2357 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
2358 | (ss.selector & SELECTOR_RPL_MASK)); | |
2359 | } | |
2360 | ||
2361 | /* | |
2362 | * Check if guest state is valid. Returns true if valid, false if | |
2363 | * not. | |
2364 | * We assume that registers are always usable | |
2365 | */ | |
2366 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
2367 | { | |
2368 | /* real mode guest state checks */ | |
3eeb3288 | 2369 | if (!is_protmode(vcpu)) { |
648dfaa7 MG |
2370 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
2371 | return false; | |
2372 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
2373 | return false; | |
2374 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
2375 | return false; | |
2376 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
2377 | return false; | |
2378 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
2379 | return false; | |
2380 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
2381 | return false; | |
2382 | } else { | |
2383 | /* protected mode guest state checks */ | |
2384 | if (!cs_ss_rpl_check(vcpu)) | |
2385 | return false; | |
2386 | if (!code_segment_valid(vcpu)) | |
2387 | return false; | |
2388 | if (!stack_segment_valid(vcpu)) | |
2389 | return false; | |
2390 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
2391 | return false; | |
2392 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
2393 | return false; | |
2394 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
2395 | return false; | |
2396 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
2397 | return false; | |
2398 | if (!tr_valid(vcpu)) | |
2399 | return false; | |
2400 | if (!ldtr_valid(vcpu)) | |
2401 | return false; | |
2402 | } | |
2403 | /* TODO: | |
2404 | * - Add checks on RIP | |
2405 | * - Add checks on RFLAGS | |
2406 | */ | |
2407 | ||
2408 | return true; | |
2409 | } | |
2410 | ||
d77c26fc | 2411 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 2412 | { |
40dcaa9f | 2413 | gfn_t fn; |
195aefde | 2414 | u16 data = 0; |
40dcaa9f | 2415 | int r, idx, ret = 0; |
6aa8b732 | 2416 | |
40dcaa9f XG |
2417 | idx = srcu_read_lock(&kvm->srcu); |
2418 | fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
195aefde IE |
2419 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2420 | if (r < 0) | |
10589a46 | 2421 | goto out; |
195aefde | 2422 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
2423 | r = kvm_write_guest_page(kvm, fn++, &data, |
2424 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 2425 | if (r < 0) |
10589a46 | 2426 | goto out; |
195aefde IE |
2427 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
2428 | if (r < 0) | |
10589a46 | 2429 | goto out; |
195aefde IE |
2430 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
2431 | if (r < 0) | |
10589a46 | 2432 | goto out; |
195aefde | 2433 | data = ~0; |
10589a46 MT |
2434 | r = kvm_write_guest_page(kvm, fn, &data, |
2435 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
2436 | sizeof(u8)); | |
195aefde | 2437 | if (r < 0) |
10589a46 MT |
2438 | goto out; |
2439 | ||
2440 | ret = 1; | |
2441 | out: | |
40dcaa9f | 2442 | srcu_read_unlock(&kvm->srcu, idx); |
10589a46 | 2443 | return ret; |
6aa8b732 AK |
2444 | } |
2445 | ||
b7ebfb05 SY |
2446 | static int init_rmode_identity_map(struct kvm *kvm) |
2447 | { | |
40dcaa9f | 2448 | int i, idx, r, ret; |
b7ebfb05 SY |
2449 | pfn_t identity_map_pfn; |
2450 | u32 tmp; | |
2451 | ||
089d034e | 2452 | if (!enable_ept) |
b7ebfb05 SY |
2453 | return 1; |
2454 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
2455 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
2456 | "haven't been allocated!\n"); | |
2457 | return 0; | |
2458 | } | |
2459 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
2460 | return 1; | |
2461 | ret = 0; | |
b927a3ce | 2462 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
40dcaa9f | 2463 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
2464 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
2465 | if (r < 0) | |
2466 | goto out; | |
2467 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
2468 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
2469 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
2470 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
2471 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
2472 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
2473 | if (r < 0) | |
2474 | goto out; | |
2475 | } | |
2476 | kvm->arch.ept_identity_pagetable_done = true; | |
2477 | ret = 1; | |
2478 | out: | |
40dcaa9f | 2479 | srcu_read_unlock(&kvm->srcu, idx); |
b7ebfb05 SY |
2480 | return ret; |
2481 | } | |
2482 | ||
6aa8b732 AK |
2483 | static void seg_setup(int seg) |
2484 | { | |
2485 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
3a624e29 | 2486 | unsigned int ar; |
6aa8b732 AK |
2487 | |
2488 | vmcs_write16(sf->selector, 0); | |
2489 | vmcs_writel(sf->base, 0); | |
2490 | vmcs_write32(sf->limit, 0xffff); | |
3a624e29 NK |
2491 | if (enable_unrestricted_guest) { |
2492 | ar = 0x93; | |
2493 | if (seg == VCPU_SREG_CS) | |
2494 | ar |= 0x08; /* code segment */ | |
2495 | } else | |
2496 | ar = 0xf3; | |
2497 | ||
2498 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
2499 | } |
2500 | ||
f78e0e2e SY |
2501 | static int alloc_apic_access_page(struct kvm *kvm) |
2502 | { | |
2503 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2504 | int r = 0; | |
2505 | ||
79fac95e | 2506 | mutex_lock(&kvm->slots_lock); |
bfc6d222 | 2507 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
2508 | goto out; |
2509 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
2510 | kvm_userspace_mem.flags = 0; | |
2511 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
2512 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
2513 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2514 | if (r) | |
2515 | goto out; | |
72dc67a6 | 2516 | |
bfc6d222 | 2517 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 2518 | out: |
79fac95e | 2519 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
2520 | return r; |
2521 | } | |
2522 | ||
b7ebfb05 SY |
2523 | static int alloc_identity_pagetable(struct kvm *kvm) |
2524 | { | |
2525 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2526 | int r = 0; | |
2527 | ||
79fac95e | 2528 | mutex_lock(&kvm->slots_lock); |
b7ebfb05 SY |
2529 | if (kvm->arch.ept_identity_pagetable) |
2530 | goto out; | |
2531 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
2532 | kvm_userspace_mem.flags = 0; | |
b927a3ce SY |
2533 | kvm_userspace_mem.guest_phys_addr = |
2534 | kvm->arch.ept_identity_map_addr; | |
b7ebfb05 SY |
2535 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
2536 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2537 | if (r) | |
2538 | goto out; | |
2539 | ||
b7ebfb05 | 2540 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
b927a3ce | 2541 | kvm->arch.ept_identity_map_addr >> PAGE_SHIFT); |
b7ebfb05 | 2542 | out: |
79fac95e | 2543 | mutex_unlock(&kvm->slots_lock); |
b7ebfb05 SY |
2544 | return r; |
2545 | } | |
2546 | ||
2384d2b3 SY |
2547 | static void allocate_vpid(struct vcpu_vmx *vmx) |
2548 | { | |
2549 | int vpid; | |
2550 | ||
2551 | vmx->vpid = 0; | |
919818ab | 2552 | if (!enable_vpid) |
2384d2b3 SY |
2553 | return; |
2554 | spin_lock(&vmx_vpid_lock); | |
2555 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
2556 | if (vpid < VMX_NR_VPIDS) { | |
2557 | vmx->vpid = vpid; | |
2558 | __set_bit(vpid, vmx_vpid_bitmap); | |
2559 | } | |
2560 | spin_unlock(&vmx_vpid_lock); | |
2561 | } | |
2562 | ||
cdbecfc3 LJ |
2563 | static void free_vpid(struct vcpu_vmx *vmx) |
2564 | { | |
2565 | if (!enable_vpid) | |
2566 | return; | |
2567 | spin_lock(&vmx_vpid_lock); | |
2568 | if (vmx->vpid != 0) | |
2569 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
2570 | spin_unlock(&vmx_vpid_lock); | |
2571 | } | |
2572 | ||
5897297b | 2573 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) |
25c5f225 | 2574 | { |
3e7c73e9 | 2575 | int f = sizeof(unsigned long); |
25c5f225 SY |
2576 | |
2577 | if (!cpu_has_vmx_msr_bitmap()) | |
2578 | return; | |
2579 | ||
2580 | /* | |
2581 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
2582 | * have the write-low and read-high bitmap offsets the wrong way round. | |
2583 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
2584 | */ | |
25c5f225 | 2585 | if (msr <= 0x1fff) { |
3e7c73e9 AK |
2586 | __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */ |
2587 | __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */ | |
25c5f225 SY |
2588 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
2589 | msr &= 0x1fff; | |
3e7c73e9 AK |
2590 | __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */ |
2591 | __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */ | |
25c5f225 | 2592 | } |
25c5f225 SY |
2593 | } |
2594 | ||
5897297b AK |
2595 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
2596 | { | |
2597 | if (!longmode_only) | |
2598 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr); | |
2599 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr); | |
2600 | } | |
2601 | ||
6aa8b732 AK |
2602 | /* |
2603 | * Sets up the vmcs for emulated real mode. | |
2604 | */ | |
8b9cf98c | 2605 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 2606 | { |
468d472f | 2607 | u32 host_sysenter_cs, msr_low, msr_high; |
6aa8b732 | 2608 | u32 junk; |
f4e1b3c8 | 2609 | u64 host_pat; |
6aa8b732 | 2610 | unsigned long a; |
89a27f4d | 2611 | struct desc_ptr dt; |
6aa8b732 | 2612 | int i; |
cd2276a7 | 2613 | unsigned long kvm_vmx_return; |
6e5d865c | 2614 | u32 exec_control; |
6aa8b732 | 2615 | |
6aa8b732 | 2616 | /* I/O */ |
3e7c73e9 AK |
2617 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
2618 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 2619 | |
25c5f225 | 2620 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 2621 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 2622 | |
6aa8b732 AK |
2623 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2624 | ||
6aa8b732 | 2625 | /* Control */ |
1c3d14fe YS |
2626 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
2627 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
2628 | |
2629 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
2630 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
2631 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2632 | #ifdef CONFIG_X86_64 | |
2633 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
2634 | CPU_BASED_CR8_LOAD_EXITING; | |
2635 | #endif | |
2636 | } | |
089d034e | 2637 | if (!enable_ept) |
d56f546d | 2638 | exec_control |= CPU_BASED_CR3_STORE_EXITING | |
83dbc83a MT |
2639 | CPU_BASED_CR3_LOAD_EXITING | |
2640 | CPU_BASED_INVLPG_EXITING; | |
6e5d865c | 2641 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 2642 | |
83ff3b9d SY |
2643 | if (cpu_has_secondary_exec_ctrls()) { |
2644 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
2645 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2646 | exec_control &= | |
2647 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
2648 | if (vmx->vpid == 0) |
2649 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
046d8710 | 2650 | if (!enable_ept) { |
d56f546d | 2651 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; |
046d8710 SY |
2652 | enable_unrestricted_guest = 0; |
2653 | } | |
3a624e29 NK |
2654 | if (!enable_unrestricted_guest) |
2655 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4b8d54f9 ZE |
2656 | if (!ple_gap) |
2657 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
83ff3b9d SY |
2658 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2659 | } | |
f78e0e2e | 2660 | |
4b8d54f9 ZE |
2661 | if (ple_gap) { |
2662 | vmcs_write32(PLE_GAP, ple_gap); | |
2663 | vmcs_write32(PLE_WINDOW, ple_window); | |
2664 | } | |
2665 | ||
c7addb90 AK |
2666 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
2667 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
2668 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
2669 | ||
1c11e713 | 2670 | vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */ |
6aa8b732 AK |
2671 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ |
2672 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
2673 | ||
2674 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
2675 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
2676 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
9581d442 AK |
2677 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
2678 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
6aa8b732 | 2679 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 2680 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2681 | rdmsrl(MSR_FS_BASE, a); |
2682 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
2683 | rdmsrl(MSR_GS_BASE, a); | |
2684 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
2685 | #else | |
2686 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
2687 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
2688 | #endif | |
2689 | ||
2690 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
2691 | ||
ec68798c | 2692 | native_store_idt(&dt); |
89a27f4d | 2693 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ |
6aa8b732 | 2694 | |
d77c26fc | 2695 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 2696 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
2697 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
2698 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 2699 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 2700 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 2701 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 AK |
2702 | |
2703 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
2704 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
2705 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
2706 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
2707 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
2708 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
2709 | ||
468d472f SY |
2710 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { |
2711 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2712 | host_pat = msr_low | ((u64) msr_high << 32); | |
2713 | vmcs_write64(HOST_IA32_PAT, host_pat); | |
2714 | } | |
2715 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
2716 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); | |
2717 | host_pat = msr_low | ((u64) msr_high << 32); | |
2718 | /* Write the default value follow host pat */ | |
2719 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
2720 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
2721 | vmx->vcpu.arch.pat = host_pat; | |
2722 | } | |
2723 | ||
6aa8b732 AK |
2724 | for (i = 0; i < NR_VMX_MSR; ++i) { |
2725 | u32 index = vmx_msr_index[i]; | |
2726 | u32 data_low, data_high; | |
a2fa3e9f | 2727 | int j = vmx->nmsrs; |
6aa8b732 AK |
2728 | |
2729 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
2730 | continue; | |
432bd6cb AK |
2731 | if (wrmsr_safe(index, data_low, data_high) < 0) |
2732 | continue; | |
26bb0981 AK |
2733 | vmx->guest_msrs[j].index = i; |
2734 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 2735 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 2736 | ++vmx->nmsrs; |
6aa8b732 | 2737 | } |
6aa8b732 | 2738 | |
1c3d14fe | 2739 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2740 | |
2741 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2742 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2743 | ||
e00c8cf2 | 2744 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
4c38609a | 2745 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; |
ce03e4f2 AK |
2746 | if (enable_ept) |
2747 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
4c38609a | 2748 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
e00c8cf2 | 2749 | |
99e3e30a | 2750 | kvm_write_tsc(&vmx->vcpu, 0); |
f78e0e2e | 2751 | |
e00c8cf2 AK |
2752 | return 0; |
2753 | } | |
2754 | ||
2755 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |
2756 | { | |
2757 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2758 | u64 msr; | |
4b9d3a04 | 2759 | int ret; |
e00c8cf2 | 2760 | |
5fdbf976 | 2761 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
e00c8cf2 | 2762 | |
7ffd92c5 | 2763 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 2764 | |
3b86cd99 JK |
2765 | vmx->soft_vnmi_blocked = 0; |
2766 | ||
ad312c7c | 2767 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2768 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 | 2769 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 2770 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
e00c8cf2 AK |
2771 | msr |= MSR_IA32_APICBASE_BSP; |
2772 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2773 | ||
10ab25cd JK |
2774 | ret = fx_init(&vmx->vcpu); |
2775 | if (ret != 0) | |
2776 | goto out; | |
e00c8cf2 | 2777 | |
5706be0d | 2778 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
2779 | /* |
2780 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2781 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2782 | */ | |
c5af89b6 | 2783 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) { |
e00c8cf2 AK |
2784 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
2785 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2786 | } else { | |
ad312c7c ZX |
2787 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2788 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 2789 | } |
e00c8cf2 AK |
2790 | |
2791 | seg_setup(VCPU_SREG_DS); | |
2792 | seg_setup(VCPU_SREG_ES); | |
2793 | seg_setup(VCPU_SREG_FS); | |
2794 | seg_setup(VCPU_SREG_GS); | |
2795 | seg_setup(VCPU_SREG_SS); | |
2796 | ||
2797 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2798 | vmcs_writel(GUEST_TR_BASE, 0); | |
2799 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2800 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2801 | ||
2802 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2803 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2804 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2805 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2806 | ||
2807 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2808 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2809 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2810 | ||
2811 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
c5af89b6 | 2812 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
5fdbf976 | 2813 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2814 | else |
5fdbf976 MT |
2815 | kvm_rip_write(vcpu, 0); |
2816 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 | 2817 | |
e00c8cf2 AK |
2818 | vmcs_writel(GUEST_DR7, 0x400); |
2819 | ||
2820 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2821 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2822 | ||
2823 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2824 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2825 | ||
443381a8 | 2826 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 AK |
2827 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
2828 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2829 | ||
e00c8cf2 AK |
2830 | /* Special registers */ |
2831 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2832 | ||
2833 | setup_msrs(vmx); | |
2834 | ||
6aa8b732 AK |
2835 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2836 | ||
f78e0e2e SY |
2837 | if (cpu_has_vmx_tpr_shadow()) { |
2838 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2839 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2840 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
afc20184 | 2841 | __pa(vmx->vcpu.arch.apic->regs)); |
f78e0e2e SY |
2842 | vmcs_write32(TPR_THRESHOLD, 0); |
2843 | } | |
2844 | ||
2845 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2846 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2847 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2848 | |
2384d2b3 SY |
2849 | if (vmx->vpid != 0) |
2850 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2851 | ||
fa40052c | 2852 | vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
4d4ec087 | 2853 | vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */ |
8b9cf98c | 2854 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2855 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2856 | vmx_fpu_activate(&vmx->vcpu); |
2857 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2858 | |
b9d762fa | 2859 | vpid_sync_context(vmx); |
2384d2b3 | 2860 | |
3200f405 | 2861 | ret = 0; |
6aa8b732 | 2862 | |
a89a8fb9 MG |
2863 | /* HACK: Don't enable emulation on guest boot/reset */ |
2864 | vmx->emulation_required = 0; | |
2865 | ||
6aa8b732 AK |
2866 | out: |
2867 | return ret; | |
2868 | } | |
2869 | ||
3b86cd99 JK |
2870 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2871 | { | |
2872 | u32 cpu_based_vm_exec_control; | |
2873 | ||
2874 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2875 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2876 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2877 | } | |
2878 | ||
2879 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
2880 | { | |
2881 | u32 cpu_based_vm_exec_control; | |
2882 | ||
2883 | if (!cpu_has_virtual_nmis()) { | |
2884 | enable_irq_window(vcpu); | |
2885 | return; | |
2886 | } | |
2887 | ||
30bd0c4c AK |
2888 | if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
2889 | enable_irq_window(vcpu); | |
2890 | return; | |
2891 | } | |
3b86cd99 JK |
2892 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
2893 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2894 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2895 | } | |
2896 | ||
66fd3f7f | 2897 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 2898 | { |
9c8cba37 | 2899 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
2900 | uint32_t intr; |
2901 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 2902 | |
229456fc | 2903 | trace_kvm_inj_virq(irq); |
2714d1d3 | 2904 | |
fa89a817 | 2905 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 2906 | if (vmx->rmode.vm86_active) { |
a92601bb MG |
2907 | if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE) |
2908 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
85f455f7 ED |
2909 | return; |
2910 | } | |
66fd3f7f GN |
2911 | intr = irq | INTR_INFO_VALID_MASK; |
2912 | if (vcpu->arch.interrupt.soft) { | |
2913 | intr |= INTR_TYPE_SOFT_INTR; | |
2914 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2915 | vmx->vcpu.arch.event_exit_inst_len); | |
2916 | } else | |
2917 | intr |= INTR_TYPE_EXT_INTR; | |
2918 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
443381a8 | 2919 | vmx_clear_hlt(vcpu); |
85f455f7 ED |
2920 | } |
2921 | ||
f08864b4 SY |
2922 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2923 | { | |
66a5a347 JK |
2924 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2925 | ||
3b86cd99 JK |
2926 | if (!cpu_has_virtual_nmis()) { |
2927 | /* | |
2928 | * Tracking the NMI-blocked state in software is built upon | |
2929 | * finding the next open IRQ window. This, in turn, depends on | |
2930 | * well-behaving guests: They have to keep IRQs disabled at | |
2931 | * least as long as the NMI handler runs. Otherwise we may | |
2932 | * cause NMI nesting, maybe breaking the guest. But as this is | |
2933 | * highly unlikely, we can live with the residual risk. | |
2934 | */ | |
2935 | vmx->soft_vnmi_blocked = 1; | |
2936 | vmx->vnmi_blocked_time = 0; | |
2937 | } | |
2938 | ||
487b391d | 2939 | ++vcpu->stat.nmi_injections; |
7ffd92c5 | 2940 | if (vmx->rmode.vm86_active) { |
a92601bb MG |
2941 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE) |
2942 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
66a5a347 JK |
2943 | return; |
2944 | } | |
f08864b4 SY |
2945 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2946 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
443381a8 | 2947 | vmx_clear_hlt(vcpu); |
f08864b4 SY |
2948 | } |
2949 | ||
c4282df9 | 2950 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
33f089ca | 2951 | { |
3b86cd99 | 2952 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
c4282df9 | 2953 | return 0; |
33f089ca | 2954 | |
c4282df9 | 2955 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
30bd0c4c AK |
2956 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
2957 | | GUEST_INTR_STATE_NMI)); | |
33f089ca JK |
2958 | } |
2959 | ||
3cfc3092 JK |
2960 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
2961 | { | |
2962 | if (!cpu_has_virtual_nmis()) | |
2963 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
c332c83a | 2964 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
2965 | } |
2966 | ||
2967 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
2968 | { | |
2969 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2970 | ||
2971 | if (!cpu_has_virtual_nmis()) { | |
2972 | if (vmx->soft_vnmi_blocked != masked) { | |
2973 | vmx->soft_vnmi_blocked = masked; | |
2974 | vmx->vnmi_blocked_time = 0; | |
2975 | } | |
2976 | } else { | |
2977 | if (masked) | |
2978 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2979 | GUEST_INTR_STATE_NMI); | |
2980 | else | |
2981 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2982 | GUEST_INTR_STATE_NMI); | |
2983 | } | |
2984 | } | |
2985 | ||
78646121 GN |
2986 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
2987 | { | |
c4282df9 GN |
2988 | return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2989 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
2990 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
2991 | } |
2992 | ||
cbc94022 IE |
2993 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2994 | { | |
2995 | int ret; | |
2996 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 2997 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
2998 | .guest_phys_addr = addr, |
2999 | .memory_size = PAGE_SIZE * 3, | |
3000 | .flags = 0, | |
3001 | }; | |
3002 | ||
3003 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
3004 | if (ret) | |
3005 | return ret; | |
bfc6d222 | 3006 | kvm->arch.tss_addr = addr; |
93ea5388 GN |
3007 | if (!init_rmode_tss(kvm)) |
3008 | return -ENOMEM; | |
3009 | ||
cbc94022 IE |
3010 | return 0; |
3011 | } | |
3012 | ||
6aa8b732 AK |
3013 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, |
3014 | int vec, u32 err_code) | |
3015 | { | |
b3f37707 NK |
3016 | /* |
3017 | * Instruction with address size override prefix opcode 0x67 | |
3018 | * Cause the #SS fault with 0 error code in VM86 mode. | |
3019 | */ | |
3020 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
51d8b661 | 3021 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) |
6aa8b732 | 3022 | return 1; |
77ab6db0 JK |
3023 | /* |
3024 | * Forward all other exceptions that are valid in real mode. | |
3025 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
3026 | * the required debugging infrastructure rework. | |
3027 | */ | |
3028 | switch (vec) { | |
77ab6db0 | 3029 | case DB_VECTOR: |
d0bfb940 JK |
3030 | if (vcpu->guest_debug & |
3031 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
3032 | return 0; | |
3033 | kvm_queue_exception(vcpu, vec); | |
3034 | return 1; | |
77ab6db0 | 3035 | case BP_VECTOR: |
c573cd22 JK |
3036 | /* |
3037 | * Update instruction length as we may reinject the exception | |
3038 | * from user space while in guest debugging mode. | |
3039 | */ | |
3040 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
3041 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 JK |
3042 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
3043 | return 0; | |
3044 | /* fall through */ | |
3045 | case DE_VECTOR: | |
77ab6db0 JK |
3046 | case OF_VECTOR: |
3047 | case BR_VECTOR: | |
3048 | case UD_VECTOR: | |
3049 | case DF_VECTOR: | |
3050 | case SS_VECTOR: | |
3051 | case GP_VECTOR: | |
3052 | case MF_VECTOR: | |
3053 | kvm_queue_exception(vcpu, vec); | |
3054 | return 1; | |
3055 | } | |
6aa8b732 AK |
3056 | return 0; |
3057 | } | |
3058 | ||
a0861c02 AK |
3059 | /* |
3060 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
3061 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
3062 | * We pass a fake environment to the machine check handler because we want | |
3063 | * the guest to be always treated like user space, no matter what context | |
3064 | * it used internally. | |
3065 | */ | |
3066 | static void kvm_machine_check(void) | |
3067 | { | |
3068 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
3069 | struct pt_regs regs = { | |
3070 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
3071 | .flags = X86_EFLAGS_IF, | |
3072 | }; | |
3073 | ||
3074 | do_machine_check(®s, 0); | |
3075 | #endif | |
3076 | } | |
3077 | ||
851ba692 | 3078 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
3079 | { |
3080 | /* already handled by vcpu_run */ | |
3081 | return 1; | |
3082 | } | |
3083 | ||
851ba692 | 3084 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 3085 | { |
1155f76a | 3086 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 3087 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 3088 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 3089 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
3090 | u32 vect_info; |
3091 | enum emulation_result er; | |
3092 | ||
1155f76a | 3093 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
3094 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
3095 | ||
a0861c02 | 3096 | if (is_machine_check(intr_info)) |
851ba692 | 3097 | return handle_machine_check(vcpu); |
a0861c02 | 3098 | |
6aa8b732 | 3099 | if ((vect_info & VECTORING_INFO_VALID_MASK) && |
65ac7264 AK |
3100 | !is_page_fault(intr_info)) { |
3101 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3102 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
3103 | vcpu->run->internal.ndata = 2; | |
3104 | vcpu->run->internal.data[0] = vect_info; | |
3105 | vcpu->run->internal.data[1] = intr_info; | |
3106 | return 0; | |
3107 | } | |
6aa8b732 | 3108 | |
e4a41889 | 3109 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 3110 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
3111 | |
3112 | if (is_no_device(intr_info)) { | |
5fd86fcf | 3113 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
3114 | return 1; |
3115 | } | |
3116 | ||
7aa81cc0 | 3117 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 3118 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 3119 | if (er != EMULATE_DONE) |
7ee5d940 | 3120 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
3121 | return 1; |
3122 | } | |
3123 | ||
6aa8b732 | 3124 | error_code = 0; |
5fdbf976 | 3125 | rip = kvm_rip_read(vcpu); |
2e11384c | 3126 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
3127 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
3128 | if (is_page_fault(intr_info)) { | |
1439442c | 3129 | /* EPT won't cause page fault directly */ |
089d034e | 3130 | if (enable_ept) |
1439442c | 3131 | BUG(); |
6aa8b732 | 3132 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
3133 | trace_kvm_page_fault(cr2, error_code); |
3134 | ||
3298b75c | 3135 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 3136 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 3137 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
3138 | } |
3139 | ||
7ffd92c5 | 3140 | if (vmx->rmode.vm86_active && |
6aa8b732 | 3141 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 3142 | error_code)) { |
ad312c7c ZX |
3143 | if (vcpu->arch.halt_request) { |
3144 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
3145 | return kvm_emulate_halt(vcpu); |
3146 | } | |
6aa8b732 | 3147 | return 1; |
72d6e5a0 | 3148 | } |
6aa8b732 | 3149 | |
d0bfb940 | 3150 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
42dbaa5a JK |
3151 | switch (ex_no) { |
3152 | case DB_VECTOR: | |
3153 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
3154 | if (!(vcpu->guest_debug & | |
3155 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
3156 | vcpu->arch.dr6 = dr6 | DR6_FIXED_1; | |
3157 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3158 | return 1; | |
3159 | } | |
3160 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
3161 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
3162 | /* fall through */ | |
3163 | case BP_VECTOR: | |
c573cd22 JK |
3164 | /* |
3165 | * Update instruction length as we may reinject #BP from | |
3166 | * user space while in guest debugging mode. Reading it for | |
3167 | * #DB as well causes no harm, it is not used in that case. | |
3168 | */ | |
3169 | vmx->vcpu.arch.event_exit_inst_len = | |
3170 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 3171 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
d0bfb940 JK |
3172 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
3173 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
3174 | break; |
3175 | default: | |
d0bfb940 JK |
3176 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
3177 | kvm_run->ex.exception = ex_no; | |
3178 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 3179 | break; |
6aa8b732 | 3180 | } |
6aa8b732 AK |
3181 | return 0; |
3182 | } | |
3183 | ||
851ba692 | 3184 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 3185 | { |
1165f5fe | 3186 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
3187 | return 1; |
3188 | } | |
3189 | ||
851ba692 | 3190 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 3191 | { |
851ba692 | 3192 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
3193 | return 0; |
3194 | } | |
6aa8b732 | 3195 | |
851ba692 | 3196 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 3197 | { |
bfdaab09 | 3198 | unsigned long exit_qualification; |
34c33d16 | 3199 | int size, in, string; |
039576c0 | 3200 | unsigned port; |
6aa8b732 | 3201 | |
bfdaab09 | 3202 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 3203 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 3204 | in = (exit_qualification & 8) != 0; |
e70669ab | 3205 | |
cf8f70bf | 3206 | ++vcpu->stat.io_exits; |
e70669ab | 3207 | |
cf8f70bf | 3208 | if (string || in) |
51d8b661 | 3209 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 3210 | |
cf8f70bf GN |
3211 | port = exit_qualification >> 16; |
3212 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 3213 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
3214 | |
3215 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
3216 | } |
3217 | ||
102d8325 IM |
3218 | static void |
3219 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3220 | { | |
3221 | /* | |
3222 | * Patch in the VMCALL instruction: | |
3223 | */ | |
3224 | hypercall[0] = 0x0f; | |
3225 | hypercall[1] = 0x01; | |
3226 | hypercall[2] = 0xc1; | |
102d8325 IM |
3227 | } |
3228 | ||
851ba692 | 3229 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3230 | { |
229456fc | 3231 | unsigned long exit_qualification, val; |
6aa8b732 AK |
3232 | int cr; |
3233 | int reg; | |
49a9b07e | 3234 | int err; |
6aa8b732 | 3235 | |
bfdaab09 | 3236 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
3237 | cr = exit_qualification & 15; |
3238 | reg = (exit_qualification >> 8) & 15; | |
3239 | switch ((exit_qualification >> 4) & 3) { | |
3240 | case 0: /* mov to cr */ | |
229456fc MT |
3241 | val = kvm_register_read(vcpu, reg); |
3242 | trace_kvm_cr_write(cr, val); | |
6aa8b732 AK |
3243 | switch (cr) { |
3244 | case 0: | |
49a9b07e | 3245 | err = kvm_set_cr0(vcpu, val); |
db8fcefa | 3246 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
3247 | return 1; |
3248 | case 3: | |
2390218b | 3249 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 3250 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
3251 | return 1; |
3252 | case 4: | |
a83b29c6 | 3253 | err = kvm_set_cr4(vcpu, val); |
db8fcefa | 3254 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 3255 | return 1; |
0a5fff19 GN |
3256 | case 8: { |
3257 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
3258 | u8 cr8 = kvm_register_read(vcpu, reg); | |
eea1cff9 | 3259 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 3260 | kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
3261 | if (irqchip_in_kernel(vcpu->kvm)) |
3262 | return 1; | |
3263 | if (cr8_prev <= cr8) | |
3264 | return 1; | |
851ba692 | 3265 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
3266 | return 0; |
3267 | } | |
6aa8b732 AK |
3268 | }; |
3269 | break; | |
25c4c276 | 3270 | case 2: /* clts */ |
edcafe3c | 3271 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); |
4d4ec087 | 3272 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 3273 | skip_emulated_instruction(vcpu); |
6b52d186 | 3274 | vmx_fpu_activate(vcpu); |
25c4c276 | 3275 | return 1; |
6aa8b732 AK |
3276 | case 1: /*mov from cr*/ |
3277 | switch (cr) { | |
3278 | case 3: | |
9f8fe504 AK |
3279 | val = kvm_read_cr3(vcpu); |
3280 | kvm_register_write(vcpu, reg, val); | |
3281 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
3282 | skip_emulated_instruction(vcpu); |
3283 | return 1; | |
3284 | case 8: | |
229456fc MT |
3285 | val = kvm_get_cr8(vcpu); |
3286 | kvm_register_write(vcpu, reg, val); | |
3287 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
3288 | skip_emulated_instruction(vcpu); |
3289 | return 1; | |
3290 | } | |
3291 | break; | |
3292 | case 3: /* lmsw */ | |
a1f83a74 | 3293 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 3294 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 3295 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
3296 | |
3297 | skip_emulated_instruction(vcpu); | |
3298 | return 1; | |
3299 | default: | |
3300 | break; | |
3301 | } | |
851ba692 | 3302 | vcpu->run->exit_reason = 0; |
f0242478 | 3303 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
3304 | (int)(exit_qualification >> 4) & 3, cr); |
3305 | return 0; | |
3306 | } | |
3307 | ||
851ba692 | 3308 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3309 | { |
bfdaab09 | 3310 | unsigned long exit_qualification; |
6aa8b732 AK |
3311 | int dr, reg; |
3312 | ||
f2483415 | 3313 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
3314 | if (!kvm_require_cpl(vcpu, 0)) |
3315 | return 1; | |
42dbaa5a JK |
3316 | dr = vmcs_readl(GUEST_DR7); |
3317 | if (dr & DR7_GD) { | |
3318 | /* | |
3319 | * As the vm-exit takes precedence over the debug trap, we | |
3320 | * need to emulate the latter, either for the host or the | |
3321 | * guest debugging itself. | |
3322 | */ | |
3323 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 AK |
3324 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
3325 | vcpu->run->debug.arch.dr7 = dr; | |
3326 | vcpu->run->debug.arch.pc = | |
42dbaa5a JK |
3327 | vmcs_readl(GUEST_CS_BASE) + |
3328 | vmcs_readl(GUEST_RIP); | |
851ba692 AK |
3329 | vcpu->run->debug.arch.exception = DB_VECTOR; |
3330 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
3331 | return 0; |
3332 | } else { | |
3333 | vcpu->arch.dr7 &= ~DR7_GD; | |
3334 | vcpu->arch.dr6 |= DR6_BD; | |
3335 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
3336 | kvm_queue_exception(vcpu, DB_VECTOR); | |
3337 | return 1; | |
3338 | } | |
3339 | } | |
3340 | ||
bfdaab09 | 3341 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
42dbaa5a JK |
3342 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
3343 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); | |
3344 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 GN |
3345 | unsigned long val; |
3346 | if (!kvm_get_dr(vcpu, dr, &val)) | |
3347 | kvm_register_write(vcpu, reg, val); | |
3348 | } else | |
3349 | kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]); | |
6aa8b732 AK |
3350 | skip_emulated_instruction(vcpu); |
3351 | return 1; | |
3352 | } | |
3353 | ||
020df079 GN |
3354 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
3355 | { | |
3356 | vmcs_writel(GUEST_DR7, val); | |
3357 | } | |
3358 | ||
851ba692 | 3359 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 3360 | { |
06465c5a AK |
3361 | kvm_emulate_cpuid(vcpu); |
3362 | return 1; | |
6aa8b732 AK |
3363 | } |
3364 | ||
851ba692 | 3365 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3366 | { |
ad312c7c | 3367 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
3368 | u64 data; |
3369 | ||
3370 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
59200273 | 3371 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 3372 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3373 | return 1; |
3374 | } | |
3375 | ||
229456fc | 3376 | trace_kvm_msr_read(ecx, data); |
2714d1d3 | 3377 | |
6aa8b732 | 3378 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
3379 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
3380 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
3381 | skip_emulated_instruction(vcpu); |
3382 | return 1; | |
3383 | } | |
3384 | ||
851ba692 | 3385 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 3386 | { |
ad312c7c ZX |
3387 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
3388 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
3389 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 AK |
3390 | |
3391 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
59200273 | 3392 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 3393 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
3394 | return 1; |
3395 | } | |
3396 | ||
59200273 | 3397 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
3398 | skip_emulated_instruction(vcpu); |
3399 | return 1; | |
3400 | } | |
3401 | ||
851ba692 | 3402 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 3403 | { |
3842d135 | 3404 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
3405 | return 1; |
3406 | } | |
3407 | ||
851ba692 | 3408 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3409 | { |
85f455f7 ED |
3410 | u32 cpu_based_vm_exec_control; |
3411 | ||
3412 | /* clear pending irq */ | |
3413 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3414 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
3415 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 3416 | |
3842d135 AK |
3417 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3418 | ||
a26bf12a | 3419 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 3420 | |
c1150d8c DL |
3421 | /* |
3422 | * If the user space waits to inject interrupts, exit as soon as | |
3423 | * possible | |
3424 | */ | |
8061823a | 3425 | if (!irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 3426 | vcpu->run->request_interrupt_window && |
8061823a | 3427 | !kvm_cpu_has_interrupt(vcpu)) { |
851ba692 | 3428 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
3429 | return 0; |
3430 | } | |
6aa8b732 AK |
3431 | return 1; |
3432 | } | |
3433 | ||
851ba692 | 3434 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
3435 | { |
3436 | skip_emulated_instruction(vcpu); | |
d3bef15f | 3437 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
3438 | } |
3439 | ||
851ba692 | 3440 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 3441 | { |
510043da | 3442 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
3443 | kvm_emulate_hypercall(vcpu); |
3444 | return 1; | |
c21415e8 IM |
3445 | } |
3446 | ||
851ba692 | 3447 | static int handle_vmx_insn(struct kvm_vcpu *vcpu) |
e3c7cb6a AK |
3448 | { |
3449 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3450 | return 1; | |
3451 | } | |
3452 | ||
ec25d5e6 GN |
3453 | static int handle_invd(struct kvm_vcpu *vcpu) |
3454 | { | |
51d8b661 | 3455 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
3456 | } |
3457 | ||
851ba692 | 3458 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 3459 | { |
f9c617f6 | 3460 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
3461 | |
3462 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
3463 | skip_emulated_instruction(vcpu); | |
3464 | return 1; | |
3465 | } | |
3466 | ||
851ba692 | 3467 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 ED |
3468 | { |
3469 | skip_emulated_instruction(vcpu); | |
f5f48ee1 | 3470 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
3471 | return 1; |
3472 | } | |
3473 | ||
2acf923e DC |
3474 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
3475 | { | |
3476 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
3477 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3478 | ||
3479 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
3480 | skip_emulated_instruction(vcpu); | |
3481 | return 1; | |
3482 | } | |
3483 | ||
851ba692 | 3484 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 3485 | { |
51d8b661 | 3486 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
3487 | } |
3488 | ||
851ba692 | 3489 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 3490 | { |
60637aac | 3491 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 3492 | unsigned long exit_qualification; |
e269fb21 JK |
3493 | bool has_error_code = false; |
3494 | u32 error_code = 0; | |
37817f29 | 3495 | u16 tss_selector; |
64a7ec06 GN |
3496 | int reason, type, idt_v; |
3497 | ||
3498 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
3499 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); | |
37817f29 IE |
3500 | |
3501 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
3502 | ||
3503 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
3504 | if (reason == TASK_SWITCH_GATE && idt_v) { |
3505 | switch (type) { | |
3506 | case INTR_TYPE_NMI_INTR: | |
3507 | vcpu->arch.nmi_injected = false; | |
3508 | if (cpu_has_virtual_nmis()) | |
3509 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
3510 | GUEST_INTR_STATE_NMI); | |
3511 | break; | |
3512 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 3513 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
3514 | kvm_clear_interrupt_queue(vcpu); |
3515 | break; | |
3516 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
3517 | if (vmx->idt_vectoring_info & |
3518 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
3519 | has_error_code = true; | |
3520 | error_code = | |
3521 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
3522 | } | |
3523 | /* fall through */ | |
64a7ec06 GN |
3524 | case INTR_TYPE_SOFT_EXCEPTION: |
3525 | kvm_clear_exception_queue(vcpu); | |
3526 | break; | |
3527 | default: | |
3528 | break; | |
3529 | } | |
60637aac | 3530 | } |
37817f29 IE |
3531 | tss_selector = exit_qualification; |
3532 | ||
64a7ec06 GN |
3533 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
3534 | type != INTR_TYPE_EXT_INTR && | |
3535 | type != INTR_TYPE_NMI_INTR)) | |
3536 | skip_emulated_instruction(vcpu); | |
3537 | ||
acb54517 GN |
3538 | if (kvm_task_switch(vcpu, tss_selector, reason, |
3539 | has_error_code, error_code) == EMULATE_FAIL) { | |
3540 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
3541 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
3542 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 3543 | return 0; |
acb54517 | 3544 | } |
42dbaa5a JK |
3545 | |
3546 | /* clear all local breakpoint enable flags */ | |
3547 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); | |
3548 | ||
3549 | /* | |
3550 | * TODO: What about debug traps on tss switch? | |
3551 | * Are we supposed to inject them and update dr6? | |
3552 | */ | |
3553 | ||
3554 | return 1; | |
37817f29 IE |
3555 | } |
3556 | ||
851ba692 | 3557 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 3558 | { |
f9c617f6 | 3559 | unsigned long exit_qualification; |
1439442c | 3560 | gpa_t gpa; |
1439442c | 3561 | int gla_validity; |
1439442c | 3562 | |
f9c617f6 | 3563 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c SY |
3564 | |
3565 | if (exit_qualification & (1 << 6)) { | |
3566 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
7f582ab6 | 3567 | return -EINVAL; |
1439442c SY |
3568 | } |
3569 | ||
3570 | gla_validity = (exit_qualification >> 7) & 0x3; | |
3571 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
3572 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
3573 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
3574 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 3575 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
3576 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
3577 | (long unsigned int)exit_qualification); | |
851ba692 AK |
3578 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3579 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 3580 | return 0; |
1439442c SY |
3581 | } |
3582 | ||
3583 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
229456fc | 3584 | trace_kvm_page_fault(gpa, exit_qualification); |
dc25e89e | 3585 | return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0); |
1439442c SY |
3586 | } |
3587 | ||
68f89400 MT |
3588 | static u64 ept_rsvd_mask(u64 spte, int level) |
3589 | { | |
3590 | int i; | |
3591 | u64 mask = 0; | |
3592 | ||
3593 | for (i = 51; i > boot_cpu_data.x86_phys_bits; i--) | |
3594 | mask |= (1ULL << i); | |
3595 | ||
3596 | if (level > 2) | |
3597 | /* bits 7:3 reserved */ | |
3598 | mask |= 0xf8; | |
3599 | else if (level == 2) { | |
3600 | if (spte & (1ULL << 7)) | |
3601 | /* 2MB ref, bits 20:12 reserved */ | |
3602 | mask |= 0x1ff000; | |
3603 | else | |
3604 | /* bits 6:3 reserved */ | |
3605 | mask |= 0x78; | |
3606 | } | |
3607 | ||
3608 | return mask; | |
3609 | } | |
3610 | ||
3611 | static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte, | |
3612 | int level) | |
3613 | { | |
3614 | printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level); | |
3615 | ||
3616 | /* 010b (write-only) */ | |
3617 | WARN_ON((spte & 0x7) == 0x2); | |
3618 | ||
3619 | /* 110b (write/execute) */ | |
3620 | WARN_ON((spte & 0x7) == 0x6); | |
3621 | ||
3622 | /* 100b (execute-only) and value not supported by logical processor */ | |
3623 | if (!cpu_has_vmx_ept_execute_only()) | |
3624 | WARN_ON((spte & 0x7) == 0x4); | |
3625 | ||
3626 | /* not 000b */ | |
3627 | if ((spte & 0x7)) { | |
3628 | u64 rsvd_bits = spte & ept_rsvd_mask(spte, level); | |
3629 | ||
3630 | if (rsvd_bits != 0) { | |
3631 | printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n", | |
3632 | __func__, rsvd_bits); | |
3633 | WARN_ON(1); | |
3634 | } | |
3635 | ||
3636 | if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) { | |
3637 | u64 ept_mem_type = (spte & 0x38) >> 3; | |
3638 | ||
3639 | if (ept_mem_type == 2 || ept_mem_type == 3 || | |
3640 | ept_mem_type == 7) { | |
3641 | printk(KERN_ERR "%s: ept_mem_type=0x%llx\n", | |
3642 | __func__, ept_mem_type); | |
3643 | WARN_ON(1); | |
3644 | } | |
3645 | } | |
3646 | } | |
3647 | } | |
3648 | ||
851ba692 | 3649 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 MT |
3650 | { |
3651 | u64 sptes[4]; | |
3652 | int nr_sptes, i; | |
3653 | gpa_t gpa; | |
3654 | ||
3655 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
3656 | ||
3657 | printk(KERN_ERR "EPT: Misconfiguration.\n"); | |
3658 | printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa); | |
3659 | ||
3660 | nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes); | |
3661 | ||
3662 | for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i) | |
3663 | ept_misconfig_inspect_spte(vcpu, sptes[i-1], i); | |
3664 | ||
851ba692 AK |
3665 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3666 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
3667 | |
3668 | return 0; | |
3669 | } | |
3670 | ||
851ba692 | 3671 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
3672 | { |
3673 | u32 cpu_based_vm_exec_control; | |
3674 | ||
3675 | /* clear pending NMI */ | |
3676 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3677 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
3678 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3679 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 3680 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
3681 | |
3682 | return 1; | |
3683 | } | |
3684 | ||
80ced186 | 3685 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 3686 | { |
8b3079a5 AK |
3687 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3688 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 3689 | int ret = 1; |
49e9d557 AK |
3690 | u32 cpu_exec_ctrl; |
3691 | bool intr_window_requested; | |
3692 | ||
3693 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3694 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 MG |
3695 | |
3696 | while (!guest_state_valid(vcpu)) { | |
49e9d557 AK |
3697 | if (intr_window_requested |
3698 | && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF)) | |
3699 | return handle_interrupt_window(&vmx->vcpu); | |
3700 | ||
51d8b661 | 3701 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 3702 | |
80ced186 MG |
3703 | if (err == EMULATE_DO_MMIO) { |
3704 | ret = 0; | |
3705 | goto out; | |
3706 | } | |
1d5a4d9b | 3707 | |
6d77dbfc GN |
3708 | if (err != EMULATE_DONE) |
3709 | return 0; | |
ea953ef0 MG |
3710 | |
3711 | if (signal_pending(current)) | |
80ced186 | 3712 | goto out; |
ea953ef0 MG |
3713 | if (need_resched()) |
3714 | schedule(); | |
3715 | } | |
3716 | ||
80ced186 MG |
3717 | vmx->emulation_required = 0; |
3718 | out: | |
3719 | return ret; | |
ea953ef0 MG |
3720 | } |
3721 | ||
4b8d54f9 ZE |
3722 | /* |
3723 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
3724 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
3725 | */ | |
9fb41ba8 | 3726 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 ZE |
3727 | { |
3728 | skip_emulated_instruction(vcpu); | |
3729 | kvm_vcpu_on_spin(vcpu); | |
3730 | ||
3731 | return 1; | |
3732 | } | |
3733 | ||
59708670 SY |
3734 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
3735 | { | |
3736 | kvm_queue_exception(vcpu, UD_VECTOR); | |
3737 | return 1; | |
3738 | } | |
3739 | ||
6aa8b732 AK |
3740 | /* |
3741 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
3742 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
3743 | * to be done to userspace and return 0. | |
3744 | */ | |
851ba692 | 3745 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
3746 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
3747 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 3748 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 3749 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 3750 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
3751 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
3752 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
3753 | [EXIT_REASON_CPUID] = handle_cpuid, | |
3754 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
3755 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
3756 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
3757 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 3758 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 3759 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 3760 | [EXIT_REASON_VMCALL] = handle_vmcall, |
e3c7cb6a AK |
3761 | [EXIT_REASON_VMCLEAR] = handle_vmx_insn, |
3762 | [EXIT_REASON_VMLAUNCH] = handle_vmx_insn, | |
3763 | [EXIT_REASON_VMPTRLD] = handle_vmx_insn, | |
3764 | [EXIT_REASON_VMPTRST] = handle_vmx_insn, | |
3765 | [EXIT_REASON_VMREAD] = handle_vmx_insn, | |
3766 | [EXIT_REASON_VMRESUME] = handle_vmx_insn, | |
3767 | [EXIT_REASON_VMWRITE] = handle_vmx_insn, | |
3768 | [EXIT_REASON_VMOFF] = handle_vmx_insn, | |
3769 | [EXIT_REASON_VMON] = handle_vmx_insn, | |
f78e0e2e SY |
3770 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
3771 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 3772 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 3773 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 3774 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 3775 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
3776 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
3777 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 3778 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
59708670 SY |
3779 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op, |
3780 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op, | |
6aa8b732 AK |
3781 | }; |
3782 | ||
3783 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 3784 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 3785 | |
586f9607 AK |
3786 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
3787 | { | |
3788 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
3789 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
3790 | } | |
3791 | ||
6aa8b732 AK |
3792 | /* |
3793 | * The guest has exited. See if we can fix it or if we need userspace | |
3794 | * assistance. | |
3795 | */ | |
851ba692 | 3796 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 3797 | { |
29bd8a78 | 3798 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 3799 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 3800 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 3801 | |
aa17911e | 3802 | trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); |
2714d1d3 | 3803 | |
80ced186 MG |
3804 | /* If guest state is invalid, start emulating */ |
3805 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
3806 | return handle_invalid_guest_state(vcpu); | |
1d5a4d9b | 3807 | |
5120702e MG |
3808 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
3809 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
3810 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
3811 | = exit_reason; | |
3812 | return 0; | |
3813 | } | |
3814 | ||
29bd8a78 | 3815 | if (unlikely(vmx->fail)) { |
851ba692 AK |
3816 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
3817 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
3818 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
3819 | return 0; | |
3820 | } | |
6aa8b732 | 3821 | |
d77c26fc | 3822 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 3823 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
3824 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
3825 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
3826 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
3827 | "(0x%x) and exit reason is 0x%x\n", | |
3828 | __func__, vectoring_info, exit_reason); | |
3b86cd99 JK |
3829 | |
3830 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | |
c4282df9 | 3831 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 3832 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 3833 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 3834 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
3835 | /* |
3836 | * This CPU don't support us in finding the end of an | |
3837 | * NMI-blocked window if the guest runs with IRQs | |
3838 | * disabled. So we pull the trigger after 1 s of | |
3839 | * futile waiting, but inform the user about this. | |
3840 | */ | |
3841 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
3842 | "state on VCPU %d after 1 s timeout\n", | |
3843 | __func__, vcpu->vcpu_id); | |
3844 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 3845 | } |
3b86cd99 JK |
3846 | } |
3847 | ||
6aa8b732 AK |
3848 | if (exit_reason < kvm_vmx_max_exit_handlers |
3849 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 3850 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 3851 | else { |
851ba692 AK |
3852 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
3853 | vcpu->run->hw.hardware_exit_reason = exit_reason; | |
6aa8b732 AK |
3854 | } |
3855 | return 0; | |
3856 | } | |
3857 | ||
95ba8273 | 3858 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 3859 | { |
95ba8273 | 3860 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
3861 | vmcs_write32(TPR_THRESHOLD, 0); |
3862 | return; | |
3863 | } | |
3864 | ||
95ba8273 | 3865 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
3866 | } |
3867 | ||
51aa01d1 | 3868 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 3869 | { |
51aa01d1 | 3870 | u32 exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
3871 | |
3872 | /* Handle machine checks before interrupts are enabled */ | |
3873 | if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) | |
3874 | || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI | |
3875 | && is_machine_check(exit_intr_info))) | |
3876 | kvm_machine_check(); | |
3877 | ||
20f65983 GN |
3878 | /* We need to handle NMIs before interrupts are enabled */ |
3879 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && | |
ff9d07a0 ZY |
3880 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
3881 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 3882 | asm("int $2"); |
ff9d07a0 ZY |
3883 | kvm_after_handle_nmi(&vmx->vcpu); |
3884 | } | |
51aa01d1 | 3885 | } |
20f65983 | 3886 | |
51aa01d1 AK |
3887 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
3888 | { | |
3889 | u32 exit_intr_info = vmx->exit_intr_info; | |
3890 | bool unblock_nmi; | |
3891 | u8 vector; | |
3892 | bool idtv_info_valid; | |
3893 | ||
3894 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 3895 | |
cf393f75 AK |
3896 | if (cpu_has_virtual_nmis()) { |
3897 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
3898 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
3899 | /* | |
7b4a25cb | 3900 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
3901 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
3902 | * a guest IRET fault. | |
7b4a25cb GN |
3903 | * SDM 3: 23.2.2 (September 2008) |
3904 | * Bit 12 is undefined in any of the following cases: | |
3905 | * If the VM exit sets the valid bit in the IDT-vectoring | |
3906 | * information field. | |
3907 | * If the VM exit is due to a double fault. | |
cf393f75 | 3908 | */ |
7b4a25cb GN |
3909 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
3910 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
3911 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
3912 | GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
3913 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
3914 | vmx->vnmi_blocked_time += | |
3915 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
3916 | } |
3917 | ||
83422e17 AK |
3918 | static void __vmx_complete_interrupts(struct vcpu_vmx *vmx, |
3919 | u32 idt_vectoring_info, | |
3920 | int instr_len_field, | |
3921 | int error_code_field) | |
51aa01d1 | 3922 | { |
51aa01d1 AK |
3923 | u8 vector; |
3924 | int type; | |
3925 | bool idtv_info_valid; | |
3926 | ||
3927 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 3928 | |
37b96e98 GN |
3929 | vmx->vcpu.arch.nmi_injected = false; |
3930 | kvm_clear_exception_queue(&vmx->vcpu); | |
3931 | kvm_clear_interrupt_queue(&vmx->vcpu); | |
3932 | ||
3933 | if (!idtv_info_valid) | |
3934 | return; | |
3935 | ||
3842d135 AK |
3936 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); |
3937 | ||
668f612f AK |
3938 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
3939 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 3940 | |
64a7ec06 | 3941 | switch (type) { |
37b96e98 GN |
3942 | case INTR_TYPE_NMI_INTR: |
3943 | vmx->vcpu.arch.nmi_injected = true; | |
668f612f | 3944 | /* |
7b4a25cb | 3945 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
3946 | * Clear bit "block by NMI" before VM entry if a NMI |
3947 | * delivery faulted. | |
668f612f | 3948 | */ |
37b96e98 GN |
3949 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, |
3950 | GUEST_INTR_STATE_NMI); | |
3951 | break; | |
37b96e98 | 3952 | case INTR_TYPE_SOFT_EXCEPTION: |
66fd3f7f | 3953 | vmx->vcpu.arch.event_exit_inst_len = |
83422e17 | 3954 | vmcs_read32(instr_len_field); |
66fd3f7f GN |
3955 | /* fall through */ |
3956 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 3957 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 3958 | u32 err = vmcs_read32(error_code_field); |
37b96e98 | 3959 | kvm_queue_exception_e(&vmx->vcpu, vector, err); |
35920a35 AK |
3960 | } else |
3961 | kvm_queue_exception(&vmx->vcpu, vector); | |
37b96e98 | 3962 | break; |
66fd3f7f GN |
3963 | case INTR_TYPE_SOFT_INTR: |
3964 | vmx->vcpu.arch.event_exit_inst_len = | |
83422e17 | 3965 | vmcs_read32(instr_len_field); |
66fd3f7f | 3966 | /* fall through */ |
37b96e98 | 3967 | case INTR_TYPE_EXT_INTR: |
66fd3f7f GN |
3968 | kvm_queue_interrupt(&vmx->vcpu, vector, |
3969 | type == INTR_TYPE_SOFT_INTR); | |
37b96e98 GN |
3970 | break; |
3971 | default: | |
3972 | break; | |
f7d9238f | 3973 | } |
cf393f75 AK |
3974 | } |
3975 | ||
83422e17 AK |
3976 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3977 | { | |
3978 | __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info, | |
3979 | VM_EXIT_INSTRUCTION_LEN, | |
3980 | IDT_VECTORING_ERROR_CODE); | |
3981 | } | |
3982 | ||
b463a6f7 AK |
3983 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
3984 | { | |
3985 | __vmx_complete_interrupts(to_vmx(vcpu), | |
3986 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
3987 | VM_ENTRY_INSTRUCTION_LEN, | |
3988 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
3989 | ||
3990 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
3991 | } | |
3992 | ||
c801949d AK |
3993 | #ifdef CONFIG_X86_64 |
3994 | #define R "r" | |
3995 | #define Q "q" | |
3996 | #else | |
3997 | #define R "e" | |
3998 | #define Q "l" | |
3999 | #endif | |
4000 | ||
a3b5ba49 | 4001 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 4002 | { |
a2fa3e9f | 4003 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
104f226b AK |
4004 | |
4005 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
4006 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
4007 | vmx->entry_time = ktime_get(); | |
4008 | ||
4009 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
4010 | start emulation until we arrive back to a valid state */ | |
4011 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
4012 | return; | |
4013 | ||
4014 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
4015 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
4016 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
4017 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
4018 | ||
4019 | /* When single-stepping over STI and MOV SS, we must clear the | |
4020 | * corresponding interruptibility bits in the guest state. Otherwise | |
4021 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
4022 | * exceptions being set, but that's not correct for the guest debugging | |
4023 | * case. */ | |
4024 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
4025 | vmx_set_interrupt_shadow(vcpu, 0); | |
4026 | ||
4027 | asm( | |
6aa8b732 | 4028 | /* Store host registers */ |
c801949d | 4029 | "push %%"R"dx; push %%"R"bp;" |
40712fae | 4030 | "push %%"R"cx \n\t" /* placeholder for guest rcx */ |
c801949d | 4031 | "push %%"R"cx \n\t" |
313dbd49 AK |
4032 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
4033 | "je 1f \n\t" | |
4034 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 4035 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 4036 | "1: \n\t" |
d3edefc0 AK |
4037 | /* Reload cr2 if changed */ |
4038 | "mov %c[cr2](%0), %%"R"ax \n\t" | |
4039 | "mov %%cr2, %%"R"dx \n\t" | |
4040 | "cmp %%"R"ax, %%"R"dx \n\t" | |
4041 | "je 2f \n\t" | |
4042 | "mov %%"R"ax, %%cr2 \n\t" | |
4043 | "2: \n\t" | |
6aa8b732 | 4044 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 4045 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 4046 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
4047 | "mov %c[rax](%0), %%"R"ax \n\t" |
4048 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
4049 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
4050 | "mov %c[rsi](%0), %%"R"si \n\t" | |
4051 | "mov %c[rdi](%0), %%"R"di \n\t" | |
4052 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 4053 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
4054 | "mov %c[r8](%0), %%r8 \n\t" |
4055 | "mov %c[r9](%0), %%r9 \n\t" | |
4056 | "mov %c[r10](%0), %%r10 \n\t" | |
4057 | "mov %c[r11](%0), %%r11 \n\t" | |
4058 | "mov %c[r12](%0), %%r12 \n\t" | |
4059 | "mov %c[r13](%0), %%r13 \n\t" | |
4060 | "mov %c[r14](%0), %%r14 \n\t" | |
4061 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 4062 | #endif |
c801949d AK |
4063 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
4064 | ||
6aa8b732 | 4065 | /* Enter guest mode */ |
cd2276a7 | 4066 | "jne .Llaunched \n\t" |
4ecac3fd | 4067 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 4068 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 4069 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 4070 | ".Lkvm_vmx_return: " |
6aa8b732 | 4071 | /* Save guest registers, load host registers, keep flags */ |
40712fae AK |
4072 | "mov %0, %c[wordsize](%%"R"sp) \n\t" |
4073 | "pop %0 \n\t" | |
c801949d AK |
4074 | "mov %%"R"ax, %c[rax](%0) \n\t" |
4075 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
1c696d0e | 4076 | "pop"Q" %c[rcx](%0) \n\t" |
c801949d AK |
4077 | "mov %%"R"dx, %c[rdx](%0) \n\t" |
4078 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
4079 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
4080 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 4081 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
4082 | "mov %%r8, %c[r8](%0) \n\t" |
4083 | "mov %%r9, %c[r9](%0) \n\t" | |
4084 | "mov %%r10, %c[r10](%0) \n\t" | |
4085 | "mov %%r11, %c[r11](%0) \n\t" | |
4086 | "mov %%r12, %c[r12](%0) \n\t" | |
4087 | "mov %%r13, %c[r13](%0) \n\t" | |
4088 | "mov %%r14, %c[r14](%0) \n\t" | |
4089 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 4090 | #endif |
c801949d AK |
4091 | "mov %%cr2, %%"R"ax \n\t" |
4092 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
4093 | ||
1c696d0e | 4094 | "pop %%"R"bp; pop %%"R"dx \n\t" |
e08aa78a AK |
4095 | "setbe %c[fail](%0) \n\t" |
4096 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
4097 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
4098 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 4099 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
4100 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
4101 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
4102 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
4103 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
4104 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
4105 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
4106 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 4107 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
4108 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
4109 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
4110 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
4111 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
4112 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
4113 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
4114 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
4115 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 4116 | #endif |
40712fae AK |
4117 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
4118 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 | 4119 | : "cc", "memory" |
07d6f555 | 4120 | , R"ax", R"bx", R"di", R"si" |
c2036300 | 4121 | #ifdef CONFIG_X86_64 |
c2036300 LV |
4122 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
4123 | #endif | |
4124 | ); | |
6aa8b732 | 4125 | |
6de4f3ad | 4126 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
aff48baa AK |
4127 | | (1 << VCPU_EXREG_PDPTR) |
4128 | | (1 << VCPU_EXREG_CR3)); | |
5fdbf976 MT |
4129 | vcpu->arch.regs_dirty = 0; |
4130 | ||
1155f76a AK |
4131 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
4132 | ||
d77c26fc | 4133 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 4134 | vmx->launched = 1; |
1b6269db | 4135 | |
51aa01d1 AK |
4136 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
4137 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
4138 | ||
4139 | vmx_complete_atomic_exit(vmx); | |
4140 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 4141 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
4142 | } |
4143 | ||
c801949d AK |
4144 | #undef R |
4145 | #undef Q | |
4146 | ||
6aa8b732 AK |
4147 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
4148 | { | |
a2fa3e9f GH |
4149 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4150 | ||
4151 | if (vmx->vmcs) { | |
543e4243 | 4152 | vcpu_clear(vmx); |
a2fa3e9f GH |
4153 | free_vmcs(vmx->vmcs); |
4154 | vmx->vmcs = NULL; | |
6aa8b732 AK |
4155 | } |
4156 | } | |
4157 | ||
4158 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
4159 | { | |
fb3f0f51 RR |
4160 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4161 | ||
cdbecfc3 | 4162 | free_vpid(vmx); |
6aa8b732 | 4163 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
4164 | kfree(vmx->guest_msrs); |
4165 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 4166 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
4167 | } |
4168 | ||
4610c9cc DX |
4169 | static inline void vmcs_init(struct vmcs *vmcs) |
4170 | { | |
4171 | u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id())); | |
4172 | ||
4173 | if (!vmm_exclusive) | |
4174 | kvm_cpu_vmxon(phys_addr); | |
4175 | ||
4176 | vmcs_clear(vmcs); | |
4177 | ||
4178 | if (!vmm_exclusive) | |
4179 | kvm_cpu_vmxoff(); | |
4180 | } | |
4181 | ||
fb3f0f51 | 4182 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 4183 | { |
fb3f0f51 | 4184 | int err; |
c16f862d | 4185 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 4186 | int cpu; |
6aa8b732 | 4187 | |
a2fa3e9f | 4188 | if (!vmx) |
fb3f0f51 RR |
4189 | return ERR_PTR(-ENOMEM); |
4190 | ||
2384d2b3 SY |
4191 | allocate_vpid(vmx); |
4192 | ||
fb3f0f51 RR |
4193 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
4194 | if (err) | |
4195 | goto free_vcpu; | |
965b58a5 | 4196 | |
a2fa3e9f | 4197 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
4198 | if (!vmx->guest_msrs) { |
4199 | err = -ENOMEM; | |
4200 | goto uninit_vcpu; | |
4201 | } | |
965b58a5 | 4202 | |
a2fa3e9f GH |
4203 | vmx->vmcs = alloc_vmcs(); |
4204 | if (!vmx->vmcs) | |
fb3f0f51 | 4205 | goto free_msrs; |
a2fa3e9f | 4206 | |
4610c9cc | 4207 | vmcs_init(vmx->vmcs); |
a2fa3e9f | 4208 | |
15ad7146 AK |
4209 | cpu = get_cpu(); |
4210 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 4211 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 4212 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 4213 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 4214 | put_cpu(); |
fb3f0f51 RR |
4215 | if (err) |
4216 | goto free_vmcs; | |
5e4a0b3c MT |
4217 | if (vm_need_virtualize_apic_accesses(kvm)) |
4218 | if (alloc_apic_access_page(kvm) != 0) | |
4219 | goto free_vmcs; | |
fb3f0f51 | 4220 | |
b927a3ce SY |
4221 | if (enable_ept) { |
4222 | if (!kvm->arch.ept_identity_map_addr) | |
4223 | kvm->arch.ept_identity_map_addr = | |
4224 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
93ea5388 | 4225 | err = -ENOMEM; |
b7ebfb05 SY |
4226 | if (alloc_identity_pagetable(kvm) != 0) |
4227 | goto free_vmcs; | |
93ea5388 GN |
4228 | if (!init_rmode_identity_map(kvm)) |
4229 | goto free_vmcs; | |
b927a3ce | 4230 | } |
b7ebfb05 | 4231 | |
fb3f0f51 RR |
4232 | return &vmx->vcpu; |
4233 | ||
4234 | free_vmcs: | |
4235 | free_vmcs(vmx->vmcs); | |
4236 | free_msrs: | |
fb3f0f51 RR |
4237 | kfree(vmx->guest_msrs); |
4238 | uninit_vcpu: | |
4239 | kvm_vcpu_uninit(&vmx->vcpu); | |
4240 | free_vcpu: | |
cdbecfc3 | 4241 | free_vpid(vmx); |
a4770347 | 4242 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 4243 | return ERR_PTR(err); |
6aa8b732 AK |
4244 | } |
4245 | ||
002c7f7c YS |
4246 | static void __init vmx_check_processor_compat(void *rtn) |
4247 | { | |
4248 | struct vmcs_config vmcs_conf; | |
4249 | ||
4250 | *(int *)rtn = 0; | |
4251 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
4252 | *(int *)rtn = -EIO; | |
4253 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
4254 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
4255 | smp_processor_id()); | |
4256 | *(int *)rtn = -EIO; | |
4257 | } | |
4258 | } | |
4259 | ||
67253af5 SY |
4260 | static int get_ept_level(void) |
4261 | { | |
4262 | return VMX_EPT_DEFAULT_GAW + 1; | |
4263 | } | |
4264 | ||
4b12f0de | 4265 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 4266 | { |
4b12f0de SY |
4267 | u64 ret; |
4268 | ||
522c68c4 SY |
4269 | /* For VT-d and EPT combination |
4270 | * 1. MMIO: always map as UC | |
4271 | * 2. EPT with VT-d: | |
4272 | * a. VT-d without snooping control feature: can't guarantee the | |
4273 | * result, try to trust guest. | |
4274 | * b. VT-d with snooping control feature: snooping control feature of | |
4275 | * VT-d engine can guarantee the cache correctness. Just set it | |
4276 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 4277 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
4278 | * consistent with host MTRR |
4279 | */ | |
4b12f0de SY |
4280 | if (is_mmio) |
4281 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | |
522c68c4 SY |
4282 | else if (vcpu->kvm->arch.iommu_domain && |
4283 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY)) | |
4284 | ret = kvm_get_guest_memory_type(vcpu, gfn) << | |
4285 | VMX_EPT_MT_EPTE_SHIFT; | |
4b12f0de | 4286 | else |
522c68c4 | 4287 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) |
a19a6d11 | 4288 | | VMX_EPT_IPAT_BIT; |
4b12f0de SY |
4289 | |
4290 | return ret; | |
64d4d521 SY |
4291 | } |
4292 | ||
f4c9e87c AK |
4293 | #define _ER(x) { EXIT_REASON_##x, #x } |
4294 | ||
229456fc | 4295 | static const struct trace_print_flags vmx_exit_reasons_str[] = { |
f4c9e87c AK |
4296 | _ER(EXCEPTION_NMI), |
4297 | _ER(EXTERNAL_INTERRUPT), | |
4298 | _ER(TRIPLE_FAULT), | |
4299 | _ER(PENDING_INTERRUPT), | |
4300 | _ER(NMI_WINDOW), | |
4301 | _ER(TASK_SWITCH), | |
4302 | _ER(CPUID), | |
4303 | _ER(HLT), | |
4304 | _ER(INVLPG), | |
4305 | _ER(RDPMC), | |
4306 | _ER(RDTSC), | |
4307 | _ER(VMCALL), | |
4308 | _ER(VMCLEAR), | |
4309 | _ER(VMLAUNCH), | |
4310 | _ER(VMPTRLD), | |
4311 | _ER(VMPTRST), | |
4312 | _ER(VMREAD), | |
4313 | _ER(VMRESUME), | |
4314 | _ER(VMWRITE), | |
4315 | _ER(VMOFF), | |
4316 | _ER(VMON), | |
4317 | _ER(CR_ACCESS), | |
4318 | _ER(DR_ACCESS), | |
4319 | _ER(IO_INSTRUCTION), | |
4320 | _ER(MSR_READ), | |
4321 | _ER(MSR_WRITE), | |
4322 | _ER(MWAIT_INSTRUCTION), | |
4323 | _ER(MONITOR_INSTRUCTION), | |
4324 | _ER(PAUSE_INSTRUCTION), | |
4325 | _ER(MCE_DURING_VMENTRY), | |
4326 | _ER(TPR_BELOW_THRESHOLD), | |
4327 | _ER(APIC_ACCESS), | |
4328 | _ER(EPT_VIOLATION), | |
4329 | _ER(EPT_MISCONFIG), | |
4330 | _ER(WBINVD), | |
229456fc MT |
4331 | { -1, NULL } |
4332 | }; | |
4333 | ||
f4c9e87c AK |
4334 | #undef _ER |
4335 | ||
17cc3935 | 4336 | static int vmx_get_lpage_level(void) |
344f414f | 4337 | { |
878403b7 SY |
4338 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
4339 | return PT_DIRECTORY_LEVEL; | |
4340 | else | |
4341 | /* For shadow and EPT supported 1GB page */ | |
4342 | return PT_PDPE_LEVEL; | |
344f414f JR |
4343 | } |
4344 | ||
0e851880 SY |
4345 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
4346 | { | |
4e47c7a6 SY |
4347 | struct kvm_cpuid_entry2 *best; |
4348 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4349 | u32 exec_control; | |
4350 | ||
4351 | vmx->rdtscp_enabled = false; | |
4352 | if (vmx_rdtscp_supported()) { | |
4353 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
4354 | if (exec_control & SECONDARY_EXEC_RDTSCP) { | |
4355 | best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
4356 | if (best && (best->edx & bit(X86_FEATURE_RDTSCP))) | |
4357 | vmx->rdtscp_enabled = true; | |
4358 | else { | |
4359 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
4360 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
4361 | exec_control); | |
4362 | } | |
4363 | } | |
4364 | } | |
0e851880 SY |
4365 | } |
4366 | ||
d4330ef2 JR |
4367 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
4368 | { | |
4369 | } | |
4370 | ||
cbdd1bea | 4371 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
4372 | .cpu_has_kvm_support = cpu_has_kvm_support, |
4373 | .disabled_by_bios = vmx_disabled_by_bios, | |
4374 | .hardware_setup = hardware_setup, | |
4375 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 4376 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
4377 | .hardware_enable = hardware_enable, |
4378 | .hardware_disable = hardware_disable, | |
04547156 | 4379 | .cpu_has_accelerated_tpr = report_flexpriority, |
6aa8b732 AK |
4380 | |
4381 | .vcpu_create = vmx_create_vcpu, | |
4382 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 4383 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 4384 | |
04d2cc77 | 4385 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
4386 | .vcpu_load = vmx_vcpu_load, |
4387 | .vcpu_put = vmx_vcpu_put, | |
4388 | ||
4389 | .set_guest_debug = set_guest_debug, | |
4390 | .get_msr = vmx_get_msr, | |
4391 | .set_msr = vmx_set_msr, | |
4392 | .get_segment_base = vmx_get_segment_base, | |
4393 | .get_segment = vmx_get_segment, | |
4394 | .set_segment = vmx_set_segment, | |
2e4d2653 | 4395 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 4396 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 4397 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 4398 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 4399 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 4400 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
4401 | .set_cr3 = vmx_set_cr3, |
4402 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 4403 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
4404 | .get_idt = vmx_get_idt, |
4405 | .set_idt = vmx_set_idt, | |
4406 | .get_gdt = vmx_get_gdt, | |
4407 | .set_gdt = vmx_set_gdt, | |
020df079 | 4408 | .set_dr7 = vmx_set_dr7, |
5fdbf976 | 4409 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
4410 | .get_rflags = vmx_get_rflags, |
4411 | .set_rflags = vmx_set_rflags, | |
ebcbab4c | 4412 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 4413 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
4414 | |
4415 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 4416 | |
6aa8b732 | 4417 | .run = vmx_vcpu_run, |
6062d012 | 4418 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 4419 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
4420 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
4421 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 4422 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 4423 | .set_irq = vmx_inject_irq, |
95ba8273 | 4424 | .set_nmi = vmx_inject_nmi, |
298101da | 4425 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 4426 | .cancel_injection = vmx_cancel_injection, |
78646121 | 4427 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 4428 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
4429 | .get_nmi_mask = vmx_get_nmi_mask, |
4430 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
4431 | .enable_nmi_window = enable_nmi_window, |
4432 | .enable_irq_window = enable_irq_window, | |
4433 | .update_cr8_intercept = update_cr8_intercept, | |
95ba8273 | 4434 | |
cbc94022 | 4435 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 4436 | .get_tdp_level = get_ept_level, |
4b12f0de | 4437 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 4438 | |
586f9607 | 4439 | .get_exit_info = vmx_get_exit_info, |
229456fc | 4440 | .exit_reasons_str = vmx_exit_reasons_str, |
586f9607 | 4441 | |
17cc3935 | 4442 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
4443 | |
4444 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
4445 | |
4446 | .rdtscp_supported = vmx_rdtscp_supported, | |
d4330ef2 JR |
4447 | |
4448 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
4449 | |
4450 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a ZA |
4451 | |
4452 | .write_tsc_offset = vmx_write_tsc_offset, | |
e48672fa | 4453 | .adjust_tsc_offset = vmx_adjust_tsc_offset, |
1c97f0a0 JR |
4454 | |
4455 | .set_tdp_cr3 = vmx_set_cr3, | |
6aa8b732 AK |
4456 | }; |
4457 | ||
4458 | static int __init vmx_init(void) | |
4459 | { | |
26bb0981 AK |
4460 | int r, i; |
4461 | ||
4462 | rdmsrl_safe(MSR_EFER, &host_efer); | |
4463 | ||
4464 | for (i = 0; i < NR_VMX_MSR; ++i) | |
4465 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
fdef3ad1 | 4466 | |
3e7c73e9 | 4467 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
4468 | if (!vmx_io_bitmap_a) |
4469 | return -ENOMEM; | |
4470 | ||
3e7c73e9 | 4471 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
4472 | if (!vmx_io_bitmap_b) { |
4473 | r = -ENOMEM; | |
4474 | goto out; | |
4475 | } | |
4476 | ||
5897297b AK |
4477 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); |
4478 | if (!vmx_msr_bitmap_legacy) { | |
25c5f225 SY |
4479 | r = -ENOMEM; |
4480 | goto out1; | |
4481 | } | |
4482 | ||
5897297b AK |
4483 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); |
4484 | if (!vmx_msr_bitmap_longmode) { | |
4485 | r = -ENOMEM; | |
4486 | goto out2; | |
4487 | } | |
4488 | ||
fdef3ad1 HQ |
4489 | /* |
4490 | * Allow direct access to the PC debug port (it is often used for I/O | |
4491 | * delays, but the vmexits simply slow things down). | |
4492 | */ | |
3e7c73e9 AK |
4493 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
4494 | clear_bit(0x80, vmx_io_bitmap_a); | |
fdef3ad1 | 4495 | |
3e7c73e9 | 4496 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); |
fdef3ad1 | 4497 | |
5897297b AK |
4498 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); |
4499 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
25c5f225 | 4500 | |
2384d2b3 SY |
4501 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
4502 | ||
0ee75bea AK |
4503 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
4504 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 4505 | if (r) |
5897297b | 4506 | goto out3; |
25c5f225 | 4507 | |
5897297b AK |
4508 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
4509 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
4510 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
4511 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
4512 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
4513 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
fdef3ad1 | 4514 | |
089d034e | 4515 | if (enable_ept) { |
1439442c | 4516 | bypass_guest_pf = 0; |
534e38b4 | 4517 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
4b12f0de | 4518 | VMX_EPT_EXECUTABLE_MASK); |
5fdbcb9d SY |
4519 | kvm_enable_tdp(); |
4520 | } else | |
4521 | kvm_disable_tdp(); | |
1439442c | 4522 | |
c7addb90 AK |
4523 | if (bypass_guest_pf) |
4524 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
4525 | ||
fdef3ad1 HQ |
4526 | return 0; |
4527 | ||
5897297b AK |
4528 | out3: |
4529 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
25c5f225 | 4530 | out2: |
5897297b | 4531 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
fdef3ad1 | 4532 | out1: |
3e7c73e9 | 4533 | free_page((unsigned long)vmx_io_bitmap_b); |
fdef3ad1 | 4534 | out: |
3e7c73e9 | 4535 | free_page((unsigned long)vmx_io_bitmap_a); |
fdef3ad1 | 4536 | return r; |
6aa8b732 AK |
4537 | } |
4538 | ||
4539 | static void __exit vmx_exit(void) | |
4540 | { | |
5897297b AK |
4541 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
4542 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
3e7c73e9 AK |
4543 | free_page((unsigned long)vmx_io_bitmap_b); |
4544 | free_page((unsigned long)vmx_io_bitmap_a); | |
fdef3ad1 | 4545 | |
cb498ea2 | 4546 | kvm_exit(); |
6aa8b732 AK |
4547 | } |
4548 | ||
4549 | module_init(vmx_init) | |
4550 | module_exit(vmx_exit) |