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KVM: nVMX: Add KVM_REQ_IMMEDIATE_EXIT
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
d7cd9796 42#include <asm/perf_event.h>
6aa8b732 43
229456fc
MT		 44#include "trace.h"
45
4ecac3fd 46#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 47#define __ex_clear(x, reg) \
48 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 49
6aa8b732
AK		 50MODULE_AUTHOR("Qumranet");
51MODULE_LICENSE("GPL");
52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
58fbbf26
KT		 75static int __read_mostly fasteoi = 1;
76module_param(fasteoi, bool, S_IRUGO);
77
801d3424
NHE		 78/*
79 * If nested=1, nested virtualization is supported, i.e., guests may use
80 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
81 * use VMX instructions.
82 */
83static int __read_mostly nested = 0;
84module_param(nested, bool, S_IRUGO);
85
cdc0e244
AK		 86#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
87 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
88#define KVM_GUEST_CR0_MASK \
89 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 91 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 92#define KVM_VM_CR0_ALWAYS_ON \
93 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 94#define KVM_CR4_GUEST_OWNED_BITS \
95 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
96 | X86_CR4_OSXMMEXCPT)
97
cdc0e244
AK		 98#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
99#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100
78ac8b47
AK		 101#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
102
4b8d54f9
ZE		 103/*
104 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
105 * ple_gap: upper bound on the amount of time between two successive
106 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 107 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 108 * ple_window: upper bound on the amount of time a guest is allowed to execute
109 * in a PAUSE loop. Tests indicate that most spinlocks are held for
110 * less than 2^12 cycles
111 * Time is measured based on a counter that runs at the same rate as the TSC,
112 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 */
00c25bce 114#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 115#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
116static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
117module_param(ple_gap, int, S_IRUGO);
118
119static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
120module_param(ple_window, int, S_IRUGO);
121
8bf00a52 122#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 123#define VMCS02_POOL_SIZE 1
61d2ef2c 124
a2fa3e9f
GH		 125struct vmcs {
126 u32 revision_id;
127 u32 abort;
128 char data[0];
129};
130
d462b819
NHE		 131/*
132 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
133 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
134 * loaded on this CPU (so we can clear them if the CPU goes down).
135 */
136struct loaded_vmcs {
137 struct vmcs *vmcs;
138 int cpu;
139 int launched;
140 struct list_head loaded_vmcss_on_cpu_link;
141};
142
26bb0981
AK		 143struct shared_msr_entry {
144 unsigned index;
145 u64 data;
d5696725 146 u64 mask;
26bb0981
AK		 147};
148
a9d30f33
NHE		 149/*
150 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
151 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
152 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
153 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
154 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
155 * More than one of these structures may exist, if L1 runs multiple L2 guests.
156 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
157 * underlying hardware which will be used to run L2.
158 * This structure is packed to ensure that its layout is identical across
159 * machines (necessary for live migration).
160 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 */
22bd0358 162typedef u64 natural_width;
a9d30f33
NHE		 163struct __packed vmcs12 {
164 /* According to the Intel spec, a VMCS region must start with the
165 * following two fields. Then follow implementation-specific data.
166 */
167 u32 revision_id;
168 u32 abort;
22bd0358 169
27d6c865
NHE		 170 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
171 u32 padding[7]; /* room for future expansion */
172
22bd0358
NHE		 173 u64 io_bitmap_a;
174 u64 io_bitmap_b;
175 u64 msr_bitmap;
176 u64 vm_exit_msr_store_addr;
177 u64 vm_exit_msr_load_addr;
178 u64 vm_entry_msr_load_addr;
179 u64 tsc_offset;
180 u64 virtual_apic_page_addr;
181 u64 apic_access_addr;
182 u64 ept_pointer;
183 u64 guest_physical_address;
184 u64 vmcs_link_pointer;
185 u64 guest_ia32_debugctl;
186 u64 guest_ia32_pat;
187 u64 guest_ia32_efer;
188 u64 guest_ia32_perf_global_ctrl;
189 u64 guest_pdptr0;
190 u64 guest_pdptr1;
191 u64 guest_pdptr2;
192 u64 guest_pdptr3;
193 u64 host_ia32_pat;
194 u64 host_ia32_efer;
195 u64 host_ia32_perf_global_ctrl;
196 u64 padding64[8]; /* room for future expansion */
197 /*
198 * To allow migration of L1 (complete with its L2 guests) between
199 * machines of different natural widths (32 or 64 bit), we cannot have
200 * unsigned long fields with no explict size. We use u64 (aliased
201 * natural_width) instead. Luckily, x86 is little-endian.
202 */
203 natural_width cr0_guest_host_mask;
204 natural_width cr4_guest_host_mask;
205 natural_width cr0_read_shadow;
206 natural_width cr4_read_shadow;
207 natural_width cr3_target_value0;
208 natural_width cr3_target_value1;
209 natural_width cr3_target_value2;
210 natural_width cr3_target_value3;
211 natural_width exit_qualification;
212 natural_width guest_linear_address;
213 natural_width guest_cr0;
214 natural_width guest_cr3;
215 natural_width guest_cr4;
216 natural_width guest_es_base;
217 natural_width guest_cs_base;
218 natural_width guest_ss_base;
219 natural_width guest_ds_base;
220 natural_width guest_fs_base;
221 natural_width guest_gs_base;
222 natural_width guest_ldtr_base;
223 natural_width guest_tr_base;
224 natural_width guest_gdtr_base;
225 natural_width guest_idtr_base;
226 natural_width guest_dr7;
227 natural_width guest_rsp;
228 natural_width guest_rip;
229 natural_width guest_rflags;
230 natural_width guest_pending_dbg_exceptions;
231 natural_width guest_sysenter_esp;
232 natural_width guest_sysenter_eip;
233 natural_width host_cr0;
234 natural_width host_cr3;
235 natural_width host_cr4;
236 natural_width host_fs_base;
237 natural_width host_gs_base;
238 natural_width host_tr_base;
239 natural_width host_gdtr_base;
240 natural_width host_idtr_base;
241 natural_width host_ia32_sysenter_esp;
242 natural_width host_ia32_sysenter_eip;
243 natural_width host_rsp;
244 natural_width host_rip;
245 natural_width paddingl[8]; /* room for future expansion */
246 u32 pin_based_vm_exec_control;
247 u32 cpu_based_vm_exec_control;
248 u32 exception_bitmap;
249 u32 page_fault_error_code_mask;
250 u32 page_fault_error_code_match;
251 u32 cr3_target_count;
252 u32 vm_exit_controls;
253 u32 vm_exit_msr_store_count;
254 u32 vm_exit_msr_load_count;
255 u32 vm_entry_controls;
256 u32 vm_entry_msr_load_count;
257 u32 vm_entry_intr_info_field;
258 u32 vm_entry_exception_error_code;
259 u32 vm_entry_instruction_len;
260 u32 tpr_threshold;
261 u32 secondary_vm_exec_control;
262 u32 vm_instruction_error;
263 u32 vm_exit_reason;
264 u32 vm_exit_intr_info;
265 u32 vm_exit_intr_error_code;
266 u32 idt_vectoring_info_field;
267 u32 idt_vectoring_error_code;
268 u32 vm_exit_instruction_len;
269 u32 vmx_instruction_info;
270 u32 guest_es_limit;
271 u32 guest_cs_limit;
272 u32 guest_ss_limit;
273 u32 guest_ds_limit;
274 u32 guest_fs_limit;
275 u32 guest_gs_limit;
276 u32 guest_ldtr_limit;
277 u32 guest_tr_limit;
278 u32 guest_gdtr_limit;
279 u32 guest_idtr_limit;
280 u32 guest_es_ar_bytes;
281 u32 guest_cs_ar_bytes;
282 u32 guest_ss_ar_bytes;
283 u32 guest_ds_ar_bytes;
284 u32 guest_fs_ar_bytes;
285 u32 guest_gs_ar_bytes;
286 u32 guest_ldtr_ar_bytes;
287 u32 guest_tr_ar_bytes;
288 u32 guest_interruptibility_info;
289 u32 guest_activity_state;
290 u32 guest_sysenter_cs;
291 u32 host_ia32_sysenter_cs;
292 u32 padding32[8]; /* room for future expansion */
293 u16 virtual_processor_id;
294 u16 guest_es_selector;
295 u16 guest_cs_selector;
296 u16 guest_ss_selector;
297 u16 guest_ds_selector;
298 u16 guest_fs_selector;
299 u16 guest_gs_selector;
300 u16 guest_ldtr_selector;
301 u16 guest_tr_selector;
302 u16 host_es_selector;
303 u16 host_cs_selector;
304 u16 host_ss_selector;
305 u16 host_ds_selector;
306 u16 host_fs_selector;
307 u16 host_gs_selector;
308 u16 host_tr_selector;
a9d30f33
NHE		 309};
310
311/*
312 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
313 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
314 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 */
316#define VMCS12_REVISION 0x11e57ed0
317
318/*
319 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
320 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
321 * current implementation, 4K are reserved to avoid future complications.
322 */
323#define VMCS12_SIZE 0x1000
324
ff2f6fe9
NHE		 325/* Used to remember the last vmcs02 used for some recently used vmcs12s */
326struct vmcs02_list {
327 struct list_head list;
328 gpa_t vmptr;
329 struct loaded_vmcs vmcs02;
330};
331
ec378aee
NHE		 332/*
333 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
334 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
335 */
336struct nested_vmx {
337 /* Has the level1 guest done vmxon? */
338 bool vmxon;
a9d30f33
NHE		 339
340 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 gpa_t current_vmptr;
342 /* The host-usable pointer to the above */
343 struct page *current_vmcs12_page;
344 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 345
346 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
347 struct list_head vmcs02_pool;
348 int vmcs02_num;
fe3ef05c 349 u64 vmcs01_tsc_offset;
644d711a
NHE		 350 /* L2 must run next, and mustn't decide to exit to L1. */
351 bool nested_run_pending;
fe3ef05c
NHE		 352 /*
353 * Guest pages referred to in vmcs02 with host-physical pointers, so
354 * we must keep them pinned while L2 runs.
355 */
356 struct page *apic_access_page;
ec378aee
NHE		 357};
358
a2fa3e9f 359struct vcpu_vmx {
fb3f0f51 360 struct kvm_vcpu vcpu;
313dbd49 361 unsigned long host_rsp;
29bd8a78 362 u8 fail;
69c73028 363 u8 cpl;
9d58b931 364 bool nmi_known_unmasked;
51aa01d1 365 u32 exit_intr_info;
1155f76a 366 u32 idt_vectoring_info;
6de12732 367 ulong rflags;
26bb0981 368 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 369 int nmsrs;
370 int save_nmsrs;
a2fa3e9f 371#ifdef CONFIG_X86_64
44ea2b17
AK		 372 u64 msr_host_kernel_gs_base;
373 u64 msr_guest_kernel_gs_base;
a2fa3e9f 374#endif
d462b819
NHE		 375 /*
376 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
377 * non-nested (L1) guest, it always points to vmcs01. For a nested
378 * guest (L2), it points to a different VMCS.
379 */
380 struct loaded_vmcs vmcs01;
381 struct loaded_vmcs *loaded_vmcs;
382 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 383 struct msr_autoload {
384 unsigned nr;
385 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
386 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
387 } msr_autoload;
a2fa3e9f
GH		 388 struct {
389 int loaded;
390 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 391 int gs_ldt_reload_needed;
392 int fs_reload_needed;
d77c26fc 393 } host_state;
9c8cba37 394 struct {
7ffd92c5 395 int vm86_active;
78ac8b47 396 ulong save_rflags;
7ffd92c5
AK		 397 struct kvm_save_segment {
398 u16 selector;
399 unsigned long base;
400 u32 limit;
401 u32 ar;
402 } tr, es, ds, fs, gs;
9c8cba37 403 } rmode;
2fb92db1
AK		 404 struct {
405 u32 bitmask; /* 4 bits per segment (1 bit per field) */
406 struct kvm_save_segment seg[8];
407 } segment_cache;
2384d2b3 408 int vpid;
04fa4d32 409 bool emulation_required;
3b86cd99
JK		 410
411 /* Support for vnmi-less CPUs */
412 int soft_vnmi_blocked;
413 ktime_t entry_time;
414 s64 vnmi_blocked_time;
a0861c02 415 u32 exit_reason;
4e47c7a6
SY		 416
417 bool rdtscp_enabled;
ec378aee
NHE		 418
419 /* Support for a guest hypervisor (nested VMX) */
420 struct nested_vmx nested;
a2fa3e9f
GH		 421};
422
2fb92db1
AK		 423enum segment_cache_field {
424 SEG_FIELD_SEL = 0,
425 SEG_FIELD_BASE = 1,
426 SEG_FIELD_LIMIT = 2,
427 SEG_FIELD_AR = 3,
428
429 SEG_FIELD_NR = 4
430};
431
a2fa3e9f
GH		 432static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
433{
fb3f0f51 434 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 435}
436
22bd0358
NHE		 437#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
438#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
439#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
440 [number##_HIGH] = VMCS12_OFFSET(name)+4
441
442static unsigned short vmcs_field_to_offset_table[] = {
443 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
444 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
445 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
446 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
447 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
448 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
449 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
450 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
451 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
452 FIELD(HOST_ES_SELECTOR, host_es_selector),
453 FIELD(HOST_CS_SELECTOR, host_cs_selector),
454 FIELD(HOST_SS_SELECTOR, host_ss_selector),
455 FIELD(HOST_DS_SELECTOR, host_ds_selector),
456 FIELD(HOST_FS_SELECTOR, host_fs_selector),
457 FIELD(HOST_GS_SELECTOR, host_gs_selector),
458 FIELD(HOST_TR_SELECTOR, host_tr_selector),
459 FIELD64(IO_BITMAP_A, io_bitmap_a),
460 FIELD64(IO_BITMAP_B, io_bitmap_b),
461 FIELD64(MSR_BITMAP, msr_bitmap),
462 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
463 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
464 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
465 FIELD64(TSC_OFFSET, tsc_offset),
466 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
467 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
468 FIELD64(EPT_POINTER, ept_pointer),
469 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
470 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
471 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
472 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
473 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
474 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
475 FIELD64(GUEST_PDPTR0, guest_pdptr0),
476 FIELD64(GUEST_PDPTR1, guest_pdptr1),
477 FIELD64(GUEST_PDPTR2, guest_pdptr2),
478 FIELD64(GUEST_PDPTR3, guest_pdptr3),
479 FIELD64(HOST_IA32_PAT, host_ia32_pat),
480 FIELD64(HOST_IA32_EFER, host_ia32_efer),
481 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
482 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
483 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
484 FIELD(EXCEPTION_BITMAP, exception_bitmap),
485 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
486 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
487 FIELD(CR3_TARGET_COUNT, cr3_target_count),
488 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
489 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
490 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
491 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
492 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
493 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
494 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
495 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
496 FIELD(TPR_THRESHOLD, tpr_threshold),
497 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
498 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
499 FIELD(VM_EXIT_REASON, vm_exit_reason),
500 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
501 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
502 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
503 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
504 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
505 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
506 FIELD(GUEST_ES_LIMIT, guest_es_limit),
507 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
508 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
509 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
510 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
511 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
512 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
513 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
514 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
515 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
516 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
517 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
518 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
519 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
520 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
521 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
522 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
523 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
524 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
525 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
526 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
527 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
528 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
529 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
530 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
531 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
532 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
533 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
534 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
535 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
536 FIELD(EXIT_QUALIFICATION, exit_qualification),
537 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
538 FIELD(GUEST_CR0, guest_cr0),
539 FIELD(GUEST_CR3, guest_cr3),
540 FIELD(GUEST_CR4, guest_cr4),
541 FIELD(GUEST_ES_BASE, guest_es_base),
542 FIELD(GUEST_CS_BASE, guest_cs_base),
543 FIELD(GUEST_SS_BASE, guest_ss_base),
544 FIELD(GUEST_DS_BASE, guest_ds_base),
545 FIELD(GUEST_FS_BASE, guest_fs_base),
546 FIELD(GUEST_GS_BASE, guest_gs_base),
547 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
548 FIELD(GUEST_TR_BASE, guest_tr_base),
549 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
550 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
551 FIELD(GUEST_DR7, guest_dr7),
552 FIELD(GUEST_RSP, guest_rsp),
553 FIELD(GUEST_RIP, guest_rip),
554 FIELD(GUEST_RFLAGS, guest_rflags),
555 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
556 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
557 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
558 FIELD(HOST_CR0, host_cr0),
559 FIELD(HOST_CR3, host_cr3),
560 FIELD(HOST_CR4, host_cr4),
561 FIELD(HOST_FS_BASE, host_fs_base),
562 FIELD(HOST_GS_BASE, host_gs_base),
563 FIELD(HOST_TR_BASE, host_tr_base),
564 FIELD(HOST_GDTR_BASE, host_gdtr_base),
565 FIELD(HOST_IDTR_BASE, host_idtr_base),
566 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
567 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
568 FIELD(HOST_RSP, host_rsp),
569 FIELD(HOST_RIP, host_rip),
570};
571static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
572
573static inline short vmcs_field_to_offset(unsigned long field)
574{
575 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
576 return -1;
577 return vmcs_field_to_offset_table[field];
578}
579
a9d30f33
NHE		 580static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
581{
582 return to_vmx(vcpu)->nested.current_vmcs12;
583}
584
585static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
586{
587 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
588 if (is_error_page(page)) {
589 kvm_release_page_clean(page);
590 return NULL;
591 }
592 return page;
593}
594
595static void nested_release_page(struct page *page)
596{
597 kvm_release_page_dirty(page);
598}
599
600static void nested_release_page_clean(struct page *page)
601{
602 kvm_release_page_clean(page);
603}
604
4e1096d2 605static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 606static void kvm_cpu_vmxon(u64 addr);
607static void kvm_cpu_vmxoff(void);
aff48baa 608static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 609static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 610
6aa8b732
AK		 611static DEFINE_PER_CPU(struct vmcs *, vmxarea);
612static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 613/*
614 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
615 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616 */
617static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 618static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 619
3e7c73e9
AK		 620static unsigned long *vmx_io_bitmap_a;
621static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 622static unsigned long *vmx_msr_bitmap_legacy;
623static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 624
110312c8 625static bool cpu_has_load_ia32_efer;
8bf00a52 626static bool cpu_has_load_perf_global_ctrl;
110312c8 627
2384d2b3
SY		 628static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
629static DEFINE_SPINLOCK(vmx_vpid_lock);
630
1c3d14fe 631static struct vmcs_config {
6aa8b732
AK		 632 int size;
633 int order;
634 u32 revision_id;
1c3d14fe
YS		 635 u32 pin_based_exec_ctrl;
636 u32 cpu_based_exec_ctrl;
f78e0e2e 637 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 638 u32 vmexit_ctrl;
639 u32 vmentry_ctrl;
640} vmcs_config;
6aa8b732 641
efff9e53 642static struct vmx_capability {
d56f546d
SY		 643 u32 ept;
644 u32 vpid;
645} vmx_capability;
646
6aa8b732
AK		 647#define VMX_SEGMENT_FIELD(seg) \
648 [VCPU_SREG_##seg] = { \
649 .selector = GUEST_##seg##_SELECTOR, \
650 .base = GUEST_##seg##_BASE, \
651 .limit = GUEST_##seg##_LIMIT, \
652 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 }
654
655static struct kvm_vmx_segment_field {
656 unsigned selector;
657 unsigned base;
658 unsigned limit;
659 unsigned ar_bytes;
660} kvm_vmx_segment_fields[] = {
661 VMX_SEGMENT_FIELD(CS),
662 VMX_SEGMENT_FIELD(DS),
663 VMX_SEGMENT_FIELD(ES),
664 VMX_SEGMENT_FIELD(FS),
665 VMX_SEGMENT_FIELD(GS),
666 VMX_SEGMENT_FIELD(SS),
667 VMX_SEGMENT_FIELD(TR),
668 VMX_SEGMENT_FIELD(LDTR),
669};
670
26bb0981
AK		 671static u64 host_efer;
672
6de4f3ad
AK		 673static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
674
4d56c8a7 675/*
8c06585d 676 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 677 * away by decrementing the array size.
678 */
6aa8b732 679static const u32 vmx_msr_index[] = {
05b3e0c2 680#ifdef CONFIG_X86_64
44ea2b17 681 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 682#endif
8c06585d 683 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 684};
9d8f549d 685#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 686
31299944 687static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 688{
689 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
690 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 691 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 692}
693
31299944 694static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 695{
696 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
697 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 698 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 699}
700
31299944 701static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 702{
703 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 705 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 706}
707
31299944 708static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 709{
710 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
711 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
712}
713
31299944 714static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 715{
716 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
717 INTR_INFO_VALID_MASK)) ==
718 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
719}
720
31299944 721static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 722{
04547156 723 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 724}
725
31299944 726static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 727{
04547156 728 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 729}
730
31299944 731static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 732{
04547156 733 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 734}
735
31299944 736static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 737{
04547156
SY		 738 return vmcs_config.cpu_based_exec_ctrl &
739 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 740}
741
774ead3a 742static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 743{
04547156
SY		 744 return vmcs_config.cpu_based_2nd_exec_ctrl &
745 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
746}
747
748static inline bool cpu_has_vmx_flexpriority(void)
749{
750 return cpu_has_vmx_tpr_shadow() &&
751 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 752}
753
e799794e
MT		 754static inline bool cpu_has_vmx_ept_execute_only(void)
755{
31299944 756 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 757}
758
759static inline bool cpu_has_vmx_eptp_uncacheable(void)
760{
31299944 761 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 762}
763
764static inline bool cpu_has_vmx_eptp_writeback(void)
765{
31299944 766 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 767}
768
769static inline bool cpu_has_vmx_ept_2m_page(void)
770{
31299944 771 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 772}
773
878403b7
SY		 774static inline bool cpu_has_vmx_ept_1g_page(void)
775{
31299944 776 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 777}
778
4bc9b982
SY		 779static inline bool cpu_has_vmx_ept_4levels(void)
780{
781 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
782}
783
31299944 784static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 785{
31299944 786 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 787}
788
31299944 789static inline bool cpu_has_vmx_invept_context(void)
d56f546d 790{
31299944 791 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 792}
793
31299944 794static inline bool cpu_has_vmx_invept_global(void)
d56f546d 795{
31299944 796 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 797}
798
518c8aee
GJ		 799static inline bool cpu_has_vmx_invvpid_single(void)
800{
801 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
802}
803
b9d762fa
GJ		 804static inline bool cpu_has_vmx_invvpid_global(void)
805{
806 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
807}
808
31299944 809static inline bool cpu_has_vmx_ept(void)
d56f546d 810{
04547156
SY		 811 return vmcs_config.cpu_based_2nd_exec_ctrl &
812 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 813}
814
31299944 815static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 816{
817 return vmcs_config.cpu_based_2nd_exec_ctrl &
818 SECONDARY_EXEC_UNRESTRICTED_GUEST;
819}
820
31299944 821static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 822{
823 return vmcs_config.cpu_based_2nd_exec_ctrl &
824 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
825}
826
31299944 827static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 828{
6d3e435e 829 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 830}
831
31299944 832static inline bool cpu_has_vmx_vpid(void)
2384d2b3 833{
04547156
SY		 834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 836}
837
31299944 838static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 839{
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_RDTSCP;
842}
843
31299944 844static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 845{
846 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
847}
848
f5f48ee1
SY		 849static inline bool cpu_has_vmx_wbinvd_exit(void)
850{
851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_WBINVD_EXITING;
853}
854
04547156
SY		 855static inline bool report_flexpriority(void)
856{
857 return flexpriority_enabled;
858}
859
fe3ef05c
NHE		 860static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
861{
862 return vmcs12->cpu_based_vm_exec_control & bit;
863}
864
865static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
866{
867 return (vmcs12->cpu_based_vm_exec_control &
868 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
869 (vmcs12->secondary_vm_exec_control & bit);
870}
871
644d711a
NHE		 872static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
873 struct kvm_vcpu *vcpu)
874{
875 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
876}
877
878static inline bool is_exception(u32 intr_info)
879{
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
881 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
882}
883
884static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 885static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
886 struct vmcs12 *vmcs12,
887 u32 reason, unsigned long qualification);
888
8b9cf98c 889static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 890{
891 int i;
892
a2fa3e9f 893 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 894 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 895 return i;
896 return -1;
897}
898
2384d2b3
SY		 899static inline void __invvpid(int ext, u16 vpid, gva_t gva)
900{
901 struct {
902 u64 vpid : 16;
903 u64 rsvd : 48;
904 u64 gva;
905 } operand = { vpid, 0, gva };
906
4ecac3fd 907 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 908 /* CF==1 or ZF==1 --> rc = -1 */
909 "; ja 1f ; ud2 ; 1:"
910 : : "a"(&operand), "c"(ext) : "cc", "memory");
911}
912
1439442c
SY		 913static inline void __invept(int ext, u64 eptp, gpa_t gpa)
914{
915 struct {
916 u64 eptp, gpa;
917 } operand = {eptp, gpa};
918
4ecac3fd 919 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 920 /* CF==1 or ZF==1 --> rc = -1 */
921 "; ja 1f ; ud2 ; 1:\n"
922 : : "a" (&operand), "c" (ext) : "cc", "memory");
923}
924
26bb0981 925static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 926{
927 int i;
928
8b9cf98c 929 i = __find_msr_index(vmx, msr);
a75beee6 930 if (i >= 0)
a2fa3e9f 931 return &vmx->guest_msrs[i];
8b6d44c7 932 return NULL;
7725f0ba
AK		 933}
934
6aa8b732
AK		 935static void vmcs_clear(struct vmcs *vmcs)
936{
937 u64 phys_addr = __pa(vmcs);
938 u8 error;
939
4ecac3fd 940 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 941 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 942 : "cc", "memory");
943 if (error)
944 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
945 vmcs, phys_addr);
946}
947
d462b819
NHE		 948static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
949{
950 vmcs_clear(loaded_vmcs->vmcs);
951 loaded_vmcs->cpu = -1;
952 loaded_vmcs->launched = 0;
953}
954
7725b894
DX		 955static void vmcs_load(struct vmcs *vmcs)
956{
957 u64 phys_addr = __pa(vmcs);
958 u8 error;
959
960 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 962 : "cc", "memory");
963 if (error)
2844d849 964 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 965 vmcs, phys_addr);
966}
967
d462b819 968static void __loaded_vmcs_clear(void *arg)
6aa8b732 969{
d462b819 970 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 971 int cpu = raw_smp_processor_id();
6aa8b732 972
d462b819
NHE		 973 if (loaded_vmcs->cpu != cpu)
974 return; /* vcpu migration can race with cpu offline */
975 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 976 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 977 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
978 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 979}
980
d462b819 981static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 982{
d462b819
NHE		 983 if (loaded_vmcs->cpu != -1)
984 smp_call_function_single(
985 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 986}
987
1760dd49 988static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 989{
990 if (vmx->vpid == 0)
991 return;
992
518c8aee
GJ		 993 if (cpu_has_vmx_invvpid_single())
994 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 995}
996
b9d762fa
GJ		 997static inline void vpid_sync_vcpu_global(void)
998{
999 if (cpu_has_vmx_invvpid_global())
1000 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001}
1002
1003static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1004{
1005 if (cpu_has_vmx_invvpid_single())
1760dd49 1006 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1007 else
1008 vpid_sync_vcpu_global();
1009}
1010
1439442c
SY		 1011static inline void ept_sync_global(void)
1012{
1013 if (cpu_has_vmx_invept_global())
1014 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015}
1016
1017static inline void ept_sync_context(u64 eptp)
1018{
089d034e 1019 if (enable_ept) {
1439442c
SY		 1020 if (cpu_has_vmx_invept_context())
1021 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1022 else
1023 ept_sync_global();
1024 }
1025}
1026
1027static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028{
089d034e 1029 if (enable_ept) {
1439442c
SY		 1030 if (cpu_has_vmx_invept_individual_addr())
1031 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032 eptp, gpa);
1033 else
1034 ept_sync_context(eptp);
1035 }
1036}
1037
96304217 1038static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1039{
5e520e62 1040 unsigned long value;
6aa8b732 1041
5e520e62
AK		 1042 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1043 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1044 return value;
1045}
1046
96304217 1047static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1048{
1049 return vmcs_readl(field);
1050}
1051
96304217 1052static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1053{
1054 return vmcs_readl(field);
1055}
1056
96304217 1057static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1058{
05b3e0c2 1059#ifdef CONFIG_X86_64
6aa8b732
AK		 1060 return vmcs_readl(field);
1061#else
1062 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1063#endif
1064}
1065
e52de1b8
AK		 1066static noinline void vmwrite_error(unsigned long field, unsigned long value)
1067{
1068 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1069 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1070 dump_stack();
1071}
1072
6aa8b732
AK		 1073static void vmcs_writel(unsigned long field, unsigned long value)
1074{
1075 u8 error;
1076
4ecac3fd 1077 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1078 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1079 if (unlikely(error))
1080 vmwrite_error(field, value);
6aa8b732
AK		 1081}
1082
1083static void vmcs_write16(unsigned long field, u16 value)
1084{
1085 vmcs_writel(field, value);
1086}
1087
1088static void vmcs_write32(unsigned long field, u32 value)
1089{
1090 vmcs_writel(field, value);
1091}
1092
1093static void vmcs_write64(unsigned long field, u64 value)
1094{
6aa8b732 1095 vmcs_writel(field, value);
7682f2d0 1096#ifndef CONFIG_X86_64
6aa8b732
AK		 1097 asm volatile ("");
1098 vmcs_writel(field+1, value >> 32);
1099#endif
1100}
1101
2ab455cc
AL		 1102static void vmcs_clear_bits(unsigned long field, u32 mask)
1103{
1104 vmcs_writel(field, vmcs_readl(field) & ~mask);
1105}
1106
1107static void vmcs_set_bits(unsigned long field, u32 mask)
1108{
1109 vmcs_writel(field, vmcs_readl(field) | mask);
1110}
1111
2fb92db1
AK		 1112static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1113{
1114 vmx->segment_cache.bitmask = 0;
1115}
1116
1117static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1118 unsigned field)
1119{
1120 bool ret;
1121 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1122
1123 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1124 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1125 vmx->segment_cache.bitmask = 0;
1126 }
1127 ret = vmx->segment_cache.bitmask & mask;
1128 vmx->segment_cache.bitmask |= mask;
1129 return ret;
1130}
1131
1132static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1133{
1134 u16 *p = &vmx->segment_cache.seg[seg].selector;
1135
1136 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1137 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1138 return *p;
1139}
1140
1141static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1142{
1143 ulong *p = &vmx->segment_cache.seg[seg].base;
1144
1145 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1146 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1147 return *p;
1148}
1149
1150static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1151{
1152 u32 *p = &vmx->segment_cache.seg[seg].limit;
1153
1154 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1155 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1156 return *p;
1157}
1158
1159static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1160{
1161 u32 *p = &vmx->segment_cache.seg[seg].ar;
1162
1163 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1164 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1165 return *p;
1166}
1167
abd3f2d6
AK		 1168static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1169{
1170 u32 eb;
1171
fd7373cc
JK		 1172 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1173 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1174 if ((vcpu->guest_debug &
1175 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1176 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1177 eb |= 1u << BP_VECTOR;
7ffd92c5 1178 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1179 eb = ~0;
089d034e 1180 if (enable_ept)
1439442c 1181 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1182 if (vcpu->fpu_active)
1183 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1184
1185 /* When we are running a nested L2 guest and L1 specified for it a
1186 * certain exception bitmap, we must trap the same exceptions and pass
1187 * them to L1. When running L2, we will only handle the exceptions
1188 * specified above if L1 did not want them.
1189 */
1190 if (is_guest_mode(vcpu))
1191 eb |= get_vmcs12(vcpu)->exception_bitmap;
1192
abd3f2d6
AK		 1193 vmcs_write32(EXCEPTION_BITMAP, eb);
1194}
1195
8bf00a52
GN		 1196static void clear_atomic_switch_msr_special(unsigned long entry,
1197 unsigned long exit)
1198{
1199 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1200 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1201}
1202
61d2ef2c
AK		 1203static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1204{
1205 unsigned i;
1206 struct msr_autoload *m = &vmx->msr_autoload;
1207
8bf00a52
GN		 1208 switch (msr) {
1209 case MSR_EFER:
1210 if (cpu_has_load_ia32_efer) {
1211 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1212 VM_EXIT_LOAD_IA32_EFER);
1213 return;
1214 }
1215 break;
1216 case MSR_CORE_PERF_GLOBAL_CTRL:
1217 if (cpu_has_load_perf_global_ctrl) {
1218 clear_atomic_switch_msr_special(
1219 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1220 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1221 return;
1222 }
1223 break;
110312c8
AK		 1224 }
1225
61d2ef2c
AK		 1226 for (i = 0; i < m->nr; ++i)
1227 if (m->guest[i].index == msr)
1228 break;
1229
1230 if (i == m->nr)
1231 return;
1232 --m->nr;
1233 m->guest[i] = m->guest[m->nr];
1234 m->host[i] = m->host[m->nr];
1235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237}
1238
8bf00a52
GN		 1239static void add_atomic_switch_msr_special(unsigned long entry,
1240 unsigned long exit, unsigned long guest_val_vmcs,
1241 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1242{
1243 vmcs_write64(guest_val_vmcs, guest_val);
1244 vmcs_write64(host_val_vmcs, host_val);
1245 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1246 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1247}
1248
61d2ef2c
AK		 1249static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1250 u64 guest_val, u64 host_val)
1251{
1252 unsigned i;
1253 struct msr_autoload *m = &vmx->msr_autoload;
1254
8bf00a52
GN		 1255 switch (msr) {
1256 case MSR_EFER:
1257 if (cpu_has_load_ia32_efer) {
1258 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1259 VM_EXIT_LOAD_IA32_EFER,
1260 GUEST_IA32_EFER,
1261 HOST_IA32_EFER,
1262 guest_val, host_val);
1263 return;
1264 }
1265 break;
1266 case MSR_CORE_PERF_GLOBAL_CTRL:
1267 if (cpu_has_load_perf_global_ctrl) {
1268 add_atomic_switch_msr_special(
1269 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1270 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1271 GUEST_IA32_PERF_GLOBAL_CTRL,
1272 HOST_IA32_PERF_GLOBAL_CTRL,
1273 guest_val, host_val);
1274 return;
1275 }
1276 break;
110312c8
AK		 1277 }
1278
61d2ef2c
AK		 1279 for (i = 0; i < m->nr; ++i)
1280 if (m->guest[i].index == msr)
1281 break;
1282
e7fc6f93
GN		 1283 if (i == NR_AUTOLOAD_MSRS) {
1284 printk_once(KERN_WARNING"Not enough mst switch entries. "
1285 "Can't add msr %x\n", msr);
1286 return;
1287 } else if (i == m->nr) {
61d2ef2c
AK		 1288 ++m->nr;
1289 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1290 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1291 }
1292
1293 m->guest[i].index = msr;
1294 m->guest[i].value = guest_val;
1295 m->host[i].index = msr;
1296 m->host[i].value = host_val;
1297}
1298
33ed6329
AK		 1299static void reload_tss(void)
1300{
33ed6329
AK		 1301 /*
1302 * VT restores TR but not its size. Useless.
1303 */
d359192f 1304 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1305 struct desc_struct *descs;
33ed6329 1306
d359192f 1307 descs = (void *)gdt->address;
33ed6329
AK		 1308 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1309 load_TR_desc();
33ed6329
AK		 1310}
1311
92c0d900 1312static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1313{
3a34a881 1314 u64 guest_efer;
51c6cf66
AK		 1315 u64 ignore_bits;
1316
f6801dff 1317 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1318
51c6cf66
AK		 1319 /*
1320 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1321 * outside long mode
1322 */
1323 ignore_bits = EFER_NX | EFER_SCE;
1324#ifdef CONFIG_X86_64
1325 ignore_bits |= EFER_LMA | EFER_LME;
1326 /* SCE is meaningful only in long mode on Intel */
1327 if (guest_efer & EFER_LMA)
1328 ignore_bits &= ~(u64)EFER_SCE;
1329#endif
51c6cf66
AK		 1330 guest_efer &= ~ignore_bits;
1331 guest_efer |= host_efer & ignore_bits;
26bb0981 1332 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1333 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1334
1335 clear_atomic_switch_msr(vmx, MSR_EFER);
1336 /* On ept, can't emulate nx, and must switch nx atomically */
1337 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1338 guest_efer = vmx->vcpu.arch.efer;
1339 if (!(guest_efer & EFER_LMA))
1340 guest_efer &= ~EFER_LME;
1341 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1342 return false;
1343 }
1344
26bb0981 1345 return true;
51c6cf66
AK		 1346}
1347
2d49ec72
GN		 1348static unsigned long segment_base(u16 selector)
1349{
d359192f 1350 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1351 struct desc_struct *d;
1352 unsigned long table_base;
1353 unsigned long v;
1354
1355 if (!(selector & ~3))
1356 return 0;
1357
d359192f 1358 table_base = gdt->address;
2d49ec72
GN		 1359
1360 if (selector & 4) { /* from ldt */
1361 u16 ldt_selector = kvm_read_ldt();
1362
1363 if (!(ldt_selector & ~3))
1364 return 0;
1365
1366 table_base = segment_base(ldt_selector);
1367 }
1368 d = (struct desc_struct *)(table_base + (selector & ~7));
1369 v = get_desc_base(d);
1370#ifdef CONFIG_X86_64
1371 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1372 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1373#endif
1374 return v;
1375}
1376
1377static inline unsigned long kvm_read_tr_base(void)
1378{
1379 u16 tr;
1380 asm("str %0" : "=g"(tr));
1381 return segment_base(tr);
1382}
1383
04d2cc77 1384static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1385{
04d2cc77 1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1387 int i;
04d2cc77 1388
a2fa3e9f 1389 if (vmx->host_state.loaded)
33ed6329
AK		 1390 return;
1391
a2fa3e9f 1392 vmx->host_state.loaded = 1;
33ed6329
AK		 1393 /*
1394 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1395 * allow segment selectors with cpl > 0 or ti == 1.
1396 */
d6e88aec 1397 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1398 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1399 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1400 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1401 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1402 vmx->host_state.fs_reload_needed = 0;
1403 } else {
33ed6329 1404 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1405 vmx->host_state.fs_reload_needed = 1;
33ed6329 1406 }
9581d442 1407 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1408 if (!(vmx->host_state.gs_sel & 7))
1409 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1410 else {
1411 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1412 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1413 }
1414
1415#ifdef CONFIG_X86_64
1416 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1417 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1418#else
a2fa3e9f
GH		 1419 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1420 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1421#endif
707c0874
AK		 1422
1423#ifdef CONFIG_X86_64
c8770e7b
AK		 1424 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1425 if (is_long_mode(&vmx->vcpu))
44ea2b17 1426 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1427#endif
26bb0981
AK		 1428 for (i = 0; i < vmx->save_nmsrs; ++i)
1429 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1430 vmx->guest_msrs[i].data,
1431 vmx->guest_msrs[i].mask);
33ed6329
AK		 1432}
1433
a9b21b62 1434static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1435{
a2fa3e9f 1436 if (!vmx->host_state.loaded)
33ed6329
AK		 1437 return;
1438
e1beb1d3 1439 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1440 vmx->host_state.loaded = 0;
c8770e7b
AK		 1441#ifdef CONFIG_X86_64
1442 if (is_long_mode(&vmx->vcpu))
1443 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1444#endif
152d3f2f 1445 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1446 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1447#ifdef CONFIG_X86_64
9581d442 1448 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1449#else
1450 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1451#endif
33ed6329 1452 }
0a77fe4c
AK		 1453 if (vmx->host_state.fs_reload_needed)
1454 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1455 reload_tss();
44ea2b17 1456#ifdef CONFIG_X86_64
c8770e7b 1457 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1458#endif
1c11e713
AK		 1459 if (current_thread_info()->status & TS_USEDFPU)
1460 clts();
3444d7da 1461 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1462}
1463
a9b21b62
AK		 1464static void vmx_load_host_state(struct vcpu_vmx *vmx)
1465{
1466 preempt_disable();
1467 __vmx_load_host_state(vmx);
1468 preempt_enable();
1469}
1470
6aa8b732
AK		 1471/*
1472 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1473 * vcpu mutex is already taken.
1474 */
15ad7146 1475static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1476{
a2fa3e9f 1477 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1478 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1479
4610c9cc
DX		 1480 if (!vmm_exclusive)
1481 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1482 else if (vmx->loaded_vmcs->cpu != cpu)
1483 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1484
d462b819
NHE		 1485 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1486 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1487 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1488 }
1489
d462b819 1490 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1491 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1492 unsigned long sysenter_esp;
1493
a8eeb04a 1494 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1495 local_irq_disable();
d462b819
NHE		 1496 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1497 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1498 local_irq_enable();
1499
6aa8b732
AK		 1500 /*
1501 * Linux uses per-cpu TSS and GDT, so set these when switching
1502 * processors.
1503 */
d6e88aec 1504 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1505 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1506
1507 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1508 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1509 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1510 }
6aa8b732
AK		 1511}
1512
1513static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1514{
a9b21b62 1515 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1516 if (!vmm_exclusive) {
d462b819
NHE		 1517 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1518 vcpu->cpu = -1;
4610c9cc
DX		 1519 kvm_cpu_vmxoff();
1520 }
6aa8b732
AK		 1521}
1522
5fd86fcf
AK		 1523static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1524{
81231c69
AK		 1525 ulong cr0;
1526
5fd86fcf
AK		 1527 if (vcpu->fpu_active)
1528 return;
1529 vcpu->fpu_active = 1;
81231c69
AK		 1530 cr0 = vmcs_readl(GUEST_CR0);
1531 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1532 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1533 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1534 update_exception_bitmap(vcpu);
edcafe3c 1535 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1536 if (is_guest_mode(vcpu))
1537 vcpu->arch.cr0_guest_owned_bits &=
1538 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1539 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1540}
1541
edcafe3c
AK		 1542static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1543
fe3ef05c
NHE		 1544/*
1545 * Return the cr0 value that a nested guest would read. This is a combination
1546 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1547 * its hypervisor (cr0_read_shadow).
1548 */
1549static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1550{
1551 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1552 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1553}
1554static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1555{
1556 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1557 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1558}
1559
5fd86fcf
AK		 1560static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1561{
36cf24e0
NHE		 1562 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1563 * set this *before* calling this function.
1564 */
edcafe3c 1565 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1566 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1567 update_exception_bitmap(vcpu);
edcafe3c
AK		 1568 vcpu->arch.cr0_guest_owned_bits = 0;
1569 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1570 if (is_guest_mode(vcpu)) {
1571 /*
1572 * L1's specified read shadow might not contain the TS bit,
1573 * so now that we turned on shadowing of this bit, we need to
1574 * set this bit of the shadow. Like in nested_vmx_run we need
1575 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1576 * up-to-date here because we just decached cr0.TS (and we'll
1577 * only update vmcs12->guest_cr0 on nested exit).
1578 */
1579 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1581 (vcpu->arch.cr0 & X86_CR0_TS);
1582 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1583 } else
1584 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1585}
1586
6aa8b732
AK		 1587static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1588{
78ac8b47 1589 unsigned long rflags, save_rflags;
345dcaa8 1590
6de12732
AK		 1591 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1592 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1593 rflags = vmcs_readl(GUEST_RFLAGS);
1594 if (to_vmx(vcpu)->rmode.vm86_active) {
1595 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1596 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1597 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1598 }
1599 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1600 }
6de12732 1601 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1602}
1603
1604static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1605{
6de12732 1606 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1607 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1608 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1609 if (to_vmx(vcpu)->rmode.vm86_active) {
1610 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1611 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1612 }
6aa8b732
AK		 1613 vmcs_writel(GUEST_RFLAGS, rflags);
1614}
1615
2809f5d2
GC		 1616static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1617{
1618 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1619 int ret = 0;
1620
1621 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1622 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1623 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1624 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1625
1626 return ret & mask;
1627}
1628
1629static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1630{
1631 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1632 u32 interruptibility = interruptibility_old;
1633
1634 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1635
48005f64 1636 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1637 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1638 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1639 interruptibility |= GUEST_INTR_STATE_STI;
1640
1641 if ((interruptibility != interruptibility_old))
1642 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1643}
1644
6aa8b732
AK		 1645static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1646{
1647 unsigned long rip;
6aa8b732 1648
5fdbf976 1649 rip = kvm_rip_read(vcpu);
6aa8b732 1650 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1651 kvm_rip_write(vcpu, rip);
6aa8b732 1652
2809f5d2
GC		 1653 /* skipping an emulated instruction also counts */
1654 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1655}
1656
443381a8
AL		 1657static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1658{
1659 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1660 * explicitly skip the instruction because if the HLT state is set, then
1661 * the instruction is already executing and RIP has already been
1662 * advanced. */
1663 if (!yield_on_hlt &&
1664 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1665 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1666}
1667
0b6ac343
NHE		 1668/*
1669 * KVM wants to inject page-faults which it got to the guest. This function
1670 * checks whether in a nested guest, we need to inject them to L1 or L2.
1671 * This function assumes it is called with the exit reason in vmcs02 being
1672 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1673 * is running).
1674 */
1675static int nested_pf_handled(struct kvm_vcpu *vcpu)
1676{
1677 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1678
1679 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1680 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1681 return 0;
1682
1683 nested_vmx_vmexit(vcpu);
1684 return 1;
1685}
1686
298101da 1687static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1688 bool has_error_code, u32 error_code,
1689 bool reinject)
298101da 1690{
77ab6db0 1691 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1692 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1693
0b6ac343
NHE		 1694 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1695 nested_pf_handled(vcpu))
1696 return;
1697
8ab2d2e2 1698 if (has_error_code) {
77ab6db0 1699 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1700 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1701 }
77ab6db0 1702
7ffd92c5 1703 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1704 int inc_eip = 0;
1705 if (kvm_exception_is_soft(nr))
1706 inc_eip = vcpu->arch.event_exit_inst_len;
1707 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1709 return;
1710 }
1711
66fd3f7f
GN		 1712 if (kvm_exception_is_soft(nr)) {
1713 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1714 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1715 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1716 } else
1717 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1718
1719 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1720 vmx_clear_hlt(vcpu);
298101da
AK		 1721}
1722
4e47c7a6
SY		 1723static bool vmx_rdtscp_supported(void)
1724{
1725 return cpu_has_vmx_rdtscp();
1726}
1727
a75beee6
ED		 1728/*
1729 * Swap MSR entry in host/guest MSR entry array.
1730 */
8b9cf98c 1731static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1732{
26bb0981 1733 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1734
1735 tmp = vmx->guest_msrs[to];
1736 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1737 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1738}
1739
e38aea3e
AK		 1740/*
1741 * Set up the vmcs to automatically save and restore system
1742 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1743 * mode, as fiddling with msrs is very expensive.
1744 */
8b9cf98c 1745static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1746{
26bb0981 1747 int save_nmsrs, index;
5897297b 1748 unsigned long *msr_bitmap;
e38aea3e 1749
33f9c505 1750 vmx_load_host_state(vmx);
a75beee6
ED		 1751 save_nmsrs = 0;
1752#ifdef CONFIG_X86_64
8b9cf98c 1753 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1754 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1755 if (index >= 0)
8b9cf98c
RR		 1756 move_msr_up(vmx, index, save_nmsrs++);
1757 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1758 if (index >= 0)
8b9cf98c
RR		 1759 move_msr_up(vmx, index, save_nmsrs++);
1760 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1761 if (index >= 0)
8b9cf98c 1762 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1763 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764 if (index >= 0 && vmx->rdtscp_enabled)
1765 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1766 /*
8c06585d 1767 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1768 * if efer.sce is enabled.
1769 */
8c06585d 1770 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1771 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1772 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1773 }
1774#endif
92c0d900
AK		 1775 index = __find_msr_index(vmx, MSR_EFER);
1776 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1777 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1778
26bb0981 1779 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1780
1781 if (cpu_has_vmx_msr_bitmap()) {
1782 if (is_long_mode(&vmx->vcpu))
1783 msr_bitmap = vmx_msr_bitmap_longmode;
1784 else
1785 msr_bitmap = vmx_msr_bitmap_legacy;
1786
1787 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1788 }
e38aea3e
AK		 1789}
1790
6aa8b732
AK		 1791/*
1792 * reads and returns guest's timestamp counter "register"
1793 * guest_tsc = host_tsc + tsc_offset -- 21.3
1794 */
1795static u64 guest_read_tsc(void)
1796{
1797 u64 host_tsc, tsc_offset;
1798
1799 rdtscll(host_tsc);
1800 tsc_offset = vmcs_read64(TSC_OFFSET);
1801 return host_tsc + tsc_offset;
1802}
1803
d5c1785d
NHE		 1804/*
1805 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806 * counter, even if a nested guest (L2) is currently running.
1807 */
1808u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1809{
1810 u64 host_tsc, tsc_offset;
1811
1812 rdtscll(host_tsc);
1813 tsc_offset = is_guest_mode(vcpu) ?
1814 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815 vmcs_read64(TSC_OFFSET);
1816 return host_tsc + tsc_offset;
1817}
1818
4051b188
JR		 1819/*
1820 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1821 * ioctl. In this case the call-back should update internal vmx state to make
1822 * the changes effective.
1823 */
1824static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1825{
1826 /* Nothing to do here */
1827}
1828
6aa8b732 1829/*
99e3e30a 1830 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1831 */
99e3e30a 1832static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1833{
27fc51b2 1834 if (is_guest_mode(vcpu)) {
7991825b 1835 /*
27fc51b2
NHE		 1836 * We're here if L1 chose not to trap WRMSR to TSC. According
1837 * to the spec, this should set L1's TSC; The offset that L1
1838 * set for L2 remains unchanged, and still needs to be added
1839 * to the newly set TSC to get L2's TSC.
7991825b 1840 */
27fc51b2
NHE		 1841 struct vmcs12 *vmcs12;
1842 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1843 /* recalculate vmcs02.TSC_OFFSET: */
1844 vmcs12 = get_vmcs12(vcpu);
1845 vmcs_write64(TSC_OFFSET, offset +
1846 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1847 vmcs12->tsc_offset : 0));
1848 } else {
1849 vmcs_write64(TSC_OFFSET, offset);
1850 }
6aa8b732
AK		 1851}
1852
e48672fa
ZA		 1853static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1854{
1855 u64 offset = vmcs_read64(TSC_OFFSET);
1856 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1857 if (is_guest_mode(vcpu)) {
1858 /* Even when running L2, the adjustment needs to apply to L1 */
1859 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1860 }
e48672fa
ZA		 1861}
1862
857e4099
JR		 1863static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1864{
1865 return target_tsc - native_read_tsc();
1866}
1867
801d3424
NHE		 1868static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1869{
1870 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1871 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1872}
1873
1874/*
1875 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1876 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1877 * all guests if the "nested" module option is off, and can also be disabled
1878 * for a single guest by disabling its VMX cpuid bit.
1879 */
1880static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1881{
1882 return nested && guest_cpuid_has_vmx(vcpu);
1883}
1884
b87a51ae
NHE		 1885/*
1886 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1887 * returned for the various VMX controls MSRs when nested VMX is enabled.
1888 * The same values should also be used to verify that vmcs12 control fields are
1889 * valid during nested entry from L1 to L2.
1890 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1891 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1892 * bit in the high half is on if the corresponding bit in the control field
1893 * may be on. See also vmx_control_verify().
1894 * TODO: allow these variables to be modified (downgraded) by module options
1895 * or other means.
1896 */
1897static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1898static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1899static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1900static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1901static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1902static __init void nested_vmx_setup_ctls_msrs(void)
1903{
1904 /*
1905 * Note that as a general rule, the high half of the MSRs (bits in
1906 * the control fields which may be 1) should be initialized by the
1907 * intersection of the underlying hardware's MSR (i.e., features which
1908 * can be supported) and the list of features we want to expose -
1909 * because they are known to be properly supported in our code.
1910 * Also, usually, the low half of the MSRs (bits which must be 1) can
1911 * be set to 0, meaning that L1 may turn off any of these bits. The
1912 * reason is that if one of these bits is necessary, it will appear
1913 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1914 * fields of vmcs01 and vmcs02, will turn these bits off - and
1915 * nested_vmx_exit_handled() will not pass related exits to L1.
1916 * These rules have exceptions below.
1917 */
1918
1919 /* pin-based controls */
1920 /*
1921 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1922 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1923 */
1924 nested_vmx_pinbased_ctls_low = 0x16 ;
1925 nested_vmx_pinbased_ctls_high = 0x16 |
1926 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1927 PIN_BASED_VIRTUAL_NMIS;
1928
1929 /* exit controls */
1930 nested_vmx_exit_ctls_low = 0;
b6f1250e 1931 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1932#ifdef CONFIG_X86_64
1933 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1934#else
1935 nested_vmx_exit_ctls_high = 0;
1936#endif
1937
1938 /* entry controls */
1939 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1940 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1941 nested_vmx_entry_ctls_low = 0;
1942 nested_vmx_entry_ctls_high &=
1943 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1944
1945 /* cpu-based controls */
1946 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1947 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1948 nested_vmx_procbased_ctls_low = 0;
1949 nested_vmx_procbased_ctls_high &=
1950 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1951 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1952 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1953 CPU_BASED_CR3_STORE_EXITING |
1954#ifdef CONFIG_X86_64
1955 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1956#endif
1957 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1958 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1959 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1960 /*
1961 * We can allow some features even when not supported by the
1962 * hardware. For example, L1 can specify an MSR bitmap - and we
1963 * can use it to avoid exits to L1 - even when L0 runs L2
1964 * without MSR bitmaps.
1965 */
1966 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1967
1968 /* secondary cpu-based controls */
1969 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1970 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1971 nested_vmx_secondary_ctls_low = 0;
1972 nested_vmx_secondary_ctls_high &=
1973 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1974}
1975
1976static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1977{
1978 /*
1979 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1980 */
1981 return ((control & high) | low) == control;
1982}
1983
1984static inline u64 vmx_control_msr(u32 low, u32 high)
1985{
1986 return low | ((u64)high << 32);
1987}
1988
1989/*
1990 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1991 * also let it use VMX-specific MSRs.
1992 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1993 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1994 * like all other MSRs).
1995 */
1996static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1997{
1998 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1999 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2000 /*
2001 * According to the spec, processors which do not support VMX
2002 * should throw a #GP(0) when VMX capability MSRs are read.
2003 */
2004 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2005 return 1;
2006 }
2007
2008 switch (msr_index) {
2009 case MSR_IA32_FEATURE_CONTROL:
2010 *pdata = 0;
2011 break;
2012 case MSR_IA32_VMX_BASIC:
2013 /*
2014 * This MSR reports some information about VMX support. We
2015 * should return information about the VMX we emulate for the
2016 * guest, and the VMCS structure we give it - not about the
2017 * VMX support of the underlying hardware.
2018 */
2019 *pdata = VMCS12_REVISION |
2020 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2021 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2022 break;
2023 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2024 case MSR_IA32_VMX_PINBASED_CTLS:
2025 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2026 nested_vmx_pinbased_ctls_high);
2027 break;
2028 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2029 case MSR_IA32_VMX_PROCBASED_CTLS:
2030 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2031 nested_vmx_procbased_ctls_high);
2032 break;
2033 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2034 case MSR_IA32_VMX_EXIT_CTLS:
2035 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2036 nested_vmx_exit_ctls_high);
2037 break;
2038 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2039 case MSR_IA32_VMX_ENTRY_CTLS:
2040 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2041 nested_vmx_entry_ctls_high);
2042 break;
2043 case MSR_IA32_VMX_MISC:
2044 *pdata = 0;
2045 break;
2046 /*
2047 * These MSRs specify bits which the guest must keep fixed (on or off)
2048 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2049 * We picked the standard core2 setting.
2050 */
2051#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2052#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2053 case MSR_IA32_VMX_CR0_FIXED0:
2054 *pdata = VMXON_CR0_ALWAYSON;
2055 break;
2056 case MSR_IA32_VMX_CR0_FIXED1:
2057 *pdata = -1ULL;
2058 break;
2059 case MSR_IA32_VMX_CR4_FIXED0:
2060 *pdata = VMXON_CR4_ALWAYSON;
2061 break;
2062 case MSR_IA32_VMX_CR4_FIXED1:
2063 *pdata = -1ULL;
2064 break;
2065 case MSR_IA32_VMX_VMCS_ENUM:
2066 *pdata = 0x1f;
2067 break;
2068 case MSR_IA32_VMX_PROCBASED_CTLS2:
2069 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2070 nested_vmx_secondary_ctls_high);
2071 break;
2072 case MSR_IA32_VMX_EPT_VPID_CAP:
2073 /* Currently, no nested ept or nested vpid */
2074 *pdata = 0;
2075 break;
2076 default:
2077 return 0;
2078 }
2079
2080 return 1;
2081}
2082
2083static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2084{
2085 if (!nested_vmx_allowed(vcpu))
2086 return 0;
2087
2088 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2089 /* TODO: the right thing. */
2090 return 1;
2091 /*
2092 * No need to treat VMX capability MSRs specially: If we don't handle
2093 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2094 */
2095 return 0;
2096}
2097
6aa8b732
AK		 2098/*
2099 * Reads an msr value (of 'msr_index') into 'pdata'.
2100 * Returns 0 on success, non-0 otherwise.
2101 * Assumes vcpu_load() was already called.
2102 */
2103static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2104{
2105 u64 data;
26bb0981 2106 struct shared_msr_entry *msr;
6aa8b732
AK		 2107
2108 if (!pdata) {
2109 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2110 return -EINVAL;
2111 }
2112
2113 switch (msr_index) {
05b3e0c2 2114#ifdef CONFIG_X86_64
6aa8b732
AK		 2115 case MSR_FS_BASE:
2116 data = vmcs_readl(GUEST_FS_BASE);
2117 break;
2118 case MSR_GS_BASE:
2119 data = vmcs_readl(GUEST_GS_BASE);
2120 break;
44ea2b17
AK		 2121 case MSR_KERNEL_GS_BASE:
2122 vmx_load_host_state(to_vmx(vcpu));
2123 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2124 break;
26bb0981 2125#endif
6aa8b732 2126 case MSR_EFER:
3bab1f5d 2127 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2128 case MSR_IA32_TSC:
6aa8b732
AK		 2129 data = guest_read_tsc();
2130 break;
2131 case MSR_IA32_SYSENTER_CS:
2132 data = vmcs_read32(GUEST_SYSENTER_CS);
2133 break;
2134 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2135 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2136 break;
2137 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2138 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2139 break;
4e47c7a6
SY		 2140 case MSR_TSC_AUX:
2141 if (!to_vmx(vcpu)->rdtscp_enabled)
2142 return 1;
2143 /* Otherwise falls through */
6aa8b732 2144 default:
26bb0981 2145 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2146 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2147 return 0;
8b9cf98c 2148 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2149 if (msr) {
542423b0 2150 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2151 data = msr->data;
2152 break;
6aa8b732 2153 }
3bab1f5d 2154 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2155 }
2156
2157 *pdata = data;
2158 return 0;
2159}
2160
2161/*
2162 * Writes msr value into into the appropriate "register".
2163 * Returns 0 on success, non-0 otherwise.
2164 * Assumes vcpu_load() was already called.
2165 */
2166static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2167{
a2fa3e9f 2168 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2169 struct shared_msr_entry *msr;
2cc51560
ED		 2170 int ret = 0;
2171
6aa8b732 2172 switch (msr_index) {
3bab1f5d 2173 case MSR_EFER:
a9b21b62 2174 vmx_load_host_state(vmx);
2cc51560 2175 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2176 break;
16175a79 2177#ifdef CONFIG_X86_64
6aa8b732 2178 case MSR_FS_BASE:
2fb92db1 2179 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2180 vmcs_writel(GUEST_FS_BASE, data);
2181 break;
2182 case MSR_GS_BASE:
2fb92db1 2183 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2184 vmcs_writel(GUEST_GS_BASE, data);
2185 break;
44ea2b17
AK		 2186 case MSR_KERNEL_GS_BASE:
2187 vmx_load_host_state(vmx);
2188 vmx->msr_guest_kernel_gs_base = data;
2189 break;
6aa8b732
AK		 2190#endif
2191 case MSR_IA32_SYSENTER_CS:
2192 vmcs_write32(GUEST_SYSENTER_CS, data);
2193 break;
2194 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2195 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2196 break;
2197 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2198 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2199 break;
af24a4e4 2200 case MSR_IA32_TSC:
99e3e30a 2201 kvm_write_tsc(vcpu, data);
6aa8b732 2202 break;
468d472f
SY		 2203 case MSR_IA32_CR_PAT:
2204 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2205 vmcs_write64(GUEST_IA32_PAT, data);
2206 vcpu->arch.pat = data;
2207 break;
2208 }
4e47c7a6
SY		 2209 ret = kvm_set_msr_common(vcpu, msr_index, data);
2210 break;
2211 case MSR_TSC_AUX:
2212 if (!vmx->rdtscp_enabled)
2213 return 1;
2214 /* Check reserved bit, higher 32 bits should be zero */
2215 if ((data >> 32) != 0)
2216 return 1;
2217 /* Otherwise falls through */
6aa8b732 2218 default:
b87a51ae
NHE		 2219 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2220 break;
8b9cf98c 2221 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2222 if (msr) {
542423b0 2223 vmx_load_host_state(vmx);
3bab1f5d
AK		 2224 msr->data = data;
2225 break;
6aa8b732 2226 }
2cc51560 2227 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2228 }
2229
2cc51560 2230 return ret;
6aa8b732
AK		 2231}
2232
5fdbf976 2233static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2234{
5fdbf976
MT		 2235 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2236 switch (reg) {
2237 case VCPU_REGS_RSP:
2238 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2239 break;
2240 case VCPU_REGS_RIP:
2241 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2242 break;
6de4f3ad
AK		 2243 case VCPU_EXREG_PDPTR:
2244 if (enable_ept)
2245 ept_save_pdptrs(vcpu);
2246 break;
5fdbf976
MT		 2247 default:
2248 break;
2249 }
6aa8b732
AK		 2250}
2251
355be0b9 2252static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2253{
ae675ef0
JK		 2254 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2255 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2256 else
2257 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2258
abd3f2d6 2259 update_exception_bitmap(vcpu);
6aa8b732
AK		 2260}
2261
2262static __init int cpu_has_kvm_support(void)
2263{
6210e37b 2264 return cpu_has_vmx();
6aa8b732
AK		 2265}
2266
2267static __init int vmx_disabled_by_bios(void)
2268{
2269 u64 msr;
2270
2271 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2272 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2273 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2274 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2275 && tboot_enabled())
2276 return 1;
23f3e991 2277 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2278 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2279 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2280 && !tboot_enabled()) {
2281 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2282 "activate TXT before enabling KVM\n");
cafd6659 2283 return 1;
f9335afe 2284 }
23f3e991
JC		 2285 /* launched w/o TXT and VMX disabled */
2286 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2287 && !tboot_enabled())
2288 return 1;
cafd6659
SW		 2289 }
2290
2291 return 0;
6aa8b732
AK		 2292}
2293
7725b894
DX		 2294static void kvm_cpu_vmxon(u64 addr)
2295{
2296 asm volatile (ASM_VMX_VMXON_RAX
2297 : : "a"(&addr), "m"(addr)
2298 : "memory", "cc");
2299}
2300
10474ae8 2301static int hardware_enable(void *garbage)
6aa8b732
AK		 2302{
2303 int cpu = raw_smp_processor_id();
2304 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2305 u64 old, test_bits;
6aa8b732 2306
10474ae8
AG		 2307 if (read_cr4() & X86_CR4_VMXE)
2308 return -EBUSY;
2309
d462b819 2310 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2311 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2312
2313 test_bits = FEATURE_CONTROL_LOCKED;
2314 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2315 if (tboot_enabled())
2316 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2317
2318 if ((old & test_bits) != test_bits) {
6aa8b732 2319 /* enable and lock */
cafd6659
SW		 2320 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2321 }
66aee91a 2322 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2323
4610c9cc
DX		 2324 if (vmm_exclusive) {
2325 kvm_cpu_vmxon(phys_addr);
2326 ept_sync_global();
2327 }
10474ae8 2328
3444d7da
AK		 2329 store_gdt(&__get_cpu_var(host_gdt));
2330
10474ae8 2331 return 0;
6aa8b732
AK		 2332}
2333
d462b819 2334static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2335{
2336 int cpu = raw_smp_processor_id();
d462b819 2337 struct loaded_vmcs *v, *n;
543e4243 2338
d462b819
NHE		 2339 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2340 loaded_vmcss_on_cpu_link)
2341 __loaded_vmcs_clear(v);
543e4243
AK		 2342}
2343
710ff4a8
EH		 2344
2345/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2346 * tricks.
2347 */
2348static void kvm_cpu_vmxoff(void)
6aa8b732 2349{
4ecac3fd 2350 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2351}
2352
710ff4a8
EH		 2353static void hardware_disable(void *garbage)
2354{
4610c9cc 2355 if (vmm_exclusive) {
d462b819 2356 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2357 kvm_cpu_vmxoff();
2358 }
7725b894 2359 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2360}
2361
1c3d14fe 2362static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2363 u32 msr, u32 *result)
1c3d14fe
YS		 2364{
2365 u32 vmx_msr_low, vmx_msr_high;
2366 u32 ctl = ctl_min | ctl_opt;
2367
2368 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2369
2370 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2371 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2372
2373 /* Ensure minimum (required) set of control bits are supported. */
2374 if (ctl_min & ~ctl)
002c7f7c 2375 return -EIO;
1c3d14fe
YS		 2376
2377 *result = ctl;
2378 return 0;
2379}
2380
110312c8
AK		 2381static __init bool allow_1_setting(u32 msr, u32 ctl)
2382{
2383 u32 vmx_msr_low, vmx_msr_high;
2384
2385 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2386 return vmx_msr_high & ctl;
2387}
2388
002c7f7c 2389static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2390{
2391 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2392 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2393 u32 _pin_based_exec_control = 0;
2394 u32 _cpu_based_exec_control = 0;
f78e0e2e 2395 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2396 u32 _vmexit_control = 0;
2397 u32 _vmentry_control = 0;
2398
2399 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2400 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2401 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2402 &_pin_based_exec_control) < 0)
002c7f7c 2403 return -EIO;
1c3d14fe 2404
443381a8 2405 min =
1c3d14fe
YS		 2406#ifdef CONFIG_X86_64
2407 CPU_BASED_CR8_LOAD_EXITING |
2408 CPU_BASED_CR8_STORE_EXITING |
2409#endif
d56f546d
SY		 2410 CPU_BASED_CR3_LOAD_EXITING |
2411 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2412 CPU_BASED_USE_IO_BITMAPS |
2413 CPU_BASED_MOV_DR_EXITING |
a7052897 2414 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2415 CPU_BASED_MWAIT_EXITING |
2416 CPU_BASED_MONITOR_EXITING |
a7052897 2417 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2418
2419 if (yield_on_hlt)
2420 min |= CPU_BASED_HLT_EXITING;
2421
f78e0e2e 2422 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2423 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2424 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2425 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2426 &_cpu_based_exec_control) < 0)
002c7f7c 2427 return -EIO;
6e5d865c
YS		 2428#ifdef CONFIG_X86_64
2429 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2430 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2431 ~CPU_BASED_CR8_STORE_EXITING;
2432#endif
f78e0e2e 2433 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2434 min2 = 0;
2435 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2436 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2437 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2438 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2439 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2440 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2441 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2442 if (adjust_vmx_controls(min2, opt2,
2443 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2444 &_cpu_based_2nd_exec_control) < 0)
2445 return -EIO;
2446 }
2447#ifndef CONFIG_X86_64
2448 if (!(_cpu_based_2nd_exec_control &
2449 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2450 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2451#endif
d56f546d 2452 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2453 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2454 enabled */
5fff7d27
GN		 2455 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2456 CPU_BASED_CR3_STORE_EXITING |
2457 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2458 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2459 vmx_capability.ept, vmx_capability.vpid);
2460 }
1c3d14fe
YS		 2461
2462 min = 0;
2463#ifdef CONFIG_X86_64
2464 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2465#endif
468d472f 2466 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2467 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2468 &_vmexit_control) < 0)
002c7f7c 2469 return -EIO;
1c3d14fe 2470
468d472f
SY		 2471 min = 0;
2472 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2473 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2474 &_vmentry_control) < 0)
002c7f7c 2475 return -EIO;
6aa8b732 2476
c68876fd 2477 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2478
2479 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2480 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2481 return -EIO;
1c3d14fe
YS		 2482
2483#ifdef CONFIG_X86_64
2484 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2485 if (vmx_msr_high & (1u<<16))
002c7f7c 2486 return -EIO;
1c3d14fe
YS		 2487#endif
2488
2489 /* Require Write-Back (WB) memory type for VMCS accesses. */
2490 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2491 return -EIO;
1c3d14fe 2492
002c7f7c
YS		 2493 vmcs_conf->size = vmx_msr_high & 0x1fff;
2494 vmcs_conf->order = get_order(vmcs_config.size);
2495 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2496
002c7f7c
YS		 2497 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2498 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2499 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2500 vmcs_conf->vmexit_ctrl = _vmexit_control;
2501 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2502
110312c8
AK		 2503 cpu_has_load_ia32_efer =
2504 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2505 VM_ENTRY_LOAD_IA32_EFER)
2506 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2507 VM_EXIT_LOAD_IA32_EFER);
2508
8bf00a52
GN		 2509 cpu_has_load_perf_global_ctrl =
2510 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2511 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2512 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2513 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2514
2515 /*
2516 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2517 * but due to arrata below it can't be used. Workaround is to use
2518 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2519 *
2520 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2521 *
2522 * AAK155 (model 26)
2523 * AAP115 (model 30)
2524 * AAT100 (model 37)
2525 * BC86,AAY89,BD102 (model 44)
2526 * BA97 (model 46)
2527 *
2528 */
2529 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2530 switch (boot_cpu_data.x86_model) {
2531 case 26:
2532 case 30:
2533 case 37:
2534 case 44:
2535 case 46:
2536 cpu_has_load_perf_global_ctrl = false;
2537 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2538 "does not work properly. Using workaround\n");
2539 break;
2540 default:
2541 break;
2542 }
2543 }
2544
1c3d14fe 2545 return 0;
c68876fd 2546}
6aa8b732
AK		 2547
2548static struct vmcs *alloc_vmcs_cpu(int cpu)
2549{
2550 int node = cpu_to_node(cpu);
2551 struct page *pages;
2552 struct vmcs *vmcs;
2553
6484eb3e 2554 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2555 if (!pages)
2556 return NULL;
2557 vmcs = page_address(pages);
1c3d14fe
YS		 2558 memset(vmcs, 0, vmcs_config.size);
2559 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2560 return vmcs;
2561}
2562
2563static struct vmcs *alloc_vmcs(void)
2564{
d3b2c338 2565 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2566}
2567
2568static void free_vmcs(struct vmcs *vmcs)
2569{
1c3d14fe 2570 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2571}
2572
d462b819
NHE		 2573/*
2574 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2575 */
2576static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2577{
2578 if (!loaded_vmcs->vmcs)
2579 return;
2580 loaded_vmcs_clear(loaded_vmcs);
2581 free_vmcs(loaded_vmcs->vmcs);
2582 loaded_vmcs->vmcs = NULL;
2583}
2584
39959588 2585static void free_kvm_area(void)
6aa8b732
AK		 2586{
2587 int cpu;
2588
3230bb47 2589 for_each_possible_cpu(cpu) {
6aa8b732 2590 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2591 per_cpu(vmxarea, cpu) = NULL;
2592 }
6aa8b732
AK		 2593}
2594
6aa8b732
AK		 2595static __init int alloc_kvm_area(void)
2596{
2597 int cpu;
2598
3230bb47 2599 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2600 struct vmcs *vmcs;
2601
2602 vmcs = alloc_vmcs_cpu(cpu);
2603 if (!vmcs) {
2604 free_kvm_area();
2605 return -ENOMEM;
2606 }
2607
2608 per_cpu(vmxarea, cpu) = vmcs;
2609 }
2610 return 0;
2611}
2612
2613static __init int hardware_setup(void)
2614{
002c7f7c
YS		 2615 if (setup_vmcs_config(&vmcs_config) < 0)
2616 return -EIO;
50a37eb4
JR		 2617
2618 if (boot_cpu_has(X86_FEATURE_NX))
2619 kvm_enable_efer_bits(EFER_NX);
2620
93ba03c2
SY		 2621 if (!cpu_has_vmx_vpid())
2622 enable_vpid = 0;
2623
4bc9b982
SY		 2624 if (!cpu_has_vmx_ept() ||
2625 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2626 enable_ept = 0;
3a624e29
NK		 2627 enable_unrestricted_guest = 0;
2628 }
2629
2630 if (!cpu_has_vmx_unrestricted_guest())
2631 enable_unrestricted_guest = 0;
93ba03c2
SY		 2632
2633 if (!cpu_has_vmx_flexpriority())
2634 flexpriority_enabled = 0;
2635
95ba8273
GN		 2636 if (!cpu_has_vmx_tpr_shadow())
2637 kvm_x86_ops->update_cr8_intercept = NULL;
2638
54dee993
MT		 2639 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2640 kvm_disable_largepages();
2641
4b8d54f9
ZE		 2642 if (!cpu_has_vmx_ple())
2643 ple_gap = 0;
2644
b87a51ae
NHE		 2645 if (nested)
2646 nested_vmx_setup_ctls_msrs();
2647
6aa8b732
AK		 2648 return alloc_kvm_area();
2649}
2650
2651static __exit void hardware_unsetup(void)
2652{
2653 free_kvm_area();
2654}
2655
6aa8b732
AK		 2656static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2657{
2658 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2659
6af11b9e 2660 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2661 vmcs_write16(sf->selector, save->selector);
2662 vmcs_writel(sf->base, save->base);
2663 vmcs_write32(sf->limit, save->limit);
2664 vmcs_write32(sf->ar_bytes, save->ar);
2665 } else {
2666 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2667 << AR_DPL_SHIFT;
2668 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2669 }
2670}
2671
2672static void enter_pmode(struct kvm_vcpu *vcpu)
2673{
2674 unsigned long flags;
a89a8fb9 2675 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2676
a89a8fb9 2677 vmx->emulation_required = 1;
7ffd92c5 2678 vmx->rmode.vm86_active = 0;
6aa8b732 2679
2fb92db1
AK		 2680 vmx_segment_cache_clear(vmx);
2681
d0ba64f9 2682 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2683 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2684 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2685 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2686
2687 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2688 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2689 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2690 vmcs_writel(GUEST_RFLAGS, flags);
2691
66aee91a
RR		 2692 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2693 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2694
2695 update_exception_bitmap(vcpu);
2696
a89a8fb9
MG		 2697 if (emulate_invalid_guest_state)
2698 return;
2699
7ffd92c5
AK		 2700 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2701 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2702 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2703 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2704
2fb92db1
AK		 2705 vmx_segment_cache_clear(vmx);
2706
6aa8b732
AK		 2707 vmcs_write16(GUEST_SS_SELECTOR, 0);
2708 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2709
2710 vmcs_write16(GUEST_CS_SELECTOR,
2711 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2712 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2713}
2714
d77c26fc 2715static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2716{
bfc6d222 2717 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2718 struct kvm_memslots *slots;
2719 gfn_t base_gfn;
2720
90d83dc3 2721 slots = kvm_memslots(kvm);
f495c6e5 2722 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2723 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2724 return base_gfn << PAGE_SHIFT;
2725 }
bfc6d222 2726 return kvm->arch.tss_addr;
6aa8b732
AK		 2727}
2728
2729static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2730{
2731 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2732
2733 save->selector = vmcs_read16(sf->selector);
2734 save->base = vmcs_readl(sf->base);
2735 save->limit = vmcs_read32(sf->limit);
2736 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2737 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2738 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2739 vmcs_write32(sf->limit, 0xffff);
2740 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2741 if (save->base & 0xf)
2742 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2743 " aligned when entering protected mode (seg=%d)",
2744 seg);
6aa8b732
AK		 2745}
2746
2747static void enter_rmode(struct kvm_vcpu *vcpu)
2748{
2749 unsigned long flags;
a89a8fb9 2750 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2751
3a624e29
NK		 2752 if (enable_unrestricted_guest)
2753 return;
2754
a89a8fb9 2755 vmx->emulation_required = 1;
7ffd92c5 2756 vmx->rmode.vm86_active = 1;
6aa8b732 2757
776e58ea
GN		 2758 /*
2759 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2760 * vcpu. Call it here with phys address pointing 16M below 4G.
2761 */
2762 if (!vcpu->kvm->arch.tss_addr) {
2763 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2764 "called before entering vcpu\n");
2765 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2766 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2767 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2768 }
2769
2fb92db1
AK		 2770 vmx_segment_cache_clear(vmx);
2771
d0ba64f9 2772 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2773 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2774 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2775
7ffd92c5 2776 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2777 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2778
7ffd92c5 2779 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2780 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2781
2782 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2783 vmx->rmode.save_rflags = flags;
6aa8b732 2784
053de044 2785 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2786
2787 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2788 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2789 update_exception_bitmap(vcpu);
2790
a89a8fb9
MG		 2791 if (emulate_invalid_guest_state)
2792 goto continue_rmode;
2793
6aa8b732
AK		 2794 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2795 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2796 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2797
2798 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2799 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2800 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2801 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2802 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2803
7ffd92c5
AK		 2804 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2805 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2806 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2807 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2808
a89a8fb9 2809continue_rmode:
8668a3c4 2810 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2811}
2812
401d10de
AS		 2813static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2814{
2815 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2816 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2817
2818 if (!msr)
2819 return;
401d10de 2820
44ea2b17
AK		 2821 /*
2822 * Force kernel_gs_base reloading before EFER changes, as control
2823 * of this msr depends on is_long_mode().
2824 */
2825 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2826 vcpu->arch.efer = efer;
401d10de
AS		 2827 if (efer & EFER_LMA) {
2828 vmcs_write32(VM_ENTRY_CONTROLS,
2829 vmcs_read32(VM_ENTRY_CONTROLS) |
2830 VM_ENTRY_IA32E_MODE);
2831 msr->data = efer;
2832 } else {
2833 vmcs_write32(VM_ENTRY_CONTROLS,
2834 vmcs_read32(VM_ENTRY_CONTROLS) &
2835 ~VM_ENTRY_IA32E_MODE);
2836
2837 msr->data = efer & ~EFER_LME;
2838 }
2839 setup_msrs(vmx);
2840}
2841
05b3e0c2 2842#ifdef CONFIG_X86_64
6aa8b732
AK		 2843
2844static void enter_lmode(struct kvm_vcpu *vcpu)
2845{
2846 u32 guest_tr_ar;
2847
2fb92db1
AK		 2848 vmx_segment_cache_clear(to_vmx(vcpu));
2849
6aa8b732
AK		 2850 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2851 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2852 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2853 __func__);
6aa8b732
AK		 2854 vmcs_write32(GUEST_TR_AR_BYTES,
2855 (guest_tr_ar & ~AR_TYPE_MASK)
2856 | AR_TYPE_BUSY_64_TSS);
2857 }
da38f438 2858 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2859}
2860
2861static void exit_lmode(struct kvm_vcpu *vcpu)
2862{
6aa8b732
AK		 2863 vmcs_write32(VM_ENTRY_CONTROLS,
2864 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2865 & ~VM_ENTRY_IA32E_MODE);
da38f438 2866 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2867}
2868
2869#endif
2870
2384d2b3
SY		 2871static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2872{
b9d762fa 2873 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2874 if (enable_ept) {
2875 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2876 return;
4e1096d2 2877 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2878 }
2384d2b3
SY		 2879}
2880
e8467fda
AK		 2881static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2882{
2883 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2884
2885 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2886 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2887}
2888
aff48baa
AK		 2889static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2890{
2891 if (enable_ept && is_paging(vcpu))
2892 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2893 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2894}
2895
25c4c276 2896static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2897{
fc78f519
AK		 2898 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2899
2900 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2901 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2902}
2903
1439442c
SY		 2904static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2905{
6de4f3ad
AK		 2906 if (!test_bit(VCPU_EXREG_PDPTR,
2907 (unsigned long *)&vcpu->arch.regs_dirty))
2908 return;
2909
1439442c 2910 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2911 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2912 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2913 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2914 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2915 }
2916}
2917
8f5d549f
AK		 2918static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2919{
2920 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2921 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2922 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2923 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2924 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2925 }
6de4f3ad
AK		 2926
2927 __set_bit(VCPU_EXREG_PDPTR,
2928 (unsigned long *)&vcpu->arch.regs_avail);
2929 __set_bit(VCPU_EXREG_PDPTR,
2930 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2931}
2932
5e1746d6 2933static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2934
2935static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2936 unsigned long cr0,
2937 struct kvm_vcpu *vcpu)
2938{
5233dd51
MT		 2939 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2940 vmx_decache_cr3(vcpu);
1439442c
SY		 2941 if (!(cr0 & X86_CR0_PG)) {
2942 /* From paging/starting to nonpaging */
2943 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2944 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2945 (CPU_BASED_CR3_LOAD_EXITING |
2946 CPU_BASED_CR3_STORE_EXITING));
2947 vcpu->arch.cr0 = cr0;
fc78f519 2948 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2949 } else if (!is_paging(vcpu)) {
2950 /* From nonpaging to paging */
2951 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2952 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2953 ~(CPU_BASED_CR3_LOAD_EXITING |
2954 CPU_BASED_CR3_STORE_EXITING));
2955 vcpu->arch.cr0 = cr0;
fc78f519 2956 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2957 }
95eb84a7
SY		 2958
2959 if (!(cr0 & X86_CR0_WP))
2960 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2961}
2962
6aa8b732
AK		 2963static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2964{
7ffd92c5 2965 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2966 unsigned long hw_cr0;
2967
2968 if (enable_unrestricted_guest)
2969 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2970 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2971 else
2972 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2973
7ffd92c5 2974 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2975 enter_pmode(vcpu);
2976
7ffd92c5 2977 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2978 enter_rmode(vcpu);
2979
05b3e0c2 2980#ifdef CONFIG_X86_64
f6801dff 2981 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2982 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2983 enter_lmode(vcpu);
707d92fa 2984 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2985 exit_lmode(vcpu);
2986 }
2987#endif
2988
089d034e 2989 if (enable_ept)
1439442c
SY		 2990 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2991
02daab21 2992 if (!vcpu->fpu_active)
81231c69 2993 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2994
6aa8b732 2995 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2996 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2997 vcpu->arch.cr0 = cr0;
69c73028 2998 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2999}
3000
1439442c
SY		 3001static u64 construct_eptp(unsigned long root_hpa)
3002{
3003 u64 eptp;
3004
3005 /* TODO write the value reading from MSR */
3006 eptp = VMX_EPT_DEFAULT_MT |
3007 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3008 eptp |= (root_hpa & PAGE_MASK);
3009
3010 return eptp;
3011}
3012
6aa8b732
AK		 3013static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3014{
1439442c
SY		 3015 unsigned long guest_cr3;
3016 u64 eptp;
3017
3018 guest_cr3 = cr3;
089d034e 3019 if (enable_ept) {
1439442c
SY		 3020 eptp = construct_eptp(cr3);
3021 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3022 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3023 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3024 ept_load_pdptrs(vcpu);
1439442c
SY		 3025 }
3026
2384d2b3 3027 vmx_flush_tlb(vcpu);
1439442c 3028 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3029}
3030
5e1746d6 3031static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3032{
7ffd92c5 3033 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3034 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3035
5e1746d6
NHE		 3036 if (cr4 & X86_CR4_VMXE) {
3037 /*
3038 * To use VMXON (and later other VMX instructions), a guest
3039 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3040 * So basically the check on whether to allow nested VMX
3041 * is here.
3042 */
3043 if (!nested_vmx_allowed(vcpu))
3044 return 1;
3045 } else if (to_vmx(vcpu)->nested.vmxon)
3046 return 1;
3047
ad312c7c 3048 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3049 if (enable_ept) {
3050 if (!is_paging(vcpu)) {
3051 hw_cr4 &= ~X86_CR4_PAE;
3052 hw_cr4 |= X86_CR4_PSE;
3053 } else if (!(cr4 & X86_CR4_PAE)) {
3054 hw_cr4 &= ~X86_CR4_PAE;
3055 }
3056 }
1439442c
SY		 3057
3058 vmcs_writel(CR4_READ_SHADOW, cr4);
3059 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3060 return 0;
6aa8b732
AK		 3061}
3062
6aa8b732
AK		 3063static void vmx_get_segment(struct kvm_vcpu *vcpu,
3064 struct kvm_segment *var, int seg)
3065{
a9179499 3066 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3067 struct kvm_save_segment *save;
6aa8b732
AK		 3068 u32 ar;
3069
a9179499
AK		 3070 if (vmx->rmode.vm86_active
3071 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3072 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3073 || seg == VCPU_SREG_GS)
3074 && !emulate_invalid_guest_state) {
3075 switch (seg) {
3076 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3077 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3078 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3079 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3080 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3081 default: BUG();
3082 }
3083 var->selector = save->selector;
3084 var->base = save->base;
3085 var->limit = save->limit;
3086 ar = save->ar;
3087 if (seg == VCPU_SREG_TR
2fb92db1 3088 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3089 goto use_saved_rmode_seg;
3090 }
2fb92db1
AK		 3091 var->base = vmx_read_guest_seg_base(vmx, seg);
3092 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3093 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3094 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3095use_saved_rmode_seg:
9fd4a3b7 3096 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3097 ar = 0;
3098 var->type = ar & 15;
3099 var->s = (ar >> 4) & 1;
3100 var->dpl = (ar >> 5) & 3;
3101 var->present = (ar >> 7) & 1;
3102 var->avl = (ar >> 12) & 1;
3103 var->l = (ar >> 13) & 1;
3104 var->db = (ar >> 14) & 1;
3105 var->g = (ar >> 15) & 1;
3106 var->unusable = (ar >> 16) & 1;
3107}
3108
a9179499
AK		 3109static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3110{
a9179499
AK		 3111 struct kvm_segment s;
3112
3113 if (to_vmx(vcpu)->rmode.vm86_active) {
3114 vmx_get_segment(vcpu, &s, seg);
3115 return s.base;
3116 }
2fb92db1 3117 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3118}
3119
69c73028 3120static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3121{
3eeb3288 3122 if (!is_protmode(vcpu))
2e4d2653
IE		 3123 return 0;
3124
f4c63e5d
AK		 3125 if (!is_long_mode(vcpu)
3126 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3127 return 3;
3128
2fb92db1 3129 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3130}
3131
69c73028
AK		 3132static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3133{
3134 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3135 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3136 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3137 }
3138 return to_vmx(vcpu)->cpl;
3139}
3140
3141
653e3108 3142static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3143{
6aa8b732
AK		 3144 u32 ar;
3145
653e3108 3146 if (var->unusable)
6aa8b732
AK		 3147 ar = 1 << 16;
3148 else {
3149 ar = var->type & 15;
3150 ar |= (var->s & 1) << 4;
3151 ar |= (var->dpl & 3) << 5;
3152 ar |= (var->present & 1) << 7;
3153 ar |= (var->avl & 1) << 12;
3154 ar |= (var->l & 1) << 13;
3155 ar |= (var->db & 1) << 14;
3156 ar |= (var->g & 1) << 15;
3157 }
f7fbf1fd
UL		 3158 if (ar == 0) /* a 0 value means unusable */
3159 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3160
3161 return ar;
3162}
3163
3164static void vmx_set_segment(struct kvm_vcpu *vcpu,
3165 struct kvm_segment *var, int seg)
3166{
7ffd92c5 3167 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3168 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3169 u32 ar;
3170
2fb92db1
AK		 3171 vmx_segment_cache_clear(vmx);
3172
7ffd92c5 3173 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3174 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3175 vmx->rmode.tr.selector = var->selector;
3176 vmx->rmode.tr.base = var->base;
3177 vmx->rmode.tr.limit = var->limit;
3178 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3179 return;
3180 }
3181 vmcs_writel(sf->base, var->base);
3182 vmcs_write32(sf->limit, var->limit);
3183 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3184 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3185 /*
3186 * Hack real-mode segments into vm86 compatibility.
3187 */
3188 if (var->base == 0xffff0000 && var->selector == 0xf000)
3189 vmcs_writel(sf->base, 0xf0000);
3190 ar = 0xf3;
3191 } else
3192 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3193
3194 /*
3195 * Fix the "Accessed" bit in AR field of segment registers for older
3196 * qemu binaries.
3197 * IA32 arch specifies that at the time of processor reset the
3198 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3199 * is setting it to 0 in the usedland code. This causes invalid guest
3200 * state vmexit when "unrestricted guest" mode is turned on.
3201 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3202 * tree. Newer qemu binaries with that qemu fix would not need this
3203 * kvm hack.
3204 */
3205 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3206 ar |= 0x1; /* Accessed */
3207
6aa8b732 3208 vmcs_write32(sf->ar_bytes, ar);
69c73028 3209 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3210}
3211
6aa8b732
AK		 3212static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3213{
2fb92db1 3214 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3215
3216 *db = (ar >> 14) & 1;
3217 *l = (ar >> 13) & 1;
3218}
3219
89a27f4d 3220static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3221{
89a27f4d
GN		 3222 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3223 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3224}
3225
89a27f4d 3226static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3227{
89a27f4d
GN		 3228 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3229 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3230}
3231
89a27f4d 3232static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3233{
89a27f4d
GN		 3234 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3235 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3236}
3237
89a27f4d 3238static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3239{
89a27f4d
GN		 3240 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3241 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3242}
3243
648dfaa7
MG		 3244static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3245{
3246 struct kvm_segment var;
3247 u32 ar;
3248
3249 vmx_get_segment(vcpu, &var, seg);
3250 ar = vmx_segment_access_rights(&var);
3251
3252 if (var.base != (var.selector << 4))
3253 return false;
3254 if (var.limit != 0xffff)
3255 return false;
3256 if (ar != 0xf3)
3257 return false;
3258
3259 return true;
3260}
3261
3262static bool code_segment_valid(struct kvm_vcpu *vcpu)
3263{
3264 struct kvm_segment cs;
3265 unsigned int cs_rpl;
3266
3267 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3268 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3269
1872a3f4
AK		 3270 if (cs.unusable)
3271 return false;
648dfaa7
MG		 3272 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3273 return false;
3274 if (!cs.s)
3275 return false;
1872a3f4 3276 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3277 if (cs.dpl > cs_rpl)
3278 return false;
1872a3f4 3279 } else {
648dfaa7
MG		 3280 if (cs.dpl != cs_rpl)
3281 return false;
3282 }
3283 if (!cs.present)
3284 return false;
3285
3286 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3287 return true;
3288}
3289
3290static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3291{
3292 struct kvm_segment ss;
3293 unsigned int ss_rpl;
3294
3295 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3296 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3297
1872a3f4
AK		 3298 if (ss.unusable)
3299 return true;
3300 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3301 return false;
3302 if (!ss.s)
3303 return false;
3304 if (ss.dpl != ss_rpl) /* DPL != RPL */
3305 return false;
3306 if (!ss.present)
3307 return false;
3308
3309 return true;
3310}
3311
3312static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3313{
3314 struct kvm_segment var;
3315 unsigned int rpl;
3316
3317 vmx_get_segment(vcpu, &var, seg);
3318 rpl = var.selector & SELECTOR_RPL_MASK;
3319
1872a3f4
AK		 3320 if (var.unusable)
3321 return true;
648dfaa7
MG		 3322 if (!var.s)
3323 return false;
3324 if (!var.present)
3325 return false;
3326 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3327 if (var.dpl < rpl) /* DPL < RPL */
3328 return false;
3329 }
3330
3331 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3332 * rights flags
3333 */
3334 return true;
3335}
3336
3337static bool tr_valid(struct kvm_vcpu *vcpu)
3338{
3339 struct kvm_segment tr;
3340
3341 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3342
1872a3f4
AK		 3343 if (tr.unusable)
3344 return false;
648dfaa7
MG		 3345 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3346 return false;
1872a3f4 3347 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3348 return false;
3349 if (!tr.present)
3350 return false;
3351
3352 return true;
3353}
3354
3355static bool ldtr_valid(struct kvm_vcpu *vcpu)
3356{
3357 struct kvm_segment ldtr;
3358
3359 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3360
1872a3f4
AK		 3361 if (ldtr.unusable)
3362 return true;
648dfaa7
MG		 3363 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3364 return false;
3365 if (ldtr.type != 2)
3366 return false;
3367 if (!ldtr.present)
3368 return false;
3369
3370 return true;
3371}
3372
3373static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3374{
3375 struct kvm_segment cs, ss;
3376
3377 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3378 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3379
3380 return ((cs.selector & SELECTOR_RPL_MASK) ==
3381 (ss.selector & SELECTOR_RPL_MASK));
3382}
3383
3384/*
3385 * Check if guest state is valid. Returns true if valid, false if
3386 * not.
3387 * We assume that registers are always usable
3388 */
3389static bool guest_state_valid(struct kvm_vcpu *vcpu)
3390{
3391 /* real mode guest state checks */
3eeb3288 3392 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3393 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3394 return false;
3395 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3396 return false;
3397 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3398 return false;
3399 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3400 return false;
3401 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3402 return false;
3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3404 return false;
3405 } else {
3406 /* protected mode guest state checks */
3407 if (!cs_ss_rpl_check(vcpu))
3408 return false;
3409 if (!code_segment_valid(vcpu))
3410 return false;
3411 if (!stack_segment_valid(vcpu))
3412 return false;
3413 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3414 return false;
3415 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3416 return false;
3417 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3418 return false;
3419 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3420 return false;
3421 if (!tr_valid(vcpu))
3422 return false;
3423 if (!ldtr_valid(vcpu))
3424 return false;
3425 }
3426 /* TODO:
3427 * - Add checks on RIP
3428 * - Add checks on RFLAGS
3429 */
3430
3431 return true;
3432}
3433
d77c26fc 3434static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3435{
40dcaa9f 3436 gfn_t fn;
195aefde 3437 u16 data = 0;
40dcaa9f 3438 int r, idx, ret = 0;
6aa8b732 3439
40dcaa9f
XG		 3440 idx = srcu_read_lock(&kvm->srcu);
3441 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3442 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3443 if (r < 0)
10589a46 3444 goto out;
195aefde 3445 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3446 r = kvm_write_guest_page(kvm, fn++, &data,
3447 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3448 if (r < 0)
10589a46 3449 goto out;
195aefde
IE		 3450 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3451 if (r < 0)
10589a46 3452 goto out;
195aefde
IE		 3453 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3454 if (r < 0)
10589a46 3455 goto out;
195aefde 3456 data = ~0;
10589a46
MT		 3457 r = kvm_write_guest_page(kvm, fn, &data,
3458 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3459 sizeof(u8));
195aefde 3460 if (r < 0)
10589a46
MT		 3461 goto out;
3462
3463 ret = 1;
3464out:
40dcaa9f 3465 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3466 return ret;
6aa8b732
AK		 3467}
3468
b7ebfb05
SY		 3469static int init_rmode_identity_map(struct kvm *kvm)
3470{
40dcaa9f 3471 int i, idx, r, ret;
b7ebfb05
SY		 3472 pfn_t identity_map_pfn;
3473 u32 tmp;
3474
089d034e 3475 if (!enable_ept)
b7ebfb05
SY		 3476 return 1;
3477 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3478 printk(KERN_ERR "EPT: identity-mapping pagetable "
3479 "haven't been allocated!\n");
3480 return 0;
3481 }
3482 if (likely(kvm->arch.ept_identity_pagetable_done))
3483 return 1;
3484 ret = 0;
b927a3ce 3485 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3486 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3487 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3488 if (r < 0)
3489 goto out;
3490 /* Set up identity-mapping pagetable for EPT in real mode */
3491 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3492 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3493 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3494 r = kvm_write_guest_page(kvm, identity_map_pfn,
3495 &tmp, i * sizeof(tmp), sizeof(tmp));
3496 if (r < 0)
3497 goto out;
3498 }
3499 kvm->arch.ept_identity_pagetable_done = true;
3500 ret = 1;
3501out:
40dcaa9f 3502 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3503 return ret;
3504}
3505
6aa8b732
AK		 3506static void seg_setup(int seg)
3507{
3508 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3509 unsigned int ar;
6aa8b732
AK		 3510
3511 vmcs_write16(sf->selector, 0);
3512 vmcs_writel(sf->base, 0);
3513 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3514 if (enable_unrestricted_guest) {
3515 ar = 0x93;
3516 if (seg == VCPU_SREG_CS)
3517 ar |= 0x08; /* code segment */
3518 } else
3519 ar = 0xf3;
3520
3521 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3522}
3523
f78e0e2e
SY		 3524static int alloc_apic_access_page(struct kvm *kvm)
3525{
3526 struct kvm_userspace_memory_region kvm_userspace_mem;
3527 int r = 0;
3528
79fac95e 3529 mutex_lock(&kvm->slots_lock);
bfc6d222 3530 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3531 goto out;
3532 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3533 kvm_userspace_mem.flags = 0;
3534 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3535 kvm_userspace_mem.memory_size = PAGE_SIZE;
3536 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3537 if (r)
3538 goto out;
72dc67a6 3539
bfc6d222 3540 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3541out:
79fac95e 3542 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3543 return r;
3544}
3545
b7ebfb05
SY		 3546static int alloc_identity_pagetable(struct kvm *kvm)
3547{
3548 struct kvm_userspace_memory_region kvm_userspace_mem;
3549 int r = 0;
3550
79fac95e 3551 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3552 if (kvm->arch.ept_identity_pagetable)
3553 goto out;
3554 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3555 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3556 kvm_userspace_mem.guest_phys_addr =
3557 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3558 kvm_userspace_mem.memory_size = PAGE_SIZE;
3559 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3560 if (r)
3561 goto out;
3562
b7ebfb05 3563 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3564 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3565out:
79fac95e 3566 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3567 return r;
3568}
3569
2384d2b3
SY		 3570static void allocate_vpid(struct vcpu_vmx *vmx)
3571{
3572 int vpid;
3573
3574 vmx->vpid = 0;
919818ab 3575 if (!enable_vpid)
2384d2b3
SY		 3576 return;
3577 spin_lock(&vmx_vpid_lock);
3578 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3579 if (vpid < VMX_NR_VPIDS) {
3580 vmx->vpid = vpid;
3581 __set_bit(vpid, vmx_vpid_bitmap);
3582 }
3583 spin_unlock(&vmx_vpid_lock);
3584}
3585
cdbecfc3
LJ		 3586static void free_vpid(struct vcpu_vmx *vmx)
3587{
3588 if (!enable_vpid)
3589 return;
3590 spin_lock(&vmx_vpid_lock);
3591 if (vmx->vpid != 0)
3592 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3593 spin_unlock(&vmx_vpid_lock);
3594}
3595
5897297b 3596static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3597{
3e7c73e9 3598 int f = sizeof(unsigned long);
25c5f225
SY		 3599
3600 if (!cpu_has_vmx_msr_bitmap())
3601 return;
3602
3603 /*
3604 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3605 * have the write-low and read-high bitmap offsets the wrong way round.
3606 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3607 */
25c5f225 3608 if (msr <= 0x1fff) {
3e7c73e9
AK		 3609 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3610 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3611 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3612 msr &= 0x1fff;
3e7c73e9
AK		 3613 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3614 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3615 }
25c5f225
SY		 3616}
3617
5897297b
AK		 3618static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3619{
3620 if (!longmode_only)
3621 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3622 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3623}
3624
a3a8ff8e
NHE		 3625/*
3626 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3627 * will not change in the lifetime of the guest.
3628 * Note that host-state that does change is set elsewhere. E.g., host-state
3629 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3630 */
3631static void vmx_set_constant_host_state(void)
3632{
3633 u32 low32, high32;
3634 unsigned long tmpl;
3635 struct desc_ptr dt;
3636
3637 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3638 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3639 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3640
3641 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3642 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3643 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3644 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3645 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3646
3647 native_store_idt(&dt);
3648 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3649
3650 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3651 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3652
3653 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3654 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3655 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3656 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3657
3658 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3659 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3660 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3661 }
3662}
3663
bf8179a0
NHE		 3664static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3665{
3666 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3667 if (enable_ept)
3668 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3669 if (is_guest_mode(&vmx->vcpu))
3670 vmx->vcpu.arch.cr4_guest_owned_bits &=
3671 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3672 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3673}
3674
3675static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3676{
3677 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3678 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3679 exec_control &= ~CPU_BASED_TPR_SHADOW;
3680#ifdef CONFIG_X86_64
3681 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3682 CPU_BASED_CR8_LOAD_EXITING;
3683#endif
3684 }
3685 if (!enable_ept)
3686 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3687 CPU_BASED_CR3_LOAD_EXITING |
3688 CPU_BASED_INVLPG_EXITING;
3689 return exec_control;
3690}
3691
3692static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3693{
3694 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3695 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3696 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3697 if (vmx->vpid == 0)
3698 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3699 if (!enable_ept) {
3700 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3701 enable_unrestricted_guest = 0;
3702 }
3703 if (!enable_unrestricted_guest)
3704 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3705 if (!ple_gap)
3706 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3707 return exec_control;
3708}
3709
ce88decf
XG		 3710static void ept_set_mmio_spte_mask(void)
3711{
3712 /*
3713 * EPT Misconfigurations can be generated if the value of bits 2:0
3714 * of an EPT paging-structure entry is 110b (write/execute).
3715 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3716 * spte.
3717 */
3718 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3719}
3720
6aa8b732
AK		 3721/*
3722 * Sets up the vmcs for emulated real mode.
3723 */
8b9cf98c 3724static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3725{
2e4ce7f5 3726#ifdef CONFIG_X86_64
6aa8b732 3727 unsigned long a;
2e4ce7f5 3728#endif
6aa8b732 3729 int i;
6aa8b732 3730
6aa8b732 3731 /* I/O */
3e7c73e9
AK		 3732 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3733 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3734
25c5f225 3735 if (cpu_has_vmx_msr_bitmap())
5897297b 3736 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3737
6aa8b732
AK		 3738 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3739
6aa8b732 3740 /* Control */
1c3d14fe
YS		 3741 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3742 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3743
bf8179a0 3744 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3745
83ff3b9d 3746 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3747 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3748 vmx_secondary_exec_control(vmx));
83ff3b9d 3749 }
f78e0e2e 3750
4b8d54f9
ZE		 3751 if (ple_gap) {
3752 vmcs_write32(PLE_GAP, ple_gap);
3753 vmcs_write32(PLE_WINDOW, ple_window);
3754 }
3755
c3707958
XG		 3756 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3757 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3758 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3759
9581d442
AK		 3760 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3761 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3762 vmx_set_constant_host_state();
05b3e0c2 3763#ifdef CONFIG_X86_64
6aa8b732
AK		 3764 rdmsrl(MSR_FS_BASE, a);
3765 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3766 rdmsrl(MSR_GS_BASE, a);
3767 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3768#else
3769 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3770 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3771#endif
3772
2cc51560
ED		 3773 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3774 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3775 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3776 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3777 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3778
468d472f 3779 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3780 u32 msr_low, msr_high;
3781 u64 host_pat;
468d472f
SY		 3782 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3783 host_pat = msr_low | ((u64) msr_high << 32);
3784 /* Write the default value follow host pat */
3785 vmcs_write64(GUEST_IA32_PAT, host_pat);
3786 /* Keep arch.pat sync with GUEST_IA32_PAT */
3787 vmx->vcpu.arch.pat = host_pat;
3788 }
3789
6aa8b732
AK		 3790 for (i = 0; i < NR_VMX_MSR; ++i) {
3791 u32 index = vmx_msr_index[i];
3792 u32 data_low, data_high;
a2fa3e9f 3793 int j = vmx->nmsrs;
6aa8b732
AK		 3794
3795 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3796 continue;
432bd6cb
AK		 3797 if (wrmsr_safe(index, data_low, data_high) < 0)
3798 continue;
26bb0981
AK		 3799 vmx->guest_msrs[j].index = i;
3800 vmx->guest_msrs[j].data = 0;
d5696725 3801 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3802 ++vmx->nmsrs;
6aa8b732 3803 }
6aa8b732 3804
1c3d14fe 3805 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3806
3807 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3808 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3809
e00c8cf2 3810 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3811 set_cr4_guest_host_mask(vmx);
e00c8cf2 3812
99e3e30a 3813 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3814
e00c8cf2
AK		 3815 return 0;
3816}
3817
3818static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3819{
3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3821 u64 msr;
4b9d3a04 3822 int ret;
e00c8cf2 3823
5fdbf976 3824 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3825
7ffd92c5 3826 vmx->rmode.vm86_active = 0;
e00c8cf2 3827
3b86cd99
JK		 3828 vmx->soft_vnmi_blocked = 0;
3829
ad312c7c 3830 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3831 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3832 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3833 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3834 msr |= MSR_IA32_APICBASE_BSP;
3835 kvm_set_apic_base(&vmx->vcpu, msr);
3836
10ab25cd
JK		 3837 ret = fx_init(&vmx->vcpu);
3838 if (ret != 0)
3839 goto out;
e00c8cf2 3840
2fb92db1
AK		 3841 vmx_segment_cache_clear(vmx);
3842
5706be0d 3843 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3844 /*
3845 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3846 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3847 */
c5af89b6 3848 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3849 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3850 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3851 } else {
ad312c7c
ZX		 3852 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3853 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3854 }
e00c8cf2
AK		 3855
3856 seg_setup(VCPU_SREG_DS);
3857 seg_setup(VCPU_SREG_ES);
3858 seg_setup(VCPU_SREG_FS);
3859 seg_setup(VCPU_SREG_GS);
3860 seg_setup(VCPU_SREG_SS);
3861
3862 vmcs_write16(GUEST_TR_SELECTOR, 0);
3863 vmcs_writel(GUEST_TR_BASE, 0);
3864 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3865 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3866
3867 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3868 vmcs_writel(GUEST_LDTR_BASE, 0);
3869 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3870 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3871
3872 vmcs_write32(GUEST_SYSENTER_CS, 0);
3873 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3874 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3875
3876 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3877 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3878 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3879 else
5fdbf976
MT		 3880 kvm_rip_write(vcpu, 0);
3881 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3882
e00c8cf2
AK		 3883 vmcs_writel(GUEST_DR7, 0x400);
3884
3885 vmcs_writel(GUEST_GDTR_BASE, 0);
3886 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3887
3888 vmcs_writel(GUEST_IDTR_BASE, 0);
3889 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3890
443381a8 3891 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3892 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3893 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3894
e00c8cf2
AK		 3895 /* Special registers */
3896 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3897
3898 setup_msrs(vmx);
3899
6aa8b732
AK		 3900 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3901
f78e0e2e
SY		 3902 if (cpu_has_vmx_tpr_shadow()) {
3903 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3904 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3905 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3906 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3907 vmcs_write32(TPR_THRESHOLD, 0);
3908 }
3909
3910 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3911 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3912 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3913
2384d2b3
SY		 3914 if (vmx->vpid != 0)
3915 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3916
fa40052c 3917 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3918 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3919 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3920 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3921 vmx_fpu_activate(&vmx->vcpu);
3922 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3923
b9d762fa 3924 vpid_sync_context(vmx);
2384d2b3 3925
3200f405 3926 ret = 0;
6aa8b732 3927
a89a8fb9
MG		 3928 /* HACK: Don't enable emulation on guest boot/reset */
3929 vmx->emulation_required = 0;
3930
6aa8b732
AK		 3931out:
3932 return ret;
3933}
3934
b6f1250e
NHE		 3935/*
3936 * In nested virtualization, check if L1 asked to exit on external interrupts.
3937 * For most existing hypervisors, this will always return true.
3938 */
3939static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3940{
3941 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3942 PIN_BASED_EXT_INTR_MASK;
3943}
3944
3b86cd99
JK		 3945static void enable_irq_window(struct kvm_vcpu *vcpu)
3946{
3947 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 3948 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3949 /*
3950 * We get here if vmx_interrupt_allowed() said we can't
3951 * inject to L1 now because L2 must run. Ask L2 to exit
3952 * right after entry, so we can inject to L1 more promptly.
b6f1250e 3953 */
d6185f20 3954 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 3955 return;
d6185f20 3956 }
3b86cd99
JK		 3957
3958 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3959 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3960 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3961}
3962
3963static void enable_nmi_window(struct kvm_vcpu *vcpu)
3964{
3965 u32 cpu_based_vm_exec_control;
3966
3967 if (!cpu_has_virtual_nmis()) {
3968 enable_irq_window(vcpu);
3969 return;
3970 }
3971
30bd0c4c
AK		 3972 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3973 enable_irq_window(vcpu);
3974 return;
3975 }
3b86cd99
JK		 3976 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3977 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3978 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3979}
3980
66fd3f7f 3981static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3982{
9c8cba37 3983 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3984 uint32_t intr;
3985 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3986
229456fc 3987 trace_kvm_inj_virq(irq);
2714d1d3 3988
fa89a817 3989 ++vcpu->stat.irq_injections;
7ffd92c5 3990 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3991 int inc_eip = 0;
3992 if (vcpu->arch.interrupt.soft)
3993 inc_eip = vcpu->arch.event_exit_inst_len;
3994 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3996 return;
3997 }
66fd3f7f
GN		 3998 intr = irq | INTR_INFO_VALID_MASK;
3999 if (vcpu->arch.interrupt.soft) {
4000 intr |= INTR_TYPE_SOFT_INTR;
4001 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4002 vmx->vcpu.arch.event_exit_inst_len);
4003 } else
4004 intr |= INTR_TYPE_EXT_INTR;
4005 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 4006 vmx_clear_hlt(vcpu);
85f455f7
ED		 4007}
4008
f08864b4
SY		 4009static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4010{
66a5a347
JK		 4011 struct vcpu_vmx *vmx = to_vmx(vcpu);
4012
0b6ac343
NHE		 4013 if (is_guest_mode(vcpu))
4014 return;
4015
3b86cd99
JK		 4016 if (!cpu_has_virtual_nmis()) {
4017 /*
4018 * Tracking the NMI-blocked state in software is built upon
4019 * finding the next open IRQ window. This, in turn, depends on
4020 * well-behaving guests: They have to keep IRQs disabled at
4021 * least as long as the NMI handler runs. Otherwise we may
4022 * cause NMI nesting, maybe breaking the guest. But as this is
4023 * highly unlikely, we can live with the residual risk.
4024 */
4025 vmx->soft_vnmi_blocked = 1;
4026 vmx->vnmi_blocked_time = 0;
4027 }
4028
487b391d 4029 ++vcpu->stat.nmi_injections;
9d58b931 4030 vmx->nmi_known_unmasked = false;
7ffd92c5 4031 if (vmx->rmode.vm86_active) {
71f9833b 4032 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4033 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4034 return;
4035 }
f08864b4
SY		 4036 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4037 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 4038 vmx_clear_hlt(vcpu);
f08864b4
SY		 4039}
4040
c4282df9 4041static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4042{
3b86cd99 4043 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4044 return 0;
33f089ca 4045
c4282df9 4046 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4047 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4048 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4049}
4050
3cfc3092
JK		 4051static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4052{
4053 if (!cpu_has_virtual_nmis())
4054 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4055 if (to_vmx(vcpu)->nmi_known_unmasked)
4056 return false;
c332c83a 4057 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4058}
4059
4060static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4061{
4062 struct vcpu_vmx *vmx = to_vmx(vcpu);
4063
4064 if (!cpu_has_virtual_nmis()) {
4065 if (vmx->soft_vnmi_blocked != masked) {
4066 vmx->soft_vnmi_blocked = masked;
4067 vmx->vnmi_blocked_time = 0;
4068 }
4069 } else {
9d58b931 4070 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4071 if (masked)
4072 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4073 GUEST_INTR_STATE_NMI);
4074 else
4075 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4076 GUEST_INTR_STATE_NMI);
4077 }
4078}
4079
78646121
GN		 4080static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4081{
b6f1250e
NHE		 4082 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4083 struct vmcs12 *vmcs12;
4084 if (to_vmx(vcpu)->nested.nested_run_pending)
4085 return 0;
4086 nested_vmx_vmexit(vcpu);
4087 vmcs12 = get_vmcs12(vcpu);
4088 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4089 vmcs12->vm_exit_intr_info = 0;
4090 /* fall through to normal code, but now in L1, not L2 */
4091 }
4092
c4282df9
GN		 4093 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4094 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4095 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4096}
4097
cbc94022
IE		 4098static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4099{
4100 int ret;
4101 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4102 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4103 .guest_phys_addr = addr,
4104 .memory_size = PAGE_SIZE * 3,
4105 .flags = 0,
4106 };
4107
4108 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4109 if (ret)
4110 return ret;
bfc6d222 4111 kvm->arch.tss_addr = addr;
93ea5388
GN		 4112 if (!init_rmode_tss(kvm))
4113 return -ENOMEM;
4114
cbc94022
IE		 4115 return 0;
4116}
4117
6aa8b732
AK		 4118static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4119 int vec, u32 err_code)
4120{
b3f37707
NK		 4121 /*
4122 * Instruction with address size override prefix opcode 0x67
4123 * Cause the #SS fault with 0 error code in VM86 mode.
4124 */
4125 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4126 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4127 return 1;
77ab6db0
JK		 4128 /*
4129 * Forward all other exceptions that are valid in real mode.
4130 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4131 * the required debugging infrastructure rework.
4132 */
4133 switch (vec) {
77ab6db0 4134 case DB_VECTOR:
d0bfb940
JK		 4135 if (vcpu->guest_debug &
4136 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4137 return 0;
4138 kvm_queue_exception(vcpu, vec);
4139 return 1;
77ab6db0 4140 case BP_VECTOR:
c573cd22
JK		 4141 /*
4142 * Update instruction length as we may reinject the exception
4143 * from user space while in guest debugging mode.
4144 */
4145 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4146 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4147 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4148 return 0;
4149 /* fall through */
4150 case DE_VECTOR:
77ab6db0
JK		 4151 case OF_VECTOR:
4152 case BR_VECTOR:
4153 case UD_VECTOR:
4154 case DF_VECTOR:
4155 case SS_VECTOR:
4156 case GP_VECTOR:
4157 case MF_VECTOR:
4158 kvm_queue_exception(vcpu, vec);
4159 return 1;
4160 }
6aa8b732
AK		 4161 return 0;
4162}
4163
a0861c02
AK		 4164/*
4165 * Trigger machine check on the host. We assume all the MSRs are already set up
4166 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4167 * We pass a fake environment to the machine check handler because we want
4168 * the guest to be always treated like user space, no matter what context
4169 * it used internally.
4170 */
4171static void kvm_machine_check(void)
4172{
4173#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4174 struct pt_regs regs = {
4175 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4176 .flags = X86_EFLAGS_IF,
4177 };
4178
4179 do_machine_check(&regs, 0);
4180#endif
4181}
4182
851ba692 4183static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4184{
4185 /* already handled by vcpu_run */
4186 return 1;
4187}
4188
851ba692 4189static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4190{
1155f76a 4191 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4192 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4193 u32 intr_info, ex_no, error_code;
42dbaa5a 4194 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4195 u32 vect_info;
4196 enum emulation_result er;
4197
1155f76a 4198 vect_info = vmx->idt_vectoring_info;
88786475 4199 intr_info = vmx->exit_intr_info;
6aa8b732 4200
a0861c02 4201 if (is_machine_check(intr_info))
851ba692 4202 return handle_machine_check(vcpu);
a0861c02 4203
6aa8b732 4204 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4205 !is_page_fault(intr_info)) {
4206 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4207 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4208 vcpu->run->internal.ndata = 2;
4209 vcpu->run->internal.data[0] = vect_info;
4210 vcpu->run->internal.data[1] = intr_info;
4211 return 0;
4212 }
6aa8b732 4213
e4a41889 4214 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4215 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4216
4217 if (is_no_device(intr_info)) {
5fd86fcf 4218 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4219 return 1;
4220 }
4221
7aa81cc0 4222 if (is_invalid_opcode(intr_info)) {
51d8b661 4223 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4224 if (er != EMULATE_DONE)
7ee5d940 4225 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4226 return 1;
4227 }
4228
6aa8b732 4229 error_code = 0;
2e11384c 4230 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4231 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4232 if (is_page_fault(intr_info)) {
1439442c 4233 /* EPT won't cause page fault directly */
cf3ace79 4234 BUG_ON(enable_ept);
6aa8b732 4235 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4236 trace_kvm_page_fault(cr2, error_code);
4237
3298b75c 4238 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4239 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4240 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4241 }
4242
7ffd92c5 4243 if (vmx->rmode.vm86_active &&
6aa8b732 4244 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4245 error_code)) {
ad312c7c
ZX		 4246 if (vcpu->arch.halt_request) {
4247 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4248 return kvm_emulate_halt(vcpu);
4249 }
6aa8b732 4250 return 1;
72d6e5a0 4251 }
6aa8b732 4252
d0bfb940 4253 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4254 switch (ex_no) {
4255 case DB_VECTOR:
4256 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4257 if (!(vcpu->guest_debug &
4258 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4259 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4260 kvm_queue_exception(vcpu, DB_VECTOR);
4261 return 1;
4262 }
4263 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4264 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4265 /* fall through */
4266 case BP_VECTOR:
c573cd22
JK		 4267 /*
4268 * Update instruction length as we may reinject #BP from
4269 * user space while in guest debugging mode. Reading it for
4270 * #DB as well causes no harm, it is not used in that case.
4271 */
4272 vmx->vcpu.arch.event_exit_inst_len =
4273 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4274 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4275 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4276 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4277 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4278 break;
4279 default:
d0bfb940
JK		 4280 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4281 kvm_run->ex.exception = ex_no;
4282 kvm_run->ex.error_code = error_code;
42dbaa5a 4283 break;
6aa8b732 4284 }
6aa8b732
AK		 4285 return 0;
4286}
4287
851ba692 4288static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4289{
1165f5fe 4290 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4291 return 1;
4292}
4293
851ba692 4294static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4295{
851ba692 4296 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4297 return 0;
4298}
6aa8b732 4299
851ba692 4300static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4301{
bfdaab09 4302 unsigned long exit_qualification;
34c33d16 4303 int size, in, string;
039576c0 4304 unsigned port;
6aa8b732 4305
bfdaab09 4306 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4307 string = (exit_qualification & 16) != 0;
cf8f70bf 4308 in = (exit_qualification & 8) != 0;
e70669ab 4309
cf8f70bf 4310 ++vcpu->stat.io_exits;
e70669ab 4311
cf8f70bf 4312 if (string || in)
51d8b661 4313 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4314
cf8f70bf
GN		 4315 port = exit_qualification >> 16;
4316 size = (exit_qualification & 7) + 1;
e93f36bc 4317 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4318
4319 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4320}
4321
102d8325
IM		 4322static void
4323vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4324{
4325 /*
4326 * Patch in the VMCALL instruction:
4327 */
4328 hypercall[0] = 0x0f;
4329 hypercall[1] = 0x01;
4330 hypercall[2] = 0xc1;
102d8325
IM		 4331}
4332
eeadf9e7
NHE		 4333/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4334static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4335{
4336 if (to_vmx(vcpu)->nested.vmxon &&
4337 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4338 return 1;
4339
4340 if (is_guest_mode(vcpu)) {
4341 /*
4342 * We get here when L2 changed cr0 in a way that did not change
4343 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4344 * but did change L0 shadowed bits. This can currently happen
4345 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4346 * loading) while pretending to allow the guest to change it.
4347 */
4348 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4349 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4350 return 1;
4351 vmcs_writel(CR0_READ_SHADOW, val);
4352 return 0;
4353 } else
4354 return kvm_set_cr0(vcpu, val);
4355}
4356
4357static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4358{
4359 if (is_guest_mode(vcpu)) {
4360 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4361 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4362 return 1;
4363 vmcs_writel(CR4_READ_SHADOW, val);
4364 return 0;
4365 } else
4366 return kvm_set_cr4(vcpu, val);
4367}
4368
4369/* called to set cr0 as approriate for clts instruction exit. */
4370static void handle_clts(struct kvm_vcpu *vcpu)
4371{
4372 if (is_guest_mode(vcpu)) {
4373 /*
4374 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4375 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4376 * just pretend it's off (also in arch.cr0 for fpu_activate).
4377 */
4378 vmcs_writel(CR0_READ_SHADOW,
4379 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4380 vcpu->arch.cr0 &= ~X86_CR0_TS;
4381 } else
4382 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4383}
4384
851ba692 4385static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4386{
229456fc 4387 unsigned long exit_qualification, val;
6aa8b732
AK		 4388 int cr;
4389 int reg;
49a9b07e 4390 int err;
6aa8b732 4391
bfdaab09 4392 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4393 cr = exit_qualification & 15;
4394 reg = (exit_qualification >> 8) & 15;
4395 switch ((exit_qualification >> 4) & 3) {
4396 case 0: /* mov to cr */
229456fc
MT		 4397 val = kvm_register_read(vcpu, reg);
4398 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4399 switch (cr) {
4400 case 0:
eeadf9e7 4401 err = handle_set_cr0(vcpu, val);
db8fcefa 4402 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4403 return 1;
4404 case 3:
2390218b 4405 err = kvm_set_cr3(vcpu, val);
db8fcefa 4406 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4407 return 1;
4408 case 4:
eeadf9e7 4409 err = handle_set_cr4(vcpu, val);
db8fcefa 4410 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4411 return 1;
0a5fff19
GN		 4412 case 8: {
4413 u8 cr8_prev = kvm_get_cr8(vcpu);
4414 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4415 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4416 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4417 if (irqchip_in_kernel(vcpu->kvm))
4418 return 1;
4419 if (cr8_prev <= cr8)
4420 return 1;
851ba692 4421 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4422 return 0;
4423 }
6aa8b732
AK		 4424 };
4425 break;
25c4c276 4426 case 2: /* clts */
eeadf9e7 4427 handle_clts(vcpu);
4d4ec087 4428 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4429 skip_emulated_instruction(vcpu);
6b52d186 4430 vmx_fpu_activate(vcpu);
25c4c276 4431 return 1;
6aa8b732
AK		 4432 case 1: /*mov from cr*/
4433 switch (cr) {
4434 case 3:
9f8fe504
AK		 4435 val = kvm_read_cr3(vcpu);
4436 kvm_register_write(vcpu, reg, val);
4437 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4438 skip_emulated_instruction(vcpu);
4439 return 1;
4440 case 8:
229456fc
MT		 4441 val = kvm_get_cr8(vcpu);
4442 kvm_register_write(vcpu, reg, val);
4443 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4444 skip_emulated_instruction(vcpu);
4445 return 1;
4446 }
4447 break;
4448 case 3: /* lmsw */
a1f83a74 4449 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4450 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4451 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4452
4453 skip_emulated_instruction(vcpu);
4454 return 1;
4455 default:
4456 break;
4457 }
851ba692 4458 vcpu->run->exit_reason = 0;
f0242478 4459 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4460 (int)(exit_qualification >> 4) & 3, cr);
4461 return 0;
4462}
4463
851ba692 4464static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4465{
bfdaab09 4466 unsigned long exit_qualification;
6aa8b732
AK		 4467 int dr, reg;
4468
f2483415 4469 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4470 if (!kvm_require_cpl(vcpu, 0))
4471 return 1;
42dbaa5a
JK		 4472 dr = vmcs_readl(GUEST_DR7);
4473 if (dr & DR7_GD) {
4474 /*
4475 * As the vm-exit takes precedence over the debug trap, we
4476 * need to emulate the latter, either for the host or the
4477 * guest debugging itself.
4478 */
4479 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4480 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4481 vcpu->run->debug.arch.dr7 = dr;
4482 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4483 vmcs_readl(GUEST_CS_BASE) +
4484 vmcs_readl(GUEST_RIP);
851ba692
AK		 4485 vcpu->run->debug.arch.exception = DB_VECTOR;
4486 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4487 return 0;
4488 } else {
4489 vcpu->arch.dr7 &= ~DR7_GD;
4490 vcpu->arch.dr6 |= DR6_BD;
4491 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4492 kvm_queue_exception(vcpu, DB_VECTOR);
4493 return 1;
4494 }
4495 }
4496
bfdaab09 4497 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4498 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4499 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4500 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4501 unsigned long val;
4502 if (!kvm_get_dr(vcpu, dr, &val))
4503 kvm_register_write(vcpu, reg, val);
4504 } else
4505 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4506 skip_emulated_instruction(vcpu);
4507 return 1;
4508}
4509
020df079
GN		 4510static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4511{
4512 vmcs_writel(GUEST_DR7, val);
4513}
4514
851ba692 4515static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4516{
06465c5a
AK		 4517 kvm_emulate_cpuid(vcpu);
4518 return 1;
6aa8b732
AK		 4519}
4520
851ba692 4521static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4522{
ad312c7c 4523 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4524 u64 data;
4525
4526 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4527 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4528 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4529 return 1;
4530 }
4531
229456fc 4532 trace_kvm_msr_read(ecx, data);
2714d1d3 4533
6aa8b732 4534 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4535 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4536 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4537 skip_emulated_instruction(vcpu);
4538 return 1;
4539}
4540
851ba692 4541static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4542{
ad312c7c
ZX		 4543 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4544 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4545 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4546
4547 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4548 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4549 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4550 return 1;
4551 }
4552
59200273 4553 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4554 skip_emulated_instruction(vcpu);
4555 return 1;
4556}
4557
851ba692 4558static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4559{
3842d135 4560 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4561 return 1;
4562}
4563
851ba692 4564static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4565{
85f455f7
ED		 4566 u32 cpu_based_vm_exec_control;
4567
4568 /* clear pending irq */
4569 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4570 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4571 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4572
3842d135
AK		 4573 kvm_make_request(KVM_REQ_EVENT, vcpu);
4574
a26bf12a 4575 ++vcpu->stat.irq_window_exits;
2714d1d3 4576
c1150d8c
DL		 4577 /*
4578 * If the user space waits to inject interrupts, exit as soon as
4579 * possible
4580 */
8061823a 4581 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4582 vcpu->run->request_interrupt_window &&
8061823a 4583 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4584 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4585 return 0;
4586 }
6aa8b732
AK		 4587 return 1;
4588}
4589
851ba692 4590static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4591{
4592 skip_emulated_instruction(vcpu);
d3bef15f 4593 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4594}
4595
851ba692 4596static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4597{
510043da 4598 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4599 kvm_emulate_hypercall(vcpu);
4600 return 1;
c21415e8
IM		 4601}
4602
ec25d5e6
GN		 4603static int handle_invd(struct kvm_vcpu *vcpu)
4604{
51d8b661 4605 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4606}
4607
851ba692 4608static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4609{
f9c617f6 4610 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4611
4612 kvm_mmu_invlpg(vcpu, exit_qualification);
4613 skip_emulated_instruction(vcpu);
4614 return 1;
4615}
4616
851ba692 4617static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4618{
4619 skip_emulated_instruction(vcpu);
f5f48ee1 4620 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4621 return 1;
4622}
4623
2acf923e
DC		 4624static int handle_xsetbv(struct kvm_vcpu *vcpu)
4625{
4626 u64 new_bv = kvm_read_edx_eax(vcpu);
4627 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4628
4629 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4630 skip_emulated_instruction(vcpu);
4631 return 1;
4632}
4633
851ba692 4634static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4635{
58fbbf26
KT		 4636 if (likely(fasteoi)) {
4637 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4638 int access_type, offset;
4639
4640 access_type = exit_qualification & APIC_ACCESS_TYPE;
4641 offset = exit_qualification & APIC_ACCESS_OFFSET;
4642 /*
4643 * Sane guest uses MOV to write EOI, with written value
4644 * not cared. So make a short-circuit here by avoiding
4645 * heavy instruction emulation.
4646 */
4647 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4648 (offset == APIC_EOI)) {
4649 kvm_lapic_set_eoi(vcpu);
4650 skip_emulated_instruction(vcpu);
4651 return 1;
4652 }
4653 }
51d8b661 4654 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4655}
4656
851ba692 4657static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4658{
60637aac 4659 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4660 unsigned long exit_qualification;
e269fb21
JK		 4661 bool has_error_code = false;
4662 u32 error_code = 0;
37817f29 4663 u16 tss_selector;
64a7ec06
GN		 4664 int reason, type, idt_v;
4665
4666 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4667 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4668
4669 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4670
4671 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4672 if (reason == TASK_SWITCH_GATE && idt_v) {
4673 switch (type) {
4674 case INTR_TYPE_NMI_INTR:
4675 vcpu->arch.nmi_injected = false;
654f06fc 4676 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4677 break;
4678 case INTR_TYPE_EXT_INTR:
66fd3f7f 4679 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4680 kvm_clear_interrupt_queue(vcpu);
4681 break;
4682 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4683 if (vmx->idt_vectoring_info &
4684 VECTORING_INFO_DELIVER_CODE_MASK) {
4685 has_error_code = true;
4686 error_code =
4687 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4688 }
4689 /* fall through */
64a7ec06
GN		 4690 case INTR_TYPE_SOFT_EXCEPTION:
4691 kvm_clear_exception_queue(vcpu);
4692 break;
4693 default:
4694 break;
4695 }
60637aac 4696 }
37817f29
IE		 4697 tss_selector = exit_qualification;
4698
64a7ec06
GN		 4699 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4700 type != INTR_TYPE_EXT_INTR &&
4701 type != INTR_TYPE_NMI_INTR))
4702 skip_emulated_instruction(vcpu);
4703
acb54517
GN		 4704 if (kvm_task_switch(vcpu, tss_selector, reason,
4705 has_error_code, error_code) == EMULATE_FAIL) {
4706 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4707 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4708 vcpu->run->internal.ndata = 0;
42dbaa5a 4709 return 0;
acb54517 4710 }
42dbaa5a
JK		 4711
4712 /* clear all local breakpoint enable flags */
4713 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4714
4715 /*
4716 * TODO: What about debug traps on tss switch?
4717 * Are we supposed to inject them and update dr6?
4718 */
4719
4720 return 1;
37817f29
IE		 4721}
4722
851ba692 4723static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4724{
f9c617f6 4725 unsigned long exit_qualification;
1439442c 4726 gpa_t gpa;
1439442c 4727 int gla_validity;
1439442c 4728
f9c617f6 4729 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4730
4731 if (exit_qualification & (1 << 6)) {
4732 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4733 return -EINVAL;
1439442c
SY		 4734 }
4735
4736 gla_validity = (exit_qualification >> 7) & 0x3;
4737 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4738 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4739 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4740 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4741 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4742 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4743 (long unsigned int)exit_qualification);
851ba692
AK		 4744 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4745 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4746 return 0;
1439442c
SY		 4747 }
4748
4749 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4750 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4751 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4752}
4753
68f89400
MT		 4754static u64 ept_rsvd_mask(u64 spte, int level)
4755{
4756 int i;
4757 u64 mask = 0;
4758
4759 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4760 mask |= (1ULL << i);
4761
4762 if (level > 2)
4763 /* bits 7:3 reserved */
4764 mask |= 0xf8;
4765 else if (level == 2) {
4766 if (spte & (1ULL << 7))
4767 /* 2MB ref, bits 20:12 reserved */
4768 mask |= 0x1ff000;
4769 else
4770 /* bits 6:3 reserved */
4771 mask |= 0x78;
4772 }
4773
4774 return mask;
4775}
4776
4777static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4778 int level)
4779{
4780 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4781
4782 /* 010b (write-only) */
4783 WARN_ON((spte & 0x7) == 0x2);
4784
4785 /* 110b (write/execute) */
4786 WARN_ON((spte & 0x7) == 0x6);
4787
4788 /* 100b (execute-only) and value not supported by logical processor */
4789 if (!cpu_has_vmx_ept_execute_only())
4790 WARN_ON((spte & 0x7) == 0x4);
4791
4792 /* not 000b */
4793 if ((spte & 0x7)) {
4794 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4795
4796 if (rsvd_bits != 0) {
4797 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4798 __func__, rsvd_bits);
4799 WARN_ON(1);
4800 }
4801
4802 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4803 u64 ept_mem_type = (spte & 0x38) >> 3;
4804
4805 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4806 ept_mem_type == 7) {
4807 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4808 __func__, ept_mem_type);
4809 WARN_ON(1);
4810 }
4811 }
4812 }
4813}
4814
851ba692 4815static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4816{
4817 u64 sptes[4];
ce88decf 4818 int nr_sptes, i, ret;
68f89400
MT		 4819 gpa_t gpa;
4820
4821 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4822
ce88decf
XG		 4823 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4824 if (likely(ret == 1))
4825 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4826 EMULATE_DONE;
4827 if (unlikely(!ret))
4828 return 1;
4829
4830 /* It is the real ept misconfig */
68f89400
MT		 4831 printk(KERN_ERR "EPT: Misconfiguration.\n");
4832 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4833
4834 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4835
4836 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4837 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4838
851ba692
AK		 4839 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4840 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4841
4842 return 0;
4843}
4844
851ba692 4845static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4846{
4847 u32 cpu_based_vm_exec_control;
4848
4849 /* clear pending NMI */
4850 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4851 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4853 ++vcpu->stat.nmi_window_exits;
3842d135 4854 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4855
4856 return 1;
4857}
4858
80ced186 4859static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4860{
8b3079a5
AK		 4861 struct vcpu_vmx *vmx = to_vmx(vcpu);
4862 enum emulation_result err = EMULATE_DONE;
80ced186 4863 int ret = 1;
49e9d557
AK		 4864 u32 cpu_exec_ctrl;
4865 bool intr_window_requested;
4866
4867 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4868 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4869
4870 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4871 if (intr_window_requested
4872 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4873 return handle_interrupt_window(&vmx->vcpu);
4874
51d8b661 4875 err = emulate_instruction(vcpu, 0);
ea953ef0 4876
80ced186
MG		 4877 if (err == EMULATE_DO_MMIO) {
4878 ret = 0;
4879 goto out;
4880 }
1d5a4d9b 4881
6d77dbfc
GN		 4882 if (err != EMULATE_DONE)
4883 return 0;
ea953ef0
MG		 4884
4885 if (signal_pending(current))
80ced186 4886 goto out;
ea953ef0
MG		 4887 if (need_resched())
4888 schedule();
4889 }
4890
80ced186
MG		 4891 vmx->emulation_required = 0;
4892out:
4893 return ret;
ea953ef0
MG		 4894}
4895
4b8d54f9
ZE		 4896/*
4897 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4898 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4899 */
9fb41ba8 4900static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4901{
4902 skip_emulated_instruction(vcpu);
4903 kvm_vcpu_on_spin(vcpu);
4904
4905 return 1;
4906}
4907
59708670
SY		 4908static int handle_invalid_op(struct kvm_vcpu *vcpu)
4909{
4910 kvm_queue_exception(vcpu, UD_VECTOR);
4911 return 1;
4912}
4913
ff2f6fe9
NHE		 4914/*
4915 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4916 * We could reuse a single VMCS for all the L2 guests, but we also want the
4917 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4918 * allows keeping them loaded on the processor, and in the future will allow
4919 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4920 * every entry if they never change.
4921 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4922 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4923 *
4924 * The following functions allocate and free a vmcs02 in this pool.
4925 */
4926
4927/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4928static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4929{
4930 struct vmcs02_list *item;
4931 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4932 if (item->vmptr == vmx->nested.current_vmptr) {
4933 list_move(&item->list, &vmx->nested.vmcs02_pool);
4934 return &item->vmcs02;
4935 }
4936
4937 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4938 /* Recycle the least recently used VMCS. */
4939 item = list_entry(vmx->nested.vmcs02_pool.prev,
4940 struct vmcs02_list, list);
4941 item->vmptr = vmx->nested.current_vmptr;
4942 list_move(&item->list, &vmx->nested.vmcs02_pool);
4943 return &item->vmcs02;
4944 }
4945
4946 /* Create a new VMCS */
4947 item = (struct vmcs02_list *)
4948 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4949 if (!item)
4950 return NULL;
4951 item->vmcs02.vmcs = alloc_vmcs();
4952 if (!item->vmcs02.vmcs) {
4953 kfree(item);
4954 return NULL;
4955 }
4956 loaded_vmcs_init(&item->vmcs02);
4957 item->vmptr = vmx->nested.current_vmptr;
4958 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4959 vmx->nested.vmcs02_num++;
4960 return &item->vmcs02;
4961}
4962
4963/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4964static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4965{
4966 struct vmcs02_list *item;
4967 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4968 if (item->vmptr == vmptr) {
4969 free_loaded_vmcs(&item->vmcs02);
4970 list_del(&item->list);
4971 kfree(item);
4972 vmx->nested.vmcs02_num--;
4973 return;
4974 }
4975}
4976
4977/*
4978 * Free all VMCSs saved for this vcpu, except the one pointed by
4979 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4980 * currently used, if running L2), and vmcs01 when running L2.
4981 */
4982static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4983{
4984 struct vmcs02_list *item, *n;
4985 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4986 if (vmx->loaded_vmcs != &item->vmcs02)
4987 free_loaded_vmcs(&item->vmcs02);
4988 list_del(&item->list);
4989 kfree(item);
4990 }
4991 vmx->nested.vmcs02_num = 0;
4992
4993 if (vmx->loaded_vmcs != &vmx->vmcs01)
4994 free_loaded_vmcs(&vmx->vmcs01);
4995}
4996
ec378aee
NHE		 4997/*
4998 * Emulate the VMXON instruction.
4999 * Currently, we just remember that VMX is active, and do not save or even
5000 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5001 * do not currently need to store anything in that guest-allocated memory
5002 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5003 * argument is different from the VMXON pointer (which the spec says they do).
5004 */
5005static int handle_vmon(struct kvm_vcpu *vcpu)
5006{
5007 struct kvm_segment cs;
5008 struct vcpu_vmx *vmx = to_vmx(vcpu);
5009
5010 /* The Intel VMX Instruction Reference lists a bunch of bits that
5011 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5012 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5013 * Otherwise, we should fail with #UD. We test these now:
5014 */
5015 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5016 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5017 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5018 kvm_queue_exception(vcpu, UD_VECTOR);
5019 return 1;
5020 }
5021
5022 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5023 if (is_long_mode(vcpu) && !cs.l) {
5024 kvm_queue_exception(vcpu, UD_VECTOR);
5025 return 1;
5026 }
5027
5028 if (vmx_get_cpl(vcpu)) {
5029 kvm_inject_gp(vcpu, 0);
5030 return 1;
5031 }
5032
ff2f6fe9
NHE		 5033 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5034 vmx->nested.vmcs02_num = 0;
5035
ec378aee
NHE		 5036 vmx->nested.vmxon = true;
5037
5038 skip_emulated_instruction(vcpu);
5039 return 1;
5040}
5041
5042/*
5043 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5044 * for running VMX instructions (except VMXON, whose prerequisites are
5045 * slightly different). It also specifies what exception to inject otherwise.
5046 */
5047static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5048{
5049 struct kvm_segment cs;
5050 struct vcpu_vmx *vmx = to_vmx(vcpu);
5051
5052 if (!vmx->nested.vmxon) {
5053 kvm_queue_exception(vcpu, UD_VECTOR);
5054 return 0;
5055 }
5056
5057 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5058 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5059 (is_long_mode(vcpu) && !cs.l)) {
5060 kvm_queue_exception(vcpu, UD_VECTOR);
5061 return 0;
5062 }
5063
5064 if (vmx_get_cpl(vcpu)) {
5065 kvm_inject_gp(vcpu, 0);
5066 return 0;
5067 }
5068
5069 return 1;
5070}
5071
5072/*
5073 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5074 * just stops using VMX.
5075 */
5076static void free_nested(struct vcpu_vmx *vmx)
5077{
5078 if (!vmx->nested.vmxon)
5079 return;
5080 vmx->nested.vmxon = false;
a9d30f33
NHE		 5081 if (vmx->nested.current_vmptr != -1ull) {
5082 kunmap(vmx->nested.current_vmcs12_page);
5083 nested_release_page(vmx->nested.current_vmcs12_page);
5084 vmx->nested.current_vmptr = -1ull;
5085 vmx->nested.current_vmcs12 = NULL;
5086 }
fe3ef05c
NHE		 5087 /* Unpin physical memory we referred to in current vmcs02 */
5088 if (vmx->nested.apic_access_page) {
5089 nested_release_page(vmx->nested.apic_access_page);
5090 vmx->nested.apic_access_page = 0;
5091 }
ff2f6fe9
NHE		 5092
5093 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5094}
5095
5096/* Emulate the VMXOFF instruction */
5097static int handle_vmoff(struct kvm_vcpu *vcpu)
5098{
5099 if (!nested_vmx_check_permission(vcpu))
5100 return 1;
5101 free_nested(to_vmx(vcpu));
5102 skip_emulated_instruction(vcpu);
5103 return 1;
5104}
5105
064aea77
NHE		 5106/*
5107 * Decode the memory-address operand of a vmx instruction, as recorded on an
5108 * exit caused by such an instruction (run by a guest hypervisor).
5109 * On success, returns 0. When the operand is invalid, returns 1 and throws
5110 * #UD or #GP.
5111 */
5112static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5113 unsigned long exit_qualification,
5114 u32 vmx_instruction_info, gva_t *ret)
5115{
5116 /*
5117 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5118 * Execution", on an exit, vmx_instruction_info holds most of the
5119 * addressing components of the operand. Only the displacement part
5120 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5121 * For how an actual address is calculated from all these components,
5122 * refer to Vol. 1, "Operand Addressing".
5123 */
5124 int scaling = vmx_instruction_info & 3;
5125 int addr_size = (vmx_instruction_info >> 7) & 7;
5126 bool is_reg = vmx_instruction_info & (1u << 10);
5127 int seg_reg = (vmx_instruction_info >> 15) & 7;
5128 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5129 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5130 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5131 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5132
5133 if (is_reg) {
5134 kvm_queue_exception(vcpu, UD_VECTOR);
5135 return 1;
5136 }
5137
5138 /* Addr = segment_base + offset */
5139 /* offset = base + [index * scale] + displacement */
5140 *ret = vmx_get_segment_base(vcpu, seg_reg);
5141 if (base_is_valid)
5142 *ret += kvm_register_read(vcpu, base_reg);
5143 if (index_is_valid)
5144 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5145 *ret += exit_qualification; /* holds the displacement */
5146
5147 if (addr_size == 1) /* 32 bit */
5148 *ret &= 0xffffffff;
5149
5150 /*
5151 * TODO: throw #GP (and return 1) in various cases that the VM*
5152 * instructions require it - e.g., offset beyond segment limit,
5153 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5154 * address, and so on. Currently these are not checked.
5155 */
5156 return 0;
5157}
5158
0140caea
NHE		 5159/*
5160 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5161 * set the success or error code of an emulated VMX instruction, as specified
5162 * by Vol 2B, VMX Instruction Reference, "Conventions".
5163 */
5164static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5165{
5166 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5167 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5168 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5169}
5170
5171static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5172{
5173 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5174 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5175 X86_EFLAGS_SF | X86_EFLAGS_OF))
5176 | X86_EFLAGS_CF);
5177}
5178
5179static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5180 u32 vm_instruction_error)
5181{
5182 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5183 /*
5184 * failValid writes the error number to the current VMCS, which
5185 * can't be done there isn't a current VMCS.
5186 */
5187 nested_vmx_failInvalid(vcpu);
5188 return;
5189 }
5190 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5191 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5192 X86_EFLAGS_SF | X86_EFLAGS_OF))
5193 | X86_EFLAGS_ZF);
5194 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5195}
5196
27d6c865
NHE		 5197/* Emulate the VMCLEAR instruction */
5198static int handle_vmclear(struct kvm_vcpu *vcpu)
5199{
5200 struct vcpu_vmx *vmx = to_vmx(vcpu);
5201 gva_t gva;
5202 gpa_t vmptr;
5203 struct vmcs12 *vmcs12;
5204 struct page *page;
5205 struct x86_exception e;
5206
5207 if (!nested_vmx_check_permission(vcpu))
5208 return 1;
5209
5210 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5211 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5212 return 1;
5213
5214 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5215 sizeof(vmptr), &e)) {
5216 kvm_inject_page_fault(vcpu, &e);
5217 return 1;
5218 }
5219
5220 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5221 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5222 skip_emulated_instruction(vcpu);
5223 return 1;
5224 }
5225
5226 if (vmptr == vmx->nested.current_vmptr) {
5227 kunmap(vmx->nested.current_vmcs12_page);
5228 nested_release_page(vmx->nested.current_vmcs12_page);
5229 vmx->nested.current_vmptr = -1ull;
5230 vmx->nested.current_vmcs12 = NULL;
5231 }
5232
5233 page = nested_get_page(vcpu, vmptr);
5234 if (page == NULL) {
5235 /*
5236 * For accurate processor emulation, VMCLEAR beyond available
5237 * physical memory should do nothing at all. However, it is
5238 * possible that a nested vmx bug, not a guest hypervisor bug,
5239 * resulted in this case, so let's shut down before doing any
5240 * more damage:
5241 */
5242 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5243 return 1;
5244 }
5245 vmcs12 = kmap(page);
5246 vmcs12->launch_state = 0;
5247 kunmap(page);
5248 nested_release_page(page);
5249
5250 nested_free_vmcs02(vmx, vmptr);
5251
5252 skip_emulated_instruction(vcpu);
5253 nested_vmx_succeed(vcpu);
5254 return 1;
5255}
5256
cd232ad0
NHE		 5257static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5258
5259/* Emulate the VMLAUNCH instruction */
5260static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5261{
5262 return nested_vmx_run(vcpu, true);
5263}
5264
5265/* Emulate the VMRESUME instruction */
5266static int handle_vmresume(struct kvm_vcpu *vcpu)
5267{
5268
5269 return nested_vmx_run(vcpu, false);
5270}
5271
49f705c5
NHE		 5272enum vmcs_field_type {
5273 VMCS_FIELD_TYPE_U16 = 0,
5274 VMCS_FIELD_TYPE_U64 = 1,
5275 VMCS_FIELD_TYPE_U32 = 2,
5276 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5277};
5278
5279static inline int vmcs_field_type(unsigned long field)
5280{
5281 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5282 return VMCS_FIELD_TYPE_U32;
5283 return (field >> 13) & 0x3 ;
5284}
5285
5286static inline int vmcs_field_readonly(unsigned long field)
5287{
5288 return (((field >> 10) & 0x3) == 1);
5289}
5290
5291/*
5292 * Read a vmcs12 field. Since these can have varying lengths and we return
5293 * one type, we chose the biggest type (u64) and zero-extend the return value
5294 * to that size. Note that the caller, handle_vmread, might need to use only
5295 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5296 * 64-bit fields are to be returned).
5297 */
5298static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5299 unsigned long field, u64 *ret)
5300{
5301 short offset = vmcs_field_to_offset(field);
5302 char *p;
5303
5304 if (offset < 0)
5305 return 0;
5306
5307 p = ((char *)(get_vmcs12(vcpu))) + offset;
5308
5309 switch (vmcs_field_type(field)) {
5310 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5311 *ret = *((natural_width *)p);
5312 return 1;
5313 case VMCS_FIELD_TYPE_U16:
5314 *ret = *((u16 *)p);
5315 return 1;
5316 case VMCS_FIELD_TYPE_U32:
5317 *ret = *((u32 *)p);
5318 return 1;
5319 case VMCS_FIELD_TYPE_U64:
5320 *ret = *((u64 *)p);
5321 return 1;
5322 default:
5323 return 0; /* can never happen. */
5324 }
5325}
5326
5327/*
5328 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5329 * used before) all generate the same failure when it is missing.
5330 */
5331static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5332{
5333 struct vcpu_vmx *vmx = to_vmx(vcpu);
5334 if (vmx->nested.current_vmptr == -1ull) {
5335 nested_vmx_failInvalid(vcpu);
5336 skip_emulated_instruction(vcpu);
5337 return 0;
5338 }
5339 return 1;
5340}
5341
5342static int handle_vmread(struct kvm_vcpu *vcpu)
5343{
5344 unsigned long field;
5345 u64 field_value;
5346 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5347 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5348 gva_t gva = 0;
5349
5350 if (!nested_vmx_check_permission(vcpu) ||
5351 !nested_vmx_check_vmcs12(vcpu))
5352 return 1;
5353
5354 /* Decode instruction info and find the field to read */
5355 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5356 /* Read the field, zero-extended to a u64 field_value */
5357 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5358 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5359 skip_emulated_instruction(vcpu);
5360 return 1;
5361 }
5362 /*
5363 * Now copy part of this value to register or memory, as requested.
5364 * Note that the number of bits actually copied is 32 or 64 depending
5365 * on the guest's mode (32 or 64 bit), not on the given field's length.
5366 */
5367 if (vmx_instruction_info & (1u << 10)) {
5368 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5369 field_value);
5370 } else {
5371 if (get_vmx_mem_address(vcpu, exit_qualification,
5372 vmx_instruction_info, &gva))
5373 return 1;
5374 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5375 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5376 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5377 }
5378
5379 nested_vmx_succeed(vcpu);
5380 skip_emulated_instruction(vcpu);
5381 return 1;
5382}
5383
5384
5385static int handle_vmwrite(struct kvm_vcpu *vcpu)
5386{
5387 unsigned long field;
5388 gva_t gva;
5389 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5390 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5391 char *p;
5392 short offset;
5393 /* The value to write might be 32 or 64 bits, depending on L1's long
5394 * mode, and eventually we need to write that into a field of several
5395 * possible lengths. The code below first zero-extends the value to 64
5396 * bit (field_value), and then copies only the approriate number of
5397 * bits into the vmcs12 field.
5398 */
5399 u64 field_value = 0;
5400 struct x86_exception e;
5401
5402 if (!nested_vmx_check_permission(vcpu) ||
5403 !nested_vmx_check_vmcs12(vcpu))
5404 return 1;
5405
5406 if (vmx_instruction_info & (1u << 10))
5407 field_value = kvm_register_read(vcpu,
5408 (((vmx_instruction_info) >> 3) & 0xf));
5409 else {
5410 if (get_vmx_mem_address(vcpu, exit_qualification,
5411 vmx_instruction_info, &gva))
5412 return 1;
5413 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5414 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5415 kvm_inject_page_fault(vcpu, &e);
5416 return 1;
5417 }
5418 }
5419
5420
5421 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5422 if (vmcs_field_readonly(field)) {
5423 nested_vmx_failValid(vcpu,
5424 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5425 skip_emulated_instruction(vcpu);
5426 return 1;
5427 }
5428
5429 offset = vmcs_field_to_offset(field);
5430 if (offset < 0) {
5431 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5432 skip_emulated_instruction(vcpu);
5433 return 1;
5434 }
5435 p = ((char *) get_vmcs12(vcpu)) + offset;
5436
5437 switch (vmcs_field_type(field)) {
5438 case VMCS_FIELD_TYPE_U16:
5439 *(u16 *)p = field_value;
5440 break;
5441 case VMCS_FIELD_TYPE_U32:
5442 *(u32 *)p = field_value;
5443 break;
5444 case VMCS_FIELD_TYPE_U64:
5445 *(u64 *)p = field_value;
5446 break;
5447 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5448 *(natural_width *)p = field_value;
5449 break;
5450 default:
5451 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5452 skip_emulated_instruction(vcpu);
5453 return 1;
5454 }
5455
5456 nested_vmx_succeed(vcpu);
5457 skip_emulated_instruction(vcpu);
5458 return 1;
5459}
5460
63846663
NHE		 5461/* Emulate the VMPTRLD instruction */
5462static int handle_vmptrld(struct kvm_vcpu *vcpu)
5463{
5464 struct vcpu_vmx *vmx = to_vmx(vcpu);
5465 gva_t gva;
5466 gpa_t vmptr;
5467 struct x86_exception e;
5468
5469 if (!nested_vmx_check_permission(vcpu))
5470 return 1;
5471
5472 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5473 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5474 return 1;
5475
5476 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5477 sizeof(vmptr), &e)) {
5478 kvm_inject_page_fault(vcpu, &e);
5479 return 1;
5480 }
5481
5482 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5483 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5484 skip_emulated_instruction(vcpu);
5485 return 1;
5486 }
5487
5488 if (vmx->nested.current_vmptr != vmptr) {
5489 struct vmcs12 *new_vmcs12;
5490 struct page *page;
5491 page = nested_get_page(vcpu, vmptr);
5492 if (page == NULL) {
5493 nested_vmx_failInvalid(vcpu);
5494 skip_emulated_instruction(vcpu);
5495 return 1;
5496 }
5497 new_vmcs12 = kmap(page);
5498 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5499 kunmap(page);
5500 nested_release_page_clean(page);
5501 nested_vmx_failValid(vcpu,
5502 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5503 skip_emulated_instruction(vcpu);
5504 return 1;
5505 }
5506 if (vmx->nested.current_vmptr != -1ull) {
5507 kunmap(vmx->nested.current_vmcs12_page);
5508 nested_release_page(vmx->nested.current_vmcs12_page);
5509 }
5510
5511 vmx->nested.current_vmptr = vmptr;
5512 vmx->nested.current_vmcs12 = new_vmcs12;
5513 vmx->nested.current_vmcs12_page = page;
5514 }
5515
5516 nested_vmx_succeed(vcpu);
5517 skip_emulated_instruction(vcpu);
5518 return 1;
5519}
5520
6a4d7550
NHE		 5521/* Emulate the VMPTRST instruction */
5522static int handle_vmptrst(struct kvm_vcpu *vcpu)
5523{
5524 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5525 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5526 gva_t vmcs_gva;
5527 struct x86_exception e;
5528
5529 if (!nested_vmx_check_permission(vcpu))
5530 return 1;
5531
5532 if (get_vmx_mem_address(vcpu, exit_qualification,
5533 vmx_instruction_info, &vmcs_gva))
5534 return 1;
5535 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5536 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5537 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5538 sizeof(u64), &e)) {
5539 kvm_inject_page_fault(vcpu, &e);
5540 return 1;
5541 }
5542 nested_vmx_succeed(vcpu);
5543 skip_emulated_instruction(vcpu);
5544 return 1;
5545}
5546
6aa8b732
AK		 5547/*
5548 * The exit handlers return 1 if the exit was handled fully and guest execution
5549 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5550 * to be done to userspace and return 0.
5551 */
851ba692 5552static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5553 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5554 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5555 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5556 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5557 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5558 [EXIT_REASON_CR_ACCESS] = handle_cr,
5559 [EXIT_REASON_DR_ACCESS] = handle_dr,
5560 [EXIT_REASON_CPUID] = handle_cpuid,
5561 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5562 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5563 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5564 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5565 [EXIT_REASON_INVD] = handle_invd,
a7052897 5566 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5567 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5568 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5569 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5570 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5571 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5572 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5573 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5574 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5575 [EXIT_REASON_VMOFF] = handle_vmoff,
5576 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5577 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5578 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5579 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5580 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5581 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5582 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5583 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5584 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5585 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5586 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5587 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5588};
5589
5590static const int kvm_vmx_max_exit_handlers =
50a3485c 5591 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5592
644d711a
NHE		 5593/*
5594 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5595 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5596 * disinterest in the current event (read or write a specific MSR) by using an
5597 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5598 */
5599static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5600 struct vmcs12 *vmcs12, u32 exit_reason)
5601{
5602 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5603 gpa_t bitmap;
5604
5605 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5606 return 1;
5607
5608 /*
5609 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5610 * for the four combinations of read/write and low/high MSR numbers.
5611 * First we need to figure out which of the four to use:
5612 */
5613 bitmap = vmcs12->msr_bitmap;
5614 if (exit_reason == EXIT_REASON_MSR_WRITE)
5615 bitmap += 2048;
5616 if (msr_index >= 0xc0000000) {
5617 msr_index -= 0xc0000000;
5618 bitmap += 1024;
5619 }
5620
5621 /* Then read the msr_index'th bit from this bitmap: */
5622 if (msr_index < 1024*8) {
5623 unsigned char b;
5624 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5625 return 1 & (b >> (msr_index & 7));
5626 } else
5627 return 1; /* let L1 handle the wrong parameter */
5628}
5629
5630/*
5631 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5632 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5633 * intercept (via guest_host_mask etc.) the current event.
5634 */
5635static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5636 struct vmcs12 *vmcs12)
5637{
5638 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5639 int cr = exit_qualification & 15;
5640 int reg = (exit_qualification >> 8) & 15;
5641 unsigned long val = kvm_register_read(vcpu, reg);
5642
5643 switch ((exit_qualification >> 4) & 3) {
5644 case 0: /* mov to cr */
5645 switch (cr) {
5646 case 0:
5647 if (vmcs12->cr0_guest_host_mask &
5648 (val ^ vmcs12->cr0_read_shadow))
5649 return 1;
5650 break;
5651 case 3:
5652 if ((vmcs12->cr3_target_count >= 1 &&
5653 vmcs12->cr3_target_value0 == val) ||
5654 (vmcs12->cr3_target_count >= 2 &&
5655 vmcs12->cr3_target_value1 == val) ||
5656 (vmcs12->cr3_target_count >= 3 &&
5657 vmcs12->cr3_target_value2 == val) ||
5658 (vmcs12->cr3_target_count >= 4 &&
5659 vmcs12->cr3_target_value3 == val))
5660 return 0;
5661 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5662 return 1;
5663 break;
5664 case 4:
5665 if (vmcs12->cr4_guest_host_mask &
5666 (vmcs12->cr4_read_shadow ^ val))
5667 return 1;
5668 break;
5669 case 8:
5670 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5671 return 1;
5672 break;
5673 }
5674 break;
5675 case 2: /* clts */
5676 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5677 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5678 return 1;
5679 break;
5680 case 1: /* mov from cr */
5681 switch (cr) {
5682 case 3:
5683 if (vmcs12->cpu_based_vm_exec_control &
5684 CPU_BASED_CR3_STORE_EXITING)
5685 return 1;
5686 break;
5687 case 8:
5688 if (vmcs12->cpu_based_vm_exec_control &
5689 CPU_BASED_CR8_STORE_EXITING)
5690 return 1;
5691 break;
5692 }
5693 break;
5694 case 3: /* lmsw */
5695 /*
5696 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5697 * cr0. Other attempted changes are ignored, with no exit.
5698 */
5699 if (vmcs12->cr0_guest_host_mask & 0xe &
5700 (val ^ vmcs12->cr0_read_shadow))
5701 return 1;
5702 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5703 !(vmcs12->cr0_read_shadow & 0x1) &&
5704 (val & 0x1))
5705 return 1;
5706 break;
5707 }
5708 return 0;
5709}
5710
5711/*
5712 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5713 * should handle it ourselves in L0 (and then continue L2). Only call this
5714 * when in is_guest_mode (L2).
5715 */
5716static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5717{
5718 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5719 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5720 struct vcpu_vmx *vmx = to_vmx(vcpu);
5721 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5722
5723 if (vmx->nested.nested_run_pending)
5724 return 0;
5725
5726 if (unlikely(vmx->fail)) {
bd80158a
JK		 5727 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5728 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5729 return 1;
5730 }
5731
5732 switch (exit_reason) {
5733 case EXIT_REASON_EXCEPTION_NMI:
5734 if (!is_exception(intr_info))
5735 return 0;
5736 else if (is_page_fault(intr_info))
5737 return enable_ept;
5738 return vmcs12->exception_bitmap &
5739 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5740 case EXIT_REASON_EXTERNAL_INTERRUPT:
5741 return 0;
5742 case EXIT_REASON_TRIPLE_FAULT:
5743 return 1;
5744 case EXIT_REASON_PENDING_INTERRUPT:
5745 case EXIT_REASON_NMI_WINDOW:
5746 /*
5747 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5748 * (aka Interrupt Window Exiting) only when L1 turned it on,
5749 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5750 * Same for NMI Window Exiting.
5751 */
5752 return 1;
5753 case EXIT_REASON_TASK_SWITCH:
5754 return 1;
5755 case EXIT_REASON_CPUID:
5756 return 1;
5757 case EXIT_REASON_HLT:
5758 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5759 case EXIT_REASON_INVD:
5760 return 1;
5761 case EXIT_REASON_INVLPG:
5762 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5763 case EXIT_REASON_RDPMC:
5764 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5765 case EXIT_REASON_RDTSC:
5766 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5767 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5768 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5769 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5770 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5771 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5772 /*
5773 * VMX instructions trap unconditionally. This allows L1 to
5774 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5775 */
5776 return 1;
5777 case EXIT_REASON_CR_ACCESS:
5778 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5779 case EXIT_REASON_DR_ACCESS:
5780 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5781 case EXIT_REASON_IO_INSTRUCTION:
5782 /* TODO: support IO bitmaps */
5783 return 1;
5784 case EXIT_REASON_MSR_READ:
5785 case EXIT_REASON_MSR_WRITE:
5786 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5787 case EXIT_REASON_INVALID_STATE:
5788 return 1;
5789 case EXIT_REASON_MWAIT_INSTRUCTION:
5790 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5791 case EXIT_REASON_MONITOR_INSTRUCTION:
5792 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5793 case EXIT_REASON_PAUSE_INSTRUCTION:
5794 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5795 nested_cpu_has2(vmcs12,
5796 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5797 case EXIT_REASON_MCE_DURING_VMENTRY:
5798 return 0;
5799 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5800 return 1;
5801 case EXIT_REASON_APIC_ACCESS:
5802 return nested_cpu_has2(vmcs12,
5803 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5804 case EXIT_REASON_EPT_VIOLATION:
5805 case EXIT_REASON_EPT_MISCONFIG:
5806 return 0;
5807 case EXIT_REASON_WBINVD:
5808 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5809 case EXIT_REASON_XSETBV:
5810 return 1;
5811 default:
5812 return 1;
5813 }
5814}
5815
586f9607
AK		 5816static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5817{
5818 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5819 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5820}
5821
6aa8b732
AK		 5822/*
5823 * The guest has exited. See if we can fix it or if we need userspace
5824 * assistance.
5825 */
851ba692 5826static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5827{
29bd8a78 5828 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5829 u32 exit_reason = vmx->exit_reason;
1155f76a 5830 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5831
80ced186
MG		 5832 /* If guest state is invalid, start emulating */
5833 if (vmx->emulation_required && emulate_invalid_guest_state)
5834 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5835
b6f1250e
NHE		 5836 /*
5837 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5838 * we did not inject a still-pending event to L1 now because of
5839 * nested_run_pending, we need to re-enable this bit.
5840 */
5841 if (vmx->nested.nested_run_pending)
5842 kvm_make_request(KVM_REQ_EVENT, vcpu);
5843
509c75ea
NHE		 5844 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5845 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5846 vmx->nested.nested_run_pending = 1;
5847 else
5848 vmx->nested.nested_run_pending = 0;
5849
5850 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5851 nested_vmx_vmexit(vcpu);
5852 return 1;
5853 }
5854
5120702e
MG		 5855 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5856 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5857 vcpu->run->fail_entry.hardware_entry_failure_reason
5858 = exit_reason;
5859 return 0;
5860 }
5861
29bd8a78 5862 if (unlikely(vmx->fail)) {
851ba692
AK		 5863 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5864 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5865 = vmcs_read32(VM_INSTRUCTION_ERROR);
5866 return 0;
5867 }
6aa8b732 5868
d77c26fc 5869 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5870 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5871 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5872 exit_reason != EXIT_REASON_TASK_SWITCH))
5873 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5874 "(0x%x) and exit reason is 0x%x\n",
5875 __func__, vectoring_info, exit_reason);
3b86cd99 5876
644d711a
NHE		 5877 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5878 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5879 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5880 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5881 vmx->soft_vnmi_blocked = 0;
3b86cd99 5882 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5883 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5884 /*
5885 * This CPU don't support us in finding the end of an
5886 * NMI-blocked window if the guest runs with IRQs
5887 * disabled. So we pull the trigger after 1 s of
5888 * futile waiting, but inform the user about this.
5889 */
5890 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5891 "state on VCPU %d after 1 s timeout\n",
5892 __func__, vcpu->vcpu_id);
5893 vmx->soft_vnmi_blocked = 0;
3b86cd99 5894 }
3b86cd99
JK		 5895 }
5896
6aa8b732
AK		 5897 if (exit_reason < kvm_vmx_max_exit_handlers
5898 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5899 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5900 else {
851ba692
AK		 5901 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5902 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5903 }
5904 return 0;
5905}
5906
95ba8273 5907static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5908{
95ba8273 5909 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5910 vmcs_write32(TPR_THRESHOLD, 0);
5911 return;
5912 }
5913
95ba8273 5914 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5915}
5916
51aa01d1 5917static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5918{
00eba012
AK		 5919 u32 exit_intr_info;
5920
5921 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5922 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5923 return;
5924
c5ca8e57 5925 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5926 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5927
5928 /* Handle machine checks before interrupts are enabled */
00eba012 5929 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5930 kvm_machine_check();
5931
20f65983 5932 /* We need to handle NMIs before interrupts are enabled */
00eba012 5933 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5934 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5935 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5936 asm("int $2");
ff9d07a0
ZY		 5937 kvm_after_handle_nmi(&vmx->vcpu);
5938 }
51aa01d1 5939}
20f65983 5940
51aa01d1
AK		 5941static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5942{
c5ca8e57 5943 u32 exit_intr_info;
51aa01d1
AK		 5944 bool unblock_nmi;
5945 u8 vector;
5946 bool idtv_info_valid;
5947
5948 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5949
cf393f75 5950 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5951 if (vmx->nmi_known_unmasked)
5952 return;
c5ca8e57
AK		 5953 /*
5954 * Can't use vmx->exit_intr_info since we're not sure what
5955 * the exit reason is.
5956 */
5957 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5958 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5959 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5960 /*
7b4a25cb 5961 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5962 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5963 * a guest IRET fault.
7b4a25cb
GN		 5964 * SDM 3: 23.2.2 (September 2008)
5965 * Bit 12 is undefined in any of the following cases:
5966 * If the VM exit sets the valid bit in the IDT-vectoring
5967 * information field.
5968 * If the VM exit is due to a double fault.
cf393f75 5969 */
7b4a25cb
GN		 5970 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5971 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5972 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5973 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5974 else
5975 vmx->nmi_known_unmasked =
5976 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5977 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5978 } else if (unlikely(vmx->soft_vnmi_blocked))
5979 vmx->vnmi_blocked_time +=
5980 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5981}
5982
83422e17
AK		 5983static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5984 u32 idt_vectoring_info,
5985 int instr_len_field,
5986 int error_code_field)
51aa01d1 5987{
51aa01d1
AK		 5988 u8 vector;
5989 int type;
5990 bool idtv_info_valid;
5991
5992 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5993
37b96e98
GN		 5994 vmx->vcpu.arch.nmi_injected = false;
5995 kvm_clear_exception_queue(&vmx->vcpu);
5996 kvm_clear_interrupt_queue(&vmx->vcpu);
5997
5998 if (!idtv_info_valid)
5999 return;
6000
3842d135
AK		 6001 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6002
668f612f
AK		 6003 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6004 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6005
64a7ec06 6006 switch (type) {
37b96e98
GN		 6007 case INTR_TYPE_NMI_INTR:
6008 vmx->vcpu.arch.nmi_injected = true;
668f612f 6009 /*
7b4a25cb 6010 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6011 * Clear bit "block by NMI" before VM entry if a NMI
6012 * delivery faulted.
668f612f 6013 */
654f06fc 6014 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6015 break;
37b96e98 6016 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6017 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6018 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6019 /* fall through */
6020 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6021 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6022 u32 err = vmcs_read32(error_code_field);
37b96e98 6023 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6024 } else
6025 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6026 break;
66fd3f7f
GN		 6027 case INTR_TYPE_SOFT_INTR:
6028 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6029 vmcs_read32(instr_len_field);
66fd3f7f 6030 /* fall through */
37b96e98 6031 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6032 kvm_queue_interrupt(&vmx->vcpu, vector,
6033 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6034 break;
6035 default:
6036 break;
f7d9238f 6037 }
cf393f75
AK		 6038}
6039
83422e17
AK		 6040static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6041{
66c78ae4
NHE		 6042 if (is_guest_mode(&vmx->vcpu))
6043 return;
83422e17
AK		 6044 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6045 VM_EXIT_INSTRUCTION_LEN,
6046 IDT_VECTORING_ERROR_CODE);
6047}
6048
b463a6f7
AK		 6049static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6050{
66c78ae4
NHE		 6051 if (is_guest_mode(vcpu))
6052 return;
b463a6f7
AK		 6053 __vmx_complete_interrupts(to_vmx(vcpu),
6054 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6055 VM_ENTRY_INSTRUCTION_LEN,
6056 VM_ENTRY_EXCEPTION_ERROR_CODE);
6057
6058 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6059}
6060
d7cd9796
GN		 6061static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6062{
6063 int i, nr_msrs;
6064 struct perf_guest_switch_msr *msrs;
6065
6066 msrs = perf_guest_get_msrs(&nr_msrs);
6067
6068 if (!msrs)
6069 return;
6070
6071 for (i = 0; i < nr_msrs; i++)
6072 if (msrs[i].host == msrs[i].guest)
6073 clear_atomic_switch_msr(vmx, msrs[i].msr);
6074 else
6075 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6076 msrs[i].host);
6077}
6078
c801949d
AK		 6079#ifdef CONFIG_X86_64
6080#define R "r"
6081#define Q "q"
6082#else
6083#define R "e"
6084#define Q "l"
6085#endif
6086
a3b5ba49 6087static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6088{
a2fa3e9f 6089 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6090
66c78ae4
NHE		 6091 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6092 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6093 if (vmcs12->idt_vectoring_info_field &
6094 VECTORING_INFO_VALID_MASK) {
6095 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6096 vmcs12->idt_vectoring_info_field);
6097 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6098 vmcs12->vm_exit_instruction_len);
6099 if (vmcs12->idt_vectoring_info_field &
6100 VECTORING_INFO_DELIVER_CODE_MASK)
6101 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6102 vmcs12->idt_vectoring_error_code);
6103 }
6104 }
6105
104f226b
AK		 6106 /* Record the guest's net vcpu time for enforced NMI injections. */
6107 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6108 vmx->entry_time = ktime_get();
6109
6110 /* Don't enter VMX if guest state is invalid, let the exit handler
6111 start emulation until we arrive back to a valid state */
6112 if (vmx->emulation_required && emulate_invalid_guest_state)
6113 return;
6114
6115 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6116 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6117 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6118 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6119
6120 /* When single-stepping over STI and MOV SS, we must clear the
6121 * corresponding interruptibility bits in the guest state. Otherwise
6122 * vmentry fails as it then expects bit 14 (BS) in pending debug
6123 * exceptions being set, but that's not correct for the guest debugging
6124 * case. */
6125 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6126 vmx_set_interrupt_shadow(vcpu, 0);
6127
d7cd9796
GN		 6128 atomic_switch_perf_msrs(vmx);
6129
d462b819 6130 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6131 asm(
6aa8b732 6132 /* Store host registers */
c801949d 6133 "push %%"R"dx; push %%"R"bp;"
40712fae 6134 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6135 "push %%"R"cx \n\t"
313dbd49
AK		 6136 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6137 "je 1f \n\t"
6138 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6139 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6140 "1: \n\t"
d3edefc0
AK		 6141 /* Reload cr2 if changed */
6142 "mov %c[cr2](%0), %%"R"ax \n\t"
6143 "mov %%cr2, %%"R"dx \n\t"
6144 "cmp %%"R"ax, %%"R"dx \n\t"
6145 "je 2f \n\t"
6146 "mov %%"R"ax, %%cr2 \n\t"
6147 "2: \n\t"
6aa8b732 6148 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6149 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6150 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6151 "mov %c[rax](%0), %%"R"ax \n\t"
6152 "mov %c[rbx](%0), %%"R"bx \n\t"
6153 "mov %c[rdx](%0), %%"R"dx \n\t"
6154 "mov %c[rsi](%0), %%"R"si \n\t"
6155 "mov %c[rdi](%0), %%"R"di \n\t"
6156 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6157#ifdef CONFIG_X86_64
e08aa78a
AK		 6158 "mov %c[r8](%0), %%r8 \n\t"
6159 "mov %c[r9](%0), %%r9 \n\t"
6160 "mov %c[r10](%0), %%r10 \n\t"
6161 "mov %c[r11](%0), %%r11 \n\t"
6162 "mov %c[r12](%0), %%r12 \n\t"
6163 "mov %c[r13](%0), %%r13 \n\t"
6164 "mov %c[r14](%0), %%r14 \n\t"
6165 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6166#endif
c801949d
AK		 6167 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6168
6aa8b732 6169 /* Enter guest mode */
cd2276a7 6170 "jne .Llaunched \n\t"
4ecac3fd 6171 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6172 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6173 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6174 ".Lkvm_vmx_return: "
6aa8b732 6175 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6176 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6177 "pop %0 \n\t"
c801949d
AK		 6178 "mov %%"R"ax, %c[rax](%0) \n\t"
6179 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6180 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6181 "mov %%"R"dx, %c[rdx](%0) \n\t"
6182 "mov %%"R"si, %c[rsi](%0) \n\t"
6183 "mov %%"R"di, %c[rdi](%0) \n\t"
6184 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6185#ifdef CONFIG_X86_64
e08aa78a
AK		 6186 "mov %%r8, %c[r8](%0) \n\t"
6187 "mov %%r9, %c[r9](%0) \n\t"
6188 "mov %%r10, %c[r10](%0) \n\t"
6189 "mov %%r11, %c[r11](%0) \n\t"
6190 "mov %%r12, %c[r12](%0) \n\t"
6191 "mov %%r13, %c[r13](%0) \n\t"
6192 "mov %%r14, %c[r14](%0) \n\t"
6193 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6194#endif
c801949d
AK		 6195 "mov %%cr2, %%"R"ax \n\t"
6196 "mov %%"R"ax, %c[cr2](%0) \n\t"
6197
1c696d0e 6198 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6199 "setbe %c[fail](%0) \n\t"
6200 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6201 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6202 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6203 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6204 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6205 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6206 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6207 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6208 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6209 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6210 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6211#ifdef CONFIG_X86_64
ad312c7c
ZX		 6212 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6213 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6214 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6215 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6216 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6217 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6218 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6219 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6220#endif
40712fae
AK		 6221 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6222 [wordsize]"i"(sizeof(ulong))
c2036300 6223 : "cc", "memory"
07d6f555 6224 , R"ax", R"bx", R"di", R"si"
c2036300 6225#ifdef CONFIG_X86_64
c2036300
LV		 6226 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6227#endif
6228 );
6aa8b732 6229
6de4f3ad 6230 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6231 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6232 | (1 << VCPU_EXREG_CPL)
aff48baa 6233 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6234 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6235 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6236 vcpu->arch.regs_dirty = 0;
6237
1155f76a
AK		 6238 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6239
66c78ae4
NHE		 6240 if (is_guest_mode(vcpu)) {
6241 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6242 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6243 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6244 vmcs12->idt_vectoring_error_code =
6245 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6246 vmcs12->vm_exit_instruction_len =
6247 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6248 }
6249 }
6250
d77c26fc 6251 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6252 vmx->loaded_vmcs->launched = 1;
1b6269db 6253
51aa01d1 6254 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6255 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6256
6257 vmx_complete_atomic_exit(vmx);
6258 vmx_recover_nmi_blocking(vmx);
cf393f75 6259 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6260}
6261
c801949d
AK		 6262#undef R
6263#undef Q
6264
6aa8b732
AK		 6265static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6266{
fb3f0f51
RR		 6267 struct vcpu_vmx *vmx = to_vmx(vcpu);
6268
cdbecfc3 6269 free_vpid(vmx);
ec378aee 6270 free_nested(vmx);
d462b819 6271 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6272 kfree(vmx->guest_msrs);
6273 kvm_vcpu_uninit(vcpu);
a4770347 6274 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6275}
6276
fb3f0f51 6277static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6278{
fb3f0f51 6279 int err;
c16f862d 6280 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6281 int cpu;
6aa8b732 6282
a2fa3e9f 6283 if (!vmx)
fb3f0f51
RR		 6284 return ERR_PTR(-ENOMEM);
6285
2384d2b3
SY		 6286 allocate_vpid(vmx);
6287
fb3f0f51
RR		 6288 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6289 if (err)
6290 goto free_vcpu;
965b58a5 6291
a2fa3e9f 6292 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6293 err = -ENOMEM;
fb3f0f51 6294 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6295 goto uninit_vcpu;
6296 }
965b58a5 6297
d462b819
NHE		 6298 vmx->loaded_vmcs = &vmx->vmcs01;
6299 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6300 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6301 goto free_msrs;
d462b819
NHE		 6302 if (!vmm_exclusive)
6303 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6304 loaded_vmcs_init(vmx->loaded_vmcs);
6305 if (!vmm_exclusive)
6306 kvm_cpu_vmxoff();
a2fa3e9f 6307
15ad7146
AK		 6308 cpu = get_cpu();
6309 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6310 vmx->vcpu.cpu = cpu;
8b9cf98c 6311 err = vmx_vcpu_setup(vmx);
fb3f0f51 6312 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6313 put_cpu();
fb3f0f51
RR		 6314 if (err)
6315 goto free_vmcs;
5e4a0b3c 6316 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6317 err = alloc_apic_access_page(kvm);
6318 if (err)
5e4a0b3c 6319 goto free_vmcs;
fb3f0f51 6320
b927a3ce
SY		 6321 if (enable_ept) {
6322 if (!kvm->arch.ept_identity_map_addr)
6323 kvm->arch.ept_identity_map_addr =
6324 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6325 err = -ENOMEM;
b7ebfb05
SY		 6326 if (alloc_identity_pagetable(kvm) != 0)
6327 goto free_vmcs;
93ea5388
GN		 6328 if (!init_rmode_identity_map(kvm))
6329 goto free_vmcs;
b927a3ce 6330 }
b7ebfb05 6331
a9d30f33
NHE		 6332 vmx->nested.current_vmptr = -1ull;
6333 vmx->nested.current_vmcs12 = NULL;
6334
fb3f0f51
RR		 6335 return &vmx->vcpu;
6336
6337free_vmcs:
d462b819 6338 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6339free_msrs:
fb3f0f51
RR		 6340 kfree(vmx->guest_msrs);
6341uninit_vcpu:
6342 kvm_vcpu_uninit(&vmx->vcpu);
6343free_vcpu:
cdbecfc3 6344 free_vpid(vmx);
a4770347 6345 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6346 return ERR_PTR(err);
6aa8b732
AK		 6347}
6348
002c7f7c
YS		 6349static void __init vmx_check_processor_compat(void *rtn)
6350{
6351 struct vmcs_config vmcs_conf;
6352
6353 *(int *)rtn = 0;
6354 if (setup_vmcs_config(&vmcs_conf) < 0)
6355 *(int *)rtn = -EIO;
6356 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6357 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6358 smp_processor_id());
6359 *(int *)rtn = -EIO;
6360 }
6361}
6362
67253af5
SY		 6363static int get_ept_level(void)
6364{
6365 return VMX_EPT_DEFAULT_GAW + 1;
6366}
6367
4b12f0de 6368static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6369{
4b12f0de
SY		 6370 u64 ret;
6371
522c68c4
SY		 6372 /* For VT-d and EPT combination
6373 * 1. MMIO: always map as UC
6374 * 2. EPT with VT-d:
6375 * a. VT-d without snooping control feature: can't guarantee the
6376 * result, try to trust guest.
6377 * b. VT-d with snooping control feature: snooping control feature of
6378 * VT-d engine can guarantee the cache correctness. Just set it
6379 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6380 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6381 * consistent with host MTRR
6382 */
4b12f0de
SY		 6383 if (is_mmio)
6384 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6385 else if (vcpu->kvm->arch.iommu_domain &&
6386 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6387 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6388 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6389 else
522c68c4 6390 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6391 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6392
6393 return ret;
64d4d521
SY		 6394}
6395
17cc3935 6396static int vmx_get_lpage_level(void)
344f414f 6397{
878403b7
SY		 6398 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6399 return PT_DIRECTORY_LEVEL;
6400 else
6401 /* For shadow and EPT supported 1GB page */
6402 return PT_PDPE_LEVEL;
344f414f
JR		 6403}
6404
0e851880
SY		 6405static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6406{
4e47c7a6
SY		 6407 struct kvm_cpuid_entry2 *best;
6408 struct vcpu_vmx *vmx = to_vmx(vcpu);
6409 u32 exec_control;
6410
6411 vmx->rdtscp_enabled = false;
6412 if (vmx_rdtscp_supported()) {
6413 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6414 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6415 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6416 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6417 vmx->rdtscp_enabled = true;
6418 else {
6419 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6420 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6421 exec_control);
6422 }
6423 }
6424 }
0e851880
SY		 6425}
6426
d4330ef2
JR		 6427static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6428{
7b8050f5
NHE		 6429 if (func == 1 && nested)
6430 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6431}
6432
fe3ef05c
NHE		 6433/*
6434 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6435 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6436 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6437 * guest in a way that will both be appropriate to L1's requests, and our
6438 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6439 * function also has additional necessary side-effects, like setting various
6440 * vcpu->arch fields.
6441 */
6442static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6443{
6444 struct vcpu_vmx *vmx = to_vmx(vcpu);
6445 u32 exec_control;
6446
6447 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6448 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6449 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6450 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6451 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6452 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6453 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6454 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6455 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6456 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6457 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6458 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6459 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6460 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6461 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6462 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6463 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6464 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6465 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6466 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6467 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6468 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6469 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6470 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6471 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6472 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6473 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6474 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6475 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6476 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6477 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6478 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6479 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6480 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6481 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6482 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6483
6484 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6485 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6486 vmcs12->vm_entry_intr_info_field);
6487 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6488 vmcs12->vm_entry_exception_error_code);
6489 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6490 vmcs12->vm_entry_instruction_len);
6491 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6492 vmcs12->guest_interruptibility_info);
6493 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6494 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6495 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6496 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6497 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6498 vmcs12->guest_pending_dbg_exceptions);
6499 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6500 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6501
6502 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6503
6504 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6505 (vmcs_config.pin_based_exec_ctrl |
6506 vmcs12->pin_based_vm_exec_control));
6507
6508 /*
6509 * Whether page-faults are trapped is determined by a combination of
6510 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6511 * If enable_ept, L0 doesn't care about page faults and we should
6512 * set all of these to L1's desires. However, if !enable_ept, L0 does
6513 * care about (at least some) page faults, and because it is not easy
6514 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6515 * to exit on each and every L2 page fault. This is done by setting
6516 * MASK=MATCH=0 and (see below) EB.PF=1.
6517 * Note that below we don't need special code to set EB.PF beyond the
6518 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6519 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6520 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6521 *
6522 * A problem with this approach (when !enable_ept) is that L1 may be
6523 * injected with more page faults than it asked for. This could have
6524 * caused problems, but in practice existing hypervisors don't care.
6525 * To fix this, we will need to emulate the PFEC checking (on the L1
6526 * page tables), using walk_addr(), when injecting PFs to L1.
6527 */
6528 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6529 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6530 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6531 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6532
6533 if (cpu_has_secondary_exec_ctrls()) {
6534 u32 exec_control = vmx_secondary_exec_control(vmx);
6535 if (!vmx->rdtscp_enabled)
6536 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6537 /* Take the following fields only from vmcs12 */
6538 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6539 if (nested_cpu_has(vmcs12,
6540 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6541 exec_control |= vmcs12->secondary_vm_exec_control;
6542
6543 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6544 /*
6545 * Translate L1 physical address to host physical
6546 * address for vmcs02. Keep the page pinned, so this
6547 * physical address remains valid. We keep a reference
6548 * to it so we can release it later.
6549 */
6550 if (vmx->nested.apic_access_page) /* shouldn't happen */
6551 nested_release_page(vmx->nested.apic_access_page);
6552 vmx->nested.apic_access_page =
6553 nested_get_page(vcpu, vmcs12->apic_access_addr);
6554 /*
6555 * If translation failed, no matter: This feature asks
6556 * to exit when accessing the given address, and if it
6557 * can never be accessed, this feature won't do
6558 * anything anyway.
6559 */
6560 if (!vmx->nested.apic_access_page)
6561 exec_control &=
6562 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6563 else
6564 vmcs_write64(APIC_ACCESS_ADDR,
6565 page_to_phys(vmx->nested.apic_access_page));
6566 }
6567
6568 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6569 }
6570
6571
6572 /*
6573 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6574 * Some constant fields are set here by vmx_set_constant_host_state().
6575 * Other fields are different per CPU, and will be set later when
6576 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6577 */
6578 vmx_set_constant_host_state();
6579
6580 /*
6581 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6582 * entry, but only if the current (host) sp changed from the value
6583 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6584 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6585 * here we just force the write to happen on entry.
6586 */
6587 vmx->host_rsp = 0;
6588
6589 exec_control = vmx_exec_control(vmx); /* L0's desires */
6590 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6591 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6592 exec_control &= ~CPU_BASED_TPR_SHADOW;
6593 exec_control |= vmcs12->cpu_based_vm_exec_control;
6594 /*
6595 * Merging of IO and MSR bitmaps not currently supported.
6596 * Rather, exit every time.
6597 */
6598 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6599 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6600 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6601
6602 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6603
6604 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6605 * bitwise-or of what L1 wants to trap for L2, and what we want to
6606 * trap. Note that CR0.TS also needs updating - we do this later.
6607 */
6608 update_exception_bitmap(vcpu);
6609 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6610 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6611
6612 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6613 vmcs_write32(VM_EXIT_CONTROLS,
6614 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6615 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6616 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6617
6618 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6619 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6620 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6621 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6622
6623
6624 set_cr4_guest_host_mask(vmx);
6625
27fc51b2
NHE		 6626 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6627 vmcs_write64(TSC_OFFSET,
6628 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6629 else
6630 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6631
6632 if (enable_vpid) {
6633 /*
6634 * Trivially support vpid by letting L2s share their parent
6635 * L1's vpid. TODO: move to a more elaborate solution, giving
6636 * each L2 its own vpid and exposing the vpid feature to L1.
6637 */
6638 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6639 vmx_flush_tlb(vcpu);
6640 }
6641
6642 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6643 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6644 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6645 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6646 else
6647 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6648 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6649 vmx_set_efer(vcpu, vcpu->arch.efer);
6650
6651 /*
6652 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6653 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6654 * The CR0_READ_SHADOW is what L2 should have expected to read given
6655 * the specifications by L1; It's not enough to take
6656 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6657 * have more bits than L1 expected.
6658 */
6659 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6660 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6661
6662 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6663 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6664
6665 /* shadow page tables on either EPT or shadow page tables */
6666 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6667 kvm_mmu_reset_context(vcpu);
6668
6669 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6670 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6671}
6672
cd232ad0
NHE		 6673/*
6674 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6675 * for running an L2 nested guest.
6676 */
6677static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6678{
6679 struct vmcs12 *vmcs12;
6680 struct vcpu_vmx *vmx = to_vmx(vcpu);
6681 int cpu;
6682 struct loaded_vmcs *vmcs02;
6683
6684 if (!nested_vmx_check_permission(vcpu) ||
6685 !nested_vmx_check_vmcs12(vcpu))
6686 return 1;
6687
6688 skip_emulated_instruction(vcpu);
6689 vmcs12 = get_vmcs12(vcpu);
6690
7c177938
NHE		 6691 /*
6692 * The nested entry process starts with enforcing various prerequisites
6693 * on vmcs12 as required by the Intel SDM, and act appropriately when
6694 * they fail: As the SDM explains, some conditions should cause the
6695 * instruction to fail, while others will cause the instruction to seem
6696 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6697 * To speed up the normal (success) code path, we should avoid checking
6698 * for misconfigurations which will anyway be caught by the processor
6699 * when using the merged vmcs02.
6700 */
6701 if (vmcs12->launch_state == launch) {
6702 nested_vmx_failValid(vcpu,
6703 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6704 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6705 return 1;
6706 }
6707
6708 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6709 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6710 /*TODO: Also verify bits beyond physical address width are 0*/
6711 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6712 return 1;
6713 }
6714
6715 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6716 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6717 /*TODO: Also verify bits beyond physical address width are 0*/
6718 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6719 return 1;
6720 }
6721
6722 if (vmcs12->vm_entry_msr_load_count > 0 ||
6723 vmcs12->vm_exit_msr_load_count > 0 ||
6724 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6725 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6726 __func__);
7c177938
NHE		 6727 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6728 return 1;
6729 }
6730
6731 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6732 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6733 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6734 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6735 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6736 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6737 !vmx_control_verify(vmcs12->vm_exit_controls,
6738 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6739 !vmx_control_verify(vmcs12->vm_entry_controls,
6740 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6741 {
6742 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6743 return 1;
6744 }
6745
6746 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6747 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6748 nested_vmx_failValid(vcpu,
6749 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6750 return 1;
6751 }
6752
6753 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6754 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6755 nested_vmx_entry_failure(vcpu, vmcs12,
6756 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6757 return 1;
6758 }
6759 if (vmcs12->vmcs_link_pointer != -1ull) {
6760 nested_vmx_entry_failure(vcpu, vmcs12,
6761 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6762 return 1;
6763 }
6764
6765 /*
6766 * We're finally done with prerequisite checking, and can start with
6767 * the nested entry.
6768 */
6769
cd232ad0
NHE		 6770 vmcs02 = nested_get_current_vmcs02(vmx);
6771 if (!vmcs02)
6772 return -ENOMEM;
6773
6774 enter_guest_mode(vcpu);
6775
6776 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6777
6778 cpu = get_cpu();
6779 vmx->loaded_vmcs = vmcs02;
6780 vmx_vcpu_put(vcpu);
6781 vmx_vcpu_load(vcpu, cpu);
6782 vcpu->cpu = cpu;
6783 put_cpu();
6784
6785 vmcs12->launch_state = 1;
6786
6787 prepare_vmcs02(vcpu, vmcs12);
6788
6789 /*
6790 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6791 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6792 * returned as far as L1 is concerned. It will only return (and set
6793 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6794 */
6795 return 1;
6796}
6797
4704d0be
NHE		 6798/*
6799 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6800 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6801 * This function returns the new value we should put in vmcs12.guest_cr0.
6802 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6803 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6804 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6805 * didn't trap the bit, because if L1 did, so would L0).
6806 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6807 * been modified by L2, and L1 knows it. So just leave the old value of
6808 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6809 * isn't relevant, because if L0 traps this bit it can set it to anything.
6810 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6811 * changed these bits, and therefore they need to be updated, but L0
6812 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6813 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6814 */
6815static inline unsigned long
6816vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6817{
6818 return
6819 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6820 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6821 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6822 vcpu->arch.cr0_guest_owned_bits));
6823}
6824
6825static inline unsigned long
6826vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6827{
6828 return
6829 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6830 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6831 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6832 vcpu->arch.cr4_guest_owned_bits));
6833}
6834
6835/*
6836 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6837 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6838 * and this function updates it to reflect the changes to the guest state while
6839 * L2 was running (and perhaps made some exits which were handled directly by L0
6840 * without going back to L1), and to reflect the exit reason.
6841 * Note that we do not have to copy here all VMCS fields, just those that
6842 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6843 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6844 * which already writes to vmcs12 directly.
6845 */
6846void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6847{
6848 /* update guest state fields: */
6849 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6850 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6851
6852 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6853 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6854 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6855 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6856
6857 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6858 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6859 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6860 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6861 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6862 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6863 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6864 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6865 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6866 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6867 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6868 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6869 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6870 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6871 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6872 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6873 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6874 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6875 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6876 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6877 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6878 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6879 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6880 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6881 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6882 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6883 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6884 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6885 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6886 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6887 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6888 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6889 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6890 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6891 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6892 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6893
6894 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6895 vmcs12->guest_interruptibility_info =
6896 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6897 vmcs12->guest_pending_dbg_exceptions =
6898 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6899
6900 /* TODO: These cannot have changed unless we have MSR bitmaps and
6901 * the relevant bit asks not to trap the change */
6902 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6903 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6904 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6905 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6906 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6907 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6908
6909 /* update exit information fields: */
6910
6911 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6912 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6913
6914 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6915 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6916 vmcs12->idt_vectoring_info_field =
6917 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6918 vmcs12->idt_vectoring_error_code =
6919 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6920 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6921 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6922
6923 /* clear vm-entry fields which are to be cleared on exit */
6924 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6925 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6926}
6927
6928/*
6929 * A part of what we need to when the nested L2 guest exits and we want to
6930 * run its L1 parent, is to reset L1's guest state to the host state specified
6931 * in vmcs12.
6932 * This function is to be called not only on normal nested exit, but also on
6933 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6934 * Failures During or After Loading Guest State").
6935 * This function should be called when the active VMCS is L1's (vmcs01).
6936 */
6937void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6938{
6939 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6940 vcpu->arch.efer = vmcs12->host_ia32_efer;
6941 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6942 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6943 else
6944 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6945 vmx_set_efer(vcpu, vcpu->arch.efer);
6946
6947 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6948 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6949 /*
6950 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6951 * actually changed, because it depends on the current state of
6952 * fpu_active (which may have changed).
6953 * Note that vmx_set_cr0 refers to efer set above.
6954 */
6955 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6956 /*
6957 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6958 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6959 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6960 */
6961 update_exception_bitmap(vcpu);
6962 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6963 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6964
6965 /*
6966 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6967 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6968 */
6969 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6970 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6971
6972 /* shadow page tables on either EPT or shadow page tables */
6973 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6974 kvm_mmu_reset_context(vcpu);
6975
6976 if (enable_vpid) {
6977 /*
6978 * Trivially support vpid by letting L2s share their parent
6979 * L1's vpid. TODO: move to a more elaborate solution, giving
6980 * each L2 its own vpid and exposing the vpid feature to L1.
6981 */
6982 vmx_flush_tlb(vcpu);
6983 }
6984
6985
6986 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6987 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6988 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6989 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6990 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6991 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6992 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6993 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6994 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6995 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6996 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6997 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6998 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6999 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7000 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7001
7002 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7003 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7004 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7005 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7006 vmcs12->host_ia32_perf_global_ctrl);
7007}
7008
7009/*
7010 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7011 * and modify vmcs12 to make it see what it would expect to see there if
7012 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7013 */
7014static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7015{
7016 struct vcpu_vmx *vmx = to_vmx(vcpu);
7017 int cpu;
7018 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7019
7020 leave_guest_mode(vcpu);
7021 prepare_vmcs12(vcpu, vmcs12);
7022
7023 cpu = get_cpu();
7024 vmx->loaded_vmcs = &vmx->vmcs01;
7025 vmx_vcpu_put(vcpu);
7026 vmx_vcpu_load(vcpu, cpu);
7027 vcpu->cpu = cpu;
7028 put_cpu();
7029
7030 /* if no vmcs02 cache requested, remove the one we used */
7031 if (VMCS02_POOL_SIZE == 0)
7032 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7033
7034 load_vmcs12_host_state(vcpu, vmcs12);
7035
27fc51b2 7036 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7037 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7038
7039 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7040 vmx->host_rsp = 0;
7041
7042 /* Unpin physical memory we referred to in vmcs02 */
7043 if (vmx->nested.apic_access_page) {
7044 nested_release_page(vmx->nested.apic_access_page);
7045 vmx->nested.apic_access_page = 0;
7046 }
7047
7048 /*
7049 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7050 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7051 * success or failure flag accordingly.
7052 */
7053 if (unlikely(vmx->fail)) {
7054 vmx->fail = 0;
7055 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7056 } else
7057 nested_vmx_succeed(vcpu);
7058}
7059
7c177938
NHE		 7060/*
7061 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7062 * 23.7 "VM-entry failures during or after loading guest state" (this also
7063 * lists the acceptable exit-reason and exit-qualification parameters).
7064 * It should only be called before L2 actually succeeded to run, and when
7065 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7066 */
7067static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7068 struct vmcs12 *vmcs12,
7069 u32 reason, unsigned long qualification)
7070{
7071 load_vmcs12_host_state(vcpu, vmcs12);
7072 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7073 vmcs12->exit_qualification = qualification;
7074 nested_vmx_succeed(vcpu);
7075}
7076
8a76d7f2
JR		 7077static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7078 struct x86_instruction_info *info,
7079 enum x86_intercept_stage stage)
7080{
7081 return X86EMUL_CONTINUE;
7082}
7083
cbdd1bea 7084static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7085 .cpu_has_kvm_support = cpu_has_kvm_support,
7086 .disabled_by_bios = vmx_disabled_by_bios,
7087 .hardware_setup = hardware_setup,
7088 .hardware_unsetup = hardware_unsetup,
002c7f7c 7089 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7090 .hardware_enable = hardware_enable,
7091 .hardware_disable = hardware_disable,
04547156 7092 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7093
7094 .vcpu_create = vmx_create_vcpu,
7095 .vcpu_free = vmx_free_vcpu,
04d2cc77 7096 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7097
04d2cc77 7098 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7099 .vcpu_load = vmx_vcpu_load,
7100 .vcpu_put = vmx_vcpu_put,
7101
7102 .set_guest_debug = set_guest_debug,
7103 .get_msr = vmx_get_msr,
7104 .set_msr = vmx_set_msr,
7105 .get_segment_base = vmx_get_segment_base,
7106 .get_segment = vmx_get_segment,
7107 .set_segment = vmx_set_segment,
2e4d2653 7108 .get_cpl = vmx_get_cpl,
6aa8b732 7109 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7110 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7111 .decache_cr3 = vmx_decache_cr3,
25c4c276 7112 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7113 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7114 .set_cr3 = vmx_set_cr3,
7115 .set_cr4 = vmx_set_cr4,
6aa8b732 7116 .set_efer = vmx_set_efer,
6aa8b732
AK		 7117 .get_idt = vmx_get_idt,
7118 .set_idt = vmx_set_idt,
7119 .get_gdt = vmx_get_gdt,
7120 .set_gdt = vmx_set_gdt,
020df079 7121 .set_dr7 = vmx_set_dr7,
5fdbf976 7122 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7123 .get_rflags = vmx_get_rflags,
7124 .set_rflags = vmx_set_rflags,
ebcbab4c 7125 .fpu_activate = vmx_fpu_activate,
02daab21 7126 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7127
7128 .tlb_flush = vmx_flush_tlb,
6aa8b732 7129
6aa8b732 7130 .run = vmx_vcpu_run,
6062d012 7131 .handle_exit = vmx_handle_exit,
6aa8b732 7132 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7133 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7134 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7135 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7136 .set_irq = vmx_inject_irq,
95ba8273 7137 .set_nmi = vmx_inject_nmi,
298101da 7138 .queue_exception = vmx_queue_exception,
b463a6f7 7139 .cancel_injection = vmx_cancel_injection,
78646121 7140 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7141 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7142 .get_nmi_mask = vmx_get_nmi_mask,
7143 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7144 .enable_nmi_window = enable_nmi_window,
7145 .enable_irq_window = enable_irq_window,
7146 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7147
cbc94022 7148 .set_tss_addr = vmx_set_tss_addr,
67253af5 7149 .get_tdp_level = get_ept_level,
4b12f0de 7150 .get_mt_mask = vmx_get_mt_mask,
229456fc 7151
586f9607 7152 .get_exit_info = vmx_get_exit_info,
586f9607 7153
17cc3935 7154 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7155
7156 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7157
7158 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7159
7160 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7161
7162 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7163
4051b188 7164 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7165 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7166 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7167 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7168 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7169
7170 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7171
7172 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7173};
7174
7175static int __init vmx_init(void)
7176{
26bb0981
AK		 7177 int r, i;
7178
7179 rdmsrl_safe(MSR_EFER, &host_efer);
7180
7181 for (i = 0; i < NR_VMX_MSR; ++i)
7182 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7183
3e7c73e9 7184 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7185 if (!vmx_io_bitmap_a)
7186 return -ENOMEM;
7187
3e7c73e9 7188 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7189 if (!vmx_io_bitmap_b) {
7190 r = -ENOMEM;
7191 goto out;
7192 }
7193
5897297b
AK		 7194 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7195 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7196 r = -ENOMEM;
7197 goto out1;
7198 }
7199
5897297b
AK		 7200 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7201 if (!vmx_msr_bitmap_longmode) {
7202 r = -ENOMEM;
7203 goto out2;
7204 }
7205
fdef3ad1
HQ		 7206 /*
7207 * Allow direct access to the PC debug port (it is often used for I/O
7208 * delays, but the vmexits simply slow things down).
7209 */
3e7c73e9
AK		 7210 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7211 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7212
3e7c73e9 7213 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7214
5897297b
AK		 7215 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7216 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7217
2384d2b3
SY		 7218 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7219
0ee75bea
AK		 7220 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7221 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7222 if (r)
5897297b 7223 goto out3;
25c5f225 7224
5897297b
AK		 7225 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7226 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7227 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7228 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7229 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7230 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7231
089d034e 7232 if (enable_ept) {
534e38b4 7233 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7234 VMX_EPT_EXECUTABLE_MASK);
ce88decf 7235 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7236 kvm_enable_tdp();
7237 } else
7238 kvm_disable_tdp();
1439442c 7239
fdef3ad1
HQ		 7240 return 0;
7241
5897297b
AK		 7242out3:
7243 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7244out2:
5897297b 7245 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7246out1:
3e7c73e9 7247 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7248out:
3e7c73e9 7249 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7250 return r;
6aa8b732
AK		 7251}
7252
7253static void __exit vmx_exit(void)
7254{
5897297b
AK		 7255 free_page((unsigned long)vmx_msr_bitmap_legacy);
7256 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7257 free_page((unsigned long)vmx_io_bitmap_b);
7258 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7259
cb498ea2 7260 kvm_exit();
6aa8b732
AK		 7261}
7262
7263module_init(vmx_init)
7264module_exit(vmx_exit)
Linux kernel - Deliverables
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