[deliverable/linux.git] / arch / x86 / kvm / vmx.h

#ifndef VMX_H
#define VMX_H

/*
 * vmx.h: VMX Architecture related definitions
 * Copyright (c) 2004, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 * A few random additions are:
 * Copyright (C) 2006 Qumranet
 *    Avi Kivity <avi@qumranet.com>
 *    Yaniv Kamay <yaniv@qumranet.com>
 *
 */

/*
 * Definitions of Primary Processor-Based VM-Execution Controls.
 */
#define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
#define CPU_BASED_USE_TSC_OFFSETING             0x00000008
#define CPU_BASED_HLT_EXITING                   0x00000080
#define CPU_BASED_INVLPG_EXITING                0x00000200
#define CPU_BASED_MWAIT_EXITING                 0x00000400
#define CPU_BASED_RDPMC_EXITING                 0x00000800
#define CPU_BASED_RDTSC_EXITING                 0x00001000
#define CPU_BASED_CR3_LOAD_EXITING		0x00008000
#define CPU_BASED_CR3_STORE_EXITING		0x00010000
#define CPU_BASED_CR8_LOAD_EXITING              0x00080000
#define CPU_BASED_CR8_STORE_EXITING             0x00100000
#define CPU_BASED_TPR_SHADOW                    0x00200000
#define CPU_BASED_VIRTUAL_NMI_PENDING		0x00400000
#define CPU_BASED_MOV_DR_EXITING                0x00800000
#define CPU_BASED_UNCOND_IO_EXITING             0x01000000
#define CPU_BASED_USE_IO_BITMAPS                0x02000000
#define CPU_BASED_USE_MSR_BITMAPS               0x10000000
#define CPU_BASED_MONITOR_EXITING               0x20000000
#define CPU_BASED_PAUSE_EXITING                 0x40000000
#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
/*
 * Definitions of Secondary Processor-Based VM-Execution Controls.
 */
#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
#define SECONDARY_EXEC_ENABLE_EPT               0x00000002
#define SECONDARY_EXEC_ENABLE_VPID              0x00000020
#define SECONDARY_EXEC_WBINVD_EXITING		0x00000040


#define PIN_BASED_EXT_INTR_MASK                 0x00000001
#define PIN_BASED_NMI_EXITING                   0x00000008
#define PIN_BASED_VIRTUAL_NMIS                  0x00000020

#define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
#define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000

#define VM_ENTRY_IA32E_MODE                     0x00000200
#define VM_ENTRY_SMM                            0x00000400
#define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800

/* VMCS Encodings */
enum vmcs_field {
	VIRTUAL_PROCESSOR_ID            = 0x00000000,
	GUEST_ES_SELECTOR               = 0x00000800,
	GUEST_CS_SELECTOR               = 0x00000802,
	GUEST_SS_SELECTOR               = 0x00000804,
	GUEST_DS_SELECTOR               = 0x00000806,
	GUEST_FS_SELECTOR               = 0x00000808,
	GUEST_GS_SELECTOR               = 0x0000080a,
	GUEST_LDTR_SELECTOR             = 0x0000080c,
	GUEST_TR_SELECTOR               = 0x0000080e,
	HOST_ES_SELECTOR                = 0x00000c00,
	HOST_CS_SELECTOR                = 0x00000c02,
	HOST_SS_SELECTOR                = 0x00000c04,
	HOST_DS_SELECTOR                = 0x00000c06,
	HOST_FS_SELECTOR                = 0x00000c08,
	HOST_GS_SELECTOR                = 0x00000c0a,
	HOST_TR_SELECTOR                = 0x00000c0c,
	IO_BITMAP_A                     = 0x00002000,
	IO_BITMAP_A_HIGH                = 0x00002001,
	IO_BITMAP_B                     = 0x00002002,
	IO_BITMAP_B_HIGH                = 0x00002003,
	MSR_BITMAP                      = 0x00002004,
	MSR_BITMAP_HIGH                 = 0x00002005,
	VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
	VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
	VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
	VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
	VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
	VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
	TSC_OFFSET                      = 0x00002010,
	TSC_OFFSET_HIGH                 = 0x00002011,
	VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
	VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
	APIC_ACCESS_ADDR		= 0x00002014,
	APIC_ACCESS_ADDR_HIGH		= 0x00002015,
	EPT_POINTER                     = 0x0000201a,
	EPT_POINTER_HIGH                = 0x0000201b,
	GUEST_PHYSICAL_ADDRESS          = 0x00002400,
	GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
	VMCS_LINK_POINTER               = 0x00002800,
	VMCS_LINK_POINTER_HIGH          = 0x00002801,
	GUEST_IA32_DEBUGCTL             = 0x00002802,
	GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
	GUEST_PDPTR0                    = 0x0000280a,
	GUEST_PDPTR0_HIGH               = 0x0000280b,
	GUEST_PDPTR1                    = 0x0000280c,
	GUEST_PDPTR1_HIGH               = 0x0000280d,
	GUEST_PDPTR2                    = 0x0000280e,
	GUEST_PDPTR2_HIGH               = 0x0000280f,
	GUEST_PDPTR3                    = 0x00002810,
	GUEST_PDPTR3_HIGH               = 0x00002811,
	PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
	CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
	EXCEPTION_BITMAP                = 0x00004004,
	PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
	PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
	CR3_TARGET_COUNT                = 0x0000400a,
	VM_EXIT_CONTROLS                = 0x0000400c,
	VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
	VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
	VM_ENTRY_CONTROLS               = 0x00004012,
	VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
	VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
	VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
	VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
	TPR_THRESHOLD                   = 0x0000401c,
	SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
	VM_INSTRUCTION_ERROR            = 0x00004400,
	VM_EXIT_REASON                  = 0x00004402,
	VM_EXIT_INTR_INFO               = 0x00004404,
	VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
	IDT_VECTORING_INFO_FIELD        = 0x00004408,
	IDT_VECTORING_ERROR_CODE        = 0x0000440a,
	VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
	VMX_INSTRUCTION_INFO            = 0x0000440e,
	GUEST_ES_LIMIT                  = 0x00004800,
	GUEST_CS_LIMIT                  = 0x00004802,
	GUEST_SS_LIMIT                  = 0x00004804,
	GUEST_DS_LIMIT                  = 0x00004806,
	GUEST_FS_LIMIT                  = 0x00004808,
	GUEST_GS_LIMIT                  = 0x0000480a,
	GUEST_LDTR_LIMIT                = 0x0000480c,
	GUEST_TR_LIMIT                  = 0x0000480e,
	GUEST_GDTR_LIMIT                = 0x00004810,
	GUEST_IDTR_LIMIT                = 0x00004812,
	GUEST_ES_AR_BYTES               = 0x00004814,
	GUEST_CS_AR_BYTES               = 0x00004816,
	GUEST_SS_AR_BYTES               = 0x00004818,
	GUEST_DS_AR_BYTES               = 0x0000481a,
	GUEST_FS_AR_BYTES               = 0x0000481c,
	GUEST_GS_AR_BYTES               = 0x0000481e,
	GUEST_LDTR_AR_BYTES             = 0x00004820,
	GUEST_TR_AR_BYTES               = 0x00004822,
	GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
	GUEST_ACTIVITY_STATE            = 0X00004826,
	GUEST_SYSENTER_CS               = 0x0000482A,
	HOST_IA32_SYSENTER_CS           = 0x00004c00,
	CR0_GUEST_HOST_MASK             = 0x00006000,
	CR4_GUEST_HOST_MASK             = 0x00006002,
	CR0_READ_SHADOW                 = 0x00006004,
	CR4_READ_SHADOW                 = 0x00006006,
	CR3_TARGET_VALUE0               = 0x00006008,
	CR3_TARGET_VALUE1               = 0x0000600a,
	CR3_TARGET_VALUE2               = 0x0000600c,
	CR3_TARGET_VALUE3               = 0x0000600e,
	EXIT_QUALIFICATION              = 0x00006400,
	GUEST_LINEAR_ADDRESS            = 0x0000640a,
	GUEST_CR0                       = 0x00006800,
	GUEST_CR3                       = 0x00006802,
	GUEST_CR4                       = 0x00006804,
	GUEST_ES_BASE                   = 0x00006806,
	GUEST_CS_BASE                   = 0x00006808,
	GUEST_SS_BASE                   = 0x0000680a,
	GUEST_DS_BASE                   = 0x0000680c,
	GUEST_FS_BASE                   = 0x0000680e,
	GUEST_GS_BASE                   = 0x00006810,
	GUEST_LDTR_BASE                 = 0x00006812,
	GUEST_TR_BASE                   = 0x00006814,
	GUEST_GDTR_BASE                 = 0x00006816,
	GUEST_IDTR_BASE                 = 0x00006818,
	GUEST_DR7                       = 0x0000681a,
	GUEST_RSP                       = 0x0000681c,
	GUEST_RIP                       = 0x0000681e,
	GUEST_RFLAGS                    = 0x00006820,
	GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
	GUEST_SYSENTER_ESP              = 0x00006824,
	GUEST_SYSENTER_EIP              = 0x00006826,
	HOST_CR0                        = 0x00006c00,
	HOST_CR3                        = 0x00006c02,
	HOST_CR4                        = 0x00006c04,
	HOST_FS_BASE                    = 0x00006c06,
	HOST_GS_BASE                    = 0x00006c08,
	HOST_TR_BASE                    = 0x00006c0a,
	HOST_GDTR_BASE                  = 0x00006c0c,
	HOST_IDTR_BASE                  = 0x00006c0e,
	HOST_IA32_SYSENTER_ESP          = 0x00006c10,
	HOST_IA32_SYSENTER_EIP          = 0x00006c12,
	HOST_RSP                        = 0x00006c14,
	HOST_RIP                        = 0x00006c16,
};

#define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000

#define EXIT_REASON_EXCEPTION_NMI       0
#define EXIT_REASON_EXTERNAL_INTERRUPT  1
#define EXIT_REASON_TRIPLE_FAULT        2

#define EXIT_REASON_PENDING_INTERRUPT   7
#define EXIT_REASON_NMI_WINDOW		8
#define EXIT_REASON_TASK_SWITCH         9
#define EXIT_REASON_CPUID               10
#define EXIT_REASON_HLT                 12
#define EXIT_REASON_INVLPG              14
#define EXIT_REASON_RDPMC               15
#define EXIT_REASON_RDTSC               16
#define EXIT_REASON_VMCALL              18
#define EXIT_REASON_VMCLEAR             19
#define EXIT_REASON_VMLAUNCH            20
#define EXIT_REASON_VMPTRLD             21
#define EXIT_REASON_VMPTRST             22
#define EXIT_REASON_VMREAD              23
#define EXIT_REASON_VMRESUME            24
#define EXIT_REASON_VMWRITE             25
#define EXIT_REASON_VMOFF               26
#define EXIT_REASON_VMON                27
#define EXIT_REASON_CR_ACCESS           28
#define EXIT_REASON_DR_ACCESS           29
#define EXIT_REASON_IO_INSTRUCTION      30
#define EXIT_REASON_MSR_READ            31
#define EXIT_REASON_MSR_WRITE           32
#define EXIT_REASON_MWAIT_INSTRUCTION   36
#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
#define EXIT_REASON_APIC_ACCESS         44
#define EXIT_REASON_EPT_VIOLATION       48
#define EXIT_REASON_EPT_MISCONFIG       49
#define EXIT_REASON_WBINVD		54

/*
 * Interruption-information format
 */
#define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
#define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
#define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
#define INTR_INFO_UNBLOCK_NMI		0x1000		/* 12 */
#define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
#define INTR_INFO_RESVD_BITS_MASK       0x7ffff000

#define VECTORING_INFO_VECTOR_MASK           	INTR_INFO_VECTOR_MASK
#define VECTORING_INFO_TYPE_MASK        	INTR_INFO_INTR_TYPE_MASK
#define VECTORING_INFO_DELIVER_CODE_MASK    	INTR_INFO_DELIVER_CODE_MASK
#define VECTORING_INFO_VALID_MASK       	INTR_INFO_VALID_MASK

#define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
#define INTR_TYPE_NMI_INTR		(2 << 8) /* NMI */
#define INTR_TYPE_EXCEPTION             (3 << 8) /* processor exception */
#define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */

/* GUEST_INTERRUPTIBILITY_INFO flags. */
#define GUEST_INTR_STATE_STI		0x00000001
#define GUEST_INTR_STATE_MOV_SS		0x00000002
#define GUEST_INTR_STATE_SMI		0x00000004
#define GUEST_INTR_STATE_NMI		0x00000008

/*
 * Exit Qualifications for MOV for Control Register Access
 */
#define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
#define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
#define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
#define LMSW_SOURCE_DATA_SHIFT 16
#define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
#define REG_EAX                         (0 << 8)
#define REG_ECX                         (1 << 8)
#define REG_EDX                         (2 << 8)
#define REG_EBX                         (3 << 8)
#define REG_ESP                         (4 << 8)
#define REG_EBP                         (5 << 8)
#define REG_ESI                         (6 << 8)
#define REG_EDI                         (7 << 8)
#define REG_R8                         (8 << 8)
#define REG_R9                         (9 << 8)
#define REG_R10                        (10 << 8)
#define REG_R11                        (11 << 8)
#define REG_R12                        (12 << 8)
#define REG_R13                        (13 << 8)
#define REG_R14                        (14 << 8)
#define REG_R15                        (15 << 8)

/*
 * Exit Qualifications for MOV for Debug Register Access
 */
#define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
#define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
#define TYPE_MOV_TO_DR                  (0 << 4)
#define TYPE_MOV_FROM_DR                (1 << 4)
#define DEBUG_REG_ACCESS_REG            0xf00   /* 11:8, general purpose reg. */


/* segment AR */
#define SEGMENT_AR_L_MASK (1 << 13)

#define AR_TYPE_ACCESSES_MASK 1
#define AR_TYPE_READABLE_MASK (1 << 1)
#define AR_TYPE_WRITEABLE_MASK (1 << 2)
#define AR_TYPE_CODE_MASK (1 << 3)
#define AR_TYPE_MASK 0x0f
#define AR_TYPE_BUSY_64_TSS 11
#define AR_TYPE_BUSY_32_TSS 11
#define AR_TYPE_BUSY_16_TSS 3
#define AR_TYPE_LDT 2

#define AR_UNUSABLE_MASK (1 << 16)
#define AR_S_MASK (1 << 4)
#define AR_P_MASK (1 << 7)
#define AR_L_MASK (1 << 13)
#define AR_DB_MASK (1 << 14)
#define AR_G_MASK (1 << 15)
#define AR_DPL_SHIFT 5
#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)

#define AR_RESERVD_MASK 0xfffe0f00

#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT	9
#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT	10

#define VMX_NR_VPIDS				(1 << 16)
#define VMX_VPID_EXTENT_SINGLE_CONTEXT		1
#define VMX_VPID_EXTENT_ALL_CONTEXT		2

#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR		0
#define VMX_EPT_EXTENT_CONTEXT			1
#define VMX_EPT_EXTENT_GLOBAL			2
#define VMX_EPT_EXTENT_INDIVIDUAL_BIT		(1ull << 24)
#define VMX_EPT_EXTENT_CONTEXT_BIT		(1ull << 25)
#define VMX_EPT_EXTENT_GLOBAL_BIT		(1ull << 26)
#define VMX_EPT_DEFAULT_GAW			3
#define VMX_EPT_MAX_GAW				0x4
#define VMX_EPT_MT_EPTE_SHIFT			3
#define VMX_EPT_GAW_EPTP_SHIFT			3
#define VMX_EPT_DEFAULT_MT			0x6ull
#define VMX_EPT_READABLE_MASK			0x1ull
#define VMX_EPT_WRITABLE_MASK			0x2ull
#define VMX_EPT_EXECUTABLE_MASK			0x4ull

#define VMX_EPT_IDENTITY_PAGETABLE_ADDR		0xfffbc000ul

#endif
Commit	Line	Data
6aa8b732 AK	1	#ifndef VMX_H
	2	#define VMX_H
	3
	4	/*
	5	* vmx.h: VMX Architecture related definitions
	6	* Copyright (c) 2004, Intel Corporation.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	19	* Place - Suite 330, Boston, MA 02111-1307 USA.
	20	*
	21	* A few random additions are:
	22	* Copyright (C) 2006 Qumranet
	23	* Avi Kivity <avi@qumranet.com>
	24	* Yaniv Kamay <yaniv@qumranet.com>
	25	*
	26	*/
	27
8a70cc3d ED	28	/*
	29	* Definitions of Primary Processor-Based VM-Execution Controls.
	30	*/
62b3ffb8 YS	31	#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
	32	#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
	33	#define CPU_BASED_HLT_EXITING 0x00000080
	34	#define CPU_BASED_INVLPG_EXITING 0x00000200
	35	#define CPU_BASED_MWAIT_EXITING 0x00000400
	36	#define CPU_BASED_RDPMC_EXITING 0x00000800
	37	#define CPU_BASED_RDTSC_EXITING 0x00001000
d56f546d SY	38	#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
d56f546d SY	39	#define CPU_BASED_CR3_STORE_EXITING 0x00010000
62b3ffb8 YS	40	#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
	41	#define CPU_BASED_CR8_STORE_EXITING 0x00100000
	42	#define CPU_BASED_TPR_SHADOW 0x00200000
f08864b4	43	#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
62b3ffb8 YS	44	#define CPU_BASED_MOV_DR_EXITING 0x00800000
	45	#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
	46	#define CPU_BASED_USE_IO_BITMAPS 0x02000000
	47	#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
	48	#define CPU_BASED_MONITOR_EXITING 0x20000000
	49	#define CPU_BASED_PAUSE_EXITING 0x40000000
	50	#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
8a70cc3d ED	51	/*
	52	* Definitions of Secondary Processor-Based VM-Execution Controls.
	53	*/
	54	#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
d56f546d	55	#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
2384d2b3	56	#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
e5edaa01	57	#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
8a70cc3d	58
6aa8b732	59
62b3ffb8 YS	60	#define PIN_BASED_EXT_INTR_MASK 0x00000001
	61	#define PIN_BASED_NMI_EXITING 0x00000008
	62	#define PIN_BASED_VIRTUAL_NMIS 0x00000020
6aa8b732	63
62b3ffb8 YS	64	#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
62b3ffb8 YS	65	#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
6aa8b732	66
62b3ffb8 YS	67	#define VM_ENTRY_IA32E_MODE 0x00000200
	68	#define VM_ENTRY_SMM 0x00000400
	69	#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
	70
6aa8b732 AK	71	/* VMCS Encodings */
6aa8b732 AK	72	enum vmcs_field {
2384d2b3	73	VIRTUAL_PROCESSOR_ID = 0x00000000,
6aa8b732 AK	74	GUEST_ES_SELECTOR = 0x00000800,
	75	GUEST_CS_SELECTOR = 0x00000802,
	76	GUEST_SS_SELECTOR = 0x00000804,
	77	GUEST_DS_SELECTOR = 0x00000806,
	78	GUEST_FS_SELECTOR = 0x00000808,
	79	GUEST_GS_SELECTOR = 0x0000080a,
	80	GUEST_LDTR_SELECTOR = 0x0000080c,
	81	GUEST_TR_SELECTOR = 0x0000080e,
	82	HOST_ES_SELECTOR = 0x00000c00,
	83	HOST_CS_SELECTOR = 0x00000c02,
	84	HOST_SS_SELECTOR = 0x00000c04,
	85	HOST_DS_SELECTOR = 0x00000c06,
	86	HOST_FS_SELECTOR = 0x00000c08,
	87	HOST_GS_SELECTOR = 0x00000c0a,
	88	HOST_TR_SELECTOR = 0x00000c0c,
	89	IO_BITMAP_A = 0x00002000,
	90	IO_BITMAP_A_HIGH = 0x00002001,
	91	IO_BITMAP_B = 0x00002002,
	92	IO_BITMAP_B_HIGH = 0x00002003,
	93	MSR_BITMAP = 0x00002004,
	94	MSR_BITMAP_HIGH = 0x00002005,
	95	VM_EXIT_MSR_STORE_ADDR = 0x00002006,
	96	VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
	97	VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
	98	VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
	99	VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
	100	VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
	101	TSC_OFFSET = 0x00002010,
	102	TSC_OFFSET_HIGH = 0x00002011,
	103	VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
	104	VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
f78e0e2e SY	105	APIC_ACCESS_ADDR = 0x00002014,
f78e0e2e SY	106	APIC_ACCESS_ADDR_HIGH = 0x00002015,
d56f546d SY	107	EPT_POINTER = 0x0000201a,
	108	EPT_POINTER_HIGH = 0x0000201b,
	109	GUEST_PHYSICAL_ADDRESS = 0x00002400,
	110	GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
6aa8b732 AK	111	VMCS_LINK_POINTER = 0x00002800,
	112	VMCS_LINK_POINTER_HIGH = 0x00002801,
	113	GUEST_IA32_DEBUGCTL = 0x00002802,
	114	GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
d56f546d SY	115	GUEST_PDPTR0 = 0x0000280a,
	116	GUEST_PDPTR0_HIGH = 0x0000280b,
	117	GUEST_PDPTR1 = 0x0000280c,
	118	GUEST_PDPTR1_HIGH = 0x0000280d,
	119	GUEST_PDPTR2 = 0x0000280e,
	120	GUEST_PDPTR2_HIGH = 0x0000280f,
	121	GUEST_PDPTR3 = 0x00002810,
	122	GUEST_PDPTR3_HIGH = 0x00002811,
6aa8b732 AK	123	PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
	124	CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
	125	EXCEPTION_BITMAP = 0x00004004,
	126	PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
	127	PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
	128	CR3_TARGET_COUNT = 0x0000400a,
	129	VM_EXIT_CONTROLS = 0x0000400c,
	130	VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
	131	VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
	132	VM_ENTRY_CONTROLS = 0x00004012,
	133	VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
	134	VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
	135	VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
	136	VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
	137	TPR_THRESHOLD = 0x0000401c,
	138	SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
	139	VM_INSTRUCTION_ERROR = 0x00004400,
	140	VM_EXIT_REASON = 0x00004402,
	141	VM_EXIT_INTR_INFO = 0x00004404,
	142	VM_EXIT_INTR_ERROR_CODE = 0x00004406,
	143	IDT_VECTORING_INFO_FIELD = 0x00004408,
	144	IDT_VECTORING_ERROR_CODE = 0x0000440a,
	145	VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
	146	VMX_INSTRUCTION_INFO = 0x0000440e,
	147	GUEST_ES_LIMIT = 0x00004800,
	148	GUEST_CS_LIMIT = 0x00004802,
	149	GUEST_SS_LIMIT = 0x00004804,
	150	GUEST_DS_LIMIT = 0x00004806,
	151	GUEST_FS_LIMIT = 0x00004808,
	152	GUEST_GS_LIMIT = 0x0000480a,
	153	GUEST_LDTR_LIMIT = 0x0000480c,
	154	GUEST_TR_LIMIT = 0x0000480e,
	155	GUEST_GDTR_LIMIT = 0x00004810,
	156	GUEST_IDTR_LIMIT = 0x00004812,
	157	GUEST_ES_AR_BYTES = 0x00004814,
	158	GUEST_CS_AR_BYTES = 0x00004816,
	159	GUEST_SS_AR_BYTES = 0x00004818,
	160	GUEST_DS_AR_BYTES = 0x0000481a,
	161	GUEST_FS_AR_BYTES = 0x0000481c,
	162	GUEST_GS_AR_BYTES = 0x0000481e,
	163	GUEST_LDTR_AR_BYTES = 0x00004820,
	164	GUEST_TR_AR_BYTES = 0x00004822,
	165	GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
	166	GUEST_ACTIVITY_STATE = 0X00004826,
	167	GUEST_SYSENTER_CS = 0x0000482A,
	168	HOST_IA32_SYSENTER_CS = 0x00004c00,
	169	CR0_GUEST_HOST_MASK = 0x00006000,
	170	CR4_GUEST_HOST_MASK = 0x00006002,
	171	CR0_READ_SHADOW = 0x00006004,
	172	CR4_READ_SHADOW = 0x00006006,
	173	CR3_TARGET_VALUE0 = 0x00006008,
	174	CR3_TARGET_VALUE1 = 0x0000600a,
	175	CR3_TARGET_VALUE2 = 0x0000600c,
	176	CR3_TARGET_VALUE3 = 0x0000600e,
	177	EXIT_QUALIFICATION = 0x00006400,
	178	GUEST_LINEAR_ADDRESS = 0x0000640a,
	179	GUEST_CR0 = 0x00006800,
	180	GUEST_CR3 = 0x00006802,
	181	GUEST_CR4 = 0x00006804,
	182	GUEST_ES_BASE = 0x00006806,
	183	GUEST_CS_BASE = 0x00006808,
	184	GUEST_SS_BASE = 0x0000680a,
	185	GUEST_DS_BASE = 0x0000680c,
	186	GUEST_FS_BASE = 0x0000680e,
187	GUEST_GS_BASE = 0x00006810,
188	GUEST_LDTR_BASE = 0x00006812,
189	GUEST_TR_BASE = 0x00006814,
190	GUEST_GDTR_BASE = 0x00006816,
191	GUEST_IDTR_BASE = 0x00006818,
192	GUEST_DR7 = 0x0000681a,
193	GUEST_RSP = 0x0000681c,
194	GUEST_RIP = 0x0000681e,
195	GUEST_RFLAGS = 0x00006820,
196	GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
197	GUEST_SYSENTER_ESP = 0x00006824,
198	GUEST_SYSENTER_EIP = 0x00006826,
199	HOST_CR0 = 0x00006c00,
200	HOST_CR3 = 0x00006c02,
201	HOST_CR4 = 0x00006c04,
202	HOST_FS_BASE = 0x00006c06,
203	HOST_GS_BASE = 0x00006c08,
204	HOST_TR_BASE = 0x00006c0a,
205	HOST_GDTR_BASE = 0x00006c0c,
206	HOST_IDTR_BASE = 0x00006c0e,
207	HOST_IA32_SYSENTER_ESP = 0x00006c10,
208	HOST_IA32_SYSENTER_EIP = 0x00006c12,
209	HOST_RSP = 0x00006c14,
210	HOST_RIP = 0x00006c16,
211	};
212
213	#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
214
215	#define EXIT_REASON_EXCEPTION_NMI 0
216	#define EXIT_REASON_EXTERNAL_INTERRUPT 1
988ad74f	217	#define EXIT_REASON_TRIPLE_FAULT 2
6aa8b732 AK	218
6aa8b732 AK	219	#define EXIT_REASON_PENDING_INTERRUPT 7
f08864b4	220	#define EXIT_REASON_NMI_WINDOW 8
6aa8b732 AK	221	#define EXIT_REASON_TASK_SWITCH 9
	222	#define EXIT_REASON_CPUID 10
	223	#define EXIT_REASON_HLT 12
	224	#define EXIT_REASON_INVLPG 14
	225	#define EXIT_REASON_RDPMC 15
	226	#define EXIT_REASON_RDTSC 16
	227	#define EXIT_REASON_VMCALL 18
	228	#define EXIT_REASON_VMCLEAR 19
	229	#define EXIT_REASON_VMLAUNCH 20
	230	#define EXIT_REASON_VMPTRLD 21
	231	#define EXIT_REASON_VMPTRST 22
	232	#define EXIT_REASON_VMREAD 23
	233	#define EXIT_REASON_VMRESUME 24
	234	#define EXIT_REASON_VMWRITE 25
	235	#define EXIT_REASON_VMOFF 26
	236	#define EXIT_REASON_VMON 27
	237	#define EXIT_REASON_CR_ACCESS 28
	238	#define EXIT_REASON_DR_ACCESS 29
	239	#define EXIT_REASON_IO_INSTRUCTION 30
	240	#define EXIT_REASON_MSR_READ 31
	241	#define EXIT_REASON_MSR_WRITE 32
	242	#define EXIT_REASON_MWAIT_INSTRUCTION 36
6e5d865c	243	#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
f78e0e2e	244	#define EXIT_REASON_APIC_ACCESS 44
d56f546d SY	245	#define EXIT_REASON_EPT_VIOLATION 48
d56f546d SY	246	#define EXIT_REASON_EPT_MISCONFIG 49
e5edaa01	247	#define EXIT_REASON_WBINVD 54
6aa8b732 AK	248
	249	/*
	250	* Interruption-information format
	251	*/
	252	#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
	253	#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
2e11384c	254	#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
f08864b4	255	#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
6aa8b732	256	#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
f08864b4	257	#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
6aa8b732 AK	258
	259	#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
	260	#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
2e11384c	261	#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
6aa8b732 AK	262	#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
	263
	264	#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
f08864b4	265	#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
6aa8b732	266	#define INTR_TYPE_EXCEPTION (3 << 8) /* processor exception */
9c5623e3	267	#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
6aa8b732	268
f08864b4 SY	269	/* GUEST_INTERRUPTIBILITY_INFO flags. */
	270	#define GUEST_INTR_STATE_STI 0x00000001
	271	#define GUEST_INTR_STATE_MOV_SS 0x00000002
	272	#define GUEST_INTR_STATE_SMI 0x00000004
	273	#define GUEST_INTR_STATE_NMI 0x00000008
	274
6aa8b732 AK	275	/*
	276	* Exit Qualifications for MOV for Control Register Access
	277	*/
d77c26fc	278	#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
6aa8b732	279	#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
d77c26fc	280	#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
6aa8b732 AK	281	#define LMSW_SOURCE_DATA_SHIFT 16
	282	#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
	283	#define REG_EAX (0 << 8)
	284	#define REG_ECX (1 << 8)
	285	#define REG_EDX (2 << 8)
	286	#define REG_EBX (3 << 8)
	287	#define REG_ESP (4 << 8)
	288	#define REG_EBP (5 << 8)
	289	#define REG_ESI (6 << 8)
	290	#define REG_EDI (7 << 8)
	291	#define REG_R8 (8 << 8)
	292	#define REG_R9 (9 << 8)
	293	#define REG_R10 (10 << 8)
	294	#define REG_R11 (11 << 8)
	295	#define REG_R12 (12 << 8)
	296	#define REG_R13 (13 << 8)
	297	#define REG_R14 (14 << 8)
	298	#define REG_R15 (15 << 8)
	299
	300	/*
	301	* Exit Qualifications for MOV for Debug Register Access
	302	*/
d77c26fc	303	#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
6aa8b732 AK	304	#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
	305	#define TYPE_MOV_TO_DR (0 << 4)
	306	#define TYPE_MOV_FROM_DR (1 << 4)
d77c26fc	307	#define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose reg. */
6aa8b732 AK	308
	309
	310	/* segment AR */
	311	#define SEGMENT_AR_L_MASK (1 << 13)
	312
6aa8b732 AK	313	#define AR_TYPE_ACCESSES_MASK 1
	314	#define AR_TYPE_READABLE_MASK (1 << 1)
	315	#define AR_TYPE_WRITEABLE_MASK (1 << 2)
	316	#define AR_TYPE_CODE_MASK (1 << 3)
	317	#define AR_TYPE_MASK 0x0f
	318	#define AR_TYPE_BUSY_64_TSS 11
	319	#define AR_TYPE_BUSY_32_TSS 11
	320	#define AR_TYPE_BUSY_16_TSS 3
	321	#define AR_TYPE_LDT 2
	322
	323	#define AR_UNUSABLE_MASK (1 << 16)
	324	#define AR_S_MASK (1 << 4)
	325	#define AR_P_MASK (1 << 7)
	326	#define AR_L_MASK (1 << 13)
	327	#define AR_DB_MASK (1 << 14)
	328	#define AR_G_MASK (1 << 15)
	329	#define AR_DPL_SHIFT 5
	330	#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
	331
	332	#define AR_RESERVD_MASK 0xfffe0f00
	333
f78e0e2e	334	#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT 9
b7ebfb05	335	#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT 10
f78e0e2e	336
2384d2b3 SY	337	#define VMX_NR_VPIDS (1 << 16)
	338	#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
	339	#define VMX_VPID_EXTENT_ALL_CONTEXT 2
	340
d56f546d SY	341	#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
	342	#define VMX_EPT_EXTENT_CONTEXT 1
	343	#define VMX_EPT_EXTENT_GLOBAL 2
	344	#define VMX_EPT_EXTENT_INDIVIDUAL_BIT (1ull << 24)
	345	#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
	346	#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
67253af5	347	#define VMX_EPT_DEFAULT_GAW 3
1439442c SY	348	#define VMX_EPT_MAX_GAW 0x4
	349	#define VMX_EPT_MT_EPTE_SHIFT 3
	350	#define VMX_EPT_GAW_EPTP_SHIFT 3
	351	#define VMX_EPT_DEFAULT_MT 0x6ull
	352	#define VMX_EPT_READABLE_MASK 0x1ull
	353	#define VMX_EPT_WRITABLE_MASK 0x2ull
	354	#define VMX_EPT_EXECUTABLE_MASK 0x4ull
d56f546d	355
b7ebfb05 SY	356	#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
b7ebfb05 SY	357
6aa8b732	358	#endif