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KVM: MMU: Don't track nested fault info in error-code
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
3842d135
AK		 287 kvm_make_request(KVM_REQ_EVENT, vcpu);
288
3fd28fce
ED		 289 if (!vcpu->arch.exception.pending) {
290 queue:
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
3f0fd292 295 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 296 return;
297 }
298
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
a8eeb04a 303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 304 return;
305 }
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
315 } else
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
318 exception */
319 goto queue;
320}
321
298101da
AK		 322void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
323{
ce7ddec4 324 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 325}
326EXPORT_SYMBOL_GPL(kvm_queue_exception);
327
ce7ddec4
JR		 328void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
331}
332EXPORT_SYMBOL_GPL(kvm_requeue_exception);
333
8df25a32 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 335{
8df25a32
JR		 336 unsigned error_code = vcpu->arch.fault.error_code;
337
c3c91fee 338 ++vcpu->stat.pf_guest;
8df25a32 339 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341}
342
d4f8cf66
JR		 343void kvm_propagate_fault(struct kvm_vcpu *vcpu)
344{
0959ffac 345 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 346 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
347 else
348 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 349
350 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 351}
352
3419ffc8
SY		 353void kvm_inject_nmi(struct kvm_vcpu *vcpu)
354{
3842d135 355 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 356 vcpu->arch.nmi_pending = 1;
357}
358EXPORT_SYMBOL_GPL(kvm_inject_nmi);
359
298101da
AK		 360void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
361{
ce7ddec4 362 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 363}
364EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
365
ce7ddec4
JR		 366void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
368 kvm_multiple_exception(vcpu, nr, true, error_code, true);
369}
370EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
371
0a79b009
AK		 372/*
373 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
374 * a #GP and return false.
375 */
376bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 377{
0a79b009
AK		 378 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
379 return true;
380 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
381 return false;
298101da 382}
0a79b009 383EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 384
ec92fe44
JR		 385/*
386 * This function will be used to read from the physical memory of the currently
387 * running guest. The difference to kvm_read_guest_page is that this function
388 * can read from guest physical or from the guest's guest physical memory.
389 */
390int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
391 gfn_t ngfn, void *data, int offset, int len,
392 u32 access)
393{
394 gfn_t real_gfn;
395 gpa_t ngpa;
396
397 ngpa = gfn_to_gpa(ngfn);
398 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
399 if (real_gfn == UNMAPPED_GVA)
400 return -EFAULT;
401
402 real_gfn = gpa_to_gfn(real_gfn);
403
404 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
405}
406EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
407
3d06b8bf
JR		 408int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
409 void *data, int offset, int len, u32 access)
410{
411 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
412 data, offset, len, access);
413}
414
a03490ed
CO		 415/*
416 * Load the pae pdptrs. Return true is they are all valid.
417 */
ff03a073 418int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 419{
420 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
421 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
422 int i;
423 int ret;
ff03a073 424 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 425
ff03a073
JR		 426 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
427 offset * sizeof(u64), sizeof(pdpte),
428 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 429 if (ret < 0) {
430 ret = 0;
431 goto out;
432 }
433 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 434 if (is_present_gpte(pdpte[i]) &&
20c466b5 435 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 436 ret = 0;
437 goto out;
438 }
439 }
440 ret = 1;
441
ff03a073 442 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 443 __set_bit(VCPU_EXREG_PDPTR,
444 (unsigned long *)&vcpu->arch.regs_avail);
445 __set_bit(VCPU_EXREG_PDPTR,
446 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 447out:
a03490ed
CO		 448
449 return ret;
450}
cc4b6871 451EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 452
d835dfec
AK		 453static bool pdptrs_changed(struct kvm_vcpu *vcpu)
454{
ff03a073 455 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 456 bool changed = true;
3d06b8bf
JR		 457 int offset;
458 gfn_t gfn;
d835dfec
AK		 459 int r;
460
461 if (is_long_mode(vcpu) || !is_pae(vcpu))
462 return false;
463
6de4f3ad
AK		 464 if (!test_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail))
466 return true;
467
3d06b8bf
JR		 468 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
469 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
470 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
471 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 472 if (r < 0)
473 goto out;
ff03a073 474 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 475out:
d835dfec
AK		 476
477 return changed;
478}
479
49a9b07e 480int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 481{
aad82703
SY		 482 unsigned long old_cr0 = kvm_read_cr0(vcpu);
483 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
484 X86_CR0_CD | X86_CR0_NW;
485
f9a48e6a
AK		 486 cr0 |= X86_CR0_ET;
487
ab344828 488#ifdef CONFIG_X86_64
0f12244f
GN		 489 if (cr0 & 0xffffffff00000000UL)
490 return 1;
ab344828
GN		 491#endif
492
493 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 494
0f12244f
GN		 495 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
496 return 1;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
499 return 1;
a03490ed
CO		 500
501 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
502#ifdef CONFIG_X86_64
f6801dff 503 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 504 int cs_db, cs_l;
505
0f12244f
GN		 506 if (!is_pae(vcpu))
507 return 1;
a03490ed 508 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 509 if (cs_l)
510 return 1;
a03490ed
CO		 511 } else
512#endif
ff03a073
JR		 513 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
514 vcpu->arch.cr3))
0f12244f 515 return 1;
a03490ed
CO		 516 }
517
518 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 519
aad82703
SY		 520 if ((cr0 ^ old_cr0) & update_bits)
521 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 522 return 0;
523}
2d3ad1f4 524EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 525
2d3ad1f4 526void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 527{
49a9b07e 528 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 531
2acf923e
DC		 532int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
533{
534 u64 xcr0;
535
536 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
537 if (index != XCR_XFEATURE_ENABLED_MASK)
538 return 1;
539 xcr0 = xcr;
540 if (kvm_x86_ops->get_cpl(vcpu) != 0)
541 return 1;
542 if (!(xcr0 & XSTATE_FP))
543 return 1;
544 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
545 return 1;
546 if (xcr0 & ~host_xcr0)
547 return 1;
548 vcpu->arch.xcr0 = xcr0;
549 vcpu->guest_xcr0_loaded = 0;
550 return 0;
551}
552
553int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 if (__kvm_set_xcr(vcpu, index, xcr)) {
556 kvm_inject_gp(vcpu, 0);
557 return 1;
558 }
559 return 0;
560}
561EXPORT_SYMBOL_GPL(kvm_set_xcr);
562
563static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
564{
565 struct kvm_cpuid_entry2 *best;
566
567 best = kvm_find_cpuid_entry(vcpu, 1, 0);
568 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
569}
570
571static void update_cpuid(struct kvm_vcpu *vcpu)
572{
573 struct kvm_cpuid_entry2 *best;
574
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
576 if (!best)
577 return;
578
579 /* Update OSXSAVE bit */
580 if (cpu_has_xsave && best->function == 0x1) {
581 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
583 best->ecx |= bit(X86_FEATURE_OSXSAVE);
584 }
585}
586
a83b29c6 587int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 588{
fc78f519 589 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 590 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
591
0f12244f
GN		 592 if (cr4 & CR4_RESERVED_BITS)
593 return 1;
a03490ed 594
2acf923e
DC		 595 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
596 return 1;
597
a03490ed 598 if (is_long_mode(vcpu)) {
0f12244f
GN		 599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
a2edf57f
AK		 601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 604 return 1;
605
606 if (cr4 & X86_CR4_VMXE)
607 return 1;
a03490ed 608
a03490ed 609 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 610
aad82703
SY		 611 if ((cr4 ^ old_cr4) & pdptr_bits)
612 kvm_mmu_reset_context(vcpu);
0f12244f 613
2acf923e
DC		 614 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
615 update_cpuid(vcpu);
616
0f12244f
GN		 617 return 0;
618}
2d3ad1f4 619EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 620
2390218b 621int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 622{
ad312c7c 623 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 624 kvm_mmu_sync_roots(vcpu);
d835dfec 625 kvm_mmu_flush_tlb(vcpu);
0f12244f 626 return 0;
d835dfec
AK		 627 }
628
a03490ed 629 if (is_long_mode(vcpu)) {
0f12244f
GN		 630 if (cr3 & CR3_L_MODE_RESERVED_BITS)
631 return 1;
a03490ed
CO		 632 } else {
633 if (is_pae(vcpu)) {
0f12244f
GN		 634 if (cr3 & CR3_PAE_RESERVED_BITS)
635 return 1;
ff03a073
JR		 636 if (is_paging(vcpu) &&
637 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 638 return 1;
a03490ed
CO		 639 }
640 /*
641 * We don't check reserved bits in nonpae mode, because
642 * this isn't enforced, and VMware depends on this.
643 */
644 }
645
a03490ed
CO		 646 /*
647 * Does the new cr3 value map to physical memory? (Note, we
648 * catch an invalid cr3 even in real-mode, because it would
649 * cause trouble later on when we turn on paging anyway.)
650 *
651 * A real CPU would silently accept an invalid cr3 and would
652 * attempt to use it - with largely undefined (and often hard
653 * to debug) behavior on the guest side.
654 */
655 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 656 return 1;
657 vcpu->arch.cr3 = cr3;
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660}
2d3ad1f4 661EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 662
0f12244f 663int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 664{
0f12244f
GN		 665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
a03490ed
CO		 667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
ad312c7c 670 vcpu->arch.cr8 = cr8;
0f12244f
GN		 671 return 0;
672}
673
674void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675{
676 if (__kvm_set_cr8(vcpu, cr8))
677 kvm_inject_gp(vcpu, 0);
a03490ed 678}
2d3ad1f4 679EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 680
2d3ad1f4 681unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 682{
683 if (irqchip_in_kernel(vcpu->kvm))
684 return kvm_lapic_get_cr8(vcpu);
685 else
ad312c7c 686 return vcpu->arch.cr8;
a03490ed 687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 689
338dbc97 690static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 691{
692 switch (dr) {
693 case 0 ... 3:
694 vcpu->arch.db[dr] = val;
695 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
696 vcpu->arch.eff_db[dr] = val;
697 break;
698 case 4:
338dbc97
GN		 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 return 1; /* #UD */
020df079
GN		 701 /* fall through */
702 case 6:
338dbc97
GN		 703 if (val & 0xffffffff00000000ULL)
704 return -1; /* #GP */
020df079
GN		 705 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
706 break;
707 case 5:
338dbc97
GN		 708 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
709 return 1; /* #UD */
020df079
GN		 710 /* fall through */
711 default: /* 7 */
338dbc97
GN		 712 if (val & 0xffffffff00000000ULL)
713 return -1; /* #GP */
020df079
GN		 714 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
715 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
716 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
717 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
718 }
719 break;
720 }
721
722 return 0;
723}
338dbc97
GN		 724
725int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
726{
727 int res;
728
729 res = __kvm_set_dr(vcpu, dr, val);
730 if (res > 0)
731 kvm_queue_exception(vcpu, UD_VECTOR);
732 else if (res < 0)
733 kvm_inject_gp(vcpu, 0);
734
735 return res;
736}
020df079
GN		 737EXPORT_SYMBOL_GPL(kvm_set_dr);
738
338dbc97 739static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 740{
741 switch (dr) {
742 case 0 ... 3:
743 *val = vcpu->arch.db[dr];
744 break;
745 case 4:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 case 6:
750 *val = vcpu->arch.dr6;
751 break;
752 case 5:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 default: /* 7 */
757 *val = vcpu->arch.dr7;
758 break;
759 }
760
761 return 0;
762}
338dbc97
GN		 763
764int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765{
766 if (_kvm_get_dr(vcpu, dr, val)) {
767 kvm_queue_exception(vcpu, UD_VECTOR);
768 return 1;
769 }
770 return 0;
771}
020df079
GN		 772EXPORT_SYMBOL_GPL(kvm_get_dr);
773
043405e1
CO		 774/*
775 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
776 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
777 *
778 * This list is modified at module load time to reflect the
e3267cbb
GC		 779 * capabilities of the host cpu. This capabilities test skips MSRs that are
780 * kvm-specific. Those are put in the beginning of the list.
043405e1 781 */
e3267cbb 782
11c6bffa 783#define KVM_SAVE_MSRS_BEGIN 7
043405e1 784static u32 msrs_to_save[] = {
e3267cbb 785 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 786 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 787 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 788 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 789 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 790 MSR_STAR,
043405e1
CO		 791#ifdef CONFIG_X86_64
792 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
793#endif
e90aa41e 794 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 795};
796
797static unsigned num_msrs_to_save;
798
799static u32 emulated_msrs[] = {
800 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 801 MSR_IA32_MCG_STATUS,
802 MSR_IA32_MCG_CTL,
043405e1
CO		 803};
804
b69e8cae 805static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 806{
aad82703
SY		 807 u64 old_efer = vcpu->arch.efer;
808
b69e8cae
RJ		 809 if (efer & efer_reserved_bits)
810 return 1;
15c4a640
CO		 811
812 if (is_paging(vcpu)
b69e8cae
RJ		 813 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
814 return 1;
15c4a640 815
1b2fd70c
AG		 816 if (efer & EFER_FFXSR) {
817 struct kvm_cpuid_entry2 *feat;
818
819 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 820 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
821 return 1;
1b2fd70c
AG		 822 }
823
d8017474
AG		 824 if (efer & EFER_SVME) {
825 struct kvm_cpuid_entry2 *feat;
826
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 828 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
829 return 1;
d8017474
AG		 830 }
831
15c4a640 832 efer &= ~EFER_LMA;
f6801dff 833 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 834
a3d204e2
SY		 835 kvm_x86_ops->set_efer(vcpu, efer);
836
9645bb56
AK		 837 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
838 kvm_mmu_reset_context(vcpu);
b69e8cae 839
aad82703
SY		 840 /* Update reserved bits */
841 if ((efer ^ old_efer) & EFER_NX)
842 kvm_mmu_reset_context(vcpu);
843
b69e8cae 844 return 0;
15c4a640
CO		 845}
846
f2b4b7dd
JR		 847void kvm_enable_efer_bits(u64 mask)
848{
849 efer_reserved_bits &= ~mask;
850}
851EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
852
853
15c4a640
CO		 854/*
855 * Writes msr value into into the appropriate "register".
856 * Returns 0 on success, non-0 otherwise.
857 * Assumes vcpu_load() was already called.
858 */
859int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
860{
861 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
862}
863
313a3dc7
CO		 864/*
865 * Adapt set_msr() to msr_io()'s calling convention
866 */
867static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
868{
869 return kvm_set_msr(vcpu, index, *data);
870}
871
18068523
GOC		 872static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
873{
9ed3c444
AK		 874 int version;
875 int r;
50d0a0f9 876 struct pvclock_wall_clock wc;
923de3cf 877 struct timespec boot;
18068523
GOC		 878
879 if (!wall_clock)
880 return;
881
9ed3c444
AK		 882 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
883 if (r)
884 return;
885
886 if (version & 1)
887 ++version; /* first time write, random junk */
888
889 ++version;
18068523 890
18068523
GOC		 891 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
892
50d0a0f9
GH		 893 /*
894 * The guest calculates current wall clock time by adding
895 * system time (updated by kvm_write_guest_time below) to the
896 * wall clock specified here. guest system time equals host
897 * system time for us, thus we must fill in host boot time here.
898 */
923de3cf 899 getboottime(&boot);
50d0a0f9
GH		 900
901 wc.sec = boot.tv_sec;
902 wc.nsec = boot.tv_nsec;
903 wc.version = version;
18068523
GOC		 904
905 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
906
907 version++;
908 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 909}
910
50d0a0f9
GH		 911static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
912{
913 uint32_t quotient, remainder;
914
915 /* Don't try to replace with do_div(), this one calculates
916 * "(dividend << 32) / divisor" */
917 __asm__ ( "divl %4"
918 : "=a" (quotient), "=d" (remainder)
919 : "0" (0), "1" (dividend), "r" (divisor) );
920 return quotient;
921}
922
923static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
924{
925 uint64_t nsecs = 1000000000LL;
926 int32_t shift = 0;
927 uint64_t tps64;
928 uint32_t tps32;
929
930 tps64 = tsc_khz * 1000LL;
931 while (tps64 > nsecs*2) {
932 tps64 >>= 1;
933 shift--;
934 }
935
936 tps32 = (uint32_t)tps64;
937 while (tps32 <= (uint32_t)nsecs) {
938 tps32 <<= 1;
939 shift++;
940 }
941
942 hv_clock->tsc_shift = shift;
943 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
944
945 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 946 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 947 hv_clock->tsc_to_system_mul);
948}
949
759379dd
ZA		 950static inline u64 get_kernel_ns(void)
951{
952 struct timespec ts;
953
954 WARN_ON(preemptible());
955 ktime_get_ts(&ts);
956 monotonic_to_bootbased(&ts);
957 return timespec_to_ns(&ts);
958}
959
c8076604
GH		 960static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
961
8cfdc000
ZA		 962static inline int kvm_tsc_changes_freq(void)
963{
964 int cpu = get_cpu();
965 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
966 cpufreq_quick_get(cpu) != 0;
967 put_cpu();
968 return ret;
969}
970
759379dd
ZA		 971static inline u64 nsec_to_cycles(u64 nsec)
972{
217fc9cf
AK		 973 u64 ret;
974
759379dd
ZA		 975 WARN_ON(preemptible());
976 if (kvm_tsc_changes_freq())
977 printk_once(KERN_WARNING
978 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 979 ret = nsec * __get_cpu_var(cpu_tsc_khz);
980 do_div(ret, USEC_PER_SEC);
981 return ret;
759379dd
ZA		 982}
983
99e3e30a
ZA		 984void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
985{
986 struct kvm *kvm = vcpu->kvm;
f38e098f 987 u64 offset, ns, elapsed;
99e3e30a 988 unsigned long flags;
46543ba4 989 s64 sdiff;
99e3e30a
ZA		 990
991 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
992 offset = data - native_read_tsc();
759379dd 993 ns = get_kernel_ns();
f38e098f 994 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 995 sdiff = data - kvm->arch.last_tsc_write;
996 if (sdiff < 0)
997 sdiff = -sdiff;
f38e098f
ZA		 998
999 /*
46543ba4 1000 * Special case: close write to TSC within 5 seconds of
f38e098f 1001 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1002 * The 5 seconds is to accomodate host load / swapping as
1003 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1004 *
1005 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1006 * or make a best guest using elapsed value.
f38e098f 1007 */
46543ba4
ZA		 1008 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1009 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1010 if (!check_tsc_unstable()) {
1011 offset = kvm->arch.last_tsc_offset;
1012 pr_debug("kvm: matched tsc offset for %llu\n", data);
1013 } else {
759379dd
ZA		 1014 u64 delta = nsec_to_cycles(elapsed);
1015 offset += delta;
1016 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1017 }
1018 ns = kvm->arch.last_tsc_nsec;
1019 }
1020 kvm->arch.last_tsc_nsec = ns;
1021 kvm->arch.last_tsc_write = data;
1022 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1023 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1024 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1025
1026 /* Reset of TSC must disable overshoot protection below */
1027 vcpu->arch.hv_clock.tsc_timestamp = 0;
1028}
1029EXPORT_SYMBOL_GPL(kvm_write_tsc);
1030
8cfdc000 1031static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 1032{
18068523
GOC		 1033 unsigned long flags;
1034 struct kvm_vcpu_arch *vcpu = &v->arch;
1035 void *shared_kaddr;
463656c0 1036 unsigned long this_tsc_khz;
1d5f066e
ZA		 1037 s64 kernel_ns, max_kernel_ns;
1038 u64 tsc_timestamp;
18068523
GOC		 1039
1040 if ((!vcpu->time_page))
8cfdc000 1041 return 0;
50d0a0f9 1042
18068523
GOC		 1043 /* Keep irq disabled to prevent changes to the clock */
1044 local_irq_save(flags);
1d5f066e 1045 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1046 kernel_ns = get_kernel_ns();
8cfdc000 1047 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 1048 local_irq_restore(flags);
1049
8cfdc000
ZA		 1050 if (unlikely(this_tsc_khz == 0)) {
1051 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1052 return 1;
1053 }
18068523 1054
1d5f066e
ZA		 1055 /*
1056 * Time as measured by the TSC may go backwards when resetting the base
1057 * tsc_timestamp. The reason for this is that the TSC resolution is
1058 * higher than the resolution of the other clock scales. Thus, many
1059 * possible measurments of the TSC correspond to one measurement of any
1060 * other clock, and so a spread of values is possible. This is not a
1061 * problem for the computation of the nanosecond clock; with TSC rates
1062 * around 1GHZ, there can only be a few cycles which correspond to one
1063 * nanosecond value, and any path through this code will inevitably
1064 * take longer than that. However, with the kernel_ns value itself,
1065 * the precision may be much lower, down to HZ granularity. If the
1066 * first sampling of TSC against kernel_ns ends in the low part of the
1067 * range, and the second in the high end of the range, we can get:
1068 *
1069 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1070 *
1071 * As the sampling errors potentially range in the thousands of cycles,
1072 * it is possible such a time value has already been observed by the
1073 * guest. To protect against this, we must compute the system time as
1074 * observed by the guest and ensure the new system time is greater.
1075 */
1076 max_kernel_ns = 0;
1077 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1078 max_kernel_ns = vcpu->last_guest_tsc -
1079 vcpu->hv_clock.tsc_timestamp;
1080 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1081 vcpu->hv_clock.tsc_to_system_mul,
1082 vcpu->hv_clock.tsc_shift);
1083 max_kernel_ns += vcpu->last_kernel_ns;
1084 }
1085
e48672fa 1086 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1087 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1088 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1089 }
1090
1d5f066e
ZA		 1091 if (max_kernel_ns > kernel_ns)
1092 kernel_ns = max_kernel_ns;
1093
8cfdc000 1094 /* With all the info we got, fill in the values */
1d5f066e 1095 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1096 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1097 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1098 vcpu->hv_clock.flags = 0;
1099
18068523
GOC		 1100 /*
1101 * The interface expects us to write an even number signaling that the
1102 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1103 * state, we just increase by 2 at the end.
18068523 1104 */
50d0a0f9 1105 vcpu->hv_clock.version += 2;
18068523
GOC		 1106
1107 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1108
1109 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1110 sizeof(vcpu->hv_clock));
18068523
GOC		 1111
1112 kunmap_atomic(shared_kaddr, KM_USER0);
1113
1114 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1115 return 0;
18068523
GOC		 1116}
1117
c8076604
GH		 1118static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1119{
1120 struct kvm_vcpu_arch *vcpu = &v->arch;
1121
1122 if (!vcpu->time_page)
1123 return 0;
a8eeb04a 1124 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1125 return 1;
1126}
1127
9ba075a6
AK		 1128static bool msr_mtrr_valid(unsigned msr)
1129{
1130 switch (msr) {
1131 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1132 case MSR_MTRRfix64K_00000:
1133 case MSR_MTRRfix16K_80000:
1134 case MSR_MTRRfix16K_A0000:
1135 case MSR_MTRRfix4K_C0000:
1136 case MSR_MTRRfix4K_C8000:
1137 case MSR_MTRRfix4K_D0000:
1138 case MSR_MTRRfix4K_D8000:
1139 case MSR_MTRRfix4K_E0000:
1140 case MSR_MTRRfix4K_E8000:
1141 case MSR_MTRRfix4K_F0000:
1142 case MSR_MTRRfix4K_F8000:
1143 case MSR_MTRRdefType:
1144 case MSR_IA32_CR_PAT:
1145 return true;
1146 case 0x2f8:
1147 return true;
1148 }
1149 return false;
1150}
1151
d6289b93
MT		 1152static bool valid_pat_type(unsigned t)
1153{
1154 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1155}
1156
1157static bool valid_mtrr_type(unsigned t)
1158{
1159 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1160}
1161
1162static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1163{
1164 int i;
1165
1166 if (!msr_mtrr_valid(msr))
1167 return false;
1168
1169 if (msr == MSR_IA32_CR_PAT) {
1170 for (i = 0; i < 8; i++)
1171 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1172 return false;
1173 return true;
1174 } else if (msr == MSR_MTRRdefType) {
1175 if (data & ~0xcff)
1176 return false;
1177 return valid_mtrr_type(data & 0xff);
1178 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1179 for (i = 0; i < 8 ; i++)
1180 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1181 return false;
1182 return true;
1183 }
1184
1185 /* variable MTRRs */
1186 return valid_mtrr_type(data & 0xff);
1187}
1188
9ba075a6
AK		 1189static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1190{
0bed3b56
SY		 1191 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1192
d6289b93 1193 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1194 return 1;
1195
0bed3b56
SY		 1196 if (msr == MSR_MTRRdefType) {
1197 vcpu->arch.mtrr_state.def_type = data;
1198 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1199 } else if (msr == MSR_MTRRfix64K_00000)
1200 p[0] = data;
1201 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1202 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1203 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1204 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1205 else if (msr == MSR_IA32_CR_PAT)
1206 vcpu->arch.pat = data;
1207 else { /* Variable MTRRs */
1208 int idx, is_mtrr_mask;
1209 u64 *pt;
1210
1211 idx = (msr - 0x200) / 2;
1212 is_mtrr_mask = msr - 0x200 - 2 * idx;
1213 if (!is_mtrr_mask)
1214 pt =
1215 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1216 else
1217 pt =
1218 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1219 *pt = data;
1220 }
1221
1222 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1223 return 0;
1224}
15c4a640 1225
890ca9ae 1226static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1227{
890ca9ae
HY		 1228 u64 mcg_cap = vcpu->arch.mcg_cap;
1229 unsigned bank_num = mcg_cap & 0xff;
1230
15c4a640 1231 switch (msr) {
15c4a640 1232 case MSR_IA32_MCG_STATUS:
890ca9ae 1233 vcpu->arch.mcg_status = data;
15c4a640 1234 break;
c7ac679c 1235 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1236 if (!(mcg_cap & MCG_CTL_P))
1237 return 1;
1238 if (data != 0 && data != ~(u64)0)
1239 return -1;
1240 vcpu->arch.mcg_ctl = data;
1241 break;
1242 default:
1243 if (msr >= MSR_IA32_MC0_CTL &&
1244 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1245 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1246 /* only 0 or all 1s can be written to IA32_MCi_CTL
1247 * some Linux kernels though clear bit 10 in bank 4 to
1248 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1249 * this to avoid an uncatched #GP in the guest
1250 */
890ca9ae 1251 if ((offset & 0x3) == 0 &&
114be429 1252 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1253 return -1;
1254 vcpu->arch.mce_banks[offset] = data;
1255 break;
1256 }
1257 return 1;
1258 }
1259 return 0;
1260}
1261
ffde22ac
ES		 1262static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1263{
1264 struct kvm *kvm = vcpu->kvm;
1265 int lm = is_long_mode(vcpu);
1266 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1267 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1268 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1269 : kvm->arch.xen_hvm_config.blob_size_32;
1270 u32 page_num = data & ~PAGE_MASK;
1271 u64 page_addr = data & PAGE_MASK;
1272 u8 *page;
1273 int r;
1274
1275 r = -E2BIG;
1276 if (page_num >= blob_size)
1277 goto out;
1278 r = -ENOMEM;
1279 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1280 if (!page)
1281 goto out;
1282 r = -EFAULT;
1283 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1284 goto out_free;
1285 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1286 goto out_free;
1287 r = 0;
1288out_free:
1289 kfree(page);
1290out:
1291 return r;
1292}
1293
55cd8e5a
GN		 1294static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1295{
1296 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1297}
1298
1299static bool kvm_hv_msr_partition_wide(u32 msr)
1300{
1301 bool r = false;
1302 switch (msr) {
1303 case HV_X64_MSR_GUEST_OS_ID:
1304 case HV_X64_MSR_HYPERCALL:
1305 r = true;
1306 break;
1307 }
1308
1309 return r;
1310}
1311
1312static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1313{
1314 struct kvm *kvm = vcpu->kvm;
1315
1316 switch (msr) {
1317 case HV_X64_MSR_GUEST_OS_ID:
1318 kvm->arch.hv_guest_os_id = data;
1319 /* setting guest os id to zero disables hypercall page */
1320 if (!kvm->arch.hv_guest_os_id)
1321 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1322 break;
1323 case HV_X64_MSR_HYPERCALL: {
1324 u64 gfn;
1325 unsigned long addr;
1326 u8 instructions[4];
1327
1328 /* if guest os id is not set hypercall should remain disabled */
1329 if (!kvm->arch.hv_guest_os_id)
1330 break;
1331 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1332 kvm->arch.hv_hypercall = data;
1333 break;
1334 }
1335 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1336 addr = gfn_to_hva(kvm, gfn);
1337 if (kvm_is_error_hva(addr))
1338 return 1;
1339 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1340 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1341 if (copy_to_user((void __user *)addr, instructions, 4))
1342 return 1;
1343 kvm->arch.hv_hypercall = data;
1344 break;
1345 }
1346 default:
1347 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1348 "data 0x%llx\n", msr, data);
1349 return 1;
1350 }
1351 return 0;
1352}
1353
1354static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1355{
10388a07
GN		 1356 switch (msr) {
1357 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1358 unsigned long addr;
55cd8e5a 1359
10388a07
GN		 1360 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1361 vcpu->arch.hv_vapic = data;
1362 break;
1363 }
1364 addr = gfn_to_hva(vcpu->kvm, data >>
1365 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1366 if (kvm_is_error_hva(addr))
1367 return 1;
1368 if (clear_user((void __user *)addr, PAGE_SIZE))
1369 return 1;
1370 vcpu->arch.hv_vapic = data;
1371 break;
1372 }
1373 case HV_X64_MSR_EOI:
1374 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1375 case HV_X64_MSR_ICR:
1376 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1377 case HV_X64_MSR_TPR:
1378 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1379 default:
1380 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1381 "data 0x%llx\n", msr, data);
1382 return 1;
1383 }
1384
1385 return 0;
55cd8e5a
GN		 1386}
1387
15c4a640
CO		 1388int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1389{
1390 switch (msr) {
15c4a640 1391 case MSR_EFER:
b69e8cae 1392 return set_efer(vcpu, data);
8f1589d9
AP		 1393 case MSR_K7_HWCR:
1394 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1395 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1396 if (data != 0) {
1397 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1398 data);
1399 return 1;
1400 }
15c4a640 1401 break;
f7c6d140
AP		 1402 case MSR_FAM10H_MMIO_CONF_BASE:
1403 if (data != 0) {
1404 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1405 "0x%llx\n", data);
1406 return 1;
1407 }
15c4a640 1408 break;
c323c0e5 1409 case MSR_AMD64_NB_CFG:
c7ac679c 1410 break;
b5e2fec0
AG		 1411 case MSR_IA32_DEBUGCTLMSR:
1412 if (!data) {
1413 /* We support the non-activated case already */
1414 break;
1415 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1416 /* Values other than LBR and BTF are vendor-specific,
1417 thus reserved and should throw a #GP */
1418 return 1;
1419 }
1420 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1421 __func__, data);
1422 break;
15c4a640
CO		 1423 case MSR_IA32_UCODE_REV:
1424 case MSR_IA32_UCODE_WRITE:
61a6bd67 1425 case MSR_VM_HSAVE_PA:
6098ca93 1426 case MSR_AMD64_PATCH_LOADER:
15c4a640 1427 break;
9ba075a6
AK		 1428 case 0x200 ... 0x2ff:
1429 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1430 case MSR_IA32_APICBASE:
1431 kvm_set_apic_base(vcpu, data);
1432 break;
0105d1a5
GN		 1433 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1434 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1435 case MSR_IA32_MISC_ENABLE:
ad312c7c 1436 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1437 break;
11c6bffa 1438 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1439 case MSR_KVM_WALL_CLOCK:
1440 vcpu->kvm->arch.wall_clock = data;
1441 kvm_write_wall_clock(vcpu->kvm, data);
1442 break;
11c6bffa 1443 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1444 case MSR_KVM_SYSTEM_TIME: {
1445 if (vcpu->arch.time_page) {
1446 kvm_release_page_dirty(vcpu->arch.time_page);
1447 vcpu->arch.time_page = NULL;
1448 }
1449
1450 vcpu->arch.time = data;
1451
1452 /* we verify if the enable bit is set... */
1453 if (!(data & 1))
1454 break;
1455
1456 /* ...but clean it before doing the actual write */
1457 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1458
18068523
GOC		 1459 vcpu->arch.time_page =
1460 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1461
1462 if (is_error_page(vcpu->arch.time_page)) {
1463 kvm_release_page_clean(vcpu->arch.time_page);
1464 vcpu->arch.time_page = NULL;
1465 }
1466
c8076604 1467 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1468 break;
1469 }
890ca9ae
HY		 1470 case MSR_IA32_MCG_CTL:
1471 case MSR_IA32_MCG_STATUS:
1472 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1473 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1474
1475 /* Performance counters are not protected by a CPUID bit,
1476 * so we should check all of them in the generic path for the sake of
1477 * cross vendor migration.
1478 * Writing a zero into the event select MSRs disables them,
1479 * which we perfectly emulate ;-). Any other value should be at least
1480 * reported, some guests depend on them.
1481 */
1482 case MSR_P6_EVNTSEL0:
1483 case MSR_P6_EVNTSEL1:
1484 case MSR_K7_EVNTSEL0:
1485 case MSR_K7_EVNTSEL1:
1486 case MSR_K7_EVNTSEL2:
1487 case MSR_K7_EVNTSEL3:
1488 if (data != 0)
1489 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1490 "0x%x data 0x%llx\n", msr, data);
1491 break;
1492 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1493 * so we ignore writes to make it happy.
1494 */
1495 case MSR_P6_PERFCTR0:
1496 case MSR_P6_PERFCTR1:
1497 case MSR_K7_PERFCTR0:
1498 case MSR_K7_PERFCTR1:
1499 case MSR_K7_PERFCTR2:
1500 case MSR_K7_PERFCTR3:
1501 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1502 "0x%x data 0x%llx\n", msr, data);
1503 break;
84e0cefa
JS		 1504 case MSR_K7_CLK_CTL:
1505 /*
1506 * Ignore all writes to this no longer documented MSR.
1507 * Writes are only relevant for old K7 processors,
1508 * all pre-dating SVM, but a recommended workaround from
1509 * AMD for these chips. It is possible to speicify the
1510 * affected processor models on the command line, hence
1511 * the need to ignore the workaround.
1512 */
1513 break;
55cd8e5a
GN		 1514 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1515 if (kvm_hv_msr_partition_wide(msr)) {
1516 int r;
1517 mutex_lock(&vcpu->kvm->lock);
1518 r = set_msr_hyperv_pw(vcpu, msr, data);
1519 mutex_unlock(&vcpu->kvm->lock);
1520 return r;
1521 } else
1522 return set_msr_hyperv(vcpu, msr, data);
1523 break;
15c4a640 1524 default:
ffde22ac
ES		 1525 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1526 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1527 if (!ignore_msrs) {
1528 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1529 msr, data);
1530 return 1;
1531 } else {
1532 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1533 msr, data);
1534 break;
1535 }
15c4a640
CO		 1536 }
1537 return 0;
1538}
1539EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1540
1541
1542/*
1543 * Reads an msr value (of 'msr_index') into 'pdata'.
1544 * Returns 0 on success, non-0 otherwise.
1545 * Assumes vcpu_load() was already called.
1546 */
1547int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1548{
1549 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1550}
1551
9ba075a6
AK		 1552static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1553{
0bed3b56
SY		 1554 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1555
9ba075a6
AK		 1556 if (!msr_mtrr_valid(msr))
1557 return 1;
1558
0bed3b56
SY		 1559 if (msr == MSR_MTRRdefType)
1560 *pdata = vcpu->arch.mtrr_state.def_type +
1561 (vcpu->arch.mtrr_state.enabled << 10);
1562 else if (msr == MSR_MTRRfix64K_00000)
1563 *pdata = p[0];
1564 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1565 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1566 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1567 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1568 else if (msr == MSR_IA32_CR_PAT)
1569 *pdata = vcpu->arch.pat;
1570 else { /* Variable MTRRs */
1571 int idx, is_mtrr_mask;
1572 u64 *pt;
1573
1574 idx = (msr - 0x200) / 2;
1575 is_mtrr_mask = msr - 0x200 - 2 * idx;
1576 if (!is_mtrr_mask)
1577 pt =
1578 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1579 else
1580 pt =
1581 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1582 *pdata = *pt;
1583 }
1584
9ba075a6
AK		 1585 return 0;
1586}
1587
890ca9ae 1588static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1589{
1590 u64 data;
890ca9ae
HY		 1591 u64 mcg_cap = vcpu->arch.mcg_cap;
1592 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1593
1594 switch (msr) {
15c4a640
CO		 1595 case MSR_IA32_P5_MC_ADDR:
1596 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1597 data = 0;
1598 break;
15c4a640 1599 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1600 data = vcpu->arch.mcg_cap;
1601 break;
c7ac679c 1602 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1603 if (!(mcg_cap & MCG_CTL_P))
1604 return 1;
1605 data = vcpu->arch.mcg_ctl;
1606 break;
1607 case MSR_IA32_MCG_STATUS:
1608 data = vcpu->arch.mcg_status;
1609 break;
1610 default:
1611 if (msr >= MSR_IA32_MC0_CTL &&
1612 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1613 u32 offset = msr - MSR_IA32_MC0_CTL;
1614 data = vcpu->arch.mce_banks[offset];
1615 break;
1616 }
1617 return 1;
1618 }
1619 *pdata = data;
1620 return 0;
1621}
1622
55cd8e5a
GN		 1623static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1624{
1625 u64 data = 0;
1626 struct kvm *kvm = vcpu->kvm;
1627
1628 switch (msr) {
1629 case HV_X64_MSR_GUEST_OS_ID:
1630 data = kvm->arch.hv_guest_os_id;
1631 break;
1632 case HV_X64_MSR_HYPERCALL:
1633 data = kvm->arch.hv_hypercall;
1634 break;
1635 default:
1636 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1637 return 1;
1638 }
1639
1640 *pdata = data;
1641 return 0;
1642}
1643
1644static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1645{
1646 u64 data = 0;
1647
1648 switch (msr) {
1649 case HV_X64_MSR_VP_INDEX: {
1650 int r;
1651 struct kvm_vcpu *v;
1652 kvm_for_each_vcpu(r, v, vcpu->kvm)
1653 if (v == vcpu)
1654 data = r;
1655 break;
1656 }
10388a07
GN		 1657 case HV_X64_MSR_EOI:
1658 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1659 case HV_X64_MSR_ICR:
1660 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1661 case HV_X64_MSR_TPR:
1662 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1663 default:
1664 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1665 return 1;
1666 }
1667 *pdata = data;
1668 return 0;
1669}
1670
890ca9ae
HY		 1671int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1672{
1673 u64 data;
1674
1675 switch (msr) {
890ca9ae 1676 case MSR_IA32_PLATFORM_ID:
15c4a640 1677 case MSR_IA32_UCODE_REV:
15c4a640 1678 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1679 case MSR_IA32_DEBUGCTLMSR:
1680 case MSR_IA32_LASTBRANCHFROMIP:
1681 case MSR_IA32_LASTBRANCHTOIP:
1682 case MSR_IA32_LASTINTFROMIP:
1683 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1684 case MSR_K8_SYSCFG:
1685 case MSR_K7_HWCR:
61a6bd67 1686 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1687 case MSR_P6_PERFCTR0:
1688 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1689 case MSR_P6_EVNTSEL0:
1690 case MSR_P6_EVNTSEL1:
9e699624 1691 case MSR_K7_EVNTSEL0:
1f3ee616 1692 case MSR_K7_PERFCTR0:
1fdbd48c 1693 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1694 case MSR_AMD64_NB_CFG:
f7c6d140 1695 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1696 data = 0;
1697 break;
9ba075a6
AK		 1698 case MSR_MTRRcap:
1699 data = 0x500 | KVM_NR_VAR_MTRR;
1700 break;
1701 case 0x200 ... 0x2ff:
1702 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1703 case 0xcd: /* fsb frequency */
1704 data = 3;
1705 break;
7b914098
JS		 1706 /*
1707 * MSR_EBC_FREQUENCY_ID
1708 * Conservative value valid for even the basic CPU models.
1709 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1710 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1711 * and 266MHz for model 3, or 4. Set Core Clock
1712 * Frequency to System Bus Frequency Ratio to 1 (bits
1713 * 31:24) even though these are only valid for CPU
1714 * models > 2, however guests may end up dividing or
1715 * multiplying by zero otherwise.
1716 */
1717 case MSR_EBC_FREQUENCY_ID:
1718 data = 1 << 24;
1719 break;
15c4a640
CO		 1720 case MSR_IA32_APICBASE:
1721 data = kvm_get_apic_base(vcpu);
1722 break;
0105d1a5
GN		 1723 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1724 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1725 break;
15c4a640 1726 case MSR_IA32_MISC_ENABLE:
ad312c7c 1727 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1728 break;
847f0ad8
AG		 1729 case MSR_IA32_PERF_STATUS:
1730 /* TSC increment by tick */
1731 data = 1000ULL;
1732 /* CPU multiplier */
1733 data |= (((uint64_t)4ULL) << 40);
1734 break;
15c4a640 1735 case MSR_EFER:
f6801dff 1736 data = vcpu->arch.efer;
15c4a640 1737 break;
18068523 1738 case MSR_KVM_WALL_CLOCK:
11c6bffa 1739 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1740 data = vcpu->kvm->arch.wall_clock;
1741 break;
1742 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1743 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1744 data = vcpu->arch.time;
1745 break;
890ca9ae
HY		 1746 case MSR_IA32_P5_MC_ADDR:
1747 case MSR_IA32_P5_MC_TYPE:
1748 case MSR_IA32_MCG_CAP:
1749 case MSR_IA32_MCG_CTL:
1750 case MSR_IA32_MCG_STATUS:
1751 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1752 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1753 case MSR_K7_CLK_CTL:
1754 /*
1755 * Provide expected ramp-up count for K7. All other
1756 * are set to zero, indicating minimum divisors for
1757 * every field.
1758 *
1759 * This prevents guest kernels on AMD host with CPU
1760 * type 6, model 8 and higher from exploding due to
1761 * the rdmsr failing.
1762 */
1763 data = 0x20000000;
1764 break;
55cd8e5a
GN		 1765 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1766 if (kvm_hv_msr_partition_wide(msr)) {
1767 int r;
1768 mutex_lock(&vcpu->kvm->lock);
1769 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1770 mutex_unlock(&vcpu->kvm->lock);
1771 return r;
1772 } else
1773 return get_msr_hyperv(vcpu, msr, pdata);
1774 break;
15c4a640 1775 default:
ed85c068
AP		 1776 if (!ignore_msrs) {
1777 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1778 return 1;
1779 } else {
1780 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1781 data = 0;
1782 }
1783 break;
15c4a640
CO		 1784 }
1785 *pdata = data;
1786 return 0;
1787}
1788EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1789
313a3dc7
CO		 1790/*
1791 * Read or write a bunch of msrs. All parameters are kernel addresses.
1792 *
1793 * @return number of msrs set successfully.
1794 */
1795static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1796 struct kvm_msr_entry *entries,
1797 int (*do_msr)(struct kvm_vcpu *vcpu,
1798 unsigned index, u64 *data))
1799{
f656ce01 1800 int i, idx;
313a3dc7 1801
f656ce01 1802 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1803 for (i = 0; i < msrs->nmsrs; ++i)
1804 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1805 break;
f656ce01 1806 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1807
313a3dc7
CO		 1808 return i;
1809}
1810
1811/*
1812 * Read or write a bunch of msrs. Parameters are user addresses.
1813 *
1814 * @return number of msrs set successfully.
1815 */
1816static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1817 int (*do_msr)(struct kvm_vcpu *vcpu,
1818 unsigned index, u64 *data),
1819 int writeback)
1820{
1821 struct kvm_msrs msrs;
1822 struct kvm_msr_entry *entries;
1823 int r, n;
1824 unsigned size;
1825
1826 r = -EFAULT;
1827 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1828 goto out;
1829
1830 r = -E2BIG;
1831 if (msrs.nmsrs >= MAX_IO_MSRS)
1832 goto out;
1833
1834 r = -ENOMEM;
1835 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1836 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1837 if (!entries)
1838 goto out;
1839
1840 r = -EFAULT;
1841 if (copy_from_user(entries, user_msrs->entries, size))
1842 goto out_free;
1843
1844 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1845 if (r < 0)
1846 goto out_free;
1847
1848 r = -EFAULT;
1849 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1850 goto out_free;
1851
1852 r = n;
1853
1854out_free:
7a73c028 1855 kfree(entries);
313a3dc7
CO		 1856out:
1857 return r;
1858}
1859
018d00d2
ZX		 1860int kvm_dev_ioctl_check_extension(long ext)
1861{
1862 int r;
1863
1864 switch (ext) {
1865 case KVM_CAP_IRQCHIP:
1866 case KVM_CAP_HLT:
1867 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1868 case KVM_CAP_SET_TSS_ADDR:
07716717 1869 case KVM_CAP_EXT_CPUID:
c8076604 1870 case KVM_CAP_CLOCKSOURCE:
7837699f 1871 case KVM_CAP_PIT:
a28e4f5a 1872 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1873 case KVM_CAP_MP_STATE:
ed848624 1874 case KVM_CAP_SYNC_MMU:
52d939a0 1875 case KVM_CAP_REINJECT_CONTROL:
4925663a 1876 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1877 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1878 case KVM_CAP_IRQFD:
d34e6b17 1879 case KVM_CAP_IOEVENTFD:
c5ff41ce 1880 case KVM_CAP_PIT2:
e9f42757 1881 case KVM_CAP_PIT_STATE2:
b927a3ce 1882 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1883 case KVM_CAP_XEN_HVM:
afbcf7ab 1884 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1885 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1886 case KVM_CAP_HYPERV:
10388a07 1887 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1888 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1889 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1890 case KVM_CAP_DEBUGREGS:
d2be1651 1891 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1892 case KVM_CAP_XSAVE:
018d00d2
ZX		 1893 r = 1;
1894 break;
542472b5
LV		 1895 case KVM_CAP_COALESCED_MMIO:
1896 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1897 break;
774ead3a
AK		 1898 case KVM_CAP_VAPIC:
1899 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1900 break;
f725230a
AK		 1901 case KVM_CAP_NR_VCPUS:
1902 r = KVM_MAX_VCPUS;
1903 break;
a988b910
AK		 1904 case KVM_CAP_NR_MEMSLOTS:
1905 r = KVM_MEMORY_SLOTS;
1906 break;
a68a6a72
MT		 1907 case KVM_CAP_PV_MMU: /* obsolete */
1908 r = 0;
2f333bcb 1909 break;
62c476c7 1910 case KVM_CAP_IOMMU:
19de40a8 1911 r = iommu_found();
62c476c7 1912 break;
890ca9ae
HY		 1913 case KVM_CAP_MCE:
1914 r = KVM_MAX_MCE_BANKS;
1915 break;
2d5b5a66
SY		 1916 case KVM_CAP_XCRS:
1917 r = cpu_has_xsave;
1918 break;
018d00d2
ZX		 1919 default:
1920 r = 0;
1921 break;
1922 }
1923 return r;
1924
1925}
1926
043405e1
CO		 1927long kvm_arch_dev_ioctl(struct file *filp,
1928 unsigned int ioctl, unsigned long arg)
1929{
1930 void __user *argp = (void __user *)arg;
1931 long r;
1932
1933 switch (ioctl) {
1934 case KVM_GET_MSR_INDEX_LIST: {
1935 struct kvm_msr_list __user *user_msr_list = argp;
1936 struct kvm_msr_list msr_list;
1937 unsigned n;
1938
1939 r = -EFAULT;
1940 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1941 goto out;
1942 n = msr_list.nmsrs;
1943 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1944 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1945 goto out;
1946 r = -E2BIG;
e125e7b6 1947 if (n < msr_list.nmsrs)
043405e1
CO		 1948 goto out;
1949 r = -EFAULT;
1950 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1951 num_msrs_to_save * sizeof(u32)))
1952 goto out;
e125e7b6 1953 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1954 &emulated_msrs,
1955 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1956 goto out;
1957 r = 0;
1958 break;
1959 }
674eea0f
AK		 1960 case KVM_GET_SUPPORTED_CPUID: {
1961 struct kvm_cpuid2 __user *cpuid_arg = argp;
1962 struct kvm_cpuid2 cpuid;
1963
1964 r = -EFAULT;
1965 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1966 goto out;
1967 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1968 cpuid_arg->entries);
674eea0f
AK		 1969 if (r)
1970 goto out;
1971
1972 r = -EFAULT;
1973 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1974 goto out;
1975 r = 0;
1976 break;
1977 }
890ca9ae
HY		 1978 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1979 u64 mce_cap;
1980
1981 mce_cap = KVM_MCE_CAP_SUPPORTED;
1982 r = -EFAULT;
1983 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1984 goto out;
1985 r = 0;
1986 break;
1987 }
043405e1
CO		 1988 default:
1989 r = -EINVAL;
1990 }
1991out:
1992 return r;
1993}
1994
f5f48ee1
SY		 1995static void wbinvd_ipi(void *garbage)
1996{
1997 wbinvd();
1998}
1999
2000static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2001{
2002 return vcpu->kvm->arch.iommu_domain &&
2003 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2004}
2005
313a3dc7
CO		 2006void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2007{
f5f48ee1
SY		 2008 /* Address WBINVD may be executed by guest */
2009 if (need_emulate_wbinvd(vcpu)) {
2010 if (kvm_x86_ops->has_wbinvd_exit())
2011 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2012 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2013 smp_call_function_single(vcpu->cpu,
2014 wbinvd_ipi, NULL, 1);
2015 }
2016
313a3dc7 2017 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2018 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2019 /* Make sure TSC doesn't go backwards */
2020 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2021 native_read_tsc() - vcpu->arch.last_host_tsc;
2022 if (tsc_delta < 0)
2023 mark_tsc_unstable("KVM discovered backwards TSC");
2024 if (check_tsc_unstable())
2025 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2026 kvm_migrate_timers(vcpu);
2027 vcpu->cpu = cpu;
2028 }
313a3dc7
CO		 2029}
2030
2031void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2032{
02daab21 2033 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2034 kvm_put_guest_fpu(vcpu);
e48672fa 2035 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2036}
2037
07716717 2038static int is_efer_nx(void)
313a3dc7 2039{
e286e86e 2040 unsigned long long efer = 0;
313a3dc7 2041
e286e86e 2042 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2043 return efer & EFER_NX;
2044}
2045
2046static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2047{
2048 int i;
2049 struct kvm_cpuid_entry2 *e, *entry;
2050
313a3dc7 2051 entry = NULL;
ad312c7c
ZX		 2052 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2053 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2054 if (e->function == 0x80000001) {
2055 entry = e;
2056 break;
2057 }
2058 }
07716717 2059 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2060 entry->edx &= ~(1 << 20);
2061 printk(KERN_INFO "kvm: guest NX capability removed\n");
2062 }
2063}
2064
07716717 2065/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2066static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2067 struct kvm_cpuid *cpuid,
2068 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2069{
2070 int r, i;
2071 struct kvm_cpuid_entry *cpuid_entries;
2072
2073 r = -E2BIG;
2074 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2075 goto out;
2076 r = -ENOMEM;
2077 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2078 if (!cpuid_entries)
2079 goto out;
2080 r = -EFAULT;
2081 if (copy_from_user(cpuid_entries, entries,
2082 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2083 goto out_free;
2084 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2085 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2086 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2087 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2088 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2089 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2090 vcpu->arch.cpuid_entries[i].index = 0;
2091 vcpu->arch.cpuid_entries[i].flags = 0;
2092 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2093 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2094 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2095 }
2096 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2097 cpuid_fix_nx_cap(vcpu);
2098 r = 0;
fc61b800 2099 kvm_apic_set_version(vcpu);
0e851880 2100 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2101 update_cpuid(vcpu);
07716717
DK		 2102
2103out_free:
2104 vfree(cpuid_entries);
2105out:
2106 return r;
2107}
2108
2109static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2110 struct kvm_cpuid2 *cpuid,
2111 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2112{
2113 int r;
2114
2115 r = -E2BIG;
2116 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2117 goto out;
2118 r = -EFAULT;
ad312c7c 2119 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2120 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2121 goto out;
ad312c7c 2122 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2123 kvm_apic_set_version(vcpu);
0e851880 2124 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2125 update_cpuid(vcpu);
313a3dc7
CO		 2126 return 0;
2127
2128out:
2129 return r;
2130}
2131
07716717 2132static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2133 struct kvm_cpuid2 *cpuid,
2134 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2135{
2136 int r;
2137
2138 r = -E2BIG;
ad312c7c 2139 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2140 goto out;
2141 r = -EFAULT;
ad312c7c 2142 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2143 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2144 goto out;
2145 return 0;
2146
2147out:
ad312c7c 2148 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2149 return r;
2150}
2151
07716717 2152static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2153 u32 index)
07716717
DK		 2154{
2155 entry->function = function;
2156 entry->index = index;
2157 cpuid_count(entry->function, entry->index,
19355475 2158 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2159 entry->flags = 0;
2160}
2161
7faa4ee1
AK		 2162#define F(x) bit(X86_FEATURE_##x)
2163
07716717
DK		 2164static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2165 u32 index, int *nent, int maxnent)
2166{
7faa4ee1 2167 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2168#ifdef CONFIG_X86_64
17cc3935
SY		 2169 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2170 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2171 unsigned f_lm = F(LM);
2172#else
17cc3935 2173 unsigned f_gbpages = 0;
7faa4ee1 2174 unsigned f_lm = 0;
07716717 2175#endif
4e47c7a6 2176 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2177
2178 /* cpuid 1.edx */
2179 const u32 kvm_supported_word0_x86_features =
2180 F(FPU) | F(VME) | F(DE) | F(PSE) |
2181 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2182 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2183 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2184 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2185 0 /* Reserved, DS, ACPI */ | F(MMX) |
2186 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2187 0 /* HTT, TM, Reserved, PBE */;
2188 /* cpuid 0x80000001.edx */
2189 const u32 kvm_supported_word1_x86_features =
2190 F(FPU) | F(VME) | F(DE) | F(PSE) |
2191 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2192 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2193 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2194 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2195 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2196 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2197 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2198 /* cpuid 1.ecx */
2199 const u32 kvm_supported_word4_x86_features =
6c3f6041 2200 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2201 0 /* DS-CPL, VMX, SMX, EST */ |
2202 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2203 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2204 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2205 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2206 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2207 /* cpuid 0x80000001.ecx */
07716717 2208 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2209 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1
AK		 2210 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2211 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2212 0 /* SKINIT */ | 0 /* WDT */;
07716717 2213
19355475 2214 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2215 get_cpu();
2216 do_cpuid_1_ent(entry, function, index);
2217 ++*nent;
2218
2219 switch (function) {
2220 case 0:
2acf923e 2221 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2222 break;
2223 case 1:
2224 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2225 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2226 /* we support x2apic emulation even if host does not support
2227 * it since we emulate x2apic in software */
2228 entry->ecx |= F(X2APIC);
07716717
DK		 2229 break;
2230 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2231 * may return different values. This forces us to get_cpu() before
2232 * issuing the first command, and also to emulate this annoying behavior
2233 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2234 case 2: {
2235 int t, times = entry->eax & 0xff;
2236
2237 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2238 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2239 for (t = 1; t < times && *nent < maxnent; ++t) {
2240 do_cpuid_1_ent(&entry[t], function, 0);
2241 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2242 ++*nent;
2243 }
2244 break;
2245 }
2246 /* function 4 and 0xb have additional index. */
2247 case 4: {
14af3f3c 2248 int i, cache_type;
07716717
DK		 2249
2250 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2251 /* read more entries until cache_type is zero */
14af3f3c
HH		 2252 for (i = 1; *nent < maxnent; ++i) {
2253 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2254 if (!cache_type)
2255 break;
14af3f3c
HH		 2256 do_cpuid_1_ent(&entry[i], function, i);
2257 entry[i].flags |=
07716717
DK		 2258 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2259 ++*nent;
2260 }
2261 break;
2262 }
2263 case 0xb: {
14af3f3c 2264 int i, level_type;
07716717
DK		 2265
2266 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2267 /* read more entries until level_type is zero */
14af3f3c 2268 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2269 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2270 if (!level_type)
2271 break;
14af3f3c
HH		 2272 do_cpuid_1_ent(&entry[i], function, i);
2273 entry[i].flags |=
07716717
DK		 2274 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2275 ++*nent;
2276 }
2277 break;
2278 }
2acf923e
DC		 2279 case 0xd: {
2280 int i;
2281
2282 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2283 for (i = 1; *nent < maxnent; ++i) {
2284 if (entry[i - 1].eax == 0 && i != 2)
2285 break;
2286 do_cpuid_1_ent(&entry[i], function, i);
2287 entry[i].flags |=
2288 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2289 ++*nent;
2290 }
2291 break;
2292 }
84478c82
GC		 2293 case KVM_CPUID_SIGNATURE: {
2294 char signature[12] = "KVMKVMKVM\0\0";
2295 u32 *sigptr = (u32 *)signature;
2296 entry->eax = 0;
2297 entry->ebx = sigptr[0];
2298 entry->ecx = sigptr[1];
2299 entry->edx = sigptr[2];
2300 break;
2301 }
2302 case KVM_CPUID_FEATURES:
2303 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2304 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2305 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2306 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2307 entry->ebx = 0;
2308 entry->ecx = 0;
2309 entry->edx = 0;
2310 break;
07716717
DK		 2311 case 0x80000000:
2312 entry->eax = min(entry->eax, 0x8000001a);
2313 break;
2314 case 0x80000001:
2315 entry->edx &= kvm_supported_word1_x86_features;
2316 entry->ecx &= kvm_supported_word6_x86_features;
2317 break;
2318 }
d4330ef2
JR		 2319
2320 kvm_x86_ops->set_supported_cpuid(function, entry);
2321
07716717
DK		 2322 put_cpu();
2323}
2324
7faa4ee1
AK		 2325#undef F
2326
674eea0f 2327static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2328 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2329{
2330 struct kvm_cpuid_entry2 *cpuid_entries;
2331 int limit, nent = 0, r = -E2BIG;
2332 u32 func;
2333
2334 if (cpuid->nent < 1)
2335 goto out;
6a544355
AK		 2336 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2337 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2338 r = -ENOMEM;
2339 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2340 if (!cpuid_entries)
2341 goto out;
2342
2343 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2344 limit = cpuid_entries[0].eax;
2345 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2346 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2347 &nent, cpuid->nent);
07716717
DK		 2348 r = -E2BIG;
2349 if (nent >= cpuid->nent)
2350 goto out_free;
2351
2352 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2353 limit = cpuid_entries[nent - 1].eax;
2354 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2355 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2356 &nent, cpuid->nent);
84478c82
GC		 2357
2358
2359
2360 r = -E2BIG;
2361 if (nent >= cpuid->nent)
2362 goto out_free;
2363
2364 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2365 cpuid->nent);
2366
2367 r = -E2BIG;
2368 if (nent >= cpuid->nent)
2369 goto out_free;
2370
2371 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2372 cpuid->nent);
2373
cb007648
MM		 2374 r = -E2BIG;
2375 if (nent >= cpuid->nent)
2376 goto out_free;
2377
07716717
DK		 2378 r = -EFAULT;
2379 if (copy_to_user(entries, cpuid_entries,
19355475 2380 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2381 goto out_free;
2382 cpuid->nent = nent;
2383 r = 0;
2384
2385out_free:
2386 vfree(cpuid_entries);
2387out:
2388 return r;
2389}
2390
313a3dc7
CO		 2391static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2392 struct kvm_lapic_state *s)
2393{
ad312c7c 2394 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2395
2396 return 0;
2397}
2398
2399static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2400 struct kvm_lapic_state *s)
2401{
ad312c7c 2402 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2403 kvm_apic_post_state_restore(vcpu);
cb142eb7 2404 update_cr8_intercept(vcpu);
313a3dc7
CO		 2405
2406 return 0;
2407}
2408
f77bc6a4
ZX		 2409static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2410 struct kvm_interrupt *irq)
2411{
2412 if (irq->irq < 0 || irq->irq >= 256)
2413 return -EINVAL;
2414 if (irqchip_in_kernel(vcpu->kvm))
2415 return -ENXIO;
f77bc6a4 2416
66fd3f7f 2417 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2418 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2419
f77bc6a4
ZX		 2420 return 0;
2421}
2422
c4abb7c9
JK		 2423static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2424{
c4abb7c9 2425 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2426
2427 return 0;
2428}
2429
b209749f
AK		 2430static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2431 struct kvm_tpr_access_ctl *tac)
2432{
2433 if (tac->flags)
2434 return -EINVAL;
2435 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2436 return 0;
2437}
2438
890ca9ae
HY		 2439static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2440 u64 mcg_cap)
2441{
2442 int r;
2443 unsigned bank_num = mcg_cap & 0xff, bank;
2444
2445 r = -EINVAL;
a9e38c3e 2446 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2447 goto out;
2448 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2449 goto out;
2450 r = 0;
2451 vcpu->arch.mcg_cap = mcg_cap;
2452 /* Init IA32_MCG_CTL to all 1s */
2453 if (mcg_cap & MCG_CTL_P)
2454 vcpu->arch.mcg_ctl = ~(u64)0;
2455 /* Init IA32_MCi_CTL to all 1s */
2456 for (bank = 0; bank < bank_num; bank++)
2457 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2458out:
2459 return r;
2460}
2461
2462static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2463 struct kvm_x86_mce *mce)
2464{
2465 u64 mcg_cap = vcpu->arch.mcg_cap;
2466 unsigned bank_num = mcg_cap & 0xff;
2467 u64 *banks = vcpu->arch.mce_banks;
2468
2469 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2470 return -EINVAL;
2471 /*
2472 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2473 * reporting is disabled
2474 */
2475 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2476 vcpu->arch.mcg_ctl != ~(u64)0)
2477 return 0;
2478 banks += 4 * mce->bank;
2479 /*
2480 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2481 * reporting is disabled for the bank
2482 */
2483 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2484 return 0;
2485 if (mce->status & MCI_STATUS_UC) {
2486 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2487 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2488 printk(KERN_DEBUG "kvm: set_mce: "
2489 "injects mce exception while "
2490 "previous one is in progress!\n");
a8eeb04a 2491 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2492 return 0;
2493 }
2494 if (banks[1] & MCI_STATUS_VAL)
2495 mce->status |= MCI_STATUS_OVER;
2496 banks[2] = mce->addr;
2497 banks[3] = mce->misc;
2498 vcpu->arch.mcg_status = mce->mcg_status;
2499 banks[1] = mce->status;
2500 kvm_queue_exception(vcpu, MC_VECTOR);
2501 } else if (!(banks[1] & MCI_STATUS_VAL)
2502 || !(banks[1] & MCI_STATUS_UC)) {
2503 if (banks[1] & MCI_STATUS_VAL)
2504 mce->status |= MCI_STATUS_OVER;
2505 banks[2] = mce->addr;
2506 banks[3] = mce->misc;
2507 banks[1] = mce->status;
2508 } else
2509 banks[1] |= MCI_STATUS_OVER;
2510 return 0;
2511}
2512
3cfc3092
JK		 2513static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2514 struct kvm_vcpu_events *events)
2515{
03b82a30
JK		 2516 events->exception.injected =
2517 vcpu->arch.exception.pending &&
2518 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2519 events->exception.nr = vcpu->arch.exception.nr;
2520 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2521 events->exception.error_code = vcpu->arch.exception.error_code;
2522
03b82a30
JK		 2523 events->interrupt.injected =
2524 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2525 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2526 events->interrupt.soft = 0;
48005f64
JK		 2527 events->interrupt.shadow =
2528 kvm_x86_ops->get_interrupt_shadow(vcpu,
2529 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2530
2531 events->nmi.injected = vcpu->arch.nmi_injected;
2532 events->nmi.pending = vcpu->arch.nmi_pending;
2533 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2534
2535 events->sipi_vector = vcpu->arch.sipi_vector;
2536
dab4b911 2537 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2538 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2539 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2540}
2541
2542static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2543 struct kvm_vcpu_events *events)
2544{
dab4b911 2545 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2546 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2547 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2548 return -EINVAL;
2549
3cfc3092
JK		 2550 vcpu->arch.exception.pending = events->exception.injected;
2551 vcpu->arch.exception.nr = events->exception.nr;
2552 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2553 vcpu->arch.exception.error_code = events->exception.error_code;
2554
2555 vcpu->arch.interrupt.pending = events->interrupt.injected;
2556 vcpu->arch.interrupt.nr = events->interrupt.nr;
2557 vcpu->arch.interrupt.soft = events->interrupt.soft;
2558 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2559 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2560 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2561 kvm_x86_ops->set_interrupt_shadow(vcpu,
2562 events->interrupt.shadow);
3cfc3092
JK		 2563
2564 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2565 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2566 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2567 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2568
dab4b911
JK		 2569 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2570 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2571
3842d135
AK		 2572 kvm_make_request(KVM_REQ_EVENT, vcpu);
2573
3cfc3092
JK		 2574 return 0;
2575}
2576
a1efbe77
JK		 2577static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2578 struct kvm_debugregs *dbgregs)
2579{
a1efbe77
JK		 2580 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2581 dbgregs->dr6 = vcpu->arch.dr6;
2582 dbgregs->dr7 = vcpu->arch.dr7;
2583 dbgregs->flags = 0;
a1efbe77
JK		 2584}
2585
2586static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2587 struct kvm_debugregs *dbgregs)
2588{
2589 if (dbgregs->flags)
2590 return -EINVAL;
2591
a1efbe77
JK		 2592 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2593 vcpu->arch.dr6 = dbgregs->dr6;
2594 vcpu->arch.dr7 = dbgregs->dr7;
2595
a1efbe77
JK		 2596 return 0;
2597}
2598
2d5b5a66
SY		 2599static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2600 struct kvm_xsave *guest_xsave)
2601{
2602 if (cpu_has_xsave)
2603 memcpy(guest_xsave->region,
2604 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2605 xstate_size);
2d5b5a66
SY		 2606 else {
2607 memcpy(guest_xsave->region,
2608 &vcpu->arch.guest_fpu.state->fxsave,
2609 sizeof(struct i387_fxsave_struct));
2610 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2611 XSTATE_FPSSE;
2612 }
2613}
2614
2615static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2616 struct kvm_xsave *guest_xsave)
2617{
2618 u64 xstate_bv =
2619 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2620
2621 if (cpu_has_xsave)
2622 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2623 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2624 else {
2625 if (xstate_bv & ~XSTATE_FPSSE)
2626 return -EINVAL;
2627 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2628 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2629 }
2630 return 0;
2631}
2632
2633static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2634 struct kvm_xcrs *guest_xcrs)
2635{
2636 if (!cpu_has_xsave) {
2637 guest_xcrs->nr_xcrs = 0;
2638 return;
2639 }
2640
2641 guest_xcrs->nr_xcrs = 1;
2642 guest_xcrs->flags = 0;
2643 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2644 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2645}
2646
2647static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2648 struct kvm_xcrs *guest_xcrs)
2649{
2650 int i, r = 0;
2651
2652 if (!cpu_has_xsave)
2653 return -EINVAL;
2654
2655 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2656 return -EINVAL;
2657
2658 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2659 /* Only support XCR0 currently */
2660 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2661 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2662 guest_xcrs->xcrs[0].value);
2663 break;
2664 }
2665 if (r)
2666 r = -EINVAL;
2667 return r;
2668}
2669
313a3dc7
CO		 2670long kvm_arch_vcpu_ioctl(struct file *filp,
2671 unsigned int ioctl, unsigned long arg)
2672{
2673 struct kvm_vcpu *vcpu = filp->private_data;
2674 void __user *argp = (void __user *)arg;
2675 int r;
d1ac91d8
AK		 2676 union {
2677 struct kvm_lapic_state *lapic;
2678 struct kvm_xsave *xsave;
2679 struct kvm_xcrs *xcrs;
2680 void *buffer;
2681 } u;
2682
2683 u.buffer = NULL;
313a3dc7
CO		 2684 switch (ioctl) {
2685 case KVM_GET_LAPIC: {
2204ae3c
MT		 2686 r = -EINVAL;
2687 if (!vcpu->arch.apic)
2688 goto out;
d1ac91d8 2689 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2690
b772ff36 2691 r = -ENOMEM;
d1ac91d8 2692 if (!u.lapic)
b772ff36 2693 goto out;
d1ac91d8 2694 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2695 if (r)
2696 goto out;
2697 r = -EFAULT;
d1ac91d8 2698 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2699 goto out;
2700 r = 0;
2701 break;
2702 }
2703 case KVM_SET_LAPIC: {
2204ae3c
MT		 2704 r = -EINVAL;
2705 if (!vcpu->arch.apic)
2706 goto out;
d1ac91d8 2707 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2708 r = -ENOMEM;
d1ac91d8 2709 if (!u.lapic)
b772ff36 2710 goto out;
313a3dc7 2711 r = -EFAULT;
d1ac91d8 2712 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2713 goto out;
d1ac91d8 2714 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2715 if (r)
2716 goto out;
2717 r = 0;
2718 break;
2719 }
f77bc6a4
ZX		 2720 case KVM_INTERRUPT: {
2721 struct kvm_interrupt irq;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&irq, argp, sizeof irq))
2725 goto out;
2726 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2727 if (r)
2728 goto out;
2729 r = 0;
2730 break;
2731 }
c4abb7c9
JK		 2732 case KVM_NMI: {
2733 r = kvm_vcpu_ioctl_nmi(vcpu);
2734 if (r)
2735 goto out;
2736 r = 0;
2737 break;
2738 }
313a3dc7
CO		 2739 case KVM_SET_CPUID: {
2740 struct kvm_cpuid __user *cpuid_arg = argp;
2741 struct kvm_cpuid cpuid;
2742
2743 r = -EFAULT;
2744 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2745 goto out;
2746 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2747 if (r)
2748 goto out;
2749 break;
2750 }
07716717
DK		 2751 case KVM_SET_CPUID2: {
2752 struct kvm_cpuid2 __user *cpuid_arg = argp;
2753 struct kvm_cpuid2 cpuid;
2754
2755 r = -EFAULT;
2756 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2757 goto out;
2758 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2759 cpuid_arg->entries);
07716717
DK		 2760 if (r)
2761 goto out;
2762 break;
2763 }
2764 case KVM_GET_CPUID2: {
2765 struct kvm_cpuid2 __user *cpuid_arg = argp;
2766 struct kvm_cpuid2 cpuid;
2767
2768 r = -EFAULT;
2769 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2770 goto out;
2771 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2772 cpuid_arg->entries);
07716717
DK		 2773 if (r)
2774 goto out;
2775 r = -EFAULT;
2776 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2777 goto out;
2778 r = 0;
2779 break;
2780 }
313a3dc7
CO		 2781 case KVM_GET_MSRS:
2782 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2783 break;
2784 case KVM_SET_MSRS:
2785 r = msr_io(vcpu, argp, do_set_msr, 0);
2786 break;
b209749f
AK		 2787 case KVM_TPR_ACCESS_REPORTING: {
2788 struct kvm_tpr_access_ctl tac;
2789
2790 r = -EFAULT;
2791 if (copy_from_user(&tac, argp, sizeof tac))
2792 goto out;
2793 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2794 if (r)
2795 goto out;
2796 r = -EFAULT;
2797 if (copy_to_user(argp, &tac, sizeof tac))
2798 goto out;
2799 r = 0;
2800 break;
2801 };
b93463aa
AK		 2802 case KVM_SET_VAPIC_ADDR: {
2803 struct kvm_vapic_addr va;
2804
2805 r = -EINVAL;
2806 if (!irqchip_in_kernel(vcpu->kvm))
2807 goto out;
2808 r = -EFAULT;
2809 if (copy_from_user(&va, argp, sizeof va))
2810 goto out;
2811 r = 0;
2812 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2813 break;
2814 }
890ca9ae
HY		 2815 case KVM_X86_SETUP_MCE: {
2816 u64 mcg_cap;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2820 goto out;
2821 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2822 break;
2823 }
2824 case KVM_X86_SET_MCE: {
2825 struct kvm_x86_mce mce;
2826
2827 r = -EFAULT;
2828 if (copy_from_user(&mce, argp, sizeof mce))
2829 goto out;
2830 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2831 break;
2832 }
3cfc3092
JK		 2833 case KVM_GET_VCPU_EVENTS: {
2834 struct kvm_vcpu_events events;
2835
2836 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2837
2838 r = -EFAULT;
2839 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2840 break;
2841 r = 0;
2842 break;
2843 }
2844 case KVM_SET_VCPU_EVENTS: {
2845 struct kvm_vcpu_events events;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2849 break;
2850
2851 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2852 break;
2853 }
a1efbe77
JK		 2854 case KVM_GET_DEBUGREGS: {
2855 struct kvm_debugregs dbgregs;
2856
2857 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2858
2859 r = -EFAULT;
2860 if (copy_to_user(argp, &dbgregs,
2861 sizeof(struct kvm_debugregs)))
2862 break;
2863 r = 0;
2864 break;
2865 }
2866 case KVM_SET_DEBUGREGS: {
2867 struct kvm_debugregs dbgregs;
2868
2869 r = -EFAULT;
2870 if (copy_from_user(&dbgregs, argp,
2871 sizeof(struct kvm_debugregs)))
2872 break;
2873
2874 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2875 break;
2876 }
2d5b5a66 2877 case KVM_GET_XSAVE: {
d1ac91d8 2878 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2879 r = -ENOMEM;
d1ac91d8 2880 if (!u.xsave)
2d5b5a66
SY		 2881 break;
2882
d1ac91d8 2883 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2884
2885 r = -EFAULT;
d1ac91d8 2886 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2887 break;
2888 r = 0;
2889 break;
2890 }
2891 case KVM_SET_XSAVE: {
d1ac91d8 2892 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2893 r = -ENOMEM;
d1ac91d8 2894 if (!u.xsave)
2d5b5a66
SY		 2895 break;
2896
2897 r = -EFAULT;
d1ac91d8 2898 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2899 break;
2900
d1ac91d8 2901 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2902 break;
2903 }
2904 case KVM_GET_XCRS: {
d1ac91d8 2905 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2906 r = -ENOMEM;
d1ac91d8 2907 if (!u.xcrs)
2d5b5a66
SY		 2908 break;
2909
d1ac91d8 2910 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2911
2912 r = -EFAULT;
d1ac91d8 2913 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2914 sizeof(struct kvm_xcrs)))
2915 break;
2916 r = 0;
2917 break;
2918 }
2919 case KVM_SET_XCRS: {
d1ac91d8 2920 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2921 r = -ENOMEM;
d1ac91d8 2922 if (!u.xcrs)
2d5b5a66
SY		 2923 break;
2924
2925 r = -EFAULT;
d1ac91d8 2926 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2927 sizeof(struct kvm_xcrs)))
2928 break;
2929
d1ac91d8 2930 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2931 break;
2932 }
313a3dc7
CO		 2933 default:
2934 r = -EINVAL;
2935 }
2936out:
d1ac91d8 2937 kfree(u.buffer);
313a3dc7
CO		 2938 return r;
2939}
2940
1fe779f8
CO		 2941static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2942{
2943 int ret;
2944
2945 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2946 return -1;
2947 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2948 return ret;
2949}
2950
b927a3ce
SY		 2951static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2952 u64 ident_addr)
2953{
2954 kvm->arch.ept_identity_map_addr = ident_addr;
2955 return 0;
2956}
2957
1fe779f8
CO		 2958static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2959 u32 kvm_nr_mmu_pages)
2960{
2961 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2962 return -EINVAL;
2963
79fac95e 2964 mutex_lock(&kvm->slots_lock);
7c8a83b7 2965 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2966
2967 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2968 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2969
7c8a83b7 2970 spin_unlock(&kvm->mmu_lock);
79fac95e 2971 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2972 return 0;
2973}
2974
2975static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2976{
39de71ec 2977 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2978}
2979
1fe779f8
CO		 2980static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2981{
2982 int r;
2983
2984 r = 0;
2985 switch (chip->chip_id) {
2986 case KVM_IRQCHIP_PIC_MASTER:
2987 memcpy(&chip->chip.pic,
2988 &pic_irqchip(kvm)->pics[0],
2989 sizeof(struct kvm_pic_state));
2990 break;
2991 case KVM_IRQCHIP_PIC_SLAVE:
2992 memcpy(&chip->chip.pic,
2993 &pic_irqchip(kvm)->pics[1],
2994 sizeof(struct kvm_pic_state));
2995 break;
2996 case KVM_IRQCHIP_IOAPIC:
eba0226b 2997 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2998 break;
2999 default:
3000 r = -EINVAL;
3001 break;
3002 }
3003 return r;
3004}
3005
3006static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3007{
3008 int r;
3009
3010 r = 0;
3011 switch (chip->chip_id) {
3012 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 3013 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3014 memcpy(&pic_irqchip(kvm)->pics[0],
3015 &chip->chip.pic,
3016 sizeof(struct kvm_pic_state));
fa8273e9 3017 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3018 break;
3019 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 3020 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3021 memcpy(&pic_irqchip(kvm)->pics[1],
3022 &chip->chip.pic,
3023 sizeof(struct kvm_pic_state));
fa8273e9 3024 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3025 break;
3026 case KVM_IRQCHIP_IOAPIC:
eba0226b 3027 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3028 break;
3029 default:
3030 r = -EINVAL;
3031 break;
3032 }
3033 kvm_pic_update_irq(pic_irqchip(kvm));
3034 return r;
3035}
3036
e0f63cb9
SY		 3037static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3038{
3039 int r = 0;
3040
894a9c55 3041 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3042 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3043 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3044 return r;
3045}
3046
3047static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3048{
3049 int r = 0;
3050
894a9c55 3051 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3052 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3053 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3055 return r;
3056}
3057
3058static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3059{
3060 int r = 0;
3061
3062 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3063 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3064 sizeof(ps->channels));
3065 ps->flags = kvm->arch.vpit->pit_state.flags;
3066 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3067 return r;
3068}
3069
3070static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3071{
3072 int r = 0, start = 0;
3073 u32 prev_legacy, cur_legacy;
3074 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3075 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3076 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3077 if (!prev_legacy && cur_legacy)
3078 start = 1;
3079 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3080 sizeof(kvm->arch.vpit->pit_state.channels));
3081 kvm->arch.vpit->pit_state.flags = ps->flags;
3082 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3083 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3084 return r;
3085}
3086
52d939a0
MT		 3087static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3088 struct kvm_reinject_control *control)
3089{
3090 if (!kvm->arch.vpit)
3091 return -ENXIO;
894a9c55 3092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3093 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3094 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3095 return 0;
3096}
3097
5bb064dc
ZX		 3098/*
3099 * Get (and clear) the dirty memory log for a memory slot.
3100 */
3101int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3102 struct kvm_dirty_log *log)
3103{
87bf6e7d 3104 int r, i;
5bb064dc 3105 struct kvm_memory_slot *memslot;
87bf6e7d 3106 unsigned long n;
b050b015 3107 unsigned long is_dirty = 0;
5bb064dc 3108
79fac95e 3109 mutex_lock(&kvm->slots_lock);
5bb064dc 3110
b050b015
MT		 3111 r = -EINVAL;
3112 if (log->slot >= KVM_MEMORY_SLOTS)
3113 goto out;
3114
3115 memslot = &kvm->memslots->memslots[log->slot];
3116 r = -ENOENT;
3117 if (!memslot->dirty_bitmap)
3118 goto out;
3119
87bf6e7d 3120 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3121
b050b015
MT		 3122 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3123 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3124
3125 /* If nothing is dirty, don't bother messing with page tables. */
3126 if (is_dirty) {
b050b015 3127 struct kvm_memslots *slots, *old_slots;
914ebccd 3128 unsigned long *dirty_bitmap;
b050b015 3129
7c8a83b7 3130 spin_lock(&kvm->mmu_lock);
5bb064dc 3131 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3132 spin_unlock(&kvm->mmu_lock);
b050b015 3133
914ebccd
TY		 3134 r = -ENOMEM;
3135 dirty_bitmap = vmalloc(n);
3136 if (!dirty_bitmap)
3137 goto out;
3138 memset(dirty_bitmap, 0, n);
b050b015 3139
914ebccd
TY		 3140 r = -ENOMEM;
3141 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3142 if (!slots) {
3143 vfree(dirty_bitmap);
3144 goto out;
3145 }
b050b015
MT		 3146 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3147 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3148
3149 old_slots = kvm->memslots;
3150 rcu_assign_pointer(kvm->memslots, slots);
3151 synchronize_srcu_expedited(&kvm->srcu);
3152 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3153 kfree(old_slots);
914ebccd
TY		 3154
3155 r = -EFAULT;
3156 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3157 vfree(dirty_bitmap);
3158 goto out;
3159 }
3160 vfree(dirty_bitmap);
3161 } else {
3162 r = -EFAULT;
3163 if (clear_user(log->dirty_bitmap, n))
3164 goto out;
5bb064dc 3165 }
b050b015 3166
5bb064dc
ZX		 3167 r = 0;
3168out:
79fac95e 3169 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3170 return r;
3171}
3172
1fe779f8
CO		 3173long kvm_arch_vm_ioctl(struct file *filp,
3174 unsigned int ioctl, unsigned long arg)
3175{
3176 struct kvm *kvm = filp->private_data;
3177 void __user *argp = (void __user *)arg;
367e1319 3178 int r = -ENOTTY;
f0d66275
DH		 3179 /*
3180 * This union makes it completely explicit to gcc-3.x
3181 * that these two variables' stack usage should be
3182 * combined, not added together.
3183 */
3184 union {
3185 struct kvm_pit_state ps;
e9f42757 3186 struct kvm_pit_state2 ps2;
c5ff41ce 3187 struct kvm_pit_config pit_config;
f0d66275 3188 } u;
1fe779f8
CO		 3189
3190 switch (ioctl) {
3191 case KVM_SET_TSS_ADDR:
3192 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3193 if (r < 0)
3194 goto out;
3195 break;
b927a3ce
SY		 3196 case KVM_SET_IDENTITY_MAP_ADDR: {
3197 u64 ident_addr;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3201 goto out;
3202 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3203 if (r < 0)
3204 goto out;
3205 break;
3206 }
1fe779f8
CO		 3207 case KVM_SET_NR_MMU_PAGES:
3208 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3209 if (r)
3210 goto out;
3211 break;
3212 case KVM_GET_NR_MMU_PAGES:
3213 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3214 break;
3ddea128
MT		 3215 case KVM_CREATE_IRQCHIP: {
3216 struct kvm_pic *vpic;
3217
3218 mutex_lock(&kvm->lock);
3219 r = -EEXIST;
3220 if (kvm->arch.vpic)
3221 goto create_irqchip_unlock;
1fe779f8 3222 r = -ENOMEM;
3ddea128
MT		 3223 vpic = kvm_create_pic(kvm);
3224 if (vpic) {
1fe779f8
CO		 3225 r = kvm_ioapic_init(kvm);
3226 if (r) {
72bb2fcd
WY		 3227 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3228 &vpic->dev);
3ddea128
MT		 3229 kfree(vpic);
3230 goto create_irqchip_unlock;
1fe779f8
CO		 3231 }
3232 } else
3ddea128
MT		 3233 goto create_irqchip_unlock;
3234 smp_wmb();
3235 kvm->arch.vpic = vpic;
3236 smp_wmb();
399ec807
AK		 3237 r = kvm_setup_default_irq_routing(kvm);
3238 if (r) {
3ddea128 3239 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3240 kvm_ioapic_destroy(kvm);
3241 kvm_destroy_pic(kvm);
3ddea128 3242 mutex_unlock(&kvm->irq_lock);
399ec807 3243 }
3ddea128
MT		 3244 create_irqchip_unlock:
3245 mutex_unlock(&kvm->lock);
1fe779f8 3246 break;
3ddea128 3247 }
7837699f 3248 case KVM_CREATE_PIT:
c5ff41ce
JK		 3249 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3250 goto create_pit;
3251 case KVM_CREATE_PIT2:
3252 r = -EFAULT;
3253 if (copy_from_user(&u.pit_config, argp,
3254 sizeof(struct kvm_pit_config)))
3255 goto out;
3256 create_pit:
79fac95e 3257 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3258 r = -EEXIST;
3259 if (kvm->arch.vpit)
3260 goto create_pit_unlock;
7837699f 3261 r = -ENOMEM;
c5ff41ce 3262 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3263 if (kvm->arch.vpit)
3264 r = 0;
269e05e4 3265 create_pit_unlock:
79fac95e 3266 mutex_unlock(&kvm->slots_lock);
7837699f 3267 break;
4925663a 3268 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3269 case KVM_IRQ_LINE: {
3270 struct kvm_irq_level irq_event;
3271
3272 r = -EFAULT;
3273 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3274 goto out;
160d2f6c 3275 r = -ENXIO;
1fe779f8 3276 if (irqchip_in_kernel(kvm)) {
4925663a 3277 __s32 status;
4925663a
GN		 3278 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3279 irq_event.irq, irq_event.level);
4925663a 3280 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3281 r = -EFAULT;
4925663a
GN		 3282 irq_event.status = status;
3283 if (copy_to_user(argp, &irq_event,
3284 sizeof irq_event))
3285 goto out;
3286 }
1fe779f8
CO		 3287 r = 0;
3288 }
3289 break;
3290 }
3291 case KVM_GET_IRQCHIP: {
3292 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3293 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3294
f0d66275
DH		 3295 r = -ENOMEM;
3296 if (!chip)
1fe779f8 3297 goto out;
f0d66275
DH		 3298 r = -EFAULT;
3299 if (copy_from_user(chip, argp, sizeof *chip))
3300 goto get_irqchip_out;
1fe779f8
CO		 3301 r = -ENXIO;
3302 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3303 goto get_irqchip_out;
3304 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3305 if (r)
f0d66275 3306 goto get_irqchip_out;
1fe779f8 3307 r = -EFAULT;
f0d66275
DH		 3308 if (copy_to_user(argp, chip, sizeof *chip))
3309 goto get_irqchip_out;
1fe779f8 3310 r = 0;
f0d66275
DH		 3311 get_irqchip_out:
3312 kfree(chip);
3313 if (r)
3314 goto out;
1fe779f8
CO		 3315 break;
3316 }
3317 case KVM_SET_IRQCHIP: {
3318 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3319 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3320
f0d66275
DH		 3321 r = -ENOMEM;
3322 if (!chip)
1fe779f8 3323 goto out;
f0d66275
DH		 3324 r = -EFAULT;
3325 if (copy_from_user(chip, argp, sizeof *chip))
3326 goto set_irqchip_out;
1fe779f8
CO		 3327 r = -ENXIO;
3328 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3329 goto set_irqchip_out;
3330 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3331 if (r)
f0d66275 3332 goto set_irqchip_out;
1fe779f8 3333 r = 0;
f0d66275
DH		 3334 set_irqchip_out:
3335 kfree(chip);
3336 if (r)
3337 goto out;
1fe779f8
CO		 3338 break;
3339 }
e0f63cb9 3340 case KVM_GET_PIT: {
e0f63cb9 3341 r = -EFAULT;
f0d66275 3342 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3343 goto out;
3344 r = -ENXIO;
3345 if (!kvm->arch.vpit)
3346 goto out;
f0d66275 3347 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3348 if (r)
3349 goto out;
3350 r = -EFAULT;
f0d66275 3351 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3352 goto out;
3353 r = 0;
3354 break;
3355 }
3356 case KVM_SET_PIT: {
e0f63cb9 3357 r = -EFAULT;
f0d66275 3358 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3359 goto out;
3360 r = -ENXIO;
3361 if (!kvm->arch.vpit)
3362 goto out;
f0d66275 3363 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3364 if (r)
3365 goto out;
3366 r = 0;
3367 break;
3368 }
e9f42757
BK		 3369 case KVM_GET_PIT2: {
3370 r = -ENXIO;
3371 if (!kvm->arch.vpit)
3372 goto out;
3373 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3374 if (r)
3375 goto out;
3376 r = -EFAULT;
3377 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3378 goto out;
3379 r = 0;
3380 break;
3381 }
3382 case KVM_SET_PIT2: {
3383 r = -EFAULT;
3384 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3385 goto out;
3386 r = -ENXIO;
3387 if (!kvm->arch.vpit)
3388 goto out;
3389 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3390 if (r)
3391 goto out;
3392 r = 0;
3393 break;
3394 }
52d939a0
MT		 3395 case KVM_REINJECT_CONTROL: {
3396 struct kvm_reinject_control control;
3397 r = -EFAULT;
3398 if (copy_from_user(&control, argp, sizeof(control)))
3399 goto out;
3400 r = kvm_vm_ioctl_reinject(kvm, &control);
3401 if (r)
3402 goto out;
3403 r = 0;
3404 break;
3405 }
ffde22ac
ES		 3406 case KVM_XEN_HVM_CONFIG: {
3407 r = -EFAULT;
3408 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3409 sizeof(struct kvm_xen_hvm_config)))
3410 goto out;
3411 r = -EINVAL;
3412 if (kvm->arch.xen_hvm_config.flags)
3413 goto out;
3414 r = 0;
3415 break;
3416 }
afbcf7ab 3417 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3418 struct kvm_clock_data user_ns;
3419 u64 now_ns;
3420 s64 delta;
3421
3422 r = -EFAULT;
3423 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3424 goto out;
3425
3426 r = -EINVAL;
3427 if (user_ns.flags)
3428 goto out;
3429
3430 r = 0;
759379dd 3431 now_ns = get_kernel_ns();
afbcf7ab
GC		 3432 delta = user_ns.clock - now_ns;
3433 kvm->arch.kvmclock_offset = delta;
3434 break;
3435 }
3436 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3437 struct kvm_clock_data user_ns;
3438 u64 now_ns;
3439
759379dd 3440 now_ns = get_kernel_ns();
afbcf7ab
GC		 3441 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3442 user_ns.flags = 0;
3443
3444 r = -EFAULT;
3445 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3446 goto out;
3447 r = 0;
3448 break;
3449 }
3450
1fe779f8
CO		 3451 default:
3452 ;
3453 }
3454out:
3455 return r;
3456}
3457
a16b043c 3458static void kvm_init_msr_list(void)
043405e1
CO		 3459{
3460 u32 dummy[2];
3461 unsigned i, j;
3462
e3267cbb
GC		 3463 /* skip the first msrs in the list. KVM-specific */
3464 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3465 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3466 continue;
3467 if (j < i)
3468 msrs_to_save[j] = msrs_to_save[i];
3469 j++;
3470 }
3471 num_msrs_to_save = j;
3472}
3473
bda9020e
MT		 3474static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3475 const void *v)
bbd9b64e 3476{
bda9020e
MT		 3477 if (vcpu->arch.apic &&
3478 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3479 return 0;
bbd9b64e 3480
e93f8a0f 3481 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3482}
3483
bda9020e 3484static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3485{
bda9020e
MT		 3486 if (vcpu->arch.apic &&
3487 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3488 return 0;
bbd9b64e 3489
e93f8a0f 3490 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3491}
3492
2dafc6c2
GN		 3493static void kvm_set_segment(struct kvm_vcpu *vcpu,
3494 struct kvm_segment *var, int seg)
3495{
3496 kvm_x86_ops->set_segment(vcpu, var, seg);
3497}
3498
3499void kvm_get_segment(struct kvm_vcpu *vcpu,
3500 struct kvm_segment *var, int seg)
3501{
3502 kvm_x86_ops->get_segment(vcpu, var, seg);
3503}
3504
c30a358d
JR		 3505static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3506{
3507 return gpa;
3508}
3509
02f59dc9
JR		 3510static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3511{
3512 gpa_t t_gpa;
3513 u32 error;
3514
3515 BUG_ON(!mmu_is_nested(vcpu));
3516
3517 /* NPT walks are always user-walks */
3518 access |= PFERR_USER_MASK;
3519 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3520 if (t_gpa == UNMAPPED_GVA)
0959ffac 3521 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3522
3523 return t_gpa;
3524}
3525
1871c602
GN		 3526gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3527{
3528 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3529 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3530}
3531
3532 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3533{
3534 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3535 access |= PFERR_FETCH_MASK;
14dfe855 3536 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3537}
3538
3539gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3540{
3541 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3542 access |= PFERR_WRITE_MASK;
14dfe855 3543 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3544}
3545
3546/* uses this to access any guest's mapped memory without checking CPL */
3547gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3548{
14dfe855 3549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3550}
3551
3552static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3553 struct kvm_vcpu *vcpu, u32 access,
3554 u32 *error)
bbd9b64e
CO		 3555{
3556 void *data = val;
10589a46 3557 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3558
3559 while (bytes) {
14dfe855
JR		 3560 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3561 error);
bbd9b64e 3562 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3563 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3564 int ret;
3565
10589a46
MT		 3566 if (gpa == UNMAPPED_GVA) {
3567 r = X86EMUL_PROPAGATE_FAULT;
3568 goto out;
3569 }
77c2002e 3570 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3571 if (ret < 0) {
c3cd7ffa 3572 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3573 goto out;
3574 }
bbd9b64e 3575
77c2002e
IE		 3576 bytes -= toread;
3577 data += toread;
3578 addr += toread;
bbd9b64e 3579 }
10589a46 3580out:
10589a46 3581 return r;
bbd9b64e 3582}
77c2002e 3583
1871c602
GN		 3584/* used for instruction fetching */
3585static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3586 struct kvm_vcpu *vcpu, u32 *error)
3587{
3588 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3589 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3590 access | PFERR_FETCH_MASK, error);
3591}
3592
3593static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3594 struct kvm_vcpu *vcpu, u32 *error)
3595{
3596 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3597 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3598 error);
3599}
3600
3601static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3602 struct kvm_vcpu *vcpu, u32 *error)
3603{
3604 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3605}
3606
7972995b 3607static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3608 unsigned int bytes,
7972995b 3609 struct kvm_vcpu *vcpu,
2dafc6c2 3610 u32 *error)
77c2002e
IE		 3611{
3612 void *data = val;
3613 int r = X86EMUL_CONTINUE;
3614
3615 while (bytes) {
14dfe855
JR		 3616 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3617 PFERR_WRITE_MASK,
3618 error);
77c2002e
IE		 3619 unsigned offset = addr & (PAGE_SIZE-1);
3620 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3621 int ret;
3622
3623 if (gpa == UNMAPPED_GVA) {
3624 r = X86EMUL_PROPAGATE_FAULT;
3625 goto out;
3626 }
3627 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3628 if (ret < 0) {
c3cd7ffa 3629 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3630 goto out;
3631 }
3632
3633 bytes -= towrite;
3634 data += towrite;
3635 addr += towrite;
3636 }
3637out:
3638 return r;
3639}
3640
bbd9b64e
CO		 3641static int emulator_read_emulated(unsigned long addr,
3642 void *val,
3643 unsigned int bytes,
8fe681e9 3644 unsigned int *error_code,
bbd9b64e
CO		 3645 struct kvm_vcpu *vcpu)
3646{
bbd9b64e
CO		 3647 gpa_t gpa;
3648
3649 if (vcpu->mmio_read_completed) {
3650 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3651 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3652 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3653 vcpu->mmio_read_completed = 0;
3654 return X86EMUL_CONTINUE;
3655 }
3656
8fe681e9 3657 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3658
8fe681e9 3659 if (gpa == UNMAPPED_GVA)
1871c602 3660 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3661
3662 /* For APIC access vmexit */
3663 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3664 goto mmio;
3665
1871c602 3666 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3667 == X86EMUL_CONTINUE)
bbd9b64e 3668 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3669
3670mmio:
3671 /*
3672 * Is this MMIO handled locally?
3673 */
aec51dc4
AK		 3674 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3675 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3676 return X86EMUL_CONTINUE;
3677 }
aec51dc4
AK		 3678
3679 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3680
3681 vcpu->mmio_needed = 1;
411c35b7
GN		 3682 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3683 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3684 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3685 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3686
c3cd7ffa 3687 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3688}
3689
3200f405 3690int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3691 const void *val, int bytes)
bbd9b64e
CO		 3692{
3693 int ret;
3694
3695 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3696 if (ret < 0)
bbd9b64e 3697 return 0;
ad218f85 3698 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3699 return 1;
3700}
3701
3702static int emulator_write_emulated_onepage(unsigned long addr,
3703 const void *val,
3704 unsigned int bytes,
8fe681e9 3705 unsigned int *error_code,
bbd9b64e
CO		 3706 struct kvm_vcpu *vcpu)
3707{
10589a46
MT		 3708 gpa_t gpa;
3709
8fe681e9 3710 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3711
8fe681e9 3712 if (gpa == UNMAPPED_GVA)
bbd9b64e 3713 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3714
3715 /* For APIC access vmexit */
3716 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3717 goto mmio;
3718
3719 if (emulator_write_phys(vcpu, gpa, val, bytes))
3720 return X86EMUL_CONTINUE;
3721
3722mmio:
aec51dc4 3723 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3724 /*
3725 * Is this MMIO handled locally?
3726 */
bda9020e 3727 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3728 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3729
3730 vcpu->mmio_needed = 1;
411c35b7
GN		 3731 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3732 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3733 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3734 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3735 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3736
3737 return X86EMUL_CONTINUE;
3738}
3739
3740int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3741 const void *val,
3742 unsigned int bytes,
8fe681e9 3743 unsigned int *error_code,
8f6abd06 3744 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3745{
3746 /* Crossing a page boundary? */
3747 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3748 int rc, now;
3749
3750 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3751 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3752 vcpu);
bbd9b64e
CO		 3753 if (rc != X86EMUL_CONTINUE)
3754 return rc;
3755 addr += now;
3756 val += now;
3757 bytes -= now;
3758 }
8fe681e9
GN		 3759 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3760 vcpu);
bbd9b64e 3761}
bbd9b64e 3762
daea3e73
AK		 3763#define CMPXCHG_TYPE(t, ptr, old, new) \
3764 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3765
3766#ifdef CONFIG_X86_64
3767# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3768#else
3769# define CMPXCHG64(ptr, old, new) \
9749a6c0 3770 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3771#endif
3772
bbd9b64e
CO		 3773static int emulator_cmpxchg_emulated(unsigned long addr,
3774 const void *old,
3775 const void *new,
3776 unsigned int bytes,
8fe681e9 3777 unsigned int *error_code,
bbd9b64e
CO		 3778 struct kvm_vcpu *vcpu)
3779{
daea3e73
AK		 3780 gpa_t gpa;
3781 struct page *page;
3782 char *kaddr;
3783 bool exchanged;
2bacc55c 3784
daea3e73
AK		 3785 /* guests cmpxchg8b have to be emulated atomically */
3786 if (bytes > 8 || (bytes & (bytes - 1)))
3787 goto emul_write;
10589a46 3788
daea3e73 3789 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3790
daea3e73
AK		 3791 if (gpa == UNMAPPED_GVA ||
3792 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3793 goto emul_write;
2bacc55c 3794
daea3e73
AK		 3795 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3796 goto emul_write;
72dc67a6 3797
daea3e73 3798 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3799 if (is_error_page(page)) {
3800 kvm_release_page_clean(page);
3801 goto emul_write;
3802 }
72dc67a6 3803
daea3e73
AK		 3804 kaddr = kmap_atomic(page, KM_USER0);
3805 kaddr += offset_in_page(gpa);
3806 switch (bytes) {
3807 case 1:
3808 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3809 break;
3810 case 2:
3811 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3812 break;
3813 case 4:
3814 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3815 break;
3816 case 8:
3817 exchanged = CMPXCHG64(kaddr, old, new);
3818 break;
3819 default:
3820 BUG();
2bacc55c 3821 }
daea3e73
AK		 3822 kunmap_atomic(kaddr, KM_USER0);
3823 kvm_release_page_dirty(page);
3824
3825 if (!exchanged)
3826 return X86EMUL_CMPXCHG_FAILED;
3827
8f6abd06
GN		 3828 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3829
3830 return X86EMUL_CONTINUE;
4a5f48f6 3831
3200f405 3832emul_write:
daea3e73 3833 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3834
8fe681e9 3835 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3836}
3837
cf8f70bf
GN		 3838static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3839{
3840 /* TODO: String I/O for in kernel device */
3841 int r;
3842
3843 if (vcpu->arch.pio.in)
3844 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3845 vcpu->arch.pio.size, pd);
3846 else
3847 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3848 vcpu->arch.pio.port, vcpu->arch.pio.size,
3849 pd);
3850 return r;
3851}
3852
3853
3854static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3855 unsigned int count, struct kvm_vcpu *vcpu)
3856{
7972995b 3857 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3858 goto data_avail;
3859
c41a15dd 3860 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3861
3862 vcpu->arch.pio.port = port;
3863 vcpu->arch.pio.in = 1;
7972995b 3864 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3865 vcpu->arch.pio.size = size;
3866
3867 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3868 data_avail:
3869 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3870 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3871 return 1;
3872 }
3873
3874 vcpu->run->exit_reason = KVM_EXIT_IO;
3875 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3876 vcpu->run->io.size = size;
3877 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3878 vcpu->run->io.count = count;
3879 vcpu->run->io.port = port;
3880
3881 return 0;
3882}
3883
3884static int emulator_pio_out_emulated(int size, unsigned short port,
3885 const void *val, unsigned int count,
3886 struct kvm_vcpu *vcpu)
3887{
c41a15dd 3888 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3889
3890 vcpu->arch.pio.port = port;
3891 vcpu->arch.pio.in = 0;
7972995b 3892 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3893 vcpu->arch.pio.size = size;
3894
3895 memcpy(vcpu->arch.pio_data, val, size * count);
3896
3897 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3898 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3899 return 1;
3900 }
3901
3902 vcpu->run->exit_reason = KVM_EXIT_IO;
3903 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3904 vcpu->run->io.size = size;
3905 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3906 vcpu->run->io.count = count;
3907 vcpu->run->io.port = port;
3908
3909 return 0;
3910}
3911
bbd9b64e
CO		 3912static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3913{
3914 return kvm_x86_ops->get_segment_base(vcpu, seg);
3915}
3916
3917int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3918{
a7052897 3919 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3920 return X86EMUL_CONTINUE;
3921}
3922
f5f48ee1
SY		 3923int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3924{
3925 if (!need_emulate_wbinvd(vcpu))
3926 return X86EMUL_CONTINUE;
3927
3928 if (kvm_x86_ops->has_wbinvd_exit()) {
3929 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3930 wbinvd_ipi, NULL, 1);
3931 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3932 }
3933 wbinvd();
3934 return X86EMUL_CONTINUE;
3935}
3936EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3937
bbd9b64e
CO		 3938int emulate_clts(struct kvm_vcpu *vcpu)
3939{
4d4ec087 3940 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3941 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3942 return X86EMUL_CONTINUE;
3943}
3944
35aa5375 3945int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3946{
338dbc97 3947 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3948}
3949
35aa5375 3950int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3951{
338dbc97
GN		 3952
3953 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3954}
3955
52a46617 3956static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3957{
52a46617 3958 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3959}
3960
52a46617 3961static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3962{
52a46617
GN		 3963 unsigned long value;
3964
3965 switch (cr) {
3966 case 0:
3967 value = kvm_read_cr0(vcpu);
3968 break;
3969 case 2:
3970 value = vcpu->arch.cr2;
3971 break;
3972 case 3:
3973 value = vcpu->arch.cr3;
3974 break;
3975 case 4:
3976 value = kvm_read_cr4(vcpu);
3977 break;
3978 case 8:
3979 value = kvm_get_cr8(vcpu);
3980 break;
3981 default:
3982 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3983 return 0;
3984 }
3985
3986 return value;
3987}
3988
0f12244f 3989static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3990{
0f12244f
GN		 3991 int res = 0;
3992
52a46617
GN		 3993 switch (cr) {
3994 case 0:
49a9b07e 3995 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3996 break;
3997 case 2:
3998 vcpu->arch.cr2 = val;
3999 break;
4000 case 3:
2390218b 4001 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4002 break;
4003 case 4:
a83b29c6 4004 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4005 break;
4006 case 8:
0f12244f 4007 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4008 break;
4009 default:
4010 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4011 res = -1;
52a46617 4012 }
0f12244f
GN		 4013
4014 return res;
52a46617
GN		 4015}
4016
9c537244
GN		 4017static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4018{
4019 return kvm_x86_ops->get_cpl(vcpu);
4020}
4021
2dafc6c2
GN		 4022static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4023{
4024 kvm_x86_ops->get_gdt(vcpu, dt);
4025}
4026
160ce1f1
MG		 4027static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4028{
4029 kvm_x86_ops->get_idt(vcpu, dt);
4030}
4031
5951c442
GN		 4032static unsigned long emulator_get_cached_segment_base(int seg,
4033 struct kvm_vcpu *vcpu)
4034{
4035 return get_segment_base(vcpu, seg);
4036}
4037
2dafc6c2
GN		 4038static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4039 struct kvm_vcpu *vcpu)
4040{
4041 struct kvm_segment var;
4042
4043 kvm_get_segment(vcpu, &var, seg);
4044
4045 if (var.unusable)
4046 return false;
4047
4048 if (var.g)
4049 var.limit >>= 12;
4050 set_desc_limit(desc, var.limit);
4051 set_desc_base(desc, (unsigned long)var.base);
4052 desc->type = var.type;
4053 desc->s = var.s;
4054 desc->dpl = var.dpl;
4055 desc->p = var.present;
4056 desc->avl = var.avl;
4057 desc->l = var.l;
4058 desc->d = var.db;
4059 desc->g = var.g;
4060
4061 return true;
4062}
4063
4064static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4065 struct kvm_vcpu *vcpu)
4066{
4067 struct kvm_segment var;
4068
4069 /* needed to preserve selector */
4070 kvm_get_segment(vcpu, &var, seg);
4071
4072 var.base = get_desc_base(desc);
4073 var.limit = get_desc_limit(desc);
4074 if (desc->g)
4075 var.limit = (var.limit << 12) | 0xfff;
4076 var.type = desc->type;
4077 var.present = desc->p;
4078 var.dpl = desc->dpl;
4079 var.db = desc->d;
4080 var.s = desc->s;
4081 var.l = desc->l;
4082 var.g = desc->g;
4083 var.avl = desc->avl;
4084 var.present = desc->p;
4085 var.unusable = !var.present;
4086 var.padding = 0;
4087
4088 kvm_set_segment(vcpu, &var, seg);
4089 return;
4090}
4091
4092static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4093{
4094 struct kvm_segment kvm_seg;
4095
4096 kvm_get_segment(vcpu, &kvm_seg, seg);
4097 return kvm_seg.selector;
4098}
4099
4100static void emulator_set_segment_selector(u16 sel, int seg,
4101 struct kvm_vcpu *vcpu)
4102{
4103 struct kvm_segment kvm_seg;
4104
4105 kvm_get_segment(vcpu, &kvm_seg, seg);
4106 kvm_seg.selector = sel;
4107 kvm_set_segment(vcpu, &kvm_seg, seg);
4108}
4109
14af3f3c 4110static struct x86_emulate_ops emulate_ops = {
1871c602 4111 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4112 .write_std = kvm_write_guest_virt_system,
1871c602 4113 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4114 .read_emulated = emulator_read_emulated,
4115 .write_emulated = emulator_write_emulated,
4116 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4117 .pio_in_emulated = emulator_pio_in_emulated,
4118 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4119 .get_cached_descriptor = emulator_get_cached_descriptor,
4120 .set_cached_descriptor = emulator_set_cached_descriptor,
4121 .get_segment_selector = emulator_get_segment_selector,
4122 .set_segment_selector = emulator_set_segment_selector,
5951c442 4123 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4124 .get_gdt = emulator_get_gdt,
160ce1f1 4125 .get_idt = emulator_get_idt,
52a46617
GN		 4126 .get_cr = emulator_get_cr,
4127 .set_cr = emulator_set_cr,
9c537244 4128 .cpl = emulator_get_cpl,
35aa5375
GN		 4129 .get_dr = emulator_get_dr,
4130 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4131 .set_msr = kvm_set_msr,
4132 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4133};
4134
5fdbf976
MT		 4135static void cache_all_regs(struct kvm_vcpu *vcpu)
4136{
4137 kvm_register_read(vcpu, VCPU_REGS_RAX);
4138 kvm_register_read(vcpu, VCPU_REGS_RSP);
4139 kvm_register_read(vcpu, VCPU_REGS_RIP);
4140 vcpu->arch.regs_dirty = ~0;
4141}
4142
95cb2295
GN		 4143static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4144{
4145 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4146 /*
4147 * an sti; sti; sequence only disable interrupts for the first
4148 * instruction. So, if the last instruction, be it emulated or
4149 * not, left the system with the INT_STI flag enabled, it
4150 * means that the last instruction is an sti. We should not
4151 * leave the flag on in this case. The same goes for mov ss
4152 */
4153 if (!(int_shadow & mask))
4154 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4155}
4156
54b8486f
GN		 4157static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4158{
4159 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4160 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4161 kvm_propagate_fault(vcpu);
54b8486f
GN		 4162 else if (ctxt->error_code_valid)
4163 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4164 else
4165 kvm_queue_exception(vcpu, ctxt->exception);
4166}
4167
8ec4722d
MG		 4168static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4169{
4170 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4171 int cs_db, cs_l;
4172
4173 cache_all_regs(vcpu);
4174
4175 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4176
4177 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4178 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4179 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4180 vcpu->arch.emulate_ctxt.mode =
4181 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4182 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4183 ? X86EMUL_MODE_VM86 : cs_l
4184 ? X86EMUL_MODE_PROT64 : cs_db
4185 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4186 memset(c, 0, sizeof(struct decode_cache));
4187 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4188}
4189
6d77dbfc
GN		 4190static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4191{
6d77dbfc
GN		 4192 ++vcpu->stat.insn_emulation_fail;
4193 trace_kvm_emulate_insn_failed(vcpu);
4194 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4195 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4196 vcpu->run->internal.ndata = 0;
4197 kvm_queue_exception(vcpu, UD_VECTOR);
4198 return EMULATE_FAIL;
4199}
4200
a6f177ef
GN		 4201static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4202{
4203 gpa_t gpa;
4204
68be0803
GN		 4205 if (tdp_enabled)
4206 return false;
4207
a6f177ef
GN		 4208 /*
4209 * if emulation was due to access to shadowed page table
4210 * and it failed try to unshadow page and re-entetr the
4211 * guest to let CPU execute the instruction.
4212 */
4213 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4214 return true;
4215
4216 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4217
4218 if (gpa == UNMAPPED_GVA)
4219 return true; /* let cpu generate fault */
4220
4221 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4222 return true;
4223
4224 return false;
4225}
4226
bbd9b64e 4227int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4228 unsigned long cr2,
4229 u16 error_code,
571008da 4230 int emulation_type)
bbd9b64e 4231{
95cb2295 4232 int r;
4d2179e1 4233 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4234
26eef70c 4235 kvm_clear_exception_queue(vcpu);
ad312c7c 4236 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4237 /*
56e82318 4238 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4239 * instead of direct ->regs accesses, can save hundred cycles
4240 * on Intel for instructions that don't read/change RSP, for
4241 * for example.
4242 */
4243 cache_all_regs(vcpu);
bbd9b64e 4244
571008da 4245 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4246 init_emulate_ctxt(vcpu);
95cb2295 4247 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4248 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4249 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4250
9aabc88f 4251 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4252 if (r == X86EMUL_PROPAGATE_FAULT)
4253 goto done;
4254
e46479f8 4255 trace_kvm_emulate_insn_start(vcpu);
571008da 4256
0cb5762e
AP		 4257 /* Only allow emulation of specific instructions on #UD
4258 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4259 if (emulation_type & EMULTYPE_TRAP_UD) {
4260 if (!c->twobyte)
4261 return EMULATE_FAIL;
4262 switch (c->b) {
4263 case 0x01: /* VMMCALL */
4264 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4265 return EMULATE_FAIL;
4266 break;
4267 case 0x34: /* sysenter */
4268 case 0x35: /* sysexit */
4269 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4270 return EMULATE_FAIL;
4271 break;
4272 case 0x05: /* syscall */
4273 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4274 return EMULATE_FAIL;
4275 break;
4276 default:
4277 return EMULATE_FAIL;
4278 }
4279
4280 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4281 return EMULATE_FAIL;
4282 }
571008da 4283
f2b5756b 4284 ++vcpu->stat.insn_emulation;
bbd9b64e 4285 if (r) {
a6f177ef 4286 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4287 return EMULATE_DONE;
6d77dbfc
GN		 4288 if (emulation_type & EMULTYPE_SKIP)
4289 return EMULATE_FAIL;
4290 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4291 }
4292 }
4293
ba8afb6b
GN		 4294 if (emulation_type & EMULTYPE_SKIP) {
4295 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4296 return EMULATE_DONE;
4297 }
4298
4d2179e1
GN		 4299 /* this is needed for vmware backdor interface to work since it
4300 changes registers values during IO operation */
4301 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4302
5cd21917 4303restart:
9aabc88f 4304 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4305
d2ddd1c4 4306 if (r == EMULATION_FAILED) {
a6f177ef 4307 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4308 return EMULATE_DONE;
4309
6d77dbfc 4310 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4311 }
4312
d47f00a6 4313done:
d2ddd1c4 4314 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4315 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4316 r = EMULATE_DONE;
4317 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4318 if (!vcpu->arch.pio.in)
4319 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4320 r = EMULATE_DO_MMIO;
4321 } else if (vcpu->mmio_needed) {
3457e419
GN		 4322 if (vcpu->mmio_is_write)
4323 vcpu->mmio_needed = 0;
e85d28f8 4324 r = EMULATE_DO_MMIO;
d2ddd1c4 4325 } else if (r == EMULATION_RESTART)
5cd21917 4326 goto restart;
d2ddd1c4
GN		 4327 else
4328 r = EMULATE_DONE;
f850e2e6 4329
e85d28f8
GN		 4330 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4331 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4332 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4333 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4334 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4335
4336 return r;
de7d789a 4337}
bbd9b64e 4338EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4339
cf8f70bf 4340int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4341{
cf8f70bf
GN		 4342 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4343 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4344 /* do not return to emulator after return from userspace */
7972995b 4345 vcpu->arch.pio.count = 0;
de7d789a
CO		 4346 return ret;
4347}
cf8f70bf 4348EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4349
8cfdc000
ZA		 4350static void tsc_bad(void *info)
4351{
4352 __get_cpu_var(cpu_tsc_khz) = 0;
4353}
4354
4355static void tsc_khz_changed(void *data)
c8076604 4356{
8cfdc000
ZA		 4357 struct cpufreq_freqs *freq = data;
4358 unsigned long khz = 0;
4359
4360 if (data)
4361 khz = freq->new;
4362 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4363 khz = cpufreq_quick_get(raw_smp_processor_id());
4364 if (!khz)
4365 khz = tsc_khz;
4366 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4367}
4368
c8076604
GH		 4369static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4370 void *data)
4371{
4372 struct cpufreq_freqs *freq = data;
4373 struct kvm *kvm;
4374 struct kvm_vcpu *vcpu;
4375 int i, send_ipi = 0;
4376
8cfdc000
ZA		 4377 /*
4378 * We allow guests to temporarily run on slowing clocks,
4379 * provided we notify them after, or to run on accelerating
4380 * clocks, provided we notify them before. Thus time never
4381 * goes backwards.
4382 *
4383 * However, we have a problem. We can't atomically update
4384 * the frequency of a given CPU from this function; it is
4385 * merely a notifier, which can be called from any CPU.
4386 * Changing the TSC frequency at arbitrary points in time
4387 * requires a recomputation of local variables related to
4388 * the TSC for each VCPU. We must flag these local variables
4389 * to be updated and be sure the update takes place with the
4390 * new frequency before any guests proceed.
4391 *
4392 * Unfortunately, the combination of hotplug CPU and frequency
4393 * change creates an intractable locking scenario; the order
4394 * of when these callouts happen is undefined with respect to
4395 * CPU hotplug, and they can race with each other. As such,
4396 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4397 * undefined; you can actually have a CPU frequency change take
4398 * place in between the computation of X and the setting of the
4399 * variable. To protect against this problem, all updates of
4400 * the per_cpu tsc_khz variable are done in an interrupt
4401 * protected IPI, and all callers wishing to update the value
4402 * must wait for a synchronous IPI to complete (which is trivial
4403 * if the caller is on the CPU already). This establishes the
4404 * necessary total order on variable updates.
4405 *
4406 * Note that because a guest time update may take place
4407 * anytime after the setting of the VCPU's request bit, the
4408 * correct TSC value must be set before the request. However,
4409 * to ensure the update actually makes it to any guest which
4410 * starts running in hardware virtualization between the set
4411 * and the acquisition of the spinlock, we must also ping the
4412 * CPU after setting the request bit.
4413 *
4414 */
4415
c8076604
GH		 4416 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4417 return 0;
4418 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4419 return 0;
8cfdc000
ZA		 4420
4421 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4422
4423 spin_lock(&kvm_lock);
4424 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4425 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4426 if (vcpu->cpu != freq->cpu)
4427 continue;
4428 if (!kvm_request_guest_time_update(vcpu))
4429 continue;
4430 if (vcpu->cpu != smp_processor_id())
8cfdc000 4431 send_ipi = 1;
c8076604
GH		 4432 }
4433 }
4434 spin_unlock(&kvm_lock);
4435
4436 if (freq->old < freq->new && send_ipi) {
4437 /*
4438 * We upscale the frequency. Must make the guest
4439 * doesn't see old kvmclock values while running with
4440 * the new frequency, otherwise we risk the guest sees
4441 * time go backwards.
4442 *
4443 * In case we update the frequency for another cpu
4444 * (which might be in guest context) send an interrupt
4445 * to kick the cpu out of guest context. Next time
4446 * guest context is entered kvmclock will be updated,
4447 * so the guest will not see stale values.
4448 */
8cfdc000 4449 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4450 }
4451 return 0;
4452}
4453
4454static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4455 .notifier_call = kvmclock_cpufreq_notifier
4456};
4457
4458static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4459 unsigned long action, void *hcpu)
4460{
4461 unsigned int cpu = (unsigned long)hcpu;
4462
4463 switch (action) {
4464 case CPU_ONLINE:
4465 case CPU_DOWN_FAILED:
4466 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4467 break;
4468 case CPU_DOWN_PREPARE:
4469 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4470 break;
4471 }
4472 return NOTIFY_OK;
4473}
4474
4475static struct notifier_block kvmclock_cpu_notifier_block = {
4476 .notifier_call = kvmclock_cpu_notifier,
4477 .priority = -INT_MAX
c8076604
GH		 4478};
4479
b820cc0c
ZA		 4480static void kvm_timer_init(void)
4481{
4482 int cpu;
4483
8cfdc000 4484 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4485 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4486 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4487 CPUFREQ_TRANSITION_NOTIFIER);
4488 }
8cfdc000
ZA		 4489 for_each_online_cpu(cpu)
4490 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4491}
4492
ff9d07a0
ZY		 4493static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4494
4495static int kvm_is_in_guest(void)
4496{
4497 return percpu_read(current_vcpu) != NULL;
4498}
4499
4500static int kvm_is_user_mode(void)
4501{
4502 int user_mode = 3;
dcf46b94 4503
ff9d07a0
ZY		 4504 if (percpu_read(current_vcpu))
4505 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4506
ff9d07a0
ZY		 4507 return user_mode != 0;
4508}
4509
4510static unsigned long kvm_get_guest_ip(void)
4511{
4512 unsigned long ip = 0;
dcf46b94 4513
ff9d07a0
ZY		 4514 if (percpu_read(current_vcpu))
4515 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4516
ff9d07a0
ZY		 4517 return ip;
4518}
4519
4520static struct perf_guest_info_callbacks kvm_guest_cbs = {
4521 .is_in_guest = kvm_is_in_guest,
4522 .is_user_mode = kvm_is_user_mode,
4523 .get_guest_ip = kvm_get_guest_ip,
4524};
4525
4526void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4527{
4528 percpu_write(current_vcpu, vcpu);
4529}
4530EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4531
4532void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4533{
4534 percpu_write(current_vcpu, NULL);
4535}
4536EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4537
f8c16bba 4538int kvm_arch_init(void *opaque)
043405e1 4539{
b820cc0c 4540 int r;
f8c16bba
ZX		 4541 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4542
f8c16bba
ZX		 4543 if (kvm_x86_ops) {
4544 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4545 r = -EEXIST;
4546 goto out;
f8c16bba
ZX		 4547 }
4548
4549 if (!ops->cpu_has_kvm_support()) {
4550 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4551 r = -EOPNOTSUPP;
4552 goto out;
f8c16bba
ZX		 4553 }
4554 if (ops->disabled_by_bios()) {
4555 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4556 r = -EOPNOTSUPP;
4557 goto out;
f8c16bba
ZX		 4558 }
4559
97db56ce
AK		 4560 r = kvm_mmu_module_init();
4561 if (r)
4562 goto out;
4563
4564 kvm_init_msr_list();
4565
f8c16bba 4566 kvm_x86_ops = ops;
56c6d28a 4567 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4568 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4569 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4570 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4571
b820cc0c 4572 kvm_timer_init();
c8076604 4573
ff9d07a0
ZY		 4574 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4575
2acf923e
DC		 4576 if (cpu_has_xsave)
4577 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4578
f8c16bba 4579 return 0;
56c6d28a
ZX		 4580
4581out:
56c6d28a 4582 return r;
043405e1 4583}
8776e519 4584
f8c16bba
ZX		 4585void kvm_arch_exit(void)
4586{
ff9d07a0
ZY		 4587 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4588
888d256e
JK		 4589 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4590 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4591 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4592 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4593 kvm_x86_ops = NULL;
56c6d28a
ZX		 4594 kvm_mmu_module_exit();
4595}
f8c16bba 4596
8776e519
HB		 4597int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4598{
4599 ++vcpu->stat.halt_exits;
4600 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4601 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4602 return 1;
4603 } else {
4604 vcpu->run->exit_reason = KVM_EXIT_HLT;
4605 return 0;
4606 }
4607}
4608EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4609
2f333bcb
MT		 4610static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4611 unsigned long a1)
4612{
4613 if (is_long_mode(vcpu))
4614 return a0;
4615 else
4616 return a0 | ((gpa_t)a1 << 32);
4617}
4618
55cd8e5a
GN		 4619int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4620{
4621 u64 param, ingpa, outgpa, ret;
4622 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4623 bool fast, longmode;
4624 int cs_db, cs_l;
4625
4626 /*
4627 * hypercall generates UD from non zero cpl and real mode
4628 * per HYPER-V spec
4629 */
3eeb3288 4630 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4631 kvm_queue_exception(vcpu, UD_VECTOR);
4632 return 0;
4633 }
4634
4635 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4636 longmode = is_long_mode(vcpu) && cs_l == 1;
4637
4638 if (!longmode) {
ccd46936
GN		 4639 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4640 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4641 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4642 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4643 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4644 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4645 }
4646#ifdef CONFIG_X86_64
4647 else {
4648 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4649 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4650 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4651 }
4652#endif
4653
4654 code = param & 0xffff;
4655 fast = (param >> 16) & 0x1;
4656 rep_cnt = (param >> 32) & 0xfff;
4657 rep_idx = (param >> 48) & 0xfff;
4658
4659 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4660
c25bc163
GN		 4661 switch (code) {
4662 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4663 kvm_vcpu_on_spin(vcpu);
4664 break;
4665 default:
4666 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4667 break;
4668 }
55cd8e5a
GN		 4669
4670 ret = res | (((u64)rep_done & 0xfff) << 32);
4671 if (longmode) {
4672 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4673 } else {
4674 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4675 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4676 }
4677
4678 return 1;
4679}
4680
8776e519
HB		 4681int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4682{
4683 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4684 int r = 1;
8776e519 4685
55cd8e5a
GN		 4686 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4687 return kvm_hv_hypercall(vcpu);
4688
5fdbf976
MT		 4689 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4690 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4691 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4692 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4693 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4694
229456fc 4695 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4696
8776e519
HB		 4697 if (!is_long_mode(vcpu)) {
4698 nr &= 0xFFFFFFFF;
4699 a0 &= 0xFFFFFFFF;
4700 a1 &= 0xFFFFFFFF;
4701 a2 &= 0xFFFFFFFF;
4702 a3 &= 0xFFFFFFFF;
4703 }
4704
07708c4a
JK		 4705 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4706 ret = -KVM_EPERM;
4707 goto out;
4708 }
4709
8776e519 4710 switch (nr) {
b93463aa
AK		 4711 case KVM_HC_VAPIC_POLL_IRQ:
4712 ret = 0;
4713 break;
2f333bcb
MT		 4714 case KVM_HC_MMU_OP:
4715 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4716 break;
8776e519
HB		 4717 default:
4718 ret = -KVM_ENOSYS;
4719 break;
4720 }
07708c4a 4721out:
5fdbf976 4722 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4723 ++vcpu->stat.hypercalls;
2f333bcb 4724 return r;
8776e519
HB		 4725}
4726EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4727
4728int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4729{
4730 char instruction[3];
5fdbf976 4731 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4732
8776e519
HB		 4733 /*
4734 * Blow out the MMU to ensure that no other VCPU has an active mapping
4735 * to ensure that the updated hypercall appears atomically across all
4736 * VCPUs.
4737 */
4738 kvm_mmu_zap_all(vcpu->kvm);
4739
8776e519 4740 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4741
8fe681e9 4742 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4743}
4744
8776e519
HB		 4745void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4746{
89a27f4d 4747 struct desc_ptr dt = { limit, base };
8776e519
HB		 4748
4749 kvm_x86_ops->set_gdt(vcpu, &dt);
4750}
4751
4752void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4753{
89a27f4d 4754 struct desc_ptr dt = { limit, base };
8776e519
HB		 4755
4756 kvm_x86_ops->set_idt(vcpu, &dt);
4757}
4758
07716717
DK		 4759static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4760{
ad312c7c
ZX		 4761 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4762 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4763
4764 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4765 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4766 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4767 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4768 if (ej->function == e->function) {
4769 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4770 return j;
4771 }
4772 }
4773 return 0; /* silence gcc, even though control never reaches here */
4774}
4775
4776/* find an entry with matching function, matching index (if needed), and that
4777 * should be read next (if it's stateful) */
4778static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4779 u32 function, u32 index)
4780{
4781 if (e->function != function)
4782 return 0;
4783 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4784 return 0;
4785 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4786 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4787 return 0;
4788 return 1;
4789}
4790
d8017474
AG		 4791struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4792 u32 function, u32 index)
8776e519
HB		 4793{
4794 int i;
d8017474 4795 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4796
ad312c7c 4797 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4798 struct kvm_cpuid_entry2 *e;
4799
ad312c7c 4800 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4801 if (is_matching_cpuid_entry(e, function, index)) {
4802 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4803 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4804 best = e;
4805 break;
4806 }
4807 /*
4808 * Both basic or both extended?
4809 */
4810 if (((e->function ^ function) & 0x80000000) == 0)
4811 if (!best || e->function > best->function)
4812 best = e;
4813 }
d8017474
AG		 4814 return best;
4815}
0e851880 4816EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4817
82725b20
DE		 4818int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4819{
4820 struct kvm_cpuid_entry2 *best;
4821
f7a71197
AK		 4822 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4823 if (!best || best->eax < 0x80000008)
4824 goto not_found;
82725b20
DE		 4825 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4826 if (best)
4827 return best->eax & 0xff;
f7a71197 4828not_found:
82725b20
DE		 4829 return 36;
4830}
4831
d8017474
AG		 4832void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4833{
4834 u32 function, index;
4835 struct kvm_cpuid_entry2 *best;
4836
4837 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4838 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4839 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4840 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4841 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4842 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4843 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4844 if (best) {
5fdbf976
MT		 4845 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4846 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4847 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4848 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4849 }
8776e519 4850 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4851 trace_kvm_cpuid(function,
4852 kvm_register_read(vcpu, VCPU_REGS_RAX),
4853 kvm_register_read(vcpu, VCPU_REGS_RBX),
4854 kvm_register_read(vcpu, VCPU_REGS_RCX),
4855 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4856}
4857EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4858
b6c7a5dc
HB		 4859/*
4860 * Check if userspace requested an interrupt window, and that the
4861 * interrupt window is open.
4862 *
4863 * No need to exit to userspace if we already have an interrupt queued.
4864 */
851ba692 4865static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4866{
8061823a 4867 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4868 vcpu->run->request_interrupt_window &&
5df56646 4869 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4870}
4871
851ba692 4872static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4873{
851ba692
AK		 4874 struct kvm_run *kvm_run = vcpu->run;
4875
91586a3b 4876 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4877 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4878 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4879 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4880 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4881 else
b6c7a5dc 4882 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4883 kvm_arch_interrupt_allowed(vcpu) &&
4884 !kvm_cpu_has_interrupt(vcpu) &&
4885 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4886}
4887
b93463aa
AK		 4888static void vapic_enter(struct kvm_vcpu *vcpu)
4889{
4890 struct kvm_lapic *apic = vcpu->arch.apic;
4891 struct page *page;
4892
4893 if (!apic || !apic->vapic_addr)
4894 return;
4895
4896 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4897
4898 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4899}
4900
4901static void vapic_exit(struct kvm_vcpu *vcpu)
4902{
4903 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4904 int idx;
b93463aa
AK		 4905
4906 if (!apic || !apic->vapic_addr)
4907 return;
4908
f656ce01 4909 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4910 kvm_release_page_dirty(apic->vapic_page);
4911 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4912 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4913}
4914
95ba8273
GN		 4915static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4916{
4917 int max_irr, tpr;
4918
4919 if (!kvm_x86_ops->update_cr8_intercept)
4920 return;
4921
88c808fd
AK		 4922 if (!vcpu->arch.apic)
4923 return;
4924
8db3baa2
GN		 4925 if (!vcpu->arch.apic->vapic_addr)
4926 max_irr = kvm_lapic_find_highest_irr(vcpu);
4927 else
4928 max_irr = -1;
95ba8273
GN		 4929
4930 if (max_irr != -1)
4931 max_irr >>= 4;
4932
4933 tpr = kvm_lapic_get_cr8(vcpu);
4934
4935 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4936}
4937
851ba692 4938static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4939{
4940 /* try to reinject previous events if any */
b59bb7bd 4941 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4942 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4943 vcpu->arch.exception.has_error_code,
4944 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4945 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4946 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4947 vcpu->arch.exception.error_code,
4948 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4949 return;
4950 }
4951
95ba8273
GN		 4952 if (vcpu->arch.nmi_injected) {
4953 kvm_x86_ops->set_nmi(vcpu);
4954 return;
4955 }
4956
4957 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4958 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4959 return;
4960 }
4961
4962 /* try to inject new event if pending */
4963 if (vcpu->arch.nmi_pending) {
4964 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4965 vcpu->arch.nmi_pending = false;
4966 vcpu->arch.nmi_injected = true;
4967 kvm_x86_ops->set_nmi(vcpu);
4968 }
4969 } else if (kvm_cpu_has_interrupt(vcpu)) {
4970 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4971 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4972 false);
4973 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4974 }
4975 }
4976}
4977
2acf923e
DC		 4978static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4979{
4980 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4981 !vcpu->guest_xcr0_loaded) {
4982 /* kvm_set_xcr() also depends on this */
4983 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4984 vcpu->guest_xcr0_loaded = 1;
4985 }
4986}
4987
4988static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4989{
4990 if (vcpu->guest_xcr0_loaded) {
4991 if (vcpu->arch.xcr0 != host_xcr0)
4992 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4993 vcpu->guest_xcr0_loaded = 0;
4994 }
4995}
4996
851ba692 4997static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4998{
4999 int r;
6a8b1d13 5000 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5001 vcpu->run->request_interrupt_window;
b6c7a5dc 5002
3e007509 5003 if (vcpu->requests) {
a8eeb04a 5004 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5005 kvm_mmu_unload(vcpu);
a8eeb04a 5006 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5007 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 5008 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
5009 r = kvm_write_guest_time(vcpu);
5010 if (unlikely(r))
5011 goto out;
5012 }
a8eeb04a 5013 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5014 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5015 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5016 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5017 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5018 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5019 r = 0;
5020 goto out;
5021 }
a8eeb04a 5022 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5023 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5024 r = 0;
5025 goto out;
5026 }
a8eeb04a 5027 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5028 vcpu->fpu_active = 0;
5029 kvm_x86_ops->fpu_deactivate(vcpu);
5030 }
2f52d58c 5031 }
b93463aa 5032
3e007509
AK		 5033 r = kvm_mmu_reload(vcpu);
5034 if (unlikely(r))
5035 goto out;
5036
b463a6f7
AK		 5037 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5038 inject_pending_event(vcpu);
5039
5040 /* enable NMI/IRQ window open exits if needed */
5041 if (vcpu->arch.nmi_pending)
5042 kvm_x86_ops->enable_nmi_window(vcpu);
5043 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5044 kvm_x86_ops->enable_irq_window(vcpu);
5045
5046 if (kvm_lapic_enabled(vcpu)) {
5047 update_cr8_intercept(vcpu);
5048 kvm_lapic_sync_to_vapic(vcpu);
5049 }
5050 }
5051
b6c7a5dc
HB		 5052 preempt_disable();
5053
5054 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5055 if (vcpu->fpu_active)
5056 kvm_load_guest_fpu(vcpu);
2acf923e 5057 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5058
d94e1dc9
AK		 5059 atomic_set(&vcpu->guest_mode, 1);
5060 smp_wmb();
b6c7a5dc 5061
d94e1dc9 5062 local_irq_disable();
32f88400 5063
d94e1dc9
AK		 5064 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5065 || need_resched() || signal_pending(current)) {
5066 atomic_set(&vcpu->guest_mode, 0);
5067 smp_wmb();
6c142801
AK		 5068 local_irq_enable();
5069 preempt_enable();
b463a6f7 5070 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5071 r = 1;
5072 goto out;
5073 }
5074
f656ce01 5075 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5076
b6c7a5dc
HB		 5077 kvm_guest_enter();
5078
42dbaa5a 5079 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5080 set_debugreg(0, 7);
5081 set_debugreg(vcpu->arch.eff_db[0], 0);
5082 set_debugreg(vcpu->arch.eff_db[1], 1);
5083 set_debugreg(vcpu->arch.eff_db[2], 2);
5084 set_debugreg(vcpu->arch.eff_db[3], 3);
5085 }
b6c7a5dc 5086
229456fc 5087 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5088 kvm_x86_ops->run(vcpu);
b6c7a5dc 5089
24f1e32c
FW		 5090 /*
5091 * If the guest has used debug registers, at least dr7
5092 * will be disabled while returning to the host.
5093 * If we don't have active breakpoints in the host, we don't
5094 * care about the messed up debug address registers. But if
5095 * we have some of them active, restore the old state.
5096 */
59d8eb53 5097 if (hw_breakpoint_active())
24f1e32c 5098 hw_breakpoint_restore();
42dbaa5a 5099
1d5f066e
ZA		 5100 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5101
d94e1dc9
AK		 5102 atomic_set(&vcpu->guest_mode, 0);
5103 smp_wmb();
b6c7a5dc
HB		 5104 local_irq_enable();
5105
5106 ++vcpu->stat.exits;
5107
5108 /*
5109 * We must have an instruction between local_irq_enable() and
5110 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5111 * the interrupt shadow. The stat.exits increment will do nicely.
5112 * But we need to prevent reordering, hence this barrier():
5113 */
5114 barrier();
5115
5116 kvm_guest_exit();
5117
5118 preempt_enable();
5119
f656ce01 5120 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5121
b6c7a5dc
HB		 5122 /*
5123 * Profile KVM exit RIPs:
5124 */
5125 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5126 unsigned long rip = kvm_rip_read(vcpu);
5127 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5128 }
5129
298101da 5130
b93463aa
AK		 5131 kvm_lapic_sync_from_vapic(vcpu);
5132
851ba692 5133 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5134out:
5135 return r;
5136}
b6c7a5dc 5137
09cec754 5138
851ba692 5139static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5140{
5141 int r;
f656ce01 5142 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5143
5144 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5145 pr_debug("vcpu %d received sipi with vector # %x\n",
5146 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5147 kvm_lapic_reset(vcpu);
5f179287 5148 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5149 if (r)
5150 return r;
5151 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5152 }
5153
f656ce01 5154 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5155 vapic_enter(vcpu);
5156
5157 r = 1;
5158 while (r > 0) {
af2152f5 5159 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5160 r = vcpu_enter_guest(vcpu);
d7690175 5161 else {
f656ce01 5162 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5163 kvm_vcpu_block(vcpu);
f656ce01 5164 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5165 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5166 {
5167 switch(vcpu->arch.mp_state) {
5168 case KVM_MP_STATE_HALTED:
d7690175 5169 vcpu->arch.mp_state =
09cec754
GN		 5170 KVM_MP_STATE_RUNNABLE;
5171 case KVM_MP_STATE_RUNNABLE:
5172 break;
5173 case KVM_MP_STATE_SIPI_RECEIVED:
5174 default:
5175 r = -EINTR;
5176 break;
5177 }
5178 }
d7690175
MT		 5179 }
5180
09cec754
GN		 5181 if (r <= 0)
5182 break;
5183
5184 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5185 if (kvm_cpu_has_pending_timer(vcpu))
5186 kvm_inject_pending_timer_irqs(vcpu);
5187
851ba692 5188 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5189 r = -EINTR;
851ba692 5190 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5191 ++vcpu->stat.request_irq_exits;
5192 }
5193 if (signal_pending(current)) {
5194 r = -EINTR;
851ba692 5195 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5196 ++vcpu->stat.signal_exits;
5197 }
5198 if (need_resched()) {
f656ce01 5199 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5200 kvm_resched(vcpu);
f656ce01 5201 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5202 }
b6c7a5dc
HB		 5203 }
5204
f656ce01 5205 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5206
b93463aa
AK		 5207 vapic_exit(vcpu);
5208
b6c7a5dc
HB		 5209 return r;
5210}
5211
5212int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5213{
5214 int r;
5215 sigset_t sigsaved;
5216
ac9f6dc0
AK		 5217 if (vcpu->sigset_active)
5218 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5219
a4535290 5220 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5221 kvm_vcpu_block(vcpu);
d7690175 5222 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5223 r = -EAGAIN;
5224 goto out;
b6c7a5dc
HB		 5225 }
5226
b6c7a5dc
HB		 5227 /* re-sync apic's tpr */
5228 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5229 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5230
d2ddd1c4 5231 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5232 if (vcpu->mmio_needed) {
5233 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5234 vcpu->mmio_read_completed = 1;
5235 vcpu->mmio_needed = 0;
b6c7a5dc 5236 }
f656ce01 5237 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5238 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5239 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5240 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5241 r = 0;
5242 goto out;
5243 }
5244 }
5fdbf976
MT		 5245 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5246 kvm_register_write(vcpu, VCPU_REGS_RAX,
5247 kvm_run->hypercall.ret);
b6c7a5dc 5248
851ba692 5249 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5250
5251out:
f1d86e46 5252 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5253 if (vcpu->sigset_active)
5254 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5255
b6c7a5dc
HB		 5256 return r;
5257}
5258
5259int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5260{
5fdbf976
MT		 5261 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5262 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5263 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5264 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5265 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5266 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5267 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5268 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5269#ifdef CONFIG_X86_64
5fdbf976
MT		 5270 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5271 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5272 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5273 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5274 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5275 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5276 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5277 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5278#endif
5279
5fdbf976 5280 regs->rip = kvm_rip_read(vcpu);
91586a3b 5281 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5282
b6c7a5dc
HB		 5283 return 0;
5284}
5285
5286int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5287{
5fdbf976
MT		 5288 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5289 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5290 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5291 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5292 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5293 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5294 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5295 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5296#ifdef CONFIG_X86_64
5fdbf976
MT		 5297 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5298 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5299 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5300 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5301 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5302 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5303 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5304 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5305#endif
5306
5fdbf976 5307 kvm_rip_write(vcpu, regs->rip);
91586a3b 5308 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5309
b4f14abd
JK		 5310 vcpu->arch.exception.pending = false;
5311
3842d135
AK		 5312 kvm_make_request(KVM_REQ_EVENT, vcpu);
5313
b6c7a5dc
HB		 5314 return 0;
5315}
5316
b6c7a5dc
HB		 5317void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5318{
5319 struct kvm_segment cs;
5320
3e6e0aab 5321 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5322 *db = cs.db;
5323 *l = cs.l;
5324}
5325EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5326
5327int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5328 struct kvm_sregs *sregs)
5329{
89a27f4d 5330 struct desc_ptr dt;
b6c7a5dc 5331
3e6e0aab
GT		 5332 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5333 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5334 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5335 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5336 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5337 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5338
3e6e0aab
GT		 5339 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5340 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5341
5342 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5343 sregs->idt.limit = dt.size;
5344 sregs->idt.base = dt.address;
b6c7a5dc 5345 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5346 sregs->gdt.limit = dt.size;
5347 sregs->gdt.base = dt.address;
b6c7a5dc 5348
4d4ec087 5349 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5350 sregs->cr2 = vcpu->arch.cr2;
5351 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5352 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5353 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5354 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5355 sregs->apic_base = kvm_get_apic_base(vcpu);
5356
923c61bb 5357 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5358
36752c9b 5359 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5360 set_bit(vcpu->arch.interrupt.nr,
5361 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5362
b6c7a5dc
HB		 5363 return 0;
5364}
5365
62d9f0db
MT		 5366int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5367 struct kvm_mp_state *mp_state)
5368{
62d9f0db 5369 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5370 return 0;
5371}
5372
5373int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5374 struct kvm_mp_state *mp_state)
5375{
62d9f0db 5376 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5377 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5378 return 0;
5379}
5380
e269fb21
JK		 5381int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5382 bool has_error_code, u32 error_code)
b6c7a5dc 5383{
4d2179e1 5384 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5385 int ret;
e01c2426 5386
8ec4722d 5387 init_emulate_ctxt(vcpu);
c697518a 5388
9aabc88f 5389 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5390 tss_selector, reason, has_error_code,
5391 error_code);
c697518a 5392
c697518a 5393 if (ret)
19d04437 5394 return EMULATE_FAIL;
37817f29 5395
4d2179e1 5396 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5397 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5398 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5399 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5400 return EMULATE_DONE;
37817f29
IE		 5401}
5402EXPORT_SYMBOL_GPL(kvm_task_switch);
5403
b6c7a5dc
HB		 5404int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5405 struct kvm_sregs *sregs)
5406{
5407 int mmu_reset_needed = 0;
923c61bb 5408 int pending_vec, max_bits;
89a27f4d 5409 struct desc_ptr dt;
b6c7a5dc 5410
89a27f4d
GN		 5411 dt.size = sregs->idt.limit;
5412 dt.address = sregs->idt.base;
b6c7a5dc 5413 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5414 dt.size = sregs->gdt.limit;
5415 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5416 kvm_x86_ops->set_gdt(vcpu, &dt);
5417
ad312c7c
ZX		 5418 vcpu->arch.cr2 = sregs->cr2;
5419 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5420 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5421
2d3ad1f4 5422 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5423
f6801dff 5424 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5425 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5426 kvm_set_apic_base(vcpu, sregs->apic_base);
5427
4d4ec087 5428 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5429 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5430 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5431
fc78f519 5432 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5433 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5434 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5435 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5436 mmu_reset_needed = 1;
5437 }
b6c7a5dc
HB		 5438
5439 if (mmu_reset_needed)
5440 kvm_mmu_reset_context(vcpu);
5441
923c61bb
GN		 5442 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5443 pending_vec = find_first_bit(
5444 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5445 if (pending_vec < max_bits) {
66fd3f7f 5446 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5447 pr_debug("Set back pending irq %d\n", pending_vec);
5448 if (irqchip_in_kernel(vcpu->kvm))
5449 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5450 }
5451
3e6e0aab
GT		 5452 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5453 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5454 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5455 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5456 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5457 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5458
3e6e0aab
GT		 5459 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5460 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5461
5f0269f5
ME		 5462 update_cr8_intercept(vcpu);
5463
9c3e4aab 5464 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5465 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5466 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5467 !is_protmode(vcpu))
9c3e4aab
MT		 5468 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5469
3842d135
AK		 5470 kvm_make_request(KVM_REQ_EVENT, vcpu);
5471
b6c7a5dc
HB		 5472 return 0;
5473}
5474
d0bfb940
JK		 5475int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5476 struct kvm_guest_debug *dbg)
b6c7a5dc 5477{
355be0b9 5478 unsigned long rflags;
ae675ef0 5479 int i, r;
b6c7a5dc 5480
4f926bf2
JK		 5481 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5482 r = -EBUSY;
5483 if (vcpu->arch.exception.pending)
2122ff5e 5484 goto out;
4f926bf2
JK		 5485 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5486 kvm_queue_exception(vcpu, DB_VECTOR);
5487 else
5488 kvm_queue_exception(vcpu, BP_VECTOR);
5489 }
5490
91586a3b
JK		 5491 /*
5492 * Read rflags as long as potentially injected trace flags are still
5493 * filtered out.
5494 */
5495 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5496
5497 vcpu->guest_debug = dbg->control;
5498 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5499 vcpu->guest_debug = 0;
5500
5501 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5502 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5503 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5504 vcpu->arch.switch_db_regs =
5505 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5506 } else {
5507 for (i = 0; i < KVM_NR_DB_REGS; i++)
5508 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5509 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5510 }
5511
f92653ee
JK		 5512 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5513 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5514 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5515
91586a3b
JK		 5516 /*
5517 * Trigger an rflags update that will inject or remove the trace
5518 * flags.
5519 */
5520 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5521
355be0b9 5522 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5523
4f926bf2 5524 r = 0;
d0bfb940 5525
2122ff5e 5526out:
b6c7a5dc
HB		 5527
5528 return r;
5529}
5530
8b006791
ZX		 5531/*
5532 * Translate a guest virtual address to a guest physical address.
5533 */
5534int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5535 struct kvm_translation *tr)
5536{
5537 unsigned long vaddr = tr->linear_address;
5538 gpa_t gpa;
f656ce01 5539 int idx;
8b006791 5540
f656ce01 5541 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5542 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5543 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5544 tr->physical_address = gpa;
5545 tr->valid = gpa != UNMAPPED_GVA;
5546 tr->writeable = 1;
5547 tr->usermode = 0;
8b006791
ZX		 5548
5549 return 0;
5550}
5551
d0752060
HB		 5552int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5553{
98918833
SY		 5554 struct i387_fxsave_struct *fxsave =
5555 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5556
d0752060
HB		 5557 memcpy(fpu->fpr, fxsave->st_space, 128);
5558 fpu->fcw = fxsave->cwd;
5559 fpu->fsw = fxsave->swd;
5560 fpu->ftwx = fxsave->twd;
5561 fpu->last_opcode = fxsave->fop;
5562 fpu->last_ip = fxsave->rip;
5563 fpu->last_dp = fxsave->rdp;
5564 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5565
d0752060
HB		 5566 return 0;
5567}
5568
5569int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5570{
98918833
SY		 5571 struct i387_fxsave_struct *fxsave =
5572 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5573
d0752060
HB		 5574 memcpy(fxsave->st_space, fpu->fpr, 128);
5575 fxsave->cwd = fpu->fcw;
5576 fxsave->swd = fpu->fsw;
5577 fxsave->twd = fpu->ftwx;
5578 fxsave->fop = fpu->last_opcode;
5579 fxsave->rip = fpu->last_ip;
5580 fxsave->rdp = fpu->last_dp;
5581 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5582
d0752060
HB		 5583 return 0;
5584}
5585
10ab25cd 5586int fx_init(struct kvm_vcpu *vcpu)
d0752060 5587{
10ab25cd
JK		 5588 int err;
5589
5590 err = fpu_alloc(&vcpu->arch.guest_fpu);
5591 if (err)
5592 return err;
5593
98918833 5594 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5595
2acf923e
DC		 5596 /*
5597 * Ensure guest xcr0 is valid for loading
5598 */
5599 vcpu->arch.xcr0 = XSTATE_FP;
5600
ad312c7c 5601 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5602
5603 return 0;
d0752060
HB		 5604}
5605EXPORT_SYMBOL_GPL(fx_init);
5606
98918833
SY		 5607static void fx_free(struct kvm_vcpu *vcpu)
5608{
5609 fpu_free(&vcpu->arch.guest_fpu);
5610}
5611
d0752060
HB		 5612void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5613{
2608d7a1 5614 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5615 return;
5616
2acf923e
DC		 5617 /*
5618 * Restore all possible states in the guest,
5619 * and assume host would use all available bits.
5620 * Guest xcr0 would be loaded later.
5621 */
5622 kvm_put_guest_xcr0(vcpu);
d0752060 5623 vcpu->guest_fpu_loaded = 1;
7cf30855 5624 unlazy_fpu(current);
98918833 5625 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5626 trace_kvm_fpu(1);
d0752060 5627}
d0752060
HB		 5628
5629void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5630{
2acf923e
DC		 5631 kvm_put_guest_xcr0(vcpu);
5632
d0752060
HB		 5633 if (!vcpu->guest_fpu_loaded)
5634 return;
5635
5636 vcpu->guest_fpu_loaded = 0;
98918833 5637 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5638 ++vcpu->stat.fpu_reload;
a8eeb04a 5639 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5640 trace_kvm_fpu(0);
d0752060 5641}
e9b11c17
ZX		 5642
5643void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5644{
7f1ea208
JR		 5645 if (vcpu->arch.time_page) {
5646 kvm_release_page_dirty(vcpu->arch.time_page);
5647 vcpu->arch.time_page = NULL;
5648 }
5649
f5f48ee1 5650 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5651 fx_free(vcpu);
e9b11c17
ZX		 5652 kvm_x86_ops->vcpu_free(vcpu);
5653}
5654
5655struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5656 unsigned int id)
5657{
6755bae8
ZA		 5658 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5659 printk_once(KERN_WARNING
5660 "kvm: SMP vm created on host with unstable TSC; "
5661 "guest TSC will not be reliable\n");
26e5215f
AK		 5662 return kvm_x86_ops->vcpu_create(kvm, id);
5663}
e9b11c17 5664
26e5215f
AK		 5665int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5666{
5667 int r;
e9b11c17 5668
0bed3b56 5669 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5670 vcpu_load(vcpu);
5671 r = kvm_arch_vcpu_reset(vcpu);
5672 if (r == 0)
5673 r = kvm_mmu_setup(vcpu);
5674 vcpu_put(vcpu);
5675 if (r < 0)
5676 goto free_vcpu;
5677
26e5215f 5678 return 0;
e9b11c17
ZX		 5679free_vcpu:
5680 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5681 return r;
e9b11c17
ZX		 5682}
5683
d40ccc62 5684void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5685{
5686 vcpu_load(vcpu);
5687 kvm_mmu_unload(vcpu);
5688 vcpu_put(vcpu);
5689
98918833 5690 fx_free(vcpu);
e9b11c17
ZX		 5691 kvm_x86_ops->vcpu_free(vcpu);
5692}
5693
5694int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5695{
448fa4a9
JK		 5696 vcpu->arch.nmi_pending = false;
5697 vcpu->arch.nmi_injected = false;
5698
42dbaa5a
JK		 5699 vcpu->arch.switch_db_regs = 0;
5700 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5701 vcpu->arch.dr6 = DR6_FIXED_1;
5702 vcpu->arch.dr7 = DR7_FIXED_1;
5703
3842d135
AK		 5704 kvm_make_request(KVM_REQ_EVENT, vcpu);
5705
e9b11c17
ZX		 5706 return kvm_x86_ops->vcpu_reset(vcpu);
5707}
5708
10474ae8 5709int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5710{
ca84d1a2
ZA		 5711 struct kvm *kvm;
5712 struct kvm_vcpu *vcpu;
5713 int i;
5714
18863bdd 5715 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5716 list_for_each_entry(kvm, &vm_list, vm_list)
5717 kvm_for_each_vcpu(i, vcpu, kvm)
5718 if (vcpu->cpu == smp_processor_id())
5719 kvm_request_guest_time_update(vcpu);
10474ae8 5720 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5721}
5722
5723void kvm_arch_hardware_disable(void *garbage)
5724{
5725 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5726 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5727}
5728
5729int kvm_arch_hardware_setup(void)
5730{
5731 return kvm_x86_ops->hardware_setup();
5732}
5733
5734void kvm_arch_hardware_unsetup(void)
5735{
5736 kvm_x86_ops->hardware_unsetup();
5737}
5738
5739void kvm_arch_check_processor_compat(void *rtn)
5740{
5741 kvm_x86_ops->check_processor_compatibility(rtn);
5742}
5743
5744int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5745{
5746 struct page *page;
5747 struct kvm *kvm;
5748 int r;
5749
5750 BUG_ON(vcpu->kvm == NULL);
5751 kvm = vcpu->kvm;
5752
9aabc88f 5753 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5754 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5755 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5756 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5757 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5758 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5759 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5760 else
a4535290 5761 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5762
5763 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5764 if (!page) {
5765 r = -ENOMEM;
5766 goto fail;
5767 }
ad312c7c 5768 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5769
5770 r = kvm_mmu_create(vcpu);
5771 if (r < 0)
5772 goto fail_free_pio_data;
5773
5774 if (irqchip_in_kernel(kvm)) {
5775 r = kvm_create_lapic(vcpu);
5776 if (r < 0)
5777 goto fail_mmu_destroy;
5778 }
5779
890ca9ae
HY		 5780 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5781 GFP_KERNEL);
5782 if (!vcpu->arch.mce_banks) {
5783 r = -ENOMEM;
443c39bc 5784 goto fail_free_lapic;
890ca9ae
HY		 5785 }
5786 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5787
f5f48ee1
SY		 5788 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5789 goto fail_free_mce_banks;
5790
e9b11c17 5791 return 0;
f5f48ee1
SY		 5792fail_free_mce_banks:
5793 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5794fail_free_lapic:
5795 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5796fail_mmu_destroy:
5797 kvm_mmu_destroy(vcpu);
5798fail_free_pio_data:
ad312c7c 5799 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5800fail:
5801 return r;
5802}
5803
5804void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5805{
f656ce01
MT		 5806 int idx;
5807
36cb93fd 5808 kfree(vcpu->arch.mce_banks);
e9b11c17 5809 kvm_free_lapic(vcpu);
f656ce01 5810 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5811 kvm_mmu_destroy(vcpu);
f656ce01 5812 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5813 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5814}
d19a9cd2
ZX		 5815
5816struct kvm *kvm_arch_create_vm(void)
5817{
5818 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5819
5820 if (!kvm)
5821 return ERR_PTR(-ENOMEM);
5822
f05e70ac 5823 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5824 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5825
5550af4d
SY		 5826 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5827 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5828
99e3e30a
ZA		 5829 spin_lock_init(&kvm->arch.tsc_write_lock);
5830
d19a9cd2
ZX		 5831 return kvm;
5832}
5833
5834static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5835{
5836 vcpu_load(vcpu);
5837 kvm_mmu_unload(vcpu);
5838 vcpu_put(vcpu);
5839}
5840
5841static void kvm_free_vcpus(struct kvm *kvm)
5842{
5843 unsigned int i;
988a2cae 5844 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5845
5846 /*
5847 * Unpin any mmu pages first.
5848 */
988a2cae
GN		 5849 kvm_for_each_vcpu(i, vcpu, kvm)
5850 kvm_unload_vcpu_mmu(vcpu);
5851 kvm_for_each_vcpu(i, vcpu, kvm)
5852 kvm_arch_vcpu_free(vcpu);
5853
5854 mutex_lock(&kvm->lock);
5855 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5856 kvm->vcpus[i] = NULL;
d19a9cd2 5857
988a2cae
GN		 5858 atomic_set(&kvm->online_vcpus, 0);
5859 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5860}
5861
ad8ba2cd
SY		 5862void kvm_arch_sync_events(struct kvm *kvm)
5863{
ba4cef31 5864 kvm_free_all_assigned_devices(kvm);
aea924f6 5865 kvm_free_pit(kvm);
ad8ba2cd
SY		 5866}
5867
d19a9cd2
ZX		 5868void kvm_arch_destroy_vm(struct kvm *kvm)
5869{
6eb55818 5870 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5871 kfree(kvm->arch.vpic);
5872 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5873 kvm_free_vcpus(kvm);
5874 kvm_free_physmem(kvm);
3d45830c
AK		 5875 if (kvm->arch.apic_access_page)
5876 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5877 if (kvm->arch.ept_identity_pagetable)
5878 put_page(kvm->arch.ept_identity_pagetable);
64749204 5879 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5880 kfree(kvm);
5881}
0de10343 5882
f7784b8e
MT		 5883int kvm_arch_prepare_memory_region(struct kvm *kvm,
5884 struct kvm_memory_slot *memslot,
0de10343 5885 struct kvm_memory_slot old,
f7784b8e 5886 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5887 int user_alloc)
5888{
f7784b8e 5889 int npages = memslot->npages;
7ac77099
AK		 5890 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5891
5892 /* Prevent internal slot pages from being moved by fork()/COW. */
5893 if (memslot->id >= KVM_MEMORY_SLOTS)
5894 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5895
5896 /*To keep backward compatibility with older userspace,
5897 *x86 needs to hanlde !user_alloc case.
5898 */
5899 if (!user_alloc) {
5900 if (npages && !old.rmap) {
604b38ac
AA		 5901 unsigned long userspace_addr;
5902
72dc67a6 5903 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5904 userspace_addr = do_mmap(NULL, 0,
5905 npages * PAGE_SIZE,
5906 PROT_READ | PROT_WRITE,
7ac77099 5907 map_flags,
604b38ac 5908 0);
72dc67a6 5909 up_write(&current->mm->mmap_sem);
0de10343 5910
604b38ac
AA		 5911 if (IS_ERR((void *)userspace_addr))
5912 return PTR_ERR((void *)userspace_addr);
5913
604b38ac 5914 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5915 }
5916 }
5917
f7784b8e
MT		 5918
5919 return 0;
5920}
5921
5922void kvm_arch_commit_memory_region(struct kvm *kvm,
5923 struct kvm_userspace_memory_region *mem,
5924 struct kvm_memory_slot old,
5925 int user_alloc)
5926{
5927
5928 int npages = mem->memory_size >> PAGE_SHIFT;
5929
5930 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5931 int ret;
5932
5933 down_write(&current->mm->mmap_sem);
5934 ret = do_munmap(current->mm, old.userspace_addr,
5935 old.npages * PAGE_SIZE);
5936 up_write(&current->mm->mmap_sem);
5937 if (ret < 0)
5938 printk(KERN_WARNING
5939 "kvm_vm_ioctl_set_memory_region: "
5940 "failed to munmap memory\n");
5941 }
5942
7c8a83b7 5943 spin_lock(&kvm->mmu_lock);
f05e70ac 5944 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5945 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5946 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5947 }
5948
5949 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5950 spin_unlock(&kvm->mmu_lock);
0de10343 5951}
1d737c8a 5952
34d4cb8f
MT		 5953void kvm_arch_flush_shadow(struct kvm *kvm)
5954{
5955 kvm_mmu_zap_all(kvm);
8986ecc0 5956 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5957}
5958
1d737c8a
ZX		 5959int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5960{
a4535290 5961 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5962 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5963 || vcpu->arch.nmi_pending ||
5964 (kvm_arch_interrupt_allowed(vcpu) &&
5965 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5966}
5736199a 5967
5736199a
ZX		 5968void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5969{
32f88400
MT		 5970 int me;
5971 int cpu = vcpu->cpu;
5736199a
ZX		 5972
5973 if (waitqueue_active(&vcpu->wq)) {
5974 wake_up_interruptible(&vcpu->wq);
5975 ++vcpu->stat.halt_wakeup;
5976 }
32f88400
MT		 5977
5978 me = get_cpu();
5979 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5980 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5981 smp_send_reschedule(cpu);
e9571ed5 5982 put_cpu();
5736199a 5983}
78646121
GN		 5984
5985int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5986{
5987 return kvm_x86_ops->interrupt_allowed(vcpu);
5988}
229456fc 5989
f92653ee
JK		 5990bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5991{
5992 unsigned long current_rip = kvm_rip_read(vcpu) +
5993 get_segment_base(vcpu, VCPU_SREG_CS);
5994
5995 return current_rip == linear_rip;
5996}
5997EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5998
94fe45da
JK		 5999unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6000{
6001 unsigned long rflags;
6002
6003 rflags = kvm_x86_ops->get_rflags(vcpu);
6004 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6005 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6006 return rflags;
6007}
6008EXPORT_SYMBOL_GPL(kvm_get_rflags);
6009
6010void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6011{
6012 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6013 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6014 rflags |= X86_EFLAGS_TF;
94fe45da 6015 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6016 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6017}
6018EXPORT_SYMBOL_GPL(kvm_set_rflags);
6019
229456fc
MT		 6020EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6021EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6022EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6023EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6024EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6025EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6026EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6027EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6028EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6029EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6030EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6031EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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