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kvm: x86: Fix kvm clock versioning.
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
8b3c3104 232int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 236 int err;
18863bdd 237
2bf78fa7 238 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 239 return 0;
2bf78fa7 240 smsr->values[slot].curr = value;
8b3c3104
AH		 241 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
242 if (err)
243 return 1;
244
18863bdd
AK		 245 if (!smsr->registered) {
246 smsr->urn.on_user_return = kvm_on_user_return;
247 user_return_notifier_register(&smsr->urn);
248 smsr->registered = true;
249 }
8b3c3104 250 return 0;
18863bdd
AK		 251}
252EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
253
13a34e06 254static void drop_user_return_notifiers(void)
3548bab5 255{
013f6a5d
MT		 256 unsigned int cpu = smp_processor_id();
257 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 258
259 if (smsr->registered)
260 kvm_on_user_return(&smsr->urn);
261}
262
6866b83e
CO		 263u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
264{
8a5a87d9 265 return vcpu->arch.apic_base;
6866b83e
CO		 266}
267EXPORT_SYMBOL_GPL(kvm_get_apic_base);
268
58cb628d
JK		 269int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
270{
271 u64 old_state = vcpu->arch.apic_base &
272 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
273 u64 new_state = msr_info->data &
274 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
275 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
276 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
277
278 if (!msr_info->host_initiated &&
279 ((msr_info->data & reserved_bits) != 0 ||
280 new_state == X2APIC_ENABLE ||
281 (new_state == MSR_IA32_APICBASE_ENABLE &&
282 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
283 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
284 old_state == 0)))
285 return 1;
286
287 kvm_lapic_set_base(vcpu, msr_info->data);
288 return 0;
6866b83e
CO		 289}
290EXPORT_SYMBOL_GPL(kvm_set_apic_base);
291
2605fc21 292asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 293{
294 /* Fault while not rebooting. We want the trace. */
295 BUG();
296}
297EXPORT_SYMBOL_GPL(kvm_spurious_fault);
298
3fd28fce
ED		 299#define EXCPT_BENIGN 0
300#define EXCPT_CONTRIBUTORY 1
301#define EXCPT_PF 2
302
303static int exception_class(int vector)
304{
305 switch (vector) {
306 case PF_VECTOR:
307 return EXCPT_PF;
308 case DE_VECTOR:
309 case TS_VECTOR:
310 case NP_VECTOR:
311 case SS_VECTOR:
312 case GP_VECTOR:
313 return EXCPT_CONTRIBUTORY;
314 default:
315 break;
316 }
317 return EXCPT_BENIGN;
318}
319
d6e8c854
NA		 320#define EXCPT_FAULT 0
321#define EXCPT_TRAP 1
322#define EXCPT_ABORT 2
323#define EXCPT_INTERRUPT 3
324
325static int exception_type(int vector)
326{
327 unsigned int mask;
328
329 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
330 return EXCPT_INTERRUPT;
331
332 mask = 1 << vector;
333
334 /* #DB is trap, as instruction watchpoints are handled elsewhere */
335 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
336 return EXCPT_TRAP;
337
338 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
339 return EXCPT_ABORT;
340
341 /* Reserved exceptions will result in fault */
342 return EXCPT_FAULT;
343}
344
3fd28fce 345static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 346 unsigned nr, bool has_error, u32 error_code,
347 bool reinject)
3fd28fce
ED		 348{
349 u32 prev_nr;
350 int class1, class2;
351
3842d135
AK		 352 kvm_make_request(KVM_REQ_EVENT, vcpu);
353
3fd28fce
ED		 354 if (!vcpu->arch.exception.pending) {
355 queue:
3ffb2468
NA		 356 if (has_error && !is_protmode(vcpu))
357 has_error = false;
3fd28fce
ED		 358 vcpu->arch.exception.pending = true;
359 vcpu->arch.exception.has_error_code = has_error;
360 vcpu->arch.exception.nr = nr;
361 vcpu->arch.exception.error_code = error_code;
3f0fd292 362 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 363 return;
364 }
365
366 /* to check exception */
367 prev_nr = vcpu->arch.exception.nr;
368 if (prev_nr == DF_VECTOR) {
369 /* triple fault -> shutdown */
a8eeb04a 370 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 371 return;
372 }
373 class1 = exception_class(prev_nr);
374 class2 = exception_class(nr);
375 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
376 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
377 /* generate double fault per SDM Table 5-5 */
378 vcpu->arch.exception.pending = true;
379 vcpu->arch.exception.has_error_code = true;
380 vcpu->arch.exception.nr = DF_VECTOR;
381 vcpu->arch.exception.error_code = 0;
382 } else
383 /* replace previous exception with a new one in a hope
384 that instruction re-execution will regenerate lost
385 exception */
386 goto queue;
387}
388
298101da
AK		 389void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
390{
ce7ddec4 391 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 392}
393EXPORT_SYMBOL_GPL(kvm_queue_exception);
394
ce7ddec4
JR		 395void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396{
397 kvm_multiple_exception(vcpu, nr, false, 0, true);
398}
399EXPORT_SYMBOL_GPL(kvm_requeue_exception);
400
db8fcefa 401void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 402{
db8fcefa
AP		 403 if (err)
404 kvm_inject_gp(vcpu, 0);
405 else
406 kvm_x86_ops->skip_emulated_instruction(vcpu);
407}
408EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 409
6389ee94 410void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 411{
412 ++vcpu->stat.pf_guest;
6389ee94
AK		 413 vcpu->arch.cr2 = fault->address;
414 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 415}
27d6c865 416EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 417
ef54bcfe 418static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 419{
6389ee94
AK		 420 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
421 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 422 else
6389ee94 423 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 424
425 return fault->nested_page_fault;
d4f8cf66
JR		 426}
427
3419ffc8
SY		 428void kvm_inject_nmi(struct kvm_vcpu *vcpu)
429{
7460fb4a
AK		 430 atomic_inc(&vcpu->arch.nmi_queued);
431 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 432}
433EXPORT_SYMBOL_GPL(kvm_inject_nmi);
434
298101da
AK		 435void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
436{
ce7ddec4 437 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 438}
439EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
440
ce7ddec4
JR		 441void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442{
443 kvm_multiple_exception(vcpu, nr, true, error_code, true);
444}
445EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
446
0a79b009
AK		 447/*
448 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
449 * a #GP and return false.
450 */
451bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 452{
0a79b009
AK		 453 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
454 return true;
455 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
456 return false;
298101da 457}
0a79b009 458EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 459
16f8a6f9
NA		 460bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
461{
462 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
463 return true;
464
465 kvm_queue_exception(vcpu, UD_VECTOR);
466 return false;
467}
468EXPORT_SYMBOL_GPL(kvm_require_dr);
469
ec92fe44
JR		 470/*
471 * This function will be used to read from the physical memory of the currently
472 * running guest. The difference to kvm_read_guest_page is that this function
473 * can read from guest physical or from the guest's guest physical memory.
474 */
475int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
476 gfn_t ngfn, void *data, int offset, int len,
477 u32 access)
478{
54987b7a 479 struct x86_exception exception;
ec92fe44
JR		 480 gfn_t real_gfn;
481 gpa_t ngpa;
482
483 ngpa = gfn_to_gpa(ngfn);
54987b7a 484 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 485 if (real_gfn == UNMAPPED_GVA)
486 return -EFAULT;
487
488 real_gfn = gpa_to_gfn(real_gfn);
489
490 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
491}
492EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
493
3d06b8bf
JR		 494int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
495 void *data, int offset, int len, u32 access)
496{
497 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
498 data, offset, len, access);
499}
500
a03490ed
CO		 501/*
502 * Load the pae pdptrs. Return true is they are all valid.
503 */
ff03a073 504int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 505{
506 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
507 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
508 int i;
509 int ret;
ff03a073 510 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 511
ff03a073
JR		 512 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
513 offset * sizeof(u64), sizeof(pdpte),
514 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 515 if (ret < 0) {
516 ret = 0;
517 goto out;
518 }
519 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 520 if (is_present_gpte(pdpte[i]) &&
20c466b5 521 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 522 ret = 0;
523 goto out;
524 }
525 }
526 ret = 1;
527
ff03a073 528 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 529 __set_bit(VCPU_EXREG_PDPTR,
530 (unsigned long *)&vcpu->arch.regs_avail);
531 __set_bit(VCPU_EXREG_PDPTR,
532 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 533out:
a03490ed
CO		 534
535 return ret;
536}
cc4b6871 537EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 538
d835dfec
AK		 539static bool pdptrs_changed(struct kvm_vcpu *vcpu)
540{
ff03a073 541 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 542 bool changed = true;
3d06b8bf
JR		 543 int offset;
544 gfn_t gfn;
d835dfec
AK		 545 int r;
546
547 if (is_long_mode(vcpu) || !is_pae(vcpu))
548 return false;
549
6de4f3ad
AK		 550 if (!test_bit(VCPU_EXREG_PDPTR,
551 (unsigned long *)&vcpu->arch.regs_avail))
552 return true;
553
9f8fe504
AK		 554 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
555 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 556 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
557 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 558 if (r < 0)
559 goto out;
ff03a073 560 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 561out:
d835dfec
AK		 562
563 return changed;
564}
565
49a9b07e 566int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 567{
aad82703
SY		 568 unsigned long old_cr0 = kvm_read_cr0(vcpu);
569 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
570 X86_CR0_CD | X86_CR0_NW;
571
f9a48e6a
AK		 572 cr0 |= X86_CR0_ET;
573
ab344828 574#ifdef CONFIG_X86_64
0f12244f
GN		 575 if (cr0 & 0xffffffff00000000UL)
576 return 1;
ab344828
GN		 577#endif
578
579 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 580
0f12244f
GN		 581 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
582 return 1;
a03490ed 583
0f12244f
GN		 584 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
585 return 1;
a03490ed
CO		 586
587 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
588#ifdef CONFIG_X86_64
f6801dff 589 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 590 int cs_db, cs_l;
591
0f12244f
GN		 592 if (!is_pae(vcpu))
593 return 1;
a03490ed 594 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 595 if (cs_l)
596 return 1;
a03490ed
CO		 597 } else
598#endif
ff03a073 599 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 600 kvm_read_cr3(vcpu)))
0f12244f 601 return 1;
a03490ed
CO		 602 }
603
ad756a16
MJ		 604 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
605 return 1;
606
a03490ed 607 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 608
d170c419 609 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 610 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 611 kvm_async_pf_hash_reset(vcpu);
612 }
e5f3f027 613
aad82703
SY		 614 if ((cr0 ^ old_cr0) & update_bits)
615 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 616 return 0;
617}
2d3ad1f4 618EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 619
2d3ad1f4 620void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 621{
49a9b07e 622 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 623}
2d3ad1f4 624EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 625
42bdf991
MT		 626static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
627{
628 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
629 !vcpu->guest_xcr0_loaded) {
630 /* kvm_set_xcr() also depends on this */
631 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
632 vcpu->guest_xcr0_loaded = 1;
633 }
634}
635
636static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
637{
638 if (vcpu->guest_xcr0_loaded) {
639 if (vcpu->arch.xcr0 != host_xcr0)
640 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
641 vcpu->guest_xcr0_loaded = 0;
642 }
643}
644
2acf923e
DC		 645int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
646{
56c103ec
LJ		 647 u64 xcr0 = xcr;
648 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 649 u64 valid_bits;
2acf923e
DC		 650
651 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
652 if (index != XCR_XFEATURE_ENABLED_MASK)
653 return 1;
2acf923e
DC		 654 if (!(xcr0 & XSTATE_FP))
655 return 1;
656 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
657 return 1;
46c34cb0
PB		 658
659 /*
660 * Do not allow the guest to set bits that we do not support
661 * saving. However, xcr0 bit 0 is always set, even if the
662 * emulated CPU does not support XSAVE (see fx_init).
663 */
664 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
665 if (xcr0 & ~valid_bits)
2acf923e 666 return 1;
46c34cb0 667
390bd528
LJ		 668 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
669 return 1;
670
612263b3
CP		 671 if (xcr0 & XSTATE_AVX512) {
672 if (!(xcr0 & XSTATE_YMM))
673 return 1;
674 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
675 return 1;
676 }
42bdf991 677 kvm_put_guest_xcr0(vcpu);
2acf923e 678 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 679
680 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
681 kvm_update_cpuid(vcpu);
2acf923e
DC		 682 return 0;
683}
684
685int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
686{
764bcbc5
Z		 687 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
688 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 689 kvm_inject_gp(vcpu, 0);
690 return 1;
691 }
692 return 0;
693}
694EXPORT_SYMBOL_GPL(kvm_set_xcr);
695
a83b29c6 696int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 697{
fc78f519 698 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 699 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
700 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 701 if (cr4 & CR4_RESERVED_BITS)
702 return 1;
a03490ed 703
2acf923e
DC		 704 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
705 return 1;
706
c68b734f
YW		 707 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
708 return 1;
709
97ec8c06
FW		 710 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
711 return 1;
712
afcbf13f 713 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 714 return 1;
715
a03490ed 716 if (is_long_mode(vcpu)) {
0f12244f
GN		 717 if (!(cr4 & X86_CR4_PAE))
718 return 1;
a2edf57f
AK		 719 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
720 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 721 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
722 kvm_read_cr3(vcpu)))
0f12244f
GN		 723 return 1;
724
ad756a16
MJ		 725 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
726 if (!guest_cpuid_has_pcid(vcpu))
727 return 1;
728
729 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
730 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
731 return 1;
732 }
733
5e1746d6 734 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 735 return 1;
a03490ed 736
ad756a16
MJ		 737 if (((cr4 ^ old_cr4) & pdptr_bits) ||
738 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 739 kvm_mmu_reset_context(vcpu);
0f12244f 740
97ec8c06
FW		 741 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
742 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
743
2acf923e 744 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 745 kvm_update_cpuid(vcpu);
2acf923e 746
0f12244f
GN		 747 return 0;
748}
2d3ad1f4 749EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 750
2390218b 751int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 752{
9d88fca7
NA		 753 cr3 &= ~CR3_PCID_INVD;
754
9f8fe504 755 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 756 kvm_mmu_sync_roots(vcpu);
77c3913b 757 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 758 return 0;
d835dfec
AK		 759 }
760
a03490ed 761 if (is_long_mode(vcpu)) {
d9f89b88
JK		 762 if (cr3 & CR3_L_MODE_RESERVED_BITS)
763 return 1;
764 } else if (is_pae(vcpu) && is_paging(vcpu) &&
765 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 766 return 1;
a03490ed 767
0f12244f 768 vcpu->arch.cr3 = cr3;
aff48baa 769 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 770 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 771 return 0;
772}
2d3ad1f4 773EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 774
eea1cff9 775int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 776{
0f12244f
GN		 777 if (cr8 & CR8_RESERVED_BITS)
778 return 1;
a03490ed
CO		 779 if (irqchip_in_kernel(vcpu->kvm))
780 kvm_lapic_set_tpr(vcpu, cr8);
781 else
ad312c7c 782 vcpu->arch.cr8 = cr8;
0f12244f
GN		 783 return 0;
784}
2d3ad1f4 785EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 786
2d3ad1f4 787unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 788{
789 if (irqchip_in_kernel(vcpu->kvm))
790 return kvm_lapic_get_cr8(vcpu);
791 else
ad312c7c 792 return vcpu->arch.cr8;
a03490ed 793}
2d3ad1f4 794EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 795
73aaf249
JK		 796static void kvm_update_dr6(struct kvm_vcpu *vcpu)
797{
798 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
799 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
800}
801
c8639010
JK		 802static void kvm_update_dr7(struct kvm_vcpu *vcpu)
803{
804 unsigned long dr7;
805
806 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
807 dr7 = vcpu->arch.guest_debug_dr7;
808 else
809 dr7 = vcpu->arch.dr7;
810 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 811 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
812 if (dr7 & DR7_BP_EN_MASK)
813 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 814}
815
6f43ed01
NA		 816static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
817{
818 u64 fixed = DR6_FIXED_1;
819
820 if (!guest_cpuid_has_rtm(vcpu))
821 fixed |= DR6_RTM;
822 return fixed;
823}
824
338dbc97 825static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 826{
827 switch (dr) {
828 case 0 ... 3:
829 vcpu->arch.db[dr] = val;
830 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
831 vcpu->arch.eff_db[dr] = val;
832 break;
833 case 4:
020df079
GN		 834 /* fall through */
835 case 6:
338dbc97
GN		 836 if (val & 0xffffffff00000000ULL)
837 return -1; /* #GP */
6f43ed01 838 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 839 kvm_update_dr6(vcpu);
020df079
GN		 840 break;
841 case 5:
020df079
GN		 842 /* fall through */
843 default: /* 7 */
338dbc97
GN		 844 if (val & 0xffffffff00000000ULL)
845 return -1; /* #GP */
020df079 846 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 847 kvm_update_dr7(vcpu);
020df079
GN		 848 break;
849 }
850
851 return 0;
852}
338dbc97
GN		 853
854int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
855{
16f8a6f9 856 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 857 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 858 return 1;
859 }
860 return 0;
338dbc97 861}
020df079
GN		 862EXPORT_SYMBOL_GPL(kvm_set_dr);
863
16f8a6f9 864int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 865{
866 switch (dr) {
867 case 0 ... 3:
868 *val = vcpu->arch.db[dr];
869 break;
870 case 4:
020df079
GN		 871 /* fall through */
872 case 6:
73aaf249
JK		 873 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
874 *val = vcpu->arch.dr6;
875 else
876 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 877 break;
878 case 5:
020df079
GN		 879 /* fall through */
880 default: /* 7 */
881 *val = vcpu->arch.dr7;
882 break;
883 }
338dbc97
GN		 884 return 0;
885}
020df079
GN		 886EXPORT_SYMBOL_GPL(kvm_get_dr);
887
022cd0e8
AK		 888bool kvm_rdpmc(struct kvm_vcpu *vcpu)
889{
890 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
891 u64 data;
892 int err;
893
894 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
895 if (err)
896 return err;
897 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
898 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
899 return err;
900}
901EXPORT_SYMBOL_GPL(kvm_rdpmc);
902
043405e1
CO		 903/*
904 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
905 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
906 *
907 * This list is modified at module load time to reflect the
e3267cbb
GC		 908 * capabilities of the host cpu. This capabilities test skips MSRs that are
909 * kvm-specific. Those are put in the beginning of the list.
043405e1 910 */
e3267cbb 911
e984097b 912#define KVM_SAVE_MSRS_BEGIN 12
043405e1 913static u32 msrs_to_save[] = {
e3267cbb 914 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 915 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 916 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 917 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 918 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 919 MSR_KVM_PV_EOI_EN,
043405e1 920 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 921 MSR_STAR,
043405e1
CO		 922#ifdef CONFIG_X86_64
923 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
924#endif
b3897a49 925 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 926 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 927};
928
929static unsigned num_msrs_to_save;
930
f1d24831 931static const u32 emulated_msrs[] = {
ba904635 932 MSR_IA32_TSC_ADJUST,
a3e06bbe 933 MSR_IA32_TSCDEADLINE,
043405e1 934 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 935 MSR_IA32_MCG_STATUS,
936 MSR_IA32_MCG_CTL,
043405e1
CO		 937};
938
384bb783 939bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 940{
b69e8cae 941 if (efer & efer_reserved_bits)
384bb783 942 return false;
15c4a640 943
1b2fd70c
AG		 944 if (efer & EFER_FFXSR) {
945 struct kvm_cpuid_entry2 *feat;
946
947 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 948 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 949 return false;
1b2fd70c
AG		 950 }
951
d8017474
AG		 952 if (efer & EFER_SVME) {
953 struct kvm_cpuid_entry2 *feat;
954
955 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 956 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 957 return false;
d8017474
AG		 958 }
959
384bb783
JK		 960 return true;
961}
962EXPORT_SYMBOL_GPL(kvm_valid_efer);
963
964static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
965{
966 u64 old_efer = vcpu->arch.efer;
967
968 if (!kvm_valid_efer(vcpu, efer))
969 return 1;
970
971 if (is_paging(vcpu)
972 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
973 return 1;
974
15c4a640 975 efer &= ~EFER_LMA;
f6801dff 976 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 977
a3d204e2
SY		 978 kvm_x86_ops->set_efer(vcpu, efer);
979
aad82703
SY		 980 /* Update reserved bits */
981 if ((efer ^ old_efer) & EFER_NX)
982 kvm_mmu_reset_context(vcpu);
983
b69e8cae 984 return 0;
15c4a640
CO		 985}
986
f2b4b7dd
JR		 987void kvm_enable_efer_bits(u64 mask)
988{
989 efer_reserved_bits &= ~mask;
990}
991EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
992
15c4a640
CO		 993/*
994 * Writes msr value into into the appropriate "register".
995 * Returns 0 on success, non-0 otherwise.
996 * Assumes vcpu_load() was already called.
997 */
8fe8ab46 998int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 999{
854e8bb1
NA		 1000 switch (msr->index) {
1001 case MSR_FS_BASE:
1002 case MSR_GS_BASE:
1003 case MSR_KERNEL_GS_BASE:
1004 case MSR_CSTAR:
1005 case MSR_LSTAR:
1006 if (is_noncanonical_address(msr->data))
1007 return 1;
1008 break;
1009 case MSR_IA32_SYSENTER_EIP:
1010 case MSR_IA32_SYSENTER_ESP:
1011 /*
1012 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1013 * non-canonical address is written on Intel but not on
1014 * AMD (which ignores the top 32-bits, because it does
1015 * not implement 64-bit SYSENTER).
1016 *
1017 * 64-bit code should hence be able to write a non-canonical
1018 * value on AMD. Making the address canonical ensures that
1019 * vmentry does not fail on Intel after writing a non-canonical
1020 * value, and that something deterministic happens if the guest
1021 * invokes 64-bit SYSENTER.
1022 */
1023 msr->data = get_canonical(msr->data);
1024 }
8fe8ab46 1025 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1026}
854e8bb1 1027EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1028
313a3dc7
CO		 1029/*
1030 * Adapt set_msr() to msr_io()'s calling convention
1031 */
1032static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1033{
8fe8ab46
WA		 1034 struct msr_data msr;
1035
1036 msr.data = *data;
1037 msr.index = index;
1038 msr.host_initiated = true;
1039 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1040}
1041
16e8d74d
MT		 1042#ifdef CONFIG_X86_64
1043struct pvclock_gtod_data {
1044 seqcount_t seq;
1045
1046 struct { /* extract of a clocksource struct */
1047 int vclock_mode;
1048 cycle_t cycle_last;
1049 cycle_t mask;
1050 u32 mult;
1051 u32 shift;
1052 } clock;
1053
cbcf2dd3
TG		 1054 u64 boot_ns;
1055 u64 nsec_base;
16e8d74d
MT		 1056};
1057
1058static struct pvclock_gtod_data pvclock_gtod_data;
1059
1060static void update_pvclock_gtod(struct timekeeper *tk)
1061{
1062 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1063 u64 boot_ns;
1064
d28ede83 1065 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1066
1067 write_seqcount_begin(&vdata->seq);
1068
1069 /* copy pvclock gtod data */
d28ede83
TG		 1070 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1071 vdata->clock.cycle_last = tk->tkr.cycle_last;
1072 vdata->clock.mask = tk->tkr.mask;
1073 vdata->clock.mult = tk->tkr.mult;
1074 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1075
cbcf2dd3 1076 vdata->boot_ns = boot_ns;
d28ede83 1077 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1078
1079 write_seqcount_end(&vdata->seq);
1080}
1081#endif
1082
1083
18068523
GOC		 1084static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1085{
9ed3c444
AK		 1086 int version;
1087 int r;
50d0a0f9 1088 struct pvclock_wall_clock wc;
923de3cf 1089 struct timespec boot;
18068523
GOC		 1090
1091 if (!wall_clock)
1092 return;
1093
9ed3c444
AK		 1094 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1095 if (r)
1096 return;
1097
1098 if (version & 1)
1099 ++version; /* first time write, random junk */
1100
1101 ++version;
18068523 1102
18068523
GOC		 1103 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1104
50d0a0f9
GH		 1105 /*
1106 * The guest calculates current wall clock time by adding
34c238a1 1107 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1108 * wall clock specified here. guest system time equals host
1109 * system time for us, thus we must fill in host boot time here.
1110 */
923de3cf 1111 getboottime(&boot);
50d0a0f9 1112
4b648665
BR		 1113 if (kvm->arch.kvmclock_offset) {
1114 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1115 boot = timespec_sub(boot, ts);
1116 }
50d0a0f9
GH		 1117 wc.sec = boot.tv_sec;
1118 wc.nsec = boot.tv_nsec;
1119 wc.version = version;
18068523
GOC		 1120
1121 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1122
1123 version++;
1124 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1125}
1126
50d0a0f9
GH		 1127static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1128{
1129 uint32_t quotient, remainder;
1130
1131 /* Don't try to replace with do_div(), this one calculates
1132 * "(dividend << 32) / divisor" */
1133 __asm__ ( "divl %4"
1134 : "=a" (quotient), "=d" (remainder)
1135 : "0" (0), "1" (dividend), "r" (divisor) );
1136 return quotient;
1137}
1138
5f4e3f88
ZA		 1139static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1140 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1141{
5f4e3f88 1142 uint64_t scaled64;
50d0a0f9
GH		 1143 int32_t shift = 0;
1144 uint64_t tps64;
1145 uint32_t tps32;
1146
5f4e3f88
ZA		 1147 tps64 = base_khz * 1000LL;
1148 scaled64 = scaled_khz * 1000LL;
50933623 1149 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1150 tps64 >>= 1;
1151 shift--;
1152 }
1153
1154 tps32 = (uint32_t)tps64;
50933623
JK		 1155 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1156 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1157 scaled64 >>= 1;
1158 else
1159 tps32 <<= 1;
50d0a0f9
GH		 1160 shift++;
1161 }
1162
5f4e3f88
ZA		 1163 *pshift = shift;
1164 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1165
5f4e3f88
ZA		 1166 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1167 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1168}
1169
759379dd
ZA		 1170static inline u64 get_kernel_ns(void)
1171{
bb0b5812 1172 return ktime_get_boot_ns();
50d0a0f9
GH		 1173}
1174
d828199e 1175#ifdef CONFIG_X86_64
16e8d74d 1176static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1177#endif
16e8d74d 1178
c8076604 1179static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1180unsigned long max_tsc_khz;
c8076604 1181
cc578287 1182static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1183{
cc578287
ZA		 1184 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1185 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1186}
1187
cc578287 1188static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1189{
cc578287
ZA		 1190 u64 v = (u64)khz * (1000000 + ppm);
1191 do_div(v, 1000000);
1192 return v;
1e993611
JR		 1193}
1194
cc578287 1195static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1196{
cc578287
ZA		 1197 u32 thresh_lo, thresh_hi;
1198 int use_scaling = 0;
217fc9cf 1199
03ba32ca
MT		 1200 /* tsc_khz can be zero if TSC calibration fails */
1201 if (this_tsc_khz == 0)
1202 return;
1203
c285545f
ZA		 1204 /* Compute a scale to convert nanoseconds in TSC cycles */
1205 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1206 &vcpu->arch.virtual_tsc_shift,
1207 &vcpu->arch.virtual_tsc_mult);
1208 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1209
1210 /*
1211 * Compute the variation in TSC rate which is acceptable
1212 * within the range of tolerance and decide if the
1213 * rate being applied is within that bounds of the hardware
1214 * rate. If so, no scaling or compensation need be done.
1215 */
1216 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1217 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1218 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1219 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1220 use_scaling = 1;
1221 }
1222 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1223}
1224
1225static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1226{
e26101b1 1227 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1228 vcpu->arch.virtual_tsc_mult,
1229 vcpu->arch.virtual_tsc_shift);
e26101b1 1230 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1231 return tsc;
1232}
1233
b48aa97e
MT		 1234void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1235{
1236#ifdef CONFIG_X86_64
1237 bool vcpus_matched;
b48aa97e
MT		 1238 struct kvm_arch *ka = &vcpu->kvm->arch;
1239 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1240
1241 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1242 atomic_read(&vcpu->kvm->online_vcpus));
1243
7f187922
MT		 1244 /*
1245 * Once the masterclock is enabled, always perform request in
1246 * order to update it.
1247 *
1248 * In order to enable masterclock, the host clocksource must be TSC
1249 * and the vcpus need to have matched TSCs. When that happens,
1250 * perform request to enable masterclock.
1251 */
1252 if (ka->use_master_clock ||
1253 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1254 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1255
1256 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1257 atomic_read(&vcpu->kvm->online_vcpus),
1258 ka->use_master_clock, gtod->clock.vclock_mode);
1259#endif
1260}
1261
ba904635
WA		 1262static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1263{
1264 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1265 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1266}
1267
8fe8ab46 1268void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1269{
1270 struct kvm *kvm = vcpu->kvm;
f38e098f 1271 u64 offset, ns, elapsed;
99e3e30a 1272 unsigned long flags;
02626b6a 1273 s64 usdiff;
b48aa97e 1274 bool matched;
0d3da0d2 1275 bool already_matched;
8fe8ab46 1276 u64 data = msr->data;
99e3e30a 1277
038f8c11 1278 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1279 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1280 ns = get_kernel_ns();
f38e098f 1281 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1282
03ba32ca 1283 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1284 int faulted = 0;
1285
03ba32ca
MT		 1286 /* n.b - signed multiplication and division required */
1287 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1288#ifdef CONFIG_X86_64
03ba32ca 1289 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1290#else
03ba32ca 1291 /* do_div() only does unsigned */
8915aa27
MT		 1292 asm("1: idivl %[divisor]\n"
1293 "2: xor %%edx, %%edx\n"
1294 " movl $0, %[faulted]\n"
1295 "3:\n"
1296 ".section .fixup,\"ax\"\n"
1297 "4: movl $1, %[faulted]\n"
1298 " jmp 3b\n"
1299 ".previous\n"
1300
1301 _ASM_EXTABLE(1b, 4b)
1302
1303 : "=A"(usdiff), [faulted] "=r" (faulted)
1304 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1305
5d3cb0f6 1306#endif
03ba32ca
MT		 1307 do_div(elapsed, 1000);
1308 usdiff -= elapsed;
1309 if (usdiff < 0)
1310 usdiff = -usdiff;
8915aa27
MT		 1311
1312 /* idivl overflow => difference is larger than USEC_PER_SEC */
1313 if (faulted)
1314 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1315 } else
1316 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1317
1318 /*
5d3cb0f6
ZA		 1319 * Special case: TSC write with a small delta (1 second) of virtual
1320 * cycle time against real time is interpreted as an attempt to
1321 * synchronize the CPU.
1322 *
1323 * For a reliable TSC, we can match TSC offsets, and for an unstable
1324 * TSC, we add elapsed time in this computation. We could let the
1325 * compensation code attempt to catch up if we fall behind, but
1326 * it's better to try to match offsets from the beginning.
1327 */
02626b6a 1328 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1329 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1330 if (!check_tsc_unstable()) {
e26101b1 1331 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1332 pr_debug("kvm: matched tsc offset for %llu\n", data);
1333 } else {
857e4099 1334 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1335 data += delta;
1336 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1337 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1338 }
b48aa97e 1339 matched = true;
0d3da0d2 1340 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1341 } else {
1342 /*
1343 * We split periods of matched TSC writes into generations.
1344 * For each generation, we track the original measured
1345 * nanosecond time, offset, and write, so if TSCs are in
1346 * sync, we can match exact offset, and if not, we can match
4a969980 1347 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1348 *
1349 * These values are tracked in kvm->arch.cur_xxx variables.
1350 */
1351 kvm->arch.cur_tsc_generation++;
1352 kvm->arch.cur_tsc_nsec = ns;
1353 kvm->arch.cur_tsc_write = data;
1354 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1355 matched = false;
0d3da0d2 1356 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1357 kvm->arch.cur_tsc_generation, data);
f38e098f 1358 }
e26101b1
ZA		 1359
1360 /*
1361 * We also track th most recent recorded KHZ, write and time to
1362 * allow the matching interval to be extended at each write.
1363 */
f38e098f
ZA		 1364 kvm->arch.last_tsc_nsec = ns;
1365 kvm->arch.last_tsc_write = data;
5d3cb0f6 1366 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1367
b183aa58 1368 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1369
1370 /* Keep track of which generation this VCPU has synchronized to */
1371 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1372 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1373 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1374
ba904635
WA		 1375 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1376 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1377 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1378 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1379
1380 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1381 if (!matched) {
b48aa97e 1382 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1383 } else if (!already_matched) {
1384 kvm->arch.nr_vcpus_matched_tsc++;
1385 }
b48aa97e
MT		 1386
1387 kvm_track_tsc_matching(vcpu);
1388 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1389}
e26101b1 1390
99e3e30a
ZA		 1391EXPORT_SYMBOL_GPL(kvm_write_tsc);
1392
d828199e
MT		 1393#ifdef CONFIG_X86_64
1394
1395static cycle_t read_tsc(void)
1396{
1397 cycle_t ret;
1398 u64 last;
1399
1400 /*
1401 * Empirically, a fence (of type that depends on the CPU)
1402 * before rdtsc is enough to ensure that rdtsc is ordered
1403 * with respect to loads. The various CPU manuals are unclear
1404 * as to whether rdtsc can be reordered with later loads,
1405 * but no one has ever seen it happen.
1406 */
1407 rdtsc_barrier();
1408 ret = (cycle_t)vget_cycles();
1409
1410 last = pvclock_gtod_data.clock.cycle_last;
1411
1412 if (likely(ret >= last))
1413 return ret;
1414
1415 /*
1416 * GCC likes to generate cmov here, but this branch is extremely
1417 * predictable (it's just a funciton of time and the likely is
1418 * very likely) and there's a data dependence, so force GCC
1419 * to generate a branch instead. I don't barrier() because
1420 * we don't actually need a barrier, and if this function
1421 * ever gets inlined it will generate worse code.
1422 */
1423 asm volatile ("");
1424 return last;
1425}
1426
1427static inline u64 vgettsc(cycle_t *cycle_now)
1428{
1429 long v;
1430 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1431
1432 *cycle_now = read_tsc();
1433
1434 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1435 return v * gtod->clock.mult;
1436}
1437
cbcf2dd3 1438static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1439{
cbcf2dd3 1440 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1441 unsigned long seq;
d828199e 1442 int mode;
cbcf2dd3 1443 u64 ns;
d828199e 1444
d828199e
MT		 1445 do {
1446 seq = read_seqcount_begin(&gtod->seq);
1447 mode = gtod->clock.vclock_mode;
cbcf2dd3 1448 ns = gtod->nsec_base;
d828199e
MT		 1449 ns += vgettsc(cycle_now);
1450 ns >>= gtod->clock.shift;
cbcf2dd3 1451 ns += gtod->boot_ns;
d828199e 1452 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1453 *t = ns;
d828199e
MT		 1454
1455 return mode;
1456}
1457
1458/* returns true if host is using tsc clocksource */
1459static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1460{
d828199e
MT		 1461 /* checked again under seqlock below */
1462 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1463 return false;
1464
cbcf2dd3 1465 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1466}
1467#endif
1468
1469/*
1470 *
b48aa97e
MT		 1471 * Assuming a stable TSC across physical CPUS, and a stable TSC
1472 * across virtual CPUs, the following condition is possible.
1473 * Each numbered line represents an event visible to both
d828199e
MT		 1474 * CPUs at the next numbered event.
1475 *
1476 * "timespecX" represents host monotonic time. "tscX" represents
1477 * RDTSC value.
1478 *
1479 * VCPU0 on CPU0 | VCPU1 on CPU1
1480 *
1481 * 1. read timespec0,tsc0
1482 * 2. | timespec1 = timespec0 + N
1483 * | tsc1 = tsc0 + M
1484 * 3. transition to guest | transition to guest
1485 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1486 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1487 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1488 *
1489 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1490 *
1491 * - ret0 < ret1
1492 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1493 * ...
1494 * - 0 < N - M => M < N
1495 *
1496 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1497 * always the case (the difference between two distinct xtime instances
1498 * might be smaller then the difference between corresponding TSC reads,
1499 * when updating guest vcpus pvclock areas).
1500 *
1501 * To avoid that problem, do not allow visibility of distinct
1502 * system_timestamp/tsc_timestamp values simultaneously: use a master
1503 * copy of host monotonic time values. Update that master copy
1504 * in lockstep.
1505 *
b48aa97e 1506 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1507 *
1508 */
1509
1510static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1511{
1512#ifdef CONFIG_X86_64
1513 struct kvm_arch *ka = &kvm->arch;
1514 int vclock_mode;
b48aa97e
MT		 1515 bool host_tsc_clocksource, vcpus_matched;
1516
1517 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1518 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1519
1520 /*
1521 * If the host uses TSC clock, then passthrough TSC as stable
1522 * to the guest.
1523 */
b48aa97e 1524 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1525 &ka->master_kernel_ns,
1526 &ka->master_cycle_now);
1527
16a96021
MT		 1528 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1529 && !backwards_tsc_observed;
b48aa97e 1530
d828199e
MT		 1531 if (ka->use_master_clock)
1532 atomic_set(&kvm_guest_has_master_clock, 1);
1533
1534 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1535 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1536 vcpus_matched);
d828199e
MT		 1537#endif
1538}
1539
2e762ff7
MT		 1540static void kvm_gen_update_masterclock(struct kvm *kvm)
1541{
1542#ifdef CONFIG_X86_64
1543 int i;
1544 struct kvm_vcpu *vcpu;
1545 struct kvm_arch *ka = &kvm->arch;
1546
1547 spin_lock(&ka->pvclock_gtod_sync_lock);
1548 kvm_make_mclock_inprogress_request(kvm);
1549 /* no guest entries from this point */
1550 pvclock_update_vm_gtod_copy(kvm);
1551
1552 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1553 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1554
1555 /* guest entries allowed */
1556 kvm_for_each_vcpu(i, vcpu, kvm)
1557 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1558
1559 spin_unlock(&ka->pvclock_gtod_sync_lock);
1560#endif
1561}
1562
34c238a1 1563static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1564{
d828199e 1565 unsigned long flags, this_tsc_khz;
18068523 1566 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1567 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1568 s64 kernel_ns;
d828199e 1569 u64 tsc_timestamp, host_tsc;
0b79459b 1570 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1571 u8 pvclock_flags;
d828199e
MT		 1572 bool use_master_clock;
1573
1574 kernel_ns = 0;
1575 host_tsc = 0;
18068523 1576
d828199e
MT		 1577 /*
1578 * If the host uses TSC clock, then passthrough TSC as stable
1579 * to the guest.
1580 */
1581 spin_lock(&ka->pvclock_gtod_sync_lock);
1582 use_master_clock = ka->use_master_clock;
1583 if (use_master_clock) {
1584 host_tsc = ka->master_cycle_now;
1585 kernel_ns = ka->master_kernel_ns;
1586 }
1587 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1588
1589 /* Keep irq disabled to prevent changes to the clock */
1590 local_irq_save(flags);
89cbc767 1591 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1592 if (unlikely(this_tsc_khz == 0)) {
1593 local_irq_restore(flags);
1594 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1595 return 1;
1596 }
d828199e
MT		 1597 if (!use_master_clock) {
1598 host_tsc = native_read_tsc();
1599 kernel_ns = get_kernel_ns();
1600 }
1601
1602 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1603
c285545f
ZA		 1604 /*
1605 * We may have to catch up the TSC to match elapsed wall clock
1606 * time for two reasons, even if kvmclock is used.
1607 * 1) CPU could have been running below the maximum TSC rate
1608 * 2) Broken TSC compensation resets the base at each VCPU
1609 * entry to avoid unknown leaps of TSC even when running
1610 * again on the same CPU. This may cause apparent elapsed
1611 * time to disappear, and the guest to stand still or run
1612 * very slowly.
1613 */
1614 if (vcpu->tsc_catchup) {
1615 u64 tsc = compute_guest_tsc(v, kernel_ns);
1616 if (tsc > tsc_timestamp) {
f1e2b260 1617 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1618 tsc_timestamp = tsc;
1619 }
50d0a0f9
GH		 1620 }
1621
18068523
GOC		 1622 local_irq_restore(flags);
1623
0b79459b 1624 if (!vcpu->pv_time_enabled)
c285545f 1625 return 0;
18068523 1626
e48672fa 1627 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1628 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1629 &vcpu->hv_clock.tsc_shift,
1630 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1631 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1632 }
1633
1634 /* With all the info we got, fill in the values */
1d5f066e 1635 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1636 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1637 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1638
09a0c3f1
OH		 1639 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1640 &guest_hv_clock, sizeof(guest_hv_clock))))
1641 return 0;
1642
18068523
GOC		 1643 /*
1644 * The interface expects us to write an even number signaling that the
1645 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1646 * state, we just increase by 2 at the end.
18068523 1647 */
09a0c3f1 1648 vcpu->hv_clock.version = guest_hv_clock.version + 2;
78c0337a
MT		 1649
1650 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1651 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1652
1653 if (vcpu->pvclock_set_guest_stopped_request) {
1654 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1655 vcpu->pvclock_set_guest_stopped_request = false;
1656 }
1657
d828199e
MT		 1658 /* If the host uses TSC clocksource, then it is stable */
1659 if (use_master_clock)
1660 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1661
78c0337a
MT		 1662 vcpu->hv_clock.flags = pvclock_flags;
1663
0b79459b
AH		 1664 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1665 &vcpu->hv_clock,
1666 sizeof(vcpu->hv_clock));
8cfdc000 1667 return 0;
c8076604
GH		 1668}
1669
0061d53d
MT		 1670/*
1671 * kvmclock updates which are isolated to a given vcpu, such as
1672 * vcpu->cpu migration, should not allow system_timestamp from
1673 * the rest of the vcpus to remain static. Otherwise ntp frequency
1674 * correction applies to one vcpu's system_timestamp but not
1675 * the others.
1676 *
1677 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1678 * We need to rate-limit these requests though, as they can
1679 * considerably slow guests that have a large number of vcpus.
1680 * The time for a remote vcpu to update its kvmclock is bound
1681 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1682 */
1683
7e44e449
AJ		 1684#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1685
1686static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1687{
1688 int i;
7e44e449
AJ		 1689 struct delayed_work *dwork = to_delayed_work(work);
1690 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1691 kvmclock_update_work);
1692 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1693 struct kvm_vcpu *vcpu;
1694
1695 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1696 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1697 kvm_vcpu_kick(vcpu);
1698 }
1699}
1700
7e44e449
AJ		 1701static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1702{
1703 struct kvm *kvm = v->kvm;
1704
105b21bb 1705 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1706 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1707 KVMCLOCK_UPDATE_DELAY);
1708}
1709
332967a3
AJ		 1710#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1711
1712static void kvmclock_sync_fn(struct work_struct *work)
1713{
1714 struct delayed_work *dwork = to_delayed_work(work);
1715 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1716 kvmclock_sync_work);
1717 struct kvm *kvm = container_of(ka, struct kvm, arch);
1718
1719 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1720 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1721 KVMCLOCK_SYNC_PERIOD);
1722}
1723
9ba075a6
AK		 1724static bool msr_mtrr_valid(unsigned msr)
1725{
1726 switch (msr) {
1727 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1728 case MSR_MTRRfix64K_00000:
1729 case MSR_MTRRfix16K_80000:
1730 case MSR_MTRRfix16K_A0000:
1731 case MSR_MTRRfix4K_C0000:
1732 case MSR_MTRRfix4K_C8000:
1733 case MSR_MTRRfix4K_D0000:
1734 case MSR_MTRRfix4K_D8000:
1735 case MSR_MTRRfix4K_E0000:
1736 case MSR_MTRRfix4K_E8000:
1737 case MSR_MTRRfix4K_F0000:
1738 case MSR_MTRRfix4K_F8000:
1739 case MSR_MTRRdefType:
1740 case MSR_IA32_CR_PAT:
1741 return true;
1742 case 0x2f8:
1743 return true;
1744 }
1745 return false;
1746}
1747
d6289b93
MT		 1748static bool valid_pat_type(unsigned t)
1749{
1750 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1751}
1752
1753static bool valid_mtrr_type(unsigned t)
1754{
1755 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1756}
1757
4566654b 1758bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1759{
1760 int i;
fd275235 1761 u64 mask;
d6289b93
MT		 1762
1763 if (!msr_mtrr_valid(msr))
1764 return false;
1765
1766 if (msr == MSR_IA32_CR_PAT) {
1767 for (i = 0; i < 8; i++)
1768 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1769 return false;
1770 return true;
1771 } else if (msr == MSR_MTRRdefType) {
1772 if (data & ~0xcff)
1773 return false;
1774 return valid_mtrr_type(data & 0xff);
1775 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1776 for (i = 0; i < 8 ; i++)
1777 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1778 return false;
1779 return true;
1780 }
1781
1782 /* variable MTRRs */
adfb5d27
WL		 1783 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1784
fd275235 1785 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1786 if ((msr & 1) == 0) {
adfb5d27 1787 /* MTRR base */
d7a2a246
WL		 1788 if (!valid_mtrr_type(data & 0xff))
1789 return false;
1790 mask |= 0xf00;
1791 } else
1792 /* MTRR mask */
1793 mask |= 0x7ff;
1794 if (data & mask) {
1795 kvm_inject_gp(vcpu, 0);
1796 return false;
1797 }
1798
adfb5d27 1799 return true;
d6289b93 1800}
4566654b 1801EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1802
9ba075a6
AK		 1803static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1804{
0bed3b56
SY		 1805 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1806
4566654b 1807 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1808 return 1;
1809
0bed3b56
SY		 1810 if (msr == MSR_MTRRdefType) {
1811 vcpu->arch.mtrr_state.def_type = data;
1812 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1813 } else if (msr == MSR_MTRRfix64K_00000)
1814 p[0] = data;
1815 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1816 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1817 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1818 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1819 else if (msr == MSR_IA32_CR_PAT)
1820 vcpu->arch.pat = data;
1821 else { /* Variable MTRRs */
1822 int idx, is_mtrr_mask;
1823 u64 *pt;
1824
1825 idx = (msr - 0x200) / 2;
1826 is_mtrr_mask = msr - 0x200 - 2 * idx;
1827 if (!is_mtrr_mask)
1828 pt =
1829 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1830 else
1831 pt =
1832 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1833 *pt = data;
1834 }
1835
1836 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1837 return 0;
1838}
15c4a640 1839
890ca9ae 1840static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1841{
890ca9ae
HY		 1842 u64 mcg_cap = vcpu->arch.mcg_cap;
1843 unsigned bank_num = mcg_cap & 0xff;
1844
15c4a640 1845 switch (msr) {
15c4a640 1846 case MSR_IA32_MCG_STATUS:
890ca9ae 1847 vcpu->arch.mcg_status = data;
15c4a640 1848 break;
c7ac679c 1849 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1850 if (!(mcg_cap & MCG_CTL_P))
1851 return 1;
1852 if (data != 0 && data != ~(u64)0)
1853 return -1;
1854 vcpu->arch.mcg_ctl = data;
1855 break;
1856 default:
1857 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1858 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1859 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1860 /* only 0 or all 1s can be written to IA32_MCi_CTL
1861 * some Linux kernels though clear bit 10 in bank 4 to
1862 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1863 * this to avoid an uncatched #GP in the guest
1864 */
890ca9ae 1865 if ((offset & 0x3) == 0 &&
114be429 1866 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1867 return -1;
1868 vcpu->arch.mce_banks[offset] = data;
1869 break;
1870 }
1871 return 1;
1872 }
1873 return 0;
1874}
1875
ffde22ac
ES		 1876static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1877{
1878 struct kvm *kvm = vcpu->kvm;
1879 int lm = is_long_mode(vcpu);
1880 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1881 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1882 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1883 : kvm->arch.xen_hvm_config.blob_size_32;
1884 u32 page_num = data & ~PAGE_MASK;
1885 u64 page_addr = data & PAGE_MASK;
1886 u8 *page;
1887 int r;
1888
1889 r = -E2BIG;
1890 if (page_num >= blob_size)
1891 goto out;
1892 r = -ENOMEM;
ff5c2c03
SL		 1893 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1894 if (IS_ERR(page)) {
1895 r = PTR_ERR(page);
ffde22ac 1896 goto out;
ff5c2c03 1897 }
ffde22ac
ES		 1898 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1899 goto out_free;
1900 r = 0;
1901out_free:
1902 kfree(page);
1903out:
1904 return r;
1905}
1906
55cd8e5a
GN		 1907static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1908{
1909 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1910}
1911
1912static bool kvm_hv_msr_partition_wide(u32 msr)
1913{
1914 bool r = false;
1915 switch (msr) {
1916 case HV_X64_MSR_GUEST_OS_ID:
1917 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1918 case HV_X64_MSR_REFERENCE_TSC:
1919 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1920 r = true;
1921 break;
1922 }
1923
1924 return r;
1925}
1926
1927static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1928{
1929 struct kvm *kvm = vcpu->kvm;
1930
1931 switch (msr) {
1932 case HV_X64_MSR_GUEST_OS_ID:
1933 kvm->arch.hv_guest_os_id = data;
1934 /* setting guest os id to zero disables hypercall page */
1935 if (!kvm->arch.hv_guest_os_id)
1936 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1937 break;
1938 case HV_X64_MSR_HYPERCALL: {
1939 u64 gfn;
1940 unsigned long addr;
1941 u8 instructions[4];
1942
1943 /* if guest os id is not set hypercall should remain disabled */
1944 if (!kvm->arch.hv_guest_os_id)
1945 break;
1946 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1947 kvm->arch.hv_hypercall = data;
1948 break;
1949 }
1950 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1951 addr = gfn_to_hva(kvm, gfn);
1952 if (kvm_is_error_hva(addr))
1953 return 1;
1954 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1955 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1956 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1957 return 1;
1958 kvm->arch.hv_hypercall = data;
b94b64c9 1959 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1960 break;
1961 }
e984097b
VR		 1962 case HV_X64_MSR_REFERENCE_TSC: {
1963 u64 gfn;
1964 HV_REFERENCE_TSC_PAGE tsc_ref;
1965 memset(&tsc_ref, 0, sizeof(tsc_ref));
1966 kvm->arch.hv_tsc_page = data;
1967 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1968 break;
1969 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1970 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1971 &tsc_ref, sizeof(tsc_ref)))
1972 return 1;
1973 mark_page_dirty(kvm, gfn);
1974 break;
1975 }
55cd8e5a 1976 default:
a737f256
CD		 1977 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1978 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1979 return 1;
1980 }
1981 return 0;
1982}
1983
1984static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1985{
10388a07
GN		 1986 switch (msr) {
1987 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1988 u64 gfn;
10388a07 1989 unsigned long addr;
55cd8e5a 1990
10388a07
GN		 1991 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1992 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1993 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1994 return 1;
10388a07
GN		 1995 break;
1996 }
b3af1e88
VR		 1997 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1998 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1999 if (kvm_is_error_hva(addr))
2000 return 1;
8b0cedff 2001 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2002 return 1;
2003 vcpu->arch.hv_vapic = data;
b3af1e88 2004 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2005 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2006 return 1;
10388a07
GN		 2007 break;
2008 }
2009 case HV_X64_MSR_EOI:
2010 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2011 case HV_X64_MSR_ICR:
2012 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2013 case HV_X64_MSR_TPR:
2014 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2015 default:
a737f256
CD		 2016 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2017 "data 0x%llx\n", msr, data);
10388a07
GN		 2018 return 1;
2019 }
2020
2021 return 0;
55cd8e5a
GN		 2022}
2023
344d9588
GN		 2024static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2025{
2026 gpa_t gpa = data & ~0x3f;
2027
4a969980 2028 /* Bits 2:5 are reserved, Should be zero */
6adba527 2029 if (data & 0x3c)
344d9588
GN		 2030 return 1;
2031
2032 vcpu->arch.apf.msr_val = data;
2033
2034 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2035 kvm_clear_async_pf_completion_queue(vcpu);
2036 kvm_async_pf_hash_reset(vcpu);
2037 return 0;
2038 }
2039
8f964525
AH		 2040 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2041 sizeof(u32)))
344d9588
GN		 2042 return 1;
2043
6adba527 2044 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2045 kvm_async_pf_wakeup_all(vcpu);
2046 return 0;
2047}
2048
12f9a48f
GC		 2049static void kvmclock_reset(struct kvm_vcpu *vcpu)
2050{
0b79459b 2051 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2052}
2053
c9aaa895
GC		 2054static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2055{
2056 u64 delta;
2057
2058 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2059 return;
2060
2061 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2062 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2063 vcpu->arch.st.accum_steal = delta;
2064}
2065
2066static void record_steal_time(struct kvm_vcpu *vcpu)
2067{
2068 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2069 return;
2070
2071 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2072 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2073 return;
2074
2075 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2076 vcpu->arch.st.steal.version += 2;
2077 vcpu->arch.st.accum_steal = 0;
2078
2079 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2080 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2081}
2082
8fe8ab46 2083int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2084{
5753785f 2085 bool pr = false;
8fe8ab46
WA		 2086 u32 msr = msr_info->index;
2087 u64 data = msr_info->data;
5753785f 2088
15c4a640 2089 switch (msr) {
2e32b719
BP		 2090 case MSR_AMD64_NB_CFG:
2091 case MSR_IA32_UCODE_REV:
2092 case MSR_IA32_UCODE_WRITE:
2093 case MSR_VM_HSAVE_PA:
2094 case MSR_AMD64_PATCH_LOADER:
2095 case MSR_AMD64_BU_CFG2:
2096 break;
2097
15c4a640 2098 case MSR_EFER:
b69e8cae 2099 return set_efer(vcpu, data);
8f1589d9
AP		 2100 case MSR_K7_HWCR:
2101 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2102 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2103 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2104 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2105 if (data != 0) {
a737f256
CD		 2106 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2107 data);
8f1589d9
AP		 2108 return 1;
2109 }
15c4a640 2110 break;
f7c6d140
AP		 2111 case MSR_FAM10H_MMIO_CONF_BASE:
2112 if (data != 0) {
a737f256
CD		 2113 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2114 "0x%llx\n", data);
f7c6d140
AP		 2115 return 1;
2116 }
15c4a640 2117 break;
b5e2fec0
AG		 2118 case MSR_IA32_DEBUGCTLMSR:
2119 if (!data) {
2120 /* We support the non-activated case already */
2121 break;
2122 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2123 /* Values other than LBR and BTF are vendor-specific,
2124 thus reserved and should throw a #GP */
2125 return 1;
2126 }
a737f256
CD		 2127 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2128 __func__, data);
b5e2fec0 2129 break;
9ba075a6
AK		 2130 case 0x200 ... 0x2ff:
2131 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2132 case MSR_IA32_APICBASE:
58cb628d 2133 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2134 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2135 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2136 case MSR_IA32_TSCDEADLINE:
2137 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2138 break;
ba904635
WA		 2139 case MSR_IA32_TSC_ADJUST:
2140 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2141 if (!msr_info->host_initiated) {
2142 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2143 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2144 }
2145 vcpu->arch.ia32_tsc_adjust_msr = data;
2146 }
2147 break;
15c4a640 2148 case MSR_IA32_MISC_ENABLE:
ad312c7c 2149 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2150 break;
11c6bffa 2151 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2152 case MSR_KVM_WALL_CLOCK:
2153 vcpu->kvm->arch.wall_clock = data;
2154 kvm_write_wall_clock(vcpu->kvm, data);
2155 break;
11c6bffa 2156 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2157 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2158 u64 gpa_offset;
12f9a48f 2159 kvmclock_reset(vcpu);
18068523
GOC		 2160
2161 vcpu->arch.time = data;
0061d53d 2162 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2163
2164 /* we verify if the enable bit is set... */
2165 if (!(data & 1))
2166 break;
2167
0b79459b 2168 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2169
0b79459b 2170 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2171 &vcpu->arch.pv_time, data & ~1ULL,
2172 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2173 vcpu->arch.pv_time_enabled = false;
2174 else
2175 vcpu->arch.pv_time_enabled = true;
32cad84f 2176
18068523
GOC		 2177 break;
2178 }
344d9588
GN		 2179 case MSR_KVM_ASYNC_PF_EN:
2180 if (kvm_pv_enable_async_pf(vcpu, data))
2181 return 1;
2182 break;
c9aaa895
GC		 2183 case MSR_KVM_STEAL_TIME:
2184
2185 if (unlikely(!sched_info_on()))
2186 return 1;
2187
2188 if (data & KVM_STEAL_RESERVED_MASK)
2189 return 1;
2190
2191 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2192 data & KVM_STEAL_VALID_BITS,
2193 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2194 return 1;
2195
2196 vcpu->arch.st.msr_val = data;
2197
2198 if (!(data & KVM_MSR_ENABLED))
2199 break;
2200
2201 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2202
2203 preempt_disable();
2204 accumulate_steal_time(vcpu);
2205 preempt_enable();
2206
2207 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2208
2209 break;
ae7a2a3f
MT		 2210 case MSR_KVM_PV_EOI_EN:
2211 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2212 return 1;
2213 break;
c9aaa895 2214
890ca9ae
HY		 2215 case MSR_IA32_MCG_CTL:
2216 case MSR_IA32_MCG_STATUS:
81760dcc 2217 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2218 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2219
2220 /* Performance counters are not protected by a CPUID bit,
2221 * so we should check all of them in the generic path for the sake of
2222 * cross vendor migration.
2223 * Writing a zero into the event select MSRs disables them,
2224 * which we perfectly emulate ;-). Any other value should be at least
2225 * reported, some guests depend on them.
2226 */
71db6023
AP		 2227 case MSR_K7_EVNTSEL0:
2228 case MSR_K7_EVNTSEL1:
2229 case MSR_K7_EVNTSEL2:
2230 case MSR_K7_EVNTSEL3:
2231 if (data != 0)
a737f256
CD		 2232 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2233 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2234 break;
2235 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2236 * so we ignore writes to make it happy.
2237 */
71db6023
AP		 2238 case MSR_K7_PERFCTR0:
2239 case MSR_K7_PERFCTR1:
2240 case MSR_K7_PERFCTR2:
2241 case MSR_K7_PERFCTR3:
a737f256
CD		 2242 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2243 "0x%x data 0x%llx\n", msr, data);
71db6023 2244 break;
5753785f
GN		 2245 case MSR_P6_PERFCTR0:
2246 case MSR_P6_PERFCTR1:
2247 pr = true;
2248 case MSR_P6_EVNTSEL0:
2249 case MSR_P6_EVNTSEL1:
2250 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2251 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2252
2253 if (pr || data != 0)
a737f256
CD		 2254 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2255 "0x%x data 0x%llx\n", msr, data);
5753785f 2256 break;
84e0cefa
JS		 2257 case MSR_K7_CLK_CTL:
2258 /*
2259 * Ignore all writes to this no longer documented MSR.
2260 * Writes are only relevant for old K7 processors,
2261 * all pre-dating SVM, but a recommended workaround from
4a969980 2262 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2263 * affected processor models on the command line, hence
2264 * the need to ignore the workaround.
2265 */
2266 break;
55cd8e5a
GN		 2267 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2268 if (kvm_hv_msr_partition_wide(msr)) {
2269 int r;
2270 mutex_lock(&vcpu->kvm->lock);
2271 r = set_msr_hyperv_pw(vcpu, msr, data);
2272 mutex_unlock(&vcpu->kvm->lock);
2273 return r;
2274 } else
2275 return set_msr_hyperv(vcpu, msr, data);
2276 break;
91c9c3ed 2277 case MSR_IA32_BBL_CR_CTL3:
2278 /* Drop writes to this legacy MSR -- see rdmsr
2279 * counterpart for further detail.
2280 */
a737f256 2281 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2282 break;
2b036c6b
BO		 2283 case MSR_AMD64_OSVW_ID_LENGTH:
2284 if (!guest_cpuid_has_osvw(vcpu))
2285 return 1;
2286 vcpu->arch.osvw.length = data;
2287 break;
2288 case MSR_AMD64_OSVW_STATUS:
2289 if (!guest_cpuid_has_osvw(vcpu))
2290 return 1;
2291 vcpu->arch.osvw.status = data;
2292 break;
15c4a640 2293 default:
ffde22ac
ES		 2294 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2295 return xen_hvm_config(vcpu, data);
f5132b01 2296 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2297 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2298 if (!ignore_msrs) {
a737f256
CD		 2299 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2300 msr, data);
ed85c068
AP		 2301 return 1;
2302 } else {
a737f256
CD		 2303 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2304 msr, data);
ed85c068
AP		 2305 break;
2306 }
15c4a640
CO		 2307 }
2308 return 0;
2309}
2310EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2311
2312
2313/*
2314 * Reads an msr value (of 'msr_index') into 'pdata'.
2315 * Returns 0 on success, non-0 otherwise.
2316 * Assumes vcpu_load() was already called.
2317 */
2318int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2319{
2320 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2321}
2322
9ba075a6
AK		 2323static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2324{
0bed3b56
SY		 2325 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2326
9ba075a6
AK		 2327 if (!msr_mtrr_valid(msr))
2328 return 1;
2329
0bed3b56
SY		 2330 if (msr == MSR_MTRRdefType)
2331 *pdata = vcpu->arch.mtrr_state.def_type +
2332 (vcpu->arch.mtrr_state.enabled << 10);
2333 else if (msr == MSR_MTRRfix64K_00000)
2334 *pdata = p[0];
2335 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2336 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2337 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2338 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2339 else if (msr == MSR_IA32_CR_PAT)
2340 *pdata = vcpu->arch.pat;
2341 else { /* Variable MTRRs */
2342 int idx, is_mtrr_mask;
2343 u64 *pt;
2344
2345 idx = (msr - 0x200) / 2;
2346 is_mtrr_mask = msr - 0x200 - 2 * idx;
2347 if (!is_mtrr_mask)
2348 pt =
2349 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2350 else
2351 pt =
2352 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2353 *pdata = *pt;
2354 }
2355
9ba075a6
AK		 2356 return 0;
2357}
2358
890ca9ae 2359static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2360{
2361 u64 data;
890ca9ae
HY		 2362 u64 mcg_cap = vcpu->arch.mcg_cap;
2363 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2364
2365 switch (msr) {
15c4a640
CO		 2366 case MSR_IA32_P5_MC_ADDR:
2367 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2368 data = 0;
2369 break;
15c4a640 2370 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2371 data = vcpu->arch.mcg_cap;
2372 break;
c7ac679c 2373 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2374 if (!(mcg_cap & MCG_CTL_P))
2375 return 1;
2376 data = vcpu->arch.mcg_ctl;
2377 break;
2378 case MSR_IA32_MCG_STATUS:
2379 data = vcpu->arch.mcg_status;
2380 break;
2381 default:
2382 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2383 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2384 u32 offset = msr - MSR_IA32_MC0_CTL;
2385 data = vcpu->arch.mce_banks[offset];
2386 break;
2387 }
2388 return 1;
2389 }
2390 *pdata = data;
2391 return 0;
2392}
2393
55cd8e5a
GN		 2394static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2395{
2396 u64 data = 0;
2397 struct kvm *kvm = vcpu->kvm;
2398
2399 switch (msr) {
2400 case HV_X64_MSR_GUEST_OS_ID:
2401 data = kvm->arch.hv_guest_os_id;
2402 break;
2403 case HV_X64_MSR_HYPERCALL:
2404 data = kvm->arch.hv_hypercall;
2405 break;
e984097b
VR		 2406 case HV_X64_MSR_TIME_REF_COUNT: {
2407 data =
2408 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2409 break;
2410 }
2411 case HV_X64_MSR_REFERENCE_TSC:
2412 data = kvm->arch.hv_tsc_page;
2413 break;
55cd8e5a 2414 default:
a737f256 2415 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2416 return 1;
2417 }
2418
2419 *pdata = data;
2420 return 0;
2421}
2422
2423static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2424{
2425 u64 data = 0;
2426
2427 switch (msr) {
2428 case HV_X64_MSR_VP_INDEX: {
2429 int r;
2430 struct kvm_vcpu *v;
684851a1
TY		 2431 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2432 if (v == vcpu) {
55cd8e5a 2433 data = r;
684851a1
TY		 2434 break;
2435 }
2436 }
55cd8e5a
GN		 2437 break;
2438 }
10388a07
GN		 2439 case HV_X64_MSR_EOI:
2440 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2441 case HV_X64_MSR_ICR:
2442 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2443 case HV_X64_MSR_TPR:
2444 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2445 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2446 data = vcpu->arch.hv_vapic;
2447 break;
55cd8e5a 2448 default:
a737f256 2449 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2450 return 1;
2451 }
2452 *pdata = data;
2453 return 0;
2454}
2455
890ca9ae
HY		 2456int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2457{
2458 u64 data;
2459
2460 switch (msr) {
890ca9ae 2461 case MSR_IA32_PLATFORM_ID:
15c4a640 2462 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2463 case MSR_IA32_DEBUGCTLMSR:
2464 case MSR_IA32_LASTBRANCHFROMIP:
2465 case MSR_IA32_LASTBRANCHTOIP:
2466 case MSR_IA32_LASTINTFROMIP:
2467 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2468 case MSR_K8_SYSCFG:
2469 case MSR_K7_HWCR:
61a6bd67 2470 case MSR_VM_HSAVE_PA:
9e699624 2471 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2472 case MSR_K7_EVNTSEL1:
2473 case MSR_K7_EVNTSEL2:
2474 case MSR_K7_EVNTSEL3:
1f3ee616 2475 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2476 case MSR_K7_PERFCTR1:
2477 case MSR_K7_PERFCTR2:
2478 case MSR_K7_PERFCTR3:
1fdbd48c 2479 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2480 case MSR_AMD64_NB_CFG:
f7c6d140 2481 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2482 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2483 data = 0;
2484 break;
5753785f
GN		 2485 case MSR_P6_PERFCTR0:
2486 case MSR_P6_PERFCTR1:
2487 case MSR_P6_EVNTSEL0:
2488 case MSR_P6_EVNTSEL1:
2489 if (kvm_pmu_msr(vcpu, msr))
2490 return kvm_pmu_get_msr(vcpu, msr, pdata);
2491 data = 0;
2492 break;
742bc670
MT		 2493 case MSR_IA32_UCODE_REV:
2494 data = 0x100000000ULL;
2495 break;
9ba075a6
AK		 2496 case MSR_MTRRcap:
2497 data = 0x500 | KVM_NR_VAR_MTRR;
2498 break;
2499 case 0x200 ... 0x2ff:
2500 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2501 case 0xcd: /* fsb frequency */
2502 data = 3;
2503 break;
7b914098
JS		 2504 /*
2505 * MSR_EBC_FREQUENCY_ID
2506 * Conservative value valid for even the basic CPU models.
2507 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2508 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2509 * and 266MHz for model 3, or 4. Set Core Clock
2510 * Frequency to System Bus Frequency Ratio to 1 (bits
2511 * 31:24) even though these are only valid for CPU
2512 * models > 2, however guests may end up dividing or
2513 * multiplying by zero otherwise.
2514 */
2515 case MSR_EBC_FREQUENCY_ID:
2516 data = 1 << 24;
2517 break;
15c4a640
CO		 2518 case MSR_IA32_APICBASE:
2519 data = kvm_get_apic_base(vcpu);
2520 break;
0105d1a5
GN		 2521 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2522 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2523 break;
a3e06bbe
LJ		 2524 case MSR_IA32_TSCDEADLINE:
2525 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2526 break;
ba904635
WA		 2527 case MSR_IA32_TSC_ADJUST:
2528 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2529 break;
15c4a640 2530 case MSR_IA32_MISC_ENABLE:
ad312c7c 2531 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2532 break;
847f0ad8
AG		 2533 case MSR_IA32_PERF_STATUS:
2534 /* TSC increment by tick */
2535 data = 1000ULL;
2536 /* CPU multiplier */
2537 data |= (((uint64_t)4ULL) << 40);
2538 break;
15c4a640 2539 case MSR_EFER:
f6801dff 2540 data = vcpu->arch.efer;
15c4a640 2541 break;
18068523 2542 case MSR_KVM_WALL_CLOCK:
11c6bffa 2543 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2544 data = vcpu->kvm->arch.wall_clock;
2545 break;
2546 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2547 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2548 data = vcpu->arch.time;
2549 break;
344d9588
GN		 2550 case MSR_KVM_ASYNC_PF_EN:
2551 data = vcpu->arch.apf.msr_val;
2552 break;
c9aaa895
GC		 2553 case MSR_KVM_STEAL_TIME:
2554 data = vcpu->arch.st.msr_val;
2555 break;
1d92128f
MT		 2556 case MSR_KVM_PV_EOI_EN:
2557 data = vcpu->arch.pv_eoi.msr_val;
2558 break;
890ca9ae
HY		 2559 case MSR_IA32_P5_MC_ADDR:
2560 case MSR_IA32_P5_MC_TYPE:
2561 case MSR_IA32_MCG_CAP:
2562 case MSR_IA32_MCG_CTL:
2563 case MSR_IA32_MCG_STATUS:
81760dcc 2564 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2565 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2566 case MSR_K7_CLK_CTL:
2567 /*
2568 * Provide expected ramp-up count for K7. All other
2569 * are set to zero, indicating minimum divisors for
2570 * every field.
2571 *
2572 * This prevents guest kernels on AMD host with CPU
2573 * type 6, model 8 and higher from exploding due to
2574 * the rdmsr failing.
2575 */
2576 data = 0x20000000;
2577 break;
55cd8e5a
GN		 2578 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2579 if (kvm_hv_msr_partition_wide(msr)) {
2580 int r;
2581 mutex_lock(&vcpu->kvm->lock);
2582 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2583 mutex_unlock(&vcpu->kvm->lock);
2584 return r;
2585 } else
2586 return get_msr_hyperv(vcpu, msr, pdata);
2587 break;
91c9c3ed 2588 case MSR_IA32_BBL_CR_CTL3:
2589 /* This legacy MSR exists but isn't fully documented in current
2590 * silicon. It is however accessed by winxp in very narrow
2591 * scenarios where it sets bit #19, itself documented as
2592 * a "reserved" bit. Best effort attempt to source coherent
2593 * read data here should the balance of the register be
2594 * interpreted by the guest:
2595 *
2596 * L2 cache control register 3: 64GB range, 256KB size,
2597 * enabled, latency 0x1, configured
2598 */
2599 data = 0xbe702111;
2600 break;
2b036c6b
BO		 2601 case MSR_AMD64_OSVW_ID_LENGTH:
2602 if (!guest_cpuid_has_osvw(vcpu))
2603 return 1;
2604 data = vcpu->arch.osvw.length;
2605 break;
2606 case MSR_AMD64_OSVW_STATUS:
2607 if (!guest_cpuid_has_osvw(vcpu))
2608 return 1;
2609 data = vcpu->arch.osvw.status;
2610 break;
15c4a640 2611 default:
f5132b01
GN		 2612 if (kvm_pmu_msr(vcpu, msr))
2613 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2614 if (!ignore_msrs) {
a737f256 2615 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2616 return 1;
2617 } else {
a737f256 2618 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2619 data = 0;
2620 }
2621 break;
15c4a640
CO		 2622 }
2623 *pdata = data;
2624 return 0;
2625}
2626EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2627
313a3dc7
CO		 2628/*
2629 * Read or write a bunch of msrs. All parameters are kernel addresses.
2630 *
2631 * @return number of msrs set successfully.
2632 */
2633static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2634 struct kvm_msr_entry *entries,
2635 int (*do_msr)(struct kvm_vcpu *vcpu,
2636 unsigned index, u64 *data))
2637{
f656ce01 2638 int i, idx;
313a3dc7 2639
f656ce01 2640 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2641 for (i = 0; i < msrs->nmsrs; ++i)
2642 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2643 break;
f656ce01 2644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2645
313a3dc7
CO		 2646 return i;
2647}
2648
2649/*
2650 * Read or write a bunch of msrs. Parameters are user addresses.
2651 *
2652 * @return number of msrs set successfully.
2653 */
2654static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2655 int (*do_msr)(struct kvm_vcpu *vcpu,
2656 unsigned index, u64 *data),
2657 int writeback)
2658{
2659 struct kvm_msrs msrs;
2660 struct kvm_msr_entry *entries;
2661 int r, n;
2662 unsigned size;
2663
2664 r = -EFAULT;
2665 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2666 goto out;
2667
2668 r = -E2BIG;
2669 if (msrs.nmsrs >= MAX_IO_MSRS)
2670 goto out;
2671
313a3dc7 2672 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2673 entries = memdup_user(user_msrs->entries, size);
2674 if (IS_ERR(entries)) {
2675 r = PTR_ERR(entries);
313a3dc7 2676 goto out;
ff5c2c03 2677 }
313a3dc7
CO		 2678
2679 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2680 if (r < 0)
2681 goto out_free;
2682
2683 r = -EFAULT;
2684 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2685 goto out_free;
2686
2687 r = n;
2688
2689out_free:
7a73c028 2690 kfree(entries);
313a3dc7
CO		 2691out:
2692 return r;
2693}
2694
784aa3d7 2695int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2696{
2697 int r;
2698
2699 switch (ext) {
2700 case KVM_CAP_IRQCHIP:
2701 case KVM_CAP_HLT:
2702 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2703 case KVM_CAP_SET_TSS_ADDR:
07716717 2704 case KVM_CAP_EXT_CPUID:
9c15bb1d 2705 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2706 case KVM_CAP_CLOCKSOURCE:
7837699f 2707 case KVM_CAP_PIT:
a28e4f5a 2708 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2709 case KVM_CAP_MP_STATE:
ed848624 2710 case KVM_CAP_SYNC_MMU:
a355c85c 2711 case KVM_CAP_USER_NMI:
52d939a0 2712 case KVM_CAP_REINJECT_CONTROL:
4925663a 2713 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2714 case KVM_CAP_IRQFD:
d34e6b17 2715 case KVM_CAP_IOEVENTFD:
f848a5a8 2716 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2717 case KVM_CAP_PIT2:
e9f42757 2718 case KVM_CAP_PIT_STATE2:
b927a3ce 2719 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2720 case KVM_CAP_XEN_HVM:
afbcf7ab 2721 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2722 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2723 case KVM_CAP_HYPERV:
10388a07 2724 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2725 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2726 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2727 case KVM_CAP_DEBUGREGS:
d2be1651 2728 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2729 case KVM_CAP_XSAVE:
344d9588 2730 case KVM_CAP_ASYNC_PF:
92a1f12d 2731 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2732 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2733 case KVM_CAP_READONLY_MEM:
5f66b620 2734 case KVM_CAP_HYPERV_TIME:
100943c5 2735 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2736#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2737 case KVM_CAP_ASSIGN_DEV_IRQ:
2738 case KVM_CAP_PCI_2_3:
2739#endif
018d00d2
ZX		 2740 r = 1;
2741 break;
542472b5
LV		 2742 case KVM_CAP_COALESCED_MMIO:
2743 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2744 break;
774ead3a
AK		 2745 case KVM_CAP_VAPIC:
2746 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2747 break;
f725230a 2748 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2749 r = KVM_SOFT_MAX_VCPUS;
2750 break;
2751 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2752 r = KVM_MAX_VCPUS;
2753 break;
a988b910 2754 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2755 r = KVM_USER_MEM_SLOTS;
a988b910 2756 break;
a68a6a72
MT		 2757 case KVM_CAP_PV_MMU: /* obsolete */
2758 r = 0;
2f333bcb 2759 break;
4cee4b72 2760#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2761 case KVM_CAP_IOMMU:
a1b60c1c 2762 r = iommu_present(&pci_bus_type);
62c476c7 2763 break;
4cee4b72 2764#endif
890ca9ae
HY		 2765 case KVM_CAP_MCE:
2766 r = KVM_MAX_MCE_BANKS;
2767 break;
2d5b5a66
SY		 2768 case KVM_CAP_XCRS:
2769 r = cpu_has_xsave;
2770 break;
92a1f12d
JR		 2771 case KVM_CAP_TSC_CONTROL:
2772 r = kvm_has_tsc_control;
2773 break;
4d25a066
JK		 2774 case KVM_CAP_TSC_DEADLINE_TIMER:
2775 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2776 break;
018d00d2
ZX		 2777 default:
2778 r = 0;
2779 break;
2780 }
2781 return r;
2782
2783}
2784
043405e1
CO		 2785long kvm_arch_dev_ioctl(struct file *filp,
2786 unsigned int ioctl, unsigned long arg)
2787{
2788 void __user *argp = (void __user *)arg;
2789 long r;
2790
2791 switch (ioctl) {
2792 case KVM_GET_MSR_INDEX_LIST: {
2793 struct kvm_msr_list __user *user_msr_list = argp;
2794 struct kvm_msr_list msr_list;
2795 unsigned n;
2796
2797 r = -EFAULT;
2798 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2799 goto out;
2800 n = msr_list.nmsrs;
2801 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2802 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2803 goto out;
2804 r = -E2BIG;
e125e7b6 2805 if (n < msr_list.nmsrs)
043405e1
CO		 2806 goto out;
2807 r = -EFAULT;
2808 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2809 num_msrs_to_save * sizeof(u32)))
2810 goto out;
e125e7b6 2811 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2812 &emulated_msrs,
2813 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2814 goto out;
2815 r = 0;
2816 break;
2817 }
9c15bb1d
BP		 2818 case KVM_GET_SUPPORTED_CPUID:
2819 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2820 struct kvm_cpuid2 __user *cpuid_arg = argp;
2821 struct kvm_cpuid2 cpuid;
2822
2823 r = -EFAULT;
2824 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2825 goto out;
9c15bb1d
BP		 2826
2827 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2828 ioctl);
674eea0f
AK		 2829 if (r)
2830 goto out;
2831
2832 r = -EFAULT;
2833 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2834 goto out;
2835 r = 0;
2836 break;
2837 }
890ca9ae
HY		 2838 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2839 u64 mce_cap;
2840
2841 mce_cap = KVM_MCE_CAP_SUPPORTED;
2842 r = -EFAULT;
2843 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2844 goto out;
2845 r = 0;
2846 break;
2847 }
043405e1
CO		 2848 default:
2849 r = -EINVAL;
2850 }
2851out:
2852 return r;
2853}
2854
f5f48ee1
SY		 2855static void wbinvd_ipi(void *garbage)
2856{
2857 wbinvd();
2858}
2859
2860static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2861{
e0f0bbc5 2862 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2863}
2864
313a3dc7
CO		 2865void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2866{
f5f48ee1
SY		 2867 /* Address WBINVD may be executed by guest */
2868 if (need_emulate_wbinvd(vcpu)) {
2869 if (kvm_x86_ops->has_wbinvd_exit())
2870 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2871 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2872 smp_call_function_single(vcpu->cpu,
2873 wbinvd_ipi, NULL, 1);
2874 }
2875
313a3dc7 2876 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2877
0dd6a6ed
ZA		 2878 /* Apply any externally detected TSC adjustments (due to suspend) */
2879 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2880 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2881 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2882 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2883 }
8f6055cb 2884
48434c20 2885 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2886 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2887 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2888 if (tsc_delta < 0)
2889 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2890 if (check_tsc_unstable()) {
b183aa58
ZA		 2891 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2892 vcpu->arch.last_guest_tsc);
2893 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2894 vcpu->arch.tsc_catchup = 1;
c285545f 2895 }
d98d07ca
MT		 2896 /*
2897 * On a host with synchronized TSC, there is no need to update
2898 * kvmclock on vcpu->cpu migration
2899 */
2900 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2901 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2902 if (vcpu->cpu != cpu)
2903 kvm_migrate_timers(vcpu);
e48672fa 2904 vcpu->cpu = cpu;
6b7d7e76 2905 }
c9aaa895
GC		 2906
2907 accumulate_steal_time(vcpu);
2908 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2909}
2910
2911void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2912{
02daab21 2913 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2914 kvm_put_guest_fpu(vcpu);
6f526ec5 2915 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2916}
2917
313a3dc7
CO		 2918static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2919 struct kvm_lapic_state *s)
2920{
5a71785d 2921 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2922 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2923
2924 return 0;
2925}
2926
2927static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2928 struct kvm_lapic_state *s)
2929{
64eb0620 2930 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2931 update_cr8_intercept(vcpu);
313a3dc7
CO		 2932
2933 return 0;
2934}
2935
f77bc6a4
ZX		 2936static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2937 struct kvm_interrupt *irq)
2938{
02cdb50f 2939 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2940 return -EINVAL;
2941 if (irqchip_in_kernel(vcpu->kvm))
2942 return -ENXIO;
f77bc6a4 2943
66fd3f7f 2944 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2945 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2946
f77bc6a4
ZX		 2947 return 0;
2948}
2949
c4abb7c9
JK		 2950static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2951{
c4abb7c9 2952 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2953
2954 return 0;
2955}
2956
b209749f
AK		 2957static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2958 struct kvm_tpr_access_ctl *tac)
2959{
2960 if (tac->flags)
2961 return -EINVAL;
2962 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2963 return 0;
2964}
2965
890ca9ae
HY		 2966static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2967 u64 mcg_cap)
2968{
2969 int r;
2970 unsigned bank_num = mcg_cap & 0xff, bank;
2971
2972 r = -EINVAL;
a9e38c3e 2973 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2974 goto out;
2975 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2976 goto out;
2977 r = 0;
2978 vcpu->arch.mcg_cap = mcg_cap;
2979 /* Init IA32_MCG_CTL to all 1s */
2980 if (mcg_cap & MCG_CTL_P)
2981 vcpu->arch.mcg_ctl = ~(u64)0;
2982 /* Init IA32_MCi_CTL to all 1s */
2983 for (bank = 0; bank < bank_num; bank++)
2984 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2985out:
2986 return r;
2987}
2988
2989static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2990 struct kvm_x86_mce *mce)
2991{
2992 u64 mcg_cap = vcpu->arch.mcg_cap;
2993 unsigned bank_num = mcg_cap & 0xff;
2994 u64 *banks = vcpu->arch.mce_banks;
2995
2996 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2997 return -EINVAL;
2998 /*
2999 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3000 * reporting is disabled
3001 */
3002 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3003 vcpu->arch.mcg_ctl != ~(u64)0)
3004 return 0;
3005 banks += 4 * mce->bank;
3006 /*
3007 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3008 * reporting is disabled for the bank
3009 */
3010 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3011 return 0;
3012 if (mce->status & MCI_STATUS_UC) {
3013 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3014 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3015 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3016 return 0;
3017 }
3018 if (banks[1] & MCI_STATUS_VAL)
3019 mce->status |= MCI_STATUS_OVER;
3020 banks[2] = mce->addr;
3021 banks[3] = mce->misc;
3022 vcpu->arch.mcg_status = mce->mcg_status;
3023 banks[1] = mce->status;
3024 kvm_queue_exception(vcpu, MC_VECTOR);
3025 } else if (!(banks[1] & MCI_STATUS_VAL)
3026 || !(banks[1] & MCI_STATUS_UC)) {
3027 if (banks[1] & MCI_STATUS_VAL)
3028 mce->status |= MCI_STATUS_OVER;
3029 banks[2] = mce->addr;
3030 banks[3] = mce->misc;
3031 banks[1] = mce->status;
3032 } else
3033 banks[1] |= MCI_STATUS_OVER;
3034 return 0;
3035}
3036
3cfc3092
JK		 3037static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3038 struct kvm_vcpu_events *events)
3039{
7460fb4a 3040 process_nmi(vcpu);
03b82a30
JK		 3041 events->exception.injected =
3042 vcpu->arch.exception.pending &&
3043 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3044 events->exception.nr = vcpu->arch.exception.nr;
3045 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3046 events->exception.pad = 0;
3cfc3092
JK		 3047 events->exception.error_code = vcpu->arch.exception.error_code;
3048
03b82a30
JK		 3049 events->interrupt.injected =
3050 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3051 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3052 events->interrupt.soft = 0;
37ccdcbe 3053 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3054
3055 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3056 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3057 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3058 events->nmi.pad = 0;
3cfc3092 3059
66450a21 3060 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3061
dab4b911 3062 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3063 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3064 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3065}
3066
3067static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3068 struct kvm_vcpu_events *events)
3069{
dab4b911 3070 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3071 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3072 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3073 return -EINVAL;
3074
7460fb4a 3075 process_nmi(vcpu);
3cfc3092
JK		 3076 vcpu->arch.exception.pending = events->exception.injected;
3077 vcpu->arch.exception.nr = events->exception.nr;
3078 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3079 vcpu->arch.exception.error_code = events->exception.error_code;
3080
3081 vcpu->arch.interrupt.pending = events->interrupt.injected;
3082 vcpu->arch.interrupt.nr = events->interrupt.nr;
3083 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3084 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3085 kvm_x86_ops->set_interrupt_shadow(vcpu,
3086 events->interrupt.shadow);
3cfc3092
JK		 3087
3088 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3089 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3090 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3091 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3092
66450a21
JK		 3093 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3094 kvm_vcpu_has_lapic(vcpu))
3095 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3096
3842d135
AK		 3097 kvm_make_request(KVM_REQ_EVENT, vcpu);
3098
3cfc3092
JK		 3099 return 0;
3100}
3101
a1efbe77
JK		 3102static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3103 struct kvm_debugregs *dbgregs)
3104{
73aaf249
JK		 3105 unsigned long val;
3106
a1efbe77 3107 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3108 kvm_get_dr(vcpu, 6, &val);
73aaf249 3109 dbgregs->dr6 = val;
a1efbe77
JK		 3110 dbgregs->dr7 = vcpu->arch.dr7;
3111 dbgregs->flags = 0;
97e69aa6 3112 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3113}
3114
3115static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3116 struct kvm_debugregs *dbgregs)
3117{
3118 if (dbgregs->flags)
3119 return -EINVAL;
3120
a1efbe77
JK		 3121 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3122 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3123 kvm_update_dr6(vcpu);
a1efbe77 3124 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3125 kvm_update_dr7(vcpu);
a1efbe77 3126
a1efbe77
JK		 3127 return 0;
3128}
3129
2d5b5a66
SY		 3130static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3131 struct kvm_xsave *guest_xsave)
3132{
4344ee98 3133 if (cpu_has_xsave) {
2d5b5a66
SY		 3134 memcpy(guest_xsave->region,
3135 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3136 vcpu->arch.guest_xstate_size);
3137 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3138 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3139 } else {
2d5b5a66
SY		 3140 memcpy(guest_xsave->region,
3141 &vcpu->arch.guest_fpu.state->fxsave,
3142 sizeof(struct i387_fxsave_struct));
3143 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3144 XSTATE_FPSSE;
3145 }
3146}
3147
3148static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3149 struct kvm_xsave *guest_xsave)
3150{
3151 u64 xstate_bv =
3152 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3153
d7876f1b
PB		 3154 if (cpu_has_xsave) {
3155 /*
3156 * Here we allow setting states that are not present in
3157 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3158 * with old userspace.
3159 */
4ff41732 3160 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3161 return -EINVAL;
2d5b5a66 3162 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3163 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3164 } else {
2d5b5a66
SY		 3165 if (xstate_bv & ~XSTATE_FPSSE)
3166 return -EINVAL;
3167 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3168 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3169 }
3170 return 0;
3171}
3172
3173static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3174 struct kvm_xcrs *guest_xcrs)
3175{
3176 if (!cpu_has_xsave) {
3177 guest_xcrs->nr_xcrs = 0;
3178 return;
3179 }
3180
3181 guest_xcrs->nr_xcrs = 1;
3182 guest_xcrs->flags = 0;
3183 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3184 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3185}
3186
3187static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3188 struct kvm_xcrs *guest_xcrs)
3189{
3190 int i, r = 0;
3191
3192 if (!cpu_has_xsave)
3193 return -EINVAL;
3194
3195 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3196 return -EINVAL;
3197
3198 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3199 /* Only support XCR0 currently */
c67a04cb 3200 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3201 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3202 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3203 break;
3204 }
3205 if (r)
3206 r = -EINVAL;
3207 return r;
3208}
3209
1c0b28c2
EM		 3210/*
3211 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3212 * stopped by the hypervisor. This function will be called from the host only.
3213 * EINVAL is returned when the host attempts to set the flag for a guest that
3214 * does not support pv clocks.
3215 */
3216static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3217{
0b79459b 3218 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3219 return -EINVAL;
51d59c6b 3220 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3221 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3222 return 0;
3223}
3224
313a3dc7
CO		 3225long kvm_arch_vcpu_ioctl(struct file *filp,
3226 unsigned int ioctl, unsigned long arg)
3227{
3228 struct kvm_vcpu *vcpu = filp->private_data;
3229 void __user *argp = (void __user *)arg;
3230 int r;
d1ac91d8
AK		 3231 union {
3232 struct kvm_lapic_state *lapic;
3233 struct kvm_xsave *xsave;
3234 struct kvm_xcrs *xcrs;
3235 void *buffer;
3236 } u;
3237
3238 u.buffer = NULL;
313a3dc7
CO		 3239 switch (ioctl) {
3240 case KVM_GET_LAPIC: {
2204ae3c
MT		 3241 r = -EINVAL;
3242 if (!vcpu->arch.apic)
3243 goto out;
d1ac91d8 3244 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3245
b772ff36 3246 r = -ENOMEM;
d1ac91d8 3247 if (!u.lapic)
b772ff36 3248 goto out;
d1ac91d8 3249 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3250 if (r)
3251 goto out;
3252 r = -EFAULT;
d1ac91d8 3253 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3254 goto out;
3255 r = 0;
3256 break;
3257 }
3258 case KVM_SET_LAPIC: {
2204ae3c
MT		 3259 r = -EINVAL;
3260 if (!vcpu->arch.apic)
3261 goto out;
ff5c2c03 3262 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3263 if (IS_ERR(u.lapic))
3264 return PTR_ERR(u.lapic);
ff5c2c03 3265
d1ac91d8 3266 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3267 break;
3268 }
f77bc6a4
ZX		 3269 case KVM_INTERRUPT: {
3270 struct kvm_interrupt irq;
3271
3272 r = -EFAULT;
3273 if (copy_from_user(&irq, argp, sizeof irq))
3274 goto out;
3275 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3276 break;
3277 }
c4abb7c9
JK		 3278 case KVM_NMI: {
3279 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3280 break;
3281 }
313a3dc7
CO		 3282 case KVM_SET_CPUID: {
3283 struct kvm_cpuid __user *cpuid_arg = argp;
3284 struct kvm_cpuid cpuid;
3285
3286 r = -EFAULT;
3287 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3288 goto out;
3289 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3290 break;
3291 }
07716717
DK		 3292 case KVM_SET_CPUID2: {
3293 struct kvm_cpuid2 __user *cpuid_arg = argp;
3294 struct kvm_cpuid2 cpuid;
3295
3296 r = -EFAULT;
3297 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3298 goto out;
3299 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3300 cpuid_arg->entries);
07716717
DK		 3301 break;
3302 }
3303 case KVM_GET_CPUID2: {
3304 struct kvm_cpuid2 __user *cpuid_arg = argp;
3305 struct kvm_cpuid2 cpuid;
3306
3307 r = -EFAULT;
3308 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3309 goto out;
3310 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3311 cpuid_arg->entries);
07716717
DK		 3312 if (r)
3313 goto out;
3314 r = -EFAULT;
3315 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3316 goto out;
3317 r = 0;
3318 break;
3319 }
313a3dc7
CO		 3320 case KVM_GET_MSRS:
3321 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3322 break;
3323 case KVM_SET_MSRS:
3324 r = msr_io(vcpu, argp, do_set_msr, 0);
3325 break;
b209749f
AK		 3326 case KVM_TPR_ACCESS_REPORTING: {
3327 struct kvm_tpr_access_ctl tac;
3328
3329 r = -EFAULT;
3330 if (copy_from_user(&tac, argp, sizeof tac))
3331 goto out;
3332 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3333 if (r)
3334 goto out;
3335 r = -EFAULT;
3336 if (copy_to_user(argp, &tac, sizeof tac))
3337 goto out;
3338 r = 0;
3339 break;
3340 };
b93463aa
AK		 3341 case KVM_SET_VAPIC_ADDR: {
3342 struct kvm_vapic_addr va;
3343
3344 r = -EINVAL;
3345 if (!irqchip_in_kernel(vcpu->kvm))
3346 goto out;
3347 r = -EFAULT;
3348 if (copy_from_user(&va, argp, sizeof va))
3349 goto out;
fda4e2e8 3350 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3351 break;
3352 }
890ca9ae
HY		 3353 case KVM_X86_SETUP_MCE: {
3354 u64 mcg_cap;
3355
3356 r = -EFAULT;
3357 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3358 goto out;
3359 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3360 break;
3361 }
3362 case KVM_X86_SET_MCE: {
3363 struct kvm_x86_mce mce;
3364
3365 r = -EFAULT;
3366 if (copy_from_user(&mce, argp, sizeof mce))
3367 goto out;
3368 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3369 break;
3370 }
3cfc3092
JK		 3371 case KVM_GET_VCPU_EVENTS: {
3372 struct kvm_vcpu_events events;
3373
3374 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3375
3376 r = -EFAULT;
3377 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3378 break;
3379 r = 0;
3380 break;
3381 }
3382 case KVM_SET_VCPU_EVENTS: {
3383 struct kvm_vcpu_events events;
3384
3385 r = -EFAULT;
3386 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3387 break;
3388
3389 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3390 break;
3391 }
a1efbe77
JK		 3392 case KVM_GET_DEBUGREGS: {
3393 struct kvm_debugregs dbgregs;
3394
3395 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3396
3397 r = -EFAULT;
3398 if (copy_to_user(argp, &dbgregs,
3399 sizeof(struct kvm_debugregs)))
3400 break;
3401 r = 0;
3402 break;
3403 }
3404 case KVM_SET_DEBUGREGS: {
3405 struct kvm_debugregs dbgregs;
3406
3407 r = -EFAULT;
3408 if (copy_from_user(&dbgregs, argp,
3409 sizeof(struct kvm_debugregs)))
3410 break;
3411
3412 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3413 break;
3414 }
2d5b5a66 3415 case KVM_GET_XSAVE: {
d1ac91d8 3416 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3417 r = -ENOMEM;
d1ac91d8 3418 if (!u.xsave)
2d5b5a66
SY		 3419 break;
3420
d1ac91d8 3421 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3422
3423 r = -EFAULT;
d1ac91d8 3424 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3425 break;
3426 r = 0;
3427 break;
3428 }
3429 case KVM_SET_XSAVE: {
ff5c2c03 3430 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3431 if (IS_ERR(u.xsave))
3432 return PTR_ERR(u.xsave);
2d5b5a66 3433
d1ac91d8 3434 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3435 break;
3436 }
3437 case KVM_GET_XCRS: {
d1ac91d8 3438 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3439 r = -ENOMEM;
d1ac91d8 3440 if (!u.xcrs)
2d5b5a66
SY		 3441 break;
3442
d1ac91d8 3443 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3444
3445 r = -EFAULT;
d1ac91d8 3446 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3447 sizeof(struct kvm_xcrs)))
3448 break;
3449 r = 0;
3450 break;
3451 }
3452 case KVM_SET_XCRS: {
ff5c2c03 3453 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3454 if (IS_ERR(u.xcrs))
3455 return PTR_ERR(u.xcrs);
2d5b5a66 3456
d1ac91d8 3457 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3458 break;
3459 }
92a1f12d
JR		 3460 case KVM_SET_TSC_KHZ: {
3461 u32 user_tsc_khz;
3462
3463 r = -EINVAL;
92a1f12d
JR		 3464 user_tsc_khz = (u32)arg;
3465
3466 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3467 goto out;
3468
cc578287
ZA		 3469 if (user_tsc_khz == 0)
3470 user_tsc_khz = tsc_khz;
3471
3472 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3473
3474 r = 0;
3475 goto out;
3476 }
3477 case KVM_GET_TSC_KHZ: {
cc578287 3478 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3479 goto out;
3480 }
1c0b28c2
EM		 3481 case KVM_KVMCLOCK_CTRL: {
3482 r = kvm_set_guest_paused(vcpu);
3483 goto out;
3484 }
313a3dc7
CO		 3485 default:
3486 r = -EINVAL;
3487 }
3488out:
d1ac91d8 3489 kfree(u.buffer);
313a3dc7
CO		 3490 return r;
3491}
3492
5b1c1493
CO		 3493int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3494{
3495 return VM_FAULT_SIGBUS;
3496}
3497
1fe779f8
CO		 3498static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3499{
3500 int ret;
3501
3502 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3503 return -EINVAL;
1fe779f8
CO		 3504 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3505 return ret;
3506}
3507
b927a3ce
SY		 3508static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3509 u64 ident_addr)
3510{
3511 kvm->arch.ept_identity_map_addr = ident_addr;
3512 return 0;
3513}
3514
1fe779f8
CO		 3515static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3516 u32 kvm_nr_mmu_pages)
3517{
3518 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3519 return -EINVAL;
3520
79fac95e 3521 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3522
3523 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3524 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3525
79fac95e 3526 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3527 return 0;
3528}
3529
3530static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3531{
39de71ec 3532 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3533}
3534
1fe779f8
CO		 3535static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3536{
3537 int r;
3538
3539 r = 0;
3540 switch (chip->chip_id) {
3541 case KVM_IRQCHIP_PIC_MASTER:
3542 memcpy(&chip->chip.pic,
3543 &pic_irqchip(kvm)->pics[0],
3544 sizeof(struct kvm_pic_state));
3545 break;
3546 case KVM_IRQCHIP_PIC_SLAVE:
3547 memcpy(&chip->chip.pic,
3548 &pic_irqchip(kvm)->pics[1],
3549 sizeof(struct kvm_pic_state));
3550 break;
3551 case KVM_IRQCHIP_IOAPIC:
eba0226b 3552 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3553 break;
3554 default:
3555 r = -EINVAL;
3556 break;
3557 }
3558 return r;
3559}
3560
3561static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3562{
3563 int r;
3564
3565 r = 0;
3566 switch (chip->chip_id) {
3567 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3568 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3569 memcpy(&pic_irqchip(kvm)->pics[0],
3570 &chip->chip.pic,
3571 sizeof(struct kvm_pic_state));
f4f51050 3572 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3573 break;
3574 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3575 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3576 memcpy(&pic_irqchip(kvm)->pics[1],
3577 &chip->chip.pic,
3578 sizeof(struct kvm_pic_state));
f4f51050 3579 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3580 break;
3581 case KVM_IRQCHIP_IOAPIC:
eba0226b 3582 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3583 break;
3584 default:
3585 r = -EINVAL;
3586 break;
3587 }
3588 kvm_pic_update_irq(pic_irqchip(kvm));
3589 return r;
3590}
3591
e0f63cb9
SY		 3592static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3593{
3594 int r = 0;
3595
894a9c55 3596 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3597 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3598 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3599 return r;
3600}
3601
3602static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3603{
3604 int r = 0;
3605
894a9c55 3606 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3607 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3608 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3609 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3610 return r;
3611}
3612
3613static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3614{
3615 int r = 0;
3616
3617 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3618 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3619 sizeof(ps->channels));
3620 ps->flags = kvm->arch.vpit->pit_state.flags;
3621 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3622 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3623 return r;
3624}
3625
3626static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3627{
3628 int r = 0, start = 0;
3629 u32 prev_legacy, cur_legacy;
3630 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3631 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3632 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3633 if (!prev_legacy && cur_legacy)
3634 start = 1;
3635 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3636 sizeof(kvm->arch.vpit->pit_state.channels));
3637 kvm->arch.vpit->pit_state.flags = ps->flags;
3638 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3639 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3640 return r;
3641}
3642
52d939a0
MT		 3643static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3644 struct kvm_reinject_control *control)
3645{
3646 if (!kvm->arch.vpit)
3647 return -ENXIO;
894a9c55 3648 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3649 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3650 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3651 return 0;
3652}
3653
95d4c16c 3654/**
60c34612
TY		 3655 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3656 * @kvm: kvm instance
3657 * @log: slot id and address to which we copy the log
95d4c16c 3658 *
60c34612
TY		 3659 * We need to keep it in mind that VCPU threads can write to the bitmap
3660 * concurrently. So, to avoid losing data, we keep the following order for
3661 * each bit:
95d4c16c 3662 *
60c34612
TY		 3663 * 1. Take a snapshot of the bit and clear it if needed.
3664 * 2. Write protect the corresponding page.
3665 * 3. Flush TLB's if needed.
3666 * 4. Copy the snapshot to the userspace.
95d4c16c 3667 *
60c34612
TY		 3668 * Between 2 and 3, the guest may write to the page using the remaining TLB
3669 * entry. This is not a problem because the page will be reported dirty at
3670 * step 4 using the snapshot taken before and step 3 ensures that successive
3671 * writes will be logged for the next call.
5bb064dc 3672 */
60c34612 3673int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3674{
7850ac54 3675 int r;
5bb064dc 3676 struct kvm_memory_slot *memslot;
60c34612
TY		 3677 unsigned long n, i;
3678 unsigned long *dirty_bitmap;
3679 unsigned long *dirty_bitmap_buffer;
3680 bool is_dirty = false;
5bb064dc 3681
79fac95e 3682 mutex_lock(&kvm->slots_lock);
5bb064dc 3683
b050b015 3684 r = -EINVAL;
bbacc0c1 3685 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3686 goto out;
3687
28a37544 3688 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3689
3690 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3691 r = -ENOENT;
60c34612 3692 if (!dirty_bitmap)
b050b015
MT		 3693 goto out;
3694
87bf6e7d 3695 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3696
60c34612
TY		 3697 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3698 memset(dirty_bitmap_buffer, 0, n);
b050b015 3699
60c34612 3700 spin_lock(&kvm->mmu_lock);
b050b015 3701
60c34612
TY		 3702 for (i = 0; i < n / sizeof(long); i++) {
3703 unsigned long mask;
3704 gfn_t offset;
cdfca7b3 3705
60c34612
TY		 3706 if (!dirty_bitmap[i])
3707 continue;
b050b015 3708
60c34612 3709 is_dirty = true;
914ebccd 3710
60c34612
TY		 3711 mask = xchg(&dirty_bitmap[i], 0);
3712 dirty_bitmap_buffer[i] = mask;
edde99ce 3713
60c34612
TY		 3714 offset = i * BITS_PER_LONG;
3715 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3716 }
60c34612
TY		 3717
3718 spin_unlock(&kvm->mmu_lock);
3719
198c74f4
XG		 3720 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3721 lockdep_assert_held(&kvm->slots_lock);
3722
3723 /*
3724 * All the TLBs can be flushed out of mmu lock, see the comments in
3725 * kvm_mmu_slot_remove_write_access().
3726 */
3727 if (is_dirty)
3728 kvm_flush_remote_tlbs(kvm);
3729
60c34612
TY		 3730 r = -EFAULT;
3731 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3732 goto out;
b050b015 3733
5bb064dc
ZX		 3734 r = 0;
3735out:
79fac95e 3736 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3737 return r;
3738}
3739
aa2fbe6d
YZ		 3740int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3741 bool line_status)
23d43cf9
CD		 3742{
3743 if (!irqchip_in_kernel(kvm))
3744 return -ENXIO;
3745
3746 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3747 irq_event->irq, irq_event->level,
3748 line_status);
23d43cf9
CD		 3749 return 0;
3750}
3751
1fe779f8
CO		 3752long kvm_arch_vm_ioctl(struct file *filp,
3753 unsigned int ioctl, unsigned long arg)
3754{
3755 struct kvm *kvm = filp->private_data;
3756 void __user *argp = (void __user *)arg;
367e1319 3757 int r = -ENOTTY;
f0d66275
DH		 3758 /*
3759 * This union makes it completely explicit to gcc-3.x
3760 * that these two variables' stack usage should be
3761 * combined, not added together.
3762 */
3763 union {
3764 struct kvm_pit_state ps;
e9f42757 3765 struct kvm_pit_state2 ps2;
c5ff41ce 3766 struct kvm_pit_config pit_config;
f0d66275 3767 } u;
1fe779f8
CO		 3768
3769 switch (ioctl) {
3770 case KVM_SET_TSS_ADDR:
3771 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3772 break;
b927a3ce
SY		 3773 case KVM_SET_IDENTITY_MAP_ADDR: {
3774 u64 ident_addr;
3775
3776 r = -EFAULT;
3777 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3778 goto out;
3779 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3780 break;
3781 }
1fe779f8
CO		 3782 case KVM_SET_NR_MMU_PAGES:
3783 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3784 break;
3785 case KVM_GET_NR_MMU_PAGES:
3786 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3787 break;
3ddea128
MT		 3788 case KVM_CREATE_IRQCHIP: {
3789 struct kvm_pic *vpic;
3790
3791 mutex_lock(&kvm->lock);
3792 r = -EEXIST;
3793 if (kvm->arch.vpic)
3794 goto create_irqchip_unlock;
3e515705
AK		 3795 r = -EINVAL;
3796 if (atomic_read(&kvm->online_vcpus))
3797 goto create_irqchip_unlock;
1fe779f8 3798 r = -ENOMEM;
3ddea128
MT		 3799 vpic = kvm_create_pic(kvm);
3800 if (vpic) {
1fe779f8
CO		 3801 r = kvm_ioapic_init(kvm);
3802 if (r) {
175504cd 3803 mutex_lock(&kvm->slots_lock);
72bb2fcd 3804 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3805 &vpic->dev_master);
3806 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3807 &vpic->dev_slave);
3808 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3809 &vpic->dev_eclr);
175504cd 3810 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3811 kfree(vpic);
3812 goto create_irqchip_unlock;
1fe779f8
CO		 3813 }
3814 } else
3ddea128
MT		 3815 goto create_irqchip_unlock;
3816 smp_wmb();
3817 kvm->arch.vpic = vpic;
3818 smp_wmb();
399ec807
AK		 3819 r = kvm_setup_default_irq_routing(kvm);
3820 if (r) {
175504cd 3821 mutex_lock(&kvm->slots_lock);
3ddea128 3822 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3823 kvm_ioapic_destroy(kvm);
3824 kvm_destroy_pic(kvm);
3ddea128 3825 mutex_unlock(&kvm->irq_lock);
175504cd 3826 mutex_unlock(&kvm->slots_lock);
399ec807 3827 }
3ddea128
MT		 3828 create_irqchip_unlock:
3829 mutex_unlock(&kvm->lock);
1fe779f8 3830 break;
3ddea128 3831 }
7837699f 3832 case KVM_CREATE_PIT:
c5ff41ce
JK		 3833 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3834 goto create_pit;
3835 case KVM_CREATE_PIT2:
3836 r = -EFAULT;
3837 if (copy_from_user(&u.pit_config, argp,
3838 sizeof(struct kvm_pit_config)))
3839 goto out;
3840 create_pit:
79fac95e 3841 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3842 r = -EEXIST;
3843 if (kvm->arch.vpit)
3844 goto create_pit_unlock;
7837699f 3845 r = -ENOMEM;
c5ff41ce 3846 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3847 if (kvm->arch.vpit)
3848 r = 0;
269e05e4 3849 create_pit_unlock:
79fac95e 3850 mutex_unlock(&kvm->slots_lock);
7837699f 3851 break;
1fe779f8
CO		 3852 case KVM_GET_IRQCHIP: {
3853 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3854 struct kvm_irqchip *chip;
1fe779f8 3855
ff5c2c03
SL		 3856 chip = memdup_user(argp, sizeof(*chip));
3857 if (IS_ERR(chip)) {
3858 r = PTR_ERR(chip);
1fe779f8 3859 goto out;
ff5c2c03
SL		 3860 }
3861
1fe779f8
CO		 3862 r = -ENXIO;
3863 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3864 goto get_irqchip_out;
3865 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3866 if (r)
f0d66275 3867 goto get_irqchip_out;
1fe779f8 3868 r = -EFAULT;
f0d66275
DH		 3869 if (copy_to_user(argp, chip, sizeof *chip))
3870 goto get_irqchip_out;
1fe779f8 3871 r = 0;
f0d66275
DH		 3872 get_irqchip_out:
3873 kfree(chip);
1fe779f8
CO		 3874 break;
3875 }
3876 case KVM_SET_IRQCHIP: {
3877 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3878 struct kvm_irqchip *chip;
1fe779f8 3879
ff5c2c03
SL		 3880 chip = memdup_user(argp, sizeof(*chip));
3881 if (IS_ERR(chip)) {
3882 r = PTR_ERR(chip);
1fe779f8 3883 goto out;
ff5c2c03
SL		 3884 }
3885
1fe779f8
CO		 3886 r = -ENXIO;
3887 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3888 goto set_irqchip_out;
3889 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3890 if (r)
f0d66275 3891 goto set_irqchip_out;
1fe779f8 3892 r = 0;
f0d66275
DH		 3893 set_irqchip_out:
3894 kfree(chip);
1fe779f8
CO		 3895 break;
3896 }
e0f63cb9 3897 case KVM_GET_PIT: {
e0f63cb9 3898 r = -EFAULT;
f0d66275 3899 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3900 goto out;
3901 r = -ENXIO;
3902 if (!kvm->arch.vpit)
3903 goto out;
f0d66275 3904 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3905 if (r)
3906 goto out;
3907 r = -EFAULT;
f0d66275 3908 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3909 goto out;
3910 r = 0;
3911 break;
3912 }
3913 case KVM_SET_PIT: {
e0f63cb9 3914 r = -EFAULT;
f0d66275 3915 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3916 goto out;
3917 r = -ENXIO;
3918 if (!kvm->arch.vpit)
3919 goto out;
f0d66275 3920 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3921 break;
3922 }
e9f42757
BK		 3923 case KVM_GET_PIT2: {
3924 r = -ENXIO;
3925 if (!kvm->arch.vpit)
3926 goto out;
3927 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3928 if (r)
3929 goto out;
3930 r = -EFAULT;
3931 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3932 goto out;
3933 r = 0;
3934 break;
3935 }
3936 case KVM_SET_PIT2: {
3937 r = -EFAULT;
3938 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3939 goto out;
3940 r = -ENXIO;
3941 if (!kvm->arch.vpit)
3942 goto out;
3943 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3944 break;
3945 }
52d939a0
MT		 3946 case KVM_REINJECT_CONTROL: {
3947 struct kvm_reinject_control control;
3948 r = -EFAULT;
3949 if (copy_from_user(&control, argp, sizeof(control)))
3950 goto out;
3951 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3952 break;
3953 }
ffde22ac
ES		 3954 case KVM_XEN_HVM_CONFIG: {
3955 r = -EFAULT;
3956 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3957 sizeof(struct kvm_xen_hvm_config)))
3958 goto out;
3959 r = -EINVAL;
3960 if (kvm->arch.xen_hvm_config.flags)
3961 goto out;
3962 r = 0;
3963 break;
3964 }
afbcf7ab 3965 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3966 struct kvm_clock_data user_ns;
3967 u64 now_ns;
3968 s64 delta;
3969
3970 r = -EFAULT;
3971 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3972 goto out;
3973
3974 r = -EINVAL;
3975 if (user_ns.flags)
3976 goto out;
3977
3978 r = 0;
395c6b0a 3979 local_irq_disable();
759379dd 3980 now_ns = get_kernel_ns();
afbcf7ab 3981 delta = user_ns.clock - now_ns;
395c6b0a 3982 local_irq_enable();
afbcf7ab 3983 kvm->arch.kvmclock_offset = delta;
2e762ff7 3984 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3985 break;
3986 }
3987 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3988 struct kvm_clock_data user_ns;
3989 u64 now_ns;
3990
395c6b0a 3991 local_irq_disable();
759379dd 3992 now_ns = get_kernel_ns();
afbcf7ab 3993 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3994 local_irq_enable();
afbcf7ab 3995 user_ns.flags = 0;
97e69aa6 3996 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3997
3998 r = -EFAULT;
3999 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4000 goto out;
4001 r = 0;
4002 break;
4003 }
4004
1fe779f8
CO		 4005 default:
4006 ;
4007 }
4008out:
4009 return r;
4010}
4011
a16b043c 4012static void kvm_init_msr_list(void)
043405e1
CO		 4013{
4014 u32 dummy[2];
4015 unsigned i, j;
4016
e3267cbb
GC		 4017 /* skip the first msrs in the list. KVM-specific */
4018 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4019 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4020 continue;
93c4adc7
PB		 4021
4022 /*
4023 * Even MSRs that are valid in the host may not be exposed
4024 * to the guests in some cases. We could work around this
4025 * in VMX with the generic MSR save/load machinery, but it
4026 * is not really worthwhile since it will really only
4027 * happen with nested virtualization.
4028 */
4029 switch (msrs_to_save[i]) {
4030 case MSR_IA32_BNDCFGS:
4031 if (!kvm_x86_ops->mpx_supported())
4032 continue;
4033 break;
4034 default:
4035 break;
4036 }
4037
043405e1
CO		 4038 if (j < i)
4039 msrs_to_save[j] = msrs_to_save[i];
4040 j++;
4041 }
4042 num_msrs_to_save = j;
4043}
4044
bda9020e
MT		 4045static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4046 const void *v)
bbd9b64e 4047{
70252a10
AK		 4048 int handled = 0;
4049 int n;
4050
4051 do {
4052 n = min(len, 8);
4053 if (!(vcpu->arch.apic &&
4054 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4055 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4056 break;
4057 handled += n;
4058 addr += n;
4059 len -= n;
4060 v += n;
4061 } while (len);
bbd9b64e 4062
70252a10 4063 return handled;
bbd9b64e
CO		 4064}
4065
bda9020e 4066static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4067{
70252a10
AK		 4068 int handled = 0;
4069 int n;
4070
4071 do {
4072 n = min(len, 8);
4073 if (!(vcpu->arch.apic &&
4074 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4075 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4076 break;
4077 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4078 handled += n;
4079 addr += n;
4080 len -= n;
4081 v += n;
4082 } while (len);
bbd9b64e 4083
70252a10 4084 return handled;
bbd9b64e
CO		 4085}
4086
2dafc6c2
GN		 4087static void kvm_set_segment(struct kvm_vcpu *vcpu,
4088 struct kvm_segment *var, int seg)
4089{
4090 kvm_x86_ops->set_segment(vcpu, var, seg);
4091}
4092
4093void kvm_get_segment(struct kvm_vcpu *vcpu,
4094 struct kvm_segment *var, int seg)
4095{
4096 kvm_x86_ops->get_segment(vcpu, var, seg);
4097}
4098
54987b7a
PB		 4099gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4100 struct x86_exception *exception)
02f59dc9
JR		 4101{
4102 gpa_t t_gpa;
02f59dc9
JR		 4103
4104 BUG_ON(!mmu_is_nested(vcpu));
4105
4106 /* NPT walks are always user-walks */
4107 access |= PFERR_USER_MASK;
54987b7a 4108 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4109
4110 return t_gpa;
4111}
4112
ab9ae313
AK		 4113gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4114 struct x86_exception *exception)
1871c602
GN		 4115{
4116 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4117 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4118}
4119
ab9ae313
AK		 4120 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4121 struct x86_exception *exception)
1871c602
GN		 4122{
4123 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4124 access |= PFERR_FETCH_MASK;
ab9ae313 4125 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4126}
4127
ab9ae313
AK		 4128gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4129 struct x86_exception *exception)
1871c602
GN		 4130{
4131 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4132 access |= PFERR_WRITE_MASK;
ab9ae313 4133 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4134}
4135
4136/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4137gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4138 struct x86_exception *exception)
1871c602 4139{
ab9ae313 4140 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4141}
4142
4143static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4144 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4145 struct x86_exception *exception)
bbd9b64e
CO		 4146{
4147 void *data = val;
10589a46 4148 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4149
4150 while (bytes) {
14dfe855 4151 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4152 exception);
bbd9b64e 4153 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4154 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4155 int ret;
4156
bcc55cba 4157 if (gpa == UNMAPPED_GVA)
ab9ae313 4158 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4159 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4160 offset, toread);
10589a46 4161 if (ret < 0) {
c3cd7ffa 4162 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4163 goto out;
4164 }
bbd9b64e 4165
77c2002e
IE		 4166 bytes -= toread;
4167 data += toread;
4168 addr += toread;
bbd9b64e 4169 }
10589a46 4170out:
10589a46 4171 return r;
bbd9b64e 4172}
77c2002e 4173
1871c602 4174/* used for instruction fetching */
0f65dd70
AK		 4175static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4176 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4177 struct x86_exception *exception)
1871c602 4178{
0f65dd70 4179 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4181 unsigned offset;
4182 int ret;
0f65dd70 4183
44583cba
PB		 4184 /* Inline kvm_read_guest_virt_helper for speed. */
4185 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4186 exception);
4187 if (unlikely(gpa == UNMAPPED_GVA))
4188 return X86EMUL_PROPAGATE_FAULT;
4189
4190 offset = addr & (PAGE_SIZE-1);
4191 if (WARN_ON(offset + bytes > PAGE_SIZE))
4192 bytes = (unsigned)PAGE_SIZE - offset;
4193 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4194 offset, bytes);
4195 if (unlikely(ret < 0))
4196 return X86EMUL_IO_NEEDED;
4197
4198 return X86EMUL_CONTINUE;
1871c602
GN		 4199}
4200
064aea77 4201int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4202 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4203 struct x86_exception *exception)
1871c602 4204{
0f65dd70 4205 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4206 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4207
1871c602 4208 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4209 exception);
1871c602 4210}
064aea77 4211EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4212
0f65dd70
AK		 4213static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4214 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4215 struct x86_exception *exception)
1871c602 4216{
0f65dd70 4217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4218 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4219}
4220
6a4d7550 4221int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4222 gva_t addr, void *val,
2dafc6c2 4223 unsigned int bytes,
bcc55cba 4224 struct x86_exception *exception)
77c2002e 4225{
0f65dd70 4226 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4227 void *data = val;
4228 int r = X86EMUL_CONTINUE;
4229
4230 while (bytes) {
14dfe855
JR		 4231 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4232 PFERR_WRITE_MASK,
ab9ae313 4233 exception);
77c2002e
IE		 4234 unsigned offset = addr & (PAGE_SIZE-1);
4235 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4236 int ret;
4237
bcc55cba 4238 if (gpa == UNMAPPED_GVA)
ab9ae313 4239 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4240 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4241 if (ret < 0) {
c3cd7ffa 4242 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4243 goto out;
4244 }
4245
4246 bytes -= towrite;
4247 data += towrite;
4248 addr += towrite;
4249 }
4250out:
4251 return r;
4252}
6a4d7550 4253EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4254
af7cc7d1
XG		 4255static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4256 gpa_t *gpa, struct x86_exception *exception,
4257 bool write)
4258{
97d64b78
AK		 4259 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4260 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4261
97d64b78 4262 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4263 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4264 vcpu->arch.access, access)) {
bebb106a
XG		 4265 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4266 (gva & (PAGE_SIZE - 1));
4f022648 4267 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4268 return 1;
4269 }
4270
af7cc7d1
XG		 4271 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4272
4273 if (*gpa == UNMAPPED_GVA)
4274 return -1;
4275
4276 /* For APIC access vmexit */
4277 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4278 return 1;
4279
4f022648
XG		 4280 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4281 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4282 return 1;
4f022648 4283 }
bebb106a 4284
af7cc7d1
XG		 4285 return 0;
4286}
4287
3200f405 4288int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4289 const void *val, int bytes)
bbd9b64e
CO		 4290{
4291 int ret;
4292
4293 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4294 if (ret < 0)
bbd9b64e 4295 return 0;
f57f2ef5 4296 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4297 return 1;
4298}
4299
77d197b2
XG		 4300struct read_write_emulator_ops {
4301 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4302 int bytes);
4303 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4304 void *val, int bytes);
4305 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4306 int bytes, void *val);
4307 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4308 void *val, int bytes);
4309 bool write;
4310};
4311
4312static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4313{
4314 if (vcpu->mmio_read_completed) {
77d197b2 4315 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4316 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4317 vcpu->mmio_read_completed = 0;
4318 return 1;
4319 }
4320
4321 return 0;
4322}
4323
4324static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4325 void *val, int bytes)
4326{
4327 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4328}
4329
4330static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4331 void *val, int bytes)
4332{
4333 return emulator_write_phys(vcpu, gpa, val, bytes);
4334}
4335
4336static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4337{
4338 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4339 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4340}
4341
4342static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4343 void *val, int bytes)
4344{
4345 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4346 return X86EMUL_IO_NEEDED;
4347}
4348
4349static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4350 void *val, int bytes)
4351{
f78146b0
AK		 4352 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4353
87da7e66 4354 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4355 return X86EMUL_CONTINUE;
4356}
4357
0fbe9b0b 4358static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4359 .read_write_prepare = read_prepare,
4360 .read_write_emulate = read_emulate,
4361 .read_write_mmio = vcpu_mmio_read,
4362 .read_write_exit_mmio = read_exit_mmio,
4363};
4364
0fbe9b0b 4365static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4366 .read_write_emulate = write_emulate,
4367 .read_write_mmio = write_mmio,
4368 .read_write_exit_mmio = write_exit_mmio,
4369 .write = true,
4370};
4371
22388a3c
XG		 4372static int emulator_read_write_onepage(unsigned long addr, void *val,
4373 unsigned int bytes,
4374 struct x86_exception *exception,
4375 struct kvm_vcpu *vcpu,
0fbe9b0b 4376 const struct read_write_emulator_ops *ops)
bbd9b64e 4377{
af7cc7d1
XG		 4378 gpa_t gpa;
4379 int handled, ret;
22388a3c 4380 bool write = ops->write;
f78146b0 4381 struct kvm_mmio_fragment *frag;
10589a46 4382
22388a3c 4383 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4384
af7cc7d1 4385 if (ret < 0)
bbd9b64e 4386 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4387
4388 /* For APIC access vmexit */
af7cc7d1 4389 if (ret)
bbd9b64e
CO		 4390 goto mmio;
4391
22388a3c 4392 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4393 return X86EMUL_CONTINUE;
4394
4395mmio:
4396 /*
4397 * Is this MMIO handled locally?
4398 */
22388a3c 4399 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4400 if (handled == bytes)
bbd9b64e 4401 return X86EMUL_CONTINUE;
bbd9b64e 4402
70252a10
AK		 4403 gpa += handled;
4404 bytes -= handled;
4405 val += handled;
4406
87da7e66
XG		 4407 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4408 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4409 frag->gpa = gpa;
4410 frag->data = val;
4411 frag->len = bytes;
f78146b0 4412 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4413}
4414
22388a3c
XG		 4415int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4416 void *val, unsigned int bytes,
4417 struct x86_exception *exception,
0fbe9b0b 4418 const struct read_write_emulator_ops *ops)
bbd9b64e 4419{
0f65dd70 4420 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4421 gpa_t gpa;
4422 int rc;
4423
4424 if (ops->read_write_prepare &&
4425 ops->read_write_prepare(vcpu, val, bytes))
4426 return X86EMUL_CONTINUE;
4427
4428 vcpu->mmio_nr_fragments = 0;
0f65dd70 4429
bbd9b64e
CO		 4430 /* Crossing a page boundary? */
4431 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4432 int now;
bbd9b64e
CO		 4433
4434 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4435 rc = emulator_read_write_onepage(addr, val, now, exception,
4436 vcpu, ops);
4437
bbd9b64e
CO		 4438 if (rc != X86EMUL_CONTINUE)
4439 return rc;
4440 addr += now;
4441 val += now;
4442 bytes -= now;
4443 }
22388a3c 4444
f78146b0
AK		 4445 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4446 vcpu, ops);
4447 if (rc != X86EMUL_CONTINUE)
4448 return rc;
4449
4450 if (!vcpu->mmio_nr_fragments)
4451 return rc;
4452
4453 gpa = vcpu->mmio_fragments[0].gpa;
4454
4455 vcpu->mmio_needed = 1;
4456 vcpu->mmio_cur_fragment = 0;
4457
87da7e66 4458 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4459 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4460 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4461 vcpu->run->mmio.phys_addr = gpa;
4462
4463 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4464}
4465
4466static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4467 unsigned long addr,
4468 void *val,
4469 unsigned int bytes,
4470 struct x86_exception *exception)
4471{
4472 return emulator_read_write(ctxt, addr, val, bytes,
4473 exception, &read_emultor);
4474}
4475
4476int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4477 unsigned long addr,
4478 const void *val,
4479 unsigned int bytes,
4480 struct x86_exception *exception)
4481{
4482 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4483 exception, &write_emultor);
bbd9b64e 4484}
bbd9b64e 4485
daea3e73
AK		 4486#define CMPXCHG_TYPE(t, ptr, old, new) \
4487 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4488
4489#ifdef CONFIG_X86_64
4490# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4491#else
4492# define CMPXCHG64(ptr, old, new) \
9749a6c0 4493 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4494#endif
4495
0f65dd70
AK		 4496static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4497 unsigned long addr,
bbd9b64e
CO		 4498 const void *old,
4499 const void *new,
4500 unsigned int bytes,
0f65dd70 4501 struct x86_exception *exception)
bbd9b64e 4502{
0f65dd70 4503 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4504 gpa_t gpa;
4505 struct page *page;
4506 char *kaddr;
4507 bool exchanged;
2bacc55c 4508
daea3e73
AK		 4509 /* guests cmpxchg8b have to be emulated atomically */
4510 if (bytes > 8 || (bytes & (bytes - 1)))
4511 goto emul_write;
10589a46 4512
daea3e73 4513 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4514
daea3e73
AK		 4515 if (gpa == UNMAPPED_GVA ||
4516 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4517 goto emul_write;
2bacc55c 4518
daea3e73
AK		 4519 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4520 goto emul_write;
72dc67a6 4521
daea3e73 4522 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4523 if (is_error_page(page))
c19b8bd6 4524 goto emul_write;
72dc67a6 4525
8fd75e12 4526 kaddr = kmap_atomic(page);
daea3e73
AK		 4527 kaddr += offset_in_page(gpa);
4528 switch (bytes) {
4529 case 1:
4530 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4531 break;
4532 case 2:
4533 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4534 break;
4535 case 4:
4536 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4537 break;
4538 case 8:
4539 exchanged = CMPXCHG64(kaddr, old, new);
4540 break;
4541 default:
4542 BUG();
2bacc55c 4543 }
8fd75e12 4544 kunmap_atomic(kaddr);
daea3e73
AK		 4545 kvm_release_page_dirty(page);
4546
4547 if (!exchanged)
4548 return X86EMUL_CMPXCHG_FAILED;
4549
d3714010 4550 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4551 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4552
4553 return X86EMUL_CONTINUE;
4a5f48f6 4554
3200f405 4555emul_write:
daea3e73 4556 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4557
0f65dd70 4558 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4559}
4560
cf8f70bf
GN		 4561static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4562{
4563 /* TODO: String I/O for in kernel device */
4564 int r;
4565
4566 if (vcpu->arch.pio.in)
4567 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4568 vcpu->arch.pio.size, pd);
4569 else
4570 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4571 vcpu->arch.pio.port, vcpu->arch.pio.size,
4572 pd);
4573 return r;
4574}
4575
6f6fbe98
XG		 4576static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4577 unsigned short port, void *val,
4578 unsigned int count, bool in)
cf8f70bf 4579{
cf8f70bf 4580 vcpu->arch.pio.port = port;
6f6fbe98 4581 vcpu->arch.pio.in = in;
7972995b 4582 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4583 vcpu->arch.pio.size = size;
4584
4585 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4586 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4587 return 1;
4588 }
4589
4590 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4591 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4592 vcpu->run->io.size = size;
4593 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4594 vcpu->run->io.count = count;
4595 vcpu->run->io.port = port;
4596
4597 return 0;
4598}
4599
6f6fbe98
XG		 4600static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4601 int size, unsigned short port, void *val,
4602 unsigned int count)
cf8f70bf 4603{
ca1d4a9e 4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4605 int ret;
ca1d4a9e 4606
6f6fbe98
XG		 4607 if (vcpu->arch.pio.count)
4608 goto data_avail;
cf8f70bf 4609
6f6fbe98
XG		 4610 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4611 if (ret) {
4612data_avail:
4613 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4614 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4615 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4616 return 1;
4617 }
4618
cf8f70bf
GN		 4619 return 0;
4620}
4621
6f6fbe98
XG		 4622static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4623 int size, unsigned short port,
4624 const void *val, unsigned int count)
4625{
4626 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4627
4628 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4629 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4630 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4631}
4632
bbd9b64e
CO		 4633static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4634{
4635 return kvm_x86_ops->get_segment_base(vcpu, seg);
4636}
4637
3cb16fe7 4638static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4639{
3cb16fe7 4640 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4641}
4642
f5f48ee1
SY		 4643int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4644{
4645 if (!need_emulate_wbinvd(vcpu))
4646 return X86EMUL_CONTINUE;
4647
4648 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4649 int cpu = get_cpu();
4650
4651 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4652 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4653 wbinvd_ipi, NULL, 1);
2eec7343 4654 put_cpu();
f5f48ee1 4655 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4656 } else
4657 wbinvd();
f5f48ee1
SY		 4658 return X86EMUL_CONTINUE;
4659}
4660EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4661
bcaf5cc5
AK		 4662static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4663{
4664 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4665}
4666
717746e3 4667int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4668{
16f8a6f9 4669 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4670}
4671
717746e3 4672int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4673{
338dbc97 4674
717746e3 4675 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4676}
4677
52a46617 4678static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4679{
52a46617 4680 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4681}
4682
717746e3 4683static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4684{
717746e3 4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4686 unsigned long value;
4687
4688 switch (cr) {
4689 case 0:
4690 value = kvm_read_cr0(vcpu);
4691 break;
4692 case 2:
4693 value = vcpu->arch.cr2;
4694 break;
4695 case 3:
9f8fe504 4696 value = kvm_read_cr3(vcpu);
52a46617
GN		 4697 break;
4698 case 4:
4699 value = kvm_read_cr4(vcpu);
4700 break;
4701 case 8:
4702 value = kvm_get_cr8(vcpu);
4703 break;
4704 default:
a737f256 4705 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4706 return 0;
4707 }
4708
4709 return value;
4710}
4711
717746e3 4712static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4713{
717746e3 4714 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4715 int res = 0;
4716
52a46617
GN		 4717 switch (cr) {
4718 case 0:
49a9b07e 4719 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4720 break;
4721 case 2:
4722 vcpu->arch.cr2 = val;
4723 break;
4724 case 3:
2390218b 4725 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4726 break;
4727 case 4:
a83b29c6 4728 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4729 break;
4730 case 8:
eea1cff9 4731 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4732 break;
4733 default:
a737f256 4734 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4735 res = -1;
52a46617 4736 }
0f12244f
GN		 4737
4738 return res;
52a46617
GN		 4739}
4740
717746e3 4741static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4742{
717746e3 4743 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4744}
4745
4bff1e86 4746static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4747{
4bff1e86 4748 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4749}
4750
4bff1e86 4751static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4752{
4bff1e86 4753 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4754}
4755
1ac9d0cf
AK		 4756static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4757{
4758 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4759}
4760
4761static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4762{
4763 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4764}
4765
4bff1e86
AK		 4766static unsigned long emulator_get_cached_segment_base(
4767 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4768{
4bff1e86 4769 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4770}
4771
1aa36616
AK		 4772static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4773 struct desc_struct *desc, u32 *base3,
4774 int seg)
2dafc6c2
GN		 4775{
4776 struct kvm_segment var;
4777
4bff1e86 4778 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4779 *selector = var.selector;
2dafc6c2 4780
378a8b09
GN		 4781 if (var.unusable) {
4782 memset(desc, 0, sizeof(*desc));
2dafc6c2 4783 return false;
378a8b09 4784 }
2dafc6c2
GN		 4785
4786 if (var.g)
4787 var.limit >>= 12;
4788 set_desc_limit(desc, var.limit);
4789 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4790#ifdef CONFIG_X86_64
4791 if (base3)
4792 *base3 = var.base >> 32;
4793#endif
2dafc6c2
GN		 4794 desc->type = var.type;
4795 desc->s = var.s;
4796 desc->dpl = var.dpl;
4797 desc->p = var.present;
4798 desc->avl = var.avl;
4799 desc->l = var.l;
4800 desc->d = var.db;
4801 desc->g = var.g;
4802
4803 return true;
4804}
4805
1aa36616
AK		 4806static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4807 struct desc_struct *desc, u32 base3,
4808 int seg)
2dafc6c2 4809{
4bff1e86 4810 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4811 struct kvm_segment var;
4812
1aa36616 4813 var.selector = selector;
2dafc6c2 4814 var.base = get_desc_base(desc);
5601d05b
GN		 4815#ifdef CONFIG_X86_64
4816 var.base |= ((u64)base3) << 32;
4817#endif
2dafc6c2
GN		 4818 var.limit = get_desc_limit(desc);
4819 if (desc->g)
4820 var.limit = (var.limit << 12) | 0xfff;
4821 var.type = desc->type;
2dafc6c2
GN		 4822 var.dpl = desc->dpl;
4823 var.db = desc->d;
4824 var.s = desc->s;
4825 var.l = desc->l;
4826 var.g = desc->g;
4827 var.avl = desc->avl;
4828 var.present = desc->p;
4829 var.unusable = !var.present;
4830 var.padding = 0;
4831
4832 kvm_set_segment(vcpu, &var, seg);
4833 return;
4834}
4835
717746e3
AK		 4836static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4837 u32 msr_index, u64 *pdata)
4838{
4839 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4840}
4841
4842static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4843 u32 msr_index, u64 data)
4844{
8fe8ab46
WA		 4845 struct msr_data msr;
4846
4847 msr.data = data;
4848 msr.index = msr_index;
4849 msr.host_initiated = false;
4850 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4851}
4852
67f4d428
NA		 4853static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4854 u32 pmc)
4855{
4856 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4857}
4858
222d21aa
AK		 4859static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4860 u32 pmc, u64 *pdata)
4861{
4862 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4863}
4864
6c3287f7
AK		 4865static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4866{
4867 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4868}
4869
5037f6f3
AK		 4870static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4871{
4872 preempt_disable();
5197b808 4873 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4874 /*
4875 * CR0.TS may reference the host fpu state, not the guest fpu state,
4876 * so it may be clear at this point.
4877 */
4878 clts();
4879}
4880
4881static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4882{
4883 preempt_enable();
4884}
4885
2953538e 4886static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4887 struct x86_instruction_info *info,
c4f035c6
AK		 4888 enum x86_intercept_stage stage)
4889{
2953538e 4890 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4891}
4892
0017f93a 4893static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4894 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4895{
0017f93a 4896 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4897}
4898
dd856efa
AK		 4899static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4900{
4901 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4902}
4903
4904static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4905{
4906 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4907}
4908
0225fb50 4909static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4910 .read_gpr = emulator_read_gpr,
4911 .write_gpr = emulator_write_gpr,
1871c602 4912 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4913 .write_std = kvm_write_guest_virt_system,
1871c602 4914 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4915 .read_emulated = emulator_read_emulated,
4916 .write_emulated = emulator_write_emulated,
4917 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4918 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4919 .pio_in_emulated = emulator_pio_in_emulated,
4920 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4921 .get_segment = emulator_get_segment,
4922 .set_segment = emulator_set_segment,
5951c442 4923 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4924 .get_gdt = emulator_get_gdt,
160ce1f1 4925 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4926 .set_gdt = emulator_set_gdt,
4927 .set_idt = emulator_set_idt,
52a46617
GN		 4928 .get_cr = emulator_get_cr,
4929 .set_cr = emulator_set_cr,
9c537244 4930 .cpl = emulator_get_cpl,
35aa5375
GN		 4931 .get_dr = emulator_get_dr,
4932 .set_dr = emulator_set_dr,
717746e3
AK		 4933 .set_msr = emulator_set_msr,
4934 .get_msr = emulator_get_msr,
67f4d428 4935 .check_pmc = emulator_check_pmc,
222d21aa 4936 .read_pmc = emulator_read_pmc,
6c3287f7 4937 .halt = emulator_halt,
bcaf5cc5 4938 .wbinvd = emulator_wbinvd,
d6aa1000 4939 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4940 .get_fpu = emulator_get_fpu,
4941 .put_fpu = emulator_put_fpu,
c4f035c6 4942 .intercept = emulator_intercept,
bdb42f5a 4943 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4944};
4945
95cb2295
GN		 4946static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4947{
37ccdcbe 4948 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4949 /*
4950 * an sti; sti; sequence only disable interrupts for the first
4951 * instruction. So, if the last instruction, be it emulated or
4952 * not, left the system with the INT_STI flag enabled, it
4953 * means that the last instruction is an sti. We should not
4954 * leave the flag on in this case. The same goes for mov ss
4955 */
37ccdcbe
PB		 4956 if (int_shadow & mask)
4957 mask = 0;
6addfc42 4958 if (unlikely(int_shadow || mask)) {
95cb2295 4959 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4960 if (!mask)
4961 kvm_make_request(KVM_REQ_EVENT, vcpu);
4962 }
95cb2295
GN		 4963}
4964
ef54bcfe 4965static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4966{
4967 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4968 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4969 return kvm_propagate_fault(vcpu, &ctxt->exception);
4970
4971 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4972 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4973 ctxt->exception.error_code);
54b8486f 4974 else
da9cb575 4975 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4976 return false;
54b8486f
GN		 4977}
4978
8ec4722d
MG		 4979static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4980{
adf52235 4981 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4982 int cs_db, cs_l;
4983
8ec4722d
MG		 4984 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4985
adf52235
TY		 4986 ctxt->eflags = kvm_get_rflags(vcpu);
4987 ctxt->eip = kvm_rip_read(vcpu);
4988 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4989 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4990 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4991 cs_db ? X86EMUL_MODE_PROT32 :
4992 X86EMUL_MODE_PROT16;
4993 ctxt->guest_mode = is_guest_mode(vcpu);
4994
dd856efa 4995 init_decode_cache(ctxt);
7ae441ea 4996 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4997}
4998
71f9833b 4999int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5000{
9d74191a 5001 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5002 int ret;
5003
5004 init_emulate_ctxt(vcpu);
5005
9dac77fa
AK		 5006 ctxt->op_bytes = 2;
5007 ctxt->ad_bytes = 2;
5008 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5009 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5010
5011 if (ret != X86EMUL_CONTINUE)
5012 return EMULATE_FAIL;
5013
9dac77fa 5014 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5015 kvm_rip_write(vcpu, ctxt->eip);
5016 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5017
5018 if (irq == NMI_VECTOR)
7460fb4a 5019 vcpu->arch.nmi_pending = 0;
63995653
MG		 5020 else
5021 vcpu->arch.interrupt.pending = false;
5022
5023 return EMULATE_DONE;
5024}
5025EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5026
6d77dbfc
GN		 5027static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5028{
fc3a9157
JR		 5029 int r = EMULATE_DONE;
5030
6d77dbfc
GN		 5031 ++vcpu->stat.insn_emulation_fail;
5032 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5033 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5034 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5035 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5036 vcpu->run->internal.ndata = 0;
5037 r = EMULATE_FAIL;
5038 }
6d77dbfc 5039 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5040
5041 return r;
6d77dbfc
GN		 5042}
5043
93c05d3e 5044static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5045 bool write_fault_to_shadow_pgtable,
5046 int emulation_type)
a6f177ef 5047{
95b3cf69 5048 gpa_t gpa = cr2;
8e3d9d06 5049 pfn_t pfn;
a6f177ef 5050
991eebf9
GN		 5051 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5052 return false;
5053
95b3cf69
XG		 5054 if (!vcpu->arch.mmu.direct_map) {
5055 /*
5056 * Write permission should be allowed since only
5057 * write access need to be emulated.
5058 */
5059 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5060
95b3cf69
XG		 5061 /*
5062 * If the mapping is invalid in guest, let cpu retry
5063 * it to generate fault.
5064 */
5065 if (gpa == UNMAPPED_GVA)
5066 return true;
5067 }
a6f177ef 5068
8e3d9d06
XG		 5069 /*
5070 * Do not retry the unhandleable instruction if it faults on the
5071 * readonly host memory, otherwise it will goto a infinite loop:
5072 * retry instruction -> write #PF -> emulation fail -> retry
5073 * instruction -> ...
5074 */
5075 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5076
5077 /*
5078 * If the instruction failed on the error pfn, it can not be fixed,
5079 * report the error to userspace.
5080 */
5081 if (is_error_noslot_pfn(pfn))
5082 return false;
5083
5084 kvm_release_pfn_clean(pfn);
5085
5086 /* The instructions are well-emulated on direct mmu. */
5087 if (vcpu->arch.mmu.direct_map) {
5088 unsigned int indirect_shadow_pages;
5089
5090 spin_lock(&vcpu->kvm->mmu_lock);
5091 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5092 spin_unlock(&vcpu->kvm->mmu_lock);
5093
5094 if (indirect_shadow_pages)
5095 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5096
a6f177ef 5097 return true;
8e3d9d06 5098 }
a6f177ef 5099
95b3cf69
XG		 5100 /*
5101 * if emulation was due to access to shadowed page table
5102 * and it failed try to unshadow page and re-enter the
5103 * guest to let CPU execute the instruction.
5104 */
5105 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5106
5107 /*
5108 * If the access faults on its page table, it can not
5109 * be fixed by unprotecting shadow page and it should
5110 * be reported to userspace.
5111 */
5112 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5113}
5114
1cb3f3ae
XG		 5115static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5116 unsigned long cr2, int emulation_type)
5117{
5118 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5119 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5120
5121 last_retry_eip = vcpu->arch.last_retry_eip;
5122 last_retry_addr = vcpu->arch.last_retry_addr;
5123
5124 /*
5125 * If the emulation is caused by #PF and it is non-page_table
5126 * writing instruction, it means the VM-EXIT is caused by shadow
5127 * page protected, we can zap the shadow page and retry this
5128 * instruction directly.
5129 *
5130 * Note: if the guest uses a non-page-table modifying instruction
5131 * on the PDE that points to the instruction, then we will unmap
5132 * the instruction and go to an infinite loop. So, we cache the
5133 * last retried eip and the last fault address, if we meet the eip
5134 * and the address again, we can break out of the potential infinite
5135 * loop.
5136 */
5137 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5138
5139 if (!(emulation_type & EMULTYPE_RETRY))
5140 return false;
5141
5142 if (x86_page_table_writing_insn(ctxt))
5143 return false;
5144
5145 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5146 return false;
5147
5148 vcpu->arch.last_retry_eip = ctxt->eip;
5149 vcpu->arch.last_retry_addr = cr2;
5150
5151 if (!vcpu->arch.mmu.direct_map)
5152 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5153
22368028 5154 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5155
5156 return true;
5157}
5158
716d51ab
GN		 5159static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5160static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5161
4a1e10d5
PB		 5162static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5163 unsigned long *db)
5164{
5165 u32 dr6 = 0;
5166 int i;
5167 u32 enable, rwlen;
5168
5169 enable = dr7;
5170 rwlen = dr7 >> 16;
5171 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5172 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5173 dr6 |= (1 << i);
5174 return dr6;
5175}
5176
6addfc42 5177static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5178{
5179 struct kvm_run *kvm_run = vcpu->run;
5180
5181 /*
6addfc42
PB		 5182 * rflags is the old, "raw" value of the flags. The new value has
5183 * not been saved yet.
663f4c61
PB		 5184 *
5185 * This is correct even for TF set by the guest, because "the
5186 * processor will not generate this exception after the instruction
5187 * that sets the TF flag".
5188 */
663f4c61
PB		 5189 if (unlikely(rflags & X86_EFLAGS_TF)) {
5190 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5191 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5192 DR6_RTM;
663f4c61
PB		 5193 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5194 kvm_run->debug.arch.exception = DB_VECTOR;
5195 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5196 *r = EMULATE_USER_EXIT;
5197 } else {
5198 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5199 /*
5200 * "Certain debug exceptions may clear bit 0-3. The
5201 * remaining contents of the DR6 register are never
5202 * cleared by the processor".
5203 */
5204 vcpu->arch.dr6 &= ~15;
6f43ed01 5205 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5206 kvm_queue_exception(vcpu, DB_VECTOR);
5207 }
5208 }
5209}
5210
4a1e10d5
PB		 5211static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5212{
4a1e10d5
PB		 5213 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5214 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5215 struct kvm_run *kvm_run = vcpu->run;
5216 unsigned long eip = kvm_get_linear_rip(vcpu);
5217 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5218 vcpu->arch.guest_debug_dr7,
5219 vcpu->arch.eff_db);
5220
5221 if (dr6 != 0) {
6f43ed01 5222 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5223 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5224 kvm_run->debug.arch.exception = DB_VECTOR;
5225 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5226 *r = EMULATE_USER_EXIT;
5227 return true;
5228 }
5229 }
5230
4161a569
NA		 5231 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5232 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5233 unsigned long eip = kvm_get_linear_rip(vcpu);
5234 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5235 vcpu->arch.dr7,
5236 vcpu->arch.db);
5237
5238 if (dr6 != 0) {
5239 vcpu->arch.dr6 &= ~15;
6f43ed01 5240 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5241 kvm_queue_exception(vcpu, DB_VECTOR);
5242 *r = EMULATE_DONE;
5243 return true;
5244 }
5245 }
5246
5247 return false;
5248}
5249
51d8b661
AP		 5250int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5251 unsigned long cr2,
dc25e89e
AP		 5252 int emulation_type,
5253 void *insn,
5254 int insn_len)
bbd9b64e 5255{
95cb2295 5256 int r;
9d74191a 5257 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5258 bool writeback = true;
93c05d3e 5259 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5260
93c05d3e
XG		 5261 /*
5262 * Clear write_fault_to_shadow_pgtable here to ensure it is
5263 * never reused.
5264 */
5265 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5266 kvm_clear_exception_queue(vcpu);
8d7d8102 5267
571008da 5268 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5269 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5270
5271 /*
5272 * We will reenter on the same instruction since
5273 * we do not set complete_userspace_io. This does not
5274 * handle watchpoints yet, those would be handled in
5275 * the emulate_ops.
5276 */
5277 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5278 return r;
5279
9d74191a
TY		 5280 ctxt->interruptibility = 0;
5281 ctxt->have_exception = false;
e0ad0b47 5282 ctxt->exception.vector = -1;
9d74191a 5283 ctxt->perm_ok = false;
bbd9b64e 5284
b51e974f 5285 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5286
9d74191a 5287 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5288
e46479f8 5289 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5290 ++vcpu->stat.insn_emulation;
1d2887e2 5291 if (r != EMULATION_OK) {
4005996e
AK		 5292 if (emulation_type & EMULTYPE_TRAP_UD)
5293 return EMULATE_FAIL;
991eebf9
GN		 5294 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5295 emulation_type))
bbd9b64e 5296 return EMULATE_DONE;
6d77dbfc
GN		 5297 if (emulation_type & EMULTYPE_SKIP)
5298 return EMULATE_FAIL;
5299 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5300 }
5301 }
5302
ba8afb6b 5303 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5304 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5305 if (ctxt->eflags & X86_EFLAGS_RF)
5306 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5307 return EMULATE_DONE;
5308 }
5309
1cb3f3ae
XG		 5310 if (retry_instruction(ctxt, cr2, emulation_type))
5311 return EMULATE_DONE;
5312
7ae441ea 5313 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5314 changes registers values during IO operation */
7ae441ea
GN		 5315 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5316 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5317 emulator_invalidate_register_cache(ctxt);
7ae441ea 5318 }
4d2179e1 5319
5cd21917 5320restart:
9d74191a 5321 r = x86_emulate_insn(ctxt);
bbd9b64e 5322
775fde86
JR		 5323 if (r == EMULATION_INTERCEPTED)
5324 return EMULATE_DONE;
5325
d2ddd1c4 5326 if (r == EMULATION_FAILED) {
991eebf9
GN		 5327 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5328 emulation_type))
c3cd7ffa
GN		 5329 return EMULATE_DONE;
5330
6d77dbfc 5331 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5332 }
5333
9d74191a 5334 if (ctxt->have_exception) {
d2ddd1c4 5335 r = EMULATE_DONE;
ef54bcfe
PB		 5336 if (inject_emulated_exception(vcpu))
5337 return r;
d2ddd1c4 5338 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5339 if (!vcpu->arch.pio.in) {
5340 /* FIXME: return into emulator if single-stepping. */
3457e419 5341 vcpu->arch.pio.count = 0;
0912c977 5342 } else {
7ae441ea 5343 writeback = false;
716d51ab
GN		 5344 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5345 }
ac0a48c3 5346 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5347 } else if (vcpu->mmio_needed) {
5348 if (!vcpu->mmio_is_write)
5349 writeback = false;
ac0a48c3 5350 r = EMULATE_USER_EXIT;
716d51ab 5351 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5352 } else if (r == EMULATION_RESTART)
5cd21917 5353 goto restart;
d2ddd1c4
GN		 5354 else
5355 r = EMULATE_DONE;
f850e2e6 5356
7ae441ea 5357 if (writeback) {
6addfc42 5358 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5359 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5360 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5361 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5362 if (r == EMULATE_DONE)
6addfc42 5363 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5364 if (!ctxt->have_exception ||
5365 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5366 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5367
5368 /*
5369 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5370 * do nothing, and it will be requested again as soon as
5371 * the shadow expires. But we still need to check here,
5372 * because POPF has no interrupt shadow.
5373 */
5374 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5375 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5376 } else
5377 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5378
5379 return r;
de7d789a 5380}
51d8b661 5381EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5382
cf8f70bf 5383int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5384{
cf8f70bf 5385 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5386 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5387 size, port, &val, 1);
cf8f70bf 5388 /* do not return to emulator after return from userspace */
7972995b 5389 vcpu->arch.pio.count = 0;
de7d789a
CO		 5390 return ret;
5391}
cf8f70bf 5392EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5393
8cfdc000
ZA		 5394static void tsc_bad(void *info)
5395{
0a3aee0d 5396 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5397}
5398
5399static void tsc_khz_changed(void *data)
c8076604 5400{
8cfdc000
ZA		 5401 struct cpufreq_freqs *freq = data;
5402 unsigned long khz = 0;
5403
5404 if (data)
5405 khz = freq->new;
5406 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5407 khz = cpufreq_quick_get(raw_smp_processor_id());
5408 if (!khz)
5409 khz = tsc_khz;
0a3aee0d 5410 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5411}
5412
c8076604
GH		 5413static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5414 void *data)
5415{
5416 struct cpufreq_freqs *freq = data;
5417 struct kvm *kvm;
5418 struct kvm_vcpu *vcpu;
5419 int i, send_ipi = 0;
5420
8cfdc000
ZA		 5421 /*
5422 * We allow guests to temporarily run on slowing clocks,
5423 * provided we notify them after, or to run on accelerating
5424 * clocks, provided we notify them before. Thus time never
5425 * goes backwards.
5426 *
5427 * However, we have a problem. We can't atomically update
5428 * the frequency of a given CPU from this function; it is
5429 * merely a notifier, which can be called from any CPU.
5430 * Changing the TSC frequency at arbitrary points in time
5431 * requires a recomputation of local variables related to
5432 * the TSC for each VCPU. We must flag these local variables
5433 * to be updated and be sure the update takes place with the
5434 * new frequency before any guests proceed.
5435 *
5436 * Unfortunately, the combination of hotplug CPU and frequency
5437 * change creates an intractable locking scenario; the order
5438 * of when these callouts happen is undefined with respect to
5439 * CPU hotplug, and they can race with each other. As such,
5440 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5441 * undefined; you can actually have a CPU frequency change take
5442 * place in between the computation of X and the setting of the
5443 * variable. To protect against this problem, all updates of
5444 * the per_cpu tsc_khz variable are done in an interrupt
5445 * protected IPI, and all callers wishing to update the value
5446 * must wait for a synchronous IPI to complete (which is trivial
5447 * if the caller is on the CPU already). This establishes the
5448 * necessary total order on variable updates.
5449 *
5450 * Note that because a guest time update may take place
5451 * anytime after the setting of the VCPU's request bit, the
5452 * correct TSC value must be set before the request. However,
5453 * to ensure the update actually makes it to any guest which
5454 * starts running in hardware virtualization between the set
5455 * and the acquisition of the spinlock, we must also ping the
5456 * CPU after setting the request bit.
5457 *
5458 */
5459
c8076604
GH		 5460 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5461 return 0;
5462 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5463 return 0;
8cfdc000
ZA		 5464
5465 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5466
2f303b74 5467 spin_lock(&kvm_lock);
c8076604 5468 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5469 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5470 if (vcpu->cpu != freq->cpu)
5471 continue;
c285545f 5472 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5473 if (vcpu->cpu != smp_processor_id())
8cfdc000 5474 send_ipi = 1;
c8076604
GH		 5475 }
5476 }
2f303b74 5477 spin_unlock(&kvm_lock);
c8076604
GH		 5478
5479 if (freq->old < freq->new && send_ipi) {
5480 /*
5481 * We upscale the frequency. Must make the guest
5482 * doesn't see old kvmclock values while running with
5483 * the new frequency, otherwise we risk the guest sees
5484 * time go backwards.
5485 *
5486 * In case we update the frequency for another cpu
5487 * (which might be in guest context) send an interrupt
5488 * to kick the cpu out of guest context. Next time
5489 * guest context is entered kvmclock will be updated,
5490 * so the guest will not see stale values.
5491 */
8cfdc000 5492 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5493 }
5494 return 0;
5495}
5496
5497static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5498 .notifier_call = kvmclock_cpufreq_notifier
5499};
5500
5501static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5502 unsigned long action, void *hcpu)
5503{
5504 unsigned int cpu = (unsigned long)hcpu;
5505
5506 switch (action) {
5507 case CPU_ONLINE:
5508 case CPU_DOWN_FAILED:
5509 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5510 break;
5511 case CPU_DOWN_PREPARE:
5512 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5513 break;
5514 }
5515 return NOTIFY_OK;
5516}
5517
5518static struct notifier_block kvmclock_cpu_notifier_block = {
5519 .notifier_call = kvmclock_cpu_notifier,
5520 .priority = -INT_MAX
c8076604
GH		 5521};
5522
b820cc0c
ZA		 5523static void kvm_timer_init(void)
5524{
5525 int cpu;
5526
c285545f 5527 max_tsc_khz = tsc_khz;
460dd42e
SB		 5528
5529 cpu_notifier_register_begin();
b820cc0c 5530 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5531#ifdef CONFIG_CPU_FREQ
5532 struct cpufreq_policy policy;
5533 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5534 cpu = get_cpu();
5535 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5536 if (policy.cpuinfo.max_freq)
5537 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5538 put_cpu();
c285545f 5539#endif
b820cc0c
ZA		 5540 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5541 CPUFREQ_TRANSITION_NOTIFIER);
5542 }
c285545f 5543 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5544 for_each_online_cpu(cpu)
5545 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5546
5547 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5548 cpu_notifier_register_done();
5549
b820cc0c
ZA		 5550}
5551
ff9d07a0
ZY		 5552static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5553
f5132b01 5554int kvm_is_in_guest(void)
ff9d07a0 5555{
086c9855 5556 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5557}
5558
5559static int kvm_is_user_mode(void)
5560{
5561 int user_mode = 3;
dcf46b94 5562
086c9855
AS		 5563 if (__this_cpu_read(current_vcpu))
5564 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5565
ff9d07a0
ZY		 5566 return user_mode != 0;
5567}
5568
5569static unsigned long kvm_get_guest_ip(void)
5570{
5571 unsigned long ip = 0;
dcf46b94 5572
086c9855
AS		 5573 if (__this_cpu_read(current_vcpu))
5574 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5575
ff9d07a0
ZY		 5576 return ip;
5577}
5578
5579static struct perf_guest_info_callbacks kvm_guest_cbs = {
5580 .is_in_guest = kvm_is_in_guest,
5581 .is_user_mode = kvm_is_user_mode,
5582 .get_guest_ip = kvm_get_guest_ip,
5583};
5584
5585void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5586{
086c9855 5587 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5588}
5589EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5590
5591void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5592{
086c9855 5593 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5594}
5595EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5596
ce88decf
XG		 5597static void kvm_set_mmio_spte_mask(void)
5598{
5599 u64 mask;
5600 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5601
5602 /*
5603 * Set the reserved bits and the present bit of an paging-structure
5604 * entry to generate page fault with PFER.RSV = 1.
5605 */
885032b9 5606 /* Mask the reserved physical address bits. */
d1431483 5607 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5608
5609 /* Bit 62 is always reserved for 32bit host. */
5610 mask |= 0x3ull << 62;
5611
5612 /* Set the present bit. */
ce88decf
XG		 5613 mask |= 1ull;
5614
5615#ifdef CONFIG_X86_64
5616 /*
5617 * If reserved bit is not supported, clear the present bit to disable
5618 * mmio page fault.
5619 */
5620 if (maxphyaddr == 52)
5621 mask &= ~1ull;
5622#endif
5623
5624 kvm_mmu_set_mmio_spte_mask(mask);
5625}
5626
16e8d74d
MT		 5627#ifdef CONFIG_X86_64
5628static void pvclock_gtod_update_fn(struct work_struct *work)
5629{
d828199e
MT		 5630 struct kvm *kvm;
5631
5632 struct kvm_vcpu *vcpu;
5633 int i;
5634
2f303b74 5635 spin_lock(&kvm_lock);
d828199e
MT		 5636 list_for_each_entry(kvm, &vm_list, vm_list)
5637 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5638 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5639 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5640 spin_unlock(&kvm_lock);
16e8d74d
MT		 5641}
5642
5643static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5644
5645/*
5646 * Notification about pvclock gtod data update.
5647 */
5648static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5649 void *priv)
5650{
5651 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5652 struct timekeeper *tk = priv;
5653
5654 update_pvclock_gtod(tk);
5655
5656 /* disable master clock if host does not trust, or does not
5657 * use, TSC clocksource
5658 */
5659 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5660 atomic_read(&kvm_guest_has_master_clock) != 0)
5661 queue_work(system_long_wq, &pvclock_gtod_work);
5662
5663 return 0;
5664}
5665
5666static struct notifier_block pvclock_gtod_notifier = {
5667 .notifier_call = pvclock_gtod_notify,
5668};
5669#endif
5670
f8c16bba 5671int kvm_arch_init(void *opaque)
043405e1 5672{
b820cc0c 5673 int r;
6b61edf7 5674 struct kvm_x86_ops *ops = opaque;
f8c16bba 5675
f8c16bba
ZX		 5676 if (kvm_x86_ops) {
5677 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5678 r = -EEXIST;
5679 goto out;
f8c16bba
ZX		 5680 }
5681
5682 if (!ops->cpu_has_kvm_support()) {
5683 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5684 r = -EOPNOTSUPP;
5685 goto out;
f8c16bba
ZX		 5686 }
5687 if (ops->disabled_by_bios()) {
5688 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5689 r = -EOPNOTSUPP;
5690 goto out;
f8c16bba
ZX		 5691 }
5692
013f6a5d
MT		 5693 r = -ENOMEM;
5694 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5695 if (!shared_msrs) {
5696 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5697 goto out;
5698 }
5699
97db56ce
AK		 5700 r = kvm_mmu_module_init();
5701 if (r)
013f6a5d 5702 goto out_free_percpu;
97db56ce 5703
ce88decf 5704 kvm_set_mmio_spte_mask();
97db56ce 5705
f8c16bba 5706 kvm_x86_ops = ops;
920c8377
PB		 5707 kvm_init_msr_list();
5708
7b52345e 5709 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5710 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5711
b820cc0c 5712 kvm_timer_init();
c8076604 5713
ff9d07a0
ZY		 5714 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5715
2acf923e
DC		 5716 if (cpu_has_xsave)
5717 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5718
c5cc421b 5719 kvm_lapic_init();
16e8d74d
MT		 5720#ifdef CONFIG_X86_64
5721 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5722#endif
5723
f8c16bba 5724 return 0;
56c6d28a 5725
013f6a5d
MT		 5726out_free_percpu:
5727 free_percpu(shared_msrs);
56c6d28a 5728out:
56c6d28a 5729 return r;
043405e1 5730}
8776e519 5731
f8c16bba
ZX		 5732void kvm_arch_exit(void)
5733{
ff9d07a0
ZY		 5734 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5735
888d256e
JK		 5736 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5737 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5738 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5739 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5740#ifdef CONFIG_X86_64
5741 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5742#endif
f8c16bba 5743 kvm_x86_ops = NULL;
56c6d28a 5744 kvm_mmu_module_exit();
013f6a5d 5745 free_percpu(shared_msrs);
56c6d28a 5746}
f8c16bba 5747
8776e519
HB		 5748int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5749{
5750 ++vcpu->stat.halt_exits;
5751 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5752 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5753 return 1;
5754 } else {
5755 vcpu->run->exit_reason = KVM_EXIT_HLT;
5756 return 0;
5757 }
5758}
5759EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5760
55cd8e5a
GN		 5761int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5762{
5763 u64 param, ingpa, outgpa, ret;
5764 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5765 bool fast, longmode;
55cd8e5a
GN		 5766
5767 /*
5768 * hypercall generates UD from non zero cpl and real mode
5769 * per HYPER-V spec
5770 */
3eeb3288 5771 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5772 kvm_queue_exception(vcpu, UD_VECTOR);
5773 return 0;
5774 }
5775
a449c7aa 5776 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5777
5778 if (!longmode) {
ccd46936
GN		 5779 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5780 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5781 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5782 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5783 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5784 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5785 }
5786#ifdef CONFIG_X86_64
5787 else {
5788 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5789 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5790 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5791 }
5792#endif
5793
5794 code = param & 0xffff;
5795 fast = (param >> 16) & 0x1;
5796 rep_cnt = (param >> 32) & 0xfff;
5797 rep_idx = (param >> 48) & 0xfff;
5798
5799 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5800
c25bc163
GN		 5801 switch (code) {
5802 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5803 kvm_vcpu_on_spin(vcpu);
5804 break;
5805 default:
5806 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5807 break;
5808 }
55cd8e5a
GN		 5809
5810 ret = res | (((u64)rep_done & 0xfff) << 32);
5811 if (longmode) {
5812 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5813 } else {
5814 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5815 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5816 }
5817
5818 return 1;
5819}
5820
6aef266c
SV		 5821/*
5822 * kvm_pv_kick_cpu_op: Kick a vcpu.
5823 *
5824 * @apicid - apicid of vcpu to be kicked.
5825 */
5826static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5827{
24d2166b 5828 struct kvm_lapic_irq lapic_irq;
6aef266c 5829
24d2166b
R		 5830 lapic_irq.shorthand = 0;
5831 lapic_irq.dest_mode = 0;
5832 lapic_irq.dest_id = apicid;
6aef266c 5833
24d2166b
R		 5834 lapic_irq.delivery_mode = APIC_DM_REMRD;
5835 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5836}
5837
8776e519
HB		 5838int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5839{
5840 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5841 int op_64_bit, r = 1;
8776e519 5842
55cd8e5a
GN		 5843 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5844 return kvm_hv_hypercall(vcpu);
5845
5fdbf976
MT		 5846 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5847 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5848 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5849 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5850 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5851
229456fc 5852 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5853
a449c7aa
NA		 5854 op_64_bit = is_64_bit_mode(vcpu);
5855 if (!op_64_bit) {
8776e519
HB		 5856 nr &= 0xFFFFFFFF;
5857 a0 &= 0xFFFFFFFF;
5858 a1 &= 0xFFFFFFFF;
5859 a2 &= 0xFFFFFFFF;
5860 a3 &= 0xFFFFFFFF;
5861 }
5862
07708c4a
JK		 5863 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5864 ret = -KVM_EPERM;
5865 goto out;
5866 }
5867
8776e519 5868 switch (nr) {
b93463aa
AK		 5869 case KVM_HC_VAPIC_POLL_IRQ:
5870 ret = 0;
5871 break;
6aef266c
SV		 5872 case KVM_HC_KICK_CPU:
5873 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5874 ret = 0;
5875 break;
8776e519
HB		 5876 default:
5877 ret = -KVM_ENOSYS;
5878 break;
5879 }
07708c4a 5880out:
a449c7aa
NA		 5881 if (!op_64_bit)
5882 ret = (u32)ret;
5fdbf976 5883 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5884 ++vcpu->stat.hypercalls;
2f333bcb 5885 return r;
8776e519
HB		 5886}
5887EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5888
b6785def 5889static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5890{
d6aa1000 5891 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5892 char instruction[3];
5fdbf976 5893 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5894
8776e519 5895 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5896
9d74191a 5897 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5898}
5899
b6c7a5dc
HB		 5900/*
5901 * Check if userspace requested an interrupt window, and that the
5902 * interrupt window is open.
5903 *
5904 * No need to exit to userspace if we already have an interrupt queued.
5905 */
851ba692 5906static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5907{
8061823a 5908 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5909 vcpu->run->request_interrupt_window &&
5df56646 5910 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5911}
5912
851ba692 5913static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5914{
851ba692
AK		 5915 struct kvm_run *kvm_run = vcpu->run;
5916
91586a3b 5917 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5918 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5919 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5920 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5921 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5922 else
b6c7a5dc 5923 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5924 kvm_arch_interrupt_allowed(vcpu) &&
5925 !kvm_cpu_has_interrupt(vcpu) &&
5926 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5927}
5928
95ba8273
GN		 5929static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5930{
5931 int max_irr, tpr;
5932
5933 if (!kvm_x86_ops->update_cr8_intercept)
5934 return;
5935
88c808fd
AK		 5936 if (!vcpu->arch.apic)
5937 return;
5938
8db3baa2
GN		 5939 if (!vcpu->arch.apic->vapic_addr)
5940 max_irr = kvm_lapic_find_highest_irr(vcpu);
5941 else
5942 max_irr = -1;
95ba8273
GN		 5943
5944 if (max_irr != -1)
5945 max_irr >>= 4;
5946
5947 tpr = kvm_lapic_get_cr8(vcpu);
5948
5949 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5950}
5951
b6b8a145 5952static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5953{
b6b8a145
JK		 5954 int r;
5955
95ba8273 5956 /* try to reinject previous events if any */
b59bb7bd 5957 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5958 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5959 vcpu->arch.exception.has_error_code,
5960 vcpu->arch.exception.error_code);
d6e8c854
NA		 5961
5962 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5963 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5964 X86_EFLAGS_RF);
5965
6bdf0662
NA		 5966 if (vcpu->arch.exception.nr == DB_VECTOR &&
5967 (vcpu->arch.dr7 & DR7_GD)) {
5968 vcpu->arch.dr7 &= ~DR7_GD;
5969 kvm_update_dr7(vcpu);
5970 }
5971
b59bb7bd
GN		 5972 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5973 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5974 vcpu->arch.exception.error_code,
5975 vcpu->arch.exception.reinject);
b6b8a145 5976 return 0;
b59bb7bd
GN		 5977 }
5978
95ba8273
GN		 5979 if (vcpu->arch.nmi_injected) {
5980 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5981 return 0;
95ba8273
GN		 5982 }
5983
5984 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5985 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5986 return 0;
5987 }
5988
5989 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5990 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5991 if (r != 0)
5992 return r;
95ba8273
GN		 5993 }
5994
5995 /* try to inject new event if pending */
5996 if (vcpu->arch.nmi_pending) {
5997 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5998 --vcpu->arch.nmi_pending;
95ba8273
GN		 5999 vcpu->arch.nmi_injected = true;
6000 kvm_x86_ops->set_nmi(vcpu);
6001 }
c7c9c56c 6002 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6003 /*
6004 * Because interrupts can be injected asynchronously, we are
6005 * calling check_nested_events again here to avoid a race condition.
6006 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6007 * proposal and current concerns. Perhaps we should be setting
6008 * KVM_REQ_EVENT only on certain events and not unconditionally?
6009 */
6010 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6011 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6012 if (r != 0)
6013 return r;
6014 }
95ba8273 6015 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6016 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6017 false);
6018 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6019 }
6020 }
b6b8a145 6021 return 0;
95ba8273
GN		 6022}
6023
7460fb4a
AK		 6024static void process_nmi(struct kvm_vcpu *vcpu)
6025{
6026 unsigned limit = 2;
6027
6028 /*
6029 * x86 is limited to one NMI running, and one NMI pending after it.
6030 * If an NMI is already in progress, limit further NMIs to just one.
6031 * Otherwise, allow two (and we'll inject the first one immediately).
6032 */
6033 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6034 limit = 1;
6035
6036 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6037 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6038 kvm_make_request(KVM_REQ_EVENT, vcpu);
6039}
6040
3d81bc7e 6041static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6042{
6043 u64 eoi_exit_bitmap[4];
cf9e65b7 6044 u32 tmr[8];
c7c9c56c 6045
3d81bc7e
YZ		 6046 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6047 return;
c7c9c56c
YZ		 6048
6049 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6050 memset(tmr, 0, 32);
c7c9c56c 6051
cf9e65b7 6052 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6053 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6054 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6055}
6056
a70656b6
RK		 6057static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6058{
6059 ++vcpu->stat.tlb_flush;
6060 kvm_x86_ops->tlb_flush(vcpu);
6061}
6062
4256f43f
TC		 6063void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6064{
c24ae0dc
TC		 6065 struct page *page = NULL;
6066
f439ed27
PB		 6067 if (!irqchip_in_kernel(vcpu->kvm))
6068 return;
6069
4256f43f
TC		 6070 if (!kvm_x86_ops->set_apic_access_page_addr)
6071 return;
6072
c24ae0dc
TC		 6073 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6074 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6075
6076 /*
6077 * Do not pin apic access page in memory, the MMU notifier
6078 * will call us again if it is migrated or swapped out.
6079 */
6080 put_page(page);
4256f43f
TC		 6081}
6082EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6083
fe71557a
TC		 6084void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6085 unsigned long address)
6086{
c24ae0dc
TC		 6087 /*
6088 * The physical address of apic access page is stored in the VMCS.
6089 * Update it when it becomes invalid.
6090 */
6091 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6092 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6093}
6094
9357d939
TY		 6095/*
6096 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6097 * exiting to the userspace. Otherwise, the value will be returned to the
6098 * userspace.
6099 */
851ba692 6100static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6101{
6102 int r;
6a8b1d13 6103 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6104 vcpu->run->request_interrupt_window;
730dca42 6105 bool req_immediate_exit = false;
b6c7a5dc 6106
3e007509 6107 if (vcpu->requests) {
a8eeb04a 6108 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6109 kvm_mmu_unload(vcpu);
a8eeb04a 6110 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6111 __kvm_migrate_timers(vcpu);
d828199e
MT		 6112 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6113 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6114 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6115 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6116 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6117 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6118 if (unlikely(r))
6119 goto out;
6120 }
a8eeb04a 6121 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6122 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6123 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6124 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6125 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6126 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6127 r = 0;
6128 goto out;
6129 }
a8eeb04a 6130 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6131 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6132 r = 0;
6133 goto out;
6134 }
a8eeb04a 6135 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6136 vcpu->fpu_active = 0;
6137 kvm_x86_ops->fpu_deactivate(vcpu);
6138 }
af585b92
GN		 6139 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6140 /* Page is swapped out. Do synthetic halt */
6141 vcpu->arch.apf.halted = true;
6142 r = 1;
6143 goto out;
6144 }
c9aaa895
GC		 6145 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6146 record_steal_time(vcpu);
7460fb4a
AK		 6147 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6148 process_nmi(vcpu);
f5132b01
GN		 6149 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6150 kvm_handle_pmu_event(vcpu);
6151 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6152 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6153 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6154 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6155 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6156 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6157 }
b93463aa 6158
b463a6f7 6159 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6160 kvm_apic_accept_events(vcpu);
6161 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6162 r = 1;
6163 goto out;
6164 }
6165
b6b8a145
JK		 6166 if (inject_pending_event(vcpu, req_int_win) != 0)
6167 req_immediate_exit = true;
b463a6f7 6168 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6169 else if (vcpu->arch.nmi_pending)
c9a7953f 6170 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6171 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6172 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6173
6174 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6175 /*
6176 * Update architecture specific hints for APIC
6177 * virtual interrupt delivery.
6178 */
6179 if (kvm_x86_ops->hwapic_irr_update)
6180 kvm_x86_ops->hwapic_irr_update(vcpu,
6181 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6182 update_cr8_intercept(vcpu);
6183 kvm_lapic_sync_to_vapic(vcpu);
6184 }
6185 }
6186
d8368af8
AK		 6187 r = kvm_mmu_reload(vcpu);
6188 if (unlikely(r)) {
d905c069 6189 goto cancel_injection;
d8368af8
AK		 6190 }
6191
b6c7a5dc
HB		 6192 preempt_disable();
6193
6194 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6195 if (vcpu->fpu_active)
6196 kvm_load_guest_fpu(vcpu);
2acf923e 6197 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6198
6b7e2d09
XG		 6199 vcpu->mode = IN_GUEST_MODE;
6200
01b71917
MT		 6201 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6202
6b7e2d09
XG		 6203 /* We should set ->mode before check ->requests,
6204 * see the comment in make_all_cpus_request.
6205 */
01b71917 6206 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6207
d94e1dc9 6208 local_irq_disable();
32f88400 6209
6b7e2d09 6210 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6211 || need_resched() || signal_pending(current)) {
6b7e2d09 6212 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6213 smp_wmb();
6c142801
AK		 6214 local_irq_enable();
6215 preempt_enable();
01b71917 6216 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6217 r = 1;
d905c069 6218 goto cancel_injection;
6c142801
AK		 6219 }
6220
d6185f20
NHE		 6221 if (req_immediate_exit)
6222 smp_send_reschedule(vcpu->cpu);
6223
b6c7a5dc
HB		 6224 kvm_guest_enter();
6225
42dbaa5a 6226 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6227 set_debugreg(0, 7);
6228 set_debugreg(vcpu->arch.eff_db[0], 0);
6229 set_debugreg(vcpu->arch.eff_db[1], 1);
6230 set_debugreg(vcpu->arch.eff_db[2], 2);
6231 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6232 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6233 }
b6c7a5dc 6234
229456fc 6235 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6236 kvm_x86_ops->run(vcpu);
b6c7a5dc 6237
c77fb5fe
PB		 6238 /*
6239 * Do this here before restoring debug registers on the host. And
6240 * since we do this before handling the vmexit, a DR access vmexit
6241 * can (a) read the correct value of the debug registers, (b) set
6242 * KVM_DEBUGREG_WONT_EXIT again.
6243 */
6244 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6245 int i;
6246
6247 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6248 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6249 for (i = 0; i < KVM_NR_DB_REGS; i++)
6250 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6251 }
6252
24f1e32c
FW		 6253 /*
6254 * If the guest has used debug registers, at least dr7
6255 * will be disabled while returning to the host.
6256 * If we don't have active breakpoints in the host, we don't
6257 * care about the messed up debug address registers. But if
6258 * we have some of them active, restore the old state.
6259 */
59d8eb53 6260 if (hw_breakpoint_active())
24f1e32c 6261 hw_breakpoint_restore();
42dbaa5a 6262
886b470c
MT		 6263 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6264 native_read_tsc());
1d5f066e 6265
6b7e2d09 6266 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6267 smp_wmb();
a547c6db
YZ		 6268
6269 /* Interrupt is enabled by handle_external_intr() */
6270 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6271
6272 ++vcpu->stat.exits;
6273
6274 /*
6275 * We must have an instruction between local_irq_enable() and
6276 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6277 * the interrupt shadow. The stat.exits increment will do nicely.
6278 * But we need to prevent reordering, hence this barrier():
6279 */
6280 barrier();
6281
6282 kvm_guest_exit();
6283
6284 preempt_enable();
6285
f656ce01 6286 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6287
b6c7a5dc
HB		 6288 /*
6289 * Profile KVM exit RIPs:
6290 */
6291 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6292 unsigned long rip = kvm_rip_read(vcpu);
6293 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6294 }
6295
cc578287
ZA		 6296 if (unlikely(vcpu->arch.tsc_always_catchup))
6297 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6298
5cfb1d5a
MT		 6299 if (vcpu->arch.apic_attention)
6300 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6301
851ba692 6302 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6303 return r;
6304
6305cancel_injection:
6306 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6307 if (unlikely(vcpu->arch.apic_attention))
6308 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6309out:
6310 return r;
6311}
b6c7a5dc 6312
09cec754 6313
851ba692 6314static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6315{
6316 int r;
f656ce01 6317 struct kvm *kvm = vcpu->kvm;
d7690175 6318
f656ce01 6319 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6320
6321 r = 1;
6322 while (r > 0) {
af585b92
GN		 6323 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6324 !vcpu->arch.apf.halted)
851ba692 6325 r = vcpu_enter_guest(vcpu);
d7690175 6326 else {
f656ce01 6327 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6328 kvm_vcpu_block(vcpu);
f656ce01 6329 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6330 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6331 kvm_apic_accept_events(vcpu);
09cec754
GN		 6332 switch(vcpu->arch.mp_state) {
6333 case KVM_MP_STATE_HALTED:
6aef266c 6334 vcpu->arch.pv.pv_unhalted = false;
d7690175 6335 vcpu->arch.mp_state =
09cec754
GN		 6336 KVM_MP_STATE_RUNNABLE;
6337 case KVM_MP_STATE_RUNNABLE:
af585b92 6338 vcpu->arch.apf.halted = false;
09cec754 6339 break;
66450a21
JK		 6340 case KVM_MP_STATE_INIT_RECEIVED:
6341 break;
09cec754
GN		 6342 default:
6343 r = -EINTR;
6344 break;
6345 }
6346 }
d7690175
MT		 6347 }
6348
09cec754
GN		 6349 if (r <= 0)
6350 break;
6351
6352 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6353 if (kvm_cpu_has_pending_timer(vcpu))
6354 kvm_inject_pending_timer_irqs(vcpu);
6355
851ba692 6356 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6357 r = -EINTR;
851ba692 6358 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6359 ++vcpu->stat.request_irq_exits;
6360 }
af585b92
GN		 6361
6362 kvm_check_async_pf_completion(vcpu);
6363
09cec754
GN		 6364 if (signal_pending(current)) {
6365 r = -EINTR;
851ba692 6366 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6367 ++vcpu->stat.signal_exits;
6368 }
6369 if (need_resched()) {
f656ce01 6370 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6371 cond_resched();
f656ce01 6372 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6373 }
b6c7a5dc
HB		 6374 }
6375
f656ce01 6376 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6377
6378 return r;
6379}
6380
716d51ab
GN		 6381static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6382{
6383 int r;
6384 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6385 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6386 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6387 if (r != EMULATE_DONE)
6388 return 0;
6389 return 1;
6390}
6391
6392static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6393{
6394 BUG_ON(!vcpu->arch.pio.count);
6395
6396 return complete_emulated_io(vcpu);
6397}
6398
f78146b0
AK		 6399/*
6400 * Implements the following, as a state machine:
6401 *
6402 * read:
6403 * for each fragment
87da7e66
XG		 6404 * for each mmio piece in the fragment
6405 * write gpa, len
6406 * exit
6407 * copy data
f78146b0
AK		 6408 * execute insn
6409 *
6410 * write:
6411 * for each fragment
87da7e66
XG		 6412 * for each mmio piece in the fragment
6413 * write gpa, len
6414 * copy data
6415 * exit
f78146b0 6416 */
716d51ab 6417static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6418{
6419 struct kvm_run *run = vcpu->run;
f78146b0 6420 struct kvm_mmio_fragment *frag;
87da7e66 6421 unsigned len;
5287f194 6422
716d51ab 6423 BUG_ON(!vcpu->mmio_needed);
5287f194 6424
716d51ab 6425 /* Complete previous fragment */
87da7e66
XG		 6426 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6427 len = min(8u, frag->len);
716d51ab 6428 if (!vcpu->mmio_is_write)
87da7e66
XG		 6429 memcpy(frag->data, run->mmio.data, len);
6430
6431 if (frag->len <= 8) {
6432 /* Switch to the next fragment. */
6433 frag++;
6434 vcpu->mmio_cur_fragment++;
6435 } else {
6436 /* Go forward to the next mmio piece. */
6437 frag->data += len;
6438 frag->gpa += len;
6439 frag->len -= len;
6440 }
6441
a08d3b3b 6442 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6443 vcpu->mmio_needed = 0;
0912c977
PB		 6444
6445 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6446 if (vcpu->mmio_is_write)
716d51ab
GN		 6447 return 1;
6448 vcpu->mmio_read_completed = 1;
6449 return complete_emulated_io(vcpu);
6450 }
87da7e66 6451
716d51ab
GN		 6452 run->exit_reason = KVM_EXIT_MMIO;
6453 run->mmio.phys_addr = frag->gpa;
6454 if (vcpu->mmio_is_write)
87da7e66
XG		 6455 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6456 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6457 run->mmio.is_write = vcpu->mmio_is_write;
6458 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6459 return 0;
5287f194
AK		 6460}
6461
716d51ab 6462
b6c7a5dc
HB		 6463int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6464{
6465 int r;
6466 sigset_t sigsaved;
6467
e5c30142
AK		 6468 if (!tsk_used_math(current) && init_fpu(current))
6469 return -ENOMEM;
6470
ac9f6dc0
AK		 6471 if (vcpu->sigset_active)
6472 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6473
a4535290 6474 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6475 kvm_vcpu_block(vcpu);
66450a21 6476 kvm_apic_accept_events(vcpu);
d7690175 6477 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6478 r = -EAGAIN;
6479 goto out;
b6c7a5dc
HB		 6480 }
6481
b6c7a5dc 6482 /* re-sync apic's tpr */
eea1cff9
AP		 6483 if (!irqchip_in_kernel(vcpu->kvm)) {
6484 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6485 r = -EINVAL;
6486 goto out;
6487 }
6488 }
b6c7a5dc 6489
716d51ab
GN		 6490 if (unlikely(vcpu->arch.complete_userspace_io)) {
6491 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6492 vcpu->arch.complete_userspace_io = NULL;
6493 r = cui(vcpu);
6494 if (r <= 0)
6495 goto out;
6496 } else
6497 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6498
851ba692 6499 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6500
6501out:
f1d86e46 6502 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6503 if (vcpu->sigset_active)
6504 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6505
b6c7a5dc
HB		 6506 return r;
6507}
6508
6509int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6510{
7ae441ea
GN		 6511 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6512 /*
6513 * We are here if userspace calls get_regs() in the middle of
6514 * instruction emulation. Registers state needs to be copied
4a969980 6515 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6516 * that usually, but some bad designed PV devices (vmware
6517 * backdoor interface) need this to work
6518 */
dd856efa 6519 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6520 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6521 }
5fdbf976
MT		 6522 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6523 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6524 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6525 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6526 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6527 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6528 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6529 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6530#ifdef CONFIG_X86_64
5fdbf976
MT		 6531 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6532 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6533 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6534 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6535 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6536 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6537 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6538 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6539#endif
6540
5fdbf976 6541 regs->rip = kvm_rip_read(vcpu);
91586a3b 6542 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6543
b6c7a5dc
HB		 6544 return 0;
6545}
6546
6547int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6548{
7ae441ea
GN		 6549 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6550 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6551
5fdbf976
MT		 6552 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6553 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6554 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6555 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6556 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6557 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6558 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6559 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6560#ifdef CONFIG_X86_64
5fdbf976
MT		 6561 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6562 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6563 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6564 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6565 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6566 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6567 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6568 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6569#endif
6570
5fdbf976 6571 kvm_rip_write(vcpu, regs->rip);
91586a3b 6572 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6573
b4f14abd
JK		 6574 vcpu->arch.exception.pending = false;
6575
3842d135
AK		 6576 kvm_make_request(KVM_REQ_EVENT, vcpu);
6577
b6c7a5dc
HB		 6578 return 0;
6579}
6580
b6c7a5dc
HB		 6581void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6582{
6583 struct kvm_segment cs;
6584
3e6e0aab 6585 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6586 *db = cs.db;
6587 *l = cs.l;
6588}
6589EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6590
6591int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6592 struct kvm_sregs *sregs)
6593{
89a27f4d 6594 struct desc_ptr dt;
b6c7a5dc 6595
3e6e0aab
GT		 6596 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6597 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6598 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6599 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6600 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6601 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6602
3e6e0aab
GT		 6603 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6604 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6605
6606 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6607 sregs->idt.limit = dt.size;
6608 sregs->idt.base = dt.address;
b6c7a5dc 6609 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6610 sregs->gdt.limit = dt.size;
6611 sregs->gdt.base = dt.address;
b6c7a5dc 6612
4d4ec087 6613 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6614 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6615 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6616 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6617 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6618 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6619 sregs->apic_base = kvm_get_apic_base(vcpu);
6620
923c61bb 6621 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6622
36752c9b 6623 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6624 set_bit(vcpu->arch.interrupt.nr,
6625 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6626
b6c7a5dc
HB		 6627 return 0;
6628}
6629
62d9f0db
MT		 6630int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6631 struct kvm_mp_state *mp_state)
6632{
66450a21 6633 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6634 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6635 vcpu->arch.pv.pv_unhalted)
6636 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6637 else
6638 mp_state->mp_state = vcpu->arch.mp_state;
6639
62d9f0db
MT		 6640 return 0;
6641}
6642
6643int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6644 struct kvm_mp_state *mp_state)
6645{
66450a21
JK		 6646 if (!kvm_vcpu_has_lapic(vcpu) &&
6647 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6648 return -EINVAL;
6649
6650 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6651 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6652 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6653 } else
6654 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6655 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6656 return 0;
6657}
6658
7f3d35fd
KW		 6659int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6660 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6661{
9d74191a 6662 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6663 int ret;
e01c2426 6664
8ec4722d 6665 init_emulate_ctxt(vcpu);
c697518a 6666
7f3d35fd 6667 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6668 has_error_code, error_code);
c697518a 6669
c697518a 6670 if (ret)
19d04437 6671 return EMULATE_FAIL;
37817f29 6672
9d74191a
TY		 6673 kvm_rip_write(vcpu, ctxt->eip);
6674 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6675 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6676 return EMULATE_DONE;
37817f29
IE		 6677}
6678EXPORT_SYMBOL_GPL(kvm_task_switch);
6679
b6c7a5dc
HB		 6680int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6681 struct kvm_sregs *sregs)
6682{
58cb628d 6683 struct msr_data apic_base_msr;
b6c7a5dc 6684 int mmu_reset_needed = 0;
63f42e02 6685 int pending_vec, max_bits, idx;
89a27f4d 6686 struct desc_ptr dt;
b6c7a5dc 6687
6d1068b3
PM		 6688 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6689 return -EINVAL;
6690
89a27f4d
GN		 6691 dt.size = sregs->idt.limit;
6692 dt.address = sregs->idt.base;
b6c7a5dc 6693 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6694 dt.size = sregs->gdt.limit;
6695 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6696 kvm_x86_ops->set_gdt(vcpu, &dt);
6697
ad312c7c 6698 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6699 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6700 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6701 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6702
2d3ad1f4 6703 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6704
f6801dff 6705 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6706 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6707 apic_base_msr.data = sregs->apic_base;
6708 apic_base_msr.host_initiated = true;
6709 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6710
4d4ec087 6711 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6712 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6713 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6714
fc78f519 6715 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6716 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6717 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6718 kvm_update_cpuid(vcpu);
63f42e02
XG		 6719
6720 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6721 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6722 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6723 mmu_reset_needed = 1;
6724 }
63f42e02 6725 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6726
6727 if (mmu_reset_needed)
6728 kvm_mmu_reset_context(vcpu);
6729
a50abc3b 6730 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6731 pending_vec = find_first_bit(
6732 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6733 if (pending_vec < max_bits) {
66fd3f7f 6734 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6735 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6736 }
6737
3e6e0aab
GT		 6738 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6739 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6740 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6741 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6742 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6743 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6744
3e6e0aab
GT		 6745 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6746 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6747
5f0269f5
ME		 6748 update_cr8_intercept(vcpu);
6749
9c3e4aab 6750 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6751 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6752 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6753 !is_protmode(vcpu))
9c3e4aab
MT		 6754 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6755
3842d135
AK		 6756 kvm_make_request(KVM_REQ_EVENT, vcpu);
6757
b6c7a5dc
HB		 6758 return 0;
6759}
6760
d0bfb940
JK		 6761int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6762 struct kvm_guest_debug *dbg)
b6c7a5dc 6763{
355be0b9 6764 unsigned long rflags;
ae675ef0 6765 int i, r;
b6c7a5dc 6766
4f926bf2
JK		 6767 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6768 r = -EBUSY;
6769 if (vcpu->arch.exception.pending)
2122ff5e 6770 goto out;
4f926bf2
JK		 6771 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6772 kvm_queue_exception(vcpu, DB_VECTOR);
6773 else
6774 kvm_queue_exception(vcpu, BP_VECTOR);
6775 }
6776
91586a3b
JK		 6777 /*
6778 * Read rflags as long as potentially injected trace flags are still
6779 * filtered out.
6780 */
6781 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6782
6783 vcpu->guest_debug = dbg->control;
6784 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6785 vcpu->guest_debug = 0;
6786
6787 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6788 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6789 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6790 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6791 } else {
6792 for (i = 0; i < KVM_NR_DB_REGS; i++)
6793 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6794 }
c8639010 6795 kvm_update_dr7(vcpu);
ae675ef0 6796
f92653ee
JK		 6797 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6798 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6799 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6800
91586a3b
JK		 6801 /*
6802 * Trigger an rflags update that will inject or remove the trace
6803 * flags.
6804 */
6805 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6806
c8639010 6807 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6808
4f926bf2 6809 r = 0;
d0bfb940 6810
2122ff5e 6811out:
b6c7a5dc
HB		 6812
6813 return r;
6814}
6815
8b006791
ZX		 6816/*
6817 * Translate a guest virtual address to a guest physical address.
6818 */
6819int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6820 struct kvm_translation *tr)
6821{
6822 unsigned long vaddr = tr->linear_address;
6823 gpa_t gpa;
f656ce01 6824 int idx;
8b006791 6825
f656ce01 6826 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6827 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6828 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6829 tr->physical_address = gpa;
6830 tr->valid = gpa != UNMAPPED_GVA;
6831 tr->writeable = 1;
6832 tr->usermode = 0;
8b006791
ZX		 6833
6834 return 0;
6835}
6836
d0752060
HB		 6837int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6838{
98918833
SY		 6839 struct i387_fxsave_struct *fxsave =
6840 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6841
d0752060
HB		 6842 memcpy(fpu->fpr, fxsave->st_space, 128);
6843 fpu->fcw = fxsave->cwd;
6844 fpu->fsw = fxsave->swd;
6845 fpu->ftwx = fxsave->twd;
6846 fpu->last_opcode = fxsave->fop;
6847 fpu->last_ip = fxsave->rip;
6848 fpu->last_dp = fxsave->rdp;
6849 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6850
d0752060
HB		 6851 return 0;
6852}
6853
6854int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6855{
98918833
SY		 6856 struct i387_fxsave_struct *fxsave =
6857 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6858
d0752060
HB		 6859 memcpy(fxsave->st_space, fpu->fpr, 128);
6860 fxsave->cwd = fpu->fcw;
6861 fxsave->swd = fpu->fsw;
6862 fxsave->twd = fpu->ftwx;
6863 fxsave->fop = fpu->last_opcode;
6864 fxsave->rip = fpu->last_ip;
6865 fxsave->rdp = fpu->last_dp;
6866 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6867
d0752060
HB		 6868 return 0;
6869}
6870
10ab25cd 6871int fx_init(struct kvm_vcpu *vcpu)
d0752060 6872{
10ab25cd
JK		 6873 int err;
6874
6875 err = fpu_alloc(&vcpu->arch.guest_fpu);
6876 if (err)
6877 return err;
6878
98918833 6879 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6880
2acf923e
DC		 6881 /*
6882 * Ensure guest xcr0 is valid for loading
6883 */
6884 vcpu->arch.xcr0 = XSTATE_FP;
6885
ad312c7c 6886 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6887
6888 return 0;
d0752060
HB		 6889}
6890EXPORT_SYMBOL_GPL(fx_init);
6891
98918833
SY		 6892static void fx_free(struct kvm_vcpu *vcpu)
6893{
6894 fpu_free(&vcpu->arch.guest_fpu);
6895}
6896
d0752060
HB		 6897void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6898{
2608d7a1 6899 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6900 return;
6901
2acf923e
DC		 6902 /*
6903 * Restore all possible states in the guest,
6904 * and assume host would use all available bits.
6905 * Guest xcr0 would be loaded later.
6906 */
6907 kvm_put_guest_xcr0(vcpu);
d0752060 6908 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6909 __kernel_fpu_begin();
98918833 6910 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6911 trace_kvm_fpu(1);
d0752060 6912}
d0752060
HB		 6913
6914void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6915{
2acf923e
DC		 6916 kvm_put_guest_xcr0(vcpu);
6917
d0752060
HB		 6918 if (!vcpu->guest_fpu_loaded)
6919 return;
6920
6921 vcpu->guest_fpu_loaded = 0;
98918833 6922 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6923 __kernel_fpu_end();
f096ed85 6924 ++vcpu->stat.fpu_reload;
a8eeb04a 6925 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6926 trace_kvm_fpu(0);
d0752060 6927}
e9b11c17
ZX		 6928
6929void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6930{
12f9a48f 6931 kvmclock_reset(vcpu);
7f1ea208 6932
f5f48ee1 6933 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6934 fx_free(vcpu);
e9b11c17
ZX		 6935 kvm_x86_ops->vcpu_free(vcpu);
6936}
6937
6938struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6939 unsigned int id)
6940{
6755bae8
ZA		 6941 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6942 printk_once(KERN_WARNING
6943 "kvm: SMP vm created on host with unstable TSC; "
6944 "guest TSC will not be reliable\n");
26e5215f
AK		 6945 return kvm_x86_ops->vcpu_create(kvm, id);
6946}
e9b11c17 6947
26e5215f
AK		 6948int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6949{
6950 int r;
e9b11c17 6951
0bed3b56 6952 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6953 r = vcpu_load(vcpu);
6954 if (r)
6955 return r;
57f252f2 6956 kvm_vcpu_reset(vcpu);
8a3c1a33 6957 kvm_mmu_setup(vcpu);
e9b11c17 6958 vcpu_put(vcpu);
e9b11c17 6959
26e5215f 6960 return r;
e9b11c17
ZX		 6961}
6962
42897d86
MT		 6963int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6964{
6965 int r;
8fe8ab46 6966 struct msr_data msr;
332967a3 6967 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6968
6969 r = vcpu_load(vcpu);
6970 if (r)
6971 return r;
8fe8ab46
WA		 6972 msr.data = 0x0;
6973 msr.index = MSR_IA32_TSC;
6974 msr.host_initiated = true;
6975 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6976 vcpu_put(vcpu);
6977
332967a3
AJ		 6978 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6979 KVMCLOCK_SYNC_PERIOD);
6980
42897d86
MT		 6981 return r;
6982}
6983
d40ccc62 6984void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6985{
9fc77441 6986 int r;
344d9588
GN		 6987 vcpu->arch.apf.msr_val = 0;
6988
9fc77441
MT		 6989 r = vcpu_load(vcpu);
6990 BUG_ON(r);
e9b11c17
ZX		 6991 kvm_mmu_unload(vcpu);
6992 vcpu_put(vcpu);
6993
98918833 6994 fx_free(vcpu);
e9b11c17
ZX		 6995 kvm_x86_ops->vcpu_free(vcpu);
6996}
6997
66450a21 6998void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6999{
7460fb4a
AK		 7000 atomic_set(&vcpu->arch.nmi_queued, 0);
7001 vcpu->arch.nmi_pending = 0;
448fa4a9 7002 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7003 kvm_clear_interrupt_queue(vcpu);
7004 kvm_clear_exception_queue(vcpu);
448fa4a9 7005
42dbaa5a 7006 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7007 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7008 kvm_update_dr6(vcpu);
42dbaa5a 7009 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7010 kvm_update_dr7(vcpu);
42dbaa5a 7011
3842d135 7012 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7013 vcpu->arch.apf.msr_val = 0;
c9aaa895 7014 vcpu->arch.st.msr_val = 0;
3842d135 7015
12f9a48f
GC		 7016 kvmclock_reset(vcpu);
7017
af585b92
GN		 7018 kvm_clear_async_pf_completion_queue(vcpu);
7019 kvm_async_pf_hash_reset(vcpu);
7020 vcpu->arch.apf.halted = false;
3842d135 7021
f5132b01
GN		 7022 kvm_pmu_reset(vcpu);
7023
66f7b72e
JS		 7024 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7025 vcpu->arch.regs_avail = ~0;
7026 vcpu->arch.regs_dirty = ~0;
7027
57f252f2 7028 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7029}
7030
66450a21
JK		 7031void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
7032{
7033 struct kvm_segment cs;
7034
7035 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7036 cs.selector = vector << 8;
7037 cs.base = vector << 12;
7038 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7039 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7040}
7041
13a34e06 7042int kvm_arch_hardware_enable(void)
e9b11c17 7043{
ca84d1a2
ZA		 7044 struct kvm *kvm;
7045 struct kvm_vcpu *vcpu;
7046 int i;
0dd6a6ed
ZA		 7047 int ret;
7048 u64 local_tsc;
7049 u64 max_tsc = 0;
7050 bool stable, backwards_tsc = false;
18863bdd
AK		 7051
7052 kvm_shared_msr_cpu_online();
13a34e06 7053 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7054 if (ret != 0)
7055 return ret;
7056
7057 local_tsc = native_read_tsc();
7058 stable = !check_tsc_unstable();
7059 list_for_each_entry(kvm, &vm_list, vm_list) {
7060 kvm_for_each_vcpu(i, vcpu, kvm) {
7061 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7063 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7064 backwards_tsc = true;
7065 if (vcpu->arch.last_host_tsc > max_tsc)
7066 max_tsc = vcpu->arch.last_host_tsc;
7067 }
7068 }
7069 }
7070
7071 /*
7072 * Sometimes, even reliable TSCs go backwards. This happens on
7073 * platforms that reset TSC during suspend or hibernate actions, but
7074 * maintain synchronization. We must compensate. Fortunately, we can
7075 * detect that condition here, which happens early in CPU bringup,
7076 * before any KVM threads can be running. Unfortunately, we can't
7077 * bring the TSCs fully up to date with real time, as we aren't yet far
7078 * enough into CPU bringup that we know how much real time has actually
7079 * elapsed; our helper function, get_kernel_ns() will be using boot
7080 * variables that haven't been updated yet.
7081 *
7082 * So we simply find the maximum observed TSC above, then record the
7083 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7084 * the adjustment will be applied. Note that we accumulate
7085 * adjustments, in case multiple suspend cycles happen before some VCPU
7086 * gets a chance to run again. In the event that no KVM threads get a
7087 * chance to run, we will miss the entire elapsed period, as we'll have
7088 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7089 * loose cycle time. This isn't too big a deal, since the loss will be
7090 * uniform across all VCPUs (not to mention the scenario is extremely
7091 * unlikely). It is possible that a second hibernate recovery happens
7092 * much faster than a first, causing the observed TSC here to be
7093 * smaller; this would require additional padding adjustment, which is
7094 * why we set last_host_tsc to the local tsc observed here.
7095 *
7096 * N.B. - this code below runs only on platforms with reliable TSC,
7097 * as that is the only way backwards_tsc is set above. Also note
7098 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7099 * have the same delta_cyc adjustment applied if backwards_tsc
7100 * is detected. Note further, this adjustment is only done once,
7101 * as we reset last_host_tsc on all VCPUs to stop this from being
7102 * called multiple times (one for each physical CPU bringup).
7103 *
4a969980 7104 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7105 * will be compensated by the logic in vcpu_load, which sets the TSC to
7106 * catchup mode. This will catchup all VCPUs to real time, but cannot
7107 * guarantee that they stay in perfect synchronization.
7108 */
7109 if (backwards_tsc) {
7110 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7111 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7112 list_for_each_entry(kvm, &vm_list, vm_list) {
7113 kvm_for_each_vcpu(i, vcpu, kvm) {
7114 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7115 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7116 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7117 }
7118
7119 /*
7120 * We have to disable TSC offset matching.. if you were
7121 * booting a VM while issuing an S4 host suspend....
7122 * you may have some problem. Solving this issue is
7123 * left as an exercise to the reader.
7124 */
7125 kvm->arch.last_tsc_nsec = 0;
7126 kvm->arch.last_tsc_write = 0;
7127 }
7128
7129 }
7130 return 0;
e9b11c17
ZX		 7131}
7132
13a34e06 7133void kvm_arch_hardware_disable(void)
e9b11c17 7134{
13a34e06
RK		 7135 kvm_x86_ops->hardware_disable();
7136 drop_user_return_notifiers();
e9b11c17
ZX		 7137}
7138
7139int kvm_arch_hardware_setup(void)
7140{
7141 return kvm_x86_ops->hardware_setup();
7142}
7143
7144void kvm_arch_hardware_unsetup(void)
7145{
7146 kvm_x86_ops->hardware_unsetup();
7147}
7148
7149void kvm_arch_check_processor_compat(void *rtn)
7150{
7151 kvm_x86_ops->check_processor_compatibility(rtn);
7152}
7153
3e515705
AK		 7154bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7155{
7156 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7157}
7158
54e9818f
GN		 7159struct static_key kvm_no_apic_vcpu __read_mostly;
7160
e9b11c17
ZX		 7161int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7162{
7163 struct page *page;
7164 struct kvm *kvm;
7165 int r;
7166
7167 BUG_ON(vcpu->kvm == NULL);
7168 kvm = vcpu->kvm;
7169
6aef266c 7170 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7171 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7172 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7173 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7174 else
a4535290 7175 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7176
7177 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7178 if (!page) {
7179 r = -ENOMEM;
7180 goto fail;
7181 }
ad312c7c 7182 vcpu->arch.pio_data = page_address(page);
e9b11c17 7183
cc578287 7184 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7185
e9b11c17
ZX		 7186 r = kvm_mmu_create(vcpu);
7187 if (r < 0)
7188 goto fail_free_pio_data;
7189
7190 if (irqchip_in_kernel(kvm)) {
7191 r = kvm_create_lapic(vcpu);
7192 if (r < 0)
7193 goto fail_mmu_destroy;
54e9818f
GN		 7194 } else
7195 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7196
890ca9ae
HY		 7197 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7198 GFP_KERNEL);
7199 if (!vcpu->arch.mce_banks) {
7200 r = -ENOMEM;
443c39bc 7201 goto fail_free_lapic;
890ca9ae
HY		 7202 }
7203 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7204
f1797359
WY		 7205 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7206 r = -ENOMEM;
f5f48ee1 7207 goto fail_free_mce_banks;
f1797359 7208 }
f5f48ee1 7209
66f7b72e
JS		 7210 r = fx_init(vcpu);
7211 if (r)
7212 goto fail_free_wbinvd_dirty_mask;
7213
ba904635 7214 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7215 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7216
7217 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7218 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7219
af585b92 7220 kvm_async_pf_hash_reset(vcpu);
f5132b01 7221 kvm_pmu_init(vcpu);
af585b92 7222
e9b11c17 7223 return 0;
66f7b72e
JS		 7224fail_free_wbinvd_dirty_mask:
7225 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7226fail_free_mce_banks:
7227 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7228fail_free_lapic:
7229 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7230fail_mmu_destroy:
7231 kvm_mmu_destroy(vcpu);
7232fail_free_pio_data:
ad312c7c 7233 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7234fail:
7235 return r;
7236}
7237
7238void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7239{
f656ce01
MT		 7240 int idx;
7241
f5132b01 7242 kvm_pmu_destroy(vcpu);
36cb93fd 7243 kfree(vcpu->arch.mce_banks);
e9b11c17 7244 kvm_free_lapic(vcpu);
f656ce01 7245 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7246 kvm_mmu_destroy(vcpu);
f656ce01 7247 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7248 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7249 if (!irqchip_in_kernel(vcpu->kvm))
7250 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7251}
d19a9cd2 7252
e790d9ef
RK		 7253void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7254{
ae97a3b8 7255 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7256}
7257
e08b9637 7258int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7259{
e08b9637
CO		 7260 if (type)
7261 return -EINVAL;
7262
f05e70ac 7263 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7264 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7265 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7266 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7267
5550af4d
SY		 7268 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7269 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7270 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7271 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7272 &kvm->arch.irq_sources_bitmap);
5550af4d 7273
038f8c11 7274 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7275 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7276 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7277
7278 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7279
7e44e449 7280 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7281 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7282
d89f5eff 7283 return 0;
d19a9cd2
ZX		 7284}
7285
7286static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7287{
9fc77441
MT		 7288 int r;
7289 r = vcpu_load(vcpu);
7290 BUG_ON(r);
d19a9cd2
ZX		 7291 kvm_mmu_unload(vcpu);
7292 vcpu_put(vcpu);
7293}
7294
7295static void kvm_free_vcpus(struct kvm *kvm)
7296{
7297 unsigned int i;
988a2cae 7298 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7299
7300 /*
7301 * Unpin any mmu pages first.
7302 */
af585b92
GN		 7303 kvm_for_each_vcpu(i, vcpu, kvm) {
7304 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7305 kvm_unload_vcpu_mmu(vcpu);
af585b92 7306 }
988a2cae
GN		 7307 kvm_for_each_vcpu(i, vcpu, kvm)
7308 kvm_arch_vcpu_free(vcpu);
7309
7310 mutex_lock(&kvm->lock);
7311 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7312 kvm->vcpus[i] = NULL;
d19a9cd2 7313
988a2cae
GN		 7314 atomic_set(&kvm->online_vcpus, 0);
7315 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7316}
7317
ad8ba2cd
SY		 7318void kvm_arch_sync_events(struct kvm *kvm)
7319{
332967a3 7320 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7321 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7322 kvm_free_all_assigned_devices(kvm);
aea924f6 7323 kvm_free_pit(kvm);
ad8ba2cd
SY		 7324}
7325
d19a9cd2
ZX		 7326void kvm_arch_destroy_vm(struct kvm *kvm)
7327{
27469d29
AH		 7328 if (current->mm == kvm->mm) {
7329 /*
7330 * Free memory regions allocated on behalf of userspace,
7331 * unless the the memory map has changed due to process exit
7332 * or fd copying.
7333 */
7334 struct kvm_userspace_memory_region mem;
7335 memset(&mem, 0, sizeof(mem));
7336 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7337 kvm_set_memory_region(kvm, &mem);
7338
7339 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7340 kvm_set_memory_region(kvm, &mem);
7341
7342 mem.slot = TSS_PRIVATE_MEMSLOT;
7343 kvm_set_memory_region(kvm, &mem);
7344 }
6eb55818 7345 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7346 kfree(kvm->arch.vpic);
7347 kfree(kvm->arch.vioapic);
d19a9cd2 7348 kvm_free_vcpus(kvm);
1e08ec4a 7349 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7350}
0de10343 7351
5587027c 7352void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7353 struct kvm_memory_slot *dont)
7354{
7355 int i;
7356
d89cc617
TY		 7357 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7358 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7359 kvm_kvfree(free->arch.rmap[i]);
7360 free->arch.rmap[i] = NULL;
77d11309 7361 }
d89cc617
TY		 7362 if (i == 0)
7363 continue;
7364
7365 if (!dont || free->arch.lpage_info[i - 1] !=
7366 dont->arch.lpage_info[i - 1]) {
7367 kvm_kvfree(free->arch.lpage_info[i - 1]);
7368 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7369 }
7370 }
7371}
7372
5587027c
AK		 7373int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7374 unsigned long npages)
db3fe4eb
TY		 7375{
7376 int i;
7377
d89cc617 7378 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7379 unsigned long ugfn;
7380 int lpages;
d89cc617 7381 int level = i + 1;
db3fe4eb
TY		 7382
7383 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7384 slot->base_gfn, level) + 1;
7385
d89cc617
TY		 7386 slot->arch.rmap[i] =
7387 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7388 if (!slot->arch.rmap[i])
77d11309 7389 goto out_free;
d89cc617
TY		 7390 if (i == 0)
7391 continue;
77d11309 7392
d89cc617
TY		 7393 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7394 sizeof(*slot->arch.lpage_info[i - 1]));
7395 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7396 goto out_free;
7397
7398 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7399 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7400 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7401 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7402 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7403 /*
7404 * If the gfn and userspace address are not aligned wrt each
7405 * other, or if explicitly asked to, disable large page
7406 * support for this slot
7407 */
7408 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7409 !kvm_largepages_enabled()) {
7410 unsigned long j;
7411
7412 for (j = 0; j < lpages; ++j)
d89cc617 7413 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7414 }
7415 }
7416
7417 return 0;
7418
7419out_free:
d89cc617
TY		 7420 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7421 kvm_kvfree(slot->arch.rmap[i]);
7422 slot->arch.rmap[i] = NULL;
7423 if (i == 0)
7424 continue;
7425
7426 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7427 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7428 }
7429 return -ENOMEM;
7430}
7431
e59dbe09
TY		 7432void kvm_arch_memslots_updated(struct kvm *kvm)
7433{
e6dff7d1
TY		 7434 /*
7435 * memslots->generation has been incremented.
7436 * mmio generation may have reached its maximum value.
7437 */
7438 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7439}
7440
f7784b8e
MT		 7441int kvm_arch_prepare_memory_region(struct kvm *kvm,
7442 struct kvm_memory_slot *memslot,
f7784b8e 7443 struct kvm_userspace_memory_region *mem,
7b6195a9 7444 enum kvm_mr_change change)
0de10343 7445{
7a905b14
TY		 7446 /*
7447 * Only private memory slots need to be mapped here since
7448 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7449 */
7b6195a9 7450 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7451 unsigned long userspace_addr;
604b38ac 7452
7a905b14
TY		 7453 /*
7454 * MAP_SHARED to prevent internal slot pages from being moved
7455 * by fork()/COW.
7456 */
7b6195a9 7457 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7458 PROT_READ | PROT_WRITE,
7459 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7460
7a905b14
TY		 7461 if (IS_ERR((void *)userspace_addr))
7462 return PTR_ERR((void *)userspace_addr);
604b38ac 7463
7a905b14 7464 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7465 }
7466
f7784b8e
MT		 7467 return 0;
7468}
7469
7470void kvm_arch_commit_memory_region(struct kvm *kvm,
7471 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7472 const struct kvm_memory_slot *old,
7473 enum kvm_mr_change change)
f7784b8e
MT		 7474{
7475
8482644a 7476 int nr_mmu_pages = 0;
f7784b8e 7477
8482644a 7478 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7479 int ret;
7480
8482644a
TY		 7481 ret = vm_munmap(old->userspace_addr,
7482 old->npages * PAGE_SIZE);
f7784b8e
MT		 7483 if (ret < 0)
7484 printk(KERN_WARNING
7485 "kvm_vm_ioctl_set_memory_region: "
7486 "failed to munmap memory\n");
7487 }
7488
48c0e4e9
XG		 7489 if (!kvm->arch.n_requested_mmu_pages)
7490 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7491
48c0e4e9 7492 if (nr_mmu_pages)
0de10343 7493 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7494 /*
7495 * Write protect all pages for dirty logging.
c126d94f
XG		 7496 *
7497 * All the sptes including the large sptes which point to this
7498 * slot are set to readonly. We can not create any new large
7499 * spte on this slot until the end of the logging.
7500 *
7501 * See the comments in fast_page_fault().
c972f3b1 7502 */
8482644a 7503 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7504 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7505}
1d737c8a 7506
2df72e9b 7507void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7508{
6ca18b69 7509 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7510}
7511
2df72e9b
MT		 7512void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7513 struct kvm_memory_slot *slot)
7514{
6ca18b69 7515 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7516}
7517
1d737c8a
ZX		 7518int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7519{
b6b8a145
JK		 7520 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7521 kvm_x86_ops->check_nested_events(vcpu, false);
7522
af585b92
GN		 7523 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7524 !vcpu->arch.apf.halted)
7525 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7526 || kvm_apic_has_events(vcpu)
6aef266c 7527 || vcpu->arch.pv.pv_unhalted
7460fb4a 7528 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7529 (kvm_arch_interrupt_allowed(vcpu) &&
7530 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7531}
5736199a 7532
b6d33834 7533int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7534{
b6d33834 7535 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7536}
78646121
GN		 7537
7538int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7539{
7540 return kvm_x86_ops->interrupt_allowed(vcpu);
7541}
229456fc 7542
82b32774 7543unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7544{
82b32774
NA		 7545 if (is_64_bit_mode(vcpu))
7546 return kvm_rip_read(vcpu);
7547 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7548 kvm_rip_read(vcpu));
7549}
7550EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7551
82b32774
NA		 7552bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7553{
7554 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7555}
7556EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7557
94fe45da
JK		 7558unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7559{
7560 unsigned long rflags;
7561
7562 rflags = kvm_x86_ops->get_rflags(vcpu);
7563 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7564 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7565 return rflags;
7566}
7567EXPORT_SYMBOL_GPL(kvm_get_rflags);
7568
6addfc42 7569static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7570{
7571 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7572 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7573 rflags |= X86_EFLAGS_TF;
94fe45da 7574 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7575}
7576
7577void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7578{
7579 __kvm_set_rflags(vcpu, rflags);
3842d135 7580 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7581}
7582EXPORT_SYMBOL_GPL(kvm_set_rflags);
7583
56028d08
GN		 7584void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7585{
7586 int r;
7587
fb67e14f 7588 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7589 work->wakeup_all)
56028d08
GN		 7590 return;
7591
7592 r = kvm_mmu_reload(vcpu);
7593 if (unlikely(r))
7594 return;
7595
fb67e14f
XG		 7596 if (!vcpu->arch.mmu.direct_map &&
7597 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7598 return;
7599
56028d08
GN		 7600 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7601}
7602
af585b92
GN		 7603static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7604{
7605 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7606}
7607
7608static inline u32 kvm_async_pf_next_probe(u32 key)
7609{
7610 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7611}
7612
7613static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7614{
7615 u32 key = kvm_async_pf_hash_fn(gfn);
7616
7617 while (vcpu->arch.apf.gfns[key] != ~0)
7618 key = kvm_async_pf_next_probe(key);
7619
7620 vcpu->arch.apf.gfns[key] = gfn;
7621}
7622
7623static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7624{
7625 int i;
7626 u32 key = kvm_async_pf_hash_fn(gfn);
7627
7628 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7629 (vcpu->arch.apf.gfns[key] != gfn &&
7630 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7631 key = kvm_async_pf_next_probe(key);
7632
7633 return key;
7634}
7635
7636bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7637{
7638 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7639}
7640
7641static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7642{
7643 u32 i, j, k;
7644
7645 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7646 while (true) {
7647 vcpu->arch.apf.gfns[i] = ~0;
7648 do {
7649 j = kvm_async_pf_next_probe(j);
7650 if (vcpu->arch.apf.gfns[j] == ~0)
7651 return;
7652 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7653 /*
7654 * k lies cyclically in ]i,j]
7655 * | i.k.j |
7656 * |....j i.k.| or |.k..j i...|
7657 */
7658 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7659 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7660 i = j;
7661 }
7662}
7663
7c90705b
GN		 7664static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7665{
7666
7667 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7668 sizeof(val));
7669}
7670
af585b92
GN		 7671void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7672 struct kvm_async_pf *work)
7673{
6389ee94
AK		 7674 struct x86_exception fault;
7675
7c90705b 7676 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7677 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7678
7679 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7680 (vcpu->arch.apf.send_user_only &&
7681 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7682 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7683 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7684 fault.vector = PF_VECTOR;
7685 fault.error_code_valid = true;
7686 fault.error_code = 0;
7687 fault.nested_page_fault = false;
7688 fault.address = work->arch.token;
7689 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7690 }
af585b92
GN		 7691}
7692
7693void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7694 struct kvm_async_pf *work)
7695{
6389ee94
AK		 7696 struct x86_exception fault;
7697
7c90705b 7698 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7699 if (work->wakeup_all)
7c90705b
GN		 7700 work->arch.token = ~0; /* broadcast wakeup */
7701 else
7702 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7703
7704 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7705 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7706 fault.vector = PF_VECTOR;
7707 fault.error_code_valid = true;
7708 fault.error_code = 0;
7709 fault.nested_page_fault = false;
7710 fault.address = work->arch.token;
7711 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7712 }
e6d53e3b 7713 vcpu->arch.apf.halted = false;
a4fa1635 7714 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7715}
7716
7717bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7718{
7719 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7720 return true;
7721 else
7722 return !kvm_event_needs_reinjection(vcpu) &&
7723 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7724}
7725
e0f0bbc5
AW		 7726void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7727{
7728 atomic_inc(&kvm->arch.noncoherent_dma_count);
7729}
7730EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7731
7732void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7733{
7734 atomic_dec(&kvm->arch.noncoherent_dma_count);
7735}
7736EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7737
7738bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7739{
7740 return atomic_read(&kvm->arch.noncoherent_dma_count);
7741}
7742EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7743
229456fc
MT		 7744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7745EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7746EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7747EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7748EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7749EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7750EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7751EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7752EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7753EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7754EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7755EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7756EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7757EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux kernel - Deliverables
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