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x86: kvmclock: set scheduler clock stable
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
630994b3
MT		 102static bool __read_mostly kvmclock_periodic_sync = true;
103module_param(kvmclock_periodic_sync, bool, S_IRUGO);
104
92a1f12d
JR		 105bool kvm_has_tsc_control;
106EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
107u32 kvm_max_guest_tsc_khz;
108EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
109
cc578287
ZA		 110/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
111static u32 tsc_tolerance_ppm = 250;
112module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
113
d0659d94
MT		 114/* lapic timer advance (tscdeadline mode only) in nanoseconds */
115unsigned int lapic_timer_advance_ns = 0;
116module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
117
16a96021
MT		 118static bool backwards_tsc_observed = false;
119
18863bdd
AK		 120#define KVM_NR_SHARED_MSRS 16
121
122struct kvm_shared_msrs_global {
123 int nr;
2bf78fa7 124 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 125};
126
127struct kvm_shared_msrs {
128 struct user_return_notifier urn;
129 bool registered;
2bf78fa7
SY		 130 struct kvm_shared_msr_values {
131 u64 host;
132 u64 curr;
133 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 134};
135
136static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 137static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 138
417bc304 139struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 140 { "pf_fixed", VCPU_STAT(pf_fixed) },
141 { "pf_guest", VCPU_STAT(pf_guest) },
142 { "tlb_flush", VCPU_STAT(tlb_flush) },
143 { "invlpg", VCPU_STAT(invlpg) },
144 { "exits", VCPU_STAT(exits) },
145 { "io_exits", VCPU_STAT(io_exits) },
146 { "mmio_exits", VCPU_STAT(mmio_exits) },
147 { "signal_exits", VCPU_STAT(signal_exits) },
148 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 149 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 150 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 151 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 152 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 153 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 154 { "request_irq", VCPU_STAT(request_irq_exits) },
155 { "irq_exits", VCPU_STAT(irq_exits) },
156 { "host_state_reload", VCPU_STAT(host_state_reload) },
157 { "efer_reload", VCPU_STAT(efer_reload) },
158 { "fpu_reload", VCPU_STAT(fpu_reload) },
159 { "insn_emulation", VCPU_STAT(insn_emulation) },
160 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 161 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 162 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 163 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
164 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
165 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
166 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
167 { "mmu_flooded", VM_STAT(mmu_flooded) },
168 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 169 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 170 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 171 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 172 { "largepages", VM_STAT(lpages) },
417bc304
HB		 173 { NULL }
174};
175
2acf923e
DC		 176u64 __read_mostly host_xcr0;
177
b6785def 178static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 179
af585b92
GN		 180static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
181{
182 int i;
183 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
184 vcpu->arch.apf.gfns[i] = ~0;
185}
186
18863bdd
AK		 187static void kvm_on_user_return(struct user_return_notifier *urn)
188{
189 unsigned slot;
18863bdd
AK		 190 struct kvm_shared_msrs *locals
191 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 192 struct kvm_shared_msr_values *values;
18863bdd
AK		 193
194 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 195 values = &locals->values[slot];
196 if (values->host != values->curr) {
197 wrmsrl(shared_msrs_global.msrs[slot], values->host);
198 values->curr = values->host;
18863bdd
AK		 199 }
200 }
201 locals->registered = false;
202 user_return_notifier_unregister(urn);
203}
204
2bf78fa7 205static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 206{
18863bdd 207 u64 value;
013f6a5d
MT		 208 unsigned int cpu = smp_processor_id();
209 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 210
2bf78fa7
SY		 211 /* only read, and nobody should modify it at this time,
212 * so don't need lock */
213 if (slot >= shared_msrs_global.nr) {
214 printk(KERN_ERR "kvm: invalid MSR slot!");
215 return;
216 }
217 rdmsrl_safe(msr, &value);
218 smsr->values[slot].host = value;
219 smsr->values[slot].curr = value;
220}
221
222void kvm_define_shared_msr(unsigned slot, u32 msr)
223{
0123be42 224 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 225 if (slot >= shared_msrs_global.nr)
226 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 227 shared_msrs_global.msrs[slot] = msr;
228 /* we need ensured the shared_msr_global have been updated */
229 smp_wmb();
18863bdd
AK		 230}
231EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
232
233static void kvm_shared_msr_cpu_online(void)
234{
235 unsigned i;
18863bdd
AK		 236
237 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 238 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 239}
240
8b3c3104 241int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 242{
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 245 int err;
18863bdd 246
2bf78fa7 247 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 248 return 0;
2bf78fa7 249 smsr->values[slot].curr = value;
8b3c3104
AH		 250 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
251 if (err)
252 return 1;
253
18863bdd
AK		 254 if (!smsr->registered) {
255 smsr->urn.on_user_return = kvm_on_user_return;
256 user_return_notifier_register(&smsr->urn);
257 smsr->registered = true;
258 }
8b3c3104 259 return 0;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
262
13a34e06 263static void drop_user_return_notifiers(void)
3548bab5 264{
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 267
268 if (smsr->registered)
269 kvm_on_user_return(&smsr->urn);
270}
271
6866b83e
CO		 272u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
273{
8a5a87d9 274 return vcpu->arch.apic_base;
6866b83e
CO		 275}
276EXPORT_SYMBOL_GPL(kvm_get_apic_base);
277
58cb628d
JK		 278int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
279{
280 u64 old_state = vcpu->arch.apic_base &
281 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
282 u64 new_state = msr_info->data &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
285 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
286
287 if (!msr_info->host_initiated &&
288 ((msr_info->data & reserved_bits) != 0 ||
289 new_state == X2APIC_ENABLE ||
290 (new_state == MSR_IA32_APICBASE_ENABLE &&
291 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
292 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
293 old_state == 0)))
294 return 1;
295
296 kvm_lapic_set_base(vcpu, msr_info->data);
297 return 0;
6866b83e
CO		 298}
299EXPORT_SYMBOL_GPL(kvm_set_apic_base);
300
2605fc21 301asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 302{
303 /* Fault while not rebooting. We want the trace. */
304 BUG();
305}
306EXPORT_SYMBOL_GPL(kvm_spurious_fault);
307
3fd28fce
ED		 308#define EXCPT_BENIGN 0
309#define EXCPT_CONTRIBUTORY 1
310#define EXCPT_PF 2
311
312static int exception_class(int vector)
313{
314 switch (vector) {
315 case PF_VECTOR:
316 return EXCPT_PF;
317 case DE_VECTOR:
318 case TS_VECTOR:
319 case NP_VECTOR:
320 case SS_VECTOR:
321 case GP_VECTOR:
322 return EXCPT_CONTRIBUTORY;
323 default:
324 break;
325 }
326 return EXCPT_BENIGN;
327}
328
d6e8c854
NA		 329#define EXCPT_FAULT 0
330#define EXCPT_TRAP 1
331#define EXCPT_ABORT 2
332#define EXCPT_INTERRUPT 3
333
334static int exception_type(int vector)
335{
336 unsigned int mask;
337
338 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
339 return EXCPT_INTERRUPT;
340
341 mask = 1 << vector;
342
343 /* #DB is trap, as instruction watchpoints are handled elsewhere */
344 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
345 return EXCPT_TRAP;
346
347 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
348 return EXCPT_ABORT;
349
350 /* Reserved exceptions will result in fault */
351 return EXCPT_FAULT;
352}
353
3fd28fce 354static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 355 unsigned nr, bool has_error, u32 error_code,
356 bool reinject)
3fd28fce
ED		 357{
358 u32 prev_nr;
359 int class1, class2;
360
3842d135
AK		 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
362
3fd28fce
ED		 363 if (!vcpu->arch.exception.pending) {
364 queue:
3ffb2468
NA		 365 if (has_error && !is_protmode(vcpu))
366 has_error = false;
3fd28fce
ED		 367 vcpu->arch.exception.pending = true;
368 vcpu->arch.exception.has_error_code = has_error;
369 vcpu->arch.exception.nr = nr;
370 vcpu->arch.exception.error_code = error_code;
3f0fd292 371 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 372 return;
373 }
374
375 /* to check exception */
376 prev_nr = vcpu->arch.exception.nr;
377 if (prev_nr == DF_VECTOR) {
378 /* triple fault -> shutdown */
a8eeb04a 379 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 380 return;
381 }
382 class1 = exception_class(prev_nr);
383 class2 = exception_class(nr);
384 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
385 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
386 /* generate double fault per SDM Table 5-5 */
387 vcpu->arch.exception.pending = true;
388 vcpu->arch.exception.has_error_code = true;
389 vcpu->arch.exception.nr = DF_VECTOR;
390 vcpu->arch.exception.error_code = 0;
391 } else
392 /* replace previous exception with a new one in a hope
393 that instruction re-execution will regenerate lost
394 exception */
395 goto queue;
396}
397
298101da
AK		 398void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
399{
ce7ddec4 400 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 401}
402EXPORT_SYMBOL_GPL(kvm_queue_exception);
403
ce7ddec4
JR		 404void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
405{
406 kvm_multiple_exception(vcpu, nr, false, 0, true);
407}
408EXPORT_SYMBOL_GPL(kvm_requeue_exception);
409
db8fcefa 410void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 411{
db8fcefa
AP		 412 if (err)
413 kvm_inject_gp(vcpu, 0);
414 else
415 kvm_x86_ops->skip_emulated_instruction(vcpu);
416}
417EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 418
6389ee94 419void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 420{
421 ++vcpu->stat.pf_guest;
6389ee94
AK		 422 vcpu->arch.cr2 = fault->address;
423 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 424}
27d6c865 425EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 426
ef54bcfe 427static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 428{
6389ee94
AK		 429 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
430 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 431 else
6389ee94 432 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 433
434 return fault->nested_page_fault;
d4f8cf66
JR		 435}
436
3419ffc8
SY		 437void kvm_inject_nmi(struct kvm_vcpu *vcpu)
438{
7460fb4a
AK		 439 atomic_inc(&vcpu->arch.nmi_queued);
440 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 441}
442EXPORT_SYMBOL_GPL(kvm_inject_nmi);
443
298101da
AK		 444void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
445{
ce7ddec4 446 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 447}
448EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
449
ce7ddec4
JR		 450void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
451{
452 kvm_multiple_exception(vcpu, nr, true, error_code, true);
453}
454EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
455
0a79b009
AK		 456/*
457 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
458 * a #GP and return false.
459 */
460bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 461{
0a79b009
AK		 462 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
463 return true;
464 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
465 return false;
298101da 466}
0a79b009 467EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 468
16f8a6f9
NA		 469bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
470{
471 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
472 return true;
473
474 kvm_queue_exception(vcpu, UD_VECTOR);
475 return false;
476}
477EXPORT_SYMBOL_GPL(kvm_require_dr);
478
ec92fe44
JR		 479/*
480 * This function will be used to read from the physical memory of the currently
481 * running guest. The difference to kvm_read_guest_page is that this function
482 * can read from guest physical or from the guest's guest physical memory.
483 */
484int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
485 gfn_t ngfn, void *data, int offset, int len,
486 u32 access)
487{
54987b7a 488 struct x86_exception exception;
ec92fe44
JR		 489 gfn_t real_gfn;
490 gpa_t ngpa;
491
492 ngpa = gfn_to_gpa(ngfn);
54987b7a 493 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 494 if (real_gfn == UNMAPPED_GVA)
495 return -EFAULT;
496
497 real_gfn = gpa_to_gfn(real_gfn);
498
499 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
500}
501EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
502
69b0049a 503static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 504 void *data, int offset, int len, u32 access)
505{
506 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
507 data, offset, len, access);
508}
509
a03490ed
CO		 510/*
511 * Load the pae pdptrs. Return true is they are all valid.
512 */
ff03a073 513int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 514{
515 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
516 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
517 int i;
518 int ret;
ff03a073 519 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 520
ff03a073
JR		 521 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
522 offset * sizeof(u64), sizeof(pdpte),
523 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 524 if (ret < 0) {
525 ret = 0;
526 goto out;
527 }
528 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 529 if (is_present_gpte(pdpte[i]) &&
20c466b5 530 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 531 ret = 0;
532 goto out;
533 }
534 }
535 ret = 1;
536
ff03a073 537 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 538 __set_bit(VCPU_EXREG_PDPTR,
539 (unsigned long *)&vcpu->arch.regs_avail);
540 __set_bit(VCPU_EXREG_PDPTR,
541 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 542out:
a03490ed
CO		 543
544 return ret;
545}
cc4b6871 546EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 547
d835dfec
AK		 548static bool pdptrs_changed(struct kvm_vcpu *vcpu)
549{
ff03a073 550 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 551 bool changed = true;
3d06b8bf
JR		 552 int offset;
553 gfn_t gfn;
d835dfec
AK		 554 int r;
555
556 if (is_long_mode(vcpu) || !is_pae(vcpu))
557 return false;
558
6de4f3ad
AK		 559 if (!test_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_avail))
561 return true;
562
9f8fe504
AK		 563 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
564 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 565 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
566 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 567 if (r < 0)
568 goto out;
ff03a073 569 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 570out:
d835dfec
AK		 571
572 return changed;
573}
574
49a9b07e 575int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 576{
aad82703 577 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 578 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 579
f9a48e6a
AK		 580 cr0 |= X86_CR0_ET;
581
ab344828 582#ifdef CONFIG_X86_64
0f12244f
GN		 583 if (cr0 & 0xffffffff00000000UL)
584 return 1;
ab344828
GN		 585#endif
586
587 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 588
0f12244f
GN		 589 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
590 return 1;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
593 return 1;
a03490ed
CO		 594
595 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
596#ifdef CONFIG_X86_64
f6801dff 597 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 598 int cs_db, cs_l;
599
0f12244f
GN		 600 if (!is_pae(vcpu))
601 return 1;
a03490ed 602 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 603 if (cs_l)
604 return 1;
a03490ed
CO		 605 } else
606#endif
ff03a073 607 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 608 kvm_read_cr3(vcpu)))
0f12244f 609 return 1;
a03490ed
CO		 610 }
611
ad756a16
MJ		 612 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
613 return 1;
614
a03490ed 615 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 616
d170c419 617 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 618 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 619 kvm_async_pf_hash_reset(vcpu);
620 }
e5f3f027 621
aad82703
SY		 622 if ((cr0 ^ old_cr0) & update_bits)
623 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 624 return 0;
625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 627
2d3ad1f4 628void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 629{
49a9b07e 630 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 631}
2d3ad1f4 632EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 633
42bdf991
MT		 634static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
635{
636 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
637 !vcpu->guest_xcr0_loaded) {
638 /* kvm_set_xcr() also depends on this */
639 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
640 vcpu->guest_xcr0_loaded = 1;
641 }
642}
643
644static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
645{
646 if (vcpu->guest_xcr0_loaded) {
647 if (vcpu->arch.xcr0 != host_xcr0)
648 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
649 vcpu->guest_xcr0_loaded = 0;
650 }
651}
652
69b0049a 653static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 654{
56c103ec
LJ		 655 u64 xcr0 = xcr;
656 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 657 u64 valid_bits;
2acf923e
DC		 658
659 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
660 if (index != XCR_XFEATURE_ENABLED_MASK)
661 return 1;
2acf923e
DC		 662 if (!(xcr0 & XSTATE_FP))
663 return 1;
664 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
665 return 1;
46c34cb0
PB		 666
667 /*
668 * Do not allow the guest to set bits that we do not support
669 * saving. However, xcr0 bit 0 is always set, even if the
670 * emulated CPU does not support XSAVE (see fx_init).
671 */
672 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
673 if (xcr0 & ~valid_bits)
2acf923e 674 return 1;
46c34cb0 675
390bd528
LJ		 676 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
677 return 1;
678
612263b3
CP		 679 if (xcr0 & XSTATE_AVX512) {
680 if (!(xcr0 & XSTATE_YMM))
681 return 1;
682 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
683 return 1;
684 }
42bdf991 685 kvm_put_guest_xcr0(vcpu);
2acf923e 686 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 687
688 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
689 kvm_update_cpuid(vcpu);
2acf923e
DC		 690 return 0;
691}
692
693int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
694{
764bcbc5
Z		 695 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
696 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 697 kvm_inject_gp(vcpu, 0);
698 return 1;
699 }
700 return 0;
701}
702EXPORT_SYMBOL_GPL(kvm_set_xcr);
703
a83b29c6 704int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 705{
fc78f519 706 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 707 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
708 X86_CR4_SMEP | X86_CR4_SMAP;
709
0f12244f
GN		 710 if (cr4 & CR4_RESERVED_BITS)
711 return 1;
a03490ed 712
2acf923e
DC		 713 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
714 return 1;
715
c68b734f
YW		 716 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
717 return 1;
718
97ec8c06
FW		 719 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
720 return 1;
721
afcbf13f 722 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 723 return 1;
724
a03490ed 725 if (is_long_mode(vcpu)) {
0f12244f
GN		 726 if (!(cr4 & X86_CR4_PAE))
727 return 1;
a2edf57f
AK		 728 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
729 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 730 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
731 kvm_read_cr3(vcpu)))
0f12244f
GN		 732 return 1;
733
ad756a16
MJ		 734 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
735 if (!guest_cpuid_has_pcid(vcpu))
736 return 1;
737
738 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
739 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
740 return 1;
741 }
742
5e1746d6 743 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 744 return 1;
a03490ed 745
ad756a16
MJ		 746 if (((cr4 ^ old_cr4) & pdptr_bits) ||
747 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 748 kvm_mmu_reset_context(vcpu);
0f12244f 749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb
GC		 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
928 * kvm-specific. Those are put in the beginning of the list.
043405e1 929 */
e3267cbb 930
e984097b 931#define KVM_SAVE_MSRS_BEGIN 12
043405e1 932static u32 msrs_to_save[] = {
e3267cbb 933 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 934 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 935 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 936 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 937 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 938 MSR_KVM_PV_EOI_EN,
043405e1 939 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 940 MSR_STAR,
043405e1
CO		 941#ifdef CONFIG_X86_64
942 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
943#endif
b3897a49 944 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 945 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 946};
947
948static unsigned num_msrs_to_save;
949
f1d24831 950static const u32 emulated_msrs[] = {
ba904635 951 MSR_IA32_TSC_ADJUST,
a3e06bbe 952 MSR_IA32_TSCDEADLINE,
043405e1 953 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 954 MSR_IA32_MCG_STATUS,
955 MSR_IA32_MCG_CTL,
043405e1
CO		 956};
957
384bb783 958bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 959{
b69e8cae 960 if (efer & efer_reserved_bits)
384bb783 961 return false;
15c4a640 962
1b2fd70c
AG		 963 if (efer & EFER_FFXSR) {
964 struct kvm_cpuid_entry2 *feat;
965
966 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 967 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 968 return false;
1b2fd70c
AG		 969 }
970
d8017474
AG		 971 if (efer & EFER_SVME) {
972 struct kvm_cpuid_entry2 *feat;
973
974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 975 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 976 return false;
d8017474
AG		 977 }
978
384bb783
JK		 979 return true;
980}
981EXPORT_SYMBOL_GPL(kvm_valid_efer);
982
983static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
984{
985 u64 old_efer = vcpu->arch.efer;
986
987 if (!kvm_valid_efer(vcpu, efer))
988 return 1;
989
990 if (is_paging(vcpu)
991 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992 return 1;
993
15c4a640 994 efer &= ~EFER_LMA;
f6801dff 995 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 996
a3d204e2
SY		 997 kvm_x86_ops->set_efer(vcpu, efer);
998
aad82703
SY		 999 /* Update reserved bits */
1000 if ((efer ^ old_efer) & EFER_NX)
1001 kvm_mmu_reset_context(vcpu);
1002
b69e8cae 1003 return 0;
15c4a640
CO		 1004}
1005
f2b4b7dd
JR		 1006void kvm_enable_efer_bits(u64 mask)
1007{
1008 efer_reserved_bits &= ~mask;
1009}
1010EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1011
15c4a640
CO		 1012/*
1013 * Writes msr value into into the appropriate "register".
1014 * Returns 0 on success, non-0 otherwise.
1015 * Assumes vcpu_load() was already called.
1016 */
8fe8ab46 1017int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1018{
854e8bb1
NA		 1019 switch (msr->index) {
1020 case MSR_FS_BASE:
1021 case MSR_GS_BASE:
1022 case MSR_KERNEL_GS_BASE:
1023 case MSR_CSTAR:
1024 case MSR_LSTAR:
1025 if (is_noncanonical_address(msr->data))
1026 return 1;
1027 break;
1028 case MSR_IA32_SYSENTER_EIP:
1029 case MSR_IA32_SYSENTER_ESP:
1030 /*
1031 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1032 * non-canonical address is written on Intel but not on
1033 * AMD (which ignores the top 32-bits, because it does
1034 * not implement 64-bit SYSENTER).
1035 *
1036 * 64-bit code should hence be able to write a non-canonical
1037 * value on AMD. Making the address canonical ensures that
1038 * vmentry does not fail on Intel after writing a non-canonical
1039 * value, and that something deterministic happens if the guest
1040 * invokes 64-bit SYSENTER.
1041 */
1042 msr->data = get_canonical(msr->data);
1043 }
8fe8ab46 1044 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1045}
854e8bb1 1046EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1047
313a3dc7
CO		 1048/*
1049 * Adapt set_msr() to msr_io()'s calling convention
1050 */
1051static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1052{
8fe8ab46
WA		 1053 struct msr_data msr;
1054
1055 msr.data = *data;
1056 msr.index = index;
1057 msr.host_initiated = true;
1058 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1059}
1060
16e8d74d
MT		 1061#ifdef CONFIG_X86_64
1062struct pvclock_gtod_data {
1063 seqcount_t seq;
1064
1065 struct { /* extract of a clocksource struct */
1066 int vclock_mode;
1067 cycle_t cycle_last;
1068 cycle_t mask;
1069 u32 mult;
1070 u32 shift;
1071 } clock;
1072
cbcf2dd3
TG		 1073 u64 boot_ns;
1074 u64 nsec_base;
16e8d74d
MT		 1075};
1076
1077static struct pvclock_gtod_data pvclock_gtod_data;
1078
1079static void update_pvclock_gtod(struct timekeeper *tk)
1080{
1081 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1082 u64 boot_ns;
1083
876e7881 1084 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1085
1086 write_seqcount_begin(&vdata->seq);
1087
1088 /* copy pvclock gtod data */
876e7881
PZ		 1089 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1090 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1091 vdata->clock.mask = tk->tkr_mono.mask;
1092 vdata->clock.mult = tk->tkr_mono.mult;
1093 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1094
cbcf2dd3 1095 vdata->boot_ns = boot_ns;
876e7881 1096 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1097
1098 write_seqcount_end(&vdata->seq);
1099}
1100#endif
1101
bab5bb39
NK		 1102void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1103{
1104 /*
1105 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1106 * vcpu_enter_guest. This function is only called from
1107 * the physical CPU that is running vcpu.
1108 */
1109 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1110}
16e8d74d 1111
18068523
GOC		 1112static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113{
9ed3c444
AK		 1114 int version;
1115 int r;
50d0a0f9 1116 struct pvclock_wall_clock wc;
923de3cf 1117 struct timespec boot;
18068523
GOC		 1118
1119 if (!wall_clock)
1120 return;
1121
9ed3c444
AK		 1122 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1123 if (r)
1124 return;
1125
1126 if (version & 1)
1127 ++version; /* first time write, random junk */
1128
1129 ++version;
18068523 1130
18068523
GOC		 1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1132
50d0a0f9
GH		 1133 /*
1134 * The guest calculates current wall clock time by adding
34c238a1 1135 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1136 * wall clock specified here. guest system time equals host
1137 * system time for us, thus we must fill in host boot time here.
1138 */
923de3cf 1139 getboottime(&boot);
50d0a0f9 1140
4b648665
BR		 1141 if (kvm->arch.kvmclock_offset) {
1142 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1143 boot = timespec_sub(boot, ts);
1144 }
50d0a0f9
GH		 1145 wc.sec = boot.tv_sec;
1146 wc.nsec = boot.tv_nsec;
1147 wc.version = version;
18068523
GOC		 1148
1149 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1150
1151 version++;
1152 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1153}
1154
50d0a0f9
GH		 1155static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1156{
1157 uint32_t quotient, remainder;
1158
1159 /* Don't try to replace with do_div(), this one calculates
1160 * "(dividend << 32) / divisor" */
1161 __asm__ ( "divl %4"
1162 : "=a" (quotient), "=d" (remainder)
1163 : "0" (0), "1" (dividend), "r" (divisor) );
1164 return quotient;
1165}
1166
5f4e3f88
ZA		 1167static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1168 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1169{
5f4e3f88 1170 uint64_t scaled64;
50d0a0f9
GH		 1171 int32_t shift = 0;
1172 uint64_t tps64;
1173 uint32_t tps32;
1174
5f4e3f88
ZA		 1175 tps64 = base_khz * 1000LL;
1176 scaled64 = scaled_khz * 1000LL;
50933623 1177 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1178 tps64 >>= 1;
1179 shift--;
1180 }
1181
1182 tps32 = (uint32_t)tps64;
50933623
JK		 1183 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1184 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1185 scaled64 >>= 1;
1186 else
1187 tps32 <<= 1;
50d0a0f9
GH		 1188 shift++;
1189 }
1190
5f4e3f88
ZA		 1191 *pshift = shift;
1192 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1193
5f4e3f88
ZA		 1194 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1195 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1196}
1197
759379dd
ZA		 1198static inline u64 get_kernel_ns(void)
1199{
bb0b5812 1200 return ktime_get_boot_ns();
50d0a0f9
GH		 1201}
1202
d828199e 1203#ifdef CONFIG_X86_64
16e8d74d 1204static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1205#endif
16e8d74d 1206
c8076604 1207static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1208static unsigned long max_tsc_khz;
c8076604 1209
cc578287 1210static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1211{
cc578287
ZA		 1212 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1213 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1214}
1215
cc578287 1216static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1217{
cc578287
ZA		 1218 u64 v = (u64)khz * (1000000 + ppm);
1219 do_div(v, 1000000);
1220 return v;
1e993611
JR		 1221}
1222
cc578287 1223static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1224{
cc578287
ZA		 1225 u32 thresh_lo, thresh_hi;
1226 int use_scaling = 0;
217fc9cf 1227
03ba32ca
MT		 1228 /* tsc_khz can be zero if TSC calibration fails */
1229 if (this_tsc_khz == 0)
1230 return;
1231
c285545f
ZA		 1232 /* Compute a scale to convert nanoseconds in TSC cycles */
1233 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1234 &vcpu->arch.virtual_tsc_shift,
1235 &vcpu->arch.virtual_tsc_mult);
1236 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1237
1238 /*
1239 * Compute the variation in TSC rate which is acceptable
1240 * within the range of tolerance and decide if the
1241 * rate being applied is within that bounds of the hardware
1242 * rate. If so, no scaling or compensation need be done.
1243 */
1244 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1245 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1246 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1247 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1248 use_scaling = 1;
1249 }
1250 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1251}
1252
1253static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1254{
e26101b1 1255 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1256 vcpu->arch.virtual_tsc_mult,
1257 vcpu->arch.virtual_tsc_shift);
e26101b1 1258 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1259 return tsc;
1260}
1261
69b0049a 1262static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1263{
1264#ifdef CONFIG_X86_64
1265 bool vcpus_matched;
b48aa97e
MT		 1266 struct kvm_arch *ka = &vcpu->kvm->arch;
1267 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1268
1269 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1270 atomic_read(&vcpu->kvm->online_vcpus));
1271
7f187922
MT		 1272 /*
1273 * Once the masterclock is enabled, always perform request in
1274 * order to update it.
1275 *
1276 * In order to enable masterclock, the host clocksource must be TSC
1277 * and the vcpus need to have matched TSCs. When that happens,
1278 * perform request to enable masterclock.
1279 */
1280 if (ka->use_master_clock ||
1281 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1282 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1283
1284 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1285 atomic_read(&vcpu->kvm->online_vcpus),
1286 ka->use_master_clock, gtod->clock.vclock_mode);
1287#endif
1288}
1289
ba904635
WA		 1290static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1291{
1292 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1293 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1294}
1295
8fe8ab46 1296void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1297{
1298 struct kvm *kvm = vcpu->kvm;
f38e098f 1299 u64 offset, ns, elapsed;
99e3e30a 1300 unsigned long flags;
02626b6a 1301 s64 usdiff;
b48aa97e 1302 bool matched;
0d3da0d2 1303 bool already_matched;
8fe8ab46 1304 u64 data = msr->data;
99e3e30a 1305
038f8c11 1306 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1308 ns = get_kernel_ns();
f38e098f 1309 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1310
03ba32ca 1311 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1312 int faulted = 0;
1313
03ba32ca
MT		 1314 /* n.b - signed multiplication and division required */
1315 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1316#ifdef CONFIG_X86_64
03ba32ca 1317 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1318#else
03ba32ca 1319 /* do_div() only does unsigned */
8915aa27
MT		 1320 asm("1: idivl %[divisor]\n"
1321 "2: xor %%edx, %%edx\n"
1322 " movl $0, %[faulted]\n"
1323 "3:\n"
1324 ".section .fixup,\"ax\"\n"
1325 "4: movl $1, %[faulted]\n"
1326 " jmp 3b\n"
1327 ".previous\n"
1328
1329 _ASM_EXTABLE(1b, 4b)
1330
1331 : "=A"(usdiff), [faulted] "=r" (faulted)
1332 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1333
5d3cb0f6 1334#endif
03ba32ca
MT		 1335 do_div(elapsed, 1000);
1336 usdiff -= elapsed;
1337 if (usdiff < 0)
1338 usdiff = -usdiff;
8915aa27
MT		 1339
1340 /* idivl overflow => difference is larger than USEC_PER_SEC */
1341 if (faulted)
1342 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1343 } else
1344 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1345
1346 /*
5d3cb0f6
ZA		 1347 * Special case: TSC write with a small delta (1 second) of virtual
1348 * cycle time against real time is interpreted as an attempt to
1349 * synchronize the CPU.
1350 *
1351 * For a reliable TSC, we can match TSC offsets, and for an unstable
1352 * TSC, we add elapsed time in this computation. We could let the
1353 * compensation code attempt to catch up if we fall behind, but
1354 * it's better to try to match offsets from the beginning.
1355 */
02626b6a 1356 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1357 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1358 if (!check_tsc_unstable()) {
e26101b1 1359 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1360 pr_debug("kvm: matched tsc offset for %llu\n", data);
1361 } else {
857e4099 1362 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1363 data += delta;
1364 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1365 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1366 }
b48aa97e 1367 matched = true;
0d3da0d2 1368 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1369 } else {
1370 /*
1371 * We split periods of matched TSC writes into generations.
1372 * For each generation, we track the original measured
1373 * nanosecond time, offset, and write, so if TSCs are in
1374 * sync, we can match exact offset, and if not, we can match
4a969980 1375 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1376 *
1377 * These values are tracked in kvm->arch.cur_xxx variables.
1378 */
1379 kvm->arch.cur_tsc_generation++;
1380 kvm->arch.cur_tsc_nsec = ns;
1381 kvm->arch.cur_tsc_write = data;
1382 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1383 matched = false;
0d3da0d2 1384 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1385 kvm->arch.cur_tsc_generation, data);
f38e098f 1386 }
e26101b1
ZA		 1387
1388 /*
1389 * We also track th most recent recorded KHZ, write and time to
1390 * allow the matching interval to be extended at each write.
1391 */
f38e098f
ZA		 1392 kvm->arch.last_tsc_nsec = ns;
1393 kvm->arch.last_tsc_write = data;
5d3cb0f6 1394 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1395
b183aa58 1396 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1397
1398 /* Keep track of which generation this VCPU has synchronized to */
1399 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1400 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1401 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1402
ba904635
WA		 1403 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1404 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1405 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1406 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1407
1408 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1409 if (!matched) {
b48aa97e 1410 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1411 } else if (!already_matched) {
1412 kvm->arch.nr_vcpus_matched_tsc++;
1413 }
b48aa97e
MT		 1414
1415 kvm_track_tsc_matching(vcpu);
1416 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1417}
e26101b1 1418
99e3e30a
ZA		 1419EXPORT_SYMBOL_GPL(kvm_write_tsc);
1420
d828199e
MT		 1421#ifdef CONFIG_X86_64
1422
1423static cycle_t read_tsc(void)
1424{
1425 cycle_t ret;
1426 u64 last;
1427
1428 /*
1429 * Empirically, a fence (of type that depends on the CPU)
1430 * before rdtsc is enough to ensure that rdtsc is ordered
1431 * with respect to loads. The various CPU manuals are unclear
1432 * as to whether rdtsc can be reordered with later loads,
1433 * but no one has ever seen it happen.
1434 */
1435 rdtsc_barrier();
1436 ret = (cycle_t)vget_cycles();
1437
1438 last = pvclock_gtod_data.clock.cycle_last;
1439
1440 if (likely(ret >= last))
1441 return ret;
1442
1443 /*
1444 * GCC likes to generate cmov here, but this branch is extremely
1445 * predictable (it's just a funciton of time and the likely is
1446 * very likely) and there's a data dependence, so force GCC
1447 * to generate a branch instead. I don't barrier() because
1448 * we don't actually need a barrier, and if this function
1449 * ever gets inlined it will generate worse code.
1450 */
1451 asm volatile ("");
1452 return last;
1453}
1454
1455static inline u64 vgettsc(cycle_t *cycle_now)
1456{
1457 long v;
1458 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1459
1460 *cycle_now = read_tsc();
1461
1462 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1463 return v * gtod->clock.mult;
1464}
1465
cbcf2dd3 1466static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1467{
cbcf2dd3 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1469 unsigned long seq;
d828199e 1470 int mode;
cbcf2dd3 1471 u64 ns;
d828199e 1472
d828199e
MT		 1473 do {
1474 seq = read_seqcount_begin(&gtod->seq);
1475 mode = gtod->clock.vclock_mode;
cbcf2dd3 1476 ns = gtod->nsec_base;
d828199e
MT		 1477 ns += vgettsc(cycle_now);
1478 ns >>= gtod->clock.shift;
cbcf2dd3 1479 ns += gtod->boot_ns;
d828199e 1480 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1481 *t = ns;
d828199e
MT		 1482
1483 return mode;
1484}
1485
1486/* returns true if host is using tsc clocksource */
1487static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1488{
d828199e
MT		 1489 /* checked again under seqlock below */
1490 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1491 return false;
1492
cbcf2dd3 1493 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1494}
1495#endif
1496
1497/*
1498 *
b48aa97e
MT		 1499 * Assuming a stable TSC across physical CPUS, and a stable TSC
1500 * across virtual CPUs, the following condition is possible.
1501 * Each numbered line represents an event visible to both
d828199e
MT		 1502 * CPUs at the next numbered event.
1503 *
1504 * "timespecX" represents host monotonic time. "tscX" represents
1505 * RDTSC value.
1506 *
1507 * VCPU0 on CPU0 | VCPU1 on CPU1
1508 *
1509 * 1. read timespec0,tsc0
1510 * 2. | timespec1 = timespec0 + N
1511 * | tsc1 = tsc0 + M
1512 * 3. transition to guest | transition to guest
1513 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1514 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1515 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1516 *
1517 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1518 *
1519 * - ret0 < ret1
1520 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1521 * ...
1522 * - 0 < N - M => M < N
1523 *
1524 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1525 * always the case (the difference between two distinct xtime instances
1526 * might be smaller then the difference between corresponding TSC reads,
1527 * when updating guest vcpus pvclock areas).
1528 *
1529 * To avoid that problem, do not allow visibility of distinct
1530 * system_timestamp/tsc_timestamp values simultaneously: use a master
1531 * copy of host monotonic time values. Update that master copy
1532 * in lockstep.
1533 *
b48aa97e 1534 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1535 *
1536 */
1537
1538static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1539{
1540#ifdef CONFIG_X86_64
1541 struct kvm_arch *ka = &kvm->arch;
1542 int vclock_mode;
b48aa97e
MT		 1543 bool host_tsc_clocksource, vcpus_matched;
1544
1545 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1546 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1547
1548 /*
1549 * If the host uses TSC clock, then passthrough TSC as stable
1550 * to the guest.
1551 */
b48aa97e 1552 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1553 &ka->master_kernel_ns,
1554 &ka->master_cycle_now);
1555
16a96021 1556 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1557 && !backwards_tsc_observed
1558 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1559
d828199e
MT		 1560 if (ka->use_master_clock)
1561 atomic_set(&kvm_guest_has_master_clock, 1);
1562
1563 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1564 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1565 vcpus_matched);
d828199e
MT		 1566#endif
1567}
1568
2e762ff7
MT		 1569static void kvm_gen_update_masterclock(struct kvm *kvm)
1570{
1571#ifdef CONFIG_X86_64
1572 int i;
1573 struct kvm_vcpu *vcpu;
1574 struct kvm_arch *ka = &kvm->arch;
1575
1576 spin_lock(&ka->pvclock_gtod_sync_lock);
1577 kvm_make_mclock_inprogress_request(kvm);
1578 /* no guest entries from this point */
1579 pvclock_update_vm_gtod_copy(kvm);
1580
1581 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1582 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1583
1584 /* guest entries allowed */
1585 kvm_for_each_vcpu(i, vcpu, kvm)
1586 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1587
1588 spin_unlock(&ka->pvclock_gtod_sync_lock);
1589#endif
1590}
1591
34c238a1 1592static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1593{
d828199e 1594 unsigned long flags, this_tsc_khz;
18068523 1595 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1596 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1597 s64 kernel_ns;
d828199e 1598 u64 tsc_timestamp, host_tsc;
0b79459b 1599 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1600 u8 pvclock_flags;
d828199e
MT		 1601 bool use_master_clock;
1602
1603 kernel_ns = 0;
1604 host_tsc = 0;
18068523 1605
d828199e
MT		 1606 /*
1607 * If the host uses TSC clock, then passthrough TSC as stable
1608 * to the guest.
1609 */
1610 spin_lock(&ka->pvclock_gtod_sync_lock);
1611 use_master_clock = ka->use_master_clock;
1612 if (use_master_clock) {
1613 host_tsc = ka->master_cycle_now;
1614 kernel_ns = ka->master_kernel_ns;
1615 }
1616 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1617
1618 /* Keep irq disabled to prevent changes to the clock */
1619 local_irq_save(flags);
89cbc767 1620 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1621 if (unlikely(this_tsc_khz == 0)) {
1622 local_irq_restore(flags);
1623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1624 return 1;
1625 }
d828199e
MT		 1626 if (!use_master_clock) {
1627 host_tsc = native_read_tsc();
1628 kernel_ns = get_kernel_ns();
1629 }
1630
1631 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1632
c285545f
ZA		 1633 /*
1634 * We may have to catch up the TSC to match elapsed wall clock
1635 * time for two reasons, even if kvmclock is used.
1636 * 1) CPU could have been running below the maximum TSC rate
1637 * 2) Broken TSC compensation resets the base at each VCPU
1638 * entry to avoid unknown leaps of TSC even when running
1639 * again on the same CPU. This may cause apparent elapsed
1640 * time to disappear, and the guest to stand still or run
1641 * very slowly.
1642 */
1643 if (vcpu->tsc_catchup) {
1644 u64 tsc = compute_guest_tsc(v, kernel_ns);
1645 if (tsc > tsc_timestamp) {
f1e2b260 1646 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1647 tsc_timestamp = tsc;
1648 }
50d0a0f9
GH		 1649 }
1650
18068523
GOC		 1651 local_irq_restore(flags);
1652
0b79459b 1653 if (!vcpu->pv_time_enabled)
c285545f 1654 return 0;
18068523 1655
e48672fa 1656 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1657 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1658 &vcpu->hv_clock.tsc_shift,
1659 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1660 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1661 }
1662
1663 /* With all the info we got, fill in the values */
1d5f066e 1664 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1665 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1666 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1667
09a0c3f1
OH		 1668 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1669 &guest_hv_clock, sizeof(guest_hv_clock))))
1670 return 0;
1671
5dca0d91
RK		 1672 /* This VCPU is paused, but it's legal for a guest to read another
1673 * VCPU's kvmclock, so we really have to follow the specification where
1674 * it says that version is odd if data is being modified, and even after
1675 * it is consistent.
1676 *
1677 * Version field updates must be kept separate. This is because
1678 * kvm_write_guest_cached might use a "rep movs" instruction, and
1679 * writes within a string instruction are weakly ordered. So there
1680 * are three writes overall.
1681 *
1682 * As a small optimization, only write the version field in the first
1683 * and third write. The vcpu->pv_time cache is still valid, because the
1684 * version field is the first in the struct.
18068523 1685 */
5dca0d91
RK		 1686 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1687
1688 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1689 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1690 &vcpu->hv_clock,
1691 sizeof(vcpu->hv_clock.version));
1692
1693 smp_wmb();
78c0337a
MT		 1694
1695 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1696 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1697
1698 if (vcpu->pvclock_set_guest_stopped_request) {
1699 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1700 vcpu->pvclock_set_guest_stopped_request = false;
1701 }
1702
d828199e
MT		 1703 /* If the host uses TSC clocksource, then it is stable */
1704 if (use_master_clock)
1705 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1706
78c0337a
MT		 1707 vcpu->hv_clock.flags = pvclock_flags;
1708
ce1a5e60
DM		 1709 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1710
0b79459b
AH		 1711 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1712 &vcpu->hv_clock,
1713 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1714
1715 smp_wmb();
1716
1717 vcpu->hv_clock.version++;
1718 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1719 &vcpu->hv_clock,
1720 sizeof(vcpu->hv_clock.version));
8cfdc000 1721 return 0;
c8076604
GH		 1722}
1723
0061d53d
MT		 1724/*
1725 * kvmclock updates which are isolated to a given vcpu, such as
1726 * vcpu->cpu migration, should not allow system_timestamp from
1727 * the rest of the vcpus to remain static. Otherwise ntp frequency
1728 * correction applies to one vcpu's system_timestamp but not
1729 * the others.
1730 *
1731 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1732 * We need to rate-limit these requests though, as they can
1733 * considerably slow guests that have a large number of vcpus.
1734 * The time for a remote vcpu to update its kvmclock is bound
1735 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1736 */
1737
7e44e449
AJ		 1738#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1739
1740static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1741{
1742 int i;
7e44e449
AJ		 1743 struct delayed_work *dwork = to_delayed_work(work);
1744 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1745 kvmclock_update_work);
1746 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1747 struct kvm_vcpu *vcpu;
1748
1749 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1750 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1751 kvm_vcpu_kick(vcpu);
1752 }
1753}
1754
7e44e449
AJ		 1755static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1756{
1757 struct kvm *kvm = v->kvm;
1758
105b21bb 1759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1760 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1761 KVMCLOCK_UPDATE_DELAY);
1762}
1763
332967a3
AJ		 1764#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1765
1766static void kvmclock_sync_fn(struct work_struct *work)
1767{
1768 struct delayed_work *dwork = to_delayed_work(work);
1769 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1770 kvmclock_sync_work);
1771 struct kvm *kvm = container_of(ka, struct kvm, arch);
1772
630994b3
MT		 1773 if (!kvmclock_periodic_sync)
1774 return;
1775
332967a3
AJ		 1776 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1777 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1778 KVMCLOCK_SYNC_PERIOD);
1779}
1780
9ba075a6
AK		 1781static bool msr_mtrr_valid(unsigned msr)
1782{
1783 switch (msr) {
1784 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1785 case MSR_MTRRfix64K_00000:
1786 case MSR_MTRRfix16K_80000:
1787 case MSR_MTRRfix16K_A0000:
1788 case MSR_MTRRfix4K_C0000:
1789 case MSR_MTRRfix4K_C8000:
1790 case MSR_MTRRfix4K_D0000:
1791 case MSR_MTRRfix4K_D8000:
1792 case MSR_MTRRfix4K_E0000:
1793 case MSR_MTRRfix4K_E8000:
1794 case MSR_MTRRfix4K_F0000:
1795 case MSR_MTRRfix4K_F8000:
1796 case MSR_MTRRdefType:
1797 case MSR_IA32_CR_PAT:
1798 return true;
1799 case 0x2f8:
1800 return true;
1801 }
1802 return false;
1803}
1804
d6289b93
MT		 1805static bool valid_pat_type(unsigned t)
1806{
1807 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1808}
1809
1810static bool valid_mtrr_type(unsigned t)
1811{
1812 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1813}
1814
4566654b 1815bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1816{
1817 int i;
fd275235 1818 u64 mask;
d6289b93
MT		 1819
1820 if (!msr_mtrr_valid(msr))
1821 return false;
1822
1823 if (msr == MSR_IA32_CR_PAT) {
1824 for (i = 0; i < 8; i++)
1825 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1826 return false;
1827 return true;
1828 } else if (msr == MSR_MTRRdefType) {
1829 if (data & ~0xcff)
1830 return false;
1831 return valid_mtrr_type(data & 0xff);
1832 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1833 for (i = 0; i < 8 ; i++)
1834 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1835 return false;
1836 return true;
1837 }
1838
1839 /* variable MTRRs */
adfb5d27
WL		 1840 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1841
fd275235 1842 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1843 if ((msr & 1) == 0) {
adfb5d27 1844 /* MTRR base */
d7a2a246
WL		 1845 if (!valid_mtrr_type(data & 0xff))
1846 return false;
1847 mask |= 0xf00;
1848 } else
1849 /* MTRR mask */
1850 mask |= 0x7ff;
1851 if (data & mask) {
1852 kvm_inject_gp(vcpu, 0);
1853 return false;
1854 }
1855
adfb5d27 1856 return true;
d6289b93 1857}
4566654b 1858EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1859
efdfe536
XG		 1860static void update_mtrr(struct kvm_vcpu *vcpu, u32 msr)
1861{
1862 struct mtrr_state_type *mtrr_state = &vcpu->arch.mtrr_state;
1863 unsigned char mtrr_enabled = mtrr_state->enabled;
1864 gfn_t start, end, mask;
1865 int index;
1866 bool is_fixed = true;
1867
1868 if (msr == MSR_IA32_CR_PAT || !tdp_enabled ||
1869 !kvm_arch_has_noncoherent_dma(vcpu->kvm))
1870 return;
1871
1872 if (!(mtrr_enabled & 0x2) && msr != MSR_MTRRdefType)
1873 return;
1874
1875 switch (msr) {
1876 case MSR_MTRRfix64K_00000:
1877 start = 0x0;
1878 end = 0x80000;
1879 break;
1880 case MSR_MTRRfix16K_80000:
1881 start = 0x80000;
1882 end = 0xa0000;
1883 break;
1884 case MSR_MTRRfix16K_A0000:
1885 start = 0xa0000;
1886 end = 0xc0000;
1887 break;
1888 case MSR_MTRRfix4K_C0000 ... MSR_MTRRfix4K_F8000:
1889 index = msr - MSR_MTRRfix4K_C0000;
1890 start = 0xc0000 + index * (32 << 10);
1891 end = start + (32 << 10);
1892 break;
1893 case MSR_MTRRdefType:
1894 is_fixed = false;
1895 start = 0x0;
1896 end = ~0ULL;
1897 break;
1898 default:
1899 /* variable range MTRRs. */
1900 is_fixed = false;
1901 index = (msr - 0x200) / 2;
1902 start = (((u64)mtrr_state->var_ranges[index].base_hi) << 32) +
1903 (mtrr_state->var_ranges[index].base_lo & PAGE_MASK);
1904 mask = (((u64)mtrr_state->var_ranges[index].mask_hi) << 32) +
1905 (mtrr_state->var_ranges[index].mask_lo & PAGE_MASK);
1906 mask |= ~0ULL << cpuid_maxphyaddr(vcpu);
1907
1908 end = ((start & mask) | ~mask) + 1;
1909 }
1910
1911 if (is_fixed && !(mtrr_enabled & 0x1))
1912 return;
1913
1914 kvm_zap_gfn_range(vcpu->kvm, gpa_to_gfn(start), gpa_to_gfn(end));
1915}
1916
9ba075a6
AK		 1917static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1918{
0bed3b56
SY		 1919 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1920
4566654b 1921 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1922 return 1;
1923
0bed3b56
SY		 1924 if (msr == MSR_MTRRdefType) {
1925 vcpu->arch.mtrr_state.def_type = data;
1926 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1927 } else if (msr == MSR_MTRRfix64K_00000)
1928 p[0] = data;
1929 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1930 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1931 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1932 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1933 else if (msr == MSR_IA32_CR_PAT)
1934 vcpu->arch.pat = data;
1935 else { /* Variable MTRRs */
1936 int idx, is_mtrr_mask;
1937 u64 *pt;
1938
1939 idx = (msr - 0x200) / 2;
1940 is_mtrr_mask = msr - 0x200 - 2 * idx;
1941 if (!is_mtrr_mask)
1942 pt =
1943 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1944 else
1945 pt =
1946 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1947 *pt = data;
1948 }
1949
efdfe536 1950 update_mtrr(vcpu, msr);
9ba075a6
AK		 1951 return 0;
1952}
15c4a640 1953
890ca9ae 1954static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1955{
890ca9ae
HY		 1956 u64 mcg_cap = vcpu->arch.mcg_cap;
1957 unsigned bank_num = mcg_cap & 0xff;
1958
15c4a640 1959 switch (msr) {
15c4a640 1960 case MSR_IA32_MCG_STATUS:
890ca9ae 1961 vcpu->arch.mcg_status = data;
15c4a640 1962 break;
c7ac679c 1963 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1964 if (!(mcg_cap & MCG_CTL_P))
1965 return 1;
1966 if (data != 0 && data != ~(u64)0)
1967 return -1;
1968 vcpu->arch.mcg_ctl = data;
1969 break;
1970 default:
1971 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1972 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1973 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1974 /* only 0 or all 1s can be written to IA32_MCi_CTL
1975 * some Linux kernels though clear bit 10 in bank 4 to
1976 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1977 * this to avoid an uncatched #GP in the guest
1978 */
890ca9ae 1979 if ((offset & 0x3) == 0 &&
114be429 1980 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1981 return -1;
1982 vcpu->arch.mce_banks[offset] = data;
1983 break;
1984 }
1985 return 1;
1986 }
1987 return 0;
1988}
1989
ffde22ac
ES		 1990static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1991{
1992 struct kvm *kvm = vcpu->kvm;
1993 int lm = is_long_mode(vcpu);
1994 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1995 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1996 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1997 : kvm->arch.xen_hvm_config.blob_size_32;
1998 u32 page_num = data & ~PAGE_MASK;
1999 u64 page_addr = data & PAGE_MASK;
2000 u8 *page;
2001 int r;
2002
2003 r = -E2BIG;
2004 if (page_num >= blob_size)
2005 goto out;
2006 r = -ENOMEM;
ff5c2c03
SL		 2007 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2008 if (IS_ERR(page)) {
2009 r = PTR_ERR(page);
ffde22ac 2010 goto out;
ff5c2c03 2011 }
ffde22ac
ES		 2012 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
2013 goto out_free;
2014 r = 0;
2015out_free:
2016 kfree(page);
2017out:
2018 return r;
2019}
2020
55cd8e5a
GN		 2021static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
2022{
2023 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
2024}
2025
2026static bool kvm_hv_msr_partition_wide(u32 msr)
2027{
2028 bool r = false;
2029 switch (msr) {
2030 case HV_X64_MSR_GUEST_OS_ID:
2031 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 2032 case HV_X64_MSR_REFERENCE_TSC:
2033 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 2034 r = true;
2035 break;
2036 }
2037
2038 return r;
2039}
2040
2041static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2042{
2043 struct kvm *kvm = vcpu->kvm;
2044
2045 switch (msr) {
2046 case HV_X64_MSR_GUEST_OS_ID:
2047 kvm->arch.hv_guest_os_id = data;
2048 /* setting guest os id to zero disables hypercall page */
2049 if (!kvm->arch.hv_guest_os_id)
2050 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
2051 break;
2052 case HV_X64_MSR_HYPERCALL: {
2053 u64 gfn;
2054 unsigned long addr;
2055 u8 instructions[4];
2056
2057 /* if guest os id is not set hypercall should remain disabled */
2058 if (!kvm->arch.hv_guest_os_id)
2059 break;
2060 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2061 kvm->arch.hv_hypercall = data;
2062 break;
2063 }
2064 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2065 addr = gfn_to_hva(kvm, gfn);
2066 if (kvm_is_error_hva(addr))
2067 return 1;
2068 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2069 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2070 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2071 return 1;
2072 kvm->arch.hv_hypercall = data;
b94b64c9 2073 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2074 break;
2075 }
e984097b
VR		 2076 case HV_X64_MSR_REFERENCE_TSC: {
2077 u64 gfn;
2078 HV_REFERENCE_TSC_PAGE tsc_ref;
2079 memset(&tsc_ref, 0, sizeof(tsc_ref));
2080 kvm->arch.hv_tsc_page = data;
2081 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2082 break;
2083 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2084 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2085 &tsc_ref, sizeof(tsc_ref)))
2086 return 1;
2087 mark_page_dirty(kvm, gfn);
2088 break;
2089 }
55cd8e5a 2090 default:
a737f256
CD		 2091 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2092 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2093 return 1;
2094 }
2095 return 0;
2096}
2097
2098static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2099{
10388a07
GN		 2100 switch (msr) {
2101 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2102 u64 gfn;
10388a07 2103 unsigned long addr;
55cd8e5a 2104
10388a07
GN		 2105 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2106 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2107 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2108 return 1;
10388a07
GN		 2109 break;
2110 }
b3af1e88
VR		 2111 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2112 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2113 if (kvm_is_error_hva(addr))
2114 return 1;
8b0cedff 2115 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2116 return 1;
2117 vcpu->arch.hv_vapic = data;
b3af1e88 2118 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2119 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2120 return 1;
10388a07
GN		 2121 break;
2122 }
2123 case HV_X64_MSR_EOI:
2124 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2125 case HV_X64_MSR_ICR:
2126 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2127 case HV_X64_MSR_TPR:
2128 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2129 default:
a737f256
CD		 2130 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2131 "data 0x%llx\n", msr, data);
10388a07
GN		 2132 return 1;
2133 }
2134
2135 return 0;
55cd8e5a
GN		 2136}
2137
344d9588
GN		 2138static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2139{
2140 gpa_t gpa = data & ~0x3f;
2141
4a969980 2142 /* Bits 2:5 are reserved, Should be zero */
6adba527 2143 if (data & 0x3c)
344d9588
GN		 2144 return 1;
2145
2146 vcpu->arch.apf.msr_val = data;
2147
2148 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2149 kvm_clear_async_pf_completion_queue(vcpu);
2150 kvm_async_pf_hash_reset(vcpu);
2151 return 0;
2152 }
2153
8f964525
AH		 2154 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2155 sizeof(u32)))
344d9588
GN		 2156 return 1;
2157
6adba527 2158 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2159 kvm_async_pf_wakeup_all(vcpu);
2160 return 0;
2161}
2162
12f9a48f
GC		 2163static void kvmclock_reset(struct kvm_vcpu *vcpu)
2164{
0b79459b 2165 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2166}
2167
c9aaa895
GC		 2168static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2169{
2170 u64 delta;
2171
2172 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2173 return;
2174
2175 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2176 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2177 vcpu->arch.st.accum_steal = delta;
2178}
2179
2180static void record_steal_time(struct kvm_vcpu *vcpu)
2181{
2182 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2183 return;
2184
2185 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2186 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2187 return;
2188
2189 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2190 vcpu->arch.st.steal.version += 2;
2191 vcpu->arch.st.accum_steal = 0;
2192
2193 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2194 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2195}
2196
8fe8ab46 2197int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2198{
5753785f 2199 bool pr = false;
8fe8ab46
WA		 2200 u32 msr = msr_info->index;
2201 u64 data = msr_info->data;
5753785f 2202
15c4a640 2203 switch (msr) {
2e32b719
BP		 2204 case MSR_AMD64_NB_CFG:
2205 case MSR_IA32_UCODE_REV:
2206 case MSR_IA32_UCODE_WRITE:
2207 case MSR_VM_HSAVE_PA:
2208 case MSR_AMD64_PATCH_LOADER:
2209 case MSR_AMD64_BU_CFG2:
2210 break;
2211
15c4a640 2212 case MSR_EFER:
b69e8cae 2213 return set_efer(vcpu, data);
8f1589d9
AP		 2214 case MSR_K7_HWCR:
2215 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2216 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2217 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2218 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2219 if (data != 0) {
a737f256
CD		 2220 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2221 data);
8f1589d9
AP		 2222 return 1;
2223 }
15c4a640 2224 break;
f7c6d140
AP		 2225 case MSR_FAM10H_MMIO_CONF_BASE:
2226 if (data != 0) {
a737f256
CD		 2227 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2228 "0x%llx\n", data);
f7c6d140
AP		 2229 return 1;
2230 }
15c4a640 2231 break;
b5e2fec0
AG		 2232 case MSR_IA32_DEBUGCTLMSR:
2233 if (!data) {
2234 /* We support the non-activated case already */
2235 break;
2236 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2237 /* Values other than LBR and BTF are vendor-specific,
2238 thus reserved and should throw a #GP */
2239 return 1;
2240 }
a737f256
CD		 2241 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2242 __func__, data);
b5e2fec0 2243 break;
9ba075a6
AK		 2244 case 0x200 ... 0x2ff:
2245 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2246 case MSR_IA32_APICBASE:
58cb628d 2247 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2248 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2249 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2250 case MSR_IA32_TSCDEADLINE:
2251 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2252 break;
ba904635
WA		 2253 case MSR_IA32_TSC_ADJUST:
2254 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2255 if (!msr_info->host_initiated) {
d913b904 2256 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2257 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2258 }
2259 vcpu->arch.ia32_tsc_adjust_msr = data;
2260 }
2261 break;
15c4a640 2262 case MSR_IA32_MISC_ENABLE:
ad312c7c 2263 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2264 break;
11c6bffa 2265 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2266 case MSR_KVM_WALL_CLOCK:
2267 vcpu->kvm->arch.wall_clock = data;
2268 kvm_write_wall_clock(vcpu->kvm, data);
2269 break;
11c6bffa 2270 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2271 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2272 u64 gpa_offset;
54750f2c
MT		 2273 struct kvm_arch *ka = &vcpu->kvm->arch;
2274
12f9a48f 2275 kvmclock_reset(vcpu);
18068523 2276
54750f2c
MT		 2277 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2278 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2279
2280 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2281 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2282 &vcpu->requests);
2283
2284 ka->boot_vcpu_runs_old_kvmclock = tmp;
2285 }
2286
18068523 2287 vcpu->arch.time = data;
0061d53d 2288 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2289
2290 /* we verify if the enable bit is set... */
2291 if (!(data & 1))
2292 break;
2293
0b79459b 2294 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2295
0b79459b 2296 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2297 &vcpu->arch.pv_time, data & ~1ULL,
2298 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2299 vcpu->arch.pv_time_enabled = false;
2300 else
2301 vcpu->arch.pv_time_enabled = true;
32cad84f 2302
18068523
GOC		 2303 break;
2304 }
344d9588
GN		 2305 case MSR_KVM_ASYNC_PF_EN:
2306 if (kvm_pv_enable_async_pf(vcpu, data))
2307 return 1;
2308 break;
c9aaa895
GC		 2309 case MSR_KVM_STEAL_TIME:
2310
2311 if (unlikely(!sched_info_on()))
2312 return 1;
2313
2314 if (data & KVM_STEAL_RESERVED_MASK)
2315 return 1;
2316
2317 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2318 data & KVM_STEAL_VALID_BITS,
2319 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2320 return 1;
2321
2322 vcpu->arch.st.msr_val = data;
2323
2324 if (!(data & KVM_MSR_ENABLED))
2325 break;
2326
2327 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2328
2329 preempt_disable();
2330 accumulate_steal_time(vcpu);
2331 preempt_enable();
2332
2333 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2334
2335 break;
ae7a2a3f
MT		 2336 case MSR_KVM_PV_EOI_EN:
2337 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2338 return 1;
2339 break;
c9aaa895 2340
890ca9ae
HY		 2341 case MSR_IA32_MCG_CTL:
2342 case MSR_IA32_MCG_STATUS:
81760dcc 2343 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2344 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2345
2346 /* Performance counters are not protected by a CPUID bit,
2347 * so we should check all of them in the generic path for the sake of
2348 * cross vendor migration.
2349 * Writing a zero into the event select MSRs disables them,
2350 * which we perfectly emulate ;-). Any other value should be at least
2351 * reported, some guests depend on them.
2352 */
71db6023
AP		 2353 case MSR_K7_EVNTSEL0:
2354 case MSR_K7_EVNTSEL1:
2355 case MSR_K7_EVNTSEL2:
2356 case MSR_K7_EVNTSEL3:
2357 if (data != 0)
a737f256
CD		 2358 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2359 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2360 break;
2361 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2362 * so we ignore writes to make it happy.
2363 */
71db6023
AP		 2364 case MSR_K7_PERFCTR0:
2365 case MSR_K7_PERFCTR1:
2366 case MSR_K7_PERFCTR2:
2367 case MSR_K7_PERFCTR3:
a737f256
CD		 2368 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2369 "0x%x data 0x%llx\n", msr, data);
71db6023 2370 break;
5753785f
GN		 2371 case MSR_P6_PERFCTR0:
2372 case MSR_P6_PERFCTR1:
2373 pr = true;
2374 case MSR_P6_EVNTSEL0:
2375 case MSR_P6_EVNTSEL1:
2376 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2377 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2378
2379 if (pr || data != 0)
a737f256
CD		 2380 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2381 "0x%x data 0x%llx\n", msr, data);
5753785f 2382 break;
84e0cefa
JS		 2383 case MSR_K7_CLK_CTL:
2384 /*
2385 * Ignore all writes to this no longer documented MSR.
2386 * Writes are only relevant for old K7 processors,
2387 * all pre-dating SVM, but a recommended workaround from
4a969980 2388 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2389 * affected processor models on the command line, hence
2390 * the need to ignore the workaround.
2391 */
2392 break;
55cd8e5a
GN		 2393 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2394 if (kvm_hv_msr_partition_wide(msr)) {
2395 int r;
2396 mutex_lock(&vcpu->kvm->lock);
2397 r = set_msr_hyperv_pw(vcpu, msr, data);
2398 mutex_unlock(&vcpu->kvm->lock);
2399 return r;
2400 } else
2401 return set_msr_hyperv(vcpu, msr, data);
2402 break;
91c9c3ed 2403 case MSR_IA32_BBL_CR_CTL3:
2404 /* Drop writes to this legacy MSR -- see rdmsr
2405 * counterpart for further detail.
2406 */
a737f256 2407 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2408 break;
2b036c6b
BO		 2409 case MSR_AMD64_OSVW_ID_LENGTH:
2410 if (!guest_cpuid_has_osvw(vcpu))
2411 return 1;
2412 vcpu->arch.osvw.length = data;
2413 break;
2414 case MSR_AMD64_OSVW_STATUS:
2415 if (!guest_cpuid_has_osvw(vcpu))
2416 return 1;
2417 vcpu->arch.osvw.status = data;
2418 break;
15c4a640 2419 default:
ffde22ac
ES		 2420 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2421 return xen_hvm_config(vcpu, data);
f5132b01 2422 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2423 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2424 if (!ignore_msrs) {
a737f256
CD		 2425 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2426 msr, data);
ed85c068
AP		 2427 return 1;
2428 } else {
a737f256
CD		 2429 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2430 msr, data);
ed85c068
AP		 2431 break;
2432 }
15c4a640
CO		 2433 }
2434 return 0;
2435}
2436EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2437
2438
2439/*
2440 * Reads an msr value (of 'msr_index') into 'pdata'.
2441 * Returns 0 on success, non-0 otherwise.
2442 * Assumes vcpu_load() was already called.
2443 */
2444int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2445{
2446 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2447}
ff651cb6 2448EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2449
9ba075a6
AK		 2450static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2451{
0bed3b56
SY		 2452 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2453
9ba075a6
AK		 2454 if (!msr_mtrr_valid(msr))
2455 return 1;
2456
0bed3b56
SY		 2457 if (msr == MSR_MTRRdefType)
2458 *pdata = vcpu->arch.mtrr_state.def_type +
2459 (vcpu->arch.mtrr_state.enabled << 10);
2460 else if (msr == MSR_MTRRfix64K_00000)
2461 *pdata = p[0];
2462 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2463 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2464 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2465 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2466 else if (msr == MSR_IA32_CR_PAT)
2467 *pdata = vcpu->arch.pat;
2468 else { /* Variable MTRRs */
2469 int idx, is_mtrr_mask;
2470 u64 *pt;
2471
2472 idx = (msr - 0x200) / 2;
2473 is_mtrr_mask = msr - 0x200 - 2 * idx;
2474 if (!is_mtrr_mask)
2475 pt =
2476 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2477 else
2478 pt =
2479 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2480 *pdata = *pt;
2481 }
2482
9ba075a6
AK		 2483 return 0;
2484}
2485
890ca9ae 2486static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2487{
2488 u64 data;
890ca9ae
HY		 2489 u64 mcg_cap = vcpu->arch.mcg_cap;
2490 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2491
2492 switch (msr) {
15c4a640
CO		 2493 case MSR_IA32_P5_MC_ADDR:
2494 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2495 data = 0;
2496 break;
15c4a640 2497 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2498 data = vcpu->arch.mcg_cap;
2499 break;
c7ac679c 2500 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2501 if (!(mcg_cap & MCG_CTL_P))
2502 return 1;
2503 data = vcpu->arch.mcg_ctl;
2504 break;
2505 case MSR_IA32_MCG_STATUS:
2506 data = vcpu->arch.mcg_status;
2507 break;
2508 default:
2509 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2510 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2511 u32 offset = msr - MSR_IA32_MC0_CTL;
2512 data = vcpu->arch.mce_banks[offset];
2513 break;
2514 }
2515 return 1;
2516 }
2517 *pdata = data;
2518 return 0;
2519}
2520
55cd8e5a
GN		 2521static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2522{
2523 u64 data = 0;
2524 struct kvm *kvm = vcpu->kvm;
2525
2526 switch (msr) {
2527 case HV_X64_MSR_GUEST_OS_ID:
2528 data = kvm->arch.hv_guest_os_id;
2529 break;
2530 case HV_X64_MSR_HYPERCALL:
2531 data = kvm->arch.hv_hypercall;
2532 break;
e984097b
VR		 2533 case HV_X64_MSR_TIME_REF_COUNT: {
2534 data =
2535 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2536 break;
2537 }
2538 case HV_X64_MSR_REFERENCE_TSC:
2539 data = kvm->arch.hv_tsc_page;
2540 break;
55cd8e5a 2541 default:
a737f256 2542 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2543 return 1;
2544 }
2545
2546 *pdata = data;
2547 return 0;
2548}
2549
2550static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2551{
2552 u64 data = 0;
2553
2554 switch (msr) {
2555 case HV_X64_MSR_VP_INDEX: {
2556 int r;
2557 struct kvm_vcpu *v;
684851a1
TY		 2558 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2559 if (v == vcpu) {
55cd8e5a 2560 data = r;
684851a1
TY		 2561 break;
2562 }
2563 }
55cd8e5a
GN		 2564 break;
2565 }
10388a07
GN		 2566 case HV_X64_MSR_EOI:
2567 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2568 case HV_X64_MSR_ICR:
2569 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2570 case HV_X64_MSR_TPR:
2571 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2572 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2573 data = vcpu->arch.hv_vapic;
2574 break;
55cd8e5a 2575 default:
a737f256 2576 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2577 return 1;
2578 }
2579 *pdata = data;
2580 return 0;
2581}
2582
890ca9ae
HY		 2583int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2584{
2585 u64 data;
2586
2587 switch (msr) {
890ca9ae 2588 case MSR_IA32_PLATFORM_ID:
15c4a640 2589 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2590 case MSR_IA32_DEBUGCTLMSR:
2591 case MSR_IA32_LASTBRANCHFROMIP:
2592 case MSR_IA32_LASTBRANCHTOIP:
2593 case MSR_IA32_LASTINTFROMIP:
2594 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2595 case MSR_K8_SYSCFG:
2596 case MSR_K7_HWCR:
61a6bd67 2597 case MSR_VM_HSAVE_PA:
9e699624 2598 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2599 case MSR_K7_EVNTSEL1:
2600 case MSR_K7_EVNTSEL2:
2601 case MSR_K7_EVNTSEL3:
1f3ee616 2602 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2603 case MSR_K7_PERFCTR1:
2604 case MSR_K7_PERFCTR2:
2605 case MSR_K7_PERFCTR3:
1fdbd48c 2606 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2607 case MSR_AMD64_NB_CFG:
f7c6d140 2608 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2609 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2610 data = 0;
2611 break;
5753785f
GN		 2612 case MSR_P6_PERFCTR0:
2613 case MSR_P6_PERFCTR1:
2614 case MSR_P6_EVNTSEL0:
2615 case MSR_P6_EVNTSEL1:
2616 if (kvm_pmu_msr(vcpu, msr))
2617 return kvm_pmu_get_msr(vcpu, msr, pdata);
2618 data = 0;
2619 break;
742bc670
MT		 2620 case MSR_IA32_UCODE_REV:
2621 data = 0x100000000ULL;
2622 break;
9ba075a6
AK		 2623 case MSR_MTRRcap:
2624 data = 0x500 | KVM_NR_VAR_MTRR;
2625 break;
2626 case 0x200 ... 0x2ff:
2627 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2628 case 0xcd: /* fsb frequency */
2629 data = 3;
2630 break;
7b914098
JS		 2631 /*
2632 * MSR_EBC_FREQUENCY_ID
2633 * Conservative value valid for even the basic CPU models.
2634 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2635 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2636 * and 266MHz for model 3, or 4. Set Core Clock
2637 * Frequency to System Bus Frequency Ratio to 1 (bits
2638 * 31:24) even though these are only valid for CPU
2639 * models > 2, however guests may end up dividing or
2640 * multiplying by zero otherwise.
2641 */
2642 case MSR_EBC_FREQUENCY_ID:
2643 data = 1 << 24;
2644 break;
15c4a640
CO		 2645 case MSR_IA32_APICBASE:
2646 data = kvm_get_apic_base(vcpu);
2647 break;
0105d1a5
GN		 2648 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2649 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2650 break;
a3e06bbe
LJ		 2651 case MSR_IA32_TSCDEADLINE:
2652 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2653 break;
ba904635
WA		 2654 case MSR_IA32_TSC_ADJUST:
2655 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2656 break;
15c4a640 2657 case MSR_IA32_MISC_ENABLE:
ad312c7c 2658 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2659 break;
847f0ad8
AG		 2660 case MSR_IA32_PERF_STATUS:
2661 /* TSC increment by tick */
2662 data = 1000ULL;
2663 /* CPU multiplier */
2664 data |= (((uint64_t)4ULL) << 40);
2665 break;
15c4a640 2666 case MSR_EFER:
f6801dff 2667 data = vcpu->arch.efer;
15c4a640 2668 break;
18068523 2669 case MSR_KVM_WALL_CLOCK:
11c6bffa 2670 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2671 data = vcpu->kvm->arch.wall_clock;
2672 break;
2673 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2674 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2675 data = vcpu->arch.time;
2676 break;
344d9588
GN		 2677 case MSR_KVM_ASYNC_PF_EN:
2678 data = vcpu->arch.apf.msr_val;
2679 break;
c9aaa895
GC		 2680 case MSR_KVM_STEAL_TIME:
2681 data = vcpu->arch.st.msr_val;
2682 break;
1d92128f
MT		 2683 case MSR_KVM_PV_EOI_EN:
2684 data = vcpu->arch.pv_eoi.msr_val;
2685 break;
890ca9ae
HY		 2686 case MSR_IA32_P5_MC_ADDR:
2687 case MSR_IA32_P5_MC_TYPE:
2688 case MSR_IA32_MCG_CAP:
2689 case MSR_IA32_MCG_CTL:
2690 case MSR_IA32_MCG_STATUS:
81760dcc 2691 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2692 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2693 case MSR_K7_CLK_CTL:
2694 /*
2695 * Provide expected ramp-up count for K7. All other
2696 * are set to zero, indicating minimum divisors for
2697 * every field.
2698 *
2699 * This prevents guest kernels on AMD host with CPU
2700 * type 6, model 8 and higher from exploding due to
2701 * the rdmsr failing.
2702 */
2703 data = 0x20000000;
2704 break;
55cd8e5a
GN		 2705 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2706 if (kvm_hv_msr_partition_wide(msr)) {
2707 int r;
2708 mutex_lock(&vcpu->kvm->lock);
2709 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2710 mutex_unlock(&vcpu->kvm->lock);
2711 return r;
2712 } else
2713 return get_msr_hyperv(vcpu, msr, pdata);
2714 break;
91c9c3ed 2715 case MSR_IA32_BBL_CR_CTL3:
2716 /* This legacy MSR exists but isn't fully documented in current
2717 * silicon. It is however accessed by winxp in very narrow
2718 * scenarios where it sets bit #19, itself documented as
2719 * a "reserved" bit. Best effort attempt to source coherent
2720 * read data here should the balance of the register be
2721 * interpreted by the guest:
2722 *
2723 * L2 cache control register 3: 64GB range, 256KB size,
2724 * enabled, latency 0x1, configured
2725 */
2726 data = 0xbe702111;
2727 break;
2b036c6b
BO		 2728 case MSR_AMD64_OSVW_ID_LENGTH:
2729 if (!guest_cpuid_has_osvw(vcpu))
2730 return 1;
2731 data = vcpu->arch.osvw.length;
2732 break;
2733 case MSR_AMD64_OSVW_STATUS:
2734 if (!guest_cpuid_has_osvw(vcpu))
2735 return 1;
2736 data = vcpu->arch.osvw.status;
2737 break;
15c4a640 2738 default:
f5132b01
GN		 2739 if (kvm_pmu_msr(vcpu, msr))
2740 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2741 if (!ignore_msrs) {
a737f256 2742 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2743 return 1;
2744 } else {
a737f256 2745 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2746 data = 0;
2747 }
2748 break;
15c4a640
CO		 2749 }
2750 *pdata = data;
2751 return 0;
2752}
2753EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2754
313a3dc7
CO		 2755/*
2756 * Read or write a bunch of msrs. All parameters are kernel addresses.
2757 *
2758 * @return number of msrs set successfully.
2759 */
2760static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2761 struct kvm_msr_entry *entries,
2762 int (*do_msr)(struct kvm_vcpu *vcpu,
2763 unsigned index, u64 *data))
2764{
f656ce01 2765 int i, idx;
313a3dc7 2766
f656ce01 2767 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2768 for (i = 0; i < msrs->nmsrs; ++i)
2769 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2770 break;
f656ce01 2771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2772
313a3dc7
CO		 2773 return i;
2774}
2775
2776/*
2777 * Read or write a bunch of msrs. Parameters are user addresses.
2778 *
2779 * @return number of msrs set successfully.
2780 */
2781static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2782 int (*do_msr)(struct kvm_vcpu *vcpu,
2783 unsigned index, u64 *data),
2784 int writeback)
2785{
2786 struct kvm_msrs msrs;
2787 struct kvm_msr_entry *entries;
2788 int r, n;
2789 unsigned size;
2790
2791 r = -EFAULT;
2792 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2793 goto out;
2794
2795 r = -E2BIG;
2796 if (msrs.nmsrs >= MAX_IO_MSRS)
2797 goto out;
2798
313a3dc7 2799 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2800 entries = memdup_user(user_msrs->entries, size);
2801 if (IS_ERR(entries)) {
2802 r = PTR_ERR(entries);
313a3dc7 2803 goto out;
ff5c2c03 2804 }
313a3dc7
CO		 2805
2806 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2807 if (r < 0)
2808 goto out_free;
2809
2810 r = -EFAULT;
2811 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2812 goto out_free;
2813
2814 r = n;
2815
2816out_free:
7a73c028 2817 kfree(entries);
313a3dc7
CO		 2818out:
2819 return r;
2820}
2821
784aa3d7 2822int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2823{
2824 int r;
2825
2826 switch (ext) {
2827 case KVM_CAP_IRQCHIP:
2828 case KVM_CAP_HLT:
2829 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2830 case KVM_CAP_SET_TSS_ADDR:
07716717 2831 case KVM_CAP_EXT_CPUID:
9c15bb1d 2832 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2833 case KVM_CAP_CLOCKSOURCE:
7837699f 2834 case KVM_CAP_PIT:
a28e4f5a 2835 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2836 case KVM_CAP_MP_STATE:
ed848624 2837 case KVM_CAP_SYNC_MMU:
a355c85c 2838 case KVM_CAP_USER_NMI:
52d939a0 2839 case KVM_CAP_REINJECT_CONTROL:
4925663a 2840 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2841 case KVM_CAP_IOEVENTFD:
f848a5a8 2842 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2843 case KVM_CAP_PIT2:
e9f42757 2844 case KVM_CAP_PIT_STATE2:
b927a3ce 2845 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2846 case KVM_CAP_XEN_HVM:
afbcf7ab 2847 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2848 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2849 case KVM_CAP_HYPERV:
10388a07 2850 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2851 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2852 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2853 case KVM_CAP_DEBUGREGS:
d2be1651 2854 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2855 case KVM_CAP_XSAVE:
344d9588 2856 case KVM_CAP_ASYNC_PF:
92a1f12d 2857 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2858 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2859 case KVM_CAP_READONLY_MEM:
5f66b620 2860 case KVM_CAP_HYPERV_TIME:
100943c5 2861 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2862 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2863 case KVM_CAP_ENABLE_CAP_VM:
2864 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2865#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2866 case KVM_CAP_ASSIGN_DEV_IRQ:
2867 case KVM_CAP_PCI_2_3:
2868#endif
018d00d2
ZX		 2869 r = 1;
2870 break;
542472b5
LV		 2871 case KVM_CAP_COALESCED_MMIO:
2872 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2873 break;
774ead3a
AK		 2874 case KVM_CAP_VAPIC:
2875 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2876 break;
f725230a 2877 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2878 r = KVM_SOFT_MAX_VCPUS;
2879 break;
2880 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2881 r = KVM_MAX_VCPUS;
2882 break;
a988b910 2883 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2884 r = KVM_USER_MEM_SLOTS;
a988b910 2885 break;
a68a6a72
MT		 2886 case KVM_CAP_PV_MMU: /* obsolete */
2887 r = 0;
2f333bcb 2888 break;
4cee4b72 2889#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2890 case KVM_CAP_IOMMU:
a1b60c1c 2891 r = iommu_present(&pci_bus_type);
62c476c7 2892 break;
4cee4b72 2893#endif
890ca9ae
HY		 2894 case KVM_CAP_MCE:
2895 r = KVM_MAX_MCE_BANKS;
2896 break;
2d5b5a66
SY		 2897 case KVM_CAP_XCRS:
2898 r = cpu_has_xsave;
2899 break;
92a1f12d
JR		 2900 case KVM_CAP_TSC_CONTROL:
2901 r = kvm_has_tsc_control;
2902 break;
018d00d2
ZX		 2903 default:
2904 r = 0;
2905 break;
2906 }
2907 return r;
2908
2909}
2910
043405e1
CO		 2911long kvm_arch_dev_ioctl(struct file *filp,
2912 unsigned int ioctl, unsigned long arg)
2913{
2914 void __user *argp = (void __user *)arg;
2915 long r;
2916
2917 switch (ioctl) {
2918 case KVM_GET_MSR_INDEX_LIST: {
2919 struct kvm_msr_list __user *user_msr_list = argp;
2920 struct kvm_msr_list msr_list;
2921 unsigned n;
2922
2923 r = -EFAULT;
2924 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2925 goto out;
2926 n = msr_list.nmsrs;
2927 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2928 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2929 goto out;
2930 r = -E2BIG;
e125e7b6 2931 if (n < msr_list.nmsrs)
043405e1
CO		 2932 goto out;
2933 r = -EFAULT;
2934 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2935 num_msrs_to_save * sizeof(u32)))
2936 goto out;
e125e7b6 2937 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2938 &emulated_msrs,
2939 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2940 goto out;
2941 r = 0;
2942 break;
2943 }
9c15bb1d
BP		 2944 case KVM_GET_SUPPORTED_CPUID:
2945 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2946 struct kvm_cpuid2 __user *cpuid_arg = argp;
2947 struct kvm_cpuid2 cpuid;
2948
2949 r = -EFAULT;
2950 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2951 goto out;
9c15bb1d
BP		 2952
2953 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2954 ioctl);
674eea0f
AK		 2955 if (r)
2956 goto out;
2957
2958 r = -EFAULT;
2959 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2960 goto out;
2961 r = 0;
2962 break;
2963 }
890ca9ae
HY		 2964 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2965 u64 mce_cap;
2966
2967 mce_cap = KVM_MCE_CAP_SUPPORTED;
2968 r = -EFAULT;
2969 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2970 goto out;
2971 r = 0;
2972 break;
2973 }
043405e1
CO		 2974 default:
2975 r = -EINVAL;
2976 }
2977out:
2978 return r;
2979}
2980
f5f48ee1
SY		 2981static void wbinvd_ipi(void *garbage)
2982{
2983 wbinvd();
2984}
2985
2986static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2987{
e0f0bbc5 2988 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2989}
2990
313a3dc7
CO		 2991void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2992{
f5f48ee1
SY		 2993 /* Address WBINVD may be executed by guest */
2994 if (need_emulate_wbinvd(vcpu)) {
2995 if (kvm_x86_ops->has_wbinvd_exit())
2996 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2997 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2998 smp_call_function_single(vcpu->cpu,
2999 wbinvd_ipi, NULL, 1);
3000 }
3001
313a3dc7 3002 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3003
0dd6a6ed
ZA		 3004 /* Apply any externally detected TSC adjustments (due to suspend) */
3005 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3006 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3007 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3008 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3009 }
8f6055cb 3010
48434c20 3011 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 3012 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3013 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3014 if (tsc_delta < 0)
3015 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 3016 if (check_tsc_unstable()) {
b183aa58
ZA		 3017 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
3018 vcpu->arch.last_guest_tsc);
3019 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 3020 vcpu->arch.tsc_catchup = 1;
c285545f 3021 }
d98d07ca
MT		 3022 /*
3023 * On a host with synchronized TSC, there is no need to update
3024 * kvmclock on vcpu->cpu migration
3025 */
3026 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3027 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 3028 if (vcpu->cpu != cpu)
3029 kvm_migrate_timers(vcpu);
e48672fa 3030 vcpu->cpu = cpu;
6b7d7e76 3031 }
c9aaa895
GC		 3032
3033 accumulate_steal_time(vcpu);
3034 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3035}
3036
3037void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3038{
02daab21 3039 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 3040 kvm_put_guest_fpu(vcpu);
6f526ec5 3041 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 3042}
3043
313a3dc7
CO		 3044static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3045 struct kvm_lapic_state *s)
3046{
5a71785d 3047 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 3048 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 3049
3050 return 0;
3051}
3052
3053static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3054 struct kvm_lapic_state *s)
3055{
64eb0620 3056 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 3057 update_cr8_intercept(vcpu);
313a3dc7
CO		 3058
3059 return 0;
3060}
3061
f77bc6a4
ZX		 3062static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3063 struct kvm_interrupt *irq)
3064{
02cdb50f 3065 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3066 return -EINVAL;
3067 if (irqchip_in_kernel(vcpu->kvm))
3068 return -ENXIO;
f77bc6a4 3069
66fd3f7f 3070 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3071 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3072
f77bc6a4
ZX		 3073 return 0;
3074}
3075
c4abb7c9
JK		 3076static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3077{
c4abb7c9 3078 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3079
3080 return 0;
3081}
3082
b209749f
AK		 3083static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3084 struct kvm_tpr_access_ctl *tac)
3085{
3086 if (tac->flags)
3087 return -EINVAL;
3088 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3089 return 0;
3090}
3091
890ca9ae
HY		 3092static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3093 u64 mcg_cap)
3094{
3095 int r;
3096 unsigned bank_num = mcg_cap & 0xff, bank;
3097
3098 r = -EINVAL;
a9e38c3e 3099 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3100 goto out;
3101 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3102 goto out;
3103 r = 0;
3104 vcpu->arch.mcg_cap = mcg_cap;
3105 /* Init IA32_MCG_CTL to all 1s */
3106 if (mcg_cap & MCG_CTL_P)
3107 vcpu->arch.mcg_ctl = ~(u64)0;
3108 /* Init IA32_MCi_CTL to all 1s */
3109 for (bank = 0; bank < bank_num; bank++)
3110 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3111out:
3112 return r;
3113}
3114
3115static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3116 struct kvm_x86_mce *mce)
3117{
3118 u64 mcg_cap = vcpu->arch.mcg_cap;
3119 unsigned bank_num = mcg_cap & 0xff;
3120 u64 *banks = vcpu->arch.mce_banks;
3121
3122 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3123 return -EINVAL;
3124 /*
3125 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3126 * reporting is disabled
3127 */
3128 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3129 vcpu->arch.mcg_ctl != ~(u64)0)
3130 return 0;
3131 banks += 4 * mce->bank;
3132 /*
3133 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3134 * reporting is disabled for the bank
3135 */
3136 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3137 return 0;
3138 if (mce->status & MCI_STATUS_UC) {
3139 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3140 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3141 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3142 return 0;
3143 }
3144 if (banks[1] & MCI_STATUS_VAL)
3145 mce->status |= MCI_STATUS_OVER;
3146 banks[2] = mce->addr;
3147 banks[3] = mce->misc;
3148 vcpu->arch.mcg_status = mce->mcg_status;
3149 banks[1] = mce->status;
3150 kvm_queue_exception(vcpu, MC_VECTOR);
3151 } else if (!(banks[1] & MCI_STATUS_VAL)
3152 || !(banks[1] & MCI_STATUS_UC)) {
3153 if (banks[1] & MCI_STATUS_VAL)
3154 mce->status |= MCI_STATUS_OVER;
3155 banks[2] = mce->addr;
3156 banks[3] = mce->misc;
3157 banks[1] = mce->status;
3158 } else
3159 banks[1] |= MCI_STATUS_OVER;
3160 return 0;
3161}
3162
3cfc3092
JK		 3163static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3164 struct kvm_vcpu_events *events)
3165{
7460fb4a 3166 process_nmi(vcpu);
03b82a30
JK		 3167 events->exception.injected =
3168 vcpu->arch.exception.pending &&
3169 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3170 events->exception.nr = vcpu->arch.exception.nr;
3171 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3172 events->exception.pad = 0;
3cfc3092
JK		 3173 events->exception.error_code = vcpu->arch.exception.error_code;
3174
03b82a30
JK		 3175 events->interrupt.injected =
3176 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3177 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3178 events->interrupt.soft = 0;
37ccdcbe 3179 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3180
3181 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3182 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3183 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3184 events->nmi.pad = 0;
3cfc3092 3185
66450a21 3186 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3187
dab4b911 3188 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3189 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3190 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3191}
3192
3193static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3194 struct kvm_vcpu_events *events)
3195{
dab4b911 3196 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3197 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3198 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3199 return -EINVAL;
3200
7460fb4a 3201 process_nmi(vcpu);
3cfc3092
JK		 3202 vcpu->arch.exception.pending = events->exception.injected;
3203 vcpu->arch.exception.nr = events->exception.nr;
3204 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3205 vcpu->arch.exception.error_code = events->exception.error_code;
3206
3207 vcpu->arch.interrupt.pending = events->interrupt.injected;
3208 vcpu->arch.interrupt.nr = events->interrupt.nr;
3209 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3210 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3211 kvm_x86_ops->set_interrupt_shadow(vcpu,
3212 events->interrupt.shadow);
3cfc3092
JK		 3213
3214 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3215 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3216 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3217 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3218
66450a21
JK		 3219 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3220 kvm_vcpu_has_lapic(vcpu))
3221 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3222
3842d135
AK		 3223 kvm_make_request(KVM_REQ_EVENT, vcpu);
3224
3cfc3092
JK		 3225 return 0;
3226}
3227
a1efbe77
JK		 3228static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3229 struct kvm_debugregs *dbgregs)
3230{
73aaf249
JK		 3231 unsigned long val;
3232
a1efbe77 3233 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3234 kvm_get_dr(vcpu, 6, &val);
73aaf249 3235 dbgregs->dr6 = val;
a1efbe77
JK		 3236 dbgregs->dr7 = vcpu->arch.dr7;
3237 dbgregs->flags = 0;
97e69aa6 3238 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3239}
3240
3241static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3242 struct kvm_debugregs *dbgregs)
3243{
3244 if (dbgregs->flags)
3245 return -EINVAL;
3246
a1efbe77 3247 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3248 kvm_update_dr0123(vcpu);
a1efbe77 3249 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3250 kvm_update_dr6(vcpu);
a1efbe77 3251 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3252 kvm_update_dr7(vcpu);
a1efbe77 3253
a1efbe77
JK		 3254 return 0;
3255}
3256
df1daba7
PB		 3257#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3258
3259static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3260{
3261 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3262 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3263 u64 valid;
3264
3265 /*
3266 * Copy legacy XSAVE area, to avoid complications with CPUID
3267 * leaves 0 and 1 in the loop below.
3268 */
3269 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3270
3271 /* Set XSTATE_BV */
3272 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3273
3274 /*
3275 * Copy each region from the possibly compacted offset to the
3276 * non-compacted offset.
3277 */
3278 valid = xstate_bv & ~XSTATE_FPSSE;
3279 while (valid) {
3280 u64 feature = valid & -valid;
3281 int index = fls64(feature) - 1;
3282 void *src = get_xsave_addr(xsave, feature);
3283
3284 if (src) {
3285 u32 size, offset, ecx, edx;
3286 cpuid_count(XSTATE_CPUID, index,
3287 &size, &offset, &ecx, &edx);
3288 memcpy(dest + offset, src, size);
3289 }
3290
3291 valid -= feature;
3292 }
3293}
3294
3295static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3296{
3297 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3298 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3299 u64 valid;
3300
3301 /*
3302 * Copy legacy XSAVE area, to avoid complications with CPUID
3303 * leaves 0 and 1 in the loop below.
3304 */
3305 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3306
3307 /* Set XSTATE_BV and possibly XCOMP_BV. */
3308 xsave->xsave_hdr.xstate_bv = xstate_bv;
3309 if (cpu_has_xsaves)
3310 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3311
3312 /*
3313 * Copy each region from the non-compacted offset to the
3314 * possibly compacted offset.
3315 */
3316 valid = xstate_bv & ~XSTATE_FPSSE;
3317 while (valid) {
3318 u64 feature = valid & -valid;
3319 int index = fls64(feature) - 1;
3320 void *dest = get_xsave_addr(xsave, feature);
3321
3322 if (dest) {
3323 u32 size, offset, ecx, edx;
3324 cpuid_count(XSTATE_CPUID, index,
3325 &size, &offset, &ecx, &edx);
3326 memcpy(dest, src + offset, size);
3327 } else
3328 WARN_ON_ONCE(1);
3329
3330 valid -= feature;
3331 }
3332}
3333
2d5b5a66
SY		 3334static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3335 struct kvm_xsave *guest_xsave)
3336{
4344ee98 3337 if (cpu_has_xsave) {
df1daba7
PB		 3338 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3339 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3340 } else {
2d5b5a66
SY		 3341 memcpy(guest_xsave->region,
3342 &vcpu->arch.guest_fpu.state->fxsave,
3343 sizeof(struct i387_fxsave_struct));
3344 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3345 XSTATE_FPSSE;
3346 }
3347}
3348
3349static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3350 struct kvm_xsave *guest_xsave)
3351{
3352 u64 xstate_bv =
3353 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3354
d7876f1b
PB		 3355 if (cpu_has_xsave) {
3356 /*
3357 * Here we allow setting states that are not present in
3358 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3359 * with old userspace.
3360 */
4ff41732 3361 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3362 return -EINVAL;
df1daba7 3363 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3364 } else {
2d5b5a66
SY		 3365 if (xstate_bv & ~XSTATE_FPSSE)
3366 return -EINVAL;
3367 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3368 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3369 }
3370 return 0;
3371}
3372
3373static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3374 struct kvm_xcrs *guest_xcrs)
3375{
3376 if (!cpu_has_xsave) {
3377 guest_xcrs->nr_xcrs = 0;
3378 return;
3379 }
3380
3381 guest_xcrs->nr_xcrs = 1;
3382 guest_xcrs->flags = 0;
3383 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3384 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3385}
3386
3387static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3388 struct kvm_xcrs *guest_xcrs)
3389{
3390 int i, r = 0;
3391
3392 if (!cpu_has_xsave)
3393 return -EINVAL;
3394
3395 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3396 return -EINVAL;
3397
3398 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3399 /* Only support XCR0 currently */
c67a04cb 3400 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3401 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3402 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3403 break;
3404 }
3405 if (r)
3406 r = -EINVAL;
3407 return r;
3408}
3409
1c0b28c2
EM		 3410/*
3411 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3412 * stopped by the hypervisor. This function will be called from the host only.
3413 * EINVAL is returned when the host attempts to set the flag for a guest that
3414 * does not support pv clocks.
3415 */
3416static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3417{
0b79459b 3418 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3419 return -EINVAL;
51d59c6b 3420 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3421 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3422 return 0;
3423}
3424
313a3dc7
CO		 3425long kvm_arch_vcpu_ioctl(struct file *filp,
3426 unsigned int ioctl, unsigned long arg)
3427{
3428 struct kvm_vcpu *vcpu = filp->private_data;
3429 void __user *argp = (void __user *)arg;
3430 int r;
d1ac91d8
AK		 3431 union {
3432 struct kvm_lapic_state *lapic;
3433 struct kvm_xsave *xsave;
3434 struct kvm_xcrs *xcrs;
3435 void *buffer;
3436 } u;
3437
3438 u.buffer = NULL;
313a3dc7
CO		 3439 switch (ioctl) {
3440 case KVM_GET_LAPIC: {
2204ae3c
MT		 3441 r = -EINVAL;
3442 if (!vcpu->arch.apic)
3443 goto out;
d1ac91d8 3444 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3445
b772ff36 3446 r = -ENOMEM;
d1ac91d8 3447 if (!u.lapic)
b772ff36 3448 goto out;
d1ac91d8 3449 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3450 if (r)
3451 goto out;
3452 r = -EFAULT;
d1ac91d8 3453 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3454 goto out;
3455 r = 0;
3456 break;
3457 }
3458 case KVM_SET_LAPIC: {
2204ae3c
MT		 3459 r = -EINVAL;
3460 if (!vcpu->arch.apic)
3461 goto out;
ff5c2c03 3462 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3463 if (IS_ERR(u.lapic))
3464 return PTR_ERR(u.lapic);
ff5c2c03 3465
d1ac91d8 3466 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3467 break;
3468 }
f77bc6a4
ZX		 3469 case KVM_INTERRUPT: {
3470 struct kvm_interrupt irq;
3471
3472 r = -EFAULT;
3473 if (copy_from_user(&irq, argp, sizeof irq))
3474 goto out;
3475 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3476 break;
3477 }
c4abb7c9
JK		 3478 case KVM_NMI: {
3479 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3480 break;
3481 }
313a3dc7
CO		 3482 case KVM_SET_CPUID: {
3483 struct kvm_cpuid __user *cpuid_arg = argp;
3484 struct kvm_cpuid cpuid;
3485
3486 r = -EFAULT;
3487 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3488 goto out;
3489 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3490 break;
3491 }
07716717
DK		 3492 case KVM_SET_CPUID2: {
3493 struct kvm_cpuid2 __user *cpuid_arg = argp;
3494 struct kvm_cpuid2 cpuid;
3495
3496 r = -EFAULT;
3497 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3498 goto out;
3499 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3500 cpuid_arg->entries);
07716717
DK		 3501 break;
3502 }
3503 case KVM_GET_CPUID2: {
3504 struct kvm_cpuid2 __user *cpuid_arg = argp;
3505 struct kvm_cpuid2 cpuid;
3506
3507 r = -EFAULT;
3508 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3509 goto out;
3510 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3511 cpuid_arg->entries);
07716717
DK		 3512 if (r)
3513 goto out;
3514 r = -EFAULT;
3515 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3516 goto out;
3517 r = 0;
3518 break;
3519 }
313a3dc7
CO		 3520 case KVM_GET_MSRS:
3521 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3522 break;
3523 case KVM_SET_MSRS:
3524 r = msr_io(vcpu, argp, do_set_msr, 0);
3525 break;
b209749f
AK		 3526 case KVM_TPR_ACCESS_REPORTING: {
3527 struct kvm_tpr_access_ctl tac;
3528
3529 r = -EFAULT;
3530 if (copy_from_user(&tac, argp, sizeof tac))
3531 goto out;
3532 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3533 if (r)
3534 goto out;
3535 r = -EFAULT;
3536 if (copy_to_user(argp, &tac, sizeof tac))
3537 goto out;
3538 r = 0;
3539 break;
3540 };
b93463aa
AK		 3541 case KVM_SET_VAPIC_ADDR: {
3542 struct kvm_vapic_addr va;
3543
3544 r = -EINVAL;
3545 if (!irqchip_in_kernel(vcpu->kvm))
3546 goto out;
3547 r = -EFAULT;
3548 if (copy_from_user(&va, argp, sizeof va))
3549 goto out;
fda4e2e8 3550 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3551 break;
3552 }
890ca9ae
HY		 3553 case KVM_X86_SETUP_MCE: {
3554 u64 mcg_cap;
3555
3556 r = -EFAULT;
3557 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3558 goto out;
3559 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3560 break;
3561 }
3562 case KVM_X86_SET_MCE: {
3563 struct kvm_x86_mce mce;
3564
3565 r = -EFAULT;
3566 if (copy_from_user(&mce, argp, sizeof mce))
3567 goto out;
3568 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3569 break;
3570 }
3cfc3092
JK		 3571 case KVM_GET_VCPU_EVENTS: {
3572 struct kvm_vcpu_events events;
3573
3574 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3575
3576 r = -EFAULT;
3577 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3578 break;
3579 r = 0;
3580 break;
3581 }
3582 case KVM_SET_VCPU_EVENTS: {
3583 struct kvm_vcpu_events events;
3584
3585 r = -EFAULT;
3586 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3587 break;
3588
3589 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3590 break;
3591 }
a1efbe77
JK		 3592 case KVM_GET_DEBUGREGS: {
3593 struct kvm_debugregs dbgregs;
3594
3595 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3596
3597 r = -EFAULT;
3598 if (copy_to_user(argp, &dbgregs,
3599 sizeof(struct kvm_debugregs)))
3600 break;
3601 r = 0;
3602 break;
3603 }
3604 case KVM_SET_DEBUGREGS: {
3605 struct kvm_debugregs dbgregs;
3606
3607 r = -EFAULT;
3608 if (copy_from_user(&dbgregs, argp,
3609 sizeof(struct kvm_debugregs)))
3610 break;
3611
3612 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3613 break;
3614 }
2d5b5a66 3615 case KVM_GET_XSAVE: {
d1ac91d8 3616 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3617 r = -ENOMEM;
d1ac91d8 3618 if (!u.xsave)
2d5b5a66
SY		 3619 break;
3620
d1ac91d8 3621 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3622
3623 r = -EFAULT;
d1ac91d8 3624 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3625 break;
3626 r = 0;
3627 break;
3628 }
3629 case KVM_SET_XSAVE: {
ff5c2c03 3630 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3631 if (IS_ERR(u.xsave))
3632 return PTR_ERR(u.xsave);
2d5b5a66 3633
d1ac91d8 3634 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3635 break;
3636 }
3637 case KVM_GET_XCRS: {
d1ac91d8 3638 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3639 r = -ENOMEM;
d1ac91d8 3640 if (!u.xcrs)
2d5b5a66
SY		 3641 break;
3642
d1ac91d8 3643 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3644
3645 r = -EFAULT;
d1ac91d8 3646 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3647 sizeof(struct kvm_xcrs)))
3648 break;
3649 r = 0;
3650 break;
3651 }
3652 case KVM_SET_XCRS: {
ff5c2c03 3653 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3654 if (IS_ERR(u.xcrs))
3655 return PTR_ERR(u.xcrs);
2d5b5a66 3656
d1ac91d8 3657 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3658 break;
3659 }
92a1f12d
JR		 3660 case KVM_SET_TSC_KHZ: {
3661 u32 user_tsc_khz;
3662
3663 r = -EINVAL;
92a1f12d
JR		 3664 user_tsc_khz = (u32)arg;
3665
3666 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3667 goto out;
3668
cc578287
ZA		 3669 if (user_tsc_khz == 0)
3670 user_tsc_khz = tsc_khz;
3671
3672 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3673
3674 r = 0;
3675 goto out;
3676 }
3677 case KVM_GET_TSC_KHZ: {
cc578287 3678 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3679 goto out;
3680 }
1c0b28c2
EM		 3681 case KVM_KVMCLOCK_CTRL: {
3682 r = kvm_set_guest_paused(vcpu);
3683 goto out;
3684 }
313a3dc7
CO		 3685 default:
3686 r = -EINVAL;
3687 }
3688out:
d1ac91d8 3689 kfree(u.buffer);
313a3dc7
CO		 3690 return r;
3691}
3692
5b1c1493
CO		 3693int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3694{
3695 return VM_FAULT_SIGBUS;
3696}
3697
1fe779f8
CO		 3698static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3699{
3700 int ret;
3701
3702 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3703 return -EINVAL;
1fe779f8
CO		 3704 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3705 return ret;
3706}
3707
b927a3ce
SY		 3708static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3709 u64 ident_addr)
3710{
3711 kvm->arch.ept_identity_map_addr = ident_addr;
3712 return 0;
3713}
3714
1fe779f8
CO		 3715static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3716 u32 kvm_nr_mmu_pages)
3717{
3718 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3719 return -EINVAL;
3720
79fac95e 3721 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3722
3723 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3724 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3725
79fac95e 3726 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3727 return 0;
3728}
3729
3730static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3731{
39de71ec 3732 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3733}
3734
1fe779f8
CO		 3735static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3736{
3737 int r;
3738
3739 r = 0;
3740 switch (chip->chip_id) {
3741 case KVM_IRQCHIP_PIC_MASTER:
3742 memcpy(&chip->chip.pic,
3743 &pic_irqchip(kvm)->pics[0],
3744 sizeof(struct kvm_pic_state));
3745 break;
3746 case KVM_IRQCHIP_PIC_SLAVE:
3747 memcpy(&chip->chip.pic,
3748 &pic_irqchip(kvm)->pics[1],
3749 sizeof(struct kvm_pic_state));
3750 break;
3751 case KVM_IRQCHIP_IOAPIC:
eba0226b 3752 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3753 break;
3754 default:
3755 r = -EINVAL;
3756 break;
3757 }
3758 return r;
3759}
3760
3761static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3762{
3763 int r;
3764
3765 r = 0;
3766 switch (chip->chip_id) {
3767 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3768 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3769 memcpy(&pic_irqchip(kvm)->pics[0],
3770 &chip->chip.pic,
3771 sizeof(struct kvm_pic_state));
f4f51050 3772 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3773 break;
3774 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3775 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3776 memcpy(&pic_irqchip(kvm)->pics[1],
3777 &chip->chip.pic,
3778 sizeof(struct kvm_pic_state));
f4f51050 3779 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3780 break;
3781 case KVM_IRQCHIP_IOAPIC:
eba0226b 3782 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3783 break;
3784 default:
3785 r = -EINVAL;
3786 break;
3787 }
3788 kvm_pic_update_irq(pic_irqchip(kvm));
3789 return r;
3790}
3791
e0f63cb9
SY		 3792static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3793{
3794 int r = 0;
3795
894a9c55 3796 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3797 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3798 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3799 return r;
3800}
3801
3802static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3803{
3804 int r = 0;
3805
894a9c55 3806 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3807 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3808 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3809 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3810 return r;
3811}
3812
3813static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3814{
3815 int r = 0;
3816
3817 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3818 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3819 sizeof(ps->channels));
3820 ps->flags = kvm->arch.vpit->pit_state.flags;
3821 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3822 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3823 return r;
3824}
3825
3826static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3827{
3828 int r = 0, start = 0;
3829 u32 prev_legacy, cur_legacy;
3830 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3831 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3832 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3833 if (!prev_legacy && cur_legacy)
3834 start = 1;
3835 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3836 sizeof(kvm->arch.vpit->pit_state.channels));
3837 kvm->arch.vpit->pit_state.flags = ps->flags;
3838 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3839 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3840 return r;
3841}
3842
52d939a0
MT		 3843static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3844 struct kvm_reinject_control *control)
3845{
3846 if (!kvm->arch.vpit)
3847 return -ENXIO;
894a9c55 3848 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3849 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3850 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3851 return 0;
3852}
3853
95d4c16c 3854/**
60c34612
TY		 3855 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3856 * @kvm: kvm instance
3857 * @log: slot id and address to which we copy the log
95d4c16c 3858 *
e108ff2f
PB		 3859 * Steps 1-4 below provide general overview of dirty page logging. See
3860 * kvm_get_dirty_log_protect() function description for additional details.
3861 *
3862 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3863 * always flush the TLB (step 4) even if previous step failed and the dirty
3864 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3865 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3866 * writes will be marked dirty for next log read.
95d4c16c 3867 *
60c34612
TY		 3868 * 1. Take a snapshot of the bit and clear it if needed.
3869 * 2. Write protect the corresponding page.
e108ff2f
PB		 3870 * 3. Copy the snapshot to the userspace.
3871 * 4. Flush TLB's if needed.
5bb064dc 3872 */
60c34612 3873int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3874{
60c34612 3875 bool is_dirty = false;
e108ff2f 3876 int r;
5bb064dc 3877
79fac95e 3878 mutex_lock(&kvm->slots_lock);
5bb064dc 3879
88178fd4
KH		 3880 /*
3881 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3882 */
3883 if (kvm_x86_ops->flush_log_dirty)
3884 kvm_x86_ops->flush_log_dirty(kvm);
3885
e108ff2f 3886 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3887
3888 /*
3889 * All the TLBs can be flushed out of mmu lock, see the comments in
3890 * kvm_mmu_slot_remove_write_access().
3891 */
e108ff2f 3892 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3893 if (is_dirty)
3894 kvm_flush_remote_tlbs(kvm);
3895
79fac95e 3896 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3897 return r;
3898}
3899
aa2fbe6d
YZ		 3900int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3901 bool line_status)
23d43cf9
CD		 3902{
3903 if (!irqchip_in_kernel(kvm))
3904 return -ENXIO;
3905
3906 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3907 irq_event->irq, irq_event->level,
3908 line_status);
23d43cf9
CD		 3909 return 0;
3910}
3911
90de4a18
NA		 3912static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3913 struct kvm_enable_cap *cap)
3914{
3915 int r;
3916
3917 if (cap->flags)
3918 return -EINVAL;
3919
3920 switch (cap->cap) {
3921 case KVM_CAP_DISABLE_QUIRKS:
3922 kvm->arch.disabled_quirks = cap->args[0];
3923 r = 0;
3924 break;
3925 default:
3926 r = -EINVAL;
3927 break;
3928 }
3929 return r;
3930}
3931
1fe779f8
CO		 3932long kvm_arch_vm_ioctl(struct file *filp,
3933 unsigned int ioctl, unsigned long arg)
3934{
3935 struct kvm *kvm = filp->private_data;
3936 void __user *argp = (void __user *)arg;
367e1319 3937 int r = -ENOTTY;
f0d66275
DH		 3938 /*
3939 * This union makes it completely explicit to gcc-3.x
3940 * that these two variables' stack usage should be
3941 * combined, not added together.
3942 */
3943 union {
3944 struct kvm_pit_state ps;
e9f42757 3945 struct kvm_pit_state2 ps2;
c5ff41ce 3946 struct kvm_pit_config pit_config;
f0d66275 3947 } u;
1fe779f8
CO		 3948
3949 switch (ioctl) {
3950 case KVM_SET_TSS_ADDR:
3951 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3952 break;
b927a3ce
SY		 3953 case KVM_SET_IDENTITY_MAP_ADDR: {
3954 u64 ident_addr;
3955
3956 r = -EFAULT;
3957 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3958 goto out;
3959 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3960 break;
3961 }
1fe779f8
CO		 3962 case KVM_SET_NR_MMU_PAGES:
3963 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3964 break;
3965 case KVM_GET_NR_MMU_PAGES:
3966 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3967 break;
3ddea128
MT		 3968 case KVM_CREATE_IRQCHIP: {
3969 struct kvm_pic *vpic;
3970
3971 mutex_lock(&kvm->lock);
3972 r = -EEXIST;
3973 if (kvm->arch.vpic)
3974 goto create_irqchip_unlock;
3e515705
AK		 3975 r = -EINVAL;
3976 if (atomic_read(&kvm->online_vcpus))
3977 goto create_irqchip_unlock;
1fe779f8 3978 r = -ENOMEM;
3ddea128
MT		 3979 vpic = kvm_create_pic(kvm);
3980 if (vpic) {
1fe779f8
CO		 3981 r = kvm_ioapic_init(kvm);
3982 if (r) {
175504cd 3983 mutex_lock(&kvm->slots_lock);
72bb2fcd 3984 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3985 &vpic->dev_master);
3986 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3987 &vpic->dev_slave);
3988 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3989 &vpic->dev_eclr);
175504cd 3990 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3991 kfree(vpic);
3992 goto create_irqchip_unlock;
1fe779f8
CO		 3993 }
3994 } else
3ddea128
MT		 3995 goto create_irqchip_unlock;
3996 smp_wmb();
3997 kvm->arch.vpic = vpic;
3998 smp_wmb();
399ec807
AK		 3999 r = kvm_setup_default_irq_routing(kvm);
4000 if (r) {
175504cd 4001 mutex_lock(&kvm->slots_lock);
3ddea128 4002 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 4003 kvm_ioapic_destroy(kvm);
4004 kvm_destroy_pic(kvm);
3ddea128 4005 mutex_unlock(&kvm->irq_lock);
175504cd 4006 mutex_unlock(&kvm->slots_lock);
399ec807 4007 }
3ddea128
MT		 4008 create_irqchip_unlock:
4009 mutex_unlock(&kvm->lock);
1fe779f8 4010 break;
3ddea128 4011 }
7837699f 4012 case KVM_CREATE_PIT:
c5ff41ce
JK		 4013 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4014 goto create_pit;
4015 case KVM_CREATE_PIT2:
4016 r = -EFAULT;
4017 if (copy_from_user(&u.pit_config, argp,
4018 sizeof(struct kvm_pit_config)))
4019 goto out;
4020 create_pit:
79fac95e 4021 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 4022 r = -EEXIST;
4023 if (kvm->arch.vpit)
4024 goto create_pit_unlock;
7837699f 4025 r = -ENOMEM;
c5ff41ce 4026 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4027 if (kvm->arch.vpit)
4028 r = 0;
269e05e4 4029 create_pit_unlock:
79fac95e 4030 mutex_unlock(&kvm->slots_lock);
7837699f 4031 break;
1fe779f8
CO		 4032 case KVM_GET_IRQCHIP: {
4033 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4034 struct kvm_irqchip *chip;
1fe779f8 4035
ff5c2c03
SL		 4036 chip = memdup_user(argp, sizeof(*chip));
4037 if (IS_ERR(chip)) {
4038 r = PTR_ERR(chip);
1fe779f8 4039 goto out;
ff5c2c03
SL		 4040 }
4041
1fe779f8
CO		 4042 r = -ENXIO;
4043 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4044 goto get_irqchip_out;
4045 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4046 if (r)
f0d66275 4047 goto get_irqchip_out;
1fe779f8 4048 r = -EFAULT;
f0d66275
DH		 4049 if (copy_to_user(argp, chip, sizeof *chip))
4050 goto get_irqchip_out;
1fe779f8 4051 r = 0;
f0d66275
DH		 4052 get_irqchip_out:
4053 kfree(chip);
1fe779f8
CO		 4054 break;
4055 }
4056 case KVM_SET_IRQCHIP: {
4057 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4058 struct kvm_irqchip *chip;
1fe779f8 4059
ff5c2c03
SL		 4060 chip = memdup_user(argp, sizeof(*chip));
4061 if (IS_ERR(chip)) {
4062 r = PTR_ERR(chip);
1fe779f8 4063 goto out;
ff5c2c03
SL		 4064 }
4065
1fe779f8
CO		 4066 r = -ENXIO;
4067 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4068 goto set_irqchip_out;
4069 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4070 if (r)
f0d66275 4071 goto set_irqchip_out;
1fe779f8 4072 r = 0;
f0d66275
DH		 4073 set_irqchip_out:
4074 kfree(chip);
1fe779f8
CO		 4075 break;
4076 }
e0f63cb9 4077 case KVM_GET_PIT: {
e0f63cb9 4078 r = -EFAULT;
f0d66275 4079 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4080 goto out;
4081 r = -ENXIO;
4082 if (!kvm->arch.vpit)
4083 goto out;
f0d66275 4084 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4085 if (r)
4086 goto out;
4087 r = -EFAULT;
f0d66275 4088 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4089 goto out;
4090 r = 0;
4091 break;
4092 }
4093 case KVM_SET_PIT: {
e0f63cb9 4094 r = -EFAULT;
f0d66275 4095 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4096 goto out;
4097 r = -ENXIO;
4098 if (!kvm->arch.vpit)
4099 goto out;
f0d66275 4100 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4101 break;
4102 }
e9f42757
BK		 4103 case KVM_GET_PIT2: {
4104 r = -ENXIO;
4105 if (!kvm->arch.vpit)
4106 goto out;
4107 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4108 if (r)
4109 goto out;
4110 r = -EFAULT;
4111 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4112 goto out;
4113 r = 0;
4114 break;
4115 }
4116 case KVM_SET_PIT2: {
4117 r = -EFAULT;
4118 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4119 goto out;
4120 r = -ENXIO;
4121 if (!kvm->arch.vpit)
4122 goto out;
4123 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4124 break;
4125 }
52d939a0
MT		 4126 case KVM_REINJECT_CONTROL: {
4127 struct kvm_reinject_control control;
4128 r = -EFAULT;
4129 if (copy_from_user(&control, argp, sizeof(control)))
4130 goto out;
4131 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4132 break;
4133 }
ffde22ac
ES		 4134 case KVM_XEN_HVM_CONFIG: {
4135 r = -EFAULT;
4136 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4137 sizeof(struct kvm_xen_hvm_config)))
4138 goto out;
4139 r = -EINVAL;
4140 if (kvm->arch.xen_hvm_config.flags)
4141 goto out;
4142 r = 0;
4143 break;
4144 }
afbcf7ab 4145 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4146 struct kvm_clock_data user_ns;
4147 u64 now_ns;
4148 s64 delta;
4149
4150 r = -EFAULT;
4151 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4152 goto out;
4153
4154 r = -EINVAL;
4155 if (user_ns.flags)
4156 goto out;
4157
4158 r = 0;
395c6b0a 4159 local_irq_disable();
759379dd 4160 now_ns = get_kernel_ns();
afbcf7ab 4161 delta = user_ns.clock - now_ns;
395c6b0a 4162 local_irq_enable();
afbcf7ab 4163 kvm->arch.kvmclock_offset = delta;
2e762ff7 4164 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4165 break;
4166 }
4167 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4168 struct kvm_clock_data user_ns;
4169 u64 now_ns;
4170
395c6b0a 4171 local_irq_disable();
759379dd 4172 now_ns = get_kernel_ns();
afbcf7ab 4173 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4174 local_irq_enable();
afbcf7ab 4175 user_ns.flags = 0;
97e69aa6 4176 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4177
4178 r = -EFAULT;
4179 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4180 goto out;
4181 r = 0;
4182 break;
4183 }
90de4a18
NA		 4184 case KVM_ENABLE_CAP: {
4185 struct kvm_enable_cap cap;
afbcf7ab 4186
90de4a18
NA		 4187 r = -EFAULT;
4188 if (copy_from_user(&cap, argp, sizeof(cap)))
4189 goto out;
4190 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4191 break;
4192 }
1fe779f8 4193 default:
c274e03a 4194 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4195 }
4196out:
4197 return r;
4198}
4199
a16b043c 4200static void kvm_init_msr_list(void)
043405e1
CO		 4201{
4202 u32 dummy[2];
4203 unsigned i, j;
4204
e3267cbb
GC		 4205 /* skip the first msrs in the list. KVM-specific */
4206 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4207 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4208 continue;
93c4adc7
PB		 4209
4210 /*
4211 * Even MSRs that are valid in the host may not be exposed
4212 * to the guests in some cases. We could work around this
4213 * in VMX with the generic MSR save/load machinery, but it
4214 * is not really worthwhile since it will really only
4215 * happen with nested virtualization.
4216 */
4217 switch (msrs_to_save[i]) {
4218 case MSR_IA32_BNDCFGS:
4219 if (!kvm_x86_ops->mpx_supported())
4220 continue;
4221 break;
4222 default:
4223 break;
4224 }
4225
043405e1
CO		 4226 if (j < i)
4227 msrs_to_save[j] = msrs_to_save[i];
4228 j++;
4229 }
4230 num_msrs_to_save = j;
4231}
4232
bda9020e
MT		 4233static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4234 const void *v)
bbd9b64e 4235{
70252a10
AK		 4236 int handled = 0;
4237 int n;
4238
4239 do {
4240 n = min(len, 8);
4241 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4242 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4243 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4244 break;
4245 handled += n;
4246 addr += n;
4247 len -= n;
4248 v += n;
4249 } while (len);
bbd9b64e 4250
70252a10 4251 return handled;
bbd9b64e
CO		 4252}
4253
bda9020e 4254static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4255{
70252a10
AK		 4256 int handled = 0;
4257 int n;
4258
4259 do {
4260 n = min(len, 8);
4261 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4262 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4263 addr, n, v))
4264 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4265 break;
4266 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4267 handled += n;
4268 addr += n;
4269 len -= n;
4270 v += n;
4271 } while (len);
bbd9b64e 4272
70252a10 4273 return handled;
bbd9b64e
CO		 4274}
4275
2dafc6c2
GN		 4276static void kvm_set_segment(struct kvm_vcpu *vcpu,
4277 struct kvm_segment *var, int seg)
4278{
4279 kvm_x86_ops->set_segment(vcpu, var, seg);
4280}
4281
4282void kvm_get_segment(struct kvm_vcpu *vcpu,
4283 struct kvm_segment *var, int seg)
4284{
4285 kvm_x86_ops->get_segment(vcpu, var, seg);
4286}
4287
54987b7a
PB		 4288gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4289 struct x86_exception *exception)
02f59dc9
JR		 4290{
4291 gpa_t t_gpa;
02f59dc9
JR		 4292
4293 BUG_ON(!mmu_is_nested(vcpu));
4294
4295 /* NPT walks are always user-walks */
4296 access |= PFERR_USER_MASK;
54987b7a 4297 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4298
4299 return t_gpa;
4300}
4301
ab9ae313
AK		 4302gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4303 struct x86_exception *exception)
1871c602
GN		 4304{
4305 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4306 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4307}
4308
ab9ae313
AK		 4309 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4310 struct x86_exception *exception)
1871c602
GN		 4311{
4312 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4313 access |= PFERR_FETCH_MASK;
ab9ae313 4314 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4315}
4316
ab9ae313
AK		 4317gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4318 struct x86_exception *exception)
1871c602
GN		 4319{
4320 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4321 access |= PFERR_WRITE_MASK;
ab9ae313 4322 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4323}
4324
4325/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4326gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4327 struct x86_exception *exception)
1871c602 4328{
ab9ae313 4329 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4330}
4331
4332static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4333 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4334 struct x86_exception *exception)
bbd9b64e
CO		 4335{
4336 void *data = val;
10589a46 4337 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4338
4339 while (bytes) {
14dfe855 4340 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4341 exception);
bbd9b64e 4342 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4343 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4344 int ret;
4345
bcc55cba 4346 if (gpa == UNMAPPED_GVA)
ab9ae313 4347 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4348 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4349 offset, toread);
10589a46 4350 if (ret < 0) {
c3cd7ffa 4351 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4352 goto out;
4353 }
bbd9b64e 4354
77c2002e
IE		 4355 bytes -= toread;
4356 data += toread;
4357 addr += toread;
bbd9b64e 4358 }
10589a46 4359out:
10589a46 4360 return r;
bbd9b64e 4361}
77c2002e 4362
1871c602 4363/* used for instruction fetching */
0f65dd70
AK		 4364static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4365 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4366 struct x86_exception *exception)
1871c602 4367{
0f65dd70 4368 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4369 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4370 unsigned offset;
4371 int ret;
0f65dd70 4372
44583cba
PB		 4373 /* Inline kvm_read_guest_virt_helper for speed. */
4374 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4375 exception);
4376 if (unlikely(gpa == UNMAPPED_GVA))
4377 return X86EMUL_PROPAGATE_FAULT;
4378
4379 offset = addr & (PAGE_SIZE-1);
4380 if (WARN_ON(offset + bytes > PAGE_SIZE))
4381 bytes = (unsigned)PAGE_SIZE - offset;
4382 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4383 offset, bytes);
4384 if (unlikely(ret < 0))
4385 return X86EMUL_IO_NEEDED;
4386
4387 return X86EMUL_CONTINUE;
1871c602
GN		 4388}
4389
064aea77 4390int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4391 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4392 struct x86_exception *exception)
1871c602 4393{
0f65dd70 4394 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4395 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4396
1871c602 4397 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4398 exception);
1871c602 4399}
064aea77 4400EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4401
0f65dd70
AK		 4402static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4403 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4404 struct x86_exception *exception)
1871c602 4405{
0f65dd70 4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4407 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4408}
4409
6a4d7550 4410int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4411 gva_t addr, void *val,
2dafc6c2 4412 unsigned int bytes,
bcc55cba 4413 struct x86_exception *exception)
77c2002e 4414{
0f65dd70 4415 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4416 void *data = val;
4417 int r = X86EMUL_CONTINUE;
4418
4419 while (bytes) {
14dfe855
JR		 4420 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4421 PFERR_WRITE_MASK,
ab9ae313 4422 exception);
77c2002e
IE		 4423 unsigned offset = addr & (PAGE_SIZE-1);
4424 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4425 int ret;
4426
bcc55cba 4427 if (gpa == UNMAPPED_GVA)
ab9ae313 4428 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4429 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4430 if (ret < 0) {
c3cd7ffa 4431 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4432 goto out;
4433 }
4434
4435 bytes -= towrite;
4436 data += towrite;
4437 addr += towrite;
4438 }
4439out:
4440 return r;
4441}
6a4d7550 4442EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4443
af7cc7d1
XG		 4444static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4445 gpa_t *gpa, struct x86_exception *exception,
4446 bool write)
4447{
97d64b78
AK		 4448 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4449 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4450
97d64b78 4451 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4452 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4453 vcpu->arch.access, access)) {
bebb106a
XG		 4454 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4455 (gva & (PAGE_SIZE - 1));
4f022648 4456 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4457 return 1;
4458 }
4459
af7cc7d1
XG		 4460 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4461
4462 if (*gpa == UNMAPPED_GVA)
4463 return -1;
4464
4465 /* For APIC access vmexit */
4466 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4467 return 1;
4468
4f022648
XG		 4469 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4470 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4471 return 1;
4f022648 4472 }
bebb106a 4473
af7cc7d1
XG		 4474 return 0;
4475}
4476
3200f405 4477int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4478 const void *val, int bytes)
bbd9b64e
CO		 4479{
4480 int ret;
4481
4482 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4483 if (ret < 0)
bbd9b64e 4484 return 0;
f57f2ef5 4485 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4486 return 1;
4487}
4488
77d197b2
XG		 4489struct read_write_emulator_ops {
4490 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4491 int bytes);
4492 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4493 void *val, int bytes);
4494 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4495 int bytes, void *val);
4496 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4497 void *val, int bytes);
4498 bool write;
4499};
4500
4501static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4502{
4503 if (vcpu->mmio_read_completed) {
77d197b2 4504 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4505 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4506 vcpu->mmio_read_completed = 0;
4507 return 1;
4508 }
4509
4510 return 0;
4511}
4512
4513static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4514 void *val, int bytes)
4515{
4516 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4517}
4518
4519static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4520 void *val, int bytes)
4521{
4522 return emulator_write_phys(vcpu, gpa, val, bytes);
4523}
4524
4525static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4526{
4527 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4528 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4529}
4530
4531static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4532 void *val, int bytes)
4533{
4534 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4535 return X86EMUL_IO_NEEDED;
4536}
4537
4538static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4539 void *val, int bytes)
4540{
f78146b0
AK		 4541 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4542
87da7e66 4543 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4544 return X86EMUL_CONTINUE;
4545}
4546
0fbe9b0b 4547static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4548 .read_write_prepare = read_prepare,
4549 .read_write_emulate = read_emulate,
4550 .read_write_mmio = vcpu_mmio_read,
4551 .read_write_exit_mmio = read_exit_mmio,
4552};
4553
0fbe9b0b 4554static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4555 .read_write_emulate = write_emulate,
4556 .read_write_mmio = write_mmio,
4557 .read_write_exit_mmio = write_exit_mmio,
4558 .write = true,
4559};
4560
22388a3c
XG		 4561static int emulator_read_write_onepage(unsigned long addr, void *val,
4562 unsigned int bytes,
4563 struct x86_exception *exception,
4564 struct kvm_vcpu *vcpu,
0fbe9b0b 4565 const struct read_write_emulator_ops *ops)
bbd9b64e 4566{
af7cc7d1
XG		 4567 gpa_t gpa;
4568 int handled, ret;
22388a3c 4569 bool write = ops->write;
f78146b0 4570 struct kvm_mmio_fragment *frag;
10589a46 4571
22388a3c 4572 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4573
af7cc7d1 4574 if (ret < 0)
bbd9b64e 4575 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4576
4577 /* For APIC access vmexit */
af7cc7d1 4578 if (ret)
bbd9b64e
CO		 4579 goto mmio;
4580
22388a3c 4581 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4582 return X86EMUL_CONTINUE;
4583
4584mmio:
4585 /*
4586 * Is this MMIO handled locally?
4587 */
22388a3c 4588 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4589 if (handled == bytes)
bbd9b64e 4590 return X86EMUL_CONTINUE;
bbd9b64e 4591
70252a10
AK		 4592 gpa += handled;
4593 bytes -= handled;
4594 val += handled;
4595
87da7e66
XG		 4596 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4597 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4598 frag->gpa = gpa;
4599 frag->data = val;
4600 frag->len = bytes;
f78146b0 4601 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4602}
4603
52eb5a6d
XL		 4604static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4605 unsigned long addr,
22388a3c
XG		 4606 void *val, unsigned int bytes,
4607 struct x86_exception *exception,
0fbe9b0b 4608 const struct read_write_emulator_ops *ops)
bbd9b64e 4609{
0f65dd70 4610 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4611 gpa_t gpa;
4612 int rc;
4613
4614 if (ops->read_write_prepare &&
4615 ops->read_write_prepare(vcpu, val, bytes))
4616 return X86EMUL_CONTINUE;
4617
4618 vcpu->mmio_nr_fragments = 0;
0f65dd70 4619
bbd9b64e
CO		 4620 /* Crossing a page boundary? */
4621 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4622 int now;
bbd9b64e
CO		 4623
4624 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4625 rc = emulator_read_write_onepage(addr, val, now, exception,
4626 vcpu, ops);
4627
bbd9b64e
CO		 4628 if (rc != X86EMUL_CONTINUE)
4629 return rc;
4630 addr += now;
bac15531
NA		 4631 if (ctxt->mode != X86EMUL_MODE_PROT64)
4632 addr = (u32)addr;
bbd9b64e
CO		 4633 val += now;
4634 bytes -= now;
4635 }
22388a3c 4636
f78146b0
AK		 4637 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4638 vcpu, ops);
4639 if (rc != X86EMUL_CONTINUE)
4640 return rc;
4641
4642 if (!vcpu->mmio_nr_fragments)
4643 return rc;
4644
4645 gpa = vcpu->mmio_fragments[0].gpa;
4646
4647 vcpu->mmio_needed = 1;
4648 vcpu->mmio_cur_fragment = 0;
4649
87da7e66 4650 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4651 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4652 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4653 vcpu->run->mmio.phys_addr = gpa;
4654
4655 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4656}
4657
4658static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4659 unsigned long addr,
4660 void *val,
4661 unsigned int bytes,
4662 struct x86_exception *exception)
4663{
4664 return emulator_read_write(ctxt, addr, val, bytes,
4665 exception, &read_emultor);
4666}
4667
52eb5a6d 4668static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4669 unsigned long addr,
4670 const void *val,
4671 unsigned int bytes,
4672 struct x86_exception *exception)
4673{
4674 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4675 exception, &write_emultor);
bbd9b64e 4676}
bbd9b64e 4677
daea3e73
AK		 4678#define CMPXCHG_TYPE(t, ptr, old, new) \
4679 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4680
4681#ifdef CONFIG_X86_64
4682# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4683#else
4684# define CMPXCHG64(ptr, old, new) \
9749a6c0 4685 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4686#endif
4687
0f65dd70
AK		 4688static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4689 unsigned long addr,
bbd9b64e
CO		 4690 const void *old,
4691 const void *new,
4692 unsigned int bytes,
0f65dd70 4693 struct x86_exception *exception)
bbd9b64e 4694{
0f65dd70 4695 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4696 gpa_t gpa;
4697 struct page *page;
4698 char *kaddr;
4699 bool exchanged;
2bacc55c 4700
daea3e73
AK		 4701 /* guests cmpxchg8b have to be emulated atomically */
4702 if (bytes > 8 || (bytes & (bytes - 1)))
4703 goto emul_write;
10589a46 4704
daea3e73 4705 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4706
daea3e73
AK		 4707 if (gpa == UNMAPPED_GVA ||
4708 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4709 goto emul_write;
2bacc55c 4710
daea3e73
AK		 4711 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4712 goto emul_write;
72dc67a6 4713
daea3e73 4714 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4715 if (is_error_page(page))
c19b8bd6 4716 goto emul_write;
72dc67a6 4717
8fd75e12 4718 kaddr = kmap_atomic(page);
daea3e73
AK		 4719 kaddr += offset_in_page(gpa);
4720 switch (bytes) {
4721 case 1:
4722 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4723 break;
4724 case 2:
4725 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4726 break;
4727 case 4:
4728 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4729 break;
4730 case 8:
4731 exchanged = CMPXCHG64(kaddr, old, new);
4732 break;
4733 default:
4734 BUG();
2bacc55c 4735 }
8fd75e12 4736 kunmap_atomic(kaddr);
daea3e73
AK		 4737 kvm_release_page_dirty(page);
4738
4739 if (!exchanged)
4740 return X86EMUL_CMPXCHG_FAILED;
4741
d3714010 4742 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4743 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4744
4745 return X86EMUL_CONTINUE;
4a5f48f6 4746
3200f405 4747emul_write:
daea3e73 4748 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4749
0f65dd70 4750 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4751}
4752
cf8f70bf
GN		 4753static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4754{
4755 /* TODO: String I/O for in kernel device */
4756 int r;
4757
4758 if (vcpu->arch.pio.in)
e32edf4f 4759 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4760 vcpu->arch.pio.size, pd);
4761 else
e32edf4f 4762 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4763 vcpu->arch.pio.port, vcpu->arch.pio.size,
4764 pd);
4765 return r;
4766}
4767
6f6fbe98
XG		 4768static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4769 unsigned short port, void *val,
4770 unsigned int count, bool in)
cf8f70bf 4771{
cf8f70bf 4772 vcpu->arch.pio.port = port;
6f6fbe98 4773 vcpu->arch.pio.in = in;
7972995b 4774 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4775 vcpu->arch.pio.size = size;
4776
4777 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4778 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4779 return 1;
4780 }
4781
4782 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4783 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4784 vcpu->run->io.size = size;
4785 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4786 vcpu->run->io.count = count;
4787 vcpu->run->io.port = port;
4788
4789 return 0;
4790}
4791
6f6fbe98
XG		 4792static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4793 int size, unsigned short port, void *val,
4794 unsigned int count)
cf8f70bf 4795{
ca1d4a9e 4796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4797 int ret;
ca1d4a9e 4798
6f6fbe98
XG		 4799 if (vcpu->arch.pio.count)
4800 goto data_avail;
cf8f70bf 4801
6f6fbe98
XG		 4802 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4803 if (ret) {
4804data_avail:
4805 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4806 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4807 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4808 return 1;
4809 }
4810
cf8f70bf
GN		 4811 return 0;
4812}
4813
6f6fbe98
XG		 4814static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4815 int size, unsigned short port,
4816 const void *val, unsigned int count)
4817{
4818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4819
4820 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4821 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4822 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4823}
4824
bbd9b64e
CO		 4825static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4826{
4827 return kvm_x86_ops->get_segment_base(vcpu, seg);
4828}
4829
3cb16fe7 4830static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4831{
3cb16fe7 4832 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4833}
4834
5cb56059 4835int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4836{
4837 if (!need_emulate_wbinvd(vcpu))
4838 return X86EMUL_CONTINUE;
4839
4840 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4841 int cpu = get_cpu();
4842
4843 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4844 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4845 wbinvd_ipi, NULL, 1);
2eec7343 4846 put_cpu();
f5f48ee1 4847 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4848 } else
4849 wbinvd();
f5f48ee1
SY		 4850 return X86EMUL_CONTINUE;
4851}
5cb56059
JS		 4852
4853int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4854{
4855 kvm_x86_ops->skip_emulated_instruction(vcpu);
4856 return kvm_emulate_wbinvd_noskip(vcpu);
4857}
f5f48ee1
SY		 4858EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4859
5cb56059
JS		 4860
4861
bcaf5cc5
AK		 4862static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4863{
5cb56059 4864 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4865}
4866
52eb5a6d
XL		 4867static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4868 unsigned long *dest)
bbd9b64e 4869{
16f8a6f9 4870 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4871}
4872
52eb5a6d
XL		 4873static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4874 unsigned long value)
bbd9b64e 4875{
338dbc97 4876
717746e3 4877 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4878}
4879
52a46617 4880static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4881{
52a46617 4882 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4883}
4884
717746e3 4885static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4886{
717746e3 4887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4888 unsigned long value;
4889
4890 switch (cr) {
4891 case 0:
4892 value = kvm_read_cr0(vcpu);
4893 break;
4894 case 2:
4895 value = vcpu->arch.cr2;
4896 break;
4897 case 3:
9f8fe504 4898 value = kvm_read_cr3(vcpu);
52a46617
GN		 4899 break;
4900 case 4:
4901 value = kvm_read_cr4(vcpu);
4902 break;
4903 case 8:
4904 value = kvm_get_cr8(vcpu);
4905 break;
4906 default:
a737f256 4907 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4908 return 0;
4909 }
4910
4911 return value;
4912}
4913
717746e3 4914static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4915{
717746e3 4916 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4917 int res = 0;
4918
52a46617
GN		 4919 switch (cr) {
4920 case 0:
49a9b07e 4921 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4922 break;
4923 case 2:
4924 vcpu->arch.cr2 = val;
4925 break;
4926 case 3:
2390218b 4927 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4928 break;
4929 case 4:
a83b29c6 4930 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4931 break;
4932 case 8:
eea1cff9 4933 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4934 break;
4935 default:
a737f256 4936 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4937 res = -1;
52a46617 4938 }
0f12244f
GN		 4939
4940 return res;
52a46617
GN		 4941}
4942
717746e3 4943static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4944{
717746e3 4945 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4946}
4947
4bff1e86 4948static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4949{
4bff1e86 4950 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4951}
4952
4bff1e86 4953static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4954{
4bff1e86 4955 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4956}
4957
1ac9d0cf
AK		 4958static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4959{
4960 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4961}
4962
4963static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4964{
4965 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4966}
4967
4bff1e86
AK		 4968static unsigned long emulator_get_cached_segment_base(
4969 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4970{
4bff1e86 4971 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4972}
4973
1aa36616
AK		 4974static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4975 struct desc_struct *desc, u32 *base3,
4976 int seg)
2dafc6c2
GN		 4977{
4978 struct kvm_segment var;
4979
4bff1e86 4980 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4981 *selector = var.selector;
2dafc6c2 4982
378a8b09
GN		 4983 if (var.unusable) {
4984 memset(desc, 0, sizeof(*desc));
2dafc6c2 4985 return false;
378a8b09 4986 }
2dafc6c2
GN		 4987
4988 if (var.g)
4989 var.limit >>= 12;
4990 set_desc_limit(desc, var.limit);
4991 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4992#ifdef CONFIG_X86_64
4993 if (base3)
4994 *base3 = var.base >> 32;
4995#endif
2dafc6c2
GN		 4996 desc->type = var.type;
4997 desc->s = var.s;
4998 desc->dpl = var.dpl;
4999 desc->p = var.present;
5000 desc->avl = var.avl;
5001 desc->l = var.l;
5002 desc->d = var.db;
5003 desc->g = var.g;
5004
5005 return true;
5006}
5007
1aa36616
AK		 5008static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5009 struct desc_struct *desc, u32 base3,
5010 int seg)
2dafc6c2 5011{
4bff1e86 5012 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5013 struct kvm_segment var;
5014
1aa36616 5015 var.selector = selector;
2dafc6c2 5016 var.base = get_desc_base(desc);
5601d05b
GN		 5017#ifdef CONFIG_X86_64
5018 var.base |= ((u64)base3) << 32;
5019#endif
2dafc6c2
GN		 5020 var.limit = get_desc_limit(desc);
5021 if (desc->g)
5022 var.limit = (var.limit << 12) | 0xfff;
5023 var.type = desc->type;
2dafc6c2
GN		 5024 var.dpl = desc->dpl;
5025 var.db = desc->d;
5026 var.s = desc->s;
5027 var.l = desc->l;
5028 var.g = desc->g;
5029 var.avl = desc->avl;
5030 var.present = desc->p;
5031 var.unusable = !var.present;
5032 var.padding = 0;
5033
5034 kvm_set_segment(vcpu, &var, seg);
5035 return;
5036}
5037
717746e3
AK		 5038static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5039 u32 msr_index, u64 *pdata)
5040{
5041 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
5042}
5043
5044static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5045 u32 msr_index, u64 data)
5046{
8fe8ab46
WA		 5047 struct msr_data msr;
5048
5049 msr.data = data;
5050 msr.index = msr_index;
5051 msr.host_initiated = false;
5052 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5053}
5054
67f4d428
NA		 5055static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5056 u32 pmc)
5057{
5058 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
5059}
5060
222d21aa
AK		 5061static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5062 u32 pmc, u64 *pdata)
5063{
5064 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5065}
5066
6c3287f7
AK		 5067static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5068{
5069 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5070}
5071
5037f6f3
AK		 5072static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5073{
5074 preempt_disable();
5197b808 5075 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5076 /*
5077 * CR0.TS may reference the host fpu state, not the guest fpu state,
5078 * so it may be clear at this point.
5079 */
5080 clts();
5081}
5082
5083static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5084{
5085 preempt_enable();
5086}
5087
2953538e 5088static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5089 struct x86_instruction_info *info,
c4f035c6
AK		 5090 enum x86_intercept_stage stage)
5091{
2953538e 5092 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5093}
5094
0017f93a 5095static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5096 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5097{
0017f93a 5098 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5099}
5100
dd856efa
AK		 5101static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5102{
5103 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5104}
5105
5106static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5107{
5108 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5109}
5110
801806d9
NA		 5111static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5112{
5113 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5114}
5115
0225fb50 5116static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5117 .read_gpr = emulator_read_gpr,
5118 .write_gpr = emulator_write_gpr,
1871c602 5119 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5120 .write_std = kvm_write_guest_virt_system,
1871c602 5121 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5122 .read_emulated = emulator_read_emulated,
5123 .write_emulated = emulator_write_emulated,
5124 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5125 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5126 .pio_in_emulated = emulator_pio_in_emulated,
5127 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5128 .get_segment = emulator_get_segment,
5129 .set_segment = emulator_set_segment,
5951c442 5130 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5131 .get_gdt = emulator_get_gdt,
160ce1f1 5132 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5133 .set_gdt = emulator_set_gdt,
5134 .set_idt = emulator_set_idt,
52a46617
GN		 5135 .get_cr = emulator_get_cr,
5136 .set_cr = emulator_set_cr,
9c537244 5137 .cpl = emulator_get_cpl,
35aa5375
GN		 5138 .get_dr = emulator_get_dr,
5139 .set_dr = emulator_set_dr,
717746e3
AK		 5140 .set_msr = emulator_set_msr,
5141 .get_msr = emulator_get_msr,
67f4d428 5142 .check_pmc = emulator_check_pmc,
222d21aa 5143 .read_pmc = emulator_read_pmc,
6c3287f7 5144 .halt = emulator_halt,
bcaf5cc5 5145 .wbinvd = emulator_wbinvd,
d6aa1000 5146 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5147 .get_fpu = emulator_get_fpu,
5148 .put_fpu = emulator_put_fpu,
c4f035c6 5149 .intercept = emulator_intercept,
bdb42f5a 5150 .get_cpuid = emulator_get_cpuid,
801806d9 5151 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5152};
5153
95cb2295
GN		 5154static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5155{
37ccdcbe 5156 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5157 /*
5158 * an sti; sti; sequence only disable interrupts for the first
5159 * instruction. So, if the last instruction, be it emulated or
5160 * not, left the system with the INT_STI flag enabled, it
5161 * means that the last instruction is an sti. We should not
5162 * leave the flag on in this case. The same goes for mov ss
5163 */
37ccdcbe
PB		 5164 if (int_shadow & mask)
5165 mask = 0;
6addfc42 5166 if (unlikely(int_shadow || mask)) {
95cb2295 5167 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5168 if (!mask)
5169 kvm_make_request(KVM_REQ_EVENT, vcpu);
5170 }
95cb2295
GN		 5171}
5172
ef54bcfe 5173static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5174{
5175 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5176 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5177 return kvm_propagate_fault(vcpu, &ctxt->exception);
5178
5179 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5180 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5181 ctxt->exception.error_code);
54b8486f 5182 else
da9cb575 5183 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5184 return false;
54b8486f
GN		 5185}
5186
8ec4722d
MG		 5187static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5188{
adf52235 5189 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5190 int cs_db, cs_l;
5191
8ec4722d
MG		 5192 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5193
adf52235
TY		 5194 ctxt->eflags = kvm_get_rflags(vcpu);
5195 ctxt->eip = kvm_rip_read(vcpu);
5196 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5197 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5198 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5199 cs_db ? X86EMUL_MODE_PROT32 :
5200 X86EMUL_MODE_PROT16;
5201 ctxt->guest_mode = is_guest_mode(vcpu);
5202
dd856efa 5203 init_decode_cache(ctxt);
7ae441ea 5204 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5205}
5206
71f9833b 5207int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5208{
9d74191a 5209 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5210 int ret;
5211
5212 init_emulate_ctxt(vcpu);
5213
9dac77fa
AK		 5214 ctxt->op_bytes = 2;
5215 ctxt->ad_bytes = 2;
5216 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5217 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5218
5219 if (ret != X86EMUL_CONTINUE)
5220 return EMULATE_FAIL;
5221
9dac77fa 5222 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5223 kvm_rip_write(vcpu, ctxt->eip);
5224 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5225
5226 if (irq == NMI_VECTOR)
7460fb4a 5227 vcpu->arch.nmi_pending = 0;
63995653
MG		 5228 else
5229 vcpu->arch.interrupt.pending = false;
5230
5231 return EMULATE_DONE;
5232}
5233EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5234
6d77dbfc
GN		 5235static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5236{
fc3a9157
JR		 5237 int r = EMULATE_DONE;
5238
6d77dbfc
GN		 5239 ++vcpu->stat.insn_emulation_fail;
5240 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5241 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5242 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5243 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5244 vcpu->run->internal.ndata = 0;
5245 r = EMULATE_FAIL;
5246 }
6d77dbfc 5247 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5248
5249 return r;
6d77dbfc
GN		 5250}
5251
93c05d3e 5252static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5253 bool write_fault_to_shadow_pgtable,
5254 int emulation_type)
a6f177ef 5255{
95b3cf69 5256 gpa_t gpa = cr2;
8e3d9d06 5257 pfn_t pfn;
a6f177ef 5258
991eebf9
GN		 5259 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5260 return false;
5261
95b3cf69
XG		 5262 if (!vcpu->arch.mmu.direct_map) {
5263 /*
5264 * Write permission should be allowed since only
5265 * write access need to be emulated.
5266 */
5267 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5268
95b3cf69
XG		 5269 /*
5270 * If the mapping is invalid in guest, let cpu retry
5271 * it to generate fault.
5272 */
5273 if (gpa == UNMAPPED_GVA)
5274 return true;
5275 }
a6f177ef 5276
8e3d9d06
XG		 5277 /*
5278 * Do not retry the unhandleable instruction if it faults on the
5279 * readonly host memory, otherwise it will goto a infinite loop:
5280 * retry instruction -> write #PF -> emulation fail -> retry
5281 * instruction -> ...
5282 */
5283 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5284
5285 /*
5286 * If the instruction failed on the error pfn, it can not be fixed,
5287 * report the error to userspace.
5288 */
5289 if (is_error_noslot_pfn(pfn))
5290 return false;
5291
5292 kvm_release_pfn_clean(pfn);
5293
5294 /* The instructions are well-emulated on direct mmu. */
5295 if (vcpu->arch.mmu.direct_map) {
5296 unsigned int indirect_shadow_pages;
5297
5298 spin_lock(&vcpu->kvm->mmu_lock);
5299 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5300 spin_unlock(&vcpu->kvm->mmu_lock);
5301
5302 if (indirect_shadow_pages)
5303 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5304
a6f177ef 5305 return true;
8e3d9d06 5306 }
a6f177ef 5307
95b3cf69
XG		 5308 /*
5309 * if emulation was due to access to shadowed page table
5310 * and it failed try to unshadow page and re-enter the
5311 * guest to let CPU execute the instruction.
5312 */
5313 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5314
5315 /*
5316 * If the access faults on its page table, it can not
5317 * be fixed by unprotecting shadow page and it should
5318 * be reported to userspace.
5319 */
5320 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5321}
5322
1cb3f3ae
XG		 5323static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5324 unsigned long cr2, int emulation_type)
5325{
5326 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5327 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5328
5329 last_retry_eip = vcpu->arch.last_retry_eip;
5330 last_retry_addr = vcpu->arch.last_retry_addr;
5331
5332 /*
5333 * If the emulation is caused by #PF and it is non-page_table
5334 * writing instruction, it means the VM-EXIT is caused by shadow
5335 * page protected, we can zap the shadow page and retry this
5336 * instruction directly.
5337 *
5338 * Note: if the guest uses a non-page-table modifying instruction
5339 * on the PDE that points to the instruction, then we will unmap
5340 * the instruction and go to an infinite loop. So, we cache the
5341 * last retried eip and the last fault address, if we meet the eip
5342 * and the address again, we can break out of the potential infinite
5343 * loop.
5344 */
5345 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5346
5347 if (!(emulation_type & EMULTYPE_RETRY))
5348 return false;
5349
5350 if (x86_page_table_writing_insn(ctxt))
5351 return false;
5352
5353 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5354 return false;
5355
5356 vcpu->arch.last_retry_eip = ctxt->eip;
5357 vcpu->arch.last_retry_addr = cr2;
5358
5359 if (!vcpu->arch.mmu.direct_map)
5360 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5361
22368028 5362 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5363
5364 return true;
5365}
5366
716d51ab
GN		 5367static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5368static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5369
4a1e10d5
PB		 5370static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5371 unsigned long *db)
5372{
5373 u32 dr6 = 0;
5374 int i;
5375 u32 enable, rwlen;
5376
5377 enable = dr7;
5378 rwlen = dr7 >> 16;
5379 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5380 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5381 dr6 |= (1 << i);
5382 return dr6;
5383}
5384
6addfc42 5385static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5386{
5387 struct kvm_run *kvm_run = vcpu->run;
5388
5389 /*
6addfc42
PB		 5390 * rflags is the old, "raw" value of the flags. The new value has
5391 * not been saved yet.
663f4c61
PB		 5392 *
5393 * This is correct even for TF set by the guest, because "the
5394 * processor will not generate this exception after the instruction
5395 * that sets the TF flag".
5396 */
663f4c61
PB		 5397 if (unlikely(rflags & X86_EFLAGS_TF)) {
5398 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5399 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5400 DR6_RTM;
663f4c61
PB		 5401 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5402 kvm_run->debug.arch.exception = DB_VECTOR;
5403 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5404 *r = EMULATE_USER_EXIT;
5405 } else {
5406 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5407 /*
5408 * "Certain debug exceptions may clear bit 0-3. The
5409 * remaining contents of the DR6 register are never
5410 * cleared by the processor".
5411 */
5412 vcpu->arch.dr6 &= ~15;
6f43ed01 5413 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5414 kvm_queue_exception(vcpu, DB_VECTOR);
5415 }
5416 }
5417}
5418
4a1e10d5
PB		 5419static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5420{
4a1e10d5
PB		 5421 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5422 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5423 struct kvm_run *kvm_run = vcpu->run;
5424 unsigned long eip = kvm_get_linear_rip(vcpu);
5425 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5426 vcpu->arch.guest_debug_dr7,
5427 vcpu->arch.eff_db);
5428
5429 if (dr6 != 0) {
6f43ed01 5430 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5431 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5432 kvm_run->debug.arch.exception = DB_VECTOR;
5433 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5434 *r = EMULATE_USER_EXIT;
5435 return true;
5436 }
5437 }
5438
4161a569
NA		 5439 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5440 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5441 unsigned long eip = kvm_get_linear_rip(vcpu);
5442 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5443 vcpu->arch.dr7,
5444 vcpu->arch.db);
5445
5446 if (dr6 != 0) {
5447 vcpu->arch.dr6 &= ~15;
6f43ed01 5448 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5449 kvm_queue_exception(vcpu, DB_VECTOR);
5450 *r = EMULATE_DONE;
5451 return true;
5452 }
5453 }
5454
5455 return false;
5456}
5457
51d8b661
AP		 5458int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5459 unsigned long cr2,
dc25e89e
AP		 5460 int emulation_type,
5461 void *insn,
5462 int insn_len)
bbd9b64e 5463{
95cb2295 5464 int r;
9d74191a 5465 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5466 bool writeback = true;
93c05d3e 5467 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5468
93c05d3e
XG		 5469 /*
5470 * Clear write_fault_to_shadow_pgtable here to ensure it is
5471 * never reused.
5472 */
5473 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5474 kvm_clear_exception_queue(vcpu);
8d7d8102 5475
571008da 5476 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5477 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5478
5479 /*
5480 * We will reenter on the same instruction since
5481 * we do not set complete_userspace_io. This does not
5482 * handle watchpoints yet, those would be handled in
5483 * the emulate_ops.
5484 */
5485 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5486 return r;
5487
9d74191a
TY		 5488 ctxt->interruptibility = 0;
5489 ctxt->have_exception = false;
e0ad0b47 5490 ctxt->exception.vector = -1;
9d74191a 5491 ctxt->perm_ok = false;
bbd9b64e 5492
b51e974f 5493 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5494
9d74191a 5495 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5496
e46479f8 5497 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5498 ++vcpu->stat.insn_emulation;
1d2887e2 5499 if (r != EMULATION_OK) {
4005996e
AK		 5500 if (emulation_type & EMULTYPE_TRAP_UD)
5501 return EMULATE_FAIL;
991eebf9
GN		 5502 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5503 emulation_type))
bbd9b64e 5504 return EMULATE_DONE;
6d77dbfc
GN		 5505 if (emulation_type & EMULTYPE_SKIP)
5506 return EMULATE_FAIL;
5507 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5508 }
5509 }
5510
ba8afb6b 5511 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5512 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5513 if (ctxt->eflags & X86_EFLAGS_RF)
5514 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5515 return EMULATE_DONE;
5516 }
5517
1cb3f3ae
XG		 5518 if (retry_instruction(ctxt, cr2, emulation_type))
5519 return EMULATE_DONE;
5520
7ae441ea 5521 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5522 changes registers values during IO operation */
7ae441ea
GN		 5523 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5524 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5525 emulator_invalidate_register_cache(ctxt);
7ae441ea 5526 }
4d2179e1 5527
5cd21917 5528restart:
9d74191a 5529 r = x86_emulate_insn(ctxt);
bbd9b64e 5530
775fde86
JR		 5531 if (r == EMULATION_INTERCEPTED)
5532 return EMULATE_DONE;
5533
d2ddd1c4 5534 if (r == EMULATION_FAILED) {
991eebf9
GN		 5535 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5536 emulation_type))
c3cd7ffa
GN		 5537 return EMULATE_DONE;
5538
6d77dbfc 5539 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5540 }
5541
9d74191a 5542 if (ctxt->have_exception) {
d2ddd1c4 5543 r = EMULATE_DONE;
ef54bcfe
PB		 5544 if (inject_emulated_exception(vcpu))
5545 return r;
d2ddd1c4 5546 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5547 if (!vcpu->arch.pio.in) {
5548 /* FIXME: return into emulator if single-stepping. */
3457e419 5549 vcpu->arch.pio.count = 0;
0912c977 5550 } else {
7ae441ea 5551 writeback = false;
716d51ab
GN		 5552 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5553 }
ac0a48c3 5554 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5555 } else if (vcpu->mmio_needed) {
5556 if (!vcpu->mmio_is_write)
5557 writeback = false;
ac0a48c3 5558 r = EMULATE_USER_EXIT;
716d51ab 5559 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5560 } else if (r == EMULATION_RESTART)
5cd21917 5561 goto restart;
d2ddd1c4
GN		 5562 else
5563 r = EMULATE_DONE;
f850e2e6 5564
7ae441ea 5565 if (writeback) {
6addfc42 5566 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5567 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5568 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5569 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5570 if (r == EMULATE_DONE)
6addfc42 5571 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5572 if (!ctxt->have_exception ||
5573 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5574 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5575
5576 /*
5577 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5578 * do nothing, and it will be requested again as soon as
5579 * the shadow expires. But we still need to check here,
5580 * because POPF has no interrupt shadow.
5581 */
5582 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5583 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5584 } else
5585 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5586
5587 return r;
de7d789a 5588}
51d8b661 5589EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5590
cf8f70bf 5591int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5592{
cf8f70bf 5593 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5594 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5595 size, port, &val, 1);
cf8f70bf 5596 /* do not return to emulator after return from userspace */
7972995b 5597 vcpu->arch.pio.count = 0;
de7d789a
CO		 5598 return ret;
5599}
cf8f70bf 5600EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5601
8cfdc000
ZA		 5602static void tsc_bad(void *info)
5603{
0a3aee0d 5604 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5605}
5606
5607static void tsc_khz_changed(void *data)
c8076604 5608{
8cfdc000
ZA		 5609 struct cpufreq_freqs *freq = data;
5610 unsigned long khz = 0;
5611
5612 if (data)
5613 khz = freq->new;
5614 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5615 khz = cpufreq_quick_get(raw_smp_processor_id());
5616 if (!khz)
5617 khz = tsc_khz;
0a3aee0d 5618 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5619}
5620
c8076604
GH		 5621static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5622 void *data)
5623{
5624 struct cpufreq_freqs *freq = data;
5625 struct kvm *kvm;
5626 struct kvm_vcpu *vcpu;
5627 int i, send_ipi = 0;
5628
8cfdc000
ZA		 5629 /*
5630 * We allow guests to temporarily run on slowing clocks,
5631 * provided we notify them after, or to run on accelerating
5632 * clocks, provided we notify them before. Thus time never
5633 * goes backwards.
5634 *
5635 * However, we have a problem. We can't atomically update
5636 * the frequency of a given CPU from this function; it is
5637 * merely a notifier, which can be called from any CPU.
5638 * Changing the TSC frequency at arbitrary points in time
5639 * requires a recomputation of local variables related to
5640 * the TSC for each VCPU. We must flag these local variables
5641 * to be updated and be sure the update takes place with the
5642 * new frequency before any guests proceed.
5643 *
5644 * Unfortunately, the combination of hotplug CPU and frequency
5645 * change creates an intractable locking scenario; the order
5646 * of when these callouts happen is undefined with respect to
5647 * CPU hotplug, and they can race with each other. As such,
5648 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5649 * undefined; you can actually have a CPU frequency change take
5650 * place in between the computation of X and the setting of the
5651 * variable. To protect against this problem, all updates of
5652 * the per_cpu tsc_khz variable are done in an interrupt
5653 * protected IPI, and all callers wishing to update the value
5654 * must wait for a synchronous IPI to complete (which is trivial
5655 * if the caller is on the CPU already). This establishes the
5656 * necessary total order on variable updates.
5657 *
5658 * Note that because a guest time update may take place
5659 * anytime after the setting of the VCPU's request bit, the
5660 * correct TSC value must be set before the request. However,
5661 * to ensure the update actually makes it to any guest which
5662 * starts running in hardware virtualization between the set
5663 * and the acquisition of the spinlock, we must also ping the
5664 * CPU after setting the request bit.
5665 *
5666 */
5667
c8076604
GH		 5668 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5669 return 0;
5670 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5671 return 0;
8cfdc000
ZA		 5672
5673 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5674
2f303b74 5675 spin_lock(&kvm_lock);
c8076604 5676 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5677 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5678 if (vcpu->cpu != freq->cpu)
5679 continue;
c285545f 5680 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5681 if (vcpu->cpu != smp_processor_id())
8cfdc000 5682 send_ipi = 1;
c8076604
GH		 5683 }
5684 }
2f303b74 5685 spin_unlock(&kvm_lock);
c8076604
GH		 5686
5687 if (freq->old < freq->new && send_ipi) {
5688 /*
5689 * We upscale the frequency. Must make the guest
5690 * doesn't see old kvmclock values while running with
5691 * the new frequency, otherwise we risk the guest sees
5692 * time go backwards.
5693 *
5694 * In case we update the frequency for another cpu
5695 * (which might be in guest context) send an interrupt
5696 * to kick the cpu out of guest context. Next time
5697 * guest context is entered kvmclock will be updated,
5698 * so the guest will not see stale values.
5699 */
8cfdc000 5700 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5701 }
5702 return 0;
5703}
5704
5705static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5706 .notifier_call = kvmclock_cpufreq_notifier
5707};
5708
5709static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5710 unsigned long action, void *hcpu)
5711{
5712 unsigned int cpu = (unsigned long)hcpu;
5713
5714 switch (action) {
5715 case CPU_ONLINE:
5716 case CPU_DOWN_FAILED:
5717 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5718 break;
5719 case CPU_DOWN_PREPARE:
5720 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5721 break;
5722 }
5723 return NOTIFY_OK;
5724}
5725
5726static struct notifier_block kvmclock_cpu_notifier_block = {
5727 .notifier_call = kvmclock_cpu_notifier,
5728 .priority = -INT_MAX
c8076604
GH		 5729};
5730
b820cc0c
ZA		 5731static void kvm_timer_init(void)
5732{
5733 int cpu;
5734
c285545f 5735 max_tsc_khz = tsc_khz;
460dd42e
SB		 5736
5737 cpu_notifier_register_begin();
b820cc0c 5738 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5739#ifdef CONFIG_CPU_FREQ
5740 struct cpufreq_policy policy;
5741 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5742 cpu = get_cpu();
5743 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5744 if (policy.cpuinfo.max_freq)
5745 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5746 put_cpu();
c285545f 5747#endif
b820cc0c
ZA		 5748 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5749 CPUFREQ_TRANSITION_NOTIFIER);
5750 }
c285545f 5751 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5752 for_each_online_cpu(cpu)
5753 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5754
5755 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5756 cpu_notifier_register_done();
5757
b820cc0c
ZA		 5758}
5759
ff9d07a0
ZY		 5760static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5761
f5132b01 5762int kvm_is_in_guest(void)
ff9d07a0 5763{
086c9855 5764 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5765}
5766
5767static int kvm_is_user_mode(void)
5768{
5769 int user_mode = 3;
dcf46b94 5770
086c9855
AS		 5771 if (__this_cpu_read(current_vcpu))
5772 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5773
ff9d07a0
ZY		 5774 return user_mode != 0;
5775}
5776
5777static unsigned long kvm_get_guest_ip(void)
5778{
5779 unsigned long ip = 0;
dcf46b94 5780
086c9855
AS		 5781 if (__this_cpu_read(current_vcpu))
5782 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5783
ff9d07a0
ZY		 5784 return ip;
5785}
5786
5787static struct perf_guest_info_callbacks kvm_guest_cbs = {
5788 .is_in_guest = kvm_is_in_guest,
5789 .is_user_mode = kvm_is_user_mode,
5790 .get_guest_ip = kvm_get_guest_ip,
5791};
5792
5793void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5794{
086c9855 5795 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5796}
5797EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5798
5799void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5800{
086c9855 5801 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5802}
5803EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5804
ce88decf
XG		 5805static void kvm_set_mmio_spte_mask(void)
5806{
5807 u64 mask;
5808 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5809
5810 /*
5811 * Set the reserved bits and the present bit of an paging-structure
5812 * entry to generate page fault with PFER.RSV = 1.
5813 */
885032b9 5814 /* Mask the reserved physical address bits. */
d1431483 5815 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5816
5817 /* Bit 62 is always reserved for 32bit host. */
5818 mask |= 0x3ull << 62;
5819
5820 /* Set the present bit. */
ce88decf
XG		 5821 mask |= 1ull;
5822
5823#ifdef CONFIG_X86_64
5824 /*
5825 * If reserved bit is not supported, clear the present bit to disable
5826 * mmio page fault.
5827 */
5828 if (maxphyaddr == 52)
5829 mask &= ~1ull;
5830#endif
5831
5832 kvm_mmu_set_mmio_spte_mask(mask);
5833}
5834
16e8d74d
MT		 5835#ifdef CONFIG_X86_64
5836static void pvclock_gtod_update_fn(struct work_struct *work)
5837{
d828199e
MT		 5838 struct kvm *kvm;
5839
5840 struct kvm_vcpu *vcpu;
5841 int i;
5842
2f303b74 5843 spin_lock(&kvm_lock);
d828199e
MT		 5844 list_for_each_entry(kvm, &vm_list, vm_list)
5845 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5846 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5847 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5848 spin_unlock(&kvm_lock);
16e8d74d
MT		 5849}
5850
5851static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5852
5853/*
5854 * Notification about pvclock gtod data update.
5855 */
5856static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5857 void *priv)
5858{
5859 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5860 struct timekeeper *tk = priv;
5861
5862 update_pvclock_gtod(tk);
5863
5864 /* disable master clock if host does not trust, or does not
5865 * use, TSC clocksource
5866 */
5867 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5868 atomic_read(&kvm_guest_has_master_clock) != 0)
5869 queue_work(system_long_wq, &pvclock_gtod_work);
5870
5871 return 0;
5872}
5873
5874static struct notifier_block pvclock_gtod_notifier = {
5875 .notifier_call = pvclock_gtod_notify,
5876};
5877#endif
5878
f8c16bba 5879int kvm_arch_init(void *opaque)
043405e1 5880{
b820cc0c 5881 int r;
6b61edf7 5882 struct kvm_x86_ops *ops = opaque;
f8c16bba 5883
f8c16bba
ZX		 5884 if (kvm_x86_ops) {
5885 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5886 r = -EEXIST;
5887 goto out;
f8c16bba
ZX		 5888 }
5889
5890 if (!ops->cpu_has_kvm_support()) {
5891 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5892 r = -EOPNOTSUPP;
5893 goto out;
f8c16bba
ZX		 5894 }
5895 if (ops->disabled_by_bios()) {
5896 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5897 r = -EOPNOTSUPP;
5898 goto out;
f8c16bba
ZX		 5899 }
5900
013f6a5d
MT		 5901 r = -ENOMEM;
5902 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5903 if (!shared_msrs) {
5904 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5905 goto out;
5906 }
5907
97db56ce
AK		 5908 r = kvm_mmu_module_init();
5909 if (r)
013f6a5d 5910 goto out_free_percpu;
97db56ce 5911
ce88decf 5912 kvm_set_mmio_spte_mask();
97db56ce 5913
f8c16bba 5914 kvm_x86_ops = ops;
920c8377 5915
7b52345e 5916 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5917 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5918
b820cc0c 5919 kvm_timer_init();
c8076604 5920
ff9d07a0
ZY		 5921 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5922
2acf923e
DC		 5923 if (cpu_has_xsave)
5924 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5925
c5cc421b 5926 kvm_lapic_init();
16e8d74d
MT		 5927#ifdef CONFIG_X86_64
5928 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5929#endif
5930
f8c16bba 5931 return 0;
56c6d28a 5932
013f6a5d
MT		 5933out_free_percpu:
5934 free_percpu(shared_msrs);
56c6d28a 5935out:
56c6d28a 5936 return r;
043405e1 5937}
8776e519 5938
f8c16bba
ZX		 5939void kvm_arch_exit(void)
5940{
ff9d07a0
ZY		 5941 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5942
888d256e
JK		 5943 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5944 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5945 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5946 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5947#ifdef CONFIG_X86_64
5948 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5949#endif
f8c16bba 5950 kvm_x86_ops = NULL;
56c6d28a 5951 kvm_mmu_module_exit();
013f6a5d 5952 free_percpu(shared_msrs);
56c6d28a 5953}
f8c16bba 5954
5cb56059 5955int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5956{
5957 ++vcpu->stat.halt_exits;
5958 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5959 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5960 return 1;
5961 } else {
5962 vcpu->run->exit_reason = KVM_EXIT_HLT;
5963 return 0;
5964 }
5965}
5cb56059
JS		 5966EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5967
5968int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5969{
5970 kvm_x86_ops->skip_emulated_instruction(vcpu);
5971 return kvm_vcpu_halt(vcpu);
5972}
8776e519
HB		 5973EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5974
55cd8e5a
GN		 5975int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5976{
5977 u64 param, ingpa, outgpa, ret;
5978 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5979 bool fast, longmode;
55cd8e5a
GN		 5980
5981 /*
5982 * hypercall generates UD from non zero cpl and real mode
5983 * per HYPER-V spec
5984 */
3eeb3288 5985 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5986 kvm_queue_exception(vcpu, UD_VECTOR);
5987 return 0;
5988 }
5989
a449c7aa 5990 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5991
5992 if (!longmode) {
ccd46936
GN		 5993 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5994 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5995 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5996 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5997 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5998 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5999 }
6000#ifdef CONFIG_X86_64
6001 else {
6002 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
6003 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
6004 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
6005 }
6006#endif
6007
6008 code = param & 0xffff;
6009 fast = (param >> 16) & 0x1;
6010 rep_cnt = (param >> 32) & 0xfff;
6011 rep_idx = (param >> 48) & 0xfff;
6012
6013 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
6014
c25bc163
GN		 6015 switch (code) {
6016 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
6017 kvm_vcpu_on_spin(vcpu);
6018 break;
6019 default:
6020 res = HV_STATUS_INVALID_HYPERCALL_CODE;
6021 break;
6022 }
55cd8e5a
GN		 6023
6024 ret = res | (((u64)rep_done & 0xfff) << 32);
6025 if (longmode) {
6026 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6027 } else {
6028 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
6029 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
6030 }
6031
6032 return 1;
6033}
6034
6aef266c
SV		 6035/*
6036 * kvm_pv_kick_cpu_op: Kick a vcpu.
6037 *
6038 * @apicid - apicid of vcpu to be kicked.
6039 */
6040static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6041{
24d2166b 6042 struct kvm_lapic_irq lapic_irq;
6aef266c 6043
24d2166b
R		 6044 lapic_irq.shorthand = 0;
6045 lapic_irq.dest_mode = 0;
6046 lapic_irq.dest_id = apicid;
93bbf0b8 6047 lapic_irq.msi_redir_hint = false;
6aef266c 6048
24d2166b 6049 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6050 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6051}
6052
8776e519
HB		 6053int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6054{
6055 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6056 int op_64_bit, r = 1;
8776e519 6057
5cb56059
JS		 6058 kvm_x86_ops->skip_emulated_instruction(vcpu);
6059
55cd8e5a
GN		 6060 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6061 return kvm_hv_hypercall(vcpu);
6062
5fdbf976
MT		 6063 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6064 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6065 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6066 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6067 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6068
229456fc 6069 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6070
a449c7aa
NA		 6071 op_64_bit = is_64_bit_mode(vcpu);
6072 if (!op_64_bit) {
8776e519
HB		 6073 nr &= 0xFFFFFFFF;
6074 a0 &= 0xFFFFFFFF;
6075 a1 &= 0xFFFFFFFF;
6076 a2 &= 0xFFFFFFFF;
6077 a3 &= 0xFFFFFFFF;
6078 }
6079
07708c4a
JK		 6080 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6081 ret = -KVM_EPERM;
6082 goto out;
6083 }
6084
8776e519 6085 switch (nr) {
b93463aa
AK		 6086 case KVM_HC_VAPIC_POLL_IRQ:
6087 ret = 0;
6088 break;
6aef266c
SV		 6089 case KVM_HC_KICK_CPU:
6090 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6091 ret = 0;
6092 break;
8776e519
HB		 6093 default:
6094 ret = -KVM_ENOSYS;
6095 break;
6096 }
07708c4a 6097out:
a449c7aa
NA		 6098 if (!op_64_bit)
6099 ret = (u32)ret;
5fdbf976 6100 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6101 ++vcpu->stat.hypercalls;
2f333bcb 6102 return r;
8776e519
HB		 6103}
6104EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6105
b6785def 6106static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6107{
d6aa1000 6108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6109 char instruction[3];
5fdbf976 6110 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6111
8776e519 6112 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6113
9d74191a 6114 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6115}
6116
b6c7a5dc
HB		 6117/*
6118 * Check if userspace requested an interrupt window, and that the
6119 * interrupt window is open.
6120 *
6121 * No need to exit to userspace if we already have an interrupt queued.
6122 */
851ba692 6123static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6124{
8061823a 6125 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6126 vcpu->run->request_interrupt_window &&
5df56646 6127 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6128}
6129
851ba692 6130static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6131{
851ba692
AK		 6132 struct kvm_run *kvm_run = vcpu->run;
6133
91586a3b 6134 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6135 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6136 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6137 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6138 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6139 else
b6c7a5dc 6140 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6141 kvm_arch_interrupt_allowed(vcpu) &&
6142 !kvm_cpu_has_interrupt(vcpu) &&
6143 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6144}
6145
95ba8273
GN		 6146static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6147{
6148 int max_irr, tpr;
6149
6150 if (!kvm_x86_ops->update_cr8_intercept)
6151 return;
6152
88c808fd
AK		 6153 if (!vcpu->arch.apic)
6154 return;
6155
8db3baa2
GN		 6156 if (!vcpu->arch.apic->vapic_addr)
6157 max_irr = kvm_lapic_find_highest_irr(vcpu);
6158 else
6159 max_irr = -1;
95ba8273
GN		 6160
6161 if (max_irr != -1)
6162 max_irr >>= 4;
6163
6164 tpr = kvm_lapic_get_cr8(vcpu);
6165
6166 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6167}
6168
b6b8a145 6169static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6170{
b6b8a145
JK		 6171 int r;
6172
95ba8273 6173 /* try to reinject previous events if any */
b59bb7bd 6174 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6175 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6176 vcpu->arch.exception.has_error_code,
6177 vcpu->arch.exception.error_code);
d6e8c854
NA		 6178
6179 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6180 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6181 X86_EFLAGS_RF);
6182
6bdf0662
NA		 6183 if (vcpu->arch.exception.nr == DB_VECTOR &&
6184 (vcpu->arch.dr7 & DR7_GD)) {
6185 vcpu->arch.dr7 &= ~DR7_GD;
6186 kvm_update_dr7(vcpu);
6187 }
6188
b59bb7bd
GN		 6189 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6190 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6191 vcpu->arch.exception.error_code,
6192 vcpu->arch.exception.reinject);
b6b8a145 6193 return 0;
b59bb7bd
GN		 6194 }
6195
95ba8273
GN		 6196 if (vcpu->arch.nmi_injected) {
6197 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6198 return 0;
95ba8273
GN		 6199 }
6200
6201 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6202 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6203 return 0;
6204 }
6205
6206 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6207 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6208 if (r != 0)
6209 return r;
95ba8273
GN		 6210 }
6211
6212 /* try to inject new event if pending */
6213 if (vcpu->arch.nmi_pending) {
6214 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6215 --vcpu->arch.nmi_pending;
95ba8273
GN		 6216 vcpu->arch.nmi_injected = true;
6217 kvm_x86_ops->set_nmi(vcpu);
6218 }
c7c9c56c 6219 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6220 /*
6221 * Because interrupts can be injected asynchronously, we are
6222 * calling check_nested_events again here to avoid a race condition.
6223 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6224 * proposal and current concerns. Perhaps we should be setting
6225 * KVM_REQ_EVENT only on certain events and not unconditionally?
6226 */
6227 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6228 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6229 if (r != 0)
6230 return r;
6231 }
95ba8273 6232 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6233 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6234 false);
6235 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6236 }
6237 }
b6b8a145 6238 return 0;
95ba8273
GN		 6239}
6240
7460fb4a
AK		 6241static void process_nmi(struct kvm_vcpu *vcpu)
6242{
6243 unsigned limit = 2;
6244
6245 /*
6246 * x86 is limited to one NMI running, and one NMI pending after it.
6247 * If an NMI is already in progress, limit further NMIs to just one.
6248 * Otherwise, allow two (and we'll inject the first one immediately).
6249 */
6250 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6251 limit = 1;
6252
6253 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6254 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6255 kvm_make_request(KVM_REQ_EVENT, vcpu);
6256}
6257
3d81bc7e 6258static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6259{
6260 u64 eoi_exit_bitmap[4];
cf9e65b7 6261 u32 tmr[8];
c7c9c56c 6262
3d81bc7e
YZ		 6263 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6264 return;
c7c9c56c
YZ		 6265
6266 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6267 memset(tmr, 0, 32);
c7c9c56c 6268
cf9e65b7 6269 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6270 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6271 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6272}
6273
a70656b6
RK		 6274static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6275{
6276 ++vcpu->stat.tlb_flush;
6277 kvm_x86_ops->tlb_flush(vcpu);
6278}
6279
4256f43f
TC		 6280void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6281{
c24ae0dc
TC		 6282 struct page *page = NULL;
6283
f439ed27
PB		 6284 if (!irqchip_in_kernel(vcpu->kvm))
6285 return;
6286
4256f43f
TC		 6287 if (!kvm_x86_ops->set_apic_access_page_addr)
6288 return;
6289
c24ae0dc 6290 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6291 if (is_error_page(page))
6292 return;
c24ae0dc
TC		 6293 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6294
6295 /*
6296 * Do not pin apic access page in memory, the MMU notifier
6297 * will call us again if it is migrated or swapped out.
6298 */
6299 put_page(page);
4256f43f
TC		 6300}
6301EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6302
fe71557a
TC		 6303void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6304 unsigned long address)
6305{
c24ae0dc
TC		 6306 /*
6307 * The physical address of apic access page is stored in the VMCS.
6308 * Update it when it becomes invalid.
6309 */
6310 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6311 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6312}
6313
9357d939 6314/*
362c698f 6315 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6316 * exiting to the userspace. Otherwise, the value will be returned to the
6317 * userspace.
6318 */
851ba692 6319static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6320{
6321 int r;
6a8b1d13 6322 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6323 vcpu->run->request_interrupt_window;
730dca42 6324 bool req_immediate_exit = false;
b6c7a5dc 6325
3e007509 6326 if (vcpu->requests) {
a8eeb04a 6327 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6328 kvm_mmu_unload(vcpu);
a8eeb04a 6329 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6330 __kvm_migrate_timers(vcpu);
d828199e
MT		 6331 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6332 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6333 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6334 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6335 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6336 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6337 if (unlikely(r))
6338 goto out;
6339 }
a8eeb04a 6340 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6341 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6342 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6343 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6344 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6345 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6346 r = 0;
6347 goto out;
6348 }
a8eeb04a 6349 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6350 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6351 r = 0;
6352 goto out;
6353 }
a8eeb04a 6354 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6355 vcpu->fpu_active = 0;
6356 kvm_x86_ops->fpu_deactivate(vcpu);
6357 }
af585b92
GN		 6358 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6359 /* Page is swapped out. Do synthetic halt */
6360 vcpu->arch.apf.halted = true;
6361 r = 1;
6362 goto out;
6363 }
c9aaa895
GC		 6364 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6365 record_steal_time(vcpu);
7460fb4a
AK		 6366 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6367 process_nmi(vcpu);
f5132b01
GN		 6368 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6369 kvm_handle_pmu_event(vcpu);
6370 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6371 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6372 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6373 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6374 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6375 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6376 }
b93463aa 6377
b463a6f7 6378 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6379 kvm_apic_accept_events(vcpu);
6380 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6381 r = 1;
6382 goto out;
6383 }
6384
b6b8a145
JK		 6385 if (inject_pending_event(vcpu, req_int_win) != 0)
6386 req_immediate_exit = true;
b463a6f7 6387 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6388 else if (vcpu->arch.nmi_pending)
c9a7953f 6389 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6390 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6391 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6392
6393 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6394 /*
6395 * Update architecture specific hints for APIC
6396 * virtual interrupt delivery.
6397 */
6398 if (kvm_x86_ops->hwapic_irr_update)
6399 kvm_x86_ops->hwapic_irr_update(vcpu,
6400 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6401 update_cr8_intercept(vcpu);
6402 kvm_lapic_sync_to_vapic(vcpu);
6403 }
6404 }
6405
d8368af8
AK		 6406 r = kvm_mmu_reload(vcpu);
6407 if (unlikely(r)) {
d905c069 6408 goto cancel_injection;
d8368af8
AK		 6409 }
6410
b6c7a5dc
HB		 6411 preempt_disable();
6412
6413 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6414 if (vcpu->fpu_active)
6415 kvm_load_guest_fpu(vcpu);
2acf923e 6416 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6417
6b7e2d09
XG		 6418 vcpu->mode = IN_GUEST_MODE;
6419
01b71917
MT		 6420 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6421
6b7e2d09
XG		 6422 /* We should set ->mode before check ->requests,
6423 * see the comment in make_all_cpus_request.
6424 */
01b71917 6425 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6426
d94e1dc9 6427 local_irq_disable();
32f88400 6428
6b7e2d09 6429 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6430 || need_resched() || signal_pending(current)) {
6b7e2d09 6431 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6432 smp_wmb();
6c142801
AK		 6433 local_irq_enable();
6434 preempt_enable();
01b71917 6435 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6436 r = 1;
d905c069 6437 goto cancel_injection;
6c142801
AK		 6438 }
6439
d6185f20
NHE		 6440 if (req_immediate_exit)
6441 smp_send_reschedule(vcpu->cpu);
6442
ccf73aaf 6443 __kvm_guest_enter();
b6c7a5dc 6444
42dbaa5a 6445 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6446 set_debugreg(0, 7);
6447 set_debugreg(vcpu->arch.eff_db[0], 0);
6448 set_debugreg(vcpu->arch.eff_db[1], 1);
6449 set_debugreg(vcpu->arch.eff_db[2], 2);
6450 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6451 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6452 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6453 }
b6c7a5dc 6454
229456fc 6455 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6456 wait_lapic_expire(vcpu);
851ba692 6457 kvm_x86_ops->run(vcpu);
b6c7a5dc 6458
c77fb5fe
PB		 6459 /*
6460 * Do this here before restoring debug registers on the host. And
6461 * since we do this before handling the vmexit, a DR access vmexit
6462 * can (a) read the correct value of the debug registers, (b) set
6463 * KVM_DEBUGREG_WONT_EXIT again.
6464 */
6465 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6466 int i;
6467
6468 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6469 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6470 for (i = 0; i < KVM_NR_DB_REGS; i++)
6471 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6472 }
6473
24f1e32c
FW		 6474 /*
6475 * If the guest has used debug registers, at least dr7
6476 * will be disabled while returning to the host.
6477 * If we don't have active breakpoints in the host, we don't
6478 * care about the messed up debug address registers. But if
6479 * we have some of them active, restore the old state.
6480 */
59d8eb53 6481 if (hw_breakpoint_active())
24f1e32c 6482 hw_breakpoint_restore();
42dbaa5a 6483
886b470c
MT		 6484 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6485 native_read_tsc());
1d5f066e 6486
6b7e2d09 6487 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6488 smp_wmb();
a547c6db
YZ		 6489
6490 /* Interrupt is enabled by handle_external_intr() */
6491 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6492
6493 ++vcpu->stat.exits;
6494
6495 /*
6496 * We must have an instruction between local_irq_enable() and
6497 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6498 * the interrupt shadow. The stat.exits increment will do nicely.
6499 * But we need to prevent reordering, hence this barrier():
6500 */
6501 barrier();
6502
6503 kvm_guest_exit();
6504
6505 preempt_enable();
6506
f656ce01 6507 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6508
b6c7a5dc
HB		 6509 /*
6510 * Profile KVM exit RIPs:
6511 */
6512 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6513 unsigned long rip = kvm_rip_read(vcpu);
6514 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6515 }
6516
cc578287
ZA		 6517 if (unlikely(vcpu->arch.tsc_always_catchup))
6518 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6519
5cfb1d5a
MT		 6520 if (vcpu->arch.apic_attention)
6521 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6522
851ba692 6523 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6524 return r;
6525
6526cancel_injection:
6527 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6528 if (unlikely(vcpu->arch.apic_attention))
6529 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6530out:
6531 return r;
6532}
b6c7a5dc 6533
362c698f
PB		 6534static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6535{
9c8fd1ba
PB		 6536 if (!kvm_arch_vcpu_runnable(vcpu)) {
6537 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6538 kvm_vcpu_block(vcpu);
6539 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6540 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6541 return 1;
6542 }
362c698f
PB		 6543
6544 kvm_apic_accept_events(vcpu);
6545 switch(vcpu->arch.mp_state) {
6546 case KVM_MP_STATE_HALTED:
6547 vcpu->arch.pv.pv_unhalted = false;
6548 vcpu->arch.mp_state =
6549 KVM_MP_STATE_RUNNABLE;
6550 case KVM_MP_STATE_RUNNABLE:
6551 vcpu->arch.apf.halted = false;
6552 break;
6553 case KVM_MP_STATE_INIT_RECEIVED:
6554 break;
6555 default:
6556 return -EINTR;
6557 break;
6558 }
6559 return 1;
6560}
09cec754 6561
362c698f 6562static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6563{
6564 int r;
f656ce01 6565 struct kvm *kvm = vcpu->kvm;
d7690175 6566
f656ce01 6567 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6568
362c698f 6569 for (;;) {
af585b92
GN		 6570 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6571 !vcpu->arch.apf.halted)
851ba692 6572 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6573 else
6574 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6575 if (r <= 0)
6576 break;
6577
6578 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6579 if (kvm_cpu_has_pending_timer(vcpu))
6580 kvm_inject_pending_timer_irqs(vcpu);
6581
851ba692 6582 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6583 r = -EINTR;
851ba692 6584 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6585 ++vcpu->stat.request_irq_exits;
362c698f 6586 break;
09cec754 6587 }
af585b92
GN		 6588
6589 kvm_check_async_pf_completion(vcpu);
6590
09cec754
GN		 6591 if (signal_pending(current)) {
6592 r = -EINTR;
851ba692 6593 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6594 ++vcpu->stat.signal_exits;
362c698f 6595 break;
09cec754
GN		 6596 }
6597 if (need_resched()) {
f656ce01 6598 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6599 cond_resched();
f656ce01 6600 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6601 }
b6c7a5dc
HB		 6602 }
6603
f656ce01 6604 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6605
6606 return r;
6607}
6608
716d51ab
GN		 6609static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6610{
6611 int r;
6612 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6613 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6614 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6615 if (r != EMULATE_DONE)
6616 return 0;
6617 return 1;
6618}
6619
6620static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6621{
6622 BUG_ON(!vcpu->arch.pio.count);
6623
6624 return complete_emulated_io(vcpu);
6625}
6626
f78146b0
AK		 6627/*
6628 * Implements the following, as a state machine:
6629 *
6630 * read:
6631 * for each fragment
87da7e66
XG		 6632 * for each mmio piece in the fragment
6633 * write gpa, len
6634 * exit
6635 * copy data
f78146b0
AK		 6636 * execute insn
6637 *
6638 * write:
6639 * for each fragment
87da7e66
XG		 6640 * for each mmio piece in the fragment
6641 * write gpa, len
6642 * copy data
6643 * exit
f78146b0 6644 */
716d51ab 6645static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6646{
6647 struct kvm_run *run = vcpu->run;
f78146b0 6648 struct kvm_mmio_fragment *frag;
87da7e66 6649 unsigned len;
5287f194 6650
716d51ab 6651 BUG_ON(!vcpu->mmio_needed);
5287f194 6652
716d51ab 6653 /* Complete previous fragment */
87da7e66
XG		 6654 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6655 len = min(8u, frag->len);
716d51ab 6656 if (!vcpu->mmio_is_write)
87da7e66
XG		 6657 memcpy(frag->data, run->mmio.data, len);
6658
6659 if (frag->len <= 8) {
6660 /* Switch to the next fragment. */
6661 frag++;
6662 vcpu->mmio_cur_fragment++;
6663 } else {
6664 /* Go forward to the next mmio piece. */
6665 frag->data += len;
6666 frag->gpa += len;
6667 frag->len -= len;
6668 }
6669
a08d3b3b 6670 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6671 vcpu->mmio_needed = 0;
0912c977
PB		 6672
6673 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6674 if (vcpu->mmio_is_write)
716d51ab
GN		 6675 return 1;
6676 vcpu->mmio_read_completed = 1;
6677 return complete_emulated_io(vcpu);
6678 }
87da7e66 6679
716d51ab
GN		 6680 run->exit_reason = KVM_EXIT_MMIO;
6681 run->mmio.phys_addr = frag->gpa;
6682 if (vcpu->mmio_is_write)
87da7e66
XG		 6683 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6684 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6685 run->mmio.is_write = vcpu->mmio_is_write;
6686 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6687 return 0;
5287f194
AK		 6688}
6689
716d51ab 6690
b6c7a5dc
HB		 6691int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6692{
6693 int r;
6694 sigset_t sigsaved;
6695
e5c30142
AK		 6696 if (!tsk_used_math(current) && init_fpu(current))
6697 return -ENOMEM;
6698
ac9f6dc0
AK		 6699 if (vcpu->sigset_active)
6700 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6701
a4535290 6702 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6703 kvm_vcpu_block(vcpu);
66450a21 6704 kvm_apic_accept_events(vcpu);
d7690175 6705 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6706 r = -EAGAIN;
6707 goto out;
b6c7a5dc
HB		 6708 }
6709
b6c7a5dc 6710 /* re-sync apic's tpr */
eea1cff9
AP		 6711 if (!irqchip_in_kernel(vcpu->kvm)) {
6712 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6713 r = -EINVAL;
6714 goto out;
6715 }
6716 }
b6c7a5dc 6717
716d51ab
GN		 6718 if (unlikely(vcpu->arch.complete_userspace_io)) {
6719 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6720 vcpu->arch.complete_userspace_io = NULL;
6721 r = cui(vcpu);
6722 if (r <= 0)
6723 goto out;
6724 } else
6725 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6726
362c698f 6727 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6728
6729out:
f1d86e46 6730 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6731 if (vcpu->sigset_active)
6732 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6733
b6c7a5dc
HB		 6734 return r;
6735}
6736
6737int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6738{
7ae441ea
GN		 6739 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6740 /*
6741 * We are here if userspace calls get_regs() in the middle of
6742 * instruction emulation. Registers state needs to be copied
4a969980 6743 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6744 * that usually, but some bad designed PV devices (vmware
6745 * backdoor interface) need this to work
6746 */
dd856efa 6747 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6748 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6749 }
5fdbf976
MT		 6750 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6751 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6752 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6753 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6754 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6755 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6756 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6757 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6758#ifdef CONFIG_X86_64
5fdbf976
MT		 6759 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6760 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6761 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6762 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6763 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6764 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6765 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6766 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6767#endif
6768
5fdbf976 6769 regs->rip = kvm_rip_read(vcpu);
91586a3b 6770 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6771
b6c7a5dc
HB		 6772 return 0;
6773}
6774
6775int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6776{
7ae441ea
GN		 6777 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6778 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6779
5fdbf976
MT		 6780 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6781 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6782 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6783 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6784 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6785 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6786 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6787 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6788#ifdef CONFIG_X86_64
5fdbf976
MT		 6789 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6790 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6791 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6792 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6793 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6794 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6795 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6796 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6797#endif
6798
5fdbf976 6799 kvm_rip_write(vcpu, regs->rip);
91586a3b 6800 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6801
b4f14abd
JK		 6802 vcpu->arch.exception.pending = false;
6803
3842d135
AK		 6804 kvm_make_request(KVM_REQ_EVENT, vcpu);
6805
b6c7a5dc
HB		 6806 return 0;
6807}
6808
b6c7a5dc
HB		 6809void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6810{
6811 struct kvm_segment cs;
6812
3e6e0aab 6813 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6814 *db = cs.db;
6815 *l = cs.l;
6816}
6817EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6818
6819int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6820 struct kvm_sregs *sregs)
6821{
89a27f4d 6822 struct desc_ptr dt;
b6c7a5dc 6823
3e6e0aab
GT		 6824 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6825 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6826 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6827 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6828 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6829 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6830
3e6e0aab
GT		 6831 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6832 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6833
6834 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6835 sregs->idt.limit = dt.size;
6836 sregs->idt.base = dt.address;
b6c7a5dc 6837 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6838 sregs->gdt.limit = dt.size;
6839 sregs->gdt.base = dt.address;
b6c7a5dc 6840
4d4ec087 6841 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6842 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6843 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6844 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6845 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6846 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6847 sregs->apic_base = kvm_get_apic_base(vcpu);
6848
923c61bb 6849 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6850
36752c9b 6851 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6852 set_bit(vcpu->arch.interrupt.nr,
6853 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6854
b6c7a5dc
HB		 6855 return 0;
6856}
6857
62d9f0db
MT		 6858int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6859 struct kvm_mp_state *mp_state)
6860{
66450a21 6861 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6862 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6863 vcpu->arch.pv.pv_unhalted)
6864 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6865 else
6866 mp_state->mp_state = vcpu->arch.mp_state;
6867
62d9f0db
MT		 6868 return 0;
6869}
6870
6871int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6872 struct kvm_mp_state *mp_state)
6873{
66450a21
JK		 6874 if (!kvm_vcpu_has_lapic(vcpu) &&
6875 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6876 return -EINVAL;
6877
6878 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6879 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6880 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6881 } else
6882 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6883 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6884 return 0;
6885}
6886
7f3d35fd
KW		 6887int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6888 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6889{
9d74191a 6890 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6891 int ret;
e01c2426 6892
8ec4722d 6893 init_emulate_ctxt(vcpu);
c697518a 6894
7f3d35fd 6895 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6896 has_error_code, error_code);
c697518a 6897
c697518a 6898 if (ret)
19d04437 6899 return EMULATE_FAIL;
37817f29 6900
9d74191a
TY		 6901 kvm_rip_write(vcpu, ctxt->eip);
6902 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6903 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6904 return EMULATE_DONE;
37817f29
IE		 6905}
6906EXPORT_SYMBOL_GPL(kvm_task_switch);
6907
b6c7a5dc
HB		 6908int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6909 struct kvm_sregs *sregs)
6910{
58cb628d 6911 struct msr_data apic_base_msr;
b6c7a5dc 6912 int mmu_reset_needed = 0;
63f42e02 6913 int pending_vec, max_bits, idx;
89a27f4d 6914 struct desc_ptr dt;
b6c7a5dc 6915
6d1068b3
PM		 6916 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6917 return -EINVAL;
6918
89a27f4d
GN		 6919 dt.size = sregs->idt.limit;
6920 dt.address = sregs->idt.base;
b6c7a5dc 6921 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6922 dt.size = sregs->gdt.limit;
6923 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6924 kvm_x86_ops->set_gdt(vcpu, &dt);
6925
ad312c7c 6926 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6927 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6928 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6929 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6930
2d3ad1f4 6931 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6932
f6801dff 6933 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6934 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6935 apic_base_msr.data = sregs->apic_base;
6936 apic_base_msr.host_initiated = true;
6937 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6938
4d4ec087 6939 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6940 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6941 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6942
fc78f519 6943 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6944 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6945 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6946 kvm_update_cpuid(vcpu);
63f42e02
XG		 6947
6948 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6949 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6950 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6951 mmu_reset_needed = 1;
6952 }
63f42e02 6953 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6954
6955 if (mmu_reset_needed)
6956 kvm_mmu_reset_context(vcpu);
6957
a50abc3b 6958 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6959 pending_vec = find_first_bit(
6960 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6961 if (pending_vec < max_bits) {
66fd3f7f 6962 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6963 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6964 }
6965
3e6e0aab
GT		 6966 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6967 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6968 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6969 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6970 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6971 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6972
3e6e0aab
GT		 6973 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6974 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6975
5f0269f5
ME		 6976 update_cr8_intercept(vcpu);
6977
9c3e4aab 6978 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6979 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6980 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6981 !is_protmode(vcpu))
9c3e4aab
MT		 6982 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6983
3842d135
AK		 6984 kvm_make_request(KVM_REQ_EVENT, vcpu);
6985
b6c7a5dc
HB		 6986 return 0;
6987}
6988
d0bfb940
JK		 6989int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6990 struct kvm_guest_debug *dbg)
b6c7a5dc 6991{
355be0b9 6992 unsigned long rflags;
ae675ef0 6993 int i, r;
b6c7a5dc 6994
4f926bf2
JK		 6995 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6996 r = -EBUSY;
6997 if (vcpu->arch.exception.pending)
2122ff5e 6998 goto out;
4f926bf2
JK		 6999 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7000 kvm_queue_exception(vcpu, DB_VECTOR);
7001 else
7002 kvm_queue_exception(vcpu, BP_VECTOR);
7003 }
7004
91586a3b
JK		 7005 /*
7006 * Read rflags as long as potentially injected trace flags are still
7007 * filtered out.
7008 */
7009 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7010
7011 vcpu->guest_debug = dbg->control;
7012 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7013 vcpu->guest_debug = 0;
7014
7015 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7016 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7017 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7018 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7019 } else {
7020 for (i = 0; i < KVM_NR_DB_REGS; i++)
7021 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7022 }
c8639010 7023 kvm_update_dr7(vcpu);
ae675ef0 7024
f92653ee
JK		 7025 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7026 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7027 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7028
91586a3b
JK		 7029 /*
7030 * Trigger an rflags update that will inject or remove the trace
7031 * flags.
7032 */
7033 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7034
c8639010 7035 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7036
4f926bf2 7037 r = 0;
d0bfb940 7038
2122ff5e 7039out:
b6c7a5dc
HB		 7040
7041 return r;
7042}
7043
8b006791
ZX		 7044/*
7045 * Translate a guest virtual address to a guest physical address.
7046 */
7047int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7048 struct kvm_translation *tr)
7049{
7050 unsigned long vaddr = tr->linear_address;
7051 gpa_t gpa;
f656ce01 7052 int idx;
8b006791 7053
f656ce01 7054 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7055 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7056 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7057 tr->physical_address = gpa;
7058 tr->valid = gpa != UNMAPPED_GVA;
7059 tr->writeable = 1;
7060 tr->usermode = 0;
8b006791
ZX		 7061
7062 return 0;
7063}
7064
d0752060
HB		 7065int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7066{
98918833
SY		 7067 struct i387_fxsave_struct *fxsave =
7068 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7069
d0752060
HB		 7070 memcpy(fpu->fpr, fxsave->st_space, 128);
7071 fpu->fcw = fxsave->cwd;
7072 fpu->fsw = fxsave->swd;
7073 fpu->ftwx = fxsave->twd;
7074 fpu->last_opcode = fxsave->fop;
7075 fpu->last_ip = fxsave->rip;
7076 fpu->last_dp = fxsave->rdp;
7077 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7078
d0752060
HB		 7079 return 0;
7080}
7081
7082int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7083{
98918833
SY		 7084 struct i387_fxsave_struct *fxsave =
7085 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7086
d0752060
HB		 7087 memcpy(fxsave->st_space, fpu->fpr, 128);
7088 fxsave->cwd = fpu->fcw;
7089 fxsave->swd = fpu->fsw;
7090 fxsave->twd = fpu->ftwx;
7091 fxsave->fop = fpu->last_opcode;
7092 fxsave->rip = fpu->last_ip;
7093 fxsave->rdp = fpu->last_dp;
7094 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7095
d0752060
HB		 7096 return 0;
7097}
7098
d28bc9dd 7099int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7100{
10ab25cd
JK		 7101 int err;
7102
7103 err = fpu_alloc(&vcpu->arch.guest_fpu);
7104 if (err)
7105 return err;
7106
d28bc9dd
NA		 7107 if (!init_event)
7108 fpu_finit(&vcpu->arch.guest_fpu);
7109
df1daba7
PB		 7110 if (cpu_has_xsaves)
7111 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7112 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7113
2acf923e
DC		 7114 /*
7115 * Ensure guest xcr0 is valid for loading
7116 */
7117 vcpu->arch.xcr0 = XSTATE_FP;
7118
ad312c7c 7119 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7120
7121 return 0;
d0752060
HB		 7122}
7123EXPORT_SYMBOL_GPL(fx_init);
7124
98918833
SY		 7125static void fx_free(struct kvm_vcpu *vcpu)
7126{
7127 fpu_free(&vcpu->arch.guest_fpu);
7128}
7129
d0752060
HB		 7130void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7131{
2608d7a1 7132 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7133 return;
7134
2acf923e
DC		 7135 /*
7136 * Restore all possible states in the guest,
7137 * and assume host would use all available bits.
7138 * Guest xcr0 would be loaded later.
7139 */
7140 kvm_put_guest_xcr0(vcpu);
d0752060 7141 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7142 __kernel_fpu_begin();
98918833 7143 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7144 trace_kvm_fpu(1);
d0752060 7145}
d0752060
HB		 7146
7147void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7148{
2acf923e
DC		 7149 kvm_put_guest_xcr0(vcpu);
7150
653f52c3
RR		 7151 if (!vcpu->guest_fpu_loaded) {
7152 vcpu->fpu_counter = 0;
d0752060 7153 return;
653f52c3 7154 }
d0752060
HB		 7155
7156 vcpu->guest_fpu_loaded = 0;
98918833 7157 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7158 __kernel_fpu_end();
f096ed85 7159 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7160 /*
7161 * If using eager FPU mode, or if the guest is a frequent user
7162 * of the FPU, just leave the FPU active for next time.
7163 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7164 * the FPU in bursts will revert to loading it on demand.
7165 */
a9b4fb7e 7166 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7167 if (++vcpu->fpu_counter < 5)
7168 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7169 }
0c04851c 7170 trace_kvm_fpu(0);
d0752060 7171}
e9b11c17
ZX		 7172
7173void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7174{
12f9a48f 7175 kvmclock_reset(vcpu);
7f1ea208 7176
f5f48ee1 7177 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7178 fx_free(vcpu);
e9b11c17
ZX		 7179 kvm_x86_ops->vcpu_free(vcpu);
7180}
7181
7182struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7183 unsigned int id)
7184{
c447e76b
LL		 7185 struct kvm_vcpu *vcpu;
7186
6755bae8
ZA		 7187 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7188 printk_once(KERN_WARNING
7189 "kvm: SMP vm created on host with unstable TSC; "
7190 "guest TSC will not be reliable\n");
c447e76b
LL		 7191
7192 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7193
7194 /*
7195 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7196 * deactivated soon if it doesn't.
7197 */
7198 kvm_x86_ops->fpu_activate(vcpu);
7199 return vcpu;
26e5215f 7200}
e9b11c17 7201
26e5215f
AK		 7202int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7203{
7204 int r;
e9b11c17 7205
0bed3b56 7206 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7207 r = vcpu_load(vcpu);
7208 if (r)
7209 return r;
d28bc9dd 7210 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7211 kvm_mmu_setup(vcpu);
e9b11c17 7212 vcpu_put(vcpu);
e9b11c17 7213
26e5215f 7214 return r;
e9b11c17
ZX		 7215}
7216
31928aa5 7217void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7218{
8fe8ab46 7219 struct msr_data msr;
332967a3 7220 struct kvm *kvm = vcpu->kvm;
42897d86 7221
31928aa5
DD		 7222 if (vcpu_load(vcpu))
7223 return;
8fe8ab46
WA		 7224 msr.data = 0x0;
7225 msr.index = MSR_IA32_TSC;
7226 msr.host_initiated = true;
7227 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7228 vcpu_put(vcpu);
7229
630994b3
MT		 7230 if (!kvmclock_periodic_sync)
7231 return;
7232
332967a3
AJ		 7233 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7234 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7235}
7236
d40ccc62 7237void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7238{
9fc77441 7239 int r;
344d9588
GN		 7240 vcpu->arch.apf.msr_val = 0;
7241
9fc77441
MT		 7242 r = vcpu_load(vcpu);
7243 BUG_ON(r);
e9b11c17
ZX		 7244 kvm_mmu_unload(vcpu);
7245 vcpu_put(vcpu);
7246
98918833 7247 fx_free(vcpu);
e9b11c17
ZX		 7248 kvm_x86_ops->vcpu_free(vcpu);
7249}
7250
d28bc9dd 7251void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7252{
7460fb4a
AK		 7253 atomic_set(&vcpu->arch.nmi_queued, 0);
7254 vcpu->arch.nmi_pending = 0;
448fa4a9 7255 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7256 kvm_clear_interrupt_queue(vcpu);
7257 kvm_clear_exception_queue(vcpu);
448fa4a9 7258
42dbaa5a 7259 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7260 kvm_update_dr0123(vcpu);
6f43ed01 7261 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7262 kvm_update_dr6(vcpu);
42dbaa5a 7263 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7264 kvm_update_dr7(vcpu);
42dbaa5a 7265
1119022c
NA		 7266 vcpu->arch.cr2 = 0;
7267
3842d135 7268 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7269 vcpu->arch.apf.msr_val = 0;
c9aaa895 7270 vcpu->arch.st.msr_val = 0;
3842d135 7271
12f9a48f
GC		 7272 kvmclock_reset(vcpu);
7273
af585b92
GN		 7274 kvm_clear_async_pf_completion_queue(vcpu);
7275 kvm_async_pf_hash_reset(vcpu);
7276 vcpu->arch.apf.halted = false;
3842d135 7277
d28bc9dd
NA		 7278 if (!init_event)
7279 kvm_pmu_reset(vcpu);
f5132b01 7280
66f7b72e
JS		 7281 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7282 vcpu->arch.regs_avail = ~0;
7283 vcpu->arch.regs_dirty = ~0;
7284
d28bc9dd 7285 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7286}
7287
2b4a273b 7288void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7289{
7290 struct kvm_segment cs;
7291
7292 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7293 cs.selector = vector << 8;
7294 cs.base = vector << 12;
7295 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7296 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7297}
7298
13a34e06 7299int kvm_arch_hardware_enable(void)
e9b11c17 7300{
ca84d1a2
ZA		 7301 struct kvm *kvm;
7302 struct kvm_vcpu *vcpu;
7303 int i;
0dd6a6ed
ZA		 7304 int ret;
7305 u64 local_tsc;
7306 u64 max_tsc = 0;
7307 bool stable, backwards_tsc = false;
18863bdd
AK		 7308
7309 kvm_shared_msr_cpu_online();
13a34e06 7310 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7311 if (ret != 0)
7312 return ret;
7313
7314 local_tsc = native_read_tsc();
7315 stable = !check_tsc_unstable();
7316 list_for_each_entry(kvm, &vm_list, vm_list) {
7317 kvm_for_each_vcpu(i, vcpu, kvm) {
7318 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7319 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7320 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7321 backwards_tsc = true;
7322 if (vcpu->arch.last_host_tsc > max_tsc)
7323 max_tsc = vcpu->arch.last_host_tsc;
7324 }
7325 }
7326 }
7327
7328 /*
7329 * Sometimes, even reliable TSCs go backwards. This happens on
7330 * platforms that reset TSC during suspend or hibernate actions, but
7331 * maintain synchronization. We must compensate. Fortunately, we can
7332 * detect that condition here, which happens early in CPU bringup,
7333 * before any KVM threads can be running. Unfortunately, we can't
7334 * bring the TSCs fully up to date with real time, as we aren't yet far
7335 * enough into CPU bringup that we know how much real time has actually
7336 * elapsed; our helper function, get_kernel_ns() will be using boot
7337 * variables that haven't been updated yet.
7338 *
7339 * So we simply find the maximum observed TSC above, then record the
7340 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7341 * the adjustment will be applied. Note that we accumulate
7342 * adjustments, in case multiple suspend cycles happen before some VCPU
7343 * gets a chance to run again. In the event that no KVM threads get a
7344 * chance to run, we will miss the entire elapsed period, as we'll have
7345 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7346 * loose cycle time. This isn't too big a deal, since the loss will be
7347 * uniform across all VCPUs (not to mention the scenario is extremely
7348 * unlikely). It is possible that a second hibernate recovery happens
7349 * much faster than a first, causing the observed TSC here to be
7350 * smaller; this would require additional padding adjustment, which is
7351 * why we set last_host_tsc to the local tsc observed here.
7352 *
7353 * N.B. - this code below runs only on platforms with reliable TSC,
7354 * as that is the only way backwards_tsc is set above. Also note
7355 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7356 * have the same delta_cyc adjustment applied if backwards_tsc
7357 * is detected. Note further, this adjustment is only done once,
7358 * as we reset last_host_tsc on all VCPUs to stop this from being
7359 * called multiple times (one for each physical CPU bringup).
7360 *
4a969980 7361 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7362 * will be compensated by the logic in vcpu_load, which sets the TSC to
7363 * catchup mode. This will catchup all VCPUs to real time, but cannot
7364 * guarantee that they stay in perfect synchronization.
7365 */
7366 if (backwards_tsc) {
7367 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7368 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7369 list_for_each_entry(kvm, &vm_list, vm_list) {
7370 kvm_for_each_vcpu(i, vcpu, kvm) {
7371 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7372 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7373 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7374 }
7375
7376 /*
7377 * We have to disable TSC offset matching.. if you were
7378 * booting a VM while issuing an S4 host suspend....
7379 * you may have some problem. Solving this issue is
7380 * left as an exercise to the reader.
7381 */
7382 kvm->arch.last_tsc_nsec = 0;
7383 kvm->arch.last_tsc_write = 0;
7384 }
7385
7386 }
7387 return 0;
e9b11c17
ZX		 7388}
7389
13a34e06 7390void kvm_arch_hardware_disable(void)
e9b11c17 7391{
13a34e06
RK		 7392 kvm_x86_ops->hardware_disable();
7393 drop_user_return_notifiers();
e9b11c17
ZX		 7394}
7395
7396int kvm_arch_hardware_setup(void)
7397{
9e9c3fe4
NA		 7398 int r;
7399
7400 r = kvm_x86_ops->hardware_setup();
7401 if (r != 0)
7402 return r;
7403
7404 kvm_init_msr_list();
7405 return 0;
e9b11c17
ZX		 7406}
7407
7408void kvm_arch_hardware_unsetup(void)
7409{
7410 kvm_x86_ops->hardware_unsetup();
7411}
7412
7413void kvm_arch_check_processor_compat(void *rtn)
7414{
7415 kvm_x86_ops->check_processor_compatibility(rtn);
7416}
7417
3e515705
AK		 7418bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7419{
7420 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7421}
7422
54e9818f
GN		 7423struct static_key kvm_no_apic_vcpu __read_mostly;
7424
e9b11c17
ZX		 7425int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7426{
7427 struct page *page;
7428 struct kvm *kvm;
7429 int r;
7430
7431 BUG_ON(vcpu->kvm == NULL);
7432 kvm = vcpu->kvm;
7433
6aef266c 7434 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7435 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7436 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7437 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7438 else
a4535290 7439 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7440
7441 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7442 if (!page) {
7443 r = -ENOMEM;
7444 goto fail;
7445 }
ad312c7c 7446 vcpu->arch.pio_data = page_address(page);
e9b11c17 7447
cc578287 7448 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7449
e9b11c17
ZX		 7450 r = kvm_mmu_create(vcpu);
7451 if (r < 0)
7452 goto fail_free_pio_data;
7453
7454 if (irqchip_in_kernel(kvm)) {
7455 r = kvm_create_lapic(vcpu);
7456 if (r < 0)
7457 goto fail_mmu_destroy;
54e9818f
GN		 7458 } else
7459 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7460
890ca9ae
HY		 7461 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7462 GFP_KERNEL);
7463 if (!vcpu->arch.mce_banks) {
7464 r = -ENOMEM;
443c39bc 7465 goto fail_free_lapic;
890ca9ae
HY		 7466 }
7467 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7468
f1797359
WY		 7469 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7470 r = -ENOMEM;
f5f48ee1 7471 goto fail_free_mce_banks;
f1797359 7472 }
f5f48ee1 7473
d28bc9dd 7474 r = fx_init(vcpu, false);
66f7b72e
JS		 7475 if (r)
7476 goto fail_free_wbinvd_dirty_mask;
7477
ba904635 7478 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7479 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7480
7481 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7482 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7483
5a4f55cd
EK		 7484 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7485
74545705
RK		 7486 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7487
af585b92 7488 kvm_async_pf_hash_reset(vcpu);
f5132b01 7489 kvm_pmu_init(vcpu);
af585b92 7490
e9b11c17 7491 return 0;
66f7b72e
JS		 7492fail_free_wbinvd_dirty_mask:
7493 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7494fail_free_mce_banks:
7495 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7496fail_free_lapic:
7497 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7498fail_mmu_destroy:
7499 kvm_mmu_destroy(vcpu);
7500fail_free_pio_data:
ad312c7c 7501 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7502fail:
7503 return r;
7504}
7505
7506void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7507{
f656ce01
MT		 7508 int idx;
7509
f5132b01 7510 kvm_pmu_destroy(vcpu);
36cb93fd 7511 kfree(vcpu->arch.mce_banks);
e9b11c17 7512 kvm_free_lapic(vcpu);
f656ce01 7513 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7514 kvm_mmu_destroy(vcpu);
f656ce01 7515 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7516 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7517 if (!irqchip_in_kernel(vcpu->kvm))
7518 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7519}
d19a9cd2 7520
e790d9ef
RK		 7521void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7522{
ae97a3b8 7523 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7524}
7525
e08b9637 7526int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7527{
e08b9637
CO		 7528 if (type)
7529 return -EINVAL;
7530
6ef768fa 7531 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7532 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7533 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7534 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7535 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7536
5550af4d
SY		 7537 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7538 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7539 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7540 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7541 &kvm->arch.irq_sources_bitmap);
5550af4d 7542
038f8c11 7543 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7544 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7545 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7546
7547 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7548
7e44e449 7549 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7550 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7551
d89f5eff 7552 return 0;
d19a9cd2
ZX		 7553}
7554
7555static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7556{
9fc77441
MT		 7557 int r;
7558 r = vcpu_load(vcpu);
7559 BUG_ON(r);
d19a9cd2
ZX		 7560 kvm_mmu_unload(vcpu);
7561 vcpu_put(vcpu);
7562}
7563
7564static void kvm_free_vcpus(struct kvm *kvm)
7565{
7566 unsigned int i;
988a2cae 7567 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7568
7569 /*
7570 * Unpin any mmu pages first.
7571 */
af585b92
GN		 7572 kvm_for_each_vcpu(i, vcpu, kvm) {
7573 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7574 kvm_unload_vcpu_mmu(vcpu);
af585b92 7575 }
988a2cae
GN		 7576 kvm_for_each_vcpu(i, vcpu, kvm)
7577 kvm_arch_vcpu_free(vcpu);
7578
7579 mutex_lock(&kvm->lock);
7580 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7581 kvm->vcpus[i] = NULL;
d19a9cd2 7582
988a2cae
GN		 7583 atomic_set(&kvm->online_vcpus, 0);
7584 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7585}
7586
ad8ba2cd
SY		 7587void kvm_arch_sync_events(struct kvm *kvm)
7588{
332967a3 7589 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7590 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7591 kvm_free_all_assigned_devices(kvm);
aea924f6 7592 kvm_free_pit(kvm);
ad8ba2cd
SY		 7593}
7594
d19a9cd2
ZX		 7595void kvm_arch_destroy_vm(struct kvm *kvm)
7596{
27469d29
AH		 7597 if (current->mm == kvm->mm) {
7598 /*
7599 * Free memory regions allocated on behalf of userspace,
7600 * unless the the memory map has changed due to process exit
7601 * or fd copying.
7602 */
7603 struct kvm_userspace_memory_region mem;
7604 memset(&mem, 0, sizeof(mem));
7605 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7606 kvm_set_memory_region(kvm, &mem);
7607
7608 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7609 kvm_set_memory_region(kvm, &mem);
7610
7611 mem.slot = TSS_PRIVATE_MEMSLOT;
7612 kvm_set_memory_region(kvm, &mem);
7613 }
6eb55818 7614 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7615 kfree(kvm->arch.vpic);
7616 kfree(kvm->arch.vioapic);
d19a9cd2 7617 kvm_free_vcpus(kvm);
1e08ec4a 7618 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7619}
0de10343 7620
5587027c 7621void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7622 struct kvm_memory_slot *dont)
7623{
7624 int i;
7625
d89cc617
TY		 7626 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7627 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7628 kvfree(free->arch.rmap[i]);
d89cc617 7629 free->arch.rmap[i] = NULL;
77d11309 7630 }
d89cc617
TY		 7631 if (i == 0)
7632 continue;
7633
7634 if (!dont || free->arch.lpage_info[i - 1] !=
7635 dont->arch.lpage_info[i - 1]) {
548ef284 7636 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7637 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7638 }
7639 }
7640}
7641
5587027c
AK		 7642int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7643 unsigned long npages)
db3fe4eb
TY		 7644{
7645 int i;
7646
d89cc617 7647 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7648 unsigned long ugfn;
7649 int lpages;
d89cc617 7650 int level = i + 1;
db3fe4eb
TY		 7651
7652 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7653 slot->base_gfn, level) + 1;
7654
d89cc617
TY		 7655 slot->arch.rmap[i] =
7656 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7657 if (!slot->arch.rmap[i])
77d11309 7658 goto out_free;
d89cc617
TY		 7659 if (i == 0)
7660 continue;
77d11309 7661
d89cc617
TY		 7662 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7663 sizeof(*slot->arch.lpage_info[i - 1]));
7664 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7665 goto out_free;
7666
7667 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7668 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7669 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7670 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7671 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7672 /*
7673 * If the gfn and userspace address are not aligned wrt each
7674 * other, or if explicitly asked to, disable large page
7675 * support for this slot
7676 */
7677 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7678 !kvm_largepages_enabled()) {
7679 unsigned long j;
7680
7681 for (j = 0; j < lpages; ++j)
d89cc617 7682 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7683 }
7684 }
7685
7686 return 0;
7687
7688out_free:
d89cc617 7689 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7690 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7691 slot->arch.rmap[i] = NULL;
7692 if (i == 0)
7693 continue;
7694
548ef284 7695 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7696 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7697 }
7698 return -ENOMEM;
7699}
7700
15f46015 7701void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7702{
e6dff7d1
TY		 7703 /*
7704 * memslots->generation has been incremented.
7705 * mmio generation may have reached its maximum value.
7706 */
7707 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7708}
7709
f7784b8e
MT		 7710int kvm_arch_prepare_memory_region(struct kvm *kvm,
7711 struct kvm_memory_slot *memslot,
09170a49 7712 const struct kvm_userspace_memory_region *mem,
7b6195a9 7713 enum kvm_mr_change change)
0de10343 7714{
7a905b14
TY		 7715 /*
7716 * Only private memory slots need to be mapped here since
7717 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7718 */
7b6195a9 7719 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7720 unsigned long userspace_addr;
604b38ac 7721
7a905b14
TY		 7722 /*
7723 * MAP_SHARED to prevent internal slot pages from being moved
7724 * by fork()/COW.
7725 */
7b6195a9 7726 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7727 PROT_READ | PROT_WRITE,
7728 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7729
7a905b14
TY		 7730 if (IS_ERR((void *)userspace_addr))
7731 return PTR_ERR((void *)userspace_addr);
604b38ac 7732
7a905b14 7733 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7734 }
7735
f7784b8e
MT		 7736 return 0;
7737}
7738
88178fd4
KH		 7739static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7740 struct kvm_memory_slot *new)
7741{
7742 /* Still write protect RO slot */
7743 if (new->flags & KVM_MEM_READONLY) {
7744 kvm_mmu_slot_remove_write_access(kvm, new);
7745 return;
7746 }
7747
7748 /*
7749 * Call kvm_x86_ops dirty logging hooks when they are valid.
7750 *
7751 * kvm_x86_ops->slot_disable_log_dirty is called when:
7752 *
7753 * - KVM_MR_CREATE with dirty logging is disabled
7754 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7755 *
7756 * The reason is, in case of PML, we need to set D-bit for any slots
7757 * with dirty logging disabled in order to eliminate unnecessary GPA
7758 * logging in PML buffer (and potential PML buffer full VMEXT). This
7759 * guarantees leaving PML enabled during guest's lifetime won't have
7760 * any additonal overhead from PML when guest is running with dirty
7761 * logging disabled for memory slots.
7762 *
7763 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7764 * to dirty logging mode.
7765 *
7766 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7767 *
7768 * In case of write protect:
7769 *
7770 * Write protect all pages for dirty logging.
7771 *
7772 * All the sptes including the large sptes which point to this
7773 * slot are set to readonly. We can not create any new large
7774 * spte on this slot until the end of the logging.
7775 *
7776 * See the comments in fast_page_fault().
7777 */
7778 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7779 if (kvm_x86_ops->slot_enable_log_dirty)
7780 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7781 else
7782 kvm_mmu_slot_remove_write_access(kvm, new);
7783 } else {
7784 if (kvm_x86_ops->slot_disable_log_dirty)
7785 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7786 }
7787}
7788
f7784b8e 7789void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7790 const struct kvm_userspace_memory_region *mem,
8482644a 7791 const struct kvm_memory_slot *old,
f36f3f28 7792 const struct kvm_memory_slot *new,
8482644a 7793 enum kvm_mr_change change)
f7784b8e 7794{
8482644a 7795 int nr_mmu_pages = 0;
f7784b8e 7796
f36f3f28 7797 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 7798 int ret;
7799
8482644a
TY		 7800 ret = vm_munmap(old->userspace_addr,
7801 old->npages * PAGE_SIZE);
f7784b8e
MT		 7802 if (ret < 0)
7803 printk(KERN_WARNING
7804 "kvm_vm_ioctl_set_memory_region: "
7805 "failed to munmap memory\n");
7806 }
7807
48c0e4e9
XG		 7808 if (!kvm->arch.n_requested_mmu_pages)
7809 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7810
48c0e4e9 7811 if (nr_mmu_pages)
0de10343 7812 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7813
3ea3b7fa
WL		 7814 /*
7815 * Dirty logging tracks sptes in 4k granularity, meaning that large
7816 * sptes have to be split. If live migration is successful, the guest
7817 * in the source machine will be destroyed and large sptes will be
7818 * created in the destination. However, if the guest continues to run
7819 * in the source machine (for example if live migration fails), small
7820 * sptes will remain around and cause bad performance.
7821 *
7822 * Scan sptes if dirty logging has been stopped, dropping those
7823 * which can be collapsed into a single large-page spte. Later
7824 * page faults will create the large-page sptes.
7825 */
7826 if ((change != KVM_MR_DELETE) &&
7827 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7828 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7829 kvm_mmu_zap_collapsible_sptes(kvm, new);
7830
c972f3b1 7831 /*
88178fd4 7832 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7833 *
88178fd4
KH		 7834 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7835 * been zapped so no dirty logging staff is needed for old slot. For
7836 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7837 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7838 *
7839 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7840 */
88178fd4 7841 if (change != KVM_MR_DELETE)
f36f3f28 7842 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7843}
1d737c8a 7844
2df72e9b 7845void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7846{
6ca18b69 7847 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7848}
7849
2df72e9b
MT		 7850void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7851 struct kvm_memory_slot *slot)
7852{
6ca18b69 7853 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7854}
7855
1d737c8a
ZX		 7856int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7857{
b6b8a145
JK		 7858 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7859 kvm_x86_ops->check_nested_events(vcpu, false);
7860
af585b92
GN		 7861 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7862 !vcpu->arch.apf.halted)
7863 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7864 || kvm_apic_has_events(vcpu)
6aef266c 7865 || vcpu->arch.pv.pv_unhalted
7460fb4a 7866 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7867 (kvm_arch_interrupt_allowed(vcpu) &&
7868 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7869}
5736199a 7870
b6d33834 7871int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7872{
b6d33834 7873 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7874}
78646121
GN		 7875
7876int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7877{
7878 return kvm_x86_ops->interrupt_allowed(vcpu);
7879}
229456fc 7880
82b32774 7881unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7882{
82b32774
NA		 7883 if (is_64_bit_mode(vcpu))
7884 return kvm_rip_read(vcpu);
7885 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7886 kvm_rip_read(vcpu));
7887}
7888EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7889
82b32774
NA		 7890bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7891{
7892 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7893}
7894EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7895
94fe45da
JK		 7896unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7897{
7898 unsigned long rflags;
7899
7900 rflags = kvm_x86_ops->get_rflags(vcpu);
7901 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7902 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7903 return rflags;
7904}
7905EXPORT_SYMBOL_GPL(kvm_get_rflags);
7906
6addfc42 7907static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7908{
7909 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7910 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7911 rflags |= X86_EFLAGS_TF;
94fe45da 7912 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7913}
7914
7915void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7916{
7917 __kvm_set_rflags(vcpu, rflags);
3842d135 7918 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7919}
7920EXPORT_SYMBOL_GPL(kvm_set_rflags);
7921
56028d08
GN		 7922void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7923{
7924 int r;
7925
fb67e14f 7926 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7927 work->wakeup_all)
56028d08
GN		 7928 return;
7929
7930 r = kvm_mmu_reload(vcpu);
7931 if (unlikely(r))
7932 return;
7933
fb67e14f
XG		 7934 if (!vcpu->arch.mmu.direct_map &&
7935 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7936 return;
7937
56028d08
GN		 7938 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7939}
7940
af585b92
GN		 7941static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7942{
7943 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7944}
7945
7946static inline u32 kvm_async_pf_next_probe(u32 key)
7947{
7948 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7949}
7950
7951static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7952{
7953 u32 key = kvm_async_pf_hash_fn(gfn);
7954
7955 while (vcpu->arch.apf.gfns[key] != ~0)
7956 key = kvm_async_pf_next_probe(key);
7957
7958 vcpu->arch.apf.gfns[key] = gfn;
7959}
7960
7961static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7962{
7963 int i;
7964 u32 key = kvm_async_pf_hash_fn(gfn);
7965
7966 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7967 (vcpu->arch.apf.gfns[key] != gfn &&
7968 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7969 key = kvm_async_pf_next_probe(key);
7970
7971 return key;
7972}
7973
7974bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7975{
7976 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7977}
7978
7979static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7980{
7981 u32 i, j, k;
7982
7983 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7984 while (true) {
7985 vcpu->arch.apf.gfns[i] = ~0;
7986 do {
7987 j = kvm_async_pf_next_probe(j);
7988 if (vcpu->arch.apf.gfns[j] == ~0)
7989 return;
7990 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7991 /*
7992 * k lies cyclically in ]i,j]
7993 * | i.k.j |
7994 * |....j i.k.| or |.k..j i...|
7995 */
7996 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7997 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7998 i = j;
7999 }
8000}
8001
7c90705b
GN		 8002static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8003{
8004
8005 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8006 sizeof(val));
8007}
8008
af585b92
GN		 8009void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8010 struct kvm_async_pf *work)
8011{
6389ee94
AK		 8012 struct x86_exception fault;
8013
7c90705b 8014 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8015 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8016
8017 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8018 (vcpu->arch.apf.send_user_only &&
8019 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8020 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8021 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8022 fault.vector = PF_VECTOR;
8023 fault.error_code_valid = true;
8024 fault.error_code = 0;
8025 fault.nested_page_fault = false;
8026 fault.address = work->arch.token;
8027 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8028 }
af585b92
GN		 8029}
8030
8031void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8032 struct kvm_async_pf *work)
8033{
6389ee94
AK		 8034 struct x86_exception fault;
8035
7c90705b 8036 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8037 if (work->wakeup_all)
7c90705b
GN		 8038 work->arch.token = ~0; /* broadcast wakeup */
8039 else
8040 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8041
8042 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8043 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8044 fault.vector = PF_VECTOR;
8045 fault.error_code_valid = true;
8046 fault.error_code = 0;
8047 fault.nested_page_fault = false;
8048 fault.address = work->arch.token;
8049 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8050 }
e6d53e3b 8051 vcpu->arch.apf.halted = false;
a4fa1635 8052 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8053}
8054
8055bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8056{
8057 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8058 return true;
8059 else
8060 return !kvm_event_needs_reinjection(vcpu) &&
8061 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8062}
8063
e0f0bbc5
AW		 8064void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8065{
8066 atomic_inc(&kvm->arch.noncoherent_dma_count);
8067}
8068EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8069
8070void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8071{
8072 atomic_dec(&kvm->arch.noncoherent_dma_count);
8073}
8074EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8075
8076bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8077{
8078 return atomic_read(&kvm->arch.noncoherent_dma_count);
8079}
8080EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8081
229456fc
MT		 8082EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8083EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8084EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8085EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8086EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8087EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8088EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8089EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8090EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8091EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8092EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8093EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8094EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8095EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8096EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
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