projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
kvm: x86: fix comment about {mmu,nested_mmu}.gva_to_gpa
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
d91cab78 676 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 677 return 1;
d91cab78 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
d91cab78 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
d91cab78
DH		 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 692 return 1;
693
d91cab78
DH		 694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 696 return 1;
d91cab78 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 698 return 1;
699 }
42bdf991 700 kvm_put_guest_xcr0(vcpu);
2acf923e 701 vcpu->arch.xcr0 = xcr0;
56c103ec 702
d91cab78 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 704 kvm_update_cpuid(vcpu);
2acf923e
DC		 705 return 0;
706}
707
708int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709{
764bcbc5
Z		 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
a83b29c6 719int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 720{
fc78f519 721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
0f12244f
GN		 725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
a03490ed 727
2acf923e
DC		 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
c68b734f
YW		 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
97ec8c06
FW		 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
afcbf13f 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 738 return 1;
739
a03490ed 740 if (is_long_mode(vcpu)) {
0f12244f
GN		 741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
a2edf57f
AK		 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
0f12244f
GN		 747 return 1;
748
ad756a16
MJ		 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
5e1746d6 758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 759 return 1;
a03490ed 760
ad756a16
MJ		 761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 763 kvm_mmu_reset_context(vcpu);
0f12244f 764
2acf923e 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 766 kvm_update_cpuid(vcpu);
2acf923e 767
0f12244f
GN		 768 return 0;
769}
2d3ad1f4 770EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 771
2390218b 772int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 773{
ac146235 774#ifdef CONFIG_X86_64
9d88fca7 775 cr3 &= ~CR3_PCID_INVD;
ac146235 776#endif
9d88fca7 777
9f8fe504 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 779 kvm_mmu_sync_roots(vcpu);
77c3913b 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 781 return 0;
d835dfec
AK		 782 }
783
a03490ed 784 if (is_long_mode(vcpu)) {
d9f89b88
JK		 785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 789 return 1;
a03490ed 790
0f12244f 791 vcpu->arch.cr3 = cr3;
aff48baa 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 793 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 797
eea1cff9 798int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 799{
0f12244f
GN		 800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
35754c98 802 if (lapic_in_kernel(vcpu))
a03490ed
CO		 803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
ad312c7c 805 vcpu->arch.cr8 = cr8;
0f12244f
GN		 806 return 0;
807}
2d3ad1f4 808EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 809
2d3ad1f4 810unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 811{
35754c98 812 if (lapic_in_kernel(vcpu))
a03490ed
CO		 813 return kvm_lapic_get_cr8(vcpu);
814 else
ad312c7c 815 return vcpu->arch.cr8;
a03490ed 816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 818
ae561ede
NA		 819static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820{
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828}
829
73aaf249
JK		 830static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831{
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834}
835
c8639010
JK		 836static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837{
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 848}
849
6f43ed01
NA		 850static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851{
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857}
858
338dbc97 859static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 860{
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
020df079
GN		 868 /* fall through */
869 case 6:
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
6f43ed01 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 873 kvm_update_dr6(vcpu);
020df079
GN		 874 break;
875 case 5:
020df079
GN		 876 /* fall through */
877 default: /* 7 */
338dbc97
GN		 878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
020df079 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 881 kvm_update_dr7(vcpu);
020df079
GN		 882 break;
883 }
884
885 return 0;
886}
338dbc97
GN		 887
888int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889{
16f8a6f9 890 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 891 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 892 return 1;
893 }
894 return 0;
338dbc97 895}
020df079
GN		 896EXPORT_SYMBOL_GPL(kvm_set_dr);
897
16f8a6f9 898int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 899{
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
020df079
GN		 905 /* fall through */
906 case 6:
73aaf249
JK		 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 911 break;
912 case 5:
020df079
GN		 913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
338dbc97
GN		 918 return 0;
919}
020df079
GN		 920EXPORT_SYMBOL_GPL(kvm_get_dr);
921
022cd0e8
AK		 922bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923{
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
c6702c9d 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934}
935EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
043405e1
CO		 937/*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
e3267cbb 942 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
043405e1 945 */
e3267cbb 946
043405e1
CO		 947static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 949 MSR_STAR,
043405e1
CO		 950#ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952#endif
b3897a49 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 955};
956
957static unsigned num_msrs_to_save;
958
62ef68bb
PB		 959static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 966 HV_X64_MSR_RESET,
11c4b1ca 967 HV_X64_MSR_VP_INDEX,
9eec50b8 968 HV_X64_MSR_VP_RUNTIME,
5c919412 969 HV_X64_MSR_SCONTROL,
1f4b34f8 970 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 971 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
972 MSR_KVM_PV_EOI_EN,
973
ba904635 974 MSR_IA32_TSC_ADJUST,
a3e06bbe 975 MSR_IA32_TSCDEADLINE,
043405e1 976 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 977 MSR_IA32_MCG_STATUS,
978 MSR_IA32_MCG_CTL,
64d60670 979 MSR_IA32_SMBASE,
043405e1
CO		 980};
981
62ef68bb
PB		 982static unsigned num_emulated_msrs;
983
384bb783 984bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 985{
b69e8cae 986 if (efer & efer_reserved_bits)
384bb783 987 return false;
15c4a640 988
1b2fd70c
AG		 989 if (efer & EFER_FFXSR) {
990 struct kvm_cpuid_entry2 *feat;
991
992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 993 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 994 return false;
1b2fd70c
AG		 995 }
996
d8017474
AG		 997 if (efer & EFER_SVME) {
998 struct kvm_cpuid_entry2 *feat;
999
1000 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1001 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1002 return false;
d8017474
AG		 1003 }
1004
384bb783
JK		 1005 return true;
1006}
1007EXPORT_SYMBOL_GPL(kvm_valid_efer);
1008
1009static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1010{
1011 u64 old_efer = vcpu->arch.efer;
1012
1013 if (!kvm_valid_efer(vcpu, efer))
1014 return 1;
1015
1016 if (is_paging(vcpu)
1017 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1018 return 1;
1019
15c4a640 1020 efer &= ~EFER_LMA;
f6801dff 1021 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1022
a3d204e2
SY		 1023 kvm_x86_ops->set_efer(vcpu, efer);
1024
aad82703
SY		 1025 /* Update reserved bits */
1026 if ((efer ^ old_efer) & EFER_NX)
1027 kvm_mmu_reset_context(vcpu);
1028
b69e8cae 1029 return 0;
15c4a640
CO		 1030}
1031
f2b4b7dd
JR		 1032void kvm_enable_efer_bits(u64 mask)
1033{
1034 efer_reserved_bits &= ~mask;
1035}
1036EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037
15c4a640
CO		 1038/*
1039 * Writes msr value into into the appropriate "register".
1040 * Returns 0 on success, non-0 otherwise.
1041 * Assumes vcpu_load() was already called.
1042 */
8fe8ab46 1043int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1044{
854e8bb1
NA		 1045 switch (msr->index) {
1046 case MSR_FS_BASE:
1047 case MSR_GS_BASE:
1048 case MSR_KERNEL_GS_BASE:
1049 case MSR_CSTAR:
1050 case MSR_LSTAR:
1051 if (is_noncanonical_address(msr->data))
1052 return 1;
1053 break;
1054 case MSR_IA32_SYSENTER_EIP:
1055 case MSR_IA32_SYSENTER_ESP:
1056 /*
1057 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1058 * non-canonical address is written on Intel but not on
1059 * AMD (which ignores the top 32-bits, because it does
1060 * not implement 64-bit SYSENTER).
1061 *
1062 * 64-bit code should hence be able to write a non-canonical
1063 * value on AMD. Making the address canonical ensures that
1064 * vmentry does not fail on Intel after writing a non-canonical
1065 * value, and that something deterministic happens if the guest
1066 * invokes 64-bit SYSENTER.
1067 */
1068 msr->data = get_canonical(msr->data);
1069 }
8fe8ab46 1070 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1071}
854e8bb1 1072EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1073
313a3dc7
CO		 1074/*
1075 * Adapt set_msr() to msr_io()'s calling convention
1076 */
609e36d3
PB		 1077static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078{
1079 struct msr_data msr;
1080 int r;
1081
1082 msr.index = index;
1083 msr.host_initiated = true;
1084 r = kvm_get_msr(vcpu, &msr);
1085 if (r)
1086 return r;
1087
1088 *data = msr.data;
1089 return 0;
1090}
1091
313a3dc7
CO		 1092static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1093{
8fe8ab46
WA		 1094 struct msr_data msr;
1095
1096 msr.data = *data;
1097 msr.index = index;
1098 msr.host_initiated = true;
1099 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1100}
1101
16e8d74d
MT		 1102#ifdef CONFIG_X86_64
1103struct pvclock_gtod_data {
1104 seqcount_t seq;
1105
1106 struct { /* extract of a clocksource struct */
1107 int vclock_mode;
1108 cycle_t cycle_last;
1109 cycle_t mask;
1110 u32 mult;
1111 u32 shift;
1112 } clock;
1113
cbcf2dd3
TG		 1114 u64 boot_ns;
1115 u64 nsec_base;
16e8d74d
MT		 1116};
1117
1118static struct pvclock_gtod_data pvclock_gtod_data;
1119
1120static void update_pvclock_gtod(struct timekeeper *tk)
1121{
1122 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1123 u64 boot_ns;
1124
876e7881 1125 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1126
1127 write_seqcount_begin(&vdata->seq);
1128
1129 /* copy pvclock gtod data */
876e7881
PZ		 1130 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1131 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1132 vdata->clock.mask = tk->tkr_mono.mask;
1133 vdata->clock.mult = tk->tkr_mono.mult;
1134 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1135
cbcf2dd3 1136 vdata->boot_ns = boot_ns;
876e7881 1137 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1138
1139 write_seqcount_end(&vdata->seq);
1140}
1141#endif
1142
bab5bb39
NK		 1143void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144{
1145 /*
1146 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1147 * vcpu_enter_guest. This function is only called from
1148 * the physical CPU that is running vcpu.
1149 */
1150 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151}
16e8d74d 1152
18068523
GOC		 1153static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1154{
9ed3c444
AK		 1155 int version;
1156 int r;
50d0a0f9 1157 struct pvclock_wall_clock wc;
923de3cf 1158 struct timespec boot;
18068523
GOC		 1159
1160 if (!wall_clock)
1161 return;
1162
9ed3c444
AK		 1163 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1164 if (r)
1165 return;
1166
1167 if (version & 1)
1168 ++version; /* first time write, random junk */
1169
1170 ++version;
18068523 1171
18068523
GOC		 1172 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1173
50d0a0f9
GH		 1174 /*
1175 * The guest calculates current wall clock time by adding
34c238a1 1176 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1177 * wall clock specified here. guest system time equals host
1178 * system time for us, thus we must fill in host boot time here.
1179 */
923de3cf 1180 getboottime(&boot);
50d0a0f9 1181
4b648665
BR		 1182 if (kvm->arch.kvmclock_offset) {
1183 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1184 boot = timespec_sub(boot, ts);
1185 }
50d0a0f9
GH		 1186 wc.sec = boot.tv_sec;
1187 wc.nsec = boot.tv_nsec;
1188 wc.version = version;
18068523
GOC		 1189
1190 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1191
1192 version++;
1193 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1194}
1195
50d0a0f9
GH		 1196static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1197{
1198 uint32_t quotient, remainder;
1199
1200 /* Don't try to replace with do_div(), this one calculates
1201 * "(dividend << 32) / divisor" */
1202 __asm__ ( "divl %4"
1203 : "=a" (quotient), "=d" (remainder)
1204 : "0" (0), "1" (dividend), "r" (divisor) );
1205 return quotient;
1206}
1207
5f4e3f88
ZA		 1208static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1209 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1210{
5f4e3f88 1211 uint64_t scaled64;
50d0a0f9
GH		 1212 int32_t shift = 0;
1213 uint64_t tps64;
1214 uint32_t tps32;
1215
5f4e3f88
ZA		 1216 tps64 = base_khz * 1000LL;
1217 scaled64 = scaled_khz * 1000LL;
50933623 1218 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1219 tps64 >>= 1;
1220 shift--;
1221 }
1222
1223 tps32 = (uint32_t)tps64;
50933623
JK		 1224 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1225 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1226 scaled64 >>= 1;
1227 else
1228 tps32 <<= 1;
50d0a0f9
GH		 1229 shift++;
1230 }
1231
5f4e3f88
ZA		 1232 *pshift = shift;
1233 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1234
5f4e3f88
ZA		 1235 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1236 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1237}
1238
d828199e 1239#ifdef CONFIG_X86_64
16e8d74d 1240static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1241#endif
16e8d74d 1242
c8076604 1243static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1244static unsigned long max_tsc_khz;
c8076604 1245
cc578287 1246static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1247{
cc578287
ZA		 1248 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1249 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1250}
1251
cc578287 1252static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1253{
cc578287
ZA		 1254 u64 v = (u64)khz * (1000000 + ppm);
1255 do_div(v, 1000000);
1256 return v;
1e993611
JR		 1257}
1258
381d585c
HZ		 1259static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1260{
1261 u64 ratio;
1262
1263 /* Guest TSC same frequency as host TSC? */
1264 if (!scale) {
1265 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1266 return 0;
1267 }
1268
1269 /* TSC scaling supported? */
1270 if (!kvm_has_tsc_control) {
1271 if (user_tsc_khz > tsc_khz) {
1272 vcpu->arch.tsc_catchup = 1;
1273 vcpu->arch.tsc_always_catchup = 1;
1274 return 0;
1275 } else {
1276 WARN(1, "user requested TSC rate below hardware speed\n");
1277 return -1;
1278 }
1279 }
1280
1281 /* TSC scaling required - calculate ratio */
1282 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1283 user_tsc_khz, tsc_khz);
1284
1285 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1286 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1287 user_tsc_khz);
1288 return -1;
1289 }
1290
1291 vcpu->arch.tsc_scaling_ratio = ratio;
1292 return 0;
1293}
1294
1295static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1296{
cc578287
ZA		 1297 u32 thresh_lo, thresh_hi;
1298 int use_scaling = 0;
217fc9cf 1299
03ba32ca 1300 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1301 if (this_tsc_khz == 0) {
1302 /* set tsc_scaling_ratio to a safe value */
1303 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1304 return -1;
ad721883 1305 }
03ba32ca 1306
c285545f
ZA		 1307 /* Compute a scale to convert nanoseconds in TSC cycles */
1308 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1309 &vcpu->arch.virtual_tsc_shift,
1310 &vcpu->arch.virtual_tsc_mult);
1311 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1312
1313 /*
1314 * Compute the variation in TSC rate which is acceptable
1315 * within the range of tolerance and decide if the
1316 * rate being applied is within that bounds of the hardware
1317 * rate. If so, no scaling or compensation need be done.
1318 */
1319 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1320 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1321 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1322 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1323 use_scaling = 1;
1324 }
381d585c 1325 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1326}
1327
1328static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1329{
e26101b1 1330 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1331 vcpu->arch.virtual_tsc_mult,
1332 vcpu->arch.virtual_tsc_shift);
e26101b1 1333 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1334 return tsc;
1335}
1336
69b0049a 1337static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1338{
1339#ifdef CONFIG_X86_64
1340 bool vcpus_matched;
b48aa97e
MT		 1341 struct kvm_arch *ka = &vcpu->kvm->arch;
1342 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1343
1344 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1345 atomic_read(&vcpu->kvm->online_vcpus));
1346
7f187922
MT		 1347 /*
1348 * Once the masterclock is enabled, always perform request in
1349 * order to update it.
1350 *
1351 * In order to enable masterclock, the host clocksource must be TSC
1352 * and the vcpus need to have matched TSCs. When that happens,
1353 * perform request to enable masterclock.
1354 */
1355 if (ka->use_master_clock ||
1356 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1357 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1358
1359 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1360 atomic_read(&vcpu->kvm->online_vcpus),
1361 ka->use_master_clock, gtod->clock.vclock_mode);
1362#endif
1363}
1364
ba904635
WA		 1365static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1366{
1367 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1368 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1369}
1370
35181e86
HZ		 1371/*
1372 * Multiply tsc by a fixed point number represented by ratio.
1373 *
1374 * The most significant 64-N bits (mult) of ratio represent the
1375 * integral part of the fixed point number; the remaining N bits
1376 * (frac) represent the fractional part, ie. ratio represents a fixed
1377 * point number (mult + frac * 2^(-N)).
1378 *
1379 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1380 */
1381static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1382{
1383 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1384}
1385
1386u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1387{
1388 u64 _tsc = tsc;
1389 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1390
1391 if (ratio != kvm_default_tsc_scaling_ratio)
1392 _tsc = __scale_tsc(ratio, tsc);
1393
1394 return _tsc;
1395}
1396EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1397
07c1419a
HZ		 1398static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1399{
1400 u64 tsc;
1401
1402 tsc = kvm_scale_tsc(vcpu, rdtsc());
1403
1404 return target_tsc - tsc;
1405}
1406
4ba76538
HZ		 1407u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1408{
1409 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1410}
1411EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1412
8fe8ab46 1413void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1414{
1415 struct kvm *kvm = vcpu->kvm;
f38e098f 1416 u64 offset, ns, elapsed;
99e3e30a 1417 unsigned long flags;
02626b6a 1418 s64 usdiff;
b48aa97e 1419 bool matched;
0d3da0d2 1420 bool already_matched;
8fe8ab46 1421 u64 data = msr->data;
99e3e30a 1422
038f8c11 1423 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1424 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1425 ns = get_kernel_ns();
f38e098f 1426 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1427
03ba32ca 1428 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1429 int faulted = 0;
1430
03ba32ca
MT		 1431 /* n.b - signed multiplication and division required */
1432 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1433#ifdef CONFIG_X86_64
03ba32ca 1434 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1435#else
03ba32ca 1436 /* do_div() only does unsigned */
8915aa27
MT		 1437 asm("1: idivl %[divisor]\n"
1438 "2: xor %%edx, %%edx\n"
1439 " movl $0, %[faulted]\n"
1440 "3:\n"
1441 ".section .fixup,\"ax\"\n"
1442 "4: movl $1, %[faulted]\n"
1443 " jmp 3b\n"
1444 ".previous\n"
1445
1446 _ASM_EXTABLE(1b, 4b)
1447
1448 : "=A"(usdiff), [faulted] "=r" (faulted)
1449 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1450
5d3cb0f6 1451#endif
03ba32ca
MT		 1452 do_div(elapsed, 1000);
1453 usdiff -= elapsed;
1454 if (usdiff < 0)
1455 usdiff = -usdiff;
8915aa27
MT		 1456
1457 /* idivl overflow => difference is larger than USEC_PER_SEC */
1458 if (faulted)
1459 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1460 } else
1461 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1462
1463 /*
5d3cb0f6
ZA		 1464 * Special case: TSC write with a small delta (1 second) of virtual
1465 * cycle time against real time is interpreted as an attempt to
1466 * synchronize the CPU.
1467 *
1468 * For a reliable TSC, we can match TSC offsets, and for an unstable
1469 * TSC, we add elapsed time in this computation. We could let the
1470 * compensation code attempt to catch up if we fall behind, but
1471 * it's better to try to match offsets from the beginning.
1472 */
02626b6a 1473 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1474 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1475 if (!check_tsc_unstable()) {
e26101b1 1476 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1477 pr_debug("kvm: matched tsc offset for %llu\n", data);
1478 } else {
857e4099 1479 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1480 data += delta;
07c1419a 1481 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1482 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1483 }
b48aa97e 1484 matched = true;
0d3da0d2 1485 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1486 } else {
1487 /*
1488 * We split periods of matched TSC writes into generations.
1489 * For each generation, we track the original measured
1490 * nanosecond time, offset, and write, so if TSCs are in
1491 * sync, we can match exact offset, and if not, we can match
4a969980 1492 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1493 *
1494 * These values are tracked in kvm->arch.cur_xxx variables.
1495 */
1496 kvm->arch.cur_tsc_generation++;
1497 kvm->arch.cur_tsc_nsec = ns;
1498 kvm->arch.cur_tsc_write = data;
1499 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1500 matched = false;
0d3da0d2 1501 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1502 kvm->arch.cur_tsc_generation, data);
f38e098f 1503 }
e26101b1
ZA		 1504
1505 /*
1506 * We also track th most recent recorded KHZ, write and time to
1507 * allow the matching interval to be extended at each write.
1508 */
f38e098f
ZA		 1509 kvm->arch.last_tsc_nsec = ns;
1510 kvm->arch.last_tsc_write = data;
5d3cb0f6 1511 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1512
b183aa58 1513 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1514
1515 /* Keep track of which generation this VCPU has synchronized to */
1516 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1517 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1518 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1519
ba904635
WA		 1520 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1521 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1522 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1523 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1524
1525 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1526 if (!matched) {
b48aa97e 1527 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1528 } else if (!already_matched) {
1529 kvm->arch.nr_vcpus_matched_tsc++;
1530 }
b48aa97e
MT		 1531
1532 kvm_track_tsc_matching(vcpu);
1533 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1534}
e26101b1 1535
99e3e30a
ZA		 1536EXPORT_SYMBOL_GPL(kvm_write_tsc);
1537
58ea6767
HZ		 1538static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1539 s64 adjustment)
1540{
1541 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1542}
1543
1544static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1545{
1546 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1547 WARN_ON(adjustment < 0);
1548 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1549 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1550}
1551
d828199e
MT		 1552#ifdef CONFIG_X86_64
1553
1554static cycle_t read_tsc(void)
1555{
03b9730b
AL		 1556 cycle_t ret = (cycle_t)rdtsc_ordered();
1557 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1558
1559 if (likely(ret >= last))
1560 return ret;
1561
1562 /*
1563 * GCC likes to generate cmov here, but this branch is extremely
1564 * predictable (it's just a funciton of time and the likely is
1565 * very likely) and there's a data dependence, so force GCC
1566 * to generate a branch instead. I don't barrier() because
1567 * we don't actually need a barrier, and if this function
1568 * ever gets inlined it will generate worse code.
1569 */
1570 asm volatile ("");
1571 return last;
1572}
1573
1574static inline u64 vgettsc(cycle_t *cycle_now)
1575{
1576 long v;
1577 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1578
1579 *cycle_now = read_tsc();
1580
1581 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1582 return v * gtod->clock.mult;
1583}
1584
cbcf2dd3 1585static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1586{
cbcf2dd3 1587 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1588 unsigned long seq;
d828199e 1589 int mode;
cbcf2dd3 1590 u64 ns;
d828199e 1591
d828199e
MT		 1592 do {
1593 seq = read_seqcount_begin(&gtod->seq);
1594 mode = gtod->clock.vclock_mode;
cbcf2dd3 1595 ns = gtod->nsec_base;
d828199e
MT		 1596 ns += vgettsc(cycle_now);
1597 ns >>= gtod->clock.shift;
cbcf2dd3 1598 ns += gtod->boot_ns;
d828199e 1599 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1600 *t = ns;
d828199e
MT		 1601
1602 return mode;
1603}
1604
1605/* returns true if host is using tsc clocksource */
1606static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1607{
d828199e
MT		 1608 /* checked again under seqlock below */
1609 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1610 return false;
1611
cbcf2dd3 1612 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1613}
1614#endif
1615
1616/*
1617 *
b48aa97e
MT		 1618 * Assuming a stable TSC across physical CPUS, and a stable TSC
1619 * across virtual CPUs, the following condition is possible.
1620 * Each numbered line represents an event visible to both
d828199e
MT		 1621 * CPUs at the next numbered event.
1622 *
1623 * "timespecX" represents host monotonic time. "tscX" represents
1624 * RDTSC value.
1625 *
1626 * VCPU0 on CPU0 | VCPU1 on CPU1
1627 *
1628 * 1. read timespec0,tsc0
1629 * 2. | timespec1 = timespec0 + N
1630 * | tsc1 = tsc0 + M
1631 * 3. transition to guest | transition to guest
1632 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1633 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1634 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1635 *
1636 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1637 *
1638 * - ret0 < ret1
1639 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1640 * ...
1641 * - 0 < N - M => M < N
1642 *
1643 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1644 * always the case (the difference between two distinct xtime instances
1645 * might be smaller then the difference between corresponding TSC reads,
1646 * when updating guest vcpus pvclock areas).
1647 *
1648 * To avoid that problem, do not allow visibility of distinct
1649 * system_timestamp/tsc_timestamp values simultaneously: use a master
1650 * copy of host monotonic time values. Update that master copy
1651 * in lockstep.
1652 *
b48aa97e 1653 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1654 *
1655 */
1656
1657static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1658{
1659#ifdef CONFIG_X86_64
1660 struct kvm_arch *ka = &kvm->arch;
1661 int vclock_mode;
b48aa97e
MT		 1662 bool host_tsc_clocksource, vcpus_matched;
1663
1664 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1665 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1666
1667 /*
1668 * If the host uses TSC clock, then passthrough TSC as stable
1669 * to the guest.
1670 */
b48aa97e 1671 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1672 &ka->master_kernel_ns,
1673 &ka->master_cycle_now);
1674
16a96021 1675 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1676 && !backwards_tsc_observed
1677 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1678
d828199e
MT		 1679 if (ka->use_master_clock)
1680 atomic_set(&kvm_guest_has_master_clock, 1);
1681
1682 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1683 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1684 vcpus_matched);
d828199e
MT		 1685#endif
1686}
1687
2e762ff7
MT		 1688static void kvm_gen_update_masterclock(struct kvm *kvm)
1689{
1690#ifdef CONFIG_X86_64
1691 int i;
1692 struct kvm_vcpu *vcpu;
1693 struct kvm_arch *ka = &kvm->arch;
1694
1695 spin_lock(&ka->pvclock_gtod_sync_lock);
1696 kvm_make_mclock_inprogress_request(kvm);
1697 /* no guest entries from this point */
1698 pvclock_update_vm_gtod_copy(kvm);
1699
1700 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1701 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1702
1703 /* guest entries allowed */
1704 kvm_for_each_vcpu(i, vcpu, kvm)
1705 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1706
1707 spin_unlock(&ka->pvclock_gtod_sync_lock);
1708#endif
1709}
1710
34c238a1 1711static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1712{
27cca94e 1713 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1714 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1715 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1716 s64 kernel_ns;
d828199e 1717 u64 tsc_timestamp, host_tsc;
0b79459b 1718 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1719 u8 pvclock_flags;
d828199e
MT		 1720 bool use_master_clock;
1721
1722 kernel_ns = 0;
1723 host_tsc = 0;
18068523 1724
d828199e
MT		 1725 /*
1726 * If the host uses TSC clock, then passthrough TSC as stable
1727 * to the guest.
1728 */
1729 spin_lock(&ka->pvclock_gtod_sync_lock);
1730 use_master_clock = ka->use_master_clock;
1731 if (use_master_clock) {
1732 host_tsc = ka->master_cycle_now;
1733 kernel_ns = ka->master_kernel_ns;
1734 }
1735 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1736
1737 /* Keep irq disabled to prevent changes to the clock */
1738 local_irq_save(flags);
89cbc767 1739 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1740 if (unlikely(this_tsc_khz == 0)) {
1741 local_irq_restore(flags);
1742 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1743 return 1;
1744 }
d828199e 1745 if (!use_master_clock) {
4ea1636b 1746 host_tsc = rdtsc();
d828199e
MT		 1747 kernel_ns = get_kernel_ns();
1748 }
1749
4ba76538 1750 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1751
c285545f
ZA		 1752 /*
1753 * We may have to catch up the TSC to match elapsed wall clock
1754 * time for two reasons, even if kvmclock is used.
1755 * 1) CPU could have been running below the maximum TSC rate
1756 * 2) Broken TSC compensation resets the base at each VCPU
1757 * entry to avoid unknown leaps of TSC even when running
1758 * again on the same CPU. This may cause apparent elapsed
1759 * time to disappear, and the guest to stand still or run
1760 * very slowly.
1761 */
1762 if (vcpu->tsc_catchup) {
1763 u64 tsc = compute_guest_tsc(v, kernel_ns);
1764 if (tsc > tsc_timestamp) {
f1e2b260 1765 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1766 tsc_timestamp = tsc;
1767 }
50d0a0f9
GH		 1768 }
1769
18068523
GOC		 1770 local_irq_restore(flags);
1771
0b79459b 1772 if (!vcpu->pv_time_enabled)
c285545f 1773 return 0;
18068523 1774
e48672fa 1775 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1776 tgt_tsc_khz = kvm_has_tsc_control ?
1777 vcpu->virtual_tsc_khz : this_tsc_khz;
1778 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1779 &vcpu->hv_clock.tsc_shift,
1780 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1781 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1782 }
1783
1784 /* With all the info we got, fill in the values */
1d5f066e 1785 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1786 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1787 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1788
09a0c3f1
OH		 1789 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1790 &guest_hv_clock, sizeof(guest_hv_clock))))
1791 return 0;
1792
5dca0d91
RK		 1793 /* This VCPU is paused, but it's legal for a guest to read another
1794 * VCPU's kvmclock, so we really have to follow the specification where
1795 * it says that version is odd if data is being modified, and even after
1796 * it is consistent.
1797 *
1798 * Version field updates must be kept separate. This is because
1799 * kvm_write_guest_cached might use a "rep movs" instruction, and
1800 * writes within a string instruction are weakly ordered. So there
1801 * are three writes overall.
1802 *
1803 * As a small optimization, only write the version field in the first
1804 * and third write. The vcpu->pv_time cache is still valid, because the
1805 * version field is the first in the struct.
18068523 1806 */
5dca0d91
RK		 1807 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1808
1809 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1810 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1811 &vcpu->hv_clock,
1812 sizeof(vcpu->hv_clock.version));
1813
1814 smp_wmb();
78c0337a
MT		 1815
1816 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1817 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1818
1819 if (vcpu->pvclock_set_guest_stopped_request) {
1820 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1821 vcpu->pvclock_set_guest_stopped_request = false;
1822 }
1823
d828199e
MT		 1824 /* If the host uses TSC clocksource, then it is stable */
1825 if (use_master_clock)
1826 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1827
78c0337a
MT		 1828 vcpu->hv_clock.flags = pvclock_flags;
1829
ce1a5e60
DM		 1830 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1831
0b79459b
AH		 1832 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1833 &vcpu->hv_clock,
1834 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1835
1836 smp_wmb();
1837
1838 vcpu->hv_clock.version++;
1839 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1840 &vcpu->hv_clock,
1841 sizeof(vcpu->hv_clock.version));
8cfdc000 1842 return 0;
c8076604
GH		 1843}
1844
0061d53d
MT		 1845/*
1846 * kvmclock updates which are isolated to a given vcpu, such as
1847 * vcpu->cpu migration, should not allow system_timestamp from
1848 * the rest of the vcpus to remain static. Otherwise ntp frequency
1849 * correction applies to one vcpu's system_timestamp but not
1850 * the others.
1851 *
1852 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1853 * We need to rate-limit these requests though, as they can
1854 * considerably slow guests that have a large number of vcpus.
1855 * The time for a remote vcpu to update its kvmclock is bound
1856 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1857 */
1858
7e44e449
AJ		 1859#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1860
1861static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1862{
1863 int i;
7e44e449
AJ		 1864 struct delayed_work *dwork = to_delayed_work(work);
1865 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1866 kvmclock_update_work);
1867 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1868 struct kvm_vcpu *vcpu;
1869
1870 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1871 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1872 kvm_vcpu_kick(vcpu);
1873 }
1874}
1875
7e44e449
AJ		 1876static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1877{
1878 struct kvm *kvm = v->kvm;
1879
105b21bb 1880 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1881 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1882 KVMCLOCK_UPDATE_DELAY);
1883}
1884
332967a3
AJ		 1885#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1886
1887static void kvmclock_sync_fn(struct work_struct *work)
1888{
1889 struct delayed_work *dwork = to_delayed_work(work);
1890 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1891 kvmclock_sync_work);
1892 struct kvm *kvm = container_of(ka, struct kvm, arch);
1893
630994b3
MT		 1894 if (!kvmclock_periodic_sync)
1895 return;
1896
332967a3
AJ		 1897 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1898 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1899 KVMCLOCK_SYNC_PERIOD);
1900}
1901
890ca9ae 1902static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1903{
890ca9ae
HY		 1904 u64 mcg_cap = vcpu->arch.mcg_cap;
1905 unsigned bank_num = mcg_cap & 0xff;
1906
15c4a640 1907 switch (msr) {
15c4a640 1908 case MSR_IA32_MCG_STATUS:
890ca9ae 1909 vcpu->arch.mcg_status = data;
15c4a640 1910 break;
c7ac679c 1911 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1912 if (!(mcg_cap & MCG_CTL_P))
1913 return 1;
1914 if (data != 0 && data != ~(u64)0)
1915 return -1;
1916 vcpu->arch.mcg_ctl = data;
1917 break;
1918 default:
1919 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1920 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1921 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1922 /* only 0 or all 1s can be written to IA32_MCi_CTL
1923 * some Linux kernels though clear bit 10 in bank 4 to
1924 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1925 * this to avoid an uncatched #GP in the guest
1926 */
890ca9ae 1927 if ((offset & 0x3) == 0 &&
114be429 1928 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1929 return -1;
1930 vcpu->arch.mce_banks[offset] = data;
1931 break;
1932 }
1933 return 1;
1934 }
1935 return 0;
1936}
1937
ffde22ac
ES		 1938static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1939{
1940 struct kvm *kvm = vcpu->kvm;
1941 int lm = is_long_mode(vcpu);
1942 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1943 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1944 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1945 : kvm->arch.xen_hvm_config.blob_size_32;
1946 u32 page_num = data & ~PAGE_MASK;
1947 u64 page_addr = data & PAGE_MASK;
1948 u8 *page;
1949 int r;
1950
1951 r = -E2BIG;
1952 if (page_num >= blob_size)
1953 goto out;
1954 r = -ENOMEM;
ff5c2c03
SL		 1955 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1956 if (IS_ERR(page)) {
1957 r = PTR_ERR(page);
ffde22ac 1958 goto out;
ff5c2c03 1959 }
54bf36aa 1960 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1961 goto out_free;
1962 r = 0;
1963out_free:
1964 kfree(page);
1965out:
1966 return r;
1967}
1968
344d9588
GN		 1969static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1970{
1971 gpa_t gpa = data & ~0x3f;
1972
4a969980 1973 /* Bits 2:5 are reserved, Should be zero */
6adba527 1974 if (data & 0x3c)
344d9588
GN		 1975 return 1;
1976
1977 vcpu->arch.apf.msr_val = data;
1978
1979 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1980 kvm_clear_async_pf_completion_queue(vcpu);
1981 kvm_async_pf_hash_reset(vcpu);
1982 return 0;
1983 }
1984
8f964525
AH		 1985 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1986 sizeof(u32)))
344d9588
GN		 1987 return 1;
1988
6adba527 1989 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1990 kvm_async_pf_wakeup_all(vcpu);
1991 return 0;
1992}
1993
12f9a48f
GC		 1994static void kvmclock_reset(struct kvm_vcpu *vcpu)
1995{
0b79459b 1996 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1997}
1998
c9aaa895
GC		 1999static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2000{
2001 u64 delta;
2002
2003 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2004 return;
2005
2006 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2007 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2008 vcpu->arch.st.accum_steal = delta;
2009}
2010
2011static void record_steal_time(struct kvm_vcpu *vcpu)
2012{
7cae2bed
MT		 2013 accumulate_steal_time(vcpu);
2014
c9aaa895
GC		 2015 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2016 return;
2017
2018 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2019 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2020 return;
2021
2022 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2023 vcpu->arch.st.steal.version += 2;
2024 vcpu->arch.st.accum_steal = 0;
2025
2026 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2027 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2028}
2029
8fe8ab46 2030int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2031{
5753785f 2032 bool pr = false;
8fe8ab46
WA		 2033 u32 msr = msr_info->index;
2034 u64 data = msr_info->data;
5753785f 2035
15c4a640 2036 switch (msr) {
2e32b719
BP		 2037 case MSR_AMD64_NB_CFG:
2038 case MSR_IA32_UCODE_REV:
2039 case MSR_IA32_UCODE_WRITE:
2040 case MSR_VM_HSAVE_PA:
2041 case MSR_AMD64_PATCH_LOADER:
2042 case MSR_AMD64_BU_CFG2:
2043 break;
2044
15c4a640 2045 case MSR_EFER:
b69e8cae 2046 return set_efer(vcpu, data);
8f1589d9
AP		 2047 case MSR_K7_HWCR:
2048 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2049 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2050 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2051 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2052 if (data != 0) {
a737f256
CD		 2053 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2054 data);
8f1589d9
AP		 2055 return 1;
2056 }
15c4a640 2057 break;
f7c6d140
AP		 2058 case MSR_FAM10H_MMIO_CONF_BASE:
2059 if (data != 0) {
a737f256
CD		 2060 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2061 "0x%llx\n", data);
f7c6d140
AP		 2062 return 1;
2063 }
15c4a640 2064 break;
b5e2fec0
AG		 2065 case MSR_IA32_DEBUGCTLMSR:
2066 if (!data) {
2067 /* We support the non-activated case already */
2068 break;
2069 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2070 /* Values other than LBR and BTF are vendor-specific,
2071 thus reserved and should throw a #GP */
2072 return 1;
2073 }
a737f256
CD		 2074 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2075 __func__, data);
b5e2fec0 2076 break;
9ba075a6 2077 case 0x200 ... 0x2ff:
ff53604b 2078 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2079 case MSR_IA32_APICBASE:
58cb628d 2080 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2081 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2082 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2083 case MSR_IA32_TSCDEADLINE:
2084 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2085 break;
ba904635
WA		 2086 case MSR_IA32_TSC_ADJUST:
2087 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2088 if (!msr_info->host_initiated) {
d913b904 2089 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2090 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2091 }
2092 vcpu->arch.ia32_tsc_adjust_msr = data;
2093 }
2094 break;
15c4a640 2095 case MSR_IA32_MISC_ENABLE:
ad312c7c 2096 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2097 break;
64d60670
PB		 2098 case MSR_IA32_SMBASE:
2099 if (!msr_info->host_initiated)
2100 return 1;
2101 vcpu->arch.smbase = data;
2102 break;
11c6bffa 2103 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2104 case MSR_KVM_WALL_CLOCK:
2105 vcpu->kvm->arch.wall_clock = data;
2106 kvm_write_wall_clock(vcpu->kvm, data);
2107 break;
11c6bffa 2108 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2109 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2110 u64 gpa_offset;
54750f2c
MT		 2111 struct kvm_arch *ka = &vcpu->kvm->arch;
2112
12f9a48f 2113 kvmclock_reset(vcpu);
18068523 2114
54750f2c
MT		 2115 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2116 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2117
2118 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2119 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2120 &vcpu->requests);
2121
2122 ka->boot_vcpu_runs_old_kvmclock = tmp;
2123 }
2124
18068523 2125 vcpu->arch.time = data;
0061d53d 2126 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2127
2128 /* we verify if the enable bit is set... */
2129 if (!(data & 1))
2130 break;
2131
0b79459b 2132 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2133
0b79459b 2134 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2135 &vcpu->arch.pv_time, data & ~1ULL,
2136 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2137 vcpu->arch.pv_time_enabled = false;
2138 else
2139 vcpu->arch.pv_time_enabled = true;
32cad84f 2140
18068523
GOC		 2141 break;
2142 }
344d9588
GN		 2143 case MSR_KVM_ASYNC_PF_EN:
2144 if (kvm_pv_enable_async_pf(vcpu, data))
2145 return 1;
2146 break;
c9aaa895
GC		 2147 case MSR_KVM_STEAL_TIME:
2148
2149 if (unlikely(!sched_info_on()))
2150 return 1;
2151
2152 if (data & KVM_STEAL_RESERVED_MASK)
2153 return 1;
2154
2155 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2156 data & KVM_STEAL_VALID_BITS,
2157 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2158 return 1;
2159
2160 vcpu->arch.st.msr_val = data;
2161
2162 if (!(data & KVM_MSR_ENABLED))
2163 break;
2164
c9aaa895
GC		 2165 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2166
2167 break;
ae7a2a3f
MT		 2168 case MSR_KVM_PV_EOI_EN:
2169 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2170 return 1;
2171 break;
c9aaa895 2172
890ca9ae
HY		 2173 case MSR_IA32_MCG_CTL:
2174 case MSR_IA32_MCG_STATUS:
81760dcc 2175 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2176 return set_msr_mce(vcpu, msr, data);
71db6023 2177
6912ac32
WH		 2178 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2179 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2180 pr = true; /* fall through */
2181 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2182 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2183 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2184 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2185
2186 if (pr || data != 0)
a737f256
CD		 2187 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2188 "0x%x data 0x%llx\n", msr, data);
5753785f 2189 break;
84e0cefa
JS		 2190 case MSR_K7_CLK_CTL:
2191 /*
2192 * Ignore all writes to this no longer documented MSR.
2193 * Writes are only relevant for old K7 processors,
2194 * all pre-dating SVM, but a recommended workaround from
4a969980 2195 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2196 * affected processor models on the command line, hence
2197 * the need to ignore the workaround.
2198 */
2199 break;
55cd8e5a 2200 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2201 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2202 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2203 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2204 return kvm_hv_set_msr_common(vcpu, msr, data,
2205 msr_info->host_initiated);
91c9c3ed 2206 case MSR_IA32_BBL_CR_CTL3:
2207 /* Drop writes to this legacy MSR -- see rdmsr
2208 * counterpart for further detail.
2209 */
a737f256 2210 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2211 break;
2b036c6b
BO		 2212 case MSR_AMD64_OSVW_ID_LENGTH:
2213 if (!guest_cpuid_has_osvw(vcpu))
2214 return 1;
2215 vcpu->arch.osvw.length = data;
2216 break;
2217 case MSR_AMD64_OSVW_STATUS:
2218 if (!guest_cpuid_has_osvw(vcpu))
2219 return 1;
2220 vcpu->arch.osvw.status = data;
2221 break;
15c4a640 2222 default:
ffde22ac
ES		 2223 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2224 return xen_hvm_config(vcpu, data);
c6702c9d 2225 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2226 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2227 if (!ignore_msrs) {
a737f256
CD		 2228 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2229 msr, data);
ed85c068
AP		 2230 return 1;
2231 } else {
a737f256
CD		 2232 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2233 msr, data);
ed85c068
AP		 2234 break;
2235 }
15c4a640
CO		 2236 }
2237 return 0;
2238}
2239EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2240
2241
2242/*
2243 * Reads an msr value (of 'msr_index') into 'pdata'.
2244 * Returns 0 on success, non-0 otherwise.
2245 * Assumes vcpu_load() was already called.
2246 */
609e36d3 2247int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2248{
609e36d3 2249 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2250}
ff651cb6 2251EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2252
890ca9ae 2253static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2254{
2255 u64 data;
890ca9ae
HY		 2256 u64 mcg_cap = vcpu->arch.mcg_cap;
2257 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2258
2259 switch (msr) {
15c4a640
CO		 2260 case MSR_IA32_P5_MC_ADDR:
2261 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2262 data = 0;
2263 break;
15c4a640 2264 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2265 data = vcpu->arch.mcg_cap;
2266 break;
c7ac679c 2267 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2268 if (!(mcg_cap & MCG_CTL_P))
2269 return 1;
2270 data = vcpu->arch.mcg_ctl;
2271 break;
2272 case MSR_IA32_MCG_STATUS:
2273 data = vcpu->arch.mcg_status;
2274 break;
2275 default:
2276 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2277 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2278 u32 offset = msr - MSR_IA32_MC0_CTL;
2279 data = vcpu->arch.mce_banks[offset];
2280 break;
2281 }
2282 return 1;
2283 }
2284 *pdata = data;
2285 return 0;
2286}
2287
609e36d3 2288int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2289{
609e36d3 2290 switch (msr_info->index) {
890ca9ae 2291 case MSR_IA32_PLATFORM_ID:
15c4a640 2292 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2293 case MSR_IA32_DEBUGCTLMSR:
2294 case MSR_IA32_LASTBRANCHFROMIP:
2295 case MSR_IA32_LASTBRANCHTOIP:
2296 case MSR_IA32_LASTINTFROMIP:
2297 case MSR_IA32_LASTINTTOIP:
60af2ecd 2298 case MSR_K8_SYSCFG:
3afb1121
PB		 2299 case MSR_K8_TSEG_ADDR:
2300 case MSR_K8_TSEG_MASK:
60af2ecd 2301 case MSR_K7_HWCR:
61a6bd67 2302 case MSR_VM_HSAVE_PA:
1fdbd48c 2303 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2304 case MSR_AMD64_NB_CFG:
f7c6d140 2305 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2306 case MSR_AMD64_BU_CFG2:
609e36d3 2307 msr_info->data = 0;
15c4a640 2308 break;
6912ac32
WH		 2309 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2310 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2311 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2312 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2313 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2314 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2315 msr_info->data = 0;
5753785f 2316 break;
742bc670 2317 case MSR_IA32_UCODE_REV:
609e36d3 2318 msr_info->data = 0x100000000ULL;
742bc670 2319 break;
9ba075a6 2320 case MSR_MTRRcap:
9ba075a6 2321 case 0x200 ... 0x2ff:
ff53604b 2322 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2323 case 0xcd: /* fsb frequency */
609e36d3 2324 msr_info->data = 3;
15c4a640 2325 break;
7b914098
JS		 2326 /*
2327 * MSR_EBC_FREQUENCY_ID
2328 * Conservative value valid for even the basic CPU models.
2329 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2330 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2331 * and 266MHz for model 3, or 4. Set Core Clock
2332 * Frequency to System Bus Frequency Ratio to 1 (bits
2333 * 31:24) even though these are only valid for CPU
2334 * models > 2, however guests may end up dividing or
2335 * multiplying by zero otherwise.
2336 */
2337 case MSR_EBC_FREQUENCY_ID:
609e36d3 2338 msr_info->data = 1 << 24;
7b914098 2339 break;
15c4a640 2340 case MSR_IA32_APICBASE:
609e36d3 2341 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2342 break;
0105d1a5 2343 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2344 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2345 break;
a3e06bbe 2346 case MSR_IA32_TSCDEADLINE:
609e36d3 2347 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2348 break;
ba904635 2349 case MSR_IA32_TSC_ADJUST:
609e36d3 2350 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2351 break;
15c4a640 2352 case MSR_IA32_MISC_ENABLE:
609e36d3 2353 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2354 break;
64d60670
PB		 2355 case MSR_IA32_SMBASE:
2356 if (!msr_info->host_initiated)
2357 return 1;
2358 msr_info->data = vcpu->arch.smbase;
15c4a640 2359 break;
847f0ad8
AG		 2360 case MSR_IA32_PERF_STATUS:
2361 /* TSC increment by tick */
609e36d3 2362 msr_info->data = 1000ULL;
847f0ad8 2363 /* CPU multiplier */
b0996ae4 2364 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2365 break;
15c4a640 2366 case MSR_EFER:
609e36d3 2367 msr_info->data = vcpu->arch.efer;
15c4a640 2368 break;
18068523 2369 case MSR_KVM_WALL_CLOCK:
11c6bffa 2370 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2371 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2372 break;
2373 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2374 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2375 msr_info->data = vcpu->arch.time;
18068523 2376 break;
344d9588 2377 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2378 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2379 break;
c9aaa895 2380 case MSR_KVM_STEAL_TIME:
609e36d3 2381 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2382 break;
1d92128f 2383 case MSR_KVM_PV_EOI_EN:
609e36d3 2384 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2385 break;
890ca9ae
HY		 2386 case MSR_IA32_P5_MC_ADDR:
2387 case MSR_IA32_P5_MC_TYPE:
2388 case MSR_IA32_MCG_CAP:
2389 case MSR_IA32_MCG_CTL:
2390 case MSR_IA32_MCG_STATUS:
81760dcc 2391 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2392 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2393 case MSR_K7_CLK_CTL:
2394 /*
2395 * Provide expected ramp-up count for K7. All other
2396 * are set to zero, indicating minimum divisors for
2397 * every field.
2398 *
2399 * This prevents guest kernels on AMD host with CPU
2400 * type 6, model 8 and higher from exploding due to
2401 * the rdmsr failing.
2402 */
609e36d3 2403 msr_info->data = 0x20000000;
84e0cefa 2404 break;
55cd8e5a 2405 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2406 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2407 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2408 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2409 return kvm_hv_get_msr_common(vcpu,
2410 msr_info->index, &msr_info->data);
55cd8e5a 2411 break;
91c9c3ed 2412 case MSR_IA32_BBL_CR_CTL3:
2413 /* This legacy MSR exists but isn't fully documented in current
2414 * silicon. It is however accessed by winxp in very narrow
2415 * scenarios where it sets bit #19, itself documented as
2416 * a "reserved" bit. Best effort attempt to source coherent
2417 * read data here should the balance of the register be
2418 * interpreted by the guest:
2419 *
2420 * L2 cache control register 3: 64GB range, 256KB size,
2421 * enabled, latency 0x1, configured
2422 */
609e36d3 2423 msr_info->data = 0xbe702111;
91c9c3ed 2424 break;
2b036c6b
BO		 2425 case MSR_AMD64_OSVW_ID_LENGTH:
2426 if (!guest_cpuid_has_osvw(vcpu))
2427 return 1;
609e36d3 2428 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2429 break;
2430 case MSR_AMD64_OSVW_STATUS:
2431 if (!guest_cpuid_has_osvw(vcpu))
2432 return 1;
609e36d3 2433 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2434 break;
15c4a640 2435 default:
c6702c9d 2436 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2437 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2438 if (!ignore_msrs) {
609e36d3 2439 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2440 return 1;
2441 } else {
609e36d3
PB		 2442 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2443 msr_info->data = 0;
ed85c068
AP		 2444 }
2445 break;
15c4a640 2446 }
15c4a640
CO		 2447 return 0;
2448}
2449EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2450
313a3dc7
CO		 2451/*
2452 * Read or write a bunch of msrs. All parameters are kernel addresses.
2453 *
2454 * @return number of msrs set successfully.
2455 */
2456static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2457 struct kvm_msr_entry *entries,
2458 int (*do_msr)(struct kvm_vcpu *vcpu,
2459 unsigned index, u64 *data))
2460{
f656ce01 2461 int i, idx;
313a3dc7 2462
f656ce01 2463 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2464 for (i = 0; i < msrs->nmsrs; ++i)
2465 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2466 break;
f656ce01 2467 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2468
313a3dc7
CO		 2469 return i;
2470}
2471
2472/*
2473 * Read or write a bunch of msrs. Parameters are user addresses.
2474 *
2475 * @return number of msrs set successfully.
2476 */
2477static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2478 int (*do_msr)(struct kvm_vcpu *vcpu,
2479 unsigned index, u64 *data),
2480 int writeback)
2481{
2482 struct kvm_msrs msrs;
2483 struct kvm_msr_entry *entries;
2484 int r, n;
2485 unsigned size;
2486
2487 r = -EFAULT;
2488 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2489 goto out;
2490
2491 r = -E2BIG;
2492 if (msrs.nmsrs >= MAX_IO_MSRS)
2493 goto out;
2494
313a3dc7 2495 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2496 entries = memdup_user(user_msrs->entries, size);
2497 if (IS_ERR(entries)) {
2498 r = PTR_ERR(entries);
313a3dc7 2499 goto out;
ff5c2c03 2500 }
313a3dc7
CO		 2501
2502 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2503 if (r < 0)
2504 goto out_free;
2505
2506 r = -EFAULT;
2507 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2508 goto out_free;
2509
2510 r = n;
2511
2512out_free:
7a73c028 2513 kfree(entries);
313a3dc7
CO		 2514out:
2515 return r;
2516}
2517
784aa3d7 2518int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2519{
2520 int r;
2521
2522 switch (ext) {
2523 case KVM_CAP_IRQCHIP:
2524 case KVM_CAP_HLT:
2525 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2526 case KVM_CAP_SET_TSS_ADDR:
07716717 2527 case KVM_CAP_EXT_CPUID:
9c15bb1d 2528 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2529 case KVM_CAP_CLOCKSOURCE:
7837699f 2530 case KVM_CAP_PIT:
a28e4f5a 2531 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2532 case KVM_CAP_MP_STATE:
ed848624 2533 case KVM_CAP_SYNC_MMU:
a355c85c 2534 case KVM_CAP_USER_NMI:
52d939a0 2535 case KVM_CAP_REINJECT_CONTROL:
4925663a 2536 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2537 case KVM_CAP_IOEVENTFD:
f848a5a8 2538 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2539 case KVM_CAP_PIT2:
e9f42757 2540 case KVM_CAP_PIT_STATE2:
b927a3ce 2541 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2542 case KVM_CAP_XEN_HVM:
afbcf7ab 2543 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2544 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2545 case KVM_CAP_HYPERV:
10388a07 2546 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2547 case KVM_CAP_HYPERV_SPIN:
5c919412 2548 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2549 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2550 case KVM_CAP_DEBUGREGS:
d2be1651 2551 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2552 case KVM_CAP_XSAVE:
344d9588 2553 case KVM_CAP_ASYNC_PF:
92a1f12d 2554 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2555 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2556 case KVM_CAP_READONLY_MEM:
5f66b620 2557 case KVM_CAP_HYPERV_TIME:
100943c5 2558 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2559 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2560 case KVM_CAP_ENABLE_CAP_VM:
2561 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2562 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2563 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2564#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2565 case KVM_CAP_ASSIGN_DEV_IRQ:
2566 case KVM_CAP_PCI_2_3:
2567#endif
018d00d2
ZX		 2568 r = 1;
2569 break;
6d396b55
PB		 2570 case KVM_CAP_X86_SMM:
2571 /* SMBASE is usually relocated above 1M on modern chipsets,
2572 * and SMM handlers might indeed rely on 4G segment limits,
2573 * so do not report SMM to be available if real mode is
2574 * emulated via vm86 mode. Still, do not go to great lengths
2575 * to avoid userspace's usage of the feature, because it is a
2576 * fringe case that is not enabled except via specific settings
2577 * of the module parameters.
2578 */
2579 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2580 break;
542472b5
LV		 2581 case KVM_CAP_COALESCED_MMIO:
2582 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2583 break;
774ead3a
AK		 2584 case KVM_CAP_VAPIC:
2585 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2586 break;
f725230a 2587 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2588 r = KVM_SOFT_MAX_VCPUS;
2589 break;
2590 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2591 r = KVM_MAX_VCPUS;
2592 break;
a988b910 2593 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2594 r = KVM_USER_MEM_SLOTS;
a988b910 2595 break;
a68a6a72
MT		 2596 case KVM_CAP_PV_MMU: /* obsolete */
2597 r = 0;
2f333bcb 2598 break;
4cee4b72 2599#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2600 case KVM_CAP_IOMMU:
a1b60c1c 2601 r = iommu_present(&pci_bus_type);
62c476c7 2602 break;
4cee4b72 2603#endif
890ca9ae
HY		 2604 case KVM_CAP_MCE:
2605 r = KVM_MAX_MCE_BANKS;
2606 break;
2d5b5a66
SY		 2607 case KVM_CAP_XCRS:
2608 r = cpu_has_xsave;
2609 break;
92a1f12d
JR		 2610 case KVM_CAP_TSC_CONTROL:
2611 r = kvm_has_tsc_control;
2612 break;
018d00d2
ZX		 2613 default:
2614 r = 0;
2615 break;
2616 }
2617 return r;
2618
2619}
2620
043405e1
CO		 2621long kvm_arch_dev_ioctl(struct file *filp,
2622 unsigned int ioctl, unsigned long arg)
2623{
2624 void __user *argp = (void __user *)arg;
2625 long r;
2626
2627 switch (ioctl) {
2628 case KVM_GET_MSR_INDEX_LIST: {
2629 struct kvm_msr_list __user *user_msr_list = argp;
2630 struct kvm_msr_list msr_list;
2631 unsigned n;
2632
2633 r = -EFAULT;
2634 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2635 goto out;
2636 n = msr_list.nmsrs;
62ef68bb 2637 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2638 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2639 goto out;
2640 r = -E2BIG;
e125e7b6 2641 if (n < msr_list.nmsrs)
043405e1
CO		 2642 goto out;
2643 r = -EFAULT;
2644 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2645 num_msrs_to_save * sizeof(u32)))
2646 goto out;
e125e7b6 2647 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2648 &emulated_msrs,
62ef68bb 2649 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2650 goto out;
2651 r = 0;
2652 break;
2653 }
9c15bb1d
BP		 2654 case KVM_GET_SUPPORTED_CPUID:
2655 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2656 struct kvm_cpuid2 __user *cpuid_arg = argp;
2657 struct kvm_cpuid2 cpuid;
2658
2659 r = -EFAULT;
2660 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2661 goto out;
9c15bb1d
BP		 2662
2663 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2664 ioctl);
674eea0f
AK		 2665 if (r)
2666 goto out;
2667
2668 r = -EFAULT;
2669 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2670 goto out;
2671 r = 0;
2672 break;
2673 }
890ca9ae
HY		 2674 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2675 u64 mce_cap;
2676
2677 mce_cap = KVM_MCE_CAP_SUPPORTED;
2678 r = -EFAULT;
2679 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2680 goto out;
2681 r = 0;
2682 break;
2683 }
043405e1
CO		 2684 default:
2685 r = -EINVAL;
2686 }
2687out:
2688 return r;
2689}
2690
f5f48ee1
SY		 2691static void wbinvd_ipi(void *garbage)
2692{
2693 wbinvd();
2694}
2695
2696static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2697{
e0f0bbc5 2698 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2699}
2700
313a3dc7
CO		 2701void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2702{
f5f48ee1
SY		 2703 /* Address WBINVD may be executed by guest */
2704 if (need_emulate_wbinvd(vcpu)) {
2705 if (kvm_x86_ops->has_wbinvd_exit())
2706 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2707 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2708 smp_call_function_single(vcpu->cpu,
2709 wbinvd_ipi, NULL, 1);
2710 }
2711
313a3dc7 2712 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2713
0dd6a6ed
ZA		 2714 /* Apply any externally detected TSC adjustments (due to suspend) */
2715 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2716 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2717 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2718 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2719 }
8f6055cb 2720
48434c20 2721 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2722 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2723 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2724 if (tsc_delta < 0)
2725 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2726 if (check_tsc_unstable()) {
07c1419a 2727 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2728 vcpu->arch.last_guest_tsc);
2729 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2730 vcpu->arch.tsc_catchup = 1;
c285545f 2731 }
d98d07ca
MT		 2732 /*
2733 * On a host with synchronized TSC, there is no need to update
2734 * kvmclock on vcpu->cpu migration
2735 */
2736 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2737 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2738 if (vcpu->cpu != cpu)
2739 kvm_migrate_timers(vcpu);
e48672fa 2740 vcpu->cpu = cpu;
6b7d7e76 2741 }
c9aaa895 2742
c9aaa895 2743 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2744}
2745
2746void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2747{
02daab21 2748 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2749 kvm_put_guest_fpu(vcpu);
4ea1636b 2750 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2751}
2752
313a3dc7
CO		 2753static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2754 struct kvm_lapic_state *s)
2755{
d62caabb
AS		 2756 if (vcpu->arch.apicv_active)
2757 kvm_x86_ops->sync_pir_to_irr(vcpu);
2758
ad312c7c 2759 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2760
2761 return 0;
2762}
2763
2764static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2765 struct kvm_lapic_state *s)
2766{
64eb0620 2767 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2768 update_cr8_intercept(vcpu);
313a3dc7
CO		 2769
2770 return 0;
2771}
2772
127a457a
MG		 2773static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2774{
2775 return (!lapic_in_kernel(vcpu) ||
2776 kvm_apic_accept_pic_intr(vcpu));
2777}
2778
782d422b
MG		 2779/*
2780 * if userspace requested an interrupt window, check that the
2781 * interrupt window is open.
2782 *
2783 * No need to exit to userspace if we already have an interrupt queued.
2784 */
2785static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2786{
2787 return kvm_arch_interrupt_allowed(vcpu) &&
2788 !kvm_cpu_has_interrupt(vcpu) &&
2789 !kvm_event_needs_reinjection(vcpu) &&
2790 kvm_cpu_accept_dm_intr(vcpu);
2791}
2792
f77bc6a4
ZX		 2793static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2794 struct kvm_interrupt *irq)
2795{
02cdb50f 2796 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2797 return -EINVAL;
1c1a9ce9
SR		 2798
2799 if (!irqchip_in_kernel(vcpu->kvm)) {
2800 kvm_queue_interrupt(vcpu, irq->irq, false);
2801 kvm_make_request(KVM_REQ_EVENT, vcpu);
2802 return 0;
2803 }
2804
2805 /*
2806 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2807 * fail for in-kernel 8259.
2808 */
2809 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2810 return -ENXIO;
f77bc6a4 2811
1c1a9ce9
SR		 2812 if (vcpu->arch.pending_external_vector != -1)
2813 return -EEXIST;
f77bc6a4 2814
1c1a9ce9 2815 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2816 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2817 return 0;
2818}
2819
c4abb7c9
JK		 2820static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2821{
c4abb7c9 2822 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2823
2824 return 0;
2825}
2826
f077825a
PB		 2827static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2828{
64d60670
PB		 2829 kvm_make_request(KVM_REQ_SMI, vcpu);
2830
f077825a
PB		 2831 return 0;
2832}
2833
b209749f
AK		 2834static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2835 struct kvm_tpr_access_ctl *tac)
2836{
2837 if (tac->flags)
2838 return -EINVAL;
2839 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2840 return 0;
2841}
2842
890ca9ae
HY		 2843static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2844 u64 mcg_cap)
2845{
2846 int r;
2847 unsigned bank_num = mcg_cap & 0xff, bank;
2848
2849 r = -EINVAL;
a9e38c3e 2850 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2851 goto out;
2852 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2853 goto out;
2854 r = 0;
2855 vcpu->arch.mcg_cap = mcg_cap;
2856 /* Init IA32_MCG_CTL to all 1s */
2857 if (mcg_cap & MCG_CTL_P)
2858 vcpu->arch.mcg_ctl = ~(u64)0;
2859 /* Init IA32_MCi_CTL to all 1s */
2860 for (bank = 0; bank < bank_num; bank++)
2861 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2862out:
2863 return r;
2864}
2865
2866static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2867 struct kvm_x86_mce *mce)
2868{
2869 u64 mcg_cap = vcpu->arch.mcg_cap;
2870 unsigned bank_num = mcg_cap & 0xff;
2871 u64 *banks = vcpu->arch.mce_banks;
2872
2873 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2874 return -EINVAL;
2875 /*
2876 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2877 * reporting is disabled
2878 */
2879 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2880 vcpu->arch.mcg_ctl != ~(u64)0)
2881 return 0;
2882 banks += 4 * mce->bank;
2883 /*
2884 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2885 * reporting is disabled for the bank
2886 */
2887 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2888 return 0;
2889 if (mce->status & MCI_STATUS_UC) {
2890 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2891 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2892 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2893 return 0;
2894 }
2895 if (banks[1] & MCI_STATUS_VAL)
2896 mce->status |= MCI_STATUS_OVER;
2897 banks[2] = mce->addr;
2898 banks[3] = mce->misc;
2899 vcpu->arch.mcg_status = mce->mcg_status;
2900 banks[1] = mce->status;
2901 kvm_queue_exception(vcpu, MC_VECTOR);
2902 } else if (!(banks[1] & MCI_STATUS_VAL)
2903 || !(banks[1] & MCI_STATUS_UC)) {
2904 if (banks[1] & MCI_STATUS_VAL)
2905 mce->status |= MCI_STATUS_OVER;
2906 banks[2] = mce->addr;
2907 banks[3] = mce->misc;
2908 banks[1] = mce->status;
2909 } else
2910 banks[1] |= MCI_STATUS_OVER;
2911 return 0;
2912}
2913
3cfc3092
JK		 2914static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2915 struct kvm_vcpu_events *events)
2916{
7460fb4a 2917 process_nmi(vcpu);
03b82a30
JK		 2918 events->exception.injected =
2919 vcpu->arch.exception.pending &&
2920 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2921 events->exception.nr = vcpu->arch.exception.nr;
2922 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2923 events->exception.pad = 0;
3cfc3092
JK		 2924 events->exception.error_code = vcpu->arch.exception.error_code;
2925
03b82a30
JK		 2926 events->interrupt.injected =
2927 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2928 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2929 events->interrupt.soft = 0;
37ccdcbe 2930 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2931
2932 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2933 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2934 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2935 events->nmi.pad = 0;
3cfc3092 2936
66450a21 2937 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2938
f077825a
PB		 2939 events->smi.smm = is_smm(vcpu);
2940 events->smi.pending = vcpu->arch.smi_pending;
2941 events->smi.smm_inside_nmi =
2942 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2943 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2944
dab4b911 2945 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2946 | KVM_VCPUEVENT_VALID_SHADOW
2947 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2948 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2949}
2950
2951static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2952 struct kvm_vcpu_events *events)
2953{
dab4b911 2954 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2955 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2956 | KVM_VCPUEVENT_VALID_SHADOW
2957 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2958 return -EINVAL;
2959
7460fb4a 2960 process_nmi(vcpu);
3cfc3092
JK		 2961 vcpu->arch.exception.pending = events->exception.injected;
2962 vcpu->arch.exception.nr = events->exception.nr;
2963 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2964 vcpu->arch.exception.error_code = events->exception.error_code;
2965
2966 vcpu->arch.interrupt.pending = events->interrupt.injected;
2967 vcpu->arch.interrupt.nr = events->interrupt.nr;
2968 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2969 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2970 kvm_x86_ops->set_interrupt_shadow(vcpu,
2971 events->interrupt.shadow);
3cfc3092
JK		 2972
2973 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2974 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2975 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2976 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2977
66450a21
JK		 2978 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2979 kvm_vcpu_has_lapic(vcpu))
2980 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2981
f077825a
PB		 2982 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2983 if (events->smi.smm)
2984 vcpu->arch.hflags |= HF_SMM_MASK;
2985 else
2986 vcpu->arch.hflags &= ~HF_SMM_MASK;
2987 vcpu->arch.smi_pending = events->smi.pending;
2988 if (events->smi.smm_inside_nmi)
2989 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2990 else
2991 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2992 if (kvm_vcpu_has_lapic(vcpu)) {
2993 if (events->smi.latched_init)
2994 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2995 else
2996 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2997 }
2998 }
2999
3842d135
AK		 3000 kvm_make_request(KVM_REQ_EVENT, vcpu);
3001
3cfc3092
JK		 3002 return 0;
3003}
3004
a1efbe77
JK		 3005static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3006 struct kvm_debugregs *dbgregs)
3007{
73aaf249
JK		 3008 unsigned long val;
3009
a1efbe77 3010 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3011 kvm_get_dr(vcpu, 6, &val);
73aaf249 3012 dbgregs->dr6 = val;
a1efbe77
JK		 3013 dbgregs->dr7 = vcpu->arch.dr7;
3014 dbgregs->flags = 0;
97e69aa6 3015 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3016}
3017
3018static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3019 struct kvm_debugregs *dbgregs)
3020{
3021 if (dbgregs->flags)
3022 return -EINVAL;
3023
a1efbe77 3024 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3025 kvm_update_dr0123(vcpu);
a1efbe77 3026 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3027 kvm_update_dr6(vcpu);
a1efbe77 3028 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3029 kvm_update_dr7(vcpu);
a1efbe77 3030
a1efbe77
JK		 3031 return 0;
3032}
3033
df1daba7
PB		 3034#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3035
3036static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3037{
c47ada30 3038 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3039 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3040 u64 valid;
3041
3042 /*
3043 * Copy legacy XSAVE area, to avoid complications with CPUID
3044 * leaves 0 and 1 in the loop below.
3045 */
3046 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3047
3048 /* Set XSTATE_BV */
3049 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3050
3051 /*
3052 * Copy each region from the possibly compacted offset to the
3053 * non-compacted offset.
3054 */
d91cab78 3055 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3056 while (valid) {
3057 u64 feature = valid & -valid;
3058 int index = fls64(feature) - 1;
3059 void *src = get_xsave_addr(xsave, feature);
3060
3061 if (src) {
3062 u32 size, offset, ecx, edx;
3063 cpuid_count(XSTATE_CPUID, index,
3064 &size, &offset, &ecx, &edx);
3065 memcpy(dest + offset, src, size);
3066 }
3067
3068 valid -= feature;
3069 }
3070}
3071
3072static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3073{
c47ada30 3074 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3075 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3076 u64 valid;
3077
3078 /*
3079 * Copy legacy XSAVE area, to avoid complications with CPUID
3080 * leaves 0 and 1 in the loop below.
3081 */
3082 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3083
3084 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3085 xsave->header.xfeatures = xstate_bv;
df1daba7 3086 if (cpu_has_xsaves)
3a54450b 3087 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3088
3089 /*
3090 * Copy each region from the non-compacted offset to the
3091 * possibly compacted offset.
3092 */
d91cab78 3093 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3094 while (valid) {
3095 u64 feature = valid & -valid;
3096 int index = fls64(feature) - 1;
3097 void *dest = get_xsave_addr(xsave, feature);
3098
3099 if (dest) {
3100 u32 size, offset, ecx, edx;
3101 cpuid_count(XSTATE_CPUID, index,
3102 &size, &offset, &ecx, &edx);
3103 memcpy(dest, src + offset, size);
ee4100da 3104 }
df1daba7
PB		 3105
3106 valid -= feature;
3107 }
3108}
3109
2d5b5a66
SY		 3110static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3111 struct kvm_xsave *guest_xsave)
3112{
4344ee98 3113 if (cpu_has_xsave) {
df1daba7
PB		 3114 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3115 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3116 } else {
2d5b5a66 3117 memcpy(guest_xsave->region,
7366ed77 3118 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3119 sizeof(struct fxregs_state));
2d5b5a66 3120 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3121 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3122 }
3123}
3124
3125static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3126 struct kvm_xsave *guest_xsave)
3127{
3128 u64 xstate_bv =
3129 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3130
d7876f1b
PB		 3131 if (cpu_has_xsave) {
3132 /*
3133 * Here we allow setting states that are not present in
3134 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3135 * with old userspace.
3136 */
4ff41732 3137 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3138 return -EINVAL;
df1daba7 3139 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3140 } else {
d91cab78 3141 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3142 return -EINVAL;
7366ed77 3143 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3144 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3145 }
3146 return 0;
3147}
3148
3149static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3150 struct kvm_xcrs *guest_xcrs)
3151{
3152 if (!cpu_has_xsave) {
3153 guest_xcrs->nr_xcrs = 0;
3154 return;
3155 }
3156
3157 guest_xcrs->nr_xcrs = 1;
3158 guest_xcrs->flags = 0;
3159 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3160 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3161}
3162
3163static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3164 struct kvm_xcrs *guest_xcrs)
3165{
3166 int i, r = 0;
3167
3168 if (!cpu_has_xsave)
3169 return -EINVAL;
3170
3171 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3172 return -EINVAL;
3173
3174 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3175 /* Only support XCR0 currently */
c67a04cb 3176 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3177 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3178 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3179 break;
3180 }
3181 if (r)
3182 r = -EINVAL;
3183 return r;
3184}
3185
1c0b28c2
EM		 3186/*
3187 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3188 * stopped by the hypervisor. This function will be called from the host only.
3189 * EINVAL is returned when the host attempts to set the flag for a guest that
3190 * does not support pv clocks.
3191 */
3192static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3193{
0b79459b 3194 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3195 return -EINVAL;
51d59c6b 3196 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3197 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3198 return 0;
3199}
3200
5c919412
AS		 3201static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3202 struct kvm_enable_cap *cap)
3203{
3204 if (cap->flags)
3205 return -EINVAL;
3206
3207 switch (cap->cap) {
3208 case KVM_CAP_HYPERV_SYNIC:
3209 return kvm_hv_activate_synic(vcpu);
3210 default:
3211 return -EINVAL;
3212 }
3213}
3214
313a3dc7
CO		 3215long kvm_arch_vcpu_ioctl(struct file *filp,
3216 unsigned int ioctl, unsigned long arg)
3217{
3218 struct kvm_vcpu *vcpu = filp->private_data;
3219 void __user *argp = (void __user *)arg;
3220 int r;
d1ac91d8
AK		 3221 union {
3222 struct kvm_lapic_state *lapic;
3223 struct kvm_xsave *xsave;
3224 struct kvm_xcrs *xcrs;
3225 void *buffer;
3226 } u;
3227
3228 u.buffer = NULL;
313a3dc7
CO		 3229 switch (ioctl) {
3230 case KVM_GET_LAPIC: {
2204ae3c
MT		 3231 r = -EINVAL;
3232 if (!vcpu->arch.apic)
3233 goto out;
d1ac91d8 3234 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3235
b772ff36 3236 r = -ENOMEM;
d1ac91d8 3237 if (!u.lapic)
b772ff36 3238 goto out;
d1ac91d8 3239 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3240 if (r)
3241 goto out;
3242 r = -EFAULT;
d1ac91d8 3243 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3244 goto out;
3245 r = 0;
3246 break;
3247 }
3248 case KVM_SET_LAPIC: {
2204ae3c
MT		 3249 r = -EINVAL;
3250 if (!vcpu->arch.apic)
3251 goto out;
ff5c2c03 3252 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3253 if (IS_ERR(u.lapic))
3254 return PTR_ERR(u.lapic);
ff5c2c03 3255
d1ac91d8 3256 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3257 break;
3258 }
f77bc6a4
ZX		 3259 case KVM_INTERRUPT: {
3260 struct kvm_interrupt irq;
3261
3262 r = -EFAULT;
3263 if (copy_from_user(&irq, argp, sizeof irq))
3264 goto out;
3265 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3266 break;
3267 }
c4abb7c9
JK		 3268 case KVM_NMI: {
3269 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3270 break;
3271 }
f077825a
PB		 3272 case KVM_SMI: {
3273 r = kvm_vcpu_ioctl_smi(vcpu);
3274 break;
3275 }
313a3dc7
CO		 3276 case KVM_SET_CPUID: {
3277 struct kvm_cpuid __user *cpuid_arg = argp;
3278 struct kvm_cpuid cpuid;
3279
3280 r = -EFAULT;
3281 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3282 goto out;
3283 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3284 break;
3285 }
07716717
DK		 3286 case KVM_SET_CPUID2: {
3287 struct kvm_cpuid2 __user *cpuid_arg = argp;
3288 struct kvm_cpuid2 cpuid;
3289
3290 r = -EFAULT;
3291 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3292 goto out;
3293 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3294 cpuid_arg->entries);
07716717
DK		 3295 break;
3296 }
3297 case KVM_GET_CPUID2: {
3298 struct kvm_cpuid2 __user *cpuid_arg = argp;
3299 struct kvm_cpuid2 cpuid;
3300
3301 r = -EFAULT;
3302 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3303 goto out;
3304 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3305 cpuid_arg->entries);
07716717
DK		 3306 if (r)
3307 goto out;
3308 r = -EFAULT;
3309 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3310 goto out;
3311 r = 0;
3312 break;
3313 }
313a3dc7 3314 case KVM_GET_MSRS:
609e36d3 3315 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3316 break;
3317 case KVM_SET_MSRS:
3318 r = msr_io(vcpu, argp, do_set_msr, 0);
3319 break;
b209749f
AK		 3320 case KVM_TPR_ACCESS_REPORTING: {
3321 struct kvm_tpr_access_ctl tac;
3322
3323 r = -EFAULT;
3324 if (copy_from_user(&tac, argp, sizeof tac))
3325 goto out;
3326 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3327 if (r)
3328 goto out;
3329 r = -EFAULT;
3330 if (copy_to_user(argp, &tac, sizeof tac))
3331 goto out;
3332 r = 0;
3333 break;
3334 };
b93463aa
AK		 3335 case KVM_SET_VAPIC_ADDR: {
3336 struct kvm_vapic_addr va;
3337
3338 r = -EINVAL;
35754c98 3339 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3340 goto out;
3341 r = -EFAULT;
3342 if (copy_from_user(&va, argp, sizeof va))
3343 goto out;
fda4e2e8 3344 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3345 break;
3346 }
890ca9ae
HY		 3347 case KVM_X86_SETUP_MCE: {
3348 u64 mcg_cap;
3349
3350 r = -EFAULT;
3351 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3352 goto out;
3353 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3354 break;
3355 }
3356 case KVM_X86_SET_MCE: {
3357 struct kvm_x86_mce mce;
3358
3359 r = -EFAULT;
3360 if (copy_from_user(&mce, argp, sizeof mce))
3361 goto out;
3362 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3363 break;
3364 }
3cfc3092
JK		 3365 case KVM_GET_VCPU_EVENTS: {
3366 struct kvm_vcpu_events events;
3367
3368 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3369
3370 r = -EFAULT;
3371 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3372 break;
3373 r = 0;
3374 break;
3375 }
3376 case KVM_SET_VCPU_EVENTS: {
3377 struct kvm_vcpu_events events;
3378
3379 r = -EFAULT;
3380 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3381 break;
3382
3383 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3384 break;
3385 }
a1efbe77
JK		 3386 case KVM_GET_DEBUGREGS: {
3387 struct kvm_debugregs dbgregs;
3388
3389 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3390
3391 r = -EFAULT;
3392 if (copy_to_user(argp, &dbgregs,
3393 sizeof(struct kvm_debugregs)))
3394 break;
3395 r = 0;
3396 break;
3397 }
3398 case KVM_SET_DEBUGREGS: {
3399 struct kvm_debugregs dbgregs;
3400
3401 r = -EFAULT;
3402 if (copy_from_user(&dbgregs, argp,
3403 sizeof(struct kvm_debugregs)))
3404 break;
3405
3406 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3407 break;
3408 }
2d5b5a66 3409 case KVM_GET_XSAVE: {
d1ac91d8 3410 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3411 r = -ENOMEM;
d1ac91d8 3412 if (!u.xsave)
2d5b5a66
SY		 3413 break;
3414
d1ac91d8 3415 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3416
3417 r = -EFAULT;
d1ac91d8 3418 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3419 break;
3420 r = 0;
3421 break;
3422 }
3423 case KVM_SET_XSAVE: {
ff5c2c03 3424 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3425 if (IS_ERR(u.xsave))
3426 return PTR_ERR(u.xsave);
2d5b5a66 3427
d1ac91d8 3428 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3429 break;
3430 }
3431 case KVM_GET_XCRS: {
d1ac91d8 3432 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3433 r = -ENOMEM;
d1ac91d8 3434 if (!u.xcrs)
2d5b5a66
SY		 3435 break;
3436
d1ac91d8 3437 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3438
3439 r = -EFAULT;
d1ac91d8 3440 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3441 sizeof(struct kvm_xcrs)))
3442 break;
3443 r = 0;
3444 break;
3445 }
3446 case KVM_SET_XCRS: {
ff5c2c03 3447 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3448 if (IS_ERR(u.xcrs))
3449 return PTR_ERR(u.xcrs);
2d5b5a66 3450
d1ac91d8 3451 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3452 break;
3453 }
92a1f12d
JR		 3454 case KVM_SET_TSC_KHZ: {
3455 u32 user_tsc_khz;
3456
3457 r = -EINVAL;
92a1f12d
JR		 3458 user_tsc_khz = (u32)arg;
3459
3460 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3461 goto out;
3462
cc578287
ZA		 3463 if (user_tsc_khz == 0)
3464 user_tsc_khz = tsc_khz;
3465
381d585c
HZ		 3466 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3467 r = 0;
92a1f12d 3468
92a1f12d
JR		 3469 goto out;
3470 }
3471 case KVM_GET_TSC_KHZ: {
cc578287 3472 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3473 goto out;
3474 }
1c0b28c2
EM		 3475 case KVM_KVMCLOCK_CTRL: {
3476 r = kvm_set_guest_paused(vcpu);
3477 goto out;
3478 }
5c919412
AS		 3479 case KVM_ENABLE_CAP: {
3480 struct kvm_enable_cap cap;
3481
3482 r = -EFAULT;
3483 if (copy_from_user(&cap, argp, sizeof(cap)))
3484 goto out;
3485 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3486 break;
3487 }
313a3dc7
CO		 3488 default:
3489 r = -EINVAL;
3490 }
3491out:
d1ac91d8 3492 kfree(u.buffer);
313a3dc7
CO		 3493 return r;
3494}
3495
5b1c1493
CO		 3496int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3497{
3498 return VM_FAULT_SIGBUS;
3499}
3500
1fe779f8
CO		 3501static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3502{
3503 int ret;
3504
3505 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3506 return -EINVAL;
1fe779f8
CO		 3507 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3508 return ret;
3509}
3510
b927a3ce
SY		 3511static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3512 u64 ident_addr)
3513{
3514 kvm->arch.ept_identity_map_addr = ident_addr;
3515 return 0;
3516}
3517
1fe779f8
CO		 3518static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3519 u32 kvm_nr_mmu_pages)
3520{
3521 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3522 return -EINVAL;
3523
79fac95e 3524 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3525
3526 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3527 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3528
79fac95e 3529 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3530 return 0;
3531}
3532
3533static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3534{
39de71ec 3535 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3536}
3537
1fe779f8
CO		 3538static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3539{
3540 int r;
3541
3542 r = 0;
3543 switch (chip->chip_id) {
3544 case KVM_IRQCHIP_PIC_MASTER:
3545 memcpy(&chip->chip.pic,
3546 &pic_irqchip(kvm)->pics[0],
3547 sizeof(struct kvm_pic_state));
3548 break;
3549 case KVM_IRQCHIP_PIC_SLAVE:
3550 memcpy(&chip->chip.pic,
3551 &pic_irqchip(kvm)->pics[1],
3552 sizeof(struct kvm_pic_state));
3553 break;
3554 case KVM_IRQCHIP_IOAPIC:
eba0226b 3555 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3556 break;
3557 default:
3558 r = -EINVAL;
3559 break;
3560 }
3561 return r;
3562}
3563
3564static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3565{
3566 int r;
3567
3568 r = 0;
3569 switch (chip->chip_id) {
3570 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3571 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3572 memcpy(&pic_irqchip(kvm)->pics[0],
3573 &chip->chip.pic,
3574 sizeof(struct kvm_pic_state));
f4f51050 3575 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3576 break;
3577 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3578 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3579 memcpy(&pic_irqchip(kvm)->pics[1],
3580 &chip->chip.pic,
3581 sizeof(struct kvm_pic_state));
f4f51050 3582 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3583 break;
3584 case KVM_IRQCHIP_IOAPIC:
eba0226b 3585 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3586 break;
3587 default:
3588 r = -EINVAL;
3589 break;
3590 }
3591 kvm_pic_update_irq(pic_irqchip(kvm));
3592 return r;
3593}
3594
e0f63cb9
SY		 3595static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3596{
894a9c55 3597 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3598 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3599 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3600 return 0;
e0f63cb9
SY		 3601}
3602
3603static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3604{
894a9c55 3605 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3606 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3607 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3608 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3609 return 0;
e9f42757
BK		 3610}
3611
3612static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3613{
e9f42757
BK		 3614 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3615 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3616 sizeof(ps->channels));
3617 ps->flags = kvm->arch.vpit->pit_state.flags;
3618 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3619 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3620 return 0;
e9f42757
BK		 3621}
3622
3623static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3624{
2da29bcc 3625 int start = 0;
e9f42757
BK		 3626 u32 prev_legacy, cur_legacy;
3627 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3628 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3629 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3630 if (!prev_legacy && cur_legacy)
3631 start = 1;
3632 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3633 sizeof(kvm->arch.vpit->pit_state.channels));
3634 kvm->arch.vpit->pit_state.flags = ps->flags;
3635 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3636 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3637 return 0;
e0f63cb9
SY		 3638}
3639
52d939a0
MT		 3640static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3641 struct kvm_reinject_control *control)
3642{
3643 if (!kvm->arch.vpit)
3644 return -ENXIO;
894a9c55 3645 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3646 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3647 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3648 return 0;
3649}
3650
95d4c16c 3651/**
60c34612
TY		 3652 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3653 * @kvm: kvm instance
3654 * @log: slot id and address to which we copy the log
95d4c16c 3655 *
e108ff2f
PB		 3656 * Steps 1-4 below provide general overview of dirty page logging. See
3657 * kvm_get_dirty_log_protect() function description for additional details.
3658 *
3659 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3660 * always flush the TLB (step 4) even if previous step failed and the dirty
3661 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3662 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3663 * writes will be marked dirty for next log read.
95d4c16c 3664 *
60c34612
TY		 3665 * 1. Take a snapshot of the bit and clear it if needed.
3666 * 2. Write protect the corresponding page.
e108ff2f
PB		 3667 * 3. Copy the snapshot to the userspace.
3668 * 4. Flush TLB's if needed.
5bb064dc 3669 */
60c34612 3670int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3671{
60c34612 3672 bool is_dirty = false;
e108ff2f 3673 int r;
5bb064dc 3674
79fac95e 3675 mutex_lock(&kvm->slots_lock);
5bb064dc 3676
88178fd4
KH		 3677 /*
3678 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3679 */
3680 if (kvm_x86_ops->flush_log_dirty)
3681 kvm_x86_ops->flush_log_dirty(kvm);
3682
e108ff2f 3683 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3684
3685 /*
3686 * All the TLBs can be flushed out of mmu lock, see the comments in
3687 * kvm_mmu_slot_remove_write_access().
3688 */
e108ff2f 3689 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3690 if (is_dirty)
3691 kvm_flush_remote_tlbs(kvm);
3692
79fac95e 3693 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3694 return r;
3695}
3696
aa2fbe6d
YZ		 3697int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3698 bool line_status)
23d43cf9
CD		 3699{
3700 if (!irqchip_in_kernel(kvm))
3701 return -ENXIO;
3702
3703 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3704 irq_event->irq, irq_event->level,
3705 line_status);
23d43cf9
CD		 3706 return 0;
3707}
3708
90de4a18
NA		 3709static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3710 struct kvm_enable_cap *cap)
3711{
3712 int r;
3713
3714 if (cap->flags)
3715 return -EINVAL;
3716
3717 switch (cap->cap) {
3718 case KVM_CAP_DISABLE_QUIRKS:
3719 kvm->arch.disabled_quirks = cap->args[0];
3720 r = 0;
3721 break;
49df6397
SR		 3722 case KVM_CAP_SPLIT_IRQCHIP: {
3723 mutex_lock(&kvm->lock);
b053b2ae
SR		 3724 r = -EINVAL;
3725 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3726 goto split_irqchip_unlock;
49df6397
SR		 3727 r = -EEXIST;
3728 if (irqchip_in_kernel(kvm))
3729 goto split_irqchip_unlock;
3730 if (atomic_read(&kvm->online_vcpus))
3731 goto split_irqchip_unlock;
3732 r = kvm_setup_empty_irq_routing(kvm);
3733 if (r)
3734 goto split_irqchip_unlock;
3735 /* Pairs with irqchip_in_kernel. */
3736 smp_wmb();
3737 kvm->arch.irqchip_split = true;
b053b2ae 3738 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3739 r = 0;
3740split_irqchip_unlock:
3741 mutex_unlock(&kvm->lock);
3742 break;
3743 }
90de4a18
NA		 3744 default:
3745 r = -EINVAL;
3746 break;
3747 }
3748 return r;
3749}
3750
1fe779f8
CO		 3751long kvm_arch_vm_ioctl(struct file *filp,
3752 unsigned int ioctl, unsigned long arg)
3753{
3754 struct kvm *kvm = filp->private_data;
3755 void __user *argp = (void __user *)arg;
367e1319 3756 int r = -ENOTTY;
f0d66275
DH		 3757 /*
3758 * This union makes it completely explicit to gcc-3.x
3759 * that these two variables' stack usage should be
3760 * combined, not added together.
3761 */
3762 union {
3763 struct kvm_pit_state ps;
e9f42757 3764 struct kvm_pit_state2 ps2;
c5ff41ce 3765 struct kvm_pit_config pit_config;
f0d66275 3766 } u;
1fe779f8
CO		 3767
3768 switch (ioctl) {
3769 case KVM_SET_TSS_ADDR:
3770 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3771 break;
b927a3ce
SY		 3772 case KVM_SET_IDENTITY_MAP_ADDR: {
3773 u64 ident_addr;
3774
3775 r = -EFAULT;
3776 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3777 goto out;
3778 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3779 break;
3780 }
1fe779f8
CO		 3781 case KVM_SET_NR_MMU_PAGES:
3782 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3783 break;
3784 case KVM_GET_NR_MMU_PAGES:
3785 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3786 break;
3ddea128
MT		 3787 case KVM_CREATE_IRQCHIP: {
3788 struct kvm_pic *vpic;
3789
3790 mutex_lock(&kvm->lock);
3791 r = -EEXIST;
3792 if (kvm->arch.vpic)
3793 goto create_irqchip_unlock;
3e515705
AK		 3794 r = -EINVAL;
3795 if (atomic_read(&kvm->online_vcpus))
3796 goto create_irqchip_unlock;
1fe779f8 3797 r = -ENOMEM;
3ddea128
MT		 3798 vpic = kvm_create_pic(kvm);
3799 if (vpic) {
1fe779f8
CO		 3800 r = kvm_ioapic_init(kvm);
3801 if (r) {
175504cd 3802 mutex_lock(&kvm->slots_lock);
71ba994c 3803 kvm_destroy_pic(vpic);
175504cd 3804 mutex_unlock(&kvm->slots_lock);
3ddea128 3805 goto create_irqchip_unlock;
1fe779f8
CO		 3806 }
3807 } else
3ddea128 3808 goto create_irqchip_unlock;
399ec807
AK		 3809 r = kvm_setup_default_irq_routing(kvm);
3810 if (r) {
175504cd 3811 mutex_lock(&kvm->slots_lock);
3ddea128 3812 mutex_lock(&kvm->irq_lock);
72bb2fcd 3813 kvm_ioapic_destroy(kvm);
71ba994c 3814 kvm_destroy_pic(vpic);
3ddea128 3815 mutex_unlock(&kvm->irq_lock);
175504cd 3816 mutex_unlock(&kvm->slots_lock);
71ba994c 3817 goto create_irqchip_unlock;
399ec807 3818 }
71ba994c
PB		 3819 /* Write kvm->irq_routing before kvm->arch.vpic. */
3820 smp_wmb();
3821 kvm->arch.vpic = vpic;
3ddea128
MT		 3822 create_irqchip_unlock:
3823 mutex_unlock(&kvm->lock);
1fe779f8 3824 break;
3ddea128 3825 }
7837699f 3826 case KVM_CREATE_PIT:
c5ff41ce
JK		 3827 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3828 goto create_pit;
3829 case KVM_CREATE_PIT2:
3830 r = -EFAULT;
3831 if (copy_from_user(&u.pit_config, argp,
3832 sizeof(struct kvm_pit_config)))
3833 goto out;
3834 create_pit:
79fac95e 3835 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3836 r = -EEXIST;
3837 if (kvm->arch.vpit)
3838 goto create_pit_unlock;
7837699f 3839 r = -ENOMEM;
c5ff41ce 3840 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3841 if (kvm->arch.vpit)
3842 r = 0;
269e05e4 3843 create_pit_unlock:
79fac95e 3844 mutex_unlock(&kvm->slots_lock);
7837699f 3845 break;
1fe779f8
CO		 3846 case KVM_GET_IRQCHIP: {
3847 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3848 struct kvm_irqchip *chip;
1fe779f8 3849
ff5c2c03
SL		 3850 chip = memdup_user(argp, sizeof(*chip));
3851 if (IS_ERR(chip)) {
3852 r = PTR_ERR(chip);
1fe779f8 3853 goto out;
ff5c2c03
SL		 3854 }
3855
1fe779f8 3856 r = -ENXIO;
49df6397 3857 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3858 goto get_irqchip_out;
3859 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3860 if (r)
f0d66275 3861 goto get_irqchip_out;
1fe779f8 3862 r = -EFAULT;
f0d66275
DH		 3863 if (copy_to_user(argp, chip, sizeof *chip))
3864 goto get_irqchip_out;
1fe779f8 3865 r = 0;
f0d66275
DH		 3866 get_irqchip_out:
3867 kfree(chip);
1fe779f8
CO		 3868 break;
3869 }
3870 case KVM_SET_IRQCHIP: {
3871 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3872 struct kvm_irqchip *chip;
1fe779f8 3873
ff5c2c03
SL		 3874 chip = memdup_user(argp, sizeof(*chip));
3875 if (IS_ERR(chip)) {
3876 r = PTR_ERR(chip);
1fe779f8 3877 goto out;
ff5c2c03
SL		 3878 }
3879
1fe779f8 3880 r = -ENXIO;
49df6397 3881 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3882 goto set_irqchip_out;
3883 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3884 if (r)
f0d66275 3885 goto set_irqchip_out;
1fe779f8 3886 r = 0;
f0d66275
DH		 3887 set_irqchip_out:
3888 kfree(chip);
1fe779f8
CO		 3889 break;
3890 }
e0f63cb9 3891 case KVM_GET_PIT: {
e0f63cb9 3892 r = -EFAULT;
f0d66275 3893 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3894 goto out;
3895 r = -ENXIO;
3896 if (!kvm->arch.vpit)
3897 goto out;
f0d66275 3898 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3899 if (r)
3900 goto out;
3901 r = -EFAULT;
f0d66275 3902 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3903 goto out;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_SET_PIT: {
e0f63cb9 3908 r = -EFAULT;
f0d66275 3909 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3910 goto out;
3911 r = -ENXIO;
3912 if (!kvm->arch.vpit)
3913 goto out;
f0d66275 3914 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3915 break;
3916 }
e9f42757
BK		 3917 case KVM_GET_PIT2: {
3918 r = -ENXIO;
3919 if (!kvm->arch.vpit)
3920 goto out;
3921 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3922 if (r)
3923 goto out;
3924 r = -EFAULT;
3925 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3926 goto out;
3927 r = 0;
3928 break;
3929 }
3930 case KVM_SET_PIT2: {
3931 r = -EFAULT;
3932 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3933 goto out;
3934 r = -ENXIO;
3935 if (!kvm->arch.vpit)
3936 goto out;
3937 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3938 break;
3939 }
52d939a0
MT		 3940 case KVM_REINJECT_CONTROL: {
3941 struct kvm_reinject_control control;
3942 r = -EFAULT;
3943 if (copy_from_user(&control, argp, sizeof(control)))
3944 goto out;
3945 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3946 break;
3947 }
d71ba788
PB		 3948 case KVM_SET_BOOT_CPU_ID:
3949 r = 0;
3950 mutex_lock(&kvm->lock);
3951 if (atomic_read(&kvm->online_vcpus) != 0)
3952 r = -EBUSY;
3953 else
3954 kvm->arch.bsp_vcpu_id = arg;
3955 mutex_unlock(&kvm->lock);
3956 break;
ffde22ac
ES		 3957 case KVM_XEN_HVM_CONFIG: {
3958 r = -EFAULT;
3959 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3960 sizeof(struct kvm_xen_hvm_config)))
3961 goto out;
3962 r = -EINVAL;
3963 if (kvm->arch.xen_hvm_config.flags)
3964 goto out;
3965 r = 0;
3966 break;
3967 }
afbcf7ab 3968 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3969 struct kvm_clock_data user_ns;
3970 u64 now_ns;
3971 s64 delta;
3972
3973 r = -EFAULT;
3974 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3975 goto out;
3976
3977 r = -EINVAL;
3978 if (user_ns.flags)
3979 goto out;
3980
3981 r = 0;
395c6b0a 3982 local_irq_disable();
759379dd 3983 now_ns = get_kernel_ns();
afbcf7ab 3984 delta = user_ns.clock - now_ns;
395c6b0a 3985 local_irq_enable();
afbcf7ab 3986 kvm->arch.kvmclock_offset = delta;
2e762ff7 3987 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3988 break;
3989 }
3990 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3991 struct kvm_clock_data user_ns;
3992 u64 now_ns;
3993
395c6b0a 3994 local_irq_disable();
759379dd 3995 now_ns = get_kernel_ns();
afbcf7ab 3996 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3997 local_irq_enable();
afbcf7ab 3998 user_ns.flags = 0;
97e69aa6 3999 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4000
4001 r = -EFAULT;
4002 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4003 goto out;
4004 r = 0;
4005 break;
4006 }
90de4a18
NA		 4007 case KVM_ENABLE_CAP: {
4008 struct kvm_enable_cap cap;
afbcf7ab 4009
90de4a18
NA		 4010 r = -EFAULT;
4011 if (copy_from_user(&cap, argp, sizeof(cap)))
4012 goto out;
4013 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4014 break;
4015 }
1fe779f8 4016 default:
c274e03a 4017 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4018 }
4019out:
4020 return r;
4021}
4022
a16b043c 4023static void kvm_init_msr_list(void)
043405e1
CO		 4024{
4025 u32 dummy[2];
4026 unsigned i, j;
4027
62ef68bb 4028 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4029 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4030 continue;
93c4adc7
PB		 4031
4032 /*
4033 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4034 * to the guests in some cases.
93c4adc7
PB		 4035 */
4036 switch (msrs_to_save[i]) {
4037 case MSR_IA32_BNDCFGS:
4038 if (!kvm_x86_ops->mpx_supported())
4039 continue;
4040 break;
9dbe6cf9
PB		 4041 case MSR_TSC_AUX:
4042 if (!kvm_x86_ops->rdtscp_supported())
4043 continue;
4044 break;
93c4adc7
PB		 4045 default:
4046 break;
4047 }
4048
043405e1
CO		 4049 if (j < i)
4050 msrs_to_save[j] = msrs_to_save[i];
4051 j++;
4052 }
4053 num_msrs_to_save = j;
62ef68bb
PB		 4054
4055 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4056 switch (emulated_msrs[i]) {
6d396b55
PB		 4057 case MSR_IA32_SMBASE:
4058 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4059 continue;
4060 break;
62ef68bb
PB		 4061 default:
4062 break;
4063 }
4064
4065 if (j < i)
4066 emulated_msrs[j] = emulated_msrs[i];
4067 j++;
4068 }
4069 num_emulated_msrs = j;
043405e1
CO		 4070}
4071
bda9020e
MT		 4072static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4073 const void *v)
bbd9b64e 4074{
70252a10
AK		 4075 int handled = 0;
4076 int n;
4077
4078 do {
4079 n = min(len, 8);
4080 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4081 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4082 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4083 break;
4084 handled += n;
4085 addr += n;
4086 len -= n;
4087 v += n;
4088 } while (len);
bbd9b64e 4089
70252a10 4090 return handled;
bbd9b64e
CO		 4091}
4092
bda9020e 4093static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4094{
70252a10
AK		 4095 int handled = 0;
4096 int n;
4097
4098 do {
4099 n = min(len, 8);
4100 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4101 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4102 addr, n, v))
4103 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4104 break;
4105 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4106 handled += n;
4107 addr += n;
4108 len -= n;
4109 v += n;
4110 } while (len);
bbd9b64e 4111
70252a10 4112 return handled;
bbd9b64e
CO		 4113}
4114
2dafc6c2
GN		 4115static void kvm_set_segment(struct kvm_vcpu *vcpu,
4116 struct kvm_segment *var, int seg)
4117{
4118 kvm_x86_ops->set_segment(vcpu, var, seg);
4119}
4120
4121void kvm_get_segment(struct kvm_vcpu *vcpu,
4122 struct kvm_segment *var, int seg)
4123{
4124 kvm_x86_ops->get_segment(vcpu, var, seg);
4125}
4126
54987b7a
PB		 4127gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4128 struct x86_exception *exception)
02f59dc9
JR		 4129{
4130 gpa_t t_gpa;
02f59dc9
JR		 4131
4132 BUG_ON(!mmu_is_nested(vcpu));
4133
4134 /* NPT walks are always user-walks */
4135 access |= PFERR_USER_MASK;
54987b7a 4136 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4137
4138 return t_gpa;
4139}
4140
ab9ae313
AK		 4141gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4142 struct x86_exception *exception)
1871c602
GN		 4143{
4144 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4145 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4146}
4147
ab9ae313
AK		 4148 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4149 struct x86_exception *exception)
1871c602
GN		 4150{
4151 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4152 access |= PFERR_FETCH_MASK;
ab9ae313 4153 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4154}
4155
ab9ae313
AK		 4156gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4157 struct x86_exception *exception)
1871c602
GN		 4158{
4159 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4160 access |= PFERR_WRITE_MASK;
ab9ae313 4161 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4162}
4163
4164/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4165gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4166 struct x86_exception *exception)
1871c602 4167{
ab9ae313 4168 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4169}
4170
4171static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4172 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4173 struct x86_exception *exception)
bbd9b64e
CO		 4174{
4175 void *data = val;
10589a46 4176 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4177
4178 while (bytes) {
14dfe855 4179 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4180 exception);
bbd9b64e 4181 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4182 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4183 int ret;
4184
bcc55cba 4185 if (gpa == UNMAPPED_GVA)
ab9ae313 4186 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4187 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4188 offset, toread);
10589a46 4189 if (ret < 0) {
c3cd7ffa 4190 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4191 goto out;
4192 }
bbd9b64e 4193
77c2002e
IE		 4194 bytes -= toread;
4195 data += toread;
4196 addr += toread;
bbd9b64e 4197 }
10589a46 4198out:
10589a46 4199 return r;
bbd9b64e 4200}
77c2002e 4201
1871c602 4202/* used for instruction fetching */
0f65dd70
AK		 4203static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4204 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4205 struct x86_exception *exception)
1871c602 4206{
0f65dd70 4207 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4208 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4209 unsigned offset;
4210 int ret;
0f65dd70 4211
44583cba
PB		 4212 /* Inline kvm_read_guest_virt_helper for speed. */
4213 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4214 exception);
4215 if (unlikely(gpa == UNMAPPED_GVA))
4216 return X86EMUL_PROPAGATE_FAULT;
4217
4218 offset = addr & (PAGE_SIZE-1);
4219 if (WARN_ON(offset + bytes > PAGE_SIZE))
4220 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4221 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4222 offset, bytes);
44583cba
PB		 4223 if (unlikely(ret < 0))
4224 return X86EMUL_IO_NEEDED;
4225
4226 return X86EMUL_CONTINUE;
1871c602
GN		 4227}
4228
064aea77 4229int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4230 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4231 struct x86_exception *exception)
1871c602 4232{
0f65dd70 4233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4234 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4235
1871c602 4236 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4237 exception);
1871c602 4238}
064aea77 4239EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4240
0f65dd70
AK		 4241static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4242 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4243 struct x86_exception *exception)
1871c602 4244{
0f65dd70 4245 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4246 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4247}
4248
7a036a6f
RK		 4249static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4250 unsigned long addr, void *val, unsigned int bytes)
4251{
4252 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4253 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4254
4255 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4256}
4257
6a4d7550 4258int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4259 gva_t addr, void *val,
2dafc6c2 4260 unsigned int bytes,
bcc55cba 4261 struct x86_exception *exception)
77c2002e 4262{
0f65dd70 4263 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4264 void *data = val;
4265 int r = X86EMUL_CONTINUE;
4266
4267 while (bytes) {
14dfe855
JR		 4268 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4269 PFERR_WRITE_MASK,
ab9ae313 4270 exception);
77c2002e
IE		 4271 unsigned offset = addr & (PAGE_SIZE-1);
4272 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4273 int ret;
4274
bcc55cba 4275 if (gpa == UNMAPPED_GVA)
ab9ae313 4276 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4277 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4278 if (ret < 0) {
c3cd7ffa 4279 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4280 goto out;
4281 }
4282
4283 bytes -= towrite;
4284 data += towrite;
4285 addr += towrite;
4286 }
4287out:
4288 return r;
4289}
6a4d7550 4290EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4291
af7cc7d1
XG		 4292static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4293 gpa_t *gpa, struct x86_exception *exception,
4294 bool write)
4295{
97d64b78
AK		 4296 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4297 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4298
97d64b78 4299 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4300 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4301 vcpu->arch.access, access)) {
bebb106a
XG		 4302 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4303 (gva & (PAGE_SIZE - 1));
4f022648 4304 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4305 return 1;
4306 }
4307
af7cc7d1
XG		 4308 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4309
4310 if (*gpa == UNMAPPED_GVA)
4311 return -1;
4312
4313 /* For APIC access vmexit */
4314 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4315 return 1;
4316
4f022648
XG		 4317 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4318 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4319 return 1;
4f022648 4320 }
bebb106a 4321
af7cc7d1
XG		 4322 return 0;
4323}
4324
3200f405 4325int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4326 const void *val, int bytes)
bbd9b64e
CO		 4327{
4328 int ret;
4329
54bf36aa 4330 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4331 if (ret < 0)
bbd9b64e 4332 return 0;
f57f2ef5 4333 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4334 return 1;
4335}
4336
77d197b2
XG		 4337struct read_write_emulator_ops {
4338 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4339 int bytes);
4340 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4341 void *val, int bytes);
4342 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4343 int bytes, void *val);
4344 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4345 void *val, int bytes);
4346 bool write;
4347};
4348
4349static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4350{
4351 if (vcpu->mmio_read_completed) {
77d197b2 4352 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4353 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4354 vcpu->mmio_read_completed = 0;
4355 return 1;
4356 }
4357
4358 return 0;
4359}
4360
4361static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4362 void *val, int bytes)
4363{
54bf36aa 4364 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4365}
4366
4367static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4368 void *val, int bytes)
4369{
4370 return emulator_write_phys(vcpu, gpa, val, bytes);
4371}
4372
4373static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4374{
4375 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4376 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4377}
4378
4379static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4380 void *val, int bytes)
4381{
4382 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4383 return X86EMUL_IO_NEEDED;
4384}
4385
4386static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4387 void *val, int bytes)
4388{
f78146b0
AK		 4389 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4390
87da7e66 4391 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4392 return X86EMUL_CONTINUE;
4393}
4394
0fbe9b0b 4395static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4396 .read_write_prepare = read_prepare,
4397 .read_write_emulate = read_emulate,
4398 .read_write_mmio = vcpu_mmio_read,
4399 .read_write_exit_mmio = read_exit_mmio,
4400};
4401
0fbe9b0b 4402static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4403 .read_write_emulate = write_emulate,
4404 .read_write_mmio = write_mmio,
4405 .read_write_exit_mmio = write_exit_mmio,
4406 .write = true,
4407};
4408
22388a3c
XG		 4409static int emulator_read_write_onepage(unsigned long addr, void *val,
4410 unsigned int bytes,
4411 struct x86_exception *exception,
4412 struct kvm_vcpu *vcpu,
0fbe9b0b 4413 const struct read_write_emulator_ops *ops)
bbd9b64e 4414{
af7cc7d1
XG		 4415 gpa_t gpa;
4416 int handled, ret;
22388a3c 4417 bool write = ops->write;
f78146b0 4418 struct kvm_mmio_fragment *frag;
10589a46 4419
22388a3c 4420 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4421
af7cc7d1 4422 if (ret < 0)
bbd9b64e 4423 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4424
4425 /* For APIC access vmexit */
af7cc7d1 4426 if (ret)
bbd9b64e
CO		 4427 goto mmio;
4428
22388a3c 4429 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4430 return X86EMUL_CONTINUE;
4431
4432mmio:
4433 /*
4434 * Is this MMIO handled locally?
4435 */
22388a3c 4436 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4437 if (handled == bytes)
bbd9b64e 4438 return X86EMUL_CONTINUE;
bbd9b64e 4439
70252a10
AK		 4440 gpa += handled;
4441 bytes -= handled;
4442 val += handled;
4443
87da7e66
XG		 4444 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4445 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4446 frag->gpa = gpa;
4447 frag->data = val;
4448 frag->len = bytes;
f78146b0 4449 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4450}
4451
52eb5a6d
XL		 4452static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4453 unsigned long addr,
22388a3c
XG		 4454 void *val, unsigned int bytes,
4455 struct x86_exception *exception,
0fbe9b0b 4456 const struct read_write_emulator_ops *ops)
bbd9b64e 4457{
0f65dd70 4458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4459 gpa_t gpa;
4460 int rc;
4461
4462 if (ops->read_write_prepare &&
4463 ops->read_write_prepare(vcpu, val, bytes))
4464 return X86EMUL_CONTINUE;
4465
4466 vcpu->mmio_nr_fragments = 0;
0f65dd70 4467
bbd9b64e
CO		 4468 /* Crossing a page boundary? */
4469 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4470 int now;
bbd9b64e
CO		 4471
4472 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4473 rc = emulator_read_write_onepage(addr, val, now, exception,
4474 vcpu, ops);
4475
bbd9b64e
CO		 4476 if (rc != X86EMUL_CONTINUE)
4477 return rc;
4478 addr += now;
bac15531
NA		 4479 if (ctxt->mode != X86EMUL_MODE_PROT64)
4480 addr = (u32)addr;
bbd9b64e
CO		 4481 val += now;
4482 bytes -= now;
4483 }
22388a3c 4484
f78146b0
AK		 4485 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4486 vcpu, ops);
4487 if (rc != X86EMUL_CONTINUE)
4488 return rc;
4489
4490 if (!vcpu->mmio_nr_fragments)
4491 return rc;
4492
4493 gpa = vcpu->mmio_fragments[0].gpa;
4494
4495 vcpu->mmio_needed = 1;
4496 vcpu->mmio_cur_fragment = 0;
4497
87da7e66 4498 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4499 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4500 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4501 vcpu->run->mmio.phys_addr = gpa;
4502
4503 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4504}
4505
4506static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4507 unsigned long addr,
4508 void *val,
4509 unsigned int bytes,
4510 struct x86_exception *exception)
4511{
4512 return emulator_read_write(ctxt, addr, val, bytes,
4513 exception, &read_emultor);
4514}
4515
52eb5a6d 4516static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4517 unsigned long addr,
4518 const void *val,
4519 unsigned int bytes,
4520 struct x86_exception *exception)
4521{
4522 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4523 exception, &write_emultor);
bbd9b64e 4524}
bbd9b64e 4525
daea3e73
AK		 4526#define CMPXCHG_TYPE(t, ptr, old, new) \
4527 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4528
4529#ifdef CONFIG_X86_64
4530# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4531#else
4532# define CMPXCHG64(ptr, old, new) \
9749a6c0 4533 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4534#endif
4535
0f65dd70
AK		 4536static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4537 unsigned long addr,
bbd9b64e
CO		 4538 const void *old,
4539 const void *new,
4540 unsigned int bytes,
0f65dd70 4541 struct x86_exception *exception)
bbd9b64e 4542{
0f65dd70 4543 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4544 gpa_t gpa;
4545 struct page *page;
4546 char *kaddr;
4547 bool exchanged;
2bacc55c 4548
daea3e73
AK		 4549 /* guests cmpxchg8b have to be emulated atomically */
4550 if (bytes > 8 || (bytes & (bytes - 1)))
4551 goto emul_write;
10589a46 4552
daea3e73 4553 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4554
daea3e73
AK		 4555 if (gpa == UNMAPPED_GVA ||
4556 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4557 goto emul_write;
2bacc55c 4558
daea3e73
AK		 4559 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4560 goto emul_write;
72dc67a6 4561
54bf36aa 4562 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4563 if (is_error_page(page))
c19b8bd6 4564 goto emul_write;
72dc67a6 4565
8fd75e12 4566 kaddr = kmap_atomic(page);
daea3e73
AK		 4567 kaddr += offset_in_page(gpa);
4568 switch (bytes) {
4569 case 1:
4570 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4571 break;
4572 case 2:
4573 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4574 break;
4575 case 4:
4576 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4577 break;
4578 case 8:
4579 exchanged = CMPXCHG64(kaddr, old, new);
4580 break;
4581 default:
4582 BUG();
2bacc55c 4583 }
8fd75e12 4584 kunmap_atomic(kaddr);
daea3e73
AK		 4585 kvm_release_page_dirty(page);
4586
4587 if (!exchanged)
4588 return X86EMUL_CMPXCHG_FAILED;
4589
54bf36aa 4590 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4591 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4592
4593 return X86EMUL_CONTINUE;
4a5f48f6 4594
3200f405 4595emul_write:
daea3e73 4596 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4597
0f65dd70 4598 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4599}
4600
cf8f70bf
GN		 4601static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4602{
4603 /* TODO: String I/O for in kernel device */
4604 int r;
4605
4606 if (vcpu->arch.pio.in)
e32edf4f 4607 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4608 vcpu->arch.pio.size, pd);
4609 else
e32edf4f 4610 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4611 vcpu->arch.pio.port, vcpu->arch.pio.size,
4612 pd);
4613 return r;
4614}
4615
6f6fbe98
XG		 4616static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4617 unsigned short port, void *val,
4618 unsigned int count, bool in)
cf8f70bf 4619{
cf8f70bf 4620 vcpu->arch.pio.port = port;
6f6fbe98 4621 vcpu->arch.pio.in = in;
7972995b 4622 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4623 vcpu->arch.pio.size = size;
4624
4625 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4626 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4627 return 1;
4628 }
4629
4630 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4631 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4632 vcpu->run->io.size = size;
4633 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4634 vcpu->run->io.count = count;
4635 vcpu->run->io.port = port;
4636
4637 return 0;
4638}
4639
6f6fbe98
XG		 4640static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4641 int size, unsigned short port, void *val,
4642 unsigned int count)
cf8f70bf 4643{
ca1d4a9e 4644 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4645 int ret;
ca1d4a9e 4646
6f6fbe98
XG		 4647 if (vcpu->arch.pio.count)
4648 goto data_avail;
cf8f70bf 4649
6f6fbe98
XG		 4650 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4651 if (ret) {
4652data_avail:
4653 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4654 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4655 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4656 return 1;
4657 }
4658
cf8f70bf
GN		 4659 return 0;
4660}
4661
6f6fbe98
XG		 4662static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4663 int size, unsigned short port,
4664 const void *val, unsigned int count)
4665{
4666 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4667
4668 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4669 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4670 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4671}
4672
bbd9b64e
CO		 4673static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4674{
4675 return kvm_x86_ops->get_segment_base(vcpu, seg);
4676}
4677
3cb16fe7 4678static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4679{
3cb16fe7 4680 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4681}
4682
5cb56059 4683int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4684{
4685 if (!need_emulate_wbinvd(vcpu))
4686 return X86EMUL_CONTINUE;
4687
4688 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4689 int cpu = get_cpu();
4690
4691 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4692 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4693 wbinvd_ipi, NULL, 1);
2eec7343 4694 put_cpu();
f5f48ee1 4695 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4696 } else
4697 wbinvd();
f5f48ee1
SY		 4698 return X86EMUL_CONTINUE;
4699}
5cb56059
JS		 4700
4701int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4702{
4703 kvm_x86_ops->skip_emulated_instruction(vcpu);
4704 return kvm_emulate_wbinvd_noskip(vcpu);
4705}
f5f48ee1
SY		 4706EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4707
5cb56059
JS		 4708
4709
bcaf5cc5
AK		 4710static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4711{
5cb56059 4712 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4713}
4714
52eb5a6d
XL		 4715static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4716 unsigned long *dest)
bbd9b64e 4717{
16f8a6f9 4718 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4719}
4720
52eb5a6d
XL		 4721static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4722 unsigned long value)
bbd9b64e 4723{
338dbc97 4724
717746e3 4725 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4726}
4727
52a46617 4728static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4729{
52a46617 4730 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4731}
4732
717746e3 4733static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4734{
717746e3 4735 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4736 unsigned long value;
4737
4738 switch (cr) {
4739 case 0:
4740 value = kvm_read_cr0(vcpu);
4741 break;
4742 case 2:
4743 value = vcpu->arch.cr2;
4744 break;
4745 case 3:
9f8fe504 4746 value = kvm_read_cr3(vcpu);
52a46617
GN		 4747 break;
4748 case 4:
4749 value = kvm_read_cr4(vcpu);
4750 break;
4751 case 8:
4752 value = kvm_get_cr8(vcpu);
4753 break;
4754 default:
a737f256 4755 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4756 return 0;
4757 }
4758
4759 return value;
4760}
4761
717746e3 4762static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4763{
717746e3 4764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4765 int res = 0;
4766
52a46617
GN		 4767 switch (cr) {
4768 case 0:
49a9b07e 4769 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4770 break;
4771 case 2:
4772 vcpu->arch.cr2 = val;
4773 break;
4774 case 3:
2390218b 4775 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4776 break;
4777 case 4:
a83b29c6 4778 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4779 break;
4780 case 8:
eea1cff9 4781 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4782 break;
4783 default:
a737f256 4784 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4785 res = -1;
52a46617 4786 }
0f12244f
GN		 4787
4788 return res;
52a46617
GN		 4789}
4790
717746e3 4791static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4792{
717746e3 4793 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4794}
4795
4bff1e86 4796static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4797{
4bff1e86 4798 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4799}
4800
4bff1e86 4801static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4802{
4bff1e86 4803 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4804}
4805
1ac9d0cf
AK		 4806static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4807{
4808 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4809}
4810
4811static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4812{
4813 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4814}
4815
4bff1e86
AK		 4816static unsigned long emulator_get_cached_segment_base(
4817 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4818{
4bff1e86 4819 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4820}
4821
1aa36616
AK		 4822static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4823 struct desc_struct *desc, u32 *base3,
4824 int seg)
2dafc6c2
GN		 4825{
4826 struct kvm_segment var;
4827
4bff1e86 4828 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4829 *selector = var.selector;
2dafc6c2 4830
378a8b09
GN		 4831 if (var.unusable) {
4832 memset(desc, 0, sizeof(*desc));
2dafc6c2 4833 return false;
378a8b09 4834 }
2dafc6c2
GN		 4835
4836 if (var.g)
4837 var.limit >>= 12;
4838 set_desc_limit(desc, var.limit);
4839 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4840#ifdef CONFIG_X86_64
4841 if (base3)
4842 *base3 = var.base >> 32;
4843#endif
2dafc6c2
GN		 4844 desc->type = var.type;
4845 desc->s = var.s;
4846 desc->dpl = var.dpl;
4847 desc->p = var.present;
4848 desc->avl = var.avl;
4849 desc->l = var.l;
4850 desc->d = var.db;
4851 desc->g = var.g;
4852
4853 return true;
4854}
4855
1aa36616
AK		 4856static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4857 struct desc_struct *desc, u32 base3,
4858 int seg)
2dafc6c2 4859{
4bff1e86 4860 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4861 struct kvm_segment var;
4862
1aa36616 4863 var.selector = selector;
2dafc6c2 4864 var.base = get_desc_base(desc);
5601d05b
GN		 4865#ifdef CONFIG_X86_64
4866 var.base |= ((u64)base3) << 32;
4867#endif
2dafc6c2
GN		 4868 var.limit = get_desc_limit(desc);
4869 if (desc->g)
4870 var.limit = (var.limit << 12) | 0xfff;
4871 var.type = desc->type;
2dafc6c2
GN		 4872 var.dpl = desc->dpl;
4873 var.db = desc->d;
4874 var.s = desc->s;
4875 var.l = desc->l;
4876 var.g = desc->g;
4877 var.avl = desc->avl;
4878 var.present = desc->p;
4879 var.unusable = !var.present;
4880 var.padding = 0;
4881
4882 kvm_set_segment(vcpu, &var, seg);
4883 return;
4884}
4885
717746e3
AK		 4886static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4887 u32 msr_index, u64 *pdata)
4888{
609e36d3
PB		 4889 struct msr_data msr;
4890 int r;
4891
4892 msr.index = msr_index;
4893 msr.host_initiated = false;
4894 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4895 if (r)
4896 return r;
4897
4898 *pdata = msr.data;
4899 return 0;
717746e3
AK		 4900}
4901
4902static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4903 u32 msr_index, u64 data)
4904{
8fe8ab46
WA		 4905 struct msr_data msr;
4906
4907 msr.data = data;
4908 msr.index = msr_index;
4909 msr.host_initiated = false;
4910 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4911}
4912
64d60670
PB		 4913static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4914{
4915 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4916
4917 return vcpu->arch.smbase;
4918}
4919
4920static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4921{
4922 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4923
4924 vcpu->arch.smbase = smbase;
4925}
4926
67f4d428
NA		 4927static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4928 u32 pmc)
4929{
c6702c9d 4930 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4931}
4932
222d21aa
AK		 4933static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4934 u32 pmc, u64 *pdata)
4935{
c6702c9d 4936 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4937}
4938
6c3287f7
AK		 4939static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4940{
4941 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4942}
4943
5037f6f3
AK		 4944static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4945{
4946 preempt_disable();
5197b808 4947 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4948 /*
4949 * CR0.TS may reference the host fpu state, not the guest fpu state,
4950 * so it may be clear at this point.
4951 */
4952 clts();
4953}
4954
4955static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4956{
4957 preempt_enable();
4958}
4959
2953538e 4960static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4961 struct x86_instruction_info *info,
c4f035c6
AK		 4962 enum x86_intercept_stage stage)
4963{
2953538e 4964 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4965}
4966
0017f93a 4967static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4968 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4969{
0017f93a 4970 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4971}
4972
dd856efa
AK		 4973static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4974{
4975 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4976}
4977
4978static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4979{
4980 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4981}
4982
801806d9
NA		 4983static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4984{
4985 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4986}
4987
0225fb50 4988static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4989 .read_gpr = emulator_read_gpr,
4990 .write_gpr = emulator_write_gpr,
1871c602 4991 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4992 .write_std = kvm_write_guest_virt_system,
7a036a6f 4993 .read_phys = kvm_read_guest_phys_system,
1871c602 4994 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4995 .read_emulated = emulator_read_emulated,
4996 .write_emulated = emulator_write_emulated,
4997 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4998 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4999 .pio_in_emulated = emulator_pio_in_emulated,
5000 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5001 .get_segment = emulator_get_segment,
5002 .set_segment = emulator_set_segment,
5951c442 5003 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5004 .get_gdt = emulator_get_gdt,
160ce1f1 5005 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5006 .set_gdt = emulator_set_gdt,
5007 .set_idt = emulator_set_idt,
52a46617
GN		 5008 .get_cr = emulator_get_cr,
5009 .set_cr = emulator_set_cr,
9c537244 5010 .cpl = emulator_get_cpl,
35aa5375
GN		 5011 .get_dr = emulator_get_dr,
5012 .set_dr = emulator_set_dr,
64d60670
PB		 5013 .get_smbase = emulator_get_smbase,
5014 .set_smbase = emulator_set_smbase,
717746e3
AK		 5015 .set_msr = emulator_set_msr,
5016 .get_msr = emulator_get_msr,
67f4d428 5017 .check_pmc = emulator_check_pmc,
222d21aa 5018 .read_pmc = emulator_read_pmc,
6c3287f7 5019 .halt = emulator_halt,
bcaf5cc5 5020 .wbinvd = emulator_wbinvd,
d6aa1000 5021 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5022 .get_fpu = emulator_get_fpu,
5023 .put_fpu = emulator_put_fpu,
c4f035c6 5024 .intercept = emulator_intercept,
bdb42f5a 5025 .get_cpuid = emulator_get_cpuid,
801806d9 5026 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5027};
5028
95cb2295
GN		 5029static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5030{
37ccdcbe 5031 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5032 /*
5033 * an sti; sti; sequence only disable interrupts for the first
5034 * instruction. So, if the last instruction, be it emulated or
5035 * not, left the system with the INT_STI flag enabled, it
5036 * means that the last instruction is an sti. We should not
5037 * leave the flag on in this case. The same goes for mov ss
5038 */
37ccdcbe
PB		 5039 if (int_shadow & mask)
5040 mask = 0;
6addfc42 5041 if (unlikely(int_shadow || mask)) {
95cb2295 5042 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5043 if (!mask)
5044 kvm_make_request(KVM_REQ_EVENT, vcpu);
5045 }
95cb2295
GN		 5046}
5047
ef54bcfe 5048static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5049{
5050 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5051 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5052 return kvm_propagate_fault(vcpu, &ctxt->exception);
5053
5054 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5055 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5056 ctxt->exception.error_code);
54b8486f 5057 else
da9cb575 5058 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5059 return false;
54b8486f
GN		 5060}
5061
8ec4722d
MG		 5062static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5063{
adf52235 5064 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5065 int cs_db, cs_l;
5066
8ec4722d
MG		 5067 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5068
adf52235
TY		 5069 ctxt->eflags = kvm_get_rflags(vcpu);
5070 ctxt->eip = kvm_rip_read(vcpu);
5071 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5072 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5073 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5074 cs_db ? X86EMUL_MODE_PROT32 :
5075 X86EMUL_MODE_PROT16;
a584539b 5076 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5077 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5078 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5079 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5080
dd856efa 5081 init_decode_cache(ctxt);
7ae441ea 5082 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5083}
5084
71f9833b 5085int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5086{
9d74191a 5087 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5088 int ret;
5089
5090 init_emulate_ctxt(vcpu);
5091
9dac77fa
AK		 5092 ctxt->op_bytes = 2;
5093 ctxt->ad_bytes = 2;
5094 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5095 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5096
5097 if (ret != X86EMUL_CONTINUE)
5098 return EMULATE_FAIL;
5099
9dac77fa 5100 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5101 kvm_rip_write(vcpu, ctxt->eip);
5102 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5103
5104 if (irq == NMI_VECTOR)
7460fb4a 5105 vcpu->arch.nmi_pending = 0;
63995653
MG		 5106 else
5107 vcpu->arch.interrupt.pending = false;
5108
5109 return EMULATE_DONE;
5110}
5111EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5112
6d77dbfc
GN		 5113static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5114{
fc3a9157
JR		 5115 int r = EMULATE_DONE;
5116
6d77dbfc
GN		 5117 ++vcpu->stat.insn_emulation_fail;
5118 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5119 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5120 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5121 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5122 vcpu->run->internal.ndata = 0;
5123 r = EMULATE_FAIL;
5124 }
6d77dbfc 5125 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5126
5127 return r;
6d77dbfc
GN		 5128}
5129
93c05d3e 5130static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5131 bool write_fault_to_shadow_pgtable,
5132 int emulation_type)
a6f177ef 5133{
95b3cf69 5134 gpa_t gpa = cr2;
8e3d9d06 5135 pfn_t pfn;
a6f177ef 5136
991eebf9
GN		 5137 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5138 return false;
5139
95b3cf69
XG		 5140 if (!vcpu->arch.mmu.direct_map) {
5141 /*
5142 * Write permission should be allowed since only
5143 * write access need to be emulated.
5144 */
5145 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5146
95b3cf69
XG		 5147 /*
5148 * If the mapping is invalid in guest, let cpu retry
5149 * it to generate fault.
5150 */
5151 if (gpa == UNMAPPED_GVA)
5152 return true;
5153 }
a6f177ef 5154
8e3d9d06
XG		 5155 /*
5156 * Do not retry the unhandleable instruction if it faults on the
5157 * readonly host memory, otherwise it will goto a infinite loop:
5158 * retry instruction -> write #PF -> emulation fail -> retry
5159 * instruction -> ...
5160 */
5161 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5162
5163 /*
5164 * If the instruction failed on the error pfn, it can not be fixed,
5165 * report the error to userspace.
5166 */
5167 if (is_error_noslot_pfn(pfn))
5168 return false;
5169
5170 kvm_release_pfn_clean(pfn);
5171
5172 /* The instructions are well-emulated on direct mmu. */
5173 if (vcpu->arch.mmu.direct_map) {
5174 unsigned int indirect_shadow_pages;
5175
5176 spin_lock(&vcpu->kvm->mmu_lock);
5177 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5178 spin_unlock(&vcpu->kvm->mmu_lock);
5179
5180 if (indirect_shadow_pages)
5181 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5182
a6f177ef 5183 return true;
8e3d9d06 5184 }
a6f177ef 5185
95b3cf69
XG		 5186 /*
5187 * if emulation was due to access to shadowed page table
5188 * and it failed try to unshadow page and re-enter the
5189 * guest to let CPU execute the instruction.
5190 */
5191 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5192
5193 /*
5194 * If the access faults on its page table, it can not
5195 * be fixed by unprotecting shadow page and it should
5196 * be reported to userspace.
5197 */
5198 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5199}
5200
1cb3f3ae
XG		 5201static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5202 unsigned long cr2, int emulation_type)
5203{
5204 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5205 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5206
5207 last_retry_eip = vcpu->arch.last_retry_eip;
5208 last_retry_addr = vcpu->arch.last_retry_addr;
5209
5210 /*
5211 * If the emulation is caused by #PF and it is non-page_table
5212 * writing instruction, it means the VM-EXIT is caused by shadow
5213 * page protected, we can zap the shadow page and retry this
5214 * instruction directly.
5215 *
5216 * Note: if the guest uses a non-page-table modifying instruction
5217 * on the PDE that points to the instruction, then we will unmap
5218 * the instruction and go to an infinite loop. So, we cache the
5219 * last retried eip and the last fault address, if we meet the eip
5220 * and the address again, we can break out of the potential infinite
5221 * loop.
5222 */
5223 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5224
5225 if (!(emulation_type & EMULTYPE_RETRY))
5226 return false;
5227
5228 if (x86_page_table_writing_insn(ctxt))
5229 return false;
5230
5231 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5232 return false;
5233
5234 vcpu->arch.last_retry_eip = ctxt->eip;
5235 vcpu->arch.last_retry_addr = cr2;
5236
5237 if (!vcpu->arch.mmu.direct_map)
5238 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5239
22368028 5240 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5241
5242 return true;
5243}
5244
716d51ab
GN		 5245static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5246static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5247
64d60670 5248static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5249{
64d60670 5250 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5251 /* This is a good place to trace that we are exiting SMM. */
5252 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5253
64d60670
PB		 5254 if (unlikely(vcpu->arch.smi_pending)) {
5255 kvm_make_request(KVM_REQ_SMI, vcpu);
5256 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5257 } else {
5258 /* Process a latched INIT, if any. */
5259 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5260 }
5261 }
699023e2
PB		 5262
5263 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5264}
5265
5266static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5267{
5268 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5269
a584539b 5270 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5271
5272 if (changed & HF_SMM_MASK)
5273 kvm_smm_changed(vcpu);
a584539b
PB		 5274}
5275
4a1e10d5
PB		 5276static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5277 unsigned long *db)
5278{
5279 u32 dr6 = 0;
5280 int i;
5281 u32 enable, rwlen;
5282
5283 enable = dr7;
5284 rwlen = dr7 >> 16;
5285 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5286 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5287 dr6 |= (1 << i);
5288 return dr6;
5289}
5290
6addfc42 5291static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5292{
5293 struct kvm_run *kvm_run = vcpu->run;
5294
5295 /*
6addfc42
PB		 5296 * rflags is the old, "raw" value of the flags. The new value has
5297 * not been saved yet.
663f4c61
PB		 5298 *
5299 * This is correct even for TF set by the guest, because "the
5300 * processor will not generate this exception after the instruction
5301 * that sets the TF flag".
5302 */
663f4c61
PB		 5303 if (unlikely(rflags & X86_EFLAGS_TF)) {
5304 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5305 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5306 DR6_RTM;
663f4c61
PB		 5307 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5308 kvm_run->debug.arch.exception = DB_VECTOR;
5309 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5310 *r = EMULATE_USER_EXIT;
5311 } else {
5312 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5313 /*
5314 * "Certain debug exceptions may clear bit 0-3. The
5315 * remaining contents of the DR6 register are never
5316 * cleared by the processor".
5317 */
5318 vcpu->arch.dr6 &= ~15;
6f43ed01 5319 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5320 kvm_queue_exception(vcpu, DB_VECTOR);
5321 }
5322 }
5323}
5324
4a1e10d5
PB		 5325static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5326{
4a1e10d5
PB		 5327 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5328 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5329 struct kvm_run *kvm_run = vcpu->run;
5330 unsigned long eip = kvm_get_linear_rip(vcpu);
5331 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5332 vcpu->arch.guest_debug_dr7,
5333 vcpu->arch.eff_db);
5334
5335 if (dr6 != 0) {
6f43ed01 5336 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5337 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5338 kvm_run->debug.arch.exception = DB_VECTOR;
5339 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5340 *r = EMULATE_USER_EXIT;
5341 return true;
5342 }
5343 }
5344
4161a569
NA		 5345 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5346 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5347 unsigned long eip = kvm_get_linear_rip(vcpu);
5348 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5349 vcpu->arch.dr7,
5350 vcpu->arch.db);
5351
5352 if (dr6 != 0) {
5353 vcpu->arch.dr6 &= ~15;
6f43ed01 5354 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5355 kvm_queue_exception(vcpu, DB_VECTOR);
5356 *r = EMULATE_DONE;
5357 return true;
5358 }
5359 }
5360
5361 return false;
5362}
5363
51d8b661
AP		 5364int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5365 unsigned long cr2,
dc25e89e
AP		 5366 int emulation_type,
5367 void *insn,
5368 int insn_len)
bbd9b64e 5369{
95cb2295 5370 int r;
9d74191a 5371 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5372 bool writeback = true;
93c05d3e 5373 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5374
93c05d3e
XG		 5375 /*
5376 * Clear write_fault_to_shadow_pgtable here to ensure it is
5377 * never reused.
5378 */
5379 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5380 kvm_clear_exception_queue(vcpu);
8d7d8102 5381
571008da 5382 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5383 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5384
5385 /*
5386 * We will reenter on the same instruction since
5387 * we do not set complete_userspace_io. This does not
5388 * handle watchpoints yet, those would be handled in
5389 * the emulate_ops.
5390 */
5391 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5392 return r;
5393
9d74191a
TY		 5394 ctxt->interruptibility = 0;
5395 ctxt->have_exception = false;
e0ad0b47 5396 ctxt->exception.vector = -1;
9d74191a 5397 ctxt->perm_ok = false;
bbd9b64e 5398
b51e974f 5399 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5400
9d74191a 5401 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5402
e46479f8 5403 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5404 ++vcpu->stat.insn_emulation;
1d2887e2 5405 if (r != EMULATION_OK) {
4005996e
AK		 5406 if (emulation_type & EMULTYPE_TRAP_UD)
5407 return EMULATE_FAIL;
991eebf9
GN		 5408 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5409 emulation_type))
bbd9b64e 5410 return EMULATE_DONE;
6d77dbfc
GN		 5411 if (emulation_type & EMULTYPE_SKIP)
5412 return EMULATE_FAIL;
5413 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5414 }
5415 }
5416
ba8afb6b 5417 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5418 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5419 if (ctxt->eflags & X86_EFLAGS_RF)
5420 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5421 return EMULATE_DONE;
5422 }
5423
1cb3f3ae
XG		 5424 if (retry_instruction(ctxt, cr2, emulation_type))
5425 return EMULATE_DONE;
5426
7ae441ea 5427 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5428 changes registers values during IO operation */
7ae441ea
GN		 5429 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5430 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5431 emulator_invalidate_register_cache(ctxt);
7ae441ea 5432 }
4d2179e1 5433
5cd21917 5434restart:
9d74191a 5435 r = x86_emulate_insn(ctxt);
bbd9b64e 5436
775fde86
JR		 5437 if (r == EMULATION_INTERCEPTED)
5438 return EMULATE_DONE;
5439
d2ddd1c4 5440 if (r == EMULATION_FAILED) {
991eebf9
GN		 5441 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5442 emulation_type))
c3cd7ffa
GN		 5443 return EMULATE_DONE;
5444
6d77dbfc 5445 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5446 }
5447
9d74191a 5448 if (ctxt->have_exception) {
d2ddd1c4 5449 r = EMULATE_DONE;
ef54bcfe
PB		 5450 if (inject_emulated_exception(vcpu))
5451 return r;
d2ddd1c4 5452 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5453 if (!vcpu->arch.pio.in) {
5454 /* FIXME: return into emulator if single-stepping. */
3457e419 5455 vcpu->arch.pio.count = 0;
0912c977 5456 } else {
7ae441ea 5457 writeback = false;
716d51ab
GN		 5458 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5459 }
ac0a48c3 5460 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5461 } else if (vcpu->mmio_needed) {
5462 if (!vcpu->mmio_is_write)
5463 writeback = false;
ac0a48c3 5464 r = EMULATE_USER_EXIT;
716d51ab 5465 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5466 } else if (r == EMULATION_RESTART)
5cd21917 5467 goto restart;
d2ddd1c4
GN		 5468 else
5469 r = EMULATE_DONE;
f850e2e6 5470
7ae441ea 5471 if (writeback) {
6addfc42 5472 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5473 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5474 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5475 if (vcpu->arch.hflags != ctxt->emul_flags)
5476 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5477 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5478 if (r == EMULATE_DONE)
6addfc42 5479 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5480 if (!ctxt->have_exception ||
5481 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5482 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5483
5484 /*
5485 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5486 * do nothing, and it will be requested again as soon as
5487 * the shadow expires. But we still need to check here,
5488 * because POPF has no interrupt shadow.
5489 */
5490 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5491 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5492 } else
5493 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5494
5495 return r;
de7d789a 5496}
51d8b661 5497EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5498
cf8f70bf 5499int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5500{
cf8f70bf 5501 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5502 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5503 size, port, &val, 1);
cf8f70bf 5504 /* do not return to emulator after return from userspace */
7972995b 5505 vcpu->arch.pio.count = 0;
de7d789a
CO		 5506 return ret;
5507}
cf8f70bf 5508EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5509
8cfdc000
ZA		 5510static void tsc_bad(void *info)
5511{
0a3aee0d 5512 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5513}
5514
5515static void tsc_khz_changed(void *data)
c8076604 5516{
8cfdc000
ZA		 5517 struct cpufreq_freqs *freq = data;
5518 unsigned long khz = 0;
5519
5520 if (data)
5521 khz = freq->new;
5522 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5523 khz = cpufreq_quick_get(raw_smp_processor_id());
5524 if (!khz)
5525 khz = tsc_khz;
0a3aee0d 5526 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5527}
5528
c8076604
GH		 5529static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5530 void *data)
5531{
5532 struct cpufreq_freqs *freq = data;
5533 struct kvm *kvm;
5534 struct kvm_vcpu *vcpu;
5535 int i, send_ipi = 0;
5536
8cfdc000
ZA		 5537 /*
5538 * We allow guests to temporarily run on slowing clocks,
5539 * provided we notify them after, or to run on accelerating
5540 * clocks, provided we notify them before. Thus time never
5541 * goes backwards.
5542 *
5543 * However, we have a problem. We can't atomically update
5544 * the frequency of a given CPU from this function; it is
5545 * merely a notifier, which can be called from any CPU.
5546 * Changing the TSC frequency at arbitrary points in time
5547 * requires a recomputation of local variables related to
5548 * the TSC for each VCPU. We must flag these local variables
5549 * to be updated and be sure the update takes place with the
5550 * new frequency before any guests proceed.
5551 *
5552 * Unfortunately, the combination of hotplug CPU and frequency
5553 * change creates an intractable locking scenario; the order
5554 * of when these callouts happen is undefined with respect to
5555 * CPU hotplug, and they can race with each other. As such,
5556 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5557 * undefined; you can actually have a CPU frequency change take
5558 * place in between the computation of X and the setting of the
5559 * variable. To protect against this problem, all updates of
5560 * the per_cpu tsc_khz variable are done in an interrupt
5561 * protected IPI, and all callers wishing to update the value
5562 * must wait for a synchronous IPI to complete (which is trivial
5563 * if the caller is on the CPU already). This establishes the
5564 * necessary total order on variable updates.
5565 *
5566 * Note that because a guest time update may take place
5567 * anytime after the setting of the VCPU's request bit, the
5568 * correct TSC value must be set before the request. However,
5569 * to ensure the update actually makes it to any guest which
5570 * starts running in hardware virtualization between the set
5571 * and the acquisition of the spinlock, we must also ping the
5572 * CPU after setting the request bit.
5573 *
5574 */
5575
c8076604
GH		 5576 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5577 return 0;
5578 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5579 return 0;
8cfdc000
ZA		 5580
5581 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5582
2f303b74 5583 spin_lock(&kvm_lock);
c8076604 5584 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5585 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5586 if (vcpu->cpu != freq->cpu)
5587 continue;
c285545f 5588 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5589 if (vcpu->cpu != smp_processor_id())
8cfdc000 5590 send_ipi = 1;
c8076604
GH		 5591 }
5592 }
2f303b74 5593 spin_unlock(&kvm_lock);
c8076604
GH		 5594
5595 if (freq->old < freq->new && send_ipi) {
5596 /*
5597 * We upscale the frequency. Must make the guest
5598 * doesn't see old kvmclock values while running with
5599 * the new frequency, otherwise we risk the guest sees
5600 * time go backwards.
5601 *
5602 * In case we update the frequency for another cpu
5603 * (which might be in guest context) send an interrupt
5604 * to kick the cpu out of guest context. Next time
5605 * guest context is entered kvmclock will be updated,
5606 * so the guest will not see stale values.
5607 */
8cfdc000 5608 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5609 }
5610 return 0;
5611}
5612
5613static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5614 .notifier_call = kvmclock_cpufreq_notifier
5615};
5616
5617static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5618 unsigned long action, void *hcpu)
5619{
5620 unsigned int cpu = (unsigned long)hcpu;
5621
5622 switch (action) {
5623 case CPU_ONLINE:
5624 case CPU_DOWN_FAILED:
5625 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5626 break;
5627 case CPU_DOWN_PREPARE:
5628 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5629 break;
5630 }
5631 return NOTIFY_OK;
5632}
5633
5634static struct notifier_block kvmclock_cpu_notifier_block = {
5635 .notifier_call = kvmclock_cpu_notifier,
5636 .priority = -INT_MAX
c8076604
GH		 5637};
5638
b820cc0c
ZA		 5639static void kvm_timer_init(void)
5640{
5641 int cpu;
5642
c285545f 5643 max_tsc_khz = tsc_khz;
460dd42e
SB		 5644
5645 cpu_notifier_register_begin();
b820cc0c 5646 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5647#ifdef CONFIG_CPU_FREQ
5648 struct cpufreq_policy policy;
5649 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5650 cpu = get_cpu();
5651 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5652 if (policy.cpuinfo.max_freq)
5653 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5654 put_cpu();
c285545f 5655#endif
b820cc0c
ZA		 5656 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5657 CPUFREQ_TRANSITION_NOTIFIER);
5658 }
c285545f 5659 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5660 for_each_online_cpu(cpu)
5661 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5662
5663 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5664 cpu_notifier_register_done();
5665
b820cc0c
ZA		 5666}
5667
ff9d07a0
ZY		 5668static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5669
f5132b01 5670int kvm_is_in_guest(void)
ff9d07a0 5671{
086c9855 5672 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5673}
5674
5675static int kvm_is_user_mode(void)
5676{
5677 int user_mode = 3;
dcf46b94 5678
086c9855
AS		 5679 if (__this_cpu_read(current_vcpu))
5680 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5681
ff9d07a0
ZY		 5682 return user_mode != 0;
5683}
5684
5685static unsigned long kvm_get_guest_ip(void)
5686{
5687 unsigned long ip = 0;
dcf46b94 5688
086c9855
AS		 5689 if (__this_cpu_read(current_vcpu))
5690 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5691
ff9d07a0
ZY		 5692 return ip;
5693}
5694
5695static struct perf_guest_info_callbacks kvm_guest_cbs = {
5696 .is_in_guest = kvm_is_in_guest,
5697 .is_user_mode = kvm_is_user_mode,
5698 .get_guest_ip = kvm_get_guest_ip,
5699};
5700
5701void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5702{
086c9855 5703 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5704}
5705EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5706
5707void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5708{
086c9855 5709 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5710}
5711EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5712
ce88decf
XG		 5713static void kvm_set_mmio_spte_mask(void)
5714{
5715 u64 mask;
5716 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5717
5718 /*
5719 * Set the reserved bits and the present bit of an paging-structure
5720 * entry to generate page fault with PFER.RSV = 1.
5721 */
885032b9 5722 /* Mask the reserved physical address bits. */
d1431483 5723 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5724
5725 /* Bit 62 is always reserved for 32bit host. */
5726 mask |= 0x3ull << 62;
5727
5728 /* Set the present bit. */
ce88decf
XG		 5729 mask |= 1ull;
5730
5731#ifdef CONFIG_X86_64
5732 /*
5733 * If reserved bit is not supported, clear the present bit to disable
5734 * mmio page fault.
5735 */
5736 if (maxphyaddr == 52)
5737 mask &= ~1ull;
5738#endif
5739
5740 kvm_mmu_set_mmio_spte_mask(mask);
5741}
5742
16e8d74d
MT		 5743#ifdef CONFIG_X86_64
5744static void pvclock_gtod_update_fn(struct work_struct *work)
5745{
d828199e
MT		 5746 struct kvm *kvm;
5747
5748 struct kvm_vcpu *vcpu;
5749 int i;
5750
2f303b74 5751 spin_lock(&kvm_lock);
d828199e
MT		 5752 list_for_each_entry(kvm, &vm_list, vm_list)
5753 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5754 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5755 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5756 spin_unlock(&kvm_lock);
16e8d74d
MT		 5757}
5758
5759static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5760
5761/*
5762 * Notification about pvclock gtod data update.
5763 */
5764static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5765 void *priv)
5766{
5767 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5768 struct timekeeper *tk = priv;
5769
5770 update_pvclock_gtod(tk);
5771
5772 /* disable master clock if host does not trust, or does not
5773 * use, TSC clocksource
5774 */
5775 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5776 atomic_read(&kvm_guest_has_master_clock) != 0)
5777 queue_work(system_long_wq, &pvclock_gtod_work);
5778
5779 return 0;
5780}
5781
5782static struct notifier_block pvclock_gtod_notifier = {
5783 .notifier_call = pvclock_gtod_notify,
5784};
5785#endif
5786
f8c16bba 5787int kvm_arch_init(void *opaque)
043405e1 5788{
b820cc0c 5789 int r;
6b61edf7 5790 struct kvm_x86_ops *ops = opaque;
f8c16bba 5791
f8c16bba
ZX		 5792 if (kvm_x86_ops) {
5793 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5794 r = -EEXIST;
5795 goto out;
f8c16bba
ZX		 5796 }
5797
5798 if (!ops->cpu_has_kvm_support()) {
5799 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5800 r = -EOPNOTSUPP;
5801 goto out;
f8c16bba
ZX		 5802 }
5803 if (ops->disabled_by_bios()) {
5804 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5805 r = -EOPNOTSUPP;
5806 goto out;
f8c16bba
ZX		 5807 }
5808
013f6a5d
MT		 5809 r = -ENOMEM;
5810 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5811 if (!shared_msrs) {
5812 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5813 goto out;
5814 }
5815
97db56ce
AK		 5816 r = kvm_mmu_module_init();
5817 if (r)
013f6a5d 5818 goto out_free_percpu;
97db56ce 5819
ce88decf 5820 kvm_set_mmio_spte_mask();
97db56ce 5821
f8c16bba 5822 kvm_x86_ops = ops;
920c8377 5823
7b52345e 5824 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5825 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5826
b820cc0c 5827 kvm_timer_init();
c8076604 5828
ff9d07a0
ZY		 5829 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5830
2acf923e
DC		 5831 if (cpu_has_xsave)
5832 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5833
c5cc421b 5834 kvm_lapic_init();
16e8d74d
MT		 5835#ifdef CONFIG_X86_64
5836 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5837#endif
5838
f8c16bba 5839 return 0;
56c6d28a 5840
013f6a5d
MT		 5841out_free_percpu:
5842 free_percpu(shared_msrs);
56c6d28a 5843out:
56c6d28a 5844 return r;
043405e1 5845}
8776e519 5846
f8c16bba
ZX		 5847void kvm_arch_exit(void)
5848{
ff9d07a0
ZY		 5849 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5850
888d256e
JK		 5851 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5852 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5853 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5854 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5855#ifdef CONFIG_X86_64
5856 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5857#endif
f8c16bba 5858 kvm_x86_ops = NULL;
56c6d28a 5859 kvm_mmu_module_exit();
013f6a5d 5860 free_percpu(shared_msrs);
56c6d28a 5861}
f8c16bba 5862
5cb56059 5863int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5864{
5865 ++vcpu->stat.halt_exits;
35754c98 5866 if (lapic_in_kernel(vcpu)) {
a4535290 5867 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5868 return 1;
5869 } else {
5870 vcpu->run->exit_reason = KVM_EXIT_HLT;
5871 return 0;
5872 }
5873}
5cb56059
JS		 5874EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5875
5876int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5877{
5878 kvm_x86_ops->skip_emulated_instruction(vcpu);
5879 return kvm_vcpu_halt(vcpu);
5880}
8776e519
HB		 5881EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5882
6aef266c
SV		 5883/*
5884 * kvm_pv_kick_cpu_op: Kick a vcpu.
5885 *
5886 * @apicid - apicid of vcpu to be kicked.
5887 */
5888static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5889{
24d2166b 5890 struct kvm_lapic_irq lapic_irq;
6aef266c 5891
24d2166b
R		 5892 lapic_irq.shorthand = 0;
5893 lapic_irq.dest_mode = 0;
5894 lapic_irq.dest_id = apicid;
93bbf0b8 5895 lapic_irq.msi_redir_hint = false;
6aef266c 5896
24d2166b 5897 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5898 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5899}
5900
d62caabb
AS		 5901void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5902{
5903 vcpu->arch.apicv_active = false;
5904 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5905}
5906
8776e519
HB		 5907int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5908{
5909 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5910 int op_64_bit, r = 1;
8776e519 5911
5cb56059
JS		 5912 kvm_x86_ops->skip_emulated_instruction(vcpu);
5913
55cd8e5a
GN		 5914 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5915 return kvm_hv_hypercall(vcpu);
5916
5fdbf976
MT		 5917 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5918 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5919 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5920 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5921 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5922
229456fc 5923 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5924
a449c7aa
NA		 5925 op_64_bit = is_64_bit_mode(vcpu);
5926 if (!op_64_bit) {
8776e519
HB		 5927 nr &= 0xFFFFFFFF;
5928 a0 &= 0xFFFFFFFF;
5929 a1 &= 0xFFFFFFFF;
5930 a2 &= 0xFFFFFFFF;
5931 a3 &= 0xFFFFFFFF;
5932 }
5933
07708c4a
JK		 5934 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5935 ret = -KVM_EPERM;
5936 goto out;
5937 }
5938
8776e519 5939 switch (nr) {
b93463aa
AK		 5940 case KVM_HC_VAPIC_POLL_IRQ:
5941 ret = 0;
5942 break;
6aef266c
SV		 5943 case KVM_HC_KICK_CPU:
5944 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5945 ret = 0;
5946 break;
8776e519
HB		 5947 default:
5948 ret = -KVM_ENOSYS;
5949 break;
5950 }
07708c4a 5951out:
a449c7aa
NA		 5952 if (!op_64_bit)
5953 ret = (u32)ret;
5fdbf976 5954 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5955 ++vcpu->stat.hypercalls;
2f333bcb 5956 return r;
8776e519
HB		 5957}
5958EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5959
b6785def 5960static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5961{
d6aa1000 5962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5963 char instruction[3];
5fdbf976 5964 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5965
8776e519 5966 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5967
9d74191a 5968 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5969}
5970
851ba692 5971static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5972{
782d422b
MG		 5973 return vcpu->run->request_interrupt_window &&
5974 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5975}
5976
851ba692 5977static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5978{
851ba692
AK		 5979 struct kvm_run *kvm_run = vcpu->run;
5980
91586a3b 5981 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5982 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5983 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5984 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 5985 kvm_run->ready_for_interrupt_injection =
5986 pic_in_kernel(vcpu->kvm) ||
782d422b 5987 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 5988}
5989
95ba8273
GN		 5990static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5991{
5992 int max_irr, tpr;
5993
5994 if (!kvm_x86_ops->update_cr8_intercept)
5995 return;
5996
88c808fd
AK		 5997 if (!vcpu->arch.apic)
5998 return;
5999
d62caabb
AS		 6000 if (vcpu->arch.apicv_active)
6001 return;
6002
8db3baa2
GN		 6003 if (!vcpu->arch.apic->vapic_addr)
6004 max_irr = kvm_lapic_find_highest_irr(vcpu);
6005 else
6006 max_irr = -1;
95ba8273
GN		 6007
6008 if (max_irr != -1)
6009 max_irr >>= 4;
6010
6011 tpr = kvm_lapic_get_cr8(vcpu);
6012
6013 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6014}
6015
b6b8a145 6016static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6017{
b6b8a145
JK		 6018 int r;
6019
95ba8273 6020 /* try to reinject previous events if any */
b59bb7bd 6021 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6022 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6023 vcpu->arch.exception.has_error_code,
6024 vcpu->arch.exception.error_code);
d6e8c854
NA		 6025
6026 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6027 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6028 X86_EFLAGS_RF);
6029
6bdf0662
NA		 6030 if (vcpu->arch.exception.nr == DB_VECTOR &&
6031 (vcpu->arch.dr7 & DR7_GD)) {
6032 vcpu->arch.dr7 &= ~DR7_GD;
6033 kvm_update_dr7(vcpu);
6034 }
6035
b59bb7bd
GN		 6036 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6037 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6038 vcpu->arch.exception.error_code,
6039 vcpu->arch.exception.reinject);
b6b8a145 6040 return 0;
b59bb7bd
GN		 6041 }
6042
95ba8273
GN		 6043 if (vcpu->arch.nmi_injected) {
6044 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6045 return 0;
95ba8273
GN		 6046 }
6047
6048 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6049 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6050 return 0;
6051 }
6052
6053 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6054 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6055 if (r != 0)
6056 return r;
95ba8273
GN		 6057 }
6058
6059 /* try to inject new event if pending */
6060 if (vcpu->arch.nmi_pending) {
6061 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6062 --vcpu->arch.nmi_pending;
95ba8273
GN		 6063 vcpu->arch.nmi_injected = true;
6064 kvm_x86_ops->set_nmi(vcpu);
6065 }
c7c9c56c 6066 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6067 /*
6068 * Because interrupts can be injected asynchronously, we are
6069 * calling check_nested_events again here to avoid a race condition.
6070 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6071 * proposal and current concerns. Perhaps we should be setting
6072 * KVM_REQ_EVENT only on certain events and not unconditionally?
6073 */
6074 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6075 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6076 if (r != 0)
6077 return r;
6078 }
95ba8273 6079 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6080 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6081 false);
6082 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6083 }
6084 }
b6b8a145 6085 return 0;
95ba8273
GN		 6086}
6087
7460fb4a
AK		 6088static void process_nmi(struct kvm_vcpu *vcpu)
6089{
6090 unsigned limit = 2;
6091
6092 /*
6093 * x86 is limited to one NMI running, and one NMI pending after it.
6094 * If an NMI is already in progress, limit further NMIs to just one.
6095 * Otherwise, allow two (and we'll inject the first one immediately).
6096 */
6097 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6098 limit = 1;
6099
6100 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6101 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6102 kvm_make_request(KVM_REQ_EVENT, vcpu);
6103}
6104
660a5d51
PB		 6105#define put_smstate(type, buf, offset, val) \
6106 *(type *)((buf) + (offset) - 0x7e00) = val
6107
6108static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6109{
6110 u32 flags = 0;
6111 flags |= seg->g << 23;
6112 flags |= seg->db << 22;
6113 flags |= seg->l << 21;
6114 flags |= seg->avl << 20;
6115 flags |= seg->present << 15;
6116 flags |= seg->dpl << 13;
6117 flags |= seg->s << 12;
6118 flags |= seg->type << 8;
6119 return flags;
6120}
6121
6122static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6123{
6124 struct kvm_segment seg;
6125 int offset;
6126
6127 kvm_get_segment(vcpu, &seg, n);
6128 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6129
6130 if (n < 3)
6131 offset = 0x7f84 + n * 12;
6132 else
6133 offset = 0x7f2c + (n - 3) * 12;
6134
6135 put_smstate(u32, buf, offset + 8, seg.base);
6136 put_smstate(u32, buf, offset + 4, seg.limit);
6137 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6138}
6139
efbb288a 6140#ifdef CONFIG_X86_64
660a5d51
PB		 6141static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6142{
6143 struct kvm_segment seg;
6144 int offset;
6145 u16 flags;
6146
6147 kvm_get_segment(vcpu, &seg, n);
6148 offset = 0x7e00 + n * 16;
6149
6150 flags = process_smi_get_segment_flags(&seg) >> 8;
6151 put_smstate(u16, buf, offset, seg.selector);
6152 put_smstate(u16, buf, offset + 2, flags);
6153 put_smstate(u32, buf, offset + 4, seg.limit);
6154 put_smstate(u64, buf, offset + 8, seg.base);
6155}
efbb288a 6156#endif
660a5d51
PB		 6157
6158static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6159{
6160 struct desc_ptr dt;
6161 struct kvm_segment seg;
6162 unsigned long val;
6163 int i;
6164
6165 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6166 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6167 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6168 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6169
6170 for (i = 0; i < 8; i++)
6171 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6172
6173 kvm_get_dr(vcpu, 6, &val);
6174 put_smstate(u32, buf, 0x7fcc, (u32)val);
6175 kvm_get_dr(vcpu, 7, &val);
6176 put_smstate(u32, buf, 0x7fc8, (u32)val);
6177
6178 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6179 put_smstate(u32, buf, 0x7fc4, seg.selector);
6180 put_smstate(u32, buf, 0x7f64, seg.base);
6181 put_smstate(u32, buf, 0x7f60, seg.limit);
6182 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6183
6184 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6185 put_smstate(u32, buf, 0x7fc0, seg.selector);
6186 put_smstate(u32, buf, 0x7f80, seg.base);
6187 put_smstate(u32, buf, 0x7f7c, seg.limit);
6188 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6189
6190 kvm_x86_ops->get_gdt(vcpu, &dt);
6191 put_smstate(u32, buf, 0x7f74, dt.address);
6192 put_smstate(u32, buf, 0x7f70, dt.size);
6193
6194 kvm_x86_ops->get_idt(vcpu, &dt);
6195 put_smstate(u32, buf, 0x7f58, dt.address);
6196 put_smstate(u32, buf, 0x7f54, dt.size);
6197
6198 for (i = 0; i < 6; i++)
6199 process_smi_save_seg_32(vcpu, buf, i);
6200
6201 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6202
6203 /* revision id */
6204 put_smstate(u32, buf, 0x7efc, 0x00020000);
6205 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6206}
6207
6208static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6209{
6210#ifdef CONFIG_X86_64
6211 struct desc_ptr dt;
6212 struct kvm_segment seg;
6213 unsigned long val;
6214 int i;
6215
6216 for (i = 0; i < 16; i++)
6217 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6218
6219 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6220 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6221
6222 kvm_get_dr(vcpu, 6, &val);
6223 put_smstate(u64, buf, 0x7f68, val);
6224 kvm_get_dr(vcpu, 7, &val);
6225 put_smstate(u64, buf, 0x7f60, val);
6226
6227 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6228 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6229 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6230
6231 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6232
6233 /* revision id */
6234 put_smstate(u32, buf, 0x7efc, 0x00020064);
6235
6236 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6237
6238 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6239 put_smstate(u16, buf, 0x7e90, seg.selector);
6240 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6241 put_smstate(u32, buf, 0x7e94, seg.limit);
6242 put_smstate(u64, buf, 0x7e98, seg.base);
6243
6244 kvm_x86_ops->get_idt(vcpu, &dt);
6245 put_smstate(u32, buf, 0x7e84, dt.size);
6246 put_smstate(u64, buf, 0x7e88, dt.address);
6247
6248 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6249 put_smstate(u16, buf, 0x7e70, seg.selector);
6250 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6251 put_smstate(u32, buf, 0x7e74, seg.limit);
6252 put_smstate(u64, buf, 0x7e78, seg.base);
6253
6254 kvm_x86_ops->get_gdt(vcpu, &dt);
6255 put_smstate(u32, buf, 0x7e64, dt.size);
6256 put_smstate(u64, buf, 0x7e68, dt.address);
6257
6258 for (i = 0; i < 6; i++)
6259 process_smi_save_seg_64(vcpu, buf, i);
6260#else
6261 WARN_ON_ONCE(1);
6262#endif
6263}
6264
64d60670
PB		 6265static void process_smi(struct kvm_vcpu *vcpu)
6266{
660a5d51 6267 struct kvm_segment cs, ds;
18c3626e 6268 struct desc_ptr dt;
660a5d51
PB		 6269 char buf[512];
6270 u32 cr0;
6271
64d60670
PB		 6272 if (is_smm(vcpu)) {
6273 vcpu->arch.smi_pending = true;
6274 return;
6275 }
6276
660a5d51
PB		 6277 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6278 vcpu->arch.hflags |= HF_SMM_MASK;
6279 memset(buf, 0, 512);
6280 if (guest_cpuid_has_longmode(vcpu))
6281 process_smi_save_state_64(vcpu, buf);
6282 else
6283 process_smi_save_state_32(vcpu, buf);
6284
54bf36aa 6285 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6286
6287 if (kvm_x86_ops->get_nmi_mask(vcpu))
6288 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6289 else
6290 kvm_x86_ops->set_nmi_mask(vcpu, true);
6291
6292 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6293 kvm_rip_write(vcpu, 0x8000);
6294
6295 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6296 kvm_x86_ops->set_cr0(vcpu, cr0);
6297 vcpu->arch.cr0 = cr0;
6298
6299 kvm_x86_ops->set_cr4(vcpu, 0);
6300
18c3626e
PB		 6301 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6302 dt.address = dt.size = 0;
6303 kvm_x86_ops->set_idt(vcpu, &dt);
6304
660a5d51
PB		 6305 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6306
6307 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6308 cs.base = vcpu->arch.smbase;
6309
6310 ds.selector = 0;
6311 ds.base = 0;
6312
6313 cs.limit = ds.limit = 0xffffffff;
6314 cs.type = ds.type = 0x3;
6315 cs.dpl = ds.dpl = 0;
6316 cs.db = ds.db = 0;
6317 cs.s = ds.s = 1;
6318 cs.l = ds.l = 0;
6319 cs.g = ds.g = 1;
6320 cs.avl = ds.avl = 0;
6321 cs.present = ds.present = 1;
6322 cs.unusable = ds.unusable = 0;
6323 cs.padding = ds.padding = 0;
6324
6325 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6326 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6327 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6328 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6329 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6330 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6331
6332 if (guest_cpuid_has_longmode(vcpu))
6333 kvm_x86_ops->set_efer(vcpu, 0);
6334
6335 kvm_update_cpuid(vcpu);
6336 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6337}
6338
3d81bc7e 6339static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6340{
5c919412
AS		 6341 u64 eoi_exit_bitmap[4];
6342
3d81bc7e
YZ		 6343 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6344 return;
c7c9c56c 6345
6308630b 6346 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6347
b053b2ae 6348 if (irqchip_split(vcpu->kvm))
6308630b 6349 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6350 else {
d62caabb
AS		 6351 if (vcpu->arch.apicv_active)
6352 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6353 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6354 }
5c919412
AS		 6355 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6356 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6357 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6358}
6359
a70656b6
RK		 6360static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6361{
6362 ++vcpu->stat.tlb_flush;
6363 kvm_x86_ops->tlb_flush(vcpu);
6364}
6365
4256f43f
TC		 6366void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6367{
c24ae0dc
TC		 6368 struct page *page = NULL;
6369
35754c98 6370 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6371 return;
6372
4256f43f
TC		 6373 if (!kvm_x86_ops->set_apic_access_page_addr)
6374 return;
6375
c24ae0dc 6376 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6377 if (is_error_page(page))
6378 return;
c24ae0dc
TC		 6379 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6380
6381 /*
6382 * Do not pin apic access page in memory, the MMU notifier
6383 * will call us again if it is migrated or swapped out.
6384 */
6385 put_page(page);
4256f43f
TC		 6386}
6387EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6388
fe71557a
TC		 6389void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6390 unsigned long address)
6391{
c24ae0dc
TC		 6392 /*
6393 * The physical address of apic access page is stored in the VMCS.
6394 * Update it when it becomes invalid.
6395 */
6396 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6397 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6398}
6399
9357d939 6400/*
362c698f 6401 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6402 * exiting to the userspace. Otherwise, the value will be returned to the
6403 * userspace.
6404 */
851ba692 6405static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6406{
6407 int r;
62a193ed
MG		 6408 bool req_int_win =
6409 dm_request_for_irq_injection(vcpu) &&
6410 kvm_cpu_accept_dm_intr(vcpu);
6411
730dca42 6412 bool req_immediate_exit = false;
b6c7a5dc 6413
3e007509 6414 if (vcpu->requests) {
a8eeb04a 6415 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6416 kvm_mmu_unload(vcpu);
a8eeb04a 6417 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6418 __kvm_migrate_timers(vcpu);
d828199e
MT		 6419 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6420 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6421 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6422 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6423 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6424 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6425 if (unlikely(r))
6426 goto out;
6427 }
a8eeb04a 6428 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6429 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6430 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6431 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6432 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6433 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6434 r = 0;
6435 goto out;
6436 }
a8eeb04a 6437 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6438 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6439 r = 0;
6440 goto out;
6441 }
a8eeb04a 6442 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6443 vcpu->fpu_active = 0;
6444 kvm_x86_ops->fpu_deactivate(vcpu);
6445 }
af585b92
GN		 6446 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6447 /* Page is swapped out. Do synthetic halt */
6448 vcpu->arch.apf.halted = true;
6449 r = 1;
6450 goto out;
6451 }
c9aaa895
GC		 6452 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6453 record_steal_time(vcpu);
64d60670
PB		 6454 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6455 process_smi(vcpu);
7460fb4a
AK		 6456 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6457 process_nmi(vcpu);
f5132b01 6458 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6459 kvm_pmu_handle_event(vcpu);
f5132b01 6460 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6461 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6462 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6463 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6464 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6465 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6466 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6467 vcpu->run->eoi.vector =
6468 vcpu->arch.pending_ioapic_eoi;
6469 r = 0;
6470 goto out;
6471 }
6472 }
3d81bc7e
YZ		 6473 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6474 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6475 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6476 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6477 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6478 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6479 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6480 r = 0;
6481 goto out;
6482 }
e516cebb
AS		 6483 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6484 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6485 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6486 r = 0;
6487 goto out;
6488 }
db397571
AS		 6489 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6490 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6491 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6492 r = 0;
6493 goto out;
6494 }
1f4b34f8
AS		 6495 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6496 kvm_hv_process_stimers(vcpu);
2f52d58c 6497 }
b93463aa 6498
bf9f6ac8
FW		 6499 /*
6500 * KVM_REQ_EVENT is not set when posted interrupts are set by
6501 * VT-d hardware, so we have to update RVI unconditionally.
6502 */
6503 if (kvm_lapic_enabled(vcpu)) {
6504 /*
6505 * Update architecture specific hints for APIC
6506 * virtual interrupt delivery.
6507 */
d62caabb 6508 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6509 kvm_x86_ops->hwapic_irr_update(vcpu,
6510 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6511 }
b93463aa 6512
b463a6f7 6513 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6514 kvm_apic_accept_events(vcpu);
6515 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6516 r = 1;
6517 goto out;
6518 }
6519
b6b8a145
JK		 6520 if (inject_pending_event(vcpu, req_int_win) != 0)
6521 req_immediate_exit = true;
b463a6f7 6522 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6523 else if (vcpu->arch.nmi_pending)
c9a7953f 6524 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6525 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6526 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6527
6528 if (kvm_lapic_enabled(vcpu)) {
6529 update_cr8_intercept(vcpu);
6530 kvm_lapic_sync_to_vapic(vcpu);
6531 }
6532 }
6533
d8368af8
AK		 6534 r = kvm_mmu_reload(vcpu);
6535 if (unlikely(r)) {
d905c069 6536 goto cancel_injection;
d8368af8
AK		 6537 }
6538
b6c7a5dc
HB		 6539 preempt_disable();
6540
6541 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6542 if (vcpu->fpu_active)
6543 kvm_load_guest_fpu(vcpu);
2acf923e 6544 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6545
6b7e2d09
XG		 6546 vcpu->mode = IN_GUEST_MODE;
6547
01b71917
MT		 6548 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6549
6b7e2d09
XG		 6550 /* We should set ->mode before check ->requests,
6551 * see the comment in make_all_cpus_request.
6552 */
01b71917 6553 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6554
d94e1dc9 6555 local_irq_disable();
32f88400 6556
6b7e2d09 6557 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6558 || need_resched() || signal_pending(current)) {
6b7e2d09 6559 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6560 smp_wmb();
6c142801
AK		 6561 local_irq_enable();
6562 preempt_enable();
01b71917 6563 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6564 r = 1;
d905c069 6565 goto cancel_injection;
6c142801
AK		 6566 }
6567
d6185f20
NHE		 6568 if (req_immediate_exit)
6569 smp_send_reschedule(vcpu->cpu);
6570
ccf73aaf 6571 __kvm_guest_enter();
b6c7a5dc 6572
42dbaa5a 6573 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6574 set_debugreg(0, 7);
6575 set_debugreg(vcpu->arch.eff_db[0], 0);
6576 set_debugreg(vcpu->arch.eff_db[1], 1);
6577 set_debugreg(vcpu->arch.eff_db[2], 2);
6578 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6579 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6580 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6581 }
b6c7a5dc 6582
229456fc 6583 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6584 wait_lapic_expire(vcpu);
851ba692 6585 kvm_x86_ops->run(vcpu);
b6c7a5dc 6586
c77fb5fe
PB		 6587 /*
6588 * Do this here before restoring debug registers on the host. And
6589 * since we do this before handling the vmexit, a DR access vmexit
6590 * can (a) read the correct value of the debug registers, (b) set
6591 * KVM_DEBUGREG_WONT_EXIT again.
6592 */
6593 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6594 int i;
6595
6596 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6597 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6598 for (i = 0; i < KVM_NR_DB_REGS; i++)
6599 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6600 }
6601
24f1e32c
FW		 6602 /*
6603 * If the guest has used debug registers, at least dr7
6604 * will be disabled while returning to the host.
6605 * If we don't have active breakpoints in the host, we don't
6606 * care about the messed up debug address registers. But if
6607 * we have some of them active, restore the old state.
6608 */
59d8eb53 6609 if (hw_breakpoint_active())
24f1e32c 6610 hw_breakpoint_restore();
42dbaa5a 6611
4ba76538 6612 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6613
6b7e2d09 6614 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6615 smp_wmb();
a547c6db
YZ		 6616
6617 /* Interrupt is enabled by handle_external_intr() */
6618 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6619
6620 ++vcpu->stat.exits;
6621
6622 /*
6623 * We must have an instruction between local_irq_enable() and
6624 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6625 * the interrupt shadow. The stat.exits increment will do nicely.
6626 * But we need to prevent reordering, hence this barrier():
6627 */
6628 barrier();
6629
6630 kvm_guest_exit();
6631
6632 preempt_enable();
6633
f656ce01 6634 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6635
b6c7a5dc
HB		 6636 /*
6637 * Profile KVM exit RIPs:
6638 */
6639 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6640 unsigned long rip = kvm_rip_read(vcpu);
6641 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6642 }
6643
cc578287
ZA		 6644 if (unlikely(vcpu->arch.tsc_always_catchup))
6645 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6646
5cfb1d5a
MT		 6647 if (vcpu->arch.apic_attention)
6648 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6649
851ba692 6650 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6651 return r;
6652
6653cancel_injection:
6654 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6655 if (unlikely(vcpu->arch.apic_attention))
6656 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6657out:
6658 return r;
6659}
b6c7a5dc 6660
362c698f
PB		 6661static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6662{
bf9f6ac8
FW		 6663 if (!kvm_arch_vcpu_runnable(vcpu) &&
6664 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6665 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6666 kvm_vcpu_block(vcpu);
6667 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6668
6669 if (kvm_x86_ops->post_block)
6670 kvm_x86_ops->post_block(vcpu);
6671
9c8fd1ba
PB		 6672 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6673 return 1;
6674 }
362c698f
PB		 6675
6676 kvm_apic_accept_events(vcpu);
6677 switch(vcpu->arch.mp_state) {
6678 case KVM_MP_STATE_HALTED:
6679 vcpu->arch.pv.pv_unhalted = false;
6680 vcpu->arch.mp_state =
6681 KVM_MP_STATE_RUNNABLE;
6682 case KVM_MP_STATE_RUNNABLE:
6683 vcpu->arch.apf.halted = false;
6684 break;
6685 case KVM_MP_STATE_INIT_RECEIVED:
6686 break;
6687 default:
6688 return -EINTR;
6689 break;
6690 }
6691 return 1;
6692}
09cec754 6693
5d9bc648
PB		 6694static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6695{
6696 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6697 !vcpu->arch.apf.halted);
6698}
6699
362c698f 6700static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6701{
6702 int r;
f656ce01 6703 struct kvm *kvm = vcpu->kvm;
d7690175 6704
f656ce01 6705 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6706
362c698f 6707 for (;;) {
58f800d5 6708 if (kvm_vcpu_running(vcpu)) {
851ba692 6709 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6710 } else {
362c698f 6711 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6712 }
6713
09cec754
GN		 6714 if (r <= 0)
6715 break;
6716
6717 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6718 if (kvm_cpu_has_pending_timer(vcpu))
6719 kvm_inject_pending_timer_irqs(vcpu);
6720
782d422b
MG		 6721 if (dm_request_for_irq_injection(vcpu) &&
6722 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6723 r = 0;
6724 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6725 ++vcpu->stat.request_irq_exits;
362c698f 6726 break;
09cec754 6727 }
af585b92
GN		 6728
6729 kvm_check_async_pf_completion(vcpu);
6730
09cec754
GN		 6731 if (signal_pending(current)) {
6732 r = -EINTR;
851ba692 6733 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6734 ++vcpu->stat.signal_exits;
362c698f 6735 break;
09cec754
GN		 6736 }
6737 if (need_resched()) {
f656ce01 6738 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6739 cond_resched();
f656ce01 6740 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6741 }
b6c7a5dc
HB		 6742 }
6743
f656ce01 6744 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6745
6746 return r;
6747}
6748
716d51ab
GN		 6749static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6750{
6751 int r;
6752 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6753 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6754 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6755 if (r != EMULATE_DONE)
6756 return 0;
6757 return 1;
6758}
6759
6760static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6761{
6762 BUG_ON(!vcpu->arch.pio.count);
6763
6764 return complete_emulated_io(vcpu);
6765}
6766
f78146b0
AK		 6767/*
6768 * Implements the following, as a state machine:
6769 *
6770 * read:
6771 * for each fragment
87da7e66
XG		 6772 * for each mmio piece in the fragment
6773 * write gpa, len
6774 * exit
6775 * copy data
f78146b0
AK		 6776 * execute insn
6777 *
6778 * write:
6779 * for each fragment
87da7e66
XG		 6780 * for each mmio piece in the fragment
6781 * write gpa, len
6782 * copy data
6783 * exit
f78146b0 6784 */
716d51ab 6785static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6786{
6787 struct kvm_run *run = vcpu->run;
f78146b0 6788 struct kvm_mmio_fragment *frag;
87da7e66 6789 unsigned len;
5287f194 6790
716d51ab 6791 BUG_ON(!vcpu->mmio_needed);
5287f194 6792
716d51ab 6793 /* Complete previous fragment */
87da7e66
XG		 6794 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6795 len = min(8u, frag->len);
716d51ab 6796 if (!vcpu->mmio_is_write)
87da7e66
XG		 6797 memcpy(frag->data, run->mmio.data, len);
6798
6799 if (frag->len <= 8) {
6800 /* Switch to the next fragment. */
6801 frag++;
6802 vcpu->mmio_cur_fragment++;
6803 } else {
6804 /* Go forward to the next mmio piece. */
6805 frag->data += len;
6806 frag->gpa += len;
6807 frag->len -= len;
6808 }
6809
a08d3b3b 6810 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6811 vcpu->mmio_needed = 0;
0912c977
PB		 6812
6813 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6814 if (vcpu->mmio_is_write)
716d51ab
GN		 6815 return 1;
6816 vcpu->mmio_read_completed = 1;
6817 return complete_emulated_io(vcpu);
6818 }
87da7e66 6819
716d51ab
GN		 6820 run->exit_reason = KVM_EXIT_MMIO;
6821 run->mmio.phys_addr = frag->gpa;
6822 if (vcpu->mmio_is_write)
87da7e66
XG		 6823 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6824 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6825 run->mmio.is_write = vcpu->mmio_is_write;
6826 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6827 return 0;
5287f194
AK		 6828}
6829
716d51ab 6830
b6c7a5dc
HB		 6831int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6832{
c5bedc68 6833 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6834 int r;
6835 sigset_t sigsaved;
6836
c4d72e2d 6837 fpu__activate_curr(fpu);
e5c30142 6838
ac9f6dc0
AK		 6839 if (vcpu->sigset_active)
6840 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6841
a4535290 6842 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6843 kvm_vcpu_block(vcpu);
66450a21 6844 kvm_apic_accept_events(vcpu);
d7690175 6845 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6846 r = -EAGAIN;
6847 goto out;
b6c7a5dc
HB		 6848 }
6849
b6c7a5dc 6850 /* re-sync apic's tpr */
35754c98 6851 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6852 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6853 r = -EINVAL;
6854 goto out;
6855 }
6856 }
b6c7a5dc 6857
716d51ab
GN		 6858 if (unlikely(vcpu->arch.complete_userspace_io)) {
6859 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6860 vcpu->arch.complete_userspace_io = NULL;
6861 r = cui(vcpu);
6862 if (r <= 0)
6863 goto out;
6864 } else
6865 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6866
362c698f 6867 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6868
6869out:
f1d86e46 6870 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6871 if (vcpu->sigset_active)
6872 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6873
b6c7a5dc
HB		 6874 return r;
6875}
6876
6877int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6878{
7ae441ea
GN		 6879 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6880 /*
6881 * We are here if userspace calls get_regs() in the middle of
6882 * instruction emulation. Registers state needs to be copied
4a969980 6883 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6884 * that usually, but some bad designed PV devices (vmware
6885 * backdoor interface) need this to work
6886 */
dd856efa 6887 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6888 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6889 }
5fdbf976
MT		 6890 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6891 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6892 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6893 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6894 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6895 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6896 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6897 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6898#ifdef CONFIG_X86_64
5fdbf976
MT		 6899 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6900 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6901 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6902 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6903 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6904 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6905 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6906 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6907#endif
6908
5fdbf976 6909 regs->rip = kvm_rip_read(vcpu);
91586a3b 6910 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6911
b6c7a5dc
HB		 6912 return 0;
6913}
6914
6915int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6916{
7ae441ea
GN		 6917 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6918 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6919
5fdbf976
MT		 6920 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6921 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6922 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6923 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6924 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6925 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6926 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6927 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6928#ifdef CONFIG_X86_64
5fdbf976
MT		 6929 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6930 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6931 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6932 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6933 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6934 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6935 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6936 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6937#endif
6938
5fdbf976 6939 kvm_rip_write(vcpu, regs->rip);
91586a3b 6940 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6941
b4f14abd
JK		 6942 vcpu->arch.exception.pending = false;
6943
3842d135
AK		 6944 kvm_make_request(KVM_REQ_EVENT, vcpu);
6945
b6c7a5dc
HB		 6946 return 0;
6947}
6948
b6c7a5dc
HB		 6949void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6950{
6951 struct kvm_segment cs;
6952
3e6e0aab 6953 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6954 *db = cs.db;
6955 *l = cs.l;
6956}
6957EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6958
6959int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6960 struct kvm_sregs *sregs)
6961{
89a27f4d 6962 struct desc_ptr dt;
b6c7a5dc 6963
3e6e0aab
GT		 6964 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6965 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6966 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6967 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6968 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6969 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6970
3e6e0aab
GT		 6971 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6972 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6973
6974 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6975 sregs->idt.limit = dt.size;
6976 sregs->idt.base = dt.address;
b6c7a5dc 6977 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6978 sregs->gdt.limit = dt.size;
6979 sregs->gdt.base = dt.address;
b6c7a5dc 6980
4d4ec087 6981 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6982 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6983 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6984 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6985 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6986 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6987 sregs->apic_base = kvm_get_apic_base(vcpu);
6988
923c61bb 6989 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6990
36752c9b 6991 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6992 set_bit(vcpu->arch.interrupt.nr,
6993 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6994
b6c7a5dc
HB		 6995 return 0;
6996}
6997
62d9f0db
MT		 6998int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6999 struct kvm_mp_state *mp_state)
7000{
66450a21 7001 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7002 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7003 vcpu->arch.pv.pv_unhalted)
7004 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7005 else
7006 mp_state->mp_state = vcpu->arch.mp_state;
7007
62d9f0db
MT		 7008 return 0;
7009}
7010
7011int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7012 struct kvm_mp_state *mp_state)
7013{
66450a21
JK		 7014 if (!kvm_vcpu_has_lapic(vcpu) &&
7015 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7016 return -EINVAL;
7017
7018 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7019 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7020 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7021 } else
7022 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7023 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7024 return 0;
7025}
7026
7f3d35fd
KW		 7027int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7028 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7029{
9d74191a 7030 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7031 int ret;
e01c2426 7032
8ec4722d 7033 init_emulate_ctxt(vcpu);
c697518a 7034
7f3d35fd 7035 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7036 has_error_code, error_code);
c697518a 7037
c697518a 7038 if (ret)
19d04437 7039 return EMULATE_FAIL;
37817f29 7040
9d74191a
TY		 7041 kvm_rip_write(vcpu, ctxt->eip);
7042 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7043 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7044 return EMULATE_DONE;
37817f29
IE		 7045}
7046EXPORT_SYMBOL_GPL(kvm_task_switch);
7047
b6c7a5dc
HB		 7048int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7049 struct kvm_sregs *sregs)
7050{
58cb628d 7051 struct msr_data apic_base_msr;
b6c7a5dc 7052 int mmu_reset_needed = 0;
63f42e02 7053 int pending_vec, max_bits, idx;
89a27f4d 7054 struct desc_ptr dt;
b6c7a5dc 7055
6d1068b3
PM		 7056 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7057 return -EINVAL;
7058
89a27f4d
GN		 7059 dt.size = sregs->idt.limit;
7060 dt.address = sregs->idt.base;
b6c7a5dc 7061 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7062 dt.size = sregs->gdt.limit;
7063 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7064 kvm_x86_ops->set_gdt(vcpu, &dt);
7065
ad312c7c 7066 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7067 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7068 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7069 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7070
2d3ad1f4 7071 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7072
f6801dff 7073 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7074 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7075 apic_base_msr.data = sregs->apic_base;
7076 apic_base_msr.host_initiated = true;
7077 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7078
4d4ec087 7079 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7080 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7081 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7082
fc78f519 7083 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7084 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7085 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7086 kvm_update_cpuid(vcpu);
63f42e02
XG		 7087
7088 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7089 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7090 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7091 mmu_reset_needed = 1;
7092 }
63f42e02 7093 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7094
7095 if (mmu_reset_needed)
7096 kvm_mmu_reset_context(vcpu);
7097
a50abc3b 7098 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7099 pending_vec = find_first_bit(
7100 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7101 if (pending_vec < max_bits) {
66fd3f7f 7102 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7103 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7104 }
7105
3e6e0aab
GT		 7106 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7107 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7108 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7109 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7110 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7111 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7112
3e6e0aab
GT		 7113 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7114 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7115
5f0269f5
ME		 7116 update_cr8_intercept(vcpu);
7117
9c3e4aab 7118 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7119 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7120 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7121 !is_protmode(vcpu))
9c3e4aab
MT		 7122 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7123
3842d135
AK		 7124 kvm_make_request(KVM_REQ_EVENT, vcpu);
7125
b6c7a5dc
HB		 7126 return 0;
7127}
7128
d0bfb940
JK		 7129int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7130 struct kvm_guest_debug *dbg)
b6c7a5dc 7131{
355be0b9 7132 unsigned long rflags;
ae675ef0 7133 int i, r;
b6c7a5dc 7134
4f926bf2
JK		 7135 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7136 r = -EBUSY;
7137 if (vcpu->arch.exception.pending)
2122ff5e 7138 goto out;
4f926bf2
JK		 7139 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7140 kvm_queue_exception(vcpu, DB_VECTOR);
7141 else
7142 kvm_queue_exception(vcpu, BP_VECTOR);
7143 }
7144
91586a3b
JK		 7145 /*
7146 * Read rflags as long as potentially injected trace flags are still
7147 * filtered out.
7148 */
7149 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7150
7151 vcpu->guest_debug = dbg->control;
7152 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7153 vcpu->guest_debug = 0;
7154
7155 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7156 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7157 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7158 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7159 } else {
7160 for (i = 0; i < KVM_NR_DB_REGS; i++)
7161 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7162 }
c8639010 7163 kvm_update_dr7(vcpu);
ae675ef0 7164
f92653ee
JK		 7165 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7166 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7167 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7168
91586a3b
JK		 7169 /*
7170 * Trigger an rflags update that will inject or remove the trace
7171 * flags.
7172 */
7173 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7174
a96036b8 7175 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7176
4f926bf2 7177 r = 0;
d0bfb940 7178
2122ff5e 7179out:
b6c7a5dc
HB		 7180
7181 return r;
7182}
7183
8b006791
ZX		 7184/*
7185 * Translate a guest virtual address to a guest physical address.
7186 */
7187int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7188 struct kvm_translation *tr)
7189{
7190 unsigned long vaddr = tr->linear_address;
7191 gpa_t gpa;
f656ce01 7192 int idx;
8b006791 7193
f656ce01 7194 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7195 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7196 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7197 tr->physical_address = gpa;
7198 tr->valid = gpa != UNMAPPED_GVA;
7199 tr->writeable = 1;
7200 tr->usermode = 0;
8b006791
ZX		 7201
7202 return 0;
7203}
7204
d0752060
HB		 7205int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7206{
c47ada30 7207 struct fxregs_state *fxsave =
7366ed77 7208 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7209
d0752060
HB		 7210 memcpy(fpu->fpr, fxsave->st_space, 128);
7211 fpu->fcw = fxsave->cwd;
7212 fpu->fsw = fxsave->swd;
7213 fpu->ftwx = fxsave->twd;
7214 fpu->last_opcode = fxsave->fop;
7215 fpu->last_ip = fxsave->rip;
7216 fpu->last_dp = fxsave->rdp;
7217 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7218
d0752060
HB		 7219 return 0;
7220}
7221
7222int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7223{
c47ada30 7224 struct fxregs_state *fxsave =
7366ed77 7225 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7226
d0752060
HB		 7227 memcpy(fxsave->st_space, fpu->fpr, 128);
7228 fxsave->cwd = fpu->fcw;
7229 fxsave->swd = fpu->fsw;
7230 fxsave->twd = fpu->ftwx;
7231 fxsave->fop = fpu->last_opcode;
7232 fxsave->rip = fpu->last_ip;
7233 fxsave->rdp = fpu->last_dp;
7234 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7235
d0752060
HB		 7236 return 0;
7237}
7238
0ee6a517 7239static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7240{
bf935b0b 7241 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7242 if (cpu_has_xsaves)
7366ed77 7243 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7244 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7245
2acf923e
DC		 7246 /*
7247 * Ensure guest xcr0 is valid for loading
7248 */
d91cab78 7249 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7250
ad312c7c 7251 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7252}
d0752060
HB		 7253
7254void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7255{
2608d7a1 7256 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7257 return;
7258
2acf923e
DC		 7259 /*
7260 * Restore all possible states in the guest,
7261 * and assume host would use all available bits.
7262 * Guest xcr0 would be loaded later.
7263 */
7264 kvm_put_guest_xcr0(vcpu);
d0752060 7265 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7266 __kernel_fpu_begin();
003e2e8b 7267 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7268 trace_kvm_fpu(1);
d0752060 7269}
d0752060
HB		 7270
7271void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7272{
2acf923e
DC		 7273 kvm_put_guest_xcr0(vcpu);
7274
653f52c3
RR		 7275 if (!vcpu->guest_fpu_loaded) {
7276 vcpu->fpu_counter = 0;
d0752060 7277 return;
653f52c3 7278 }
d0752060
HB		 7279
7280 vcpu->guest_fpu_loaded = 0;
4f836347 7281 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7282 __kernel_fpu_end();
f096ed85 7283 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7284 /*
7285 * If using eager FPU mode, or if the guest is a frequent user
7286 * of the FPU, just leave the FPU active for next time.
7287 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7288 * the FPU in bursts will revert to loading it on demand.
7289 */
a9b4fb7e 7290 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7291 if (++vcpu->fpu_counter < 5)
7292 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7293 }
0c04851c 7294 trace_kvm_fpu(0);
d0752060 7295}
e9b11c17
ZX		 7296
7297void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7298{
12f9a48f 7299 kvmclock_reset(vcpu);
7f1ea208 7300
f5f48ee1 7301 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7302 kvm_x86_ops->vcpu_free(vcpu);
7303}
7304
7305struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7306 unsigned int id)
7307{
c447e76b
LL		 7308 struct kvm_vcpu *vcpu;
7309
6755bae8
ZA		 7310 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7311 printk_once(KERN_WARNING
7312 "kvm: SMP vm created on host with unstable TSC; "
7313 "guest TSC will not be reliable\n");
c447e76b
LL		 7314
7315 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7316
c447e76b 7317 return vcpu;
26e5215f 7318}
e9b11c17 7319
26e5215f
AK		 7320int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7321{
7322 int r;
e9b11c17 7323
19efffa2 7324 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7325 r = vcpu_load(vcpu);
7326 if (r)
7327 return r;
d28bc9dd 7328 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7329 kvm_mmu_setup(vcpu);
e9b11c17 7330 vcpu_put(vcpu);
26e5215f 7331 return r;
e9b11c17
ZX		 7332}
7333
31928aa5 7334void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7335{
8fe8ab46 7336 struct msr_data msr;
332967a3 7337 struct kvm *kvm = vcpu->kvm;
42897d86 7338
31928aa5
DD		 7339 if (vcpu_load(vcpu))
7340 return;
8fe8ab46
WA		 7341 msr.data = 0x0;
7342 msr.index = MSR_IA32_TSC;
7343 msr.host_initiated = true;
7344 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7345 vcpu_put(vcpu);
7346
630994b3
MT		 7347 if (!kvmclock_periodic_sync)
7348 return;
7349
332967a3
AJ		 7350 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7351 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7352}
7353
d40ccc62 7354void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7355{
9fc77441 7356 int r;
344d9588
GN		 7357 vcpu->arch.apf.msr_val = 0;
7358
9fc77441
MT		 7359 r = vcpu_load(vcpu);
7360 BUG_ON(r);
e9b11c17
ZX		 7361 kvm_mmu_unload(vcpu);
7362 vcpu_put(vcpu);
7363
7364 kvm_x86_ops->vcpu_free(vcpu);
7365}
7366
d28bc9dd 7367void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7368{
e69fab5d
PB		 7369 vcpu->arch.hflags = 0;
7370
7460fb4a
AK		 7371 atomic_set(&vcpu->arch.nmi_queued, 0);
7372 vcpu->arch.nmi_pending = 0;
448fa4a9 7373 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7374 kvm_clear_interrupt_queue(vcpu);
7375 kvm_clear_exception_queue(vcpu);
448fa4a9 7376
42dbaa5a 7377 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7378 kvm_update_dr0123(vcpu);
6f43ed01 7379 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7380 kvm_update_dr6(vcpu);
42dbaa5a 7381 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7382 kvm_update_dr7(vcpu);
42dbaa5a 7383
1119022c
NA		 7384 vcpu->arch.cr2 = 0;
7385
3842d135 7386 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7387 vcpu->arch.apf.msr_val = 0;
c9aaa895 7388 vcpu->arch.st.msr_val = 0;
3842d135 7389
12f9a48f
GC		 7390 kvmclock_reset(vcpu);
7391
af585b92
GN		 7392 kvm_clear_async_pf_completion_queue(vcpu);
7393 kvm_async_pf_hash_reset(vcpu);
7394 vcpu->arch.apf.halted = false;
3842d135 7395
64d60670 7396 if (!init_event) {
d28bc9dd 7397 kvm_pmu_reset(vcpu);
64d60670
PB		 7398 vcpu->arch.smbase = 0x30000;
7399 }
f5132b01 7400
66f7b72e
JS		 7401 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7402 vcpu->arch.regs_avail = ~0;
7403 vcpu->arch.regs_dirty = ~0;
7404
d28bc9dd 7405 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7406}
7407
2b4a273b 7408void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7409{
7410 struct kvm_segment cs;
7411
7412 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7413 cs.selector = vector << 8;
7414 cs.base = vector << 12;
7415 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7416 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7417}
7418
13a34e06 7419int kvm_arch_hardware_enable(void)
e9b11c17 7420{
ca84d1a2
ZA		 7421 struct kvm *kvm;
7422 struct kvm_vcpu *vcpu;
7423 int i;
0dd6a6ed
ZA		 7424 int ret;
7425 u64 local_tsc;
7426 u64 max_tsc = 0;
7427 bool stable, backwards_tsc = false;
18863bdd
AK		 7428
7429 kvm_shared_msr_cpu_online();
13a34e06 7430 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7431 if (ret != 0)
7432 return ret;
7433
4ea1636b 7434 local_tsc = rdtsc();
0dd6a6ed
ZA		 7435 stable = !check_tsc_unstable();
7436 list_for_each_entry(kvm, &vm_list, vm_list) {
7437 kvm_for_each_vcpu(i, vcpu, kvm) {
7438 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7439 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7440 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7441 backwards_tsc = true;
7442 if (vcpu->arch.last_host_tsc > max_tsc)
7443 max_tsc = vcpu->arch.last_host_tsc;
7444 }
7445 }
7446 }
7447
7448 /*
7449 * Sometimes, even reliable TSCs go backwards. This happens on
7450 * platforms that reset TSC during suspend or hibernate actions, but
7451 * maintain synchronization. We must compensate. Fortunately, we can
7452 * detect that condition here, which happens early in CPU bringup,
7453 * before any KVM threads can be running. Unfortunately, we can't
7454 * bring the TSCs fully up to date with real time, as we aren't yet far
7455 * enough into CPU bringup that we know how much real time has actually
7456 * elapsed; our helper function, get_kernel_ns() will be using boot
7457 * variables that haven't been updated yet.
7458 *
7459 * So we simply find the maximum observed TSC above, then record the
7460 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7461 * the adjustment will be applied. Note that we accumulate
7462 * adjustments, in case multiple suspend cycles happen before some VCPU
7463 * gets a chance to run again. In the event that no KVM threads get a
7464 * chance to run, we will miss the entire elapsed period, as we'll have
7465 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7466 * loose cycle time. This isn't too big a deal, since the loss will be
7467 * uniform across all VCPUs (not to mention the scenario is extremely
7468 * unlikely). It is possible that a second hibernate recovery happens
7469 * much faster than a first, causing the observed TSC here to be
7470 * smaller; this would require additional padding adjustment, which is
7471 * why we set last_host_tsc to the local tsc observed here.
7472 *
7473 * N.B. - this code below runs only on platforms with reliable TSC,
7474 * as that is the only way backwards_tsc is set above. Also note
7475 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7476 * have the same delta_cyc adjustment applied if backwards_tsc
7477 * is detected. Note further, this adjustment is only done once,
7478 * as we reset last_host_tsc on all VCPUs to stop this from being
7479 * called multiple times (one for each physical CPU bringup).
7480 *
4a969980 7481 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7482 * will be compensated by the logic in vcpu_load, which sets the TSC to
7483 * catchup mode. This will catchup all VCPUs to real time, but cannot
7484 * guarantee that they stay in perfect synchronization.
7485 */
7486 if (backwards_tsc) {
7487 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7488 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7489 list_for_each_entry(kvm, &vm_list, vm_list) {
7490 kvm_for_each_vcpu(i, vcpu, kvm) {
7491 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7492 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7493 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7494 }
7495
7496 /*
7497 * We have to disable TSC offset matching.. if you were
7498 * booting a VM while issuing an S4 host suspend....
7499 * you may have some problem. Solving this issue is
7500 * left as an exercise to the reader.
7501 */
7502 kvm->arch.last_tsc_nsec = 0;
7503 kvm->arch.last_tsc_write = 0;
7504 }
7505
7506 }
7507 return 0;
e9b11c17
ZX		 7508}
7509
13a34e06 7510void kvm_arch_hardware_disable(void)
e9b11c17 7511{
13a34e06
RK		 7512 kvm_x86_ops->hardware_disable();
7513 drop_user_return_notifiers();
e9b11c17
ZX		 7514}
7515
7516int kvm_arch_hardware_setup(void)
7517{
9e9c3fe4
NA		 7518 int r;
7519
7520 r = kvm_x86_ops->hardware_setup();
7521 if (r != 0)
7522 return r;
7523
35181e86
HZ		 7524 if (kvm_has_tsc_control) {
7525 /*
7526 * Make sure the user can only configure tsc_khz values that
7527 * fit into a signed integer.
7528 * A min value is not calculated needed because it will always
7529 * be 1 on all machines.
7530 */
7531 u64 max = min(0x7fffffffULL,
7532 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7533 kvm_max_guest_tsc_khz = max;
7534
ad721883 7535 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7536 }
ad721883 7537
9e9c3fe4
NA		 7538 kvm_init_msr_list();
7539 return 0;
e9b11c17
ZX		 7540}
7541
7542void kvm_arch_hardware_unsetup(void)
7543{
7544 kvm_x86_ops->hardware_unsetup();
7545}
7546
7547void kvm_arch_check_processor_compat(void *rtn)
7548{
7549 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7550}
7551
7552bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7553{
7554 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7555}
7556EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7557
7558bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7559{
7560 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7561}
7562
3e515705
AK		 7563bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7564{
35754c98 7565 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7566}
7567
54e9818f
GN		 7568struct static_key kvm_no_apic_vcpu __read_mostly;
7569
e9b11c17
ZX		 7570int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7571{
7572 struct page *page;
7573 struct kvm *kvm;
7574 int r;
7575
7576 BUG_ON(vcpu->kvm == NULL);
7577 kvm = vcpu->kvm;
7578
d62caabb 7579 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7580 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7581 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7582 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7583 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7584 else
a4535290 7585 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7586
7587 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7588 if (!page) {
7589 r = -ENOMEM;
7590 goto fail;
7591 }
ad312c7c 7592 vcpu->arch.pio_data = page_address(page);
e9b11c17 7593
cc578287 7594 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7595
e9b11c17
ZX		 7596 r = kvm_mmu_create(vcpu);
7597 if (r < 0)
7598 goto fail_free_pio_data;
7599
7600 if (irqchip_in_kernel(kvm)) {
7601 r = kvm_create_lapic(vcpu);
7602 if (r < 0)
7603 goto fail_mmu_destroy;
54e9818f
GN		 7604 } else
7605 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7606
890ca9ae
HY		 7607 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7608 GFP_KERNEL);
7609 if (!vcpu->arch.mce_banks) {
7610 r = -ENOMEM;
443c39bc 7611 goto fail_free_lapic;
890ca9ae
HY		 7612 }
7613 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7614
f1797359
WY		 7615 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7616 r = -ENOMEM;
f5f48ee1 7617 goto fail_free_mce_banks;
f1797359 7618 }
f5f48ee1 7619
0ee6a517 7620 fx_init(vcpu);
66f7b72e 7621
ba904635 7622 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7623 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7624
7625 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7626 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7627
5a4f55cd
EK		 7628 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7629
74545705
RK		 7630 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7631
af585b92 7632 kvm_async_pf_hash_reset(vcpu);
f5132b01 7633 kvm_pmu_init(vcpu);
af585b92 7634
1c1a9ce9
SR		 7635 vcpu->arch.pending_external_vector = -1;
7636
5c919412
AS		 7637 kvm_hv_vcpu_init(vcpu);
7638
e9b11c17 7639 return 0;
0ee6a517 7640
f5f48ee1
SY		 7641fail_free_mce_banks:
7642 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7643fail_free_lapic:
7644 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7645fail_mmu_destroy:
7646 kvm_mmu_destroy(vcpu);
7647fail_free_pio_data:
ad312c7c 7648 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7649fail:
7650 return r;
7651}
7652
7653void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7654{
f656ce01
MT		 7655 int idx;
7656
1f4b34f8 7657 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7658 kvm_pmu_destroy(vcpu);
36cb93fd 7659 kfree(vcpu->arch.mce_banks);
e9b11c17 7660 kvm_free_lapic(vcpu);
f656ce01 7661 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7662 kvm_mmu_destroy(vcpu);
f656ce01 7663 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7664 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7665 if (!lapic_in_kernel(vcpu))
54e9818f 7666 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7667}
d19a9cd2 7668
e790d9ef
RK		 7669void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7670{
ae97a3b8 7671 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7672}
7673
e08b9637 7674int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7675{
e08b9637
CO		 7676 if (type)
7677 return -EINVAL;
7678
6ef768fa 7679 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7680 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7681 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7682 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7683 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7684
5550af4d
SY		 7685 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7686 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7687 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7688 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7689 &kvm->arch.irq_sources_bitmap);
5550af4d 7690
038f8c11 7691 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7692 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7693 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7694
7695 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7696
7e44e449 7697 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7698 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7699
d89f5eff 7700 return 0;
d19a9cd2
ZX		 7701}
7702
7703static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7704{
9fc77441
MT		 7705 int r;
7706 r = vcpu_load(vcpu);
7707 BUG_ON(r);
d19a9cd2
ZX		 7708 kvm_mmu_unload(vcpu);
7709 vcpu_put(vcpu);
7710}
7711
7712static void kvm_free_vcpus(struct kvm *kvm)
7713{
7714 unsigned int i;
988a2cae 7715 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7716
7717 /*
7718 * Unpin any mmu pages first.
7719 */
af585b92
GN		 7720 kvm_for_each_vcpu(i, vcpu, kvm) {
7721 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7722 kvm_unload_vcpu_mmu(vcpu);
af585b92 7723 }
988a2cae
GN		 7724 kvm_for_each_vcpu(i, vcpu, kvm)
7725 kvm_arch_vcpu_free(vcpu);
7726
7727 mutex_lock(&kvm->lock);
7728 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7729 kvm->vcpus[i] = NULL;
d19a9cd2 7730
988a2cae
GN		 7731 atomic_set(&kvm->online_vcpus, 0);
7732 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7733}
7734
ad8ba2cd
SY		 7735void kvm_arch_sync_events(struct kvm *kvm)
7736{
332967a3 7737 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7738 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7739 kvm_free_all_assigned_devices(kvm);
aea924f6 7740 kvm_free_pit(kvm);
ad8ba2cd
SY		 7741}
7742
1d8007bd 7743int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7744{
7745 int i, r;
25188b99 7746 unsigned long hva;
f0d648bd
PB		 7747 struct kvm_memslots *slots = kvm_memslots(kvm);
7748 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7749
7750 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7751 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7752 return -EINVAL;
9da0e4d5 7753
f0d648bd
PB		 7754 slot = id_to_memslot(slots, id);
7755 if (size) {
7756 if (WARN_ON(slot->npages))
7757 return -EEXIST;
7758
7759 /*
7760 * MAP_SHARED to prevent internal slot pages from being moved
7761 * by fork()/COW.
7762 */
7763 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7764 MAP_SHARED | MAP_ANONYMOUS, 0);
7765 if (IS_ERR((void *)hva))
7766 return PTR_ERR((void *)hva);
7767 } else {
7768 if (!slot->npages)
7769 return 0;
7770
7771 hva = 0;
7772 }
7773
7774 old = *slot;
9da0e4d5 7775 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7776 struct kvm_userspace_memory_region m;
9da0e4d5 7777
1d8007bd
PB		 7778 m.slot = id | (i << 16);
7779 m.flags = 0;
7780 m.guest_phys_addr = gpa;
f0d648bd 7781 m.userspace_addr = hva;
1d8007bd 7782 m.memory_size = size;
9da0e4d5
PB		 7783 r = __kvm_set_memory_region(kvm, &m);
7784 if (r < 0)
7785 return r;
7786 }
7787
f0d648bd
PB		 7788 if (!size) {
7789 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7790 WARN_ON(r < 0);
7791 }
7792
9da0e4d5
PB		 7793 return 0;
7794}
7795EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7796
1d8007bd 7797int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7798{
7799 int r;
7800
7801 mutex_lock(&kvm->slots_lock);
1d8007bd 7802 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7803 mutex_unlock(&kvm->slots_lock);
7804
7805 return r;
7806}
7807EXPORT_SYMBOL_GPL(x86_set_memory_region);
7808
d19a9cd2
ZX		 7809void kvm_arch_destroy_vm(struct kvm *kvm)
7810{
27469d29
AH		 7811 if (current->mm == kvm->mm) {
7812 /*
7813 * Free memory regions allocated on behalf of userspace,
7814 * unless the the memory map has changed due to process exit
7815 * or fd copying.
7816 */
1d8007bd
PB		 7817 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7818 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7819 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7820 }
6eb55818 7821 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7822 kfree(kvm->arch.vpic);
7823 kfree(kvm->arch.vioapic);
d19a9cd2 7824 kvm_free_vcpus(kvm);
1e08ec4a 7825 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7826}
0de10343 7827
5587027c 7828void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7829 struct kvm_memory_slot *dont)
7830{
7831 int i;
7832
d89cc617
TY		 7833 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7834 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7835 kvfree(free->arch.rmap[i]);
d89cc617 7836 free->arch.rmap[i] = NULL;
77d11309 7837 }
d89cc617
TY		 7838 if (i == 0)
7839 continue;
7840
7841 if (!dont || free->arch.lpage_info[i - 1] !=
7842 dont->arch.lpage_info[i - 1]) {
548ef284 7843 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7844 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7845 }
7846 }
7847}
7848
5587027c
AK		 7849int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7850 unsigned long npages)
db3fe4eb
TY		 7851{
7852 int i;
7853
d89cc617 7854 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7855 unsigned long ugfn;
7856 int lpages;
d89cc617 7857 int level = i + 1;
db3fe4eb
TY		 7858
7859 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7860 slot->base_gfn, level) + 1;
7861
d89cc617
TY		 7862 slot->arch.rmap[i] =
7863 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7864 if (!slot->arch.rmap[i])
77d11309 7865 goto out_free;
d89cc617
TY		 7866 if (i == 0)
7867 continue;
77d11309 7868
d89cc617
TY		 7869 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7870 sizeof(*slot->arch.lpage_info[i - 1]));
7871 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7872 goto out_free;
7873
7874 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7875 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7876 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7877 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7878 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7879 /*
7880 * If the gfn and userspace address are not aligned wrt each
7881 * other, or if explicitly asked to, disable large page
7882 * support for this slot
7883 */
7884 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7885 !kvm_largepages_enabled()) {
7886 unsigned long j;
7887
7888 for (j = 0; j < lpages; ++j)
d89cc617 7889 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7890 }
7891 }
7892
7893 return 0;
7894
7895out_free:
d89cc617 7896 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7897 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7898 slot->arch.rmap[i] = NULL;
7899 if (i == 0)
7900 continue;
7901
548ef284 7902 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7903 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7904 }
7905 return -ENOMEM;
7906}
7907
15f46015 7908void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7909{
e6dff7d1
TY		 7910 /*
7911 * memslots->generation has been incremented.
7912 * mmio generation may have reached its maximum value.
7913 */
54bf36aa 7914 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7915}
7916
f7784b8e
MT		 7917int kvm_arch_prepare_memory_region(struct kvm *kvm,
7918 struct kvm_memory_slot *memslot,
09170a49 7919 const struct kvm_userspace_memory_region *mem,
7b6195a9 7920 enum kvm_mr_change change)
0de10343 7921{
f7784b8e
MT		 7922 return 0;
7923}
7924
88178fd4
KH		 7925static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7926 struct kvm_memory_slot *new)
7927{
7928 /* Still write protect RO slot */
7929 if (new->flags & KVM_MEM_READONLY) {
7930 kvm_mmu_slot_remove_write_access(kvm, new);
7931 return;
7932 }
7933
7934 /*
7935 * Call kvm_x86_ops dirty logging hooks when they are valid.
7936 *
7937 * kvm_x86_ops->slot_disable_log_dirty is called when:
7938 *
7939 * - KVM_MR_CREATE with dirty logging is disabled
7940 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7941 *
7942 * The reason is, in case of PML, we need to set D-bit for any slots
7943 * with dirty logging disabled in order to eliminate unnecessary GPA
7944 * logging in PML buffer (and potential PML buffer full VMEXT). This
7945 * guarantees leaving PML enabled during guest's lifetime won't have
7946 * any additonal overhead from PML when guest is running with dirty
7947 * logging disabled for memory slots.
7948 *
7949 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7950 * to dirty logging mode.
7951 *
7952 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7953 *
7954 * In case of write protect:
7955 *
7956 * Write protect all pages for dirty logging.
7957 *
7958 * All the sptes including the large sptes which point to this
7959 * slot are set to readonly. We can not create any new large
7960 * spte on this slot until the end of the logging.
7961 *
7962 * See the comments in fast_page_fault().
7963 */
7964 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7965 if (kvm_x86_ops->slot_enable_log_dirty)
7966 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7967 else
7968 kvm_mmu_slot_remove_write_access(kvm, new);
7969 } else {
7970 if (kvm_x86_ops->slot_disable_log_dirty)
7971 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7972 }
7973}
7974
f7784b8e 7975void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7976 const struct kvm_userspace_memory_region *mem,
8482644a 7977 const struct kvm_memory_slot *old,
f36f3f28 7978 const struct kvm_memory_slot *new,
8482644a 7979 enum kvm_mr_change change)
f7784b8e 7980{
8482644a 7981 int nr_mmu_pages = 0;
f7784b8e 7982
48c0e4e9
XG		 7983 if (!kvm->arch.n_requested_mmu_pages)
7984 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7985
48c0e4e9 7986 if (nr_mmu_pages)
0de10343 7987 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7988
3ea3b7fa
WL		 7989 /*
7990 * Dirty logging tracks sptes in 4k granularity, meaning that large
7991 * sptes have to be split. If live migration is successful, the guest
7992 * in the source machine will be destroyed and large sptes will be
7993 * created in the destination. However, if the guest continues to run
7994 * in the source machine (for example if live migration fails), small
7995 * sptes will remain around and cause bad performance.
7996 *
7997 * Scan sptes if dirty logging has been stopped, dropping those
7998 * which can be collapsed into a single large-page spte. Later
7999 * page faults will create the large-page sptes.
8000 */
8001 if ((change != KVM_MR_DELETE) &&
8002 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8003 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8004 kvm_mmu_zap_collapsible_sptes(kvm, new);
8005
c972f3b1 8006 /*
88178fd4 8007 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8008 *
88178fd4
KH		 8009 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8010 * been zapped so no dirty logging staff is needed for old slot. For
8011 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8012 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8013 *
8014 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8015 */
88178fd4 8016 if (change != KVM_MR_DELETE)
f36f3f28 8017 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8018}
1d737c8a 8019
2df72e9b 8020void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8021{
6ca18b69 8022 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8023}
8024
2df72e9b
MT		 8025void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8026 struct kvm_memory_slot *slot)
8027{
6ca18b69 8028 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8029}
8030
5d9bc648
PB		 8031static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8032{
8033 if (!list_empty_careful(&vcpu->async_pf.done))
8034 return true;
8035
8036 if (kvm_apic_has_events(vcpu))
8037 return true;
8038
8039 if (vcpu->arch.pv.pv_unhalted)
8040 return true;
8041
8042 if (atomic_read(&vcpu->arch.nmi_queued))
8043 return true;
8044
73917739
PB		 8045 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8046 return true;
8047
5d9bc648
PB		 8048 if (kvm_arch_interrupt_allowed(vcpu) &&
8049 kvm_cpu_has_interrupt(vcpu))
8050 return true;
8051
1f4b34f8
AS		 8052 if (kvm_hv_has_stimer_pending(vcpu))
8053 return true;
8054
5d9bc648
PB		 8055 return false;
8056}
8057
1d737c8a
ZX		 8058int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8059{
b6b8a145
JK		 8060 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8061 kvm_x86_ops->check_nested_events(vcpu, false);
8062
5d9bc648 8063 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8064}
5736199a 8065
b6d33834 8066int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8067{
b6d33834 8068 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8069}
78646121
GN		 8070
8071int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8072{
8073 return kvm_x86_ops->interrupt_allowed(vcpu);
8074}
229456fc 8075
82b32774 8076unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8077{
82b32774
NA		 8078 if (is_64_bit_mode(vcpu))
8079 return kvm_rip_read(vcpu);
8080 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8081 kvm_rip_read(vcpu));
8082}
8083EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8084
82b32774
NA		 8085bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8086{
8087 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8088}
8089EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8090
94fe45da
JK		 8091unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8092{
8093 unsigned long rflags;
8094
8095 rflags = kvm_x86_ops->get_rflags(vcpu);
8096 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8097 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8098 return rflags;
8099}
8100EXPORT_SYMBOL_GPL(kvm_get_rflags);
8101
6addfc42 8102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8103{
8104 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8105 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8106 rflags |= X86_EFLAGS_TF;
94fe45da 8107 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8108}
8109
8110void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8111{
8112 __kvm_set_rflags(vcpu, rflags);
3842d135 8113 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8114}
8115EXPORT_SYMBOL_GPL(kvm_set_rflags);
8116
56028d08
GN		 8117void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8118{
8119 int r;
8120
fb67e14f 8121 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8122 work->wakeup_all)
56028d08
GN		 8123 return;
8124
8125 r = kvm_mmu_reload(vcpu);
8126 if (unlikely(r))
8127 return;
8128
fb67e14f
XG		 8129 if (!vcpu->arch.mmu.direct_map &&
8130 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8131 return;
8132
56028d08
GN		 8133 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8134}
8135
af585b92
GN		 8136static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8137{
8138 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8139}
8140
8141static inline u32 kvm_async_pf_next_probe(u32 key)
8142{
8143 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8144}
8145
8146static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8147{
8148 u32 key = kvm_async_pf_hash_fn(gfn);
8149
8150 while (vcpu->arch.apf.gfns[key] != ~0)
8151 key = kvm_async_pf_next_probe(key);
8152
8153 vcpu->arch.apf.gfns[key] = gfn;
8154}
8155
8156static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8157{
8158 int i;
8159 u32 key = kvm_async_pf_hash_fn(gfn);
8160
8161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8162 (vcpu->arch.apf.gfns[key] != gfn &&
8163 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8164 key = kvm_async_pf_next_probe(key);
8165
8166 return key;
8167}
8168
8169bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8170{
8171 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8172}
8173
8174static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8175{
8176 u32 i, j, k;
8177
8178 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8179 while (true) {
8180 vcpu->arch.apf.gfns[i] = ~0;
8181 do {
8182 j = kvm_async_pf_next_probe(j);
8183 if (vcpu->arch.apf.gfns[j] == ~0)
8184 return;
8185 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8186 /*
8187 * k lies cyclically in ]i,j]
8188 * | i.k.j |
8189 * |....j i.k.| or |.k..j i...|
8190 */
8191 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8192 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8193 i = j;
8194 }
8195}
8196
7c90705b
GN		 8197static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8198{
8199
8200 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8201 sizeof(val));
8202}
8203
af585b92
GN		 8204void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8205 struct kvm_async_pf *work)
8206{
6389ee94
AK		 8207 struct x86_exception fault;
8208
7c90705b 8209 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8210 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8211
8212 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8213 (vcpu->arch.apf.send_user_only &&
8214 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8215 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8216 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8217 fault.vector = PF_VECTOR;
8218 fault.error_code_valid = true;
8219 fault.error_code = 0;
8220 fault.nested_page_fault = false;
8221 fault.address = work->arch.token;
8222 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8223 }
af585b92
GN		 8224}
8225
8226void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8227 struct kvm_async_pf *work)
8228{
6389ee94
AK		 8229 struct x86_exception fault;
8230
7c90705b 8231 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8232 if (work->wakeup_all)
7c90705b
GN		 8233 work->arch.token = ~0; /* broadcast wakeup */
8234 else
8235 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8236
8237 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8238 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8239 fault.vector = PF_VECTOR;
8240 fault.error_code_valid = true;
8241 fault.error_code = 0;
8242 fault.nested_page_fault = false;
8243 fault.address = work->arch.token;
8244 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8245 }
e6d53e3b 8246 vcpu->arch.apf.halted = false;
a4fa1635 8247 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8248}
8249
8250bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8251{
8252 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8253 return true;
8254 else
8255 return !kvm_event_needs_reinjection(vcpu) &&
8256 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8257}
8258
5544eb9b
PB		 8259void kvm_arch_start_assignment(struct kvm *kvm)
8260{
8261 atomic_inc(&kvm->arch.assigned_device_count);
8262}
8263EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8264
8265void kvm_arch_end_assignment(struct kvm *kvm)
8266{
8267 atomic_dec(&kvm->arch.assigned_device_count);
8268}
8269EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8270
8271bool kvm_arch_has_assigned_device(struct kvm *kvm)
8272{
8273 return atomic_read(&kvm->arch.assigned_device_count);
8274}
8275EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8276
e0f0bbc5
AW		 8277void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8278{
8279 atomic_inc(&kvm->arch.noncoherent_dma_count);
8280}
8281EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8282
8283void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8284{
8285 atomic_dec(&kvm->arch.noncoherent_dma_count);
8286}
8287EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8288
8289bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8290{
8291 return atomic_read(&kvm->arch.noncoherent_dma_count);
8292}
8293EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8294
87276880
FW		 8295int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8296 struct irq_bypass_producer *prod)
8297{
8298 struct kvm_kernel_irqfd *irqfd =
8299 container_of(cons, struct kvm_kernel_irqfd, consumer);
8300
8301 if (kvm_x86_ops->update_pi_irte) {
8302 irqfd->producer = prod;
8303 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8304 prod->irq, irqfd->gsi, 1);
8305 }
8306
8307 return -EINVAL;
8308}
8309
8310void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8311 struct irq_bypass_producer *prod)
8312{
8313 int ret;
8314 struct kvm_kernel_irqfd *irqfd =
8315 container_of(cons, struct kvm_kernel_irqfd, consumer);
8316
8317 if (!kvm_x86_ops->update_pi_irte) {
8318 WARN_ON(irqfd->producer != NULL);
8319 return;
8320 }
8321
8322 WARN_ON(irqfd->producer != prod);
8323 irqfd->producer = NULL;
8324
8325 /*
8326 * When producer of consumer is unregistered, we change back to
8327 * remapped mode, so we can re-use the current implementation
8328 * when the irq is masked/disabed or the consumer side (KVM
8329 * int this case doesn't want to receive the interrupts.
8330 */
8331 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8332 if (ret)
8333 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8334 " fails: %d\n", irqfd->consumer.token, ret);
8335}
8336
8337int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8338 uint32_t guest_irq, bool set)
8339{
8340 if (!kvm_x86_ops->update_pi_irte)
8341 return -EINVAL;
8342
8343 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8344}
8345
229456fc 8346EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8347EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8348EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8349EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8350EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8351EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8352EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8353EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8354EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8355EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8356EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8357EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8358EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8359EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8360EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8361EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8362EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux kernel - Deliverables
This page took 2.626358 seconds and 5 git commands to generate.